diff --git a/Makefile b/Makefile index 7b526f4f5a8..03ba8733592 100644 --- a/Makefile +++ b/Makefile @@ -783,6 +783,7 @@ libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/ libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/ libs-y += drivers/serial/ libs-y += drivers/usb/cdns3/ +libs-y += drivers/usb/imx/ libs-y += drivers/usb/dwc3/ libs-y += drivers/usb/common/ libs-y += drivers/usb/emul/ @@ -1409,6 +1410,9 @@ else SPL_PAYLOAD := u-boot.bin endif +export ATF_LOAD_ADDR=$(CONFIG_ATF_LOAD_ADDR) +export TEE_LOAD_ADDR=$(CONFIG_TEE_LOAD_ADDR) + SPL_IMAGE := $(CONFIG_SPL_IMAGE:"%"=%) OBJCOPYFLAGS_u-boot-with-spl.bin = -I binary -O binary \ @@ -1469,6 +1473,13 @@ tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE SPL: spl/u-boot-spl.bin FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ +firmware: + $(Q)$(MAKE) $(build)=board/compulab/plat/imx8mp/firmware all + +rm_firmware: + $(Q)$(MAKE) $(build)=board/compulab/plat/imx8mp/firmware clean + + ifeq ($(CONFIG_ARCH_IMX8M)$(CONFIG_ARCH_IMX8), y) ifeq ($(CONFIG_SPL_LOAD_IMX_CONTAINER), y) u-boot.cnt: u-boot.bin FORCE @@ -1477,7 +1488,7 @@ u-boot.cnt: u-boot.bin FORCE flash.bin: spl/u-boot-spl.bin u-boot.cnt FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ else -flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE +flash.bin: spl/u-boot-spl.bin u-boot.itb firmware FORCE $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@ endif endif diff --git a/README.md b/README.md new file mode 100644 index 00000000000..79911eae61a --- /dev/null +++ b/README.md @@ -0,0 +1,52 @@ +# Disclaimer + +| !IMPORTANT! | This is a development branch, that is not relelased by CompuLab yet| +|---|---| + +# Configuring the build + +## Prerequisites +It is up to developers to prepare the host machine; it requires: + +* [Setup Cross Compiler](https://github.com/compulab-yokneam/meta-bsp-imx8mp/blob/kirkstone/Documentation/toolchain.md#linaro-toolchain-how-to) +* Install these packages: ``shareutils, swing`` + + +## Setup U-Boot environment + +* WorkDir: +``` +mkdir -p compulab-bootloader/build && cd compulab-bootloader +export BUILD=$(pwd)/build +``` + +* Set a CompuLab machine: + +| Machine | Command Line | +|---|---| +|ucm-imx8m-plus|```export MACHINE=ucm-imx8m-plus```| +|som-imx8m-plus|```export MACHINE=som-imx8m-plus```| +|iot-gate-imx8plus|```export MACHINE=iot-gate-imx8plus```| + +* Clone the source code: +``` +git clone --branch u-boot-compulab_v2021.04 https://github.com/compulab-yokneam/u-boot-compulab.git +cd u-boot-compulab +``` + +## Create U-boot binary + +* Apply the machine Config +``` +make O=${BUILD} ${MACHINE}_defconfig +``` + +* Build +``` +nice make -j`nproc` O=${BUILD} flash.bin +``` + +* Result +``` +ls -al ${BUILD}/flash.bin +``` diff --git a/arch/Kconfig b/arch/Kconfig index 27843cd79c4..f114a025fa5 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -120,6 +120,7 @@ config SANDBOX select SPI select SUPPORT_OF_CONTROL select SYSRESET_CMD_POWEROFF + select IRQ imply BITREVERSE select BLOBLIST imply CMD_DM @@ -160,6 +161,8 @@ config SANDBOX imply CMD_CLONE imply SILENT_CONSOLE imply BOOTARGS_SUBST + imply PHY_FIXED + imply DM_DSA config SH bool "SuperH architecture" @@ -181,6 +184,7 @@ config X86 select TIMER select USE_PRIVATE_LIBGCC select X86_TSC_TIMER + select IRQ imply HAS_ROM if X86_RESET_VECTOR imply BLK imply CMD_DM @@ -211,7 +215,6 @@ config X86 imply USB_HOST_ETHER imply PCH imply RTC_MC146818 - imply IRQ imply ACPIGEN if !QEMU imply SYSINFO if GENERATE_SMBIOS_TABLE imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3307f2b3fc5..6db6561824c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -67,6 +67,7 @@ config GIC_V3_ITS bool "ARM GICV3 ITS" select REGMAP select SYSCON + select IRQ help ARM GICV3 Interrupt translation service (ITS). Basic support for programming locality specific peripheral @@ -832,6 +833,9 @@ config ARCH_LPC32XX config ARCH_IMX8 bool "NXP i.MX8 platform" select ARM64 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select DM select OF_CONTROL select ENABLE_ARM_SOC_BOOT0_HOOK @@ -839,6 +843,9 @@ config ARCH_IMX8 config ARCH_IMX8M bool "NXP i.MX8M platform" select ARM64 + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select DM select SUPPORT_SPL imply CMD_DM @@ -875,6 +882,9 @@ config ARCH_MX31 config ARCH_MX7ULP bool "NXP MX7ULP" select CPU_V7A + select SYS_FSL_HAS_SEC + select SYS_FSL_SEC_COMPAT_4 + select SYS_FSL_SEC_LE select ROM_UNIFIED_SECTIONS imply MXC_GPIO imply SYS_THUMB_BUILD @@ -883,7 +893,7 @@ config ARCH_MX7 bool "Freescale MX7" select ARCH_MISC_INIT select CPU_V7A - select SYS_FSL_HAS_SEC if IMX_HAB + select SYS_FSL_HAS_SEC select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_LE imply BOARD_EARLY_INIT_F diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 28b523b37c7..bd02c214da7 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -28,6 +28,10 @@ else arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) endif +ifneq ($(CONFIG_ARCH_IMX8)$(CONFIG_ARCH_IMX8M),) +arch-y += -mgeneral-regs-only +endif + # Evaluate arch cc-option calls now arch-y := $(arch-y) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 4153f7e3713..d3c8c6ae780 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -151,6 +151,10 @@ ifdef CONFIG_EFI_LOADER OBJCOPYFLAGS += -j .efi_runtime -j .efi_runtime_rel endif +ifdef CONFIG_IMX_M4_BIND +OBJCOPYFLAGS += -j .firmware_image +endif + ifneq ($(CONFIG_IMX_CONFIG),) ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c index 4e1cf3a1e32..6a77de64db9 100644 --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@ -7,6 +7,8 @@ * * Based on code from LTIB: * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. + * */ #include diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 747059b56a5..f23c33cbc3e 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -20,6 +20,10 @@ config ARCH_LS1021A select SYS_FSL_SEC_LE select SYS_FSL_SRDS_1 select SYS_HAS_SERDES + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT imply CMD_PCI imply SCSI imply SCSI_AHCI diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index f26a5b22fdf..06c0fac82d5 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -20,7 +20,8 @@ #include #include #include - +#include +#include #include "fsl_epu.h" #define DCSR_RCPM2_BLOCK_OFFSET 0x223000 @@ -397,3 +398,18 @@ void arch_preboot_os(void) ctrl &= ~ARCH_TIMER_CTRL_ENABLE; asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl)); } + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + return 0; +} +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index ae0b7b21e81..3e92df25c51 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -18,6 +18,10 @@ config ARCH_LS1012A select SYS_I2C_MXC select SYS_I2C_MXC_I2C1 if !DM_I2C select SYS_I2C_MXC_I2C2 if !DM_I2C + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT imply PANIC_HANG config ARCH_LS1028A @@ -47,7 +51,12 @@ config ARCH_LS1028A select SYS_FSL_ERRATUM_A009663 if !TFABOOT select SYS_FSL_ERRATUM_A009942 if !TFABOOT select SYS_FSL_ERRATUM_A050382 + select SYS_FSL_ERRATUM_A011334 + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select RESV_RAM if GIC_V3_ITS + select FSL_CAAM + select FSL_BLOB + select MISC imply PANIC_HANG config ARCH_LS1043A @@ -80,6 +89,10 @@ config ARCH_LS1043A select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C select SYS_I2C_MXC_I2C4 if !DM_I2C + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT imply CMD_PCI config ARCH_LS1046A @@ -113,6 +126,10 @@ config ARCH_LS1046A select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C select SYS_I2C_MXC_I2C4 if !DM_I2C + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT imply SCSI imply SCSI_AHCI @@ -154,6 +171,9 @@ config ARCH_LS1088A select SYS_I2C_MXC_I2C3 if !TFABOOT select SYS_I2C_MXC_I2C4 if !TFABOOT select RESV_RAM if GIC_V3_ITS + select FSL_CAAM + select FSL_BLOB + select MISC imply SCSI imply PANIC_HANG @@ -205,6 +225,9 @@ config ARCH_LS2080A select SYS_I2C_MXC_I2C3 if !TFABOOT select SYS_I2C_MXC_I2C4 if !TFABOOT select RESV_RAM if GIC_V3_ITS + select FSL_CAAM + select FSL_BLOB + select MISC imply DISTRO_DEFAULTS imply PANIC_HANG @@ -221,7 +244,9 @@ config ARCH_LX2162A select SYS_FSL_DDR_VER_50 select SYS_FSL_EC1 select SYS_FSL_EC2 - select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_ERRATUM_A050204 + select SYS_FSL_ERRATUM_A011334 + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_HAS_CCN508 @@ -232,6 +257,9 @@ config ARCH_LX2162A select BOARD_EARLY_INIT_F select SYS_I2C_MXC select RESV_RAM if GIC_V3_ITS + select FSL_CAAM + select FSL_BLOB + select MISC imply DISTRO_DEFAULTS imply PANIC_HANG imply SCSI @@ -251,7 +279,9 @@ config ARCH_LX2160A select SYS_FSL_DDR_VER_50 select SYS_FSL_EC1 select SYS_FSL_EC2 - select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_ERRATUM_A050204 + select SYS_FSL_ERRATUM_A011334 + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_HAS_CCN508 @@ -262,6 +292,9 @@ config ARCH_LX2160A select BOARD_EARLY_INIT_F select SYS_I2C_MXC select RESV_RAM if GIC_V3_ITS + select FSL_CAAM + select FSL_BLOB + select MISC imply DISTRO_DEFAULTS imply PANIC_HANG imply SCSI @@ -369,8 +402,8 @@ config SYS_FSL_ERRATUM_A009008 config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798" -config SYS_FSL_ERRATUM_A050106 - bool "Workaround for USB PHY erratum A050106" +config SYS_FSL_ERRATUM_A050204 + bool "Workaround for USB PHY erratum A050204" help USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 3a5bf778260..24a2b7591ef 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -48,6 +48,8 @@ #endif #endif #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -1649,6 +1651,14 @@ __weak int serdes_misc_init(void) int arch_misc_init(void) { + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + serdes_misc_init(); return 0; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 7f29aa4725a..f1624ff30ae 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #include @@ -478,6 +478,151 @@ static bool crypto_is_disabled(unsigned int svr) return false; } +#ifdef CONFIG_FSL_PFE +void pfe_set_firmware_in_fdt(void *blob, int pfenode, void *pfw, char *pename, + unsigned int len) +{ + int rc, fwnode; + unsigned int phandle; + char subnode_str[32], prop_str[32], phandle_str[32], s[64]; + + sprintf(subnode_str, "pfe-%s-firmware", pename); + sprintf(prop_str, "fsl,pfe-%s-firmware", pename); + sprintf(phandle_str, "fsl,%s-firmware", pename); + + /*Add PE FW to fdt.*/ + /* Increase the size of the fdt to make room for the node. */ + rc = fdt_increase_size(blob, len); + if (rc < 0) { + printf("Unable to make room for %s firmware: %s\n", pename, + fdt_strerror(rc)); + return; + } + + /* Create the firmware node. */ + fwnode = fdt_add_subnode(blob, pfenode, subnode_str); + if (fwnode < 0) { + fdt_get_path(blob, pfenode, s, sizeof(s)); + printf("Could not add firmware node to %s: %s\n", s, + fdt_strerror(fwnode)); + return; + } + + rc = fdt_setprop_string(blob, fwnode, "compatible", prop_str); + if (rc < 0) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + rc = fdt_setprop_u32(blob, fwnode, "length", len); + if (rc < 0) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + /*create phandle and set the property*/ + phandle = fdt_create_phandle(blob, fwnode); + if (!phandle) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add phandle property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + rc = fdt_setprop(blob, fwnode, phandle_str, pfw, len); + if (rc < 0) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add firmware property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } +} + +void fdt_fixup_pfe_firmware(void *blob) +{ + int pfenode; + unsigned int len_class = 0, len_tmu = 0, len_util = 0; + const char *p; + void *pclassfw, *ptmufw, *putilfw; + + /* The first PFE we find, will contain the actual firmware. */ + pfenode = fdt_node_offset_by_compatible(blob, -1, "fsl,pfe"); + if (pfenode < 0) + /* Exit silently if there are no PFE devices */ + return; + + /* If we already have a firmware node, then also exit silently. */ + if (fdt_node_offset_by_compatible(blob, -1, + "fsl,pfe-class-firmware") > 0) + return; + + /* If the environment variable is not set, then exit silently */ + p = env_get("class_elf_firmware"); + if (!p) + return; + + pclassfw = (void *)simple_strtoul(p, NULL, 16); + if (!pclassfw) + return; + + p = env_get("class_elf_size"); + if (!p) + return; + len_class = simple_strtoul(p, NULL, 16); + + /* If the environment variable is not set, then exit silently */ + p = env_get("tmu_elf_firmware"); + if (!p) + return; + + ptmufw = (void *)simple_strtoul(p, NULL, 16); + if (!ptmufw) + return; + + p = env_get("tmu_elf_size"); + if (!p) + return; + len_tmu = simple_strtoul(p, NULL, 16); + + if (len_class == 0 || len_tmu == 0) { + printf("PFE FW corrupted. CLASS FW size %d, TMU FW size %d\n", + len_class, len_tmu); + return; + } + + /*Add CLASS FW to fdt.*/ + pfe_set_firmware_in_fdt(blob, pfenode, pclassfw, "class", len_class); + + /*Add TMU FW to fdt.*/ + pfe_set_firmware_in_fdt(blob, pfenode, ptmufw, "tmu", len_tmu); + + /* Util PE firmware is handled separately as it is not a usual case*/ + p = env_get("util_elf_firmware"); + if (!p) + return; + + putilfw = (void *)simple_strtoul(p, NULL, 16); + if (!putilfw) + return; + + p = env_get("util_elf_size"); + if (!p) + return; + len_util = simple_strtoul(p, NULL, 16); + + if (len_util) { + printf("PFE Util PE firmware is not added to FDT.\n"); + return; + } + + pfe_set_firmware_in_fdt(blob, pfenode, putilfw, "util", len_util); +} +#endif + void ft_cpu_setup(void *blob, struct bd_info *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -534,6 +679,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif +#ifdef CONFIG_FSL_PFE + fdt_fixup_pfe_firmware(blob); +#endif #ifndef CONFIG_ARCH_LS1012A fsl_fdt_disable_usb(blob); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7553b5bce2e..c3cd6c7ac7f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #include @@ -218,7 +218,7 @@ static void erratum_a009007(void) } #if defined(CONFIG_FSL_LSCH3) -static void erratum_a050106(void) +static void erratum_a050204(void) { #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; @@ -378,7 +378,7 @@ void fsl_lsch3_early_init_f(void) erratum_a009798(); erratum_a008997(); erratum_a009007(); - erratum_a050106(); + erratum_a050204(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/arch/arm/cpu/armv8/xen/Makefile b/arch/arm/cpu/armv8/xen/Makefile index e3b4ae2bd40..fc27329f49b 100644 --- a/arch/arm/cpu/armv8/xen/Makefile +++ b/arch/arm/cpu/armv8/xen/Makefile @@ -3,4 +3,4 @@ # (C) 2018 NXP # (C) 2020 EPAM Systems Inc. -obj-y += lowlevel_init.o hypercall.o +obj-y += lowlevel_init.o hypercall.o print.o diff --git a/arch/arm/cpu/armv8/xen/print.c b/arch/arm/cpu/armv8/xen/print.c new file mode 100644 index 00000000000..5d9e666d0e6 --- /dev/null +++ b/arch/arm/cpu/armv8/xen/print.c @@ -0,0 +1,30 @@ +/* + * Copyright 2018 NXP + * + * Peng Fan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +/* + * To non privileged domain, need CONFIG_VERBOSE_DEBUG in XEN to + * get output. + */ +void xenprintf(const char *buf) +{ + (void)HYPERVISOR_console_io(CONSOLEIO_write, strlen(buf), buf); + return; +} + +void xenprintc(const char c) +{ + (void)HYPERVISOR_console_io(CONSOLEIO_write, 1, &c); + return; +} diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 0eb164d2e69..76f45d2a085 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -177,6 +177,22 @@ SECTIONS *(.__image_copy_end) } +#ifdef CONFIG_IMX_M4_BIND + .firmware_image_start : { + *(.__firmware_image_start) + } + + .firmware_image : { + KEEP(*(.firmware_image)) + } + + .firmware_image_end : { + *(.__firmware_image_end) + } + + . = ALIGN(4); +#endif + .rel_dyn_start : { *(.__rel_dyn_start) diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index c6710826a0a..3eb955cf791 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -686,12 +686,15 @@ dtb-y += \ imx6dl-nitrogen6x.dtb \ imx6dl-pico.dtb \ imx6dl-sabreauto.dtb \ + imx6dl-sabreauto-ecspi.dtb \ + imx6dl-sabreauto-gpmi-weim.dtb \ imx6dl-sabresd.dtb \ + imx6dl-arm2.dtb \ imx6dl-wandboard-revd1.dtb \ endif -ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),) +ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL)$(CONFIG_MX6QP),) dtb-y += \ imx6-apalis.dtb \ imx6q-cm-fx6.dtb \ @@ -719,11 +722,17 @@ dtb-y += \ imx6q-pico.dtb \ imx6q-phytec-mira-rdk-nand.dtb \ imx6q-sabreauto.dtb \ + imx6q-sabreauto-ecspi.dtb \ + imx6q-sabreauto-gpmi-weim.dtb \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ + imx6q-arm2.dtb \ + imx6q-pop-arm2.dtb \ imx6q-tbs2910.dtb \ imx6q-wandboard-revd1.dtb \ imx6qp-sabreauto.dtb \ + imx6qp-sabreauto-ecspi.dtb \ + imx6qp-sabreauto-gpmi-weim.dtb \ imx6qp-sabresd.dtb \ imx6qp-wandboard-revd1.dtb \ @@ -731,11 +740,22 @@ endif dtb-$(CONFIG_MX6SL) += imx6sl-evk.dtb -dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb +dtb-$(CONFIG_MX6SLL) += imx6sll-evk.dtb \ + imx6sll-lpddr2-val.dtb \ + imx6sll-lpddr3-val.dtb \ + imx6sll-lpddr3-val-ecspi.dtb dtb-$(CONFIG_MX6SX) += \ + imx6sx-14x14-val.dtb \ + imx6sx-17x17-val.dtb \ + imx6sx-17x17-val-ecspi.dtb \ + imx6sx-17x17-val-gpmi-weim.dtb \ + imx6sx-19x19-val.dtb \ + imx6sx-19x19-val-ecspi.dtb \ + imx6sx-19x19-val-gpmi-weim.dtb \ imx6sx-sabreauto.dtb \ imx6sx-sdb.dtb \ + imx6sx-sdb-emmc.dtb \ imx6sx-softing-vining-2000.dtb dtb-$(CONFIG_MX6UL) += \ @@ -743,8 +763,13 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-isiot-emmc.dtb \ imx6ul-isiot-nand.dtb \ imx6ul-opos6uldev.dtb \ + imx6ul-14x14-ddr3-val.dtb \ + imx6ul-14x14-ddr3-val-emmc.dtb \ + imx6ul-14x14-ddr3-val-gpmi-weim.dtb \ + imx6ul-14x14-lpddr2-val.dtb \ imx6ul-14x14-evk.dtb \ - imx6ul-9x9-evk.dtb \ + imx6ul-14x14-evk-emmc.dtb \ + imx6ul-14x14-evk-gpmi-weim.dtb \ imx6ul-9x9-evk.dtb \ imx6ul-liteboard.dtb \ imx6ul-phytec-segin-ff-rdk-nand.dtb \ @@ -752,13 +777,23 @@ dtb-$(CONFIG_MX6UL) += \ imx6ul-pico-pi.dtb dtb-$(CONFIG_MX6ULL) += \ + imx6ull-14x14-ddr3-val.dtb \ + imx6ull-14x14-ddr3-val-epdc.dtb \ + imx6ull-14x14-ddr3-val-emmc.dtb \ + imx6ull-14x14-ddr3-val-gpmi-weim.dtb \ + imx6ull-14x14-ddr3-val-tsc.dtb \ imx6ull-14x14-evk.dtb \ + imx6ull-14x14-evk-emmc.dtb \ + imx6ull-14x14-evk-gpmi-weim.dtb \ + imx6ull-9x9-evk.dtb \ imx6ull-colibri.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ - imx6ulz-14x14-evk.dtb + imx6ulz-14x14-evk.dtb \ + imx6ulz-14x14-evk-emmc.dtb \ + imx6ulz-14x14-evk-gpmi-weim.dtb dtb-$(CONFIG_ARCH_MX6) += \ imx6-apalis.dtb \ @@ -766,44 +801,89 @@ dtb-$(CONFIG_ARCH_MX6) += \ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-sdb-qspi.dtb \ + imx7d-sdb-epdc.dtb \ + imx7d-sdb-gpmi-weim.dtb \ + imx7d-sdb-reva.dtb \ imx7-colibri-emmc.dtb \ imx7-colibri-rawnand.dtb \ imx7s-warp.dtb \ imx7d-meerkat96.dtb \ imx7d-pico-pi.dtb \ - imx7d-pico-hobbit.dtb + imx7d-pico-hobbit.dtb \ + imx7d-12x12-lpddr3-val.dtb \ + imx7d-12x12-lpddr3-val-ecspi.dtb \ + imx7d-12x12-lpddr3-val-qspi.dtb \ + imx7d-12x12-ddr3-val.dtb \ + imx7d-19x19-ddr3-val.dtb \ + imx7d-19x19-lpddr2-val.dtb \ + imx7d-19x19-lpddr3-val.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ - imx7ulp-evk.dtb + imx7ulp-10x10-val.dtb \ + imx7ulp-14x14-val.dtb \ + imx7ulp-evk.dtb \ + imx7ulp-evk-emmc.dtb \ + imx7ulp-evk-qspi.dtb dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ + fsl-imx8qm-ddr4-val.dtb \ + fsl-imx8qm-lpddr4-val.dtb \ + fsl-imx8qm-mek-cockpit-a53.dtb \ + fsl-imx8qm-mek-cockpit-a72.dtb \ + fsl-imx8qm-mek-xen.dtb \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ fsl-imx8qxp-apalis.dtb \ fsl-imx8qxp-mek.dtb \ + fsl-imx8qxp-lpddr4-val.dtb \ + fsl-imx8qxp-lpddr4-val-gpmi-nand.dtb \ + fsl-imx8qxp-17x17-val.dtb \ + fsl-imx8dx-17x17-val.dtb \ + fsl-imx8dx-mek.dtb \ + fsl-imx8dxl-phantom-mek.dtb \ + fsl-imx8dxl-evk.dtb \ + fsl-imx8dxl-evk-lcdif.dtb \ + fsl-imx8dxl-ddr3-evk.dtb \ imx8-deneb.dtb \ imx8-giedi.dtb dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \ + imx8mm-evk-qca-wifi.dtb \ + imx8mm-ddr4-evk.dtb \ + imx8mm-ddr3l-val.dtb \ + imx8mm-ddr4-val.dtb \ imx8mm-venice.dtb \ imx8mm-venice-gw71xx-0x.dtb \ imx8mm-venice-gw72xx-0x.dtb \ imx8mm-venice-gw73xx-0x.dtb \ imx8mm-verdin.dtb \ phycore-imx8mm.dtb \ + imx8mn-ddr3l-evk.dtb \ imx8mn-ddr4-evk.dtb \ + imx8mn-evk.dtb \ + imx8mq-ddr3l-val.dtb \ + imx8mq-ddr4-val.dtb \ imx8mq-evk.dtb \ imx8mm-beacon-kit.dtb \ imx8mn-beacon-kit.dtb \ imx8mq-phanbell.dtb \ + imx8mp-ddr4-evk.dtb \ imx8mp-evk.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ imx8mq-pico-pi.dtb +dtb-$(CONFIG_TARGET_UCM_IMX8M_MINI) += ucm-imx8m-mini.dtb +dtb-$(CONFIG_TARGET_MCM_IMX8M_MINI) += mcm-imx8m-mini.dtb +dtb-$(CONFIG_TARGET_IOT_GATE_IMX8) += iot-gate-imx8.dtb +dtb-$(CONFIG_TARGET_UCM_IMX8M_PLUS) += ucm-imx8m-plus.dtb +dtb-$(CONFIG_TARGET_MCM_IMX8M_PLUS) += mcm-imx8m-plus.dtb +dtb-$(CONFIG_TARGET_SOM_IMX8M_PLUS) += som-imx8m-plus.dtb +dtb-$(CONFIG_TARGET_IOT_GATE_IMX8PLUS) += iot-gate-imx8plus.dtb +dtb-$(CONFIG_TARGET_IOTDIN_IMX8P) += iotdin-imx8p.dtb dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb \ imxrt1020-evk.dtb diff --git a/arch/arm/dts/cpl-imx8m-mini.dtsi b/arch/arm/dts/cpl-imx8m-mini.dtsi new file mode 100644 index 00000000000..c37ad9c71d1 --- /dev/null +++ b/arch/arm/dts/cpl-imx8m-mini.dtsi @@ -0,0 +1,490 @@ +/* + * Copyright 2018 CompuLab + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "imx8mm.dtsi" + +/ { + chosen { + bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200"; + stdout-patch = &uart3; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status_led { + label = "status"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + cpl-imx8m-mini { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140 + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x140 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart3: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 + >; + }; + + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49 + MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49 + MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49 + MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-okay; + at803x,vddio-1p8v; + }; + }; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + fsl,wp-controller; + vmmc-supply = <®_usdhc2_vmmc>; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; + +&usbotg1 { + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&cpu_alert0 { + temperature = <105000>; +}; +&cpu_crit0 { + temperature = <115000>; +}; diff --git a/arch/arm/dts/fsl-imx8-ca53.dtsi b/arch/arm/dts/fsl-imx8-ca53.dtsi index 6a2292a51ec..b2039d2f9aa 100644 --- a/arch/arm/dts/fsl-imx8-ca53.dtsi +++ b/arch/arm/dts/fsl-imx8-ca53.dtsi @@ -12,6 +12,8 @@ * GNU General Public License for more details. */ +#include + /{ cpus { #address-cells = <2>; @@ -22,7 +24,6 @@ CPU_SLEEP: cpu-sleep { compatible = "arm,idle-state"; - local-timer-stop; arm,psci-suspend-param = <0x0000000>; entry-latency-us = <700>; exit-latency-us = <250>; @@ -31,7 +32,6 @@ CLUSTER_SLEEP: cluster-sleep { compatible = "arm,idle-state"; - local-timer-stop; arm,psci-suspend-param = <0x1000000>; entry-latency-us = <1000>; exit-latency-us = <700>; @@ -89,4 +89,11 @@ cpu_off = <0xc4000002>; cpu_on = <0xc4000003>; }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; + }; }; diff --git a/arch/arm/dts/fsl-imx8-ca72.dtsi b/arch/arm/dts/fsl-imx8-ca72.dtsi new file mode 100644 index 00000000000..92f8aa60cae --- /dev/null +++ b/arch/arm/dts/fsl-imx8-ca72.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ + +#include +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x0000000>; + entry-latency-us = <700>; + exit-latency-us = <250>; + min-residency-us = <1000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x1000000>; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2700>; + wakeup-latency-us = <1500>; + }; + }; + + /* We have 2nd clusters having 2 Cortex-A72 cores */ + A72_0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72","arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A72_1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72","arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + next-level-cache = <&A72_L2>; + cpu-idle-states = <&CPU_SLEEP>; + }; + + A72_L2: l2-cache1 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + interrupt-affinity = <&A72_0>, <&A72_1>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + cpu_suspend = <0xc4000001>; + cpu_off = <0xc4000002>; + cpu_on = <0xc4000003>; + }; +}; diff --git a/arch/arm/dts/fsl-imx8dx-17x17-val.dts b/arch/arm/dts/fsl-imx8dx-17x17-val.dts new file mode 100644 index 00000000000..970fac337ee --- /dev/null +++ b/arch/arm/dts/fsl-imx8dx-17x17-val.dts @@ -0,0 +1,19 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qxp-17x17-val.dts" + +/ { + model = "NXP i.MX8DX 17x17 Validation board"; +}; diff --git a/arch/arm/dts/fsl-imx8dx-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8dx-mek-u-boot.dtsi new file mode 100644 index 00000000000..f89a781b2a8 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dx-mek-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "fsl-imx8qxp-mek-u-boot.dtsi" diff --git a/arch/arm/dts/fsl-imx8dx-mek.dts b/arch/arm/dts/fsl-imx8dx-mek.dts new file mode 100644 index 00000000000..52055ff4790 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dx-mek.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include "fsl-imx8qxp-mek.dts" + +/ { + model = "NXP i.MX8DX MEK"; +}; diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi index 7d95cf0b7dc..a36bf388c79 100644 --- a/arch/arm/dts/fsl-imx8dx.dtsi +++ b/arch/arm/dts/fsl-imx8dx.dtsi @@ -6,6 +6,7 @@ #include #include "fsl-imx8-ca35.dtsi" #include +#include #include #include #include @@ -14,23 +15,35 @@ #include / { - model = "Freescale i.MX8DX"; + model = "NXP i.MX8DX"; compatible = "fsl,imx8dx", "fsl,imx8qxp"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; aliases { + csi0 = &mipi_csi_0; + video0 = &dpu1; ethernet0 = &fec1; ethernet1 = &fec2; + dsiphy0 = &mipi_dsi_phy1; + dsiphy1 = &mipi_dsi_phy2; + mipidsi0 = &mipi_dsi1; + mipidsi1 = &mipi_dsi2; + display0 = &ldb1; + display1 = &ldb2; + isi0 = &isi_0; + isi1 = &isi_1; + isi2 = &isi_2; + isi3 = &isi_3; + isi4 = &isi_4; + isi5 = &isi_5; + isi6 = &isi_6; + isi7 = &isi_7; serial0 = &lpuart0; - mmc0 = &usdhc1; - mmc1 = &usdhc2; - mmc2 = &usdhc3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; @@ -39,6 +52,48 @@ gpio5 = &gpio5; gpio6 = &gpio6; gpio7 = &gpio7; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c13 = &i2c0_mipi_lvds0; + i2c15 = &i2c0_mipi_lvds1; + spi0 = &flexspi0; + usb0 = &usbotg1; + usbphy0 = &usbphy1; + usb1 = &usbotg3; + pci0 = &pcieb; + spi1 = &lpspi0; + }; + + cpus { + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x10000>; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <5000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x10033>; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <2300>; + min-residency-us = <14000>; + }; + }; }; memory@80000000 { @@ -64,34 +119,39 @@ }; encoder_boot: encoder_boot@0x86000000 { no-map; - reg = <0 0x86000000 0 0x2000000>; + reg = <0 0x86000000 0 0x200000>; }; rpmsg_reserved: rpmsg@0x90000000 { no-map; reg = <0 0x90000000 0 0x400000>; }; - decoder_rpc: decoder_rpc@0x90400000 { + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { no-map; - reg = <0 0x90400000 0 0x1000000>; + reg = <0 0x92000000 0 0x200000>; }; - encoder_rpc: encoder_rpc@0x91400000 { + encoder_rpc: encoder_rpc@0x92200000 { no-map; - reg = <0 0x91400000 0 0x1000000>; + reg = <0 0x92200000 0 0x200000>; }; dsp_reserved: dsp@0x92400000 { no-map; reg = <0 0x92400000 0 0x2000000>; }; - decoder_str: str@0x94400000 { + encoder_reserved: encoder_reserved@0x94400000 { no-map; - reg = <0 0x94400000 0 0x1800000>; + reg = <0 0x94400000 0 0x800000>; }; /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; reusable; - size = <0 0x28000000>; - alloc-ranges = <0 0x96000000 0 0x28000000>; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; linux,cma-default; }; }; @@ -107,6 +167,14 @@ interrupt-parent = <&gic>; }; + mu8: mu@5d230000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d230000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu8a>; + status = "okay"; + }; + mu: mu@5d1c0000 { compatible = "fsl,imx8-mu"; reg = <0x0 0x5d1c0000 0x0 0x10000>; @@ -124,6 +192,52 @@ }; }; + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-dsp"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = ; + fsl,dsp_ap_mu_id = <13>; + status = "okay"; + }; + + mu_m4: mu_m4@37440000 { + compatible = "fsl,imx8-mu0-vpu-m4"; + reg = <0x0 0x37440000 0x0 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <15>; + status = "okay"; + }; + + mu_m0: mu_m0@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0"; + reg = <0x0 0x2d000000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <16>; + status = "okay"; + }; + + mu1_m0: mu1_m0@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x0 0x2d020000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + status = "okay"; + }; + + rtc: rtc { + compatible = "fsl,imx-sc-rtc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; + interrupt-parent = <&gic>; + }; + imx8qx-pm { compatible = "simple-bus"; #address-cells = <1>; @@ -136,6 +250,51 @@ #address-cells = <1>; #size-cells = <0>; + pd_lsio_pwm0: PD_LSIO_PWM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm1: PD_LSIO_PWM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm2: PD_LSIO_PWM_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm3: PD_LSIO_PWM_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm4: PD_LSIO_PWM_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm5: PD_LSIO_PWM_5 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm6: PD_LSIO_PWM_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm7: PD_LSIO_PWM_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_kpp: PD_LSIO_KPP { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; pd_lsio_gpio0: PD_LSIO_GPIO_0 { reg = ; #power-domain-cells = <0>; @@ -166,7 +325,7 @@ #power-domain-cells = <0>; power-domains = <&pd_lsio>; }; - pd_lsio_gpio6: PD_LSIO_GPIO_6 { + pd_lsio_gpio6:PD_LSIO_GPIO_6 { reg = ; #power-domain-cells = <0>; power-domains = <&pd_lsio>; @@ -176,6 +335,51 @@ #power-domain-cells = <0>; power-domains = <&pd_lsio>; }; + pd_lsio_gpt0: PD_LSIO_GPT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt1: PD_LSIO_GPT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt2: PD_LSIO_GPT_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt3: PD_LSIO_GPT_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt4: PD_LSIO_GPT_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi0: PD_LSIO_FSPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi1: PD_LSIO_FSPI_1{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu5a: PD_LSIO_MU5A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu8a: PD_LSIO_MU8A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; }; pd_conn: PD_CONN { @@ -185,6 +389,43 @@ #address-cells = <1>; #size-cells = <0>; + pd_conn_usbotg0: PD_CONN_USB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <267>; + + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usbotg0>; + wakeup-irq = <267>; + }; + + }; + pd_conn_usbotg1: PD_CONN_USB_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_usb2: PD_CONN_USB_2 { + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <271>; + + pd_conn_usb2_phy: PD_CONN_USB_2_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usb2>; + wakeup-irq = <271>; + }; + + }; pd_conn_sdch0: PD_CONN_SDHC_0 { reg = ; #power-domain-cells = <0>; @@ -204,11 +445,421 @@ reg = ; #power-domain-cells = <0>; power-domains = <&pd_conn>; + wakeup-irq = <258>; }; pd_conn_enet1: PD_CONN_ENET_1 { reg = ; #power-domain-cells = <0>; power-domains = <&pd_conn>; + fsl,wakeup_irq = <262>; + }; + pd_conn_nand: PD_CONN_NAND { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_mlb0: PD_CONN_MLB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + }; + + pd_audio: PD_AUDIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { + reg = ; + power-domains =<&pd_audio>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { + reg = ; + power-domains =<&pd_audio_pll0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { + reg = ; + power-domains =<&pd_audio_pll1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan0: PD_ASRC_0_RXA { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan1: PD_ASRC_0_RXB { + reg = ; + power-domains =<&pd_dma0_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan2: PD_ASRC_0_RXC { + reg = ; + power-domains =<&pd_dma0_chan1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan3: PD_ASRC_0_TXA { + reg = ; + power-domains =<&pd_dma0_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan4: PD_ASRC_0_TXB { + reg = ; + power-domains =<&pd_dma0_chan3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan5: PD_ASRC_0_TXC { + reg = ; + power-domains =<&pd_dma0_chan4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc0:PD_AUD_ASRC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan5>; + }; + }; + }; + }; + }; + }; + }; + + pd_dma1_chan0: PD_ASRC_1_RXA { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan1: PD_ASRC_1_RXB { + reg = ; + power-domains =<&pd_dma1_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan2: PD_ASRC_1_RXC { + reg = ; + power-domains =<&pd_dma1_chan1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan3: PD_ASRC_1_TXA { + reg = ; + power-domains =<&pd_dma1_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan4: PD_ASRC_1_TXB { + reg = ; + power-domains =<&pd_dma1_chan3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan5: PD_ASRC_1_TXC { + reg = ; + power-domains =<&pd_dma1_chan4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc1: PD_AUD_ASRC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma1_chan5>; + + }; + }; + }; + }; + }; + }; + }; + pd_dma0_chan6: PD_ESAI_0_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan7: PD_ESAI_0_TX { + reg = ; + power-domains =<&pd_dma0_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_esai0: PD_AUD_ESAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan7>; + }; + }; + }; + pd_dma0_chan8: PD_SPDIF_0_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan9: PD_SPDIF_0_TX { + reg = ; + power-domains =<&pd_dma0_chan8>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_spdif0: PD_AUD_SPDIF_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan9>; + + }; + }; + }; + pd_dma0_chan12: PD_SAI_0_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan13: PD_SAI_0_TX { + reg = ; + power-domains =<&pd_dma0_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai0:PD_AUD_SAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan13>; + }; + }; + + }; + pd_dma0_chan14: PD_SAI_1_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan15: PD_SAI_1_TX { + reg = ; + power-domains =<&pd_dma0_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai1: PD_AUD_SAI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan15>; + }; + }; + }; + pd_dma0_chan16: PD_SAI_2_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + pd_sai2: PD_AUD_SAI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan16>; + }; + }; + pd_dma0_chan17: PD_SAI_3_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai3: PD_AUD_SAI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan17>; + }; + }; + pd_dma1_chan8: PD_SAI_4_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma1_chan9: PD_SAI_4_TX { + reg = ; + power-domains =<&pd_dma1_chan8>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai4: PD_AUD_SAI_4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma1_chan9>; + + }; + }; + }; + pd_dma1_chan10: PD_SAI_5_TX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + pd_sai5: PD_AUD_SAI_5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma1_chan10>; + }; + }; + pd_gpt5: PD_AUD_GPT_5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt6: PD_AUD_GPT_6 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt7: PD_AUD_GPT_7 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt8: PD_AUD_GPT_8 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt9: PD_AUD_GPT_9 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt10: PD_AUD_GPT_10 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_amix: PD_AUD_AMIX { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mqs0: PD_AUD_MQS_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out0: PD_AUD_MCLK_OUT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out1: PD_AUD_MCLK_OUT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + }; + }; + }; + }; + + pd_dsp_mu_A: PD_DSP_MU_A { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_mu_B: PD_DSP_MU_B { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_A>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dsp_ram: PD_AUD_OCRAM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_mu_B>; + #address-cells = <1>; + #size-cells = <0>; + pd_dsp: PD_AUD_DSP { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dsp_ram>; + }; + }; + }; }; }; @@ -219,6 +870,57 @@ #address-cells = <1>; #size-cells = <0>; + pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lcd0: PD_DMA_LCD_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_elcdif_pll>; + }; + }; + pd_dma_flexcan0: PD_DMA_CAN_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <235>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_flexcan1: PD_DMA_CAN_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_flexcan0>; + wakeup-irq = <236>; + }; + + pd_dma_flexcan2: PD_DMA_CAN_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_flexcan0>; + wakeup-irq = <237>; + }; + }; + + pd_dma_ftm0: PD_DMA_FTM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm1: PD_DMA_FTM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc0: PD_DMA_ADC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; pd_dma_lpi2c0: PD_DMA_I2C_0 { reg = ; #power-domain-cells = <0>; @@ -243,24 +945,1455 @@ reg = ; #power-domain-cells = <0>; power-domains = <&pd_dma>; - wakeup-irq = <225>; + wakeup-irq = <345>; }; pd_dma_lpuart1: PD_DMA_UART1 { reg = ; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <346>; + + pd_dma2_chan10: PD_UART1_RX { + reg = ; + power-domains =<&pd_dma_lpuart1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan11: PD_UART1_TX { + reg = ; + power-domains =<&pd_dma2_chan10>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; pd_dma_lpuart2: PD_DMA_UART2 { reg = ; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <347>; + + pd_dma2_chan12: PD_UART2_RX { + reg = ; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan13: PD_UART2_TX { + reg = ; + power-domains =<&pd_dma2_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; pd_dma_lpuart3: PD_DMA_UART3 { reg = ; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <348>; + + pd_dma3_chan14: PD_UART3_RX { + reg = ; + power-domains =<&pd_dma_lpuart3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan15: PD_UART3_TX { + reg = ; + power-domains =<&pd_dma3_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpspi0: PD_DMA_SPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi1: PD_DMA_SPI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi2: PD_DMA_SPI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi3: PD_DMA_SPI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_pwm0: PD_DMA_PWM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; }; }; + + pd_gpu: gpu-power-domain { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_gpu0: gpu0 { + name = "gpu0"; + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_gpu>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + pd_vpu: vpu-power-domain { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_mu_enc: VPU_ENC_MU { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_vpu>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_enc: VPU_ENC { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_mu_enc>; + }; + }; + + pd_vpu_mu_dec: VPU_DEC_MU { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_vpu>; + #address-cells = <1>; + #size-cells = <0>; + + pd_vpu_dec: VPU_DEC { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_vpu_mu_dec>; + }; + }; + }; + + pd_hsio: hsio-power-domain { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hsio_gpio: PD_HSIO_GPIO { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes1: PD_HSIO_SERDES_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio_gpio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: PD_HSIO_PCIE_B { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_serdes1>; + }; + }; + }; + }; + + pd_cm40: PD_CM40 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_cm40_i2c: PD_CM40_I2C { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + + pd_cm40_intmux: PD_CM40_INTMUX { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + }; + + + pd_dc0: PD_DC_0 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll0: PD_DC_0_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll1: PD_DC_0_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0_pll0>; + }; + }; + pd_mipi_dsi0: PD_MIPI_0_DSI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_0_lvds: PD_LVDS0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + + pd_mipi_dsi_0_aux_lvds: PD_AUX_LVDS0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_mipi_dsi0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_1_dual_lvds: PD_DUAL_LVDS1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_mipi_dsi_0_aux_lvds>; + }; + }; + + pd_mipi_dsi_0_i2c0: PD_MIPI_0_DSI_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + pd_mipi_dsi_0_i2c1: PD_MIPI_0_DSI_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + pd_mipi_0_pwm0: PD_MIPI_0_DSI_PWM0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi0>; + }; + }; + + pd_mipi_dsi1: PD_MIPI_1_DSI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_1_lvds: PD_LVDS1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + + pd_mipi_dsi_1_aux_lvds: PD_AUX_LVDS1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_mipi_dsi1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_dsi_0_dual_lvds: PD_DUAL_LVDS0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_mipi_dsi_1_aux_lvds>; + }; + }; + + pd_mipi_dsi_1_i2c0: PD_MIPI_1_DSI_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + pd_mipi_dsi_1_i2c1: PD_MIPI_1_DSI_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + pd_mipi_1_pwm0: PD_MIPI_1_DSI_PWM0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_dsi1>; + }; + }; + }; + + pd_isi_ch0: PD_IMAGING { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi_csi: PD_MIPI_CSI0 { + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains =<&pd_isi_ch0>; + + pd_mipi_csi_i2c0: PD_MIPI_CSI0_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_csi>; + }; + + pd_mipi_csi_pwm0: PD_MIPI_CSI0_PWM { + name = "mipi_csi0_pwm"; + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi_csi>; + }; + }; + + pd_parallel_csi: PD_PARALLEL_CSI { + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains =<&pd_isi_ch0>; + + pd_parallel_csi_i2c0: PD_PARALLEL_CSI_I2C { + name = "parallel_csi_i2c"; + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_parallel_csi>; + }; + + pd_parallel_csi_pwm0: PD_PARALLEL_CSI_PWM { + name = "parallel_csi_pwm"; + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_parallel_csi>; + }; + + pd_parallel_csi_pll: PD_PARALLEL_CSI_PLL { + name = "parallel_csi_pll"; + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_parallel_csi>; + }; + }; + + pd_isi_ch1: PD_IMAGING_PDMA1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch2: PD_IMAGING_PDMA2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch3: PD_IMAGING_PDMA3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch4: PD_IMAGING_PDMA4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch5: PD_IMAGING_PDMA5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch6: PD_IMAGING_PDMA6 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_isi_ch7: PD_IMAGING_PDMA7 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + }; + + pd_jpeg_dec_mp: PD_JPEG_DEC_MP{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_jpgdec: PD_IMAGING_JPEG_DEC { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_jpeg_dec_mp>; + }; + }; + + pd_jpeg_enc_mp: PD_JPEG_ENC_MP{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_jpgenc: PD_IMAGING_JPEG_ENC { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_jpeg_enc_mp>; + }; + }; + }; + pd_caam: PD_CAAM { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_caam_jr1: PD_CAAM_JR1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr2: PD_CAAM_JR2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr3: PD_CAAM_JR3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + }; + }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qxp-sc-tsens"; + u-boot,dm-pre-reloc; + /* number of the temp sensor on the chip */ + tsens-num = <2>; + #thermal-sensor-cells = <1>; + }; + + thermal_zones: thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 1>; + status = "disabled"; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + irqsteer_csi: irqsteer@58220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58220000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg"; + power-domains = <&pd_mipi_csi>; + }; + + i2c0_csi0: i2c@58226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x58226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi>; + clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>, + <&clk IMX8QXP_CSI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CSI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_csi_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + intmux_cm40: intmux@37400000 { + compatible = "nxp,imx-intmux"; + reg = <0x0 0x37400000 0x0 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CM40_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_cm40_intmux>; + status = "disabled"; + }; + + i2c0_cm40: i2c@37230000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x37230000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intmux_cm40>; + clocks = <&clk IMX8QXP_CM40_I2C_CLK>, + <&clk IMX8QXP_CM40_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_cm40_i2c>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dpu_intsteer: dpu_intsteer@56000000 { + compatible = "fsl,imx8qxp-dpu-intsteer", "syscon"; + reg = <0x0 0x56000000 0x0 0x10000>; + }; + + pixel_combiner: pixel-combiner@56020000 { + compatible = "fsl,imx8qxp-pixel-combiner"; + reg = <0x0 0x56020000 0x0 0x10000>; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg1: prg@56040000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56040000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG0_APB_CLK>, + <&clk IMX8QXP_DC0_PRG0_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg2: prg@56050000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56050000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG1_APB_CLK>, + <&clk IMX8QXP_DC0_PRG1_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg3: prg@56060000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56060000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG2_APB_CLK>, + <&clk IMX8QXP_DC0_PRG2_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg4: prg@56070000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56070000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG3_APB_CLK>, + <&clk IMX8QXP_DC0_PRG3_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg5: prg@56080000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56080000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG4_APB_CLK>, + <&clk IMX8QXP_DC0_PRG4_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg6: prg@56090000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x56090000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG5_APB_CLK>, + <&clk IMX8QXP_DC0_PRG5_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg7: prg@560a0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x560a0000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG6_APB_CLK>, + <&clk IMX8QXP_DC0_PRG6_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg8: prg@560b0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x560b0000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG7_APB_CLK>, + <&clk IMX8QXP_DC0_PRG7_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + prg9: prg@560c0000 { + compatible = "fsl,imx8qxp-prg", "fsl,imx8qm-prg"; + reg = <0x0 0x560c0000 0x0 0x10000>; + clocks = <&clk IMX8QXP_DC0_PRG8_APB_CLK>, + <&clk IMX8QXP_DC0_PRG8_RTRAM_CLK>; + clock-names = "apb", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr1_channel1: dpr-channel@560d0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x560d0000 0x0 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&prg1>; + clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, + <&clk IMX8QXP_DC0_DPR0_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr1_channel2: dpr-channel@560e0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x560e0000 0x0 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&prg2>, <&prg1>; + clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, + <&clk IMX8QXP_DC0_DPR0_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr1_channel3: dpr-channel@560f0000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x560f0000 0x0 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&prg3>; + clocks = <&clk IMX8QXP_DC0_DPR0_APB_CLK>, + <&clk IMX8QXP_DC0_DPR0_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM0_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr2_channel1: dpr-channel@56100000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56100000 0x0 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&prg4>, <&prg5>; + clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>, + <&clk IMX8QXP_DC0_DPR1_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr2_channel2: dpr-channel@56110000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56110000 0x0 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&prg6>, <&prg7>; + clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>, + <&clk IMX8QXP_DC0_DPR1_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpr2_channel3: dpr-channel@56120000 { + compatible = "fsl,imx8qxp-dpr-channel", + "fsl,imx8qm-dpr-channel"; + reg = <0x0 0x56120000 0x0 0x10000>; + fsl,sc-resource = ; + fsl,prgs = <&prg8>, <&prg9>; + clocks = <&clk IMX8QXP_DC0_DPR1_APB_CLK>, + <&clk IMX8QXP_DC0_DPR1_B_CLK>, + <&clk IMX8QXP_DC0_RTRAM1_CLK>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd_dc0>; + status = "disabled"; + }; + + dpu1: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-dpu", "fsl,imx8qm-dpu"; + reg = <0x0 0x56180000 0x0 0x40000>; + intsteer = <&dpu_intsteer>; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", /* to M4? */ + "irq_stream1a", + "irq_stream1b", /* to M4? */ + "irq_reserved0", + "irq_reserved1", + "irq_blit", + "irq_dpr0", + "irq_dpr1"; + clocks = <&clk IMX8QXP_DC0_PLL0_CLK>, + <&clk IMX8QXP_DC0_PLL1_CLK>, + <&clk IMX8QXP_DC0_DISP0_CLK>, + <&clk IMX8QXP_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd_dc0_pll1>; + fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, + <&dpr1_channel3>, <&dpr2_channel1>, + <&dpr2_channel2>, <&dpr2_channel3>; + fsl,pixel-combiner = <&pixel_combiner>; + status = "disabled"; + + dpu_disp0: port@0 { + reg = <0>; + + dpu_disp0_lvds0_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu_disp0_lvds0_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + + dpu_disp0_mipi_dsi: endpoint@2 { + remote-endpoint = <&mipi_dsi1_in>; + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + dpu_disp1_lvds1_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu_disp1_lvds1_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + + dpu_disp1_mipi_dsi: endpoint@2 { + remote-endpoint = <&mipi_dsi2_in>; + }; + }; + }; + + irqsteer_mipi_lvds0: irqsteer@56220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56220000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_MIPI0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_dsi0>; + }; + + adma_lcdif: lcdif@5a180000 { + compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; + reg = <0x0 0x5a180000 0x0 0x10000>; + clocks = <&clk IMX8QXP_LCD_DIV>, + <&clk IMX8QXP_LCD_PXL_DIV>, + <&clk IMX8QXP_LCD_IPG_CLK>; + clock-names = "pix", "disp_axi", "axi"; + assigned-clocks = <&clk IMX8QXP_LCD_SEL>, + <&clk IMX8QXP_LCD_PXL_SEL>, + <&clk IMX8QXP_ELCDIF_PLL_DIV>; + assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>, + <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; + assigned-clock-rates = <0>, <0>, <804000000>; + interrupts = ; + power-domains = <&pd_dma_lcd0>; + status = "disabled"; + }; + + pwm_adma_lcdif: pwm@5a190000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5a190000 0 0x1000>; + clocks = <&clk IMX8QXP_PWM_IPG_CLK>, + <&clk IMX8QXP_PWM_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_PWM_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_dma_pwm0>; + status = "disabled"; + }; + + mipi_dsi_csr1: csr@56221000 { + compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon"; + reg = <0x0 0x56221000 0x0 0x1000>; + }; + + mipi_dsi_phy1: dsi_phy@56228300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8qxp-mipi-dsi-phy"; + reg = <0x0 0x56228300 0x0 0x100>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi_bridge1: mipi_dsi_bridge@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x56228000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = + <&clk IMX8QXP_MIPI0_BYPASS_CLK>, + <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = + <&clk IMX8QXP_MIPI0_DSI_TX_ESC_SEL>, + <&clk IMX8QXP_MIPI0_DSI_RX_ESC_SEL>, + <&clk IMX8QXP_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI0_DSI_RX_ESC_CLK>; + assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; + assigned-clock-parents = + <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>, + <&clk IMX8QXP_MIPI0_DSI_PLL_DIV2_CLK>; + power-domains = <&pd_mipi_dsi0>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge1_in: endpoint { + remote-endpoint = <&mipi_dsi1_out>; + }; + }; + }; + + mipi_dsi1: mipi_dsi@56228000 { + compatible = "fsl,imx8qxp-mipi-dsi"; + clocks = + <&clk IMX8QXP_MIPI0_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_BYPASS_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi_dsi0>; + csr = <&mipi_dsi_csr1>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi1_in: endpoint { + remote-endpoint = <&dpu_disp0_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi1_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_in>; + }; + }; + }; + + lvds_region1: lvds_region@56220000 { + compatible = "fsl,imx8qxp-lvds-region", "syscon"; + reg = <0x0 0x56220000 0x0 0x10000>; + }; + + ldb1_phy: ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX8QXP_MIPI0_LVDS_PHY_CLK>; + clock-names = "phy"; + status = "disabled"; + }; + + ldb1: ldb@562210e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass"; + power-domains = <&pd_mipi_dsi_0_lvds>; + gpr = <&lvds_region1>; + aux-gpr = <&lvds_region2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy>, <&ldb2_phy>; + phy-names = "ldb_phy", "aux_ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch0: endpoint { + remote-endpoint = <&dpu_disp0_lvds0_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_ch1: endpoint { + remote-endpoint = <&dpu_disp0_lvds0_ch1>; + }; + }; + }; + }; + + pwm_mipi_lvds0: pwm@56224000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x56224000 0 0x1000>; + clocks = <&clk IMX8QXP_MIPI0_PWM_IPG_CLK>, + <&clk IMX8QXP_MIPI0_PWM_CLK>, + <&clk IMX8QXP_MIPI0_PWM_32K_CLK>; + clock-names = "ipg", "per", "32k"; + assigned-clocks = <&clk IMX8QXP_MIPI0_PWM_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_mipi_0_pwm0>; + status = "disabled"; + }; + + i2c0_mipi_lvds0: i2c@56226000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds0>; + clocks = <&clk IMX8QXP_MIPI0_I2C0_CLK>, + <&clk IMX8QXP_MIPI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_MIPI0_I2C0_DIV>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_dsi_0_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + irqsteer_mipi_lvds1: irqsteer@56240000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56240000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_MIPI1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi_dsi1>; + }; + + mipi_dsi_csr2: csr@56241000 { + compatible = "fsl,imx8qxp-mipi-dsi-csr", "syscon"; + reg = <0x0 0x56241000 0x0 0x1000>; + }; + + mipi_dsi_phy2: dsi_phy@56248300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8qxp-mipi-dsi-phy"; + reg = <0x0 0x56248300 0x0 0x100>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi_bridge2: mipi_dsi_bridge@56248000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x56248000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = + <&clk IMX8QXP_MIPI1_BYPASS_CLK>, + <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = + <&clk IMX8QXP_MIPI1_DSI_TX_ESC_SEL>, + <&clk IMX8QXP_MIPI1_DSI_RX_ESC_SEL>, + <&clk IMX8QXP_MIPI1_DSI_TX_ESC_CLK>, + <&clk IMX8QXP_MIPI1_DSI_RX_ESC_CLK>; + assigned-clock-rates = <0>, <0>, <18000000>, <72000000>; + assigned-clock-parents = + <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>, + <&clk IMX8QXP_MIPI1_DSI_PLL_DIV2_CLK>; + power-domains = <&pd_mipi_dsi1>; + phys = <&mipi_dsi_phy2>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge2_in: endpoint { + remote-endpoint = <&mipi_dsi2_out>; + }; + }; + }; + + mipi_dsi2: mipi_dsi@56248000 { + compatible = "fsl,imx8qxp-mipi-dsi"; + clocks = + <&clk IMX8QXP_MIPI1_PIXEL_CLK>, + <&clk IMX8QXP_MIPI1_BYPASS_CLK>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi_dsi1>; + csr = <&mipi_dsi_csr2>; + phys = <&mipi_dsi_phy2>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi2_in: endpoint { + remote-endpoint = <&dpu_disp1_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi2_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_in>; + }; + }; + }; + + lvds_region2: lvds_region@56240000 { + compatible = "fsl,imx8qxp-lvds-region", "syscon"; + reg = <0x0 0x56240000 0x0 0x10000>; + }; + + ldb2_phy: ldb_phy@56241000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56241000 0x0 0x100>, <0x0 0x56248000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX8QXP_MIPI1_LVDS_PHY_CLK>; + clock-names = "phy"; + status = "disabled"; + }; + + ldb2: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX8QXP_MIPI1_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI1_LVDS_BYPASS_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_PIXEL_CLK>, + <&clk IMX8QXP_MIPI0_LVDS_BYPASS_CLK>; + clock-names = "pixel", "bypass", "aux_pixel", "aux_bypass"; + power-domains = <&pd_mipi_dsi_1_lvds>; + gpr = <&lvds_region2>; + aux-gpr = <&lvds_region1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy>, <&ldb1_phy>; + phy-names = "ldb_phy", "aux_ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch0: endpoint { + remote-endpoint = <&dpu_disp1_lvds1_ch0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_ch1: endpoint { + remote-endpoint = <&dpu_disp1_lvds1_ch1>; + }; + }; + }; + }; + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58100000 0x0 0x10000>; + interrupts = <0 297 0>; + interface = <2 0 2>; /* + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_0_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch0>; + status = "disabled"; + }; + + isi_1: isi@58110000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58110000 0x0 0x10000>; + interrupts = <0 298 0>; + interface = <2 1 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_1_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch1>; + status = "disabled"; + }; + + isi_2: isi@58120000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58120000 0x0 0x10000>; + interrupts = <0 299 0>; + interface = <2 2 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_2_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch2>; + status = "disabled"; + }; + + isi_3: isi@58130000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58130000 0x0 0x10000>; + interrupts = <0 300 0>; + interface = <2 3 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_3_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch3>; + status = "disabled"; + }; + + isi_4: isi@58140000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58140000 0x0 0x10000>; + interrupts = <0 301 0>; + interface = <3 0 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_4_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch4>; + status = "disabled"; + }; + + isi_5: isi@58150000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58150000 0x0 0x10000>; + interrupts = <0 302 0>; + interface = <3 1 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_5_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch5>; + status = "disabled"; + }; + + isi_6: isi@58160000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58160000 0x0 0x10000>; + interrupts = <0 303 0>; + interface = <3 2 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_6_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch6>; + status = "disabled"; + }; + + isi_7: isi@58170000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58170000 0x0 0x10000>; + interrupts = <0 304 0>; + interface = <3 3 2>; + clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QXP_IMG_PDMA_7_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch7>; + status = "disabled"; + }; + + mipi_csi_0: csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ + <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi>; + clocks = <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CSI0_CORE_CLK>, + <&clk IMX8QXP_CSI0_ESC_CLK>, + <&clk IMX8QXP_IMG_PXL_LINK_CSI0_CLK>; + clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&clk IMX8QXP_CSI0_CORE_CLK>, + <&clk IMX8QXP_CSI0_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd_mipi_csi>; + status = "disabled"; + }; + + parallel_csi: pcsi@58261000 { + compatible = "fsl,mxc-parallel-csi"; + reg = <0x0 0x58261000 0x0 0x1000>; + clocks = <&clk IMX8QXP_PARALLEL_CSI_PIXEL_CLK>, + <&clk IMX8QXP_PARALLEL_CSI_IPG_CLK>, + <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>, + <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>, + <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>; + clock-names = "pixel", "ipg", "sel", "div", "dpll"; + assigned-clocks = <&clk IMX8QXP_PARALLEL_CSI_CLK_SEL>, + <&clk IMX8QXP_PARALLEL_CSI_PER_CLK_DIV>; + assigned-clock-parents = <&clk IMX8QXP_PARALLEL_CSI_CLK_DPLL>; + assigned-clock-rates = <0>, <160000000>; /* 160MHz */ + power-domains = <&pd_parallel_csi>; + status = "disabled"; + }; + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x0 0x58400000 0x0 0x00040020 >; + interrupts = ; + clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >, + <&clk IMX8QXP_IMG_JPEG_DEC_CLK >; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_IMG_JPEG_DEC_IPG_CLK >, + <&clk IMX8QXP_IMG_JPEG_DEC_CLK >; + assigned-clock-rates = <200000000>; + power-domains =<&pd_jpgdec>; + status = "okay"; + }; + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x0 0x58450000 0x0 0x00240020 >; + interrupts = ; + clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >, + <&clk IMX8QXP_IMG_JPEG_ENC_CLK >; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_IMG_JPEG_ENC_IPG_CLK >, + <&clk IMX8QXP_IMG_JPEG_ENC_CLK >; + assigned-clock-rates = <200000000>; + power-domains =<&pd_jpgenc>; + status = "okay"; + }; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_5: i2c-rpbus-5 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_12: i2c-rpbus-12 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_13: i2c-rpbus-13 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_14: i2c-rpbus-14 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_15: i2c-rpbus-15 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + pwm_mipi_lvds1: pwm@56244000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x56244000 0 0x1000>; + clocks = <&clk IMX8QXP_MIPI1_PWM_IPG_CLK>, + <&clk IMX8QXP_MIPI1_PWM_CLK>, + <&clk IMX8QXP_MIPI1_PWM_32K_CLK>; + clock-names = "ipg", "per", "32k"; + assigned-clocks = <&clk IMX8QXP_MIPI1_PWM_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_mipi_1_pwm0>; + status = "disabled"; + }; + + i2c0_mipi_lvds1: i2c@56246000 { + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56246000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_mipi_lvds1>; + clocks = <&clk IMX8QXP_MIPI1_I2C0_CLK>, + <&clk IMX8QXP_MIPI1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_MIPI1_I2C0_DIV>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi_dsi_1_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + adc0: adc@5a880000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x0 0x5a880000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_ADC0_CLK>, + <&clk IMX8QXP_ADC0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_ADC0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_adc0>; + status = "disabled"; }; i2c0: i2c@5a800000 { @@ -327,13 +2460,168 @@ status = "disabled"; }; + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x5b0d0200 0x0 0x200>; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b100000 0x0 0x1000>; + clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg0_phy>; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0d0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&clk IMX8QXP_USB2_OH_AHB_CLK>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg0>; + status = "disabled"; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8d0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan0>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8e0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&wu>; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan1>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8f0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&wu>; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan2>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + dma_apbh: dma-apbh@5b810000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x0 0x5b810000 0x0 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8QXP_APBHDMA_CLK>; + power-domains = <&pd_conn_nand>; + }; + + gpmi: gpmi-nand@5b812000{ + compatible = "fsl,imx8qxp-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>, + <&clk IMX8QXP_GPMI_APB_CLK>, + <&clk IMX8QXP_GPMI_BCH_CLK>, + <&clk IMX8QXP_GPMI_APB_BCH_CLK>, + <&clk IMX8QXP_APBHDMA_CLK>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch", "gpmi_apbh_dma"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + power-domains = <&pd_conn_nand>; + assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>; + assigned-clock-rates = <50000000>; + status = "disabled"; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8QXP_USB3_PHY_CLK>; + clock-names = "main_clk"; + power-domains = <&pd_conn_usb2_phy>; + }; + + usbotg3: usb3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>, + <0x0 0x5B120000 0x0 0x10000>; + reg-names = "none-core", "xhci", "dev", "phy", "otg"; + interrupt-parent = <&wu>; + interrupts = ; + clocks = <&clk IMX8QXP_USB3_LPM_CLK>, + <&clk IMX8QXP_USB3_BUS_CLK>, + <&clk IMX8QXP_USB3_ACLK>, + <&clk IMX8QXP_USB3_IPG_CLK>, + <&clk IMX8QXP_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + assigned-clocks = <&clk IMX8QXP_USB3_ACLK_DIV>, + <&clk IMX8QXP_USB3_LPM_DIV>, + <&clk IMX8QXP_USB3_BUS_DIV>; + assigned-clock-rates = <125000000>, <12000000>, <250000000>; + power-domains = <&pd_conn_usb2>; + cdns3,usbphy = <&usbphynop1>; + status = "disabled"; + }; + + wu: wu { + compatible = "fsl,imx8-wu"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + gpio0: gpio@5d080000 { compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; reg = <0x0 0x5d080000 0x0 0x10000>; interrupts = ; gpio-controller; #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio0>; + power-domains = <&pd_lsio_gpio0>; interrupt-controller; #interrupt-cells = <2>; }; @@ -344,7 +2632,7 @@ interrupts = ; gpio-controller; #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio1>; + power-domains = <&pd_lsio_gpio1>; interrupt-controller; #interrupt-cells = <2>; }; @@ -355,7 +2643,7 @@ interrupts = ; gpio-controller; #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio2>; + power-domains = <&pd_lsio_gpio2>; interrupt-controller; #interrupt-cells = <2>; }; @@ -366,7 +2654,7 @@ interrupts = ; gpio-controller; #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio3>; + power-domains = <&pd_lsio_gpio3>; interrupt-controller; #interrupt-cells = <2>; }; @@ -388,7 +2676,7 @@ interrupts = ; gpio-controller; #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio5>; + power-domains = <&pd_lsio_gpio5>; interrupt-controller; #interrupt-cells = <2>; }; @@ -399,7 +2687,7 @@ interrupts = ; gpio-controller; #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio6>; + power-domains = <&pd_lsio_gpio6>; interrupt-controller; #interrupt-cells = <2>; }; @@ -410,15 +2698,111 @@ interrupts = ; gpio-controller; #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio7>; + power-domains = <&pd_lsio_gpio7>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio0_mipi_csi0: gpio@58222000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x58222000 0x0 0x1000>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_csi>; + gpio-controller; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + power-domains = <&pd_mipi_csi>; + }; + + gpu_3d0: gpu@53100000 { + compatible = "fsl,imx8-gpu"; + reg = <0x0 0x53100000 0 0x40000>; + interrupts = ; + clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; + clock-names = "core", "shader"; + assigned-clocks = <&clk IMX8QXP_GPU0_CORE_CLK>, <&clk IMX8QXP_GPU0_SHADER_CLK>; + assigned-clock-rates = <700000000>, <850000000>; + power-domains = <&pd_gpu0>; + status = "disabled"; + }; + + imx8_gpu_ss: imx8_gpu_ss { + compatible = "fsl,imx8qxp-gpu", "fsl,imx8-gpu-ss"; + cores = <&gpu_3d0>; + reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; + status = "disabled"; + }; + + ddr_pmu0: ddr_pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c020000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + lpspi0: lpspi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a000000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI0_CLK>, + <&clk IMX8QXP_SPI0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi0>; + status = "disabled"; + }; + + lpspi1: lpspi@5a010000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a010000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI1_CLK>, + <&clk IMX8QXP_SPI1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi1>; + status = "disabled"; + }; + + lpspi2: lpspi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a020000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI2_CLK>, + <&clk IMX8QXP_SPI2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi2>; + status = "disabled"; + }; + + lpspi3: lpspi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a030000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI3_CLK>, + <&clk IMX8QXP_SPI3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi3>; + status = "disabled"; }; lpuart0: serial@5a060000 { compatible = "fsl,imx8qm-lpuart"; reg = <0x0 0x5a060000 0x0 0x1000>; - interrupts = ; + interrupts = ; + interrupt-parent = <&wu>; clocks = <&clk IMX8QXP_UART0_CLK>, <&clk IMX8QXP_UART0_IPG_CLK>; clock-names = "per", "ipg"; @@ -431,39 +2815,359 @@ lpuart1: serial@5a070000 { compatible = "fsl,imx8qm-lpuart"; reg = <0x0 0x5a070000 0x0 0x1000>; - interrupts = ; + interrupts = ; + interrupt-parent = <&wu>; clocks = <&clk IMX8QXP_UART1_CLK>, - <&clk IMX8QXP_UART1_IPG_CLK>; + <&clk IMX8QXP_UART1_IPG_CLK>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QXP_UART1_CLK>; assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart1>; + power-domains = <&pd_dma2_chan11>; + dma-names = "tx","rx"; + dmas = <&edma2 11 0 0>, + <&edma2 10 0 1>; status = "disabled"; }; lpuart2: serial@5a080000 { compatible = "fsl,imx8qm-lpuart"; reg = <0x0 0x5a080000 0x0 0x1000>; - interrupts = ; + interrupts = ; + interrupt-parent = <&wu>; clocks = <&clk IMX8QXP_UART2_CLK>, - <&clk IMX8QXP_UART2_IPG_CLK>; + <&clk IMX8QXP_UART2_IPG_CLK>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QXP_UART2_CLK>; assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart2>; + power-domains = <&pd_dma2_chan13>; + dma-names = "tx","rx"; + dmas = <&edma2 13 0 0>, + <&edma2 12 0 1>; status = "disabled"; }; lpuart3: serial@5a090000 { compatible = "fsl,imx8qm-lpuart"; reg = <0x0 0x5a090000 0x0 0x1000>; - interrupts = ; + interrupts = ; + interrupt-parent = <&wu>; clocks = <&clk IMX8QXP_UART3_CLK>, - <&clk IMX8QXP_UART3_IPG_CLK>; + <&clk IMX8QXP_UART3_IPG_CLK>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QXP_UART3_CLK>; assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart3>; + power-domains = <&pd_dma3_chan15>; + dma-names = "tx","rx"; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; + status = "disabled"; + }; + + edma2: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ + <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ + <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ + <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ + <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <8>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", + "edma2-chan10-rx", "edma2-chan11-tx", + "edma2-chan12-rx", "edma2-chan13-tx", + "edma2-chan14-rx", "edma2-chan15-tx"; + status = "okay"; + }; + + edma0: dma-controller@591F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>, + <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ + <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ + <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59350000 0x0 0x10000>, + <0x0 0x59370000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <16>; + interrupts = , /* asrc 0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */ + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt5 */ + "edma0-chan23-rx"; /* gpt7 */ + status = "okay"; + }; + + edma1: dma-controller@599F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ + <0x0 0x59A10000 0x0 0x10000>, + <0x0 0x59A20000 0x0 0x10000>, + <0x0 0x59A30000 0x0 0x10000>, + <0x0 0x59A40000 0x0 0x10000>, + <0x0 0x59A50000 0x0 0x10000>, + <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */ + <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */ + <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = , /* asrc 1 */ + , + , + , + , + , + , /* sai4 */ + , + ; /* sai5 */ + interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */ + "edma1-chan2-rx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */ + "edma1-chan10-tx"; /* sai5 */ + status = "okay"; + }; + + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x0 0x59e00000 0x0 0x1D0000>; + status = "disabled"; + }; + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59040000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_0_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; + status = "disabled"; + power-domains = <&pd_sai0>; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59050000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_1_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; + status = "disabled"; + power-domains = <&pd_sai1>; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59060000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_2_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 16 0 1>; + status = "disabled"; + power-domains = <&pd_sai2>; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59070000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_3_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 17 0 1>; + status = "disabled"; + power-domains = <&pd_sai3>; + }; + + sai4: sai@59820000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59820000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_4_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_4_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + status = "disabled"; + power-domains = <&pd_sai4>; + }; + + sai5: sai@59830000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59830000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_5_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_5_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "tx"; + dmas = <&edma1 10 0 0>; + status = "disabled"; + power-domains = <&pd_sai5>; + }; + + amix: amix@59840000 { + compatible = "fsl,imx8qm-amix"; + reg = <0x0 0x59840000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_AMIX_IPG>; + clock-names = "ipg"; + power-domains = <&pd_amix>; + status = "disabled"; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x0 0x59000000 0x0 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, + <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc0>; + status = "disabled"; + }; + + asrc1: asrc@59800000 { + compatible = "fsl,imx8qm-asrc1"; + reg = <0x0 0x59800000 0x0 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8QXP_AUD_ASRC_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma1 0 0 0>, <&edma1 1 0 0>, <&edma1 2 0 0>, + <&edma1 3 0 1>, <&edma1 4 0 1>, <&edma1 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc1>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x0 0x59850000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_MQS_IPG>, + <&clk IMX8QXP_AUD_MQS_HMCLK>; + clock-names = "core", "mclk"; + power-domains = <&pd_mqs0>; status = "disabled"; }; @@ -474,10 +3178,10 @@ reg = <0x0 0x5b010000 0x0 0x10000>; clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, <&clk IMX8QXP_SDHC0_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; + <&clk IMX8QXP_SDHC0_AHB_CLK>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; - assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; assigned-clock-rates = <0>, <400000000>; power-domains = <&pd_conn_sdch0>; fsl,tuning-start-tap = <20>; @@ -492,10 +3196,10 @@ reg = <0x0 0x5b020000 0x0 0x10000>; clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, <&clk IMX8QXP_SDHC1_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; + <&clk IMX8QXP_SDHC1_AHB_CLK>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; - assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; assigned-clock-rates = <0>, <200000000>; power-domains = <&pd_conn_sdch1>; fsl,tuning-start-tap = <20>; @@ -510,109 +3214,370 @@ reg = <0x0 0x5b030000 0x0 0x10000>; clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, <&clk IMX8QXP_SDHC2_CLK>, - <&clk IMX8QXP_CLK_DUMMY>; + <&clk IMX8QXP_SDHC2_AHB_CLK>; clock-names = "ipg", "per", "ahb"; assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; - assigned-clock-parents = <&clk IMX8QXP_CONN_PLL0_CLK>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; assigned-clock-rates = <0>, <200000000>; power-domains = <&pd_conn_sdch2>; status = "disabled"; }; fec1: ethernet@5b040000 { - compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + compatible = "fsl,imx8qm-fec"; reg = <0x0 0x5b040000 0x0 0x10000>; + interrupt-parent = <&wu>; interrupts = , , , ; - clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, - <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, <&clk IMX8QXP_ENET0_PTP_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - assigned-clocks = <&clk IMX8QXP_ENET0_REF_DIV>, <&clk IMX8QXP_ENET0_PTP_CLK>; - assigned-clock-rates = <125000000>, <125000000>; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, + <&clk IMX8QXP_ENET0_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; power-domains = <&pd_conn_enet0>; status = "disabled"; }; fec2: ethernet@5b050000 { - compatible = "fsl,imx7d-fec", "fsl,imx8qm-fec"; + compatible = "fsl,imx8qm-fec"; reg = <0x0 0x5b050000 0x0 0x10000>; + interrupt-parent = <&wu>; interrupts = , , , ; - clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, - <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, <&clk IMX8QXP_ENET1_PTP_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp"; - assigned-clocks = <&clk IMX8QXP_ENET1_REF_DIV>, <&clk IMX8QXP_ENET1_PTP_CLK>; - assigned-clock-rates = <125000000>, <125000000>; + clocks = <&clk IMX8QXP_ENET1_IPG_CLK>, <&clk IMX8QXP_ENET1_AHB_CLK>, <&clk IMX8QXP_ENET1_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET1_PTP_CLK>, <&clk IMX8QXP_ENET1_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>, + <&clk IMX8QXP_ENET1_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; fsl,num-tx-queues=<3>; fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; power-domains = <&pd_conn_enet1>; status = "disabled"; }; - tsens: thermal-sensor { - compatible = "nxp,imx8qxp-sc-tsens"; - /* number of the temp sensor on the chip */ - tsens-num = <2>; - #thermal-sensor-cells = <1>; + mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QXP_MLB_CLK>, + <&clk IMX8QXP_MLB_HCLK>, + <&clk IMX8QXP_MLB_IPG_CLK>; + clock-names = "mlb", "hclk", "ipg"; + assigned-clocks = <&clk IMX8QXP_MLB_CLK>, + <&clk IMX8QXP_MLB_HCLK>, + <&clk IMX8QXP_MLB_IPG_CLK>; + assigned-clock-rates = <333333333>, <333333333>, <83333333>; + power-domains = <&pd_conn_mlb0>; + status = "disabled"; }; - thermal_zones: thermal-zones { - /* cpu thermal */ - cpu-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - /*the slope and offset of the temp sensor */ - thermal-sensors = <&tsens 0>; - trips { - cpu_alert0: trip0 { - temperature = <107000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit0: trip1 { - temperature = <127000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; + gpt0: gpt0@5d140000 { + compatible = "fsl,imx8qxp-gpt"; + reg = <0x0 0x5d140000 0x0 0x4000>; + interrupts = ; + clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_GPT_3M>; + clock-names = "ipg", "per"; + power-domains = <&pd_lsio_gpt0>; + }; + + dsp: dsp@596e8000 { + compatible = "fsl,imx8qxp-dsp"; + reserved-region = <&dsp_reserved>; + reg = <0x0 0x596e8000 0x0 0x88000>; + clocks = <&clk IMX8QXP_AUD_DSP_IPG>, + <&clk IMX8QXP_AUD_OCRAM_IPG>, + <&clk IMX8QXP_AUD_DSP_CORE_CLK>; + clock-names = "ipg", "ocram", "core"; + fsl,dsp-firmware = "imx/dsp/hifi4.bin"; + power-domains = <&pd_dsp>; + }; + + esai0: esai@59010000 { + compatible = "fsl,imx8qm-esai"; + reg = <0x0 0x59010000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>, + <&clk IMX8QXP_AUD_ESAI_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "core", "extal", "fsys", "spba"; + dmas = <&edma0 6 0 1>, <&edma0 7 0 0>; + dma-names = "rx", "tx"; + power-domains = <&pd_esai0>; + status = "disabled"; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x0 0x59020000 0x0 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ + <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8QXP_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd_spdif0>; + status = "disabled"; + }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8qxp-fspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>, + <&clk IMX8QXP_LSIO_FSPI0_CLK>; + assigned-clocks = <&clk IMX8QXP_LSIO_FSPI0_DIV>; + assigned-clock-rates = <29000000>; + clock-names = "fspi", "fspi_en"; + power-domains = <&pd_lsio_flexspi0>; + status = "disabled"; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu_disp0>, <&dpu_disp1>; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + hsio: hsio@5f080000 { + compatible = "fsl,imx8qm-hsio", "syscon"; + reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ + }; + + ocotp: ocotp { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx8qxp-ocotp", "syscon"; + }; + + pcieb: pcie@0x5f010000 { + /* + * pcieb phyx1 lane1 in default, adjust it refer to the + * exact hw design. + */ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/ + <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>, + <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, + <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, + <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>, + <&clk IMX8QXP_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QXP_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi", + "phy_per", "misc_per"; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + power-domains = <&pd_pcie>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + hsio = <&hsio>; + ctrl-id = <1>; /* pcieb */ + cpu-base-addr = <0x80000000>; + status = "disabled"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu", "nxp,imx8qxp-vpu"; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + interrupts = <0 464 0x4>, /* encoder irq */ + <0 465 0x4>, /* encoder fiq */ + <0 466 0x4>, /* decoder irq */ + <0 467 0x4>, /* decoder fiq */ + <0 468 0x4>; /* decoder sif */ + interrupt-names = "enc_irq", "enc_fiq", "dec_irq", "dec_fiq", "dec_sif"; + clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + clock-names = "vpu_clk"; + assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + power-domains = <&pd_vpu_dec>; + reg-csr = <0x2d040000>; + status = "disabled"; + }; + + vpu_encoder: vpu_encoder@2d000000 { + compatible = "nxp,imx8qxp-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ + reg-names = "vpu_regs"; + power-domains = <&pd_vpu_enc>; + reg-rpc-system = <0x40000000>; + + resolution-max = <1920 1080>; + fps-max = <120>; + status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1050000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; }; + }; + imx_rpmsg: imx_rpmsg { + compatible = "fsl,rpmsg-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; - drc-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tsens 1>; + mu_rpmsg: mu_rpmsg@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x0 0x5d200000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lsio_mu5a>; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; status = "disabled"; - trips { - drc_alert0: trip0 { - temperature = <107000>; - hysteresis = <2000>; - type = "passive"; - }; - drc_crit0: trip1 { - temperature = <127000>; - hysteresis = <2000>; - type = "critical"; - }; - }; + mub-partition = <3>; + power-domains = <&pd_lsio_mu5a>; + memory-region = <&rpmsg_dma_reserved>; }; }; + + crypto: caam@0x31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0 0x31400000 0 0x400000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x31400000 0x400000>; + fsl,first-jr-index = <2>; + fsl,sec-era = <9>; + + sec_jr1: jr1@0x20000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr1>; + status = "disabled"; + }; + + sec_jr2: jr2@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr2>; + status = "okay"; + }; + + sec_jr3: jr3@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr3>; + status = "okay"; + }; + }; + + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x31800000 0 0x10000>; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = ; + wakeup-source; + }; + + wdog: wdog { + compatible = "fsl,imx8-wdt"; + }; }; &A35_0 { + operating-points = < + /* kHz uV*/ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 900000 0 + >; clocks = <&clk IMX8QXP_A35_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; }; /delete-node/ &A35_2; diff --git a/arch/arm/dts/fsl-imx8dxl-ddr3-evk-u-boot.dtsi b/arch/arm/dts/fsl-imx8dxl-ddr3-evk-u-boot.dtsi new file mode 100644 index 00000000000..bb50353eaa9 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-ddr3-evk-u-boot.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + gpio8 = &pca6416_a; + gpio9 = &pca6416_b; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8dxl-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +®_usb_otg1_vbus { + u-boot,dm-spl; +}; + +®_usb_otg2_vbus { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8dxl-evk} { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_usbotg1 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg1_phy { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&eqos { + compatible = "fsl,imx-eqos"; + phy-mode = "rgmii-id"; +}; + +&usbphy2 { + u-boot,dm-spl; +}; + +&usbotg2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8dxl-ddr3-evk.dts b/arch/arm/dts/fsl-imx8dxl-ddr3-evk.dts new file mode 100644 index 00000000000..825c45f81e4 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-ddr3-evk.dts @@ -0,0 +1,420 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "fsl-imx8dxl.dtsi" + +/ { + model = "NXP i.MX8DXL DDR3 EVK Board"; + compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + u-boot,off-on-delay-us = <12000>; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8dxl-evk { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021 + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + SC_P_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + SC_P_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + SC_P_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + SC_P_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + SC_P_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + SC_P_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + SC_P_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + SC_P_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + SC_P_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + SC_P_EMMC0_CMD_CONN_NAND_DQS 0x0e00004c + + SC_P_USDHC1_RESET_B_CONN_NAND_WE_B 0x0e00004c + SC_P_USDHC1_WP_CONN_NAND_ALE 0x0e00004c + SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + SC_P_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + SC_P_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + SC_P_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000021 /* RESET_B */ + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + }; +}; + +&A35_0 { + u-boot,dm-pre-reloc; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + i2cswitch@70 { + compatible = "nxp,pca9646"; + reg = <0x70>; + u-boot,i2c-offset-len = <0>; + #address-cells = <1>; + #size-cells = <0>; + + v2x_i2c2: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + audio_codec1_i2c2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + audio_codec2_i2c2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + audio_codec3_i2c2: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + audio_codec0_i2c2: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; + + pca6416_a: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_b: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "disabled"; + + i2cswitch@70 { + compatible = "nxp,pca9646"; + reg = <0x70>; + u-boot,i2c-offset-len = <0>; + #address-cells = <1>; + #size-cells = <0>; + + alt_audio_codec1_i2c3: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + alt_audio_codec2_i2c3: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + alt_audio_codec3_i2c3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + usb1_i2c3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + usb2_i2c3: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; + + pca6416_c: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + max-frequency = <100000000>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + phy-reset-gpios = <&pca6416_a 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&pcieb{ + ext_osc = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts b/arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts new file mode 100644 index 00000000000..8ff96eeec05 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-evk-lcdif.dts @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020 NXP. + */ + +#include "fsl-imx8dxl-evk.dts" +#include "fsl-imx8dxl-evk-u-boot.dtsi" + +&eqos { + status = "disabled"; +}; + +&lpspi3 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_lcdif: lcdifgrp { + fsl,pins = < + SC_P_SPI3_SCK_ADMA_LCDIF_D00 0x00000023 + SC_P_SPI3_SDO_ADMA_LCDIF_D01 0x00000023 + SC_P_SPI3_SDI_ADMA_LCDIF_D02 0x00000023 + SC_P_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 0x00000023 + SC_P_UART1_TX_ADMA_LCDIF_D04 0x00000023 + SC_P_UART1_RX_ADMA_LCDIF_D05 0x00000023 + SC_P_UART1_RTS_B_ADMA_LCDIF_D06 0x00000023 + SC_P_UART1_CTS_B_ADMA_LCDIF_D07 0x00000023 + SC_P_SPI0_SCK_ADMA_LCDIF_D08 0x00000023 + SC_P_SPI0_SDI_ADMA_LCDIF_D09 0x00000023 + SC_P_SPI0_SDO_ADMA_LCDIF_D10 0x00000023 + SC_P_SPI0_CS1_ADMA_LCDIF_D11 0x00000023 + SC_P_SPI0_CS0_ADMA_LCDIF_D12 0x00000023 + SC_P_ADC_IN1_ADMA_LCDIF_D13 0x00200003 + SC_P_ADC_IN0_ADMA_LCDIF_D14 0x00200003 + SC_P_ADC_IN3_ADMA_LCDIF_D15 0x00200003 + SC_P_ADC_IN2_ADMA_LCDIF_D16 0x00200003 + SC_P_ADC_IN5_ADMA_LCDIF_D17 0x00200003 + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000023 + SC_P_SPI3_CS1_ADMA_LCDIF_RESET 0x00000023 + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000023 + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000023 + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000023 + >; + }; +}; + +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "okay"; + + assigned-clocks = <&clk IMX8QXP_LCD_SEL>, + <&clk IMX8QXP_LCD_PXL_SEL>, + <&clk IMX8QXP_ELCDIF_PLL_DIV>; + assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>, + <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; + assigned-clock-rates = <0>, <0>, <711000000>; + + display = <&display0>; + + display0: display@0 { + bits-per-pixel = <18>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <71100000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <70>; + hback-porch = <80>; + hsync-len = <10>; + vback-porch = <10>; + vfront-porch = <10>; + vsync-len = <3>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi b/arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi new file mode 100644 index 00000000000..af5a2db96d7 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-evk-u-boot.dtsi @@ -0,0 +1,230 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + gpio8 = &pca6416_a; + gpio9 = &pca6416_b; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8dxl-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +®_usb_otg1_vbus { + u-boot,dm-spl; +}; + +®_usb_otg2_vbus { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8dxl-evk} { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_usbotg1 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg1_phy { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; + phy-mode = "rgmii-id"; +}; + +&fec1 { + phy-mode = "rgmii-id"; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&usbphy2 { + u-boot,dm-spl; +}; + +&usbotg2 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8dxl-evk.dts b/arch/arm/dts/fsl-imx8dxl-evk.dts new file mode 100644 index 00000000000..073a4df1ba5 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-evk.dts @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include "fsl-imx8dxl.dtsi" + +/ { + model = "NXP i.MX8DXL EVK Board"; + compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_fec1: regfec1 { + compatible = "regulator-fixed"; + regulator-name = "fec1_supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&pca6416_a 11 GPIO_ACTIVE_LOW>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + u-boot,off-on-delay-us = <12000>; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca6416_a 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + + }; + + pcie_clk_sel_ext: fixedregulator@101 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <0000000>; + regulator-max-microvolt = <3300000>; + regulator-name = "clk_ext_sel"; + gpio = <&pca6416_a 10 GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; + + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8dxl-evk { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021 + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + SC_P_ENET0_MDC_CONN_EQOS_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020 + SC_P_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_SPI1_SDO_ADMA_I2C2_SCL 0x06000021 + SC_P_SPI1_SCK_ADMA_I2C2_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + SC_P_SPI1_SDI_ADMA_I2C3_SCL 0x06000021 + SC_P_SPI1_CS0_ADMA_I2C3_SDA 0x06000021 + >; + }; + + pinctrl_lpspi3: lpspi3grp { + fsl,pins = < + SC_P_SPI3_SCK_ADMA_SPI3_SCK 0x0600004c + SC_P_SPI3_SDO_ADMA_SPI3_SDO 0x0600004c + SC_P_SPI3_SDI_ADMA_SPI3_SDI 0x0600004c + SC_P_SPI3_CS1_ADMA_SPI3_CS1 0x0600004c + SC_P_SPI3_CS0_LSIO_GPIO0_IO16 0x21 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000021 /* RESET_B */ + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */ + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + }; +}; + +&A35_0 { + u-boot,dm-pre-reloc; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&lpspi3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi3>; + cs-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, <0>, <0>, <0>; + spi-max-frequency = <1000000>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + status = "okay"; + + i2cswitch@70 { + compatible = "nxp,pca9646"; + reg = <0x70>; + u-boot,i2c-offset-len = <0>; + #address-cells = <1>; + #size-cells = <0>; + + v2x_i2c2: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + audio_codec1_i2c2: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + audio_codec2_i2c2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + audio_codec3_i2c2: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + m2_i2c2: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + pcie_i2c2: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + + lcd_i2c2: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + }; + + pca6416_a: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca6416_b: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "disabled"; + + i2cswitch@70 { + compatible = "nxp,pca9646"; + reg = <0x70>; + u-boot,i2c-offset-len = <0>; + #address-cells = <1>; + #size-cells = <0>; + + alt_audio_codec1_i2c3: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + alt_audio_codec2_i2c3: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + + alt_audio_codec3_i2c3: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + + usb1_i2c3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + usb2_i2c3: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + }; + + pca6416_c: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + max-frequency = <100000000>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + phy-reset-gpios = <&pca6416_a 2 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + }; +}; + +&pcieb{ + ext_osc = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + power-on-gpio = <&pca6416_a 12 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on = <&epdev_on>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + phy-supply = <®_fec1>; + status = "disable"; + phy-reset-gpios = <&pca6416_a 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + /* mdio/mdc pins conflict with eqos, so should be shared mii bus + * fec1 pins has conflict with usdhc2 + * for bringup, only enable one mac + */ + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; /* ensure your net card phy id: 0x1 */ + }; + + }; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8dxl-phantom-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8dxl-phantom-mek-u-boot.dtsi new file mode 100644 index 00000000000..a77dbaa6a43 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-phantom-mek-u-boot.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/ { + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8qx-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qxp-mek} { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_caam { + u-boot,dm-spl; +}; + +&pd_caam_jr1 { + u-boot,dm-spl; +}; + +&pd_caam_jr2 { + u-boot,dm-spl; +}; + +&pd_caam_jr3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&fec2 { + phy-mode = "rgmii-id"; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8dxl-phantom-mek.dts b/arch/arm/dts/fsl-imx8dxl-phantom-mek.dts new file mode 100644 index 00000000000..74810b13e0f --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl-phantom-mek.dts @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "NXP i.MX8DXL PHANTOM MEK"; + compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&gpio4 18 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qxp-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x00000021 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x06000020 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x00000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + >; + }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x07800000 + >; + }; + }; +}; + +&A35_0 { + u-boot,dm-pre-reloc; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; + + phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on = <&epdev_on>; + ext_osc = <1>; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8dxl.dtsi b/arch/arm/dts/fsl-imx8dxl.dtsi new file mode 100644 index 00000000000..cef27a79895 --- /dev/null +++ b/arch/arm/dts/fsl-imx8dxl.dtsi @@ -0,0 +1,1938 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include "fsl-imx8-ca35.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "NXP i.MX8DXL"; + compatible = "fsl,imx8dxl"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + ethernet0 = &fec1; + ethernet1 = &eqos; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + spi0 = &flexspi0; + spi1 = &lpspi3; + usb0 = &usbotg1; + usbphy0 = &usbphy1; + usb1 = &usbotg2; + usbphy1 = &usbphy2; + pci0 = &pcieb; + }; + + cpus { + idle-states { + entry-method = "psci"; + + CPU_SLEEP: cpu-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x10000>; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <500>; + min-residency-us = <5000>; + }; + + CLUSTER_SLEEP: cluster-sleep { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x10033>; + local-timer-stop; + entry-latency-us = <500>; + exit-latency-us = <2300>; + min-residency-us = <14000>; + }; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; + }; + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + mu8: mu@5d230000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d230000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu8a>; + status = "okay"; + }; + + mu: mu@5d1c0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1c0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + status = "okay"; + + clk: clk { + compatible = "fsl,imx8qxp-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qxp-iomuxc"; + }; + }; + + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-dsp"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = ; + fsl,dsp_ap_mu_id = <13>; + status = "okay"; + }; + + rtc: rtc { + compatible = "fsl,imx-sc-rtc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; + interrupt-parent = <&gic>; + }; + + imx8dxl-pm { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio: PD_LSIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio_pwm0: PD_LSIO_PWM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm1: PD_LSIO_PWM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm2: PD_LSIO_PWM_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm3: PD_LSIO_PWM_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm4: PD_LSIO_PWM_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm5: PD_LSIO_PWM_5 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm6: PD_LSIO_PWM_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_pwm7: PD_LSIO_PWM_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_kpp: PD_LSIO_KPP { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio0: PD_LSIO_GPIO_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio1: PD_LSIO_GPIO_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio2: PD_LSIO_GPIO_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio3: PD_LSIO_GPIO_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio4: PD_LSIO_GPIO_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio5: PD_LSIO_GPIO_5{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio6:PD_LSIO_GPIO_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio7: PD_LSIO_GPIO_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt0: PD_LSIO_GPT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt1: PD_LSIO_GPT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt2: PD_LSIO_GPT_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt3: PD_LSIO_GPT_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpt4: PD_LSIO_GPT_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi0: PD_LSIO_FSPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi1: PD_LSIO_FSPI_1{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu5a: PD_LSIO_MU5A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu8a: PD_LSIO_MU8A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + }; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_usbotg0: PD_CONN_USB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <169>; + + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usbotg0>; + wakeup-irq = <169>; + }; + + }; + pd_conn_usbotg1: PD_CONN_USB_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <166>; + + pd_conn_usbotg1_phy: PD_CONN_USB_1_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usbotg1>; + wakeup-irq = <166>; + }; + }; + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch1: PD_CONN_SDHC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch2: PD_CONN_SDHC_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet0: PD_CONN_ENET_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <258>; + }; + pd_conn_enet1: PD_CONN_ENET_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + fsl,wakeup_irq = <262>; + }; + pd_conn_nand: PD_CONN_NAND { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + }; + + pd_audio: PD_AUDIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll0: PD_AUD_AUDIO_PLL_0 { + reg = ; + power-domains =<&pd_audio>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_pll1: PD_AUD_AUDIO_PLL_1 { + reg = ; + power-domains =<&pd_audio_pll0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk0: PD_AUD_AUDIO_CLK_0 { + reg = ; + power-domains =<&pd_audio_pll1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_audio_clk1: PD_AUD_AUDIO_CLK_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan0: PD_ASRC_0_RXA { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan1: PD_ASRC_0_RXB { + reg = ; + power-domains =<&pd_dma0_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan2: PD_ASRC_0_RXC { + reg = ; + power-domains =<&pd_dma0_chan1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan3: PD_ASRC_0_TXA { + reg = ; + power-domains =<&pd_dma0_chan2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan4: PD_ASRC_0_TXB { + reg = ; + power-domains =<&pd_dma0_chan3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan5: PD_ASRC_0_TXC { + reg = ; + power-domains =<&pd_dma0_chan4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_asrc0:PD_AUD_ASRC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan5>; + }; + }; + }; + }; + }; + }; + }; + + pd_dma0_chan8: PD_SPDIF_0_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan9: PD_SPDIF_0_TX { + reg = ; + power-domains =<&pd_dma0_chan8>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_spdif0: PD_AUD_SPDIF_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan9>; + + }; + }; + }; + pd_dma0_chan12: PD_SAI_0_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan13: PD_SAI_0_TX { + reg = ; + power-domains =<&pd_dma0_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai0:PD_AUD_SAI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan13>; + }; + }; + + }; + pd_dma0_chan14: PD_SAI_1_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan15: PD_SAI_1_TX { + reg = ; + power-domains =<&pd_dma0_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai1: PD_AUD_SAI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan15>; + }; + }; + }; + pd_dma0_chan16: PD_SAI_2_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + pd_sai2: PD_AUD_SAI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan16>; + }; + }; + pd_dma0_chan17: PD_SAI_3_RX { + reg = ; + power-domains =<&pd_audio_clk1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sai3: PD_AUD_SAI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dma0_chan17>; + }; + }; + pd_gpt5: PD_AUD_GPT_5 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt6: PD_AUD_GPT_6 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt7: PD_AUD_GPT_7 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_gpt8: PD_AUD_GPT_8 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mqs0: PD_AUD_MQS_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out0: PD_AUD_MCLK_OUT_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + pd_mclk_out1: PD_AUD_MCLK_OUT_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_audio_clk1>; + }; + }; + }; + }; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_elcdif_pll: PD_DMA_ELCDIF_PLL { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lcd0: PD_DMA_LCD_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_elcdif_pll>; + }; + }; + pd_dma_flexcan0: PD_DMA_CAN_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <235>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_flexcan1: PD_DMA_CAN_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_flexcan0>; + wakeup-irq = <236>; + }; + + pd_dma_flexcan2: PD_DMA_CAN_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_flexcan0>; + wakeup-irq = <237>; + }; + }; + + pd_dma_ftm0: PD_DMA_FTM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_ftm1: PD_DMA_FTM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_adc0: PD_DMA_ADC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c0: PD_DMA_I2C_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c1: PD_DMA_I2C_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c2:PD_DMA_I2C_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c3: PD_DMA_I2C_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart0: PD_DMA_UART0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <345>; + }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <346>; + + pd_dma2_chan10: PD_UART1_RX { + reg = ; + power-domains =<&pd_dma_lpuart1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan11: PD_UART1_TX { + reg = ; + power-domains =<&pd_dma2_chan10>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <347>; + + pd_dma2_chan12: PD_UART2_RX { + reg = ; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma2_chan13: PD_UART2_TX { + reg = ; + power-domains =<&pd_dma2_chan12>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <348>; + + pd_dma3_chan14: PD_UART3_RX { + reg = ; + power-domains =<&pd_dma_lpuart3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma3_chan15: PD_UART3_TX { + reg = ; + power-domains =<&pd_dma3_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpspi0: PD_DMA_SPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi1: PD_DMA_SPI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi2: PD_DMA_SPI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi3: PD_DMA_SPI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_pwm0: PD_DMA_PWM_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + }; + + pd_hsio: hsio-power-domain { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hsio_gpio: PD_HSIO_GPIO { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes1: PD_HSIO_SERDES_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio_gpio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie: PD_HSIO_PCIE_B { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_serdes1>; + }; + }; + }; + }; + + pd_cm40: PD_CM40 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_cm40_i2c: PD_CM40_I2C { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + + pd_cm40_intmux: PD_CM40_INTMUX { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_cm40>; + }; + }; + + pd_caam: PD_CAAM { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_caam_jr1: PD_CAAM_JR1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr2: PD_CAAM_JR2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr3: PD_CAAM_JR3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + }; + }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qxp-sc-tsens"; + u-boot,dm-pre-reloc; + /* number of the temp sensor on the chip */ + tsens-num = <2>; + #thermal-sensor-cells = <1>; + }; + + thermal_zones: thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 1>; + status = "disabled"; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + intmux_cm40: intmux@37400000 { + compatible = "nxp,imx-intmux"; + reg = <0x0 0x37400000 0x0 0x1000>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QXP_CM40_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_cm40_intmux>; + status = "disabled"; + }; + + i2c0_cm40: i2c@37230000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x37230000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intmux_cm40>; + clocks = <&clk IMX8QXP_CM40_I2C_CLK>, + <&clk IMX8QXP_CM40_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_CM40_I2C_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_cm40_i2c>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + adma_lcdif: lcdif@5a180000 { + compatible = "fsl,imx8qxp-lcdif", "fsl,imx28-lcdif"; + reg = <0x0 0x5a180000 0x0 0x10000>; + clocks = <&clk IMX8QXP_LCD_DIV>, + <&clk IMX8QXP_LCD_PXL_DIV>, + <&clk IMX8QXP_LCD_IPG_CLK>; + clock-names = "pix", "disp_axi", "axi"; + assigned-clocks = <&clk IMX8QXP_LCD_SEL>, + <&clk IMX8QXP_LCD_PXL_SEL>, + <&clk IMX8QXP_ELCDIF_PLL_DIV>; + assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL_DIV>, + <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; + assigned-clock-rates = <0>, <0>, <804000000>; + interrupts = ; + power-domains = <&pd_dma_lcd0>; + status = "disabled"; + }; + + pwm_adma_lcdif: pwm@5a190000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5a190000 0 0x1000>; + clocks = <&clk IMX8QXP_PWM_IPG_CLK>, + <&clk IMX8QXP_PWM_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_PWM_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_dma_pwm0>; + status = "disabled"; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_5: i2c-rpbus-5 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_12: i2c-rpbus-12 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_13: i2c-rpbus-13 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_14: i2c-rpbus-14 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_15: i2c-rpbus-15 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + adc0: adc@5a880000 { + compatible = "fsl,imx8qxp-adc"; + reg = <0x0 0x5a880000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_ADC0_CLK>, + <&clk IMX8QXP_ADC0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_ADC0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_adc0>; + status = "disabled"; + }; + + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C0_CLK>, + <&clk IMX8QXP_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C1_CLK>, + <&clk IMX8QXP_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C2_CLK>, + <&clk IMX8QXP_I2C2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_I2C3_CLK>, + <&clk IMX8QXP_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b100000 0x0 0x1000>; + clocks = <&clk IMX8QXP_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg0_phy>; + }; + + usbphy2: usbphy@0x5b110000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b110000 0x0 0x1000>; + clocks = <&clk IMX8DXL_USB2_PHY2_IPG_CLK>; + power-domains = <&pd_conn_usbotg1_phy>; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0d0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg0>; + status = "disabled"; + }; + + usbotg2: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0e0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = ; + fsl,usbphy = <&usbphy2>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg1>; + status = "disabled"; + }; + + flexcan1: can@5a8d0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8d0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan0>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + flexcan2: can@5a8e0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8e0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&wu>; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan1>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + flexcan3: can@5a8f0000 { + compatible = "fsl,imx8qxp-flexcan", "fsl,imx8qm-flexcan"; + reg = <0x0 0x5a8f0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&wu>; + /* CAN0 clock and PD is shared among all CAN instances */ + clocks = <&clk IMX8QXP_CAN0_IPG_CLK>, + <&clk IMX8QXP_CAN0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_CAN0_CLK>; + assigned-clock-rates = <40000000>; + power-domains = <&pd_dma_flexcan2>; + /* SLSlice[4] */ + clk-src = <0>; + status = "disabled"; + }; + + dma_apbh: dma-apbh@5b810000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x0 0x5b810000 0x0 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8QXP_APBHDMA_CLK>; + power-domains = <&pd_conn_nand>; + }; + + gpmi: gpmi-nand@5b812000{ + compatible = "fsl,imx8qxp-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x5b812000 0x0 0x2000>, <0x0 0x5b814000 0x0 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>, + <&clk IMX8QXP_GPMI_APB_CLK>, + <&clk IMX8QXP_GPMI_BCH_CLK>, + <&clk IMX8QXP_GPMI_APB_BCH_CLK>, + <&clk IMX8QXP_APBHDMA_CLK>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", "gpmi_apb_bch", "gpmi_apbh_dma"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + power-domains = <&pd_conn_nand>; + assigned-clocks = <&clk IMX8QXP_GPMI_BCH_IO_CLK>; + assigned-clock-rates = <50000000>; + status = "disabled"; + }; + + wu: wu { + compatible = "fsl,imx8-wu"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + gpio0: gpio@5d080000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d080000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@5d090000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d090000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0a0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0b0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio3>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0c0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0d0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio5>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0e0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0f0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio7>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ddr_pmu0: ddr_pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c020000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + lpspi0: lpspi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a000000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI0_CLK>, + <&clk IMX8QXP_SPI0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi0>; + status = "disabled"; + }; + + lpspi1: lpspi@5a010000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a010000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI1_CLK>, + <&clk IMX8QXP_SPI1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi1>; + status = "disabled"; + }; + + lpspi2: lpspi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a020000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI2_CLK>, + <&clk IMX8QXP_SPI2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi2>; + status = "disabled"; + }; + + lpspi3: lpspi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a030000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QXP_SPI3_CLK>, + <&clk IMX8QXP_SPI3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_SPI3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpspi3>; + status = "disabled"; + }; + + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART0_CLK>, + <&clk IMX8QXP_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart0>; + status = "disabled"; + }; + + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART1_CLK>, + <&clk IMX8QXP_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma2_chan11>; + dma-names = "tx","rx"; + dmas = <&edma2 11 0 0>, + <&edma2 10 0 1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART2_CLK>, + <&clk IMX8QXP_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma2_chan13>; + dma-names = "tx","rx"; + dmas = <&edma2 13 0 0>, + <&edma2 12 0 1>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QXP_UART3_CLK>, + <&clk IMX8QXP_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QXP_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma3_chan15>; + dma-names = "tx","rx"; + dmas = <&edma2 15 0 0>, + <&edma2 14 0 1>; + status = "disabled"; + }; + + edma2: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a280000 0x0 0x10000>, /* channel8 UART0 rx */ + <0x0 0x5a290000 0x0 0x10000>, /* channel9 UART0 tx */ + <0x0 0x5a2a0000 0x0 0x10000>, /* channel10 UART1 rx */ + <0x0 0x5a2b0000 0x0 0x10000>, /* channel11 UART1 tx */ + <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART2 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART2 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART3 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART3 tx */ + #dma-cells = <3>; + dma-channels = <8>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx", + "edma2-chan10-rx", "edma2-chan11-tx", + "edma2-chan12-rx", "edma2-chan13-tx", + "edma2-chan14-rx", "edma2-chan15-tx"; + status = "okay"; + }; + + edma0: dma-controller@591F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>, + <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59350000 0x0 0x10000>, + <0x0 0x59370000 0x0 0x10000>; + #dma-cells = <3>; + shared-interrupt; + dma-channels = <16>; + interrupts = , /* asrc 0 */ + , + , + , + , + , + , /* spdif0 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + "edma0-chan21-tx", /* gpt0 */ + "edma0-chan23-rx"; /* gpt2 */ + status = "okay"; + }; + acm: acm@59e00000 { + compatible = "nxp,imx8qm-acm"; + reg = <0x0 0x59e00000 0x0 0x1D0000>; + status = "disabled"; + }; + + sai0: sai@59040000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59040000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_0_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 12 0 1>, <&edma0 13 0 0>; + status = "disabled"; + power-domains = <&pd_sai0>; + }; + + sai1: sai@59050000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59050000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_1_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_1_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&edma0 14 0 1>, <&edma0 15 0 0>; + status = "disabled"; + power-domains = <&pd_sai1>; + }; + + sai2: sai@59060000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59060000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_2_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_2_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 16 0 1>; + status = "disabled"; + power-domains = <&pd_sai2>; + }; + + sai3: sai@59070000 { + compatible = "fsl,imx8qm-sai"; + reg = <0x0 0x59070000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_AUD_SAI_3_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_SAI_3_MCLK>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx"; + dmas = <&edma0 17 0 1>; + status = "disabled"; + power-domains = <&pd_sai3>; + }; + + asrc0: asrc@59000000 { + compatible = "fsl,imx8qm-asrc0"; + reg = <0x0 0x59000000 0x0 0x10000>; + interrupts = , + ; + clocks = <&clk IMX8QXP_AUD_ASRC_0_IPG>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>, + <&clk IMX8QXP_ACM_AUD_CLK0_SEL>, + <&clk IMX8QXP_ACM_AUD_CLK1_SEL>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>, + <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "ipg", "mem", + "asrck_0", "asrck_1", "asrck_2", "asrck_3", + "asrck_4", "asrck_5", "asrck_6", "asrck_7", + "asrck_8", "asrck_9", "asrck_a", "asrck_b", + "asrck_c", "asrck_d", "asrck_e", "asrck_f", + "spba"; + dmas = <&edma0 0 0 0>, <&edma0 1 0 0>, <&edma0 2 0 0>, + <&edma0 3 0 1>, <&edma0 4 0 1>, <&edma0 5 0 1>; + dma-names = "rxa", "rxb", "rxc", + "txa", "txb", "txc"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + power-domains = <&pd_asrc0>; + status = "disabled"; + }; + + mqs: mqs@59850000 { + compatible = "fsl,imx8qm-mqs"; + reg = <0x0 0x59850000 0x0 0x10000>; + clocks = <&clk IMX8QXP_AUD_MQS_IPG>, + <&clk IMX8QXP_AUD_MQS_HMCLK>; + clock-names = "core", "mclk"; + power-domains = <&pd_mqs0>; + status = "disabled"; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC0_IPG_CLK>, + <&clk IMX8QXP_SDHC0_CLK>, + <&clk IMX8QXP_SDHC0_AHB_CLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC0_SEL>, <&clk IMX8QXP_SDHC0_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; + assigned-clock-rates = <0>, <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc2: usdhc@5b020000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b020000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC1_IPG_CLK>, + <&clk IMX8QXP_SDHC1_CLK>, + <&clk IMX8QXP_SDHC1_AHB_CLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC1_SEL>, <&clk IMX8QXP_SDHC1_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; + assigned-clock-rates = <0>, <200000000>; + power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "disabled"; + }; + + usdhc3: usdhc@5b030000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b030000 0x0 0x10000>; + clocks = <&clk IMX8QXP_SDHC2_IPG_CLK>, + <&clk IMX8QXP_SDHC2_CLK>, + <&clk IMX8QXP_SDHC2_AHB_CLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QXP_SDHC2_SEL>, <&clk IMX8QXP_SDHC2_DIV>; + assigned-clock-parents = <&clk IMX8QXP_CONN_PLL1_CLK>; + assigned-clock-rates = <0>, <200000000>; + power-domains = <&pd_conn_sdch2>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx8qm-fec"; + reg = <0x0 0x5b040000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, <&clk IMX8QXP_ENET0_AHB_CLK>, <&clk IMX8QXP_ENET0_RGMII_TX_CLK>, + <&clk IMX8QXP_ENET0_PTP_CLK>, <&clk IMX8QXP_ENET0_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QXP_ENET0_ROOT_DIV>, + <&clk IMX8QXP_ENET0_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; + power-domains = <&pd_conn_enet0>; + status = "disabled"; + }; + + eqos: ethernet@5b050000 { + compatible = "fsl,imx-eqos"; + reg = <0x0 0x5b050000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = , + ; + clocks = <&clk IMX8DXL_EQOS_ACLK>, <&clk IMX8DXL_EQOS_CSR_CLK>, <&clk IMX8DXL_EQOS_CLK>, + <&clk IMX8DXL_EQOS_PTP_CLK>; + clock-names = "aclk", "csr", "tx_clk", "ptp"; + assigned-clocks = <&clk IMX8QXP_ENET1_ROOT_DIV>; + assigned-clock-rates = <125000000>; + power-domains = <&pd_conn_enet1>; + status = "disabled"; + }; + + gpt0: gpt0@5d140000 { + compatible = "fsl,imx8qxp-gpt"; + reg = <0x0 0x5d140000 0x0 0x4000>; + interrupts = ; + clocks = <&clk IMX8QXP_CLK_DUMMY>, <&clk IMX8QXP_GPT_3M>; + clock-names = "ipg", "per"; + power-domains = <&pd_lsio_gpt0>; + }; + + spdif0: spdif@59020000 { + compatible = "fsl,imx8qm-spdif"; + reg = <0x0 0x59020000 0x0 0x10000>; + interrupts = , /* rx */ + ; /* tx */ + clocks = <&clk IMX8QXP_AUD_SPDIF_0_GCLKW>, /* core */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx0 */ + <&clk IMX8QXP_AUD_SPDIF_0_TX_CLK>, /* rxtx1 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx2 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx3 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx4 */ + <&clk IMX8QXP_IPG_AUD_CLK_ROOT>, /* rxtx5 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx6 */ + <&clk IMX8QXP_CLK_DUMMY>, /* rxtx7 */ + <&clk IMX8QXP_CLK_DUMMY>; /* spba */ + clock-names = "core", "rxtx0", + "rxtx1", "rxtx2", + "rxtx3", "rxtx4", + "rxtx5", "rxtx6", + "rxtx7", "spba"; + dmas = <&edma0 8 0 5>, <&edma0 9 0 4>; + dma-names = "rx", "tx"; + power-domains = <&pd_spdif0>; + status = "disabled"; + }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8dxl-fspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, <0x0 0x08000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8QXP_LSIO_FSPI0_CLK>, + <&clk IMX8QXP_LSIO_FSPI0_CLK>; + assigned-clocks = <&clk IMX8QXP_LSIO_FSPI0_DIV>; + assigned-clock-rates = <29000000>; + clock-names = "fspi", "fspi_en"; + power-domains = <&pd_lsio_flexspi0>; + status = "disabled"; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + hsio: hsio@5f080000 { + compatible = "fsl,imx8qm-hsio", "syscon"; + reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ + }; + + ocotp: ocotp { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx8qxp-ocotp", "syscon"; + }; + + pcieb: pcie@0x5f010000 { + /* + * pcieb phyx1 lane1 in default, adjust it refer to the + * exact hw design. + */ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg*/ + <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK>, + <&clk IMX8QXP_HSIO_PCIE_SLV_AXI_CLK>, + <&clk IMX8QXP_HSIO_PHY_X1_PCLK>, + <&clk IMX8QXP_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QXP_HSIO_PCIE_DBI_AXI_CLK>, + <&clk IMX8QXP_HSIO_PHY_X1_PER_CLK>, + <&clk IMX8QXP_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi", + "phy_per", "misc_per"; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + power-domains = <&pd_pcie>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + hsio = <&hsio>; + ctrl-id = <1>; /* pcieb */ + cpu-base-addr = <0x80000000>; + status = "disabled"; + }; + + imx_ion { + compatible = "fsl,mxc-ion"; + fsl,heap-id = <0>; + }; + + imx_rpmsg: imx_rpmsg { + compatible = "fsl,rpmsg-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mu_rpmsg: mu_rpmsg@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x0 0x5d200000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QXP_LSIO_MU5A_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lsio_mu5a>; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + status = "disabled"; + mub-partition = <3>; + power-domains = <&pd_lsio_mu5a>; + memory-region = <&rpmsg_dma_reserved>; + }; + }; + + crypto: caam@0x31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0 0x31400000 0 0x400000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x31400000 0x400000>; + fsl,first-jr-index = <2>; + fsl,sec-era = <9>; + + sec_jr1: jr1@0x20000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr1>; + status = "disabled"; + }; + + sec_jr2: jr2@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr2>; + status = "okay"; + }; + + sec_jr3: jr3@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr3>; + status = "okay"; + }; + }; + + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x31800000 0 0x10000>; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = ; + wakeup-source; + }; + + wdog: wdog { + compatible = "fsl,imx8-wdt"; + }; +}; + +&A35_0 { + operating-points = < + /* kHz uV*/ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 900000 0 + >; + clocks = <&clk IMX8QXP_A35_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; +}; diff --git a/arch/arm/dts/fsl-imx8dxp.dtsi b/arch/arm/dts/fsl-imx8dxp.dtsi index cc688f44695..ebadb02e7d4 100644 --- a/arch/arm/dts/fsl-imx8dxp.dtsi +++ b/arch/arm/dts/fsl-imx8dxp.dtsi @@ -6,6 +6,23 @@ #include "fsl-imx8dx.dtsi" / { - model = "Freescale i.MX8DXP"; + model = "NXP i.MX8DXP"; compatible = "fsl,imx8dxp", "fsl,imx8qxp"; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + clock-names = "vpu_clk"; + assigned-clocks = <&clk IMX8QXP_VPU_DEC_CLK>; + power-domains = <&pd_vpu_dec>; + status = "disabled"; + }; +}; + +&gpu_3d0 { + assigned-clock-rates = <700000000>, <850000000>; }; diff --git a/arch/arm/dts/fsl-imx8qm-cockpit-a53.dtsi b/arch/arm/dts/fsl-imx8qm-cockpit-a53.dtsi new file mode 100644 index 00000000000..26bb6ad7cc1 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-cockpit-a53.dtsi @@ -0,0 +1,351 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "fsl-imx8-ca53.dtsi" +#include "fsl-imx8-ca72.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + dpu0 = &dpu1; + ethernet0 = &fec1; + dsiphy0 = &mipi_dsi_phy1; + mipidsi0 = &mipi_dsi1; + ldb0 = &ldb1; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial3 = &lpuart3; + serial4 = &lpuart4; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + usb0 = &usbotg1; + usbphy0 = &usbphy1; + usb1 = &usbotg3; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c6 = &i2c1_lvds0; + spi0 = &flexspi0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0x80000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x52000000 0 0x2000>, /* GICC */ + <0x0 0x52010000 0 0x1000>, /* GICH */ + <0x0 0x52020000 0 0x20000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + mu8: mu@5d230000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d230000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu8a>; + status = "okay"; + }; + + mu9: mu@5d240000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d240000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu9a>; + status = "okay"; + }; + + mu: mu@5d1c0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1c0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + #mbox-cells = <4>; + status = "okay"; + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + }; + + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-dsp"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = ; + fsl,dsp_ap_mu_id = <13>; + status = "okay"; + }; + + mu_m0: mu_m0@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0"; + reg = <0x0 0x2d000000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <16>; + status = "disabled"; + }; + + mu1_m0: mu1_m0@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x0 0x2d020000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + status = "disabled"; + }; + + mu2_m0: mu2_m0@2d040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x0 0x2d040000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + status = "disabled"; + }; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + reg-csr = <0x2d080000>; + status = "disabled"; + }; + + vpu_encoder: vpu_encoder@2d000000 { + compatible = "nxp,imx8qm-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ + reg-names = "vpu_regs"; + reg-rpc-system = <0x40000000>; + + resolution-max = <1920 1080>; + fps-max = <120>; + status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10a0000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; + interrupt-parent = <&gic>; + }; + + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + }; + + cci: cci@52090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x52090000 0 0x1000>; + ranges = <0 0 0x52090000 0x10000>; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1", + "arm,cci-400-pmu"; + reg = <0x9000 0x4000>; + interrupts = , + , + , + , + , + ; + interrupt-parent = <&gic>; + }; + }; + + #include "fsl-imx8qm-device.dtsi" +}; + +&A53_0 { + operating-points = < + /* kHz uV */ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 1104000 0 + 900000 0 + 600000 0 + >; + clocks = <&clk IMX8QM_A53_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; + /delete-property/ cpu-idle-states; +}; + +&A72_0 { + operating-points = < + /* kHz uV */ + /* voltage is maintained by SCFW, so no need here */ + 1596000 0 + 1296000 0 + 1056000 0 + 600000 0 + >; + clocks = <&clk IMX8QM_A72_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; + /delete-property/ cpu-idle-states; +}; + +&A53_1 { + /delete-property/ cpu-idle-states; +}; + +&A53_2 { + /delete-property/ cpu-idle-states; +}; + +&A53_3 { + /delete-property/ cpu-idle-states; +}; + +&A72_1 { + /delete-property/ cpu-idle-states; +}; diff --git a/arch/arm/dts/fsl-imx8qm-cockpit-a72.dtsi b/arch/arm/dts/fsl-imx8qm-cockpit-a72.dtsi new file mode 100644 index 00000000000..3da1f464f5f --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-cockpit-a72.dtsi @@ -0,0 +1,343 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "fsl-imx8-ca53.dtsi" +#include "fsl-imx8-ca72.dtsi" +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + compatible = "fsl,imx8qm"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + dpu1 = &dpu2; + ethernet1 = &fec2; + dsiphy1 = &mipi_dsi_phy2; + mipidsi1 = &mipi_dsi2; + ldb1 = &ldb2; + serial2 = &lpuart2; + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + mmc0 = &usdhc1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c8 = &i2c1_lvds1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x00000000 0xc0000000 0 0x40000000>; + /* DRAM space - 1, size : 1 GB DRAM */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0xd6000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + + gic: interrupt-controller@51a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ + <0x0 0x51b00000 0 0xC0000>, /* GICR */ + <0x0 0x52000000 0 0x2000>, /* GICC */ + <0x0 0x52010000 0 0x1000>, /* GICH */ + <0x0 0x52020000 0 0x20000>; /* GICV */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + + mu8: mu@5d230000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d230000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu8a>; + status = "disabled"; + }; + + mu9: mu@5d240000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d240000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu9a>; + status = "disabled"; + }; + + mu: mu@5d1d0000 { + compatible = "fsl,imx8-mu"; + reg = <0x0 0x5d1d0000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + #mbox-cells = <4>; + status = "okay"; + + clk: clk { + compatible = "fsl,imx8qm-clk"; + #clock-cells = <1>; + }; + + iomuxc: iomuxc { + compatible = "fsl,imx8qm-iomuxc"; + }; + }; + + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-dsp"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = ; + fsl,dsp_ap_mu_id = <13>; + status = "disabled"; + }; + + mu_m0: mu_m0@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0"; + reg = <0x0 0x2d000000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <16>; + status = "okay"; + }; + + mu1_m0: mu1_m0@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x0 0x2d020000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + status = "okay"; + }; + + mu2_m0: mu2_m0@2d040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x0 0x2d040000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + status = "okay"; + }; + + vpu_decoder: vpu_decoder@2c000000 { + compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg = <0x0 0x2c000000 0x0 0x1000000>; + reg-names = "vpu_regs"; + reg-csr = <0x2d080000>; + status = "disabled"; + }; + + vpu_encoder: vpu_encoder@2d000000 { + compatible = "nxp,imx8qm-b0-vpuenc"; + #address-cells = <1>; + #size-cells = <1>; + + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ + <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ + reg-names = "vpu_regs"; + reg-rpc-system = <0x40000000>; + + resolution-max = <1920 1080>; + fps-max = <120>; + status = "disabled"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1090000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + core1@1040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x1040000 0x20000>; + reg-csr = <0x10a0000 0x10000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; + interrupt-parent = <&gic>; + }; + + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; + interrupt-parent = <&gic>; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; + }; + + cci: cci@52090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x52090000 0 0x1000>; + ranges = <0 0 0x52090000 0x10000>; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1", + "arm,cci-400-pmu"; + reg = <0x9000 0x4000>; + interrupts = , + , + , + , + , + ; + interrupt-parent = <&gic>; + }; + }; + + #include "fsl-imx8qm-device.dtsi" +}; + +&A53_0 { + operating-points = < + /* kHz uV */ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 1104000 0 + 900000 0 + 600000 0 + >; + clocks = <&clk IMX8QM_A53_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; + /delete-property/ cpu-idle-states; +}; + +&A72_0 { + operating-points = < + /* kHz uV */ + /* voltage is maintained by SCFW, so no need here */ + 1596000 0 + 1296000 0 + 1056000 0 + 600000 0 + >; + clocks = <&clk IMX8QM_A72_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; + /delete-property/ cpu-idle-states; +}; + + +&A53_1 { + /delete-property/ cpu-idle-states; +}; + +&A53_2 { + /delete-property/ cpu-idle-states; +}; + +&A53_3 { + /delete-property/ cpu-idle-states; +}; + +&A72_1 { + /delete-property/ cpu-idle-states; +}; diff --git a/arch/arm/dts/fsl-imx8qm-ddr4-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-ddr4-val-u-boot.dtsi new file mode 100644 index 00000000000..a0a8c7d6f5a --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-ddr4-val-u-boot.dtsi @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8qm-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qm-val} { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-spl; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&wu { + u-boot,dm-spl; +}; + +&fec1 { + phy-mode = "rgmii-id"; +}; + +&fec2 { + phy-mode = "rgmii-id"; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/fsl-imx8qm-ddr4-val.dts b/arch/arm/dts/fsl-imx8qm-ddr4-val.dts new file mode 100644 index 00000000000..dfcf660f326 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-ddr4-val.dts @@ -0,0 +1,423 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + * + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "NXP i.MX8QM DDR4 VAL"; + compatible = "fsl,imx8qm-val", "fsl,imx8qm"; + + aliases { + gpio8 = &pca9557_a; + gpio9 = &pca9557_b; + gpio10 = &pca9557_c; + gpio11 = &pca9557_d; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qm-val { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x06000021 + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x06000021 + SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x06000021 + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x06000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_RESET_B_CONN_USDHC2_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000020 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000020 + >; + }; + + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0x06000020 + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x06000020 + /* + * Change the default alt function from SCL/SDA to others, + * to avoid select input conflict with GPT0 + */ + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0700004c + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0700004c + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0700004c + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0700004c + >; + }; + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c + SC_P_SPI0_CS1_DMA_SPI0_CS1 0x0600004c + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>,<&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>,<&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>,<&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; + +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + phy-reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + }; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <4000000>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + status = "okay"; +}; + diff --git a/arch/arm/dts/fsl-imx8qm-device.dtsi b/arch/arm/dts/fsl-imx8qm-device.dtsi new file mode 100644 index 00000000000..e4ce8b1a654 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-device.dtsi @@ -0,0 +1,2381 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + + imx8qm-pm { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0: PD_DC_0 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll0: PD_DC_0_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc0_pll1: PD_DC_0_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0_pll0>; + }; + }; + + pd_mipi0: PD_MIPI_0_DSI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi0_i2c0: PD_MIPI_0_DSI_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + + pd_mipi0_i2c1: PD_MIPI_0_DSI_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + + pd_mipi0_pwm: PD_MIPI_0_DSI_PWM0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi0>; + }; + }; + + pd_lvds0: PD_LVDS0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lvds0_i2c0: PD_LVDS0_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_lvds0>; + }; + + pd_lvds0_pwm: PD_LVDS0_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_lvds0>; + }; + }; + + pd_hdmi: PD_HDMI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_pll0: PD_HDMI_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_pll1: PD_HDMI_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_pll0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_i2c0: PD_HDMI_I2C_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_pll1>; + }; + + pd_hdmi_i2s: PD_HDMI_I2S { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_pll1>; + }; + }; + }; + + }; + + }; + + pd_dc1: PD_DC_1 { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc1_pll0: PD_DC_1_PLL_0{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dc1_pll1: PD_DC_1_PLL_1{ + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1_pll0>; + }; + }; + + pd_mipi1: PD_MIPI_1_DSI { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_mipi1_i2c0: PD_MIPI_1_DSI_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + + pd_mipi1_i2c1: PD_MIPI_1_DSI_I2C1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + + pd_mipi1_pwm: PD_MIPI_1_DSI_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_mipi1>; + }; + }; + + pd_lvds1: PD_LVDS1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_dc1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lvds1_i2c0: PD_LVDS1_I2C0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_lvds1>; + }; + + pd_lvds1_pwm: PD_LVDS1_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_lvds1>; + }; + }; + }; + + pd_lsio: PD_LSIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_lsio_gpio0: PD_LSIO_GPIO_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio1: PD_LSIO_GPIO_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio2: PD_LSIO_GPIO_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio3: PD_LSIO_GPIO_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio4: PD_LSIO_GPIO_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio5: PD_LSIO_GPIO_5{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio6:PD_LSIO_GPIO_6 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_gpio7: PD_LSIO_GPIO_7 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi0: PD_LSIO_FSPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_flexspi1: PD_LSIO_FSPI_1{ + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu5a: PD_LSIO_MU5A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu6a: PD_LSIO_MU6A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu8a: PD_LSIO_MU8A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + pd_lsio_mu9a: PD_LSIO_MU9A { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_lsio>; + }; + }; + + pd_conn: PD_CONN { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_conn_usbotg0: PD_CONN_USB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <267>; + }; + + pd_conn_usbotg0_phy: PD_CONN_USB_0_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <267>; + }; + + pd_conn_usbh1: PD_CONN_USB_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <268>; + }; + + pd_conn_usb2: PD_CONN_USB_2 { + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <271>; + + pd_conn_usb2_phy: PD_CONN_USB_2_PHY { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn_usb2>; + wakeup-irq = <271>; + }; + }; + pd_conn_sdch0: PD_CONN_SDHC_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch1: PD_CONN_SDHC_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_sdch2: PD_CONN_SDHC_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_enet0: PD_CONN_ENET_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + wakeup-irq = <258>; + }; + pd_conn_enet1: PD_CONN_ENET_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + fsl,wakeup_irq = <262>; + }; + pd_conn_nand: PD_CONN_NAND { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_mlb0: PD_CONN_MLB_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_conn>; + }; + pd_conn_edma_ch0: PD_CONN_DMA_4_CH0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch1: PD_CONN_DMA_4_CH1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch2: PD_CONN_DMA_4_CH2 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch3: PD_CONN_DMA_4_CH3 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + pd_conn_edma_ch4: PD_CONN_DMA_4_CH4 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_conn>; + }; + }; + + pd_hsio: PD_HSIO { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hsio_gpio: PD_HSIO_GPIO { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes0: PD_HSIO_SERDES_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hsio_gpio>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie0: PD_HSIO_PCIE_A { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_serdes0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_pcie1: PD_HSIO_PCIE_B { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_pcie0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_serdes1: PD_HSIO_SERDES_1 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_pcie1>; + #address-cells = <1>; + #size-cells = <0>; + + pd_sata0: PD_HSIO_SATA_0 { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_serdes1>; + }; + }; + }; + }; + }; + }; + }; + + pd_dma: PD_DMA { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma_lpi2c0: PD_DMA_I2C_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c1: PD_DMA_I2C_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c2:PD_DMA_I2C_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c3: PD_DMA_I2C_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpi2c4: PD_DMA_I2C_4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpuart0: PD_DMA_UART0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + wakeup-irq = <345>; + }; + pd_dma_lpuart1: PD_DMA_UART1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <346>; + + pd_dma0_chan14: PD_UART1_RX { + reg = ; + power-domains =<&pd_dma_lpuart1>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan15: PD_UART1_TX { + reg = ; + power-domains =<&pd_dma0_chan14>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart2: PD_DMA_UART2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <347>; + + pd_dma0_chan16: PD_UART2_RX { + reg = ; + power-domains =<&pd_dma_lpuart2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan17: PD_UART2_TX { + reg = ; + power-domains =<&pd_dma0_chan16>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart3: PD_DMA_UART3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <348>; + + pd_dma0_chan18: PD_UART3_RX { + reg = ; + power-domains =<&pd_dma_lpuart3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan19: PD_UART3_TX { + reg = ; + power-domains =<&pd_dma0_chan18>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpuart4: PD_DMA_UART4 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + wakeup-irq = <349>; + + pd_dma0_chan20: PD_UART4_RX { + reg = ; + power-domains =<&pd_dma_lpuart4>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan21: PD_UART4_TX { + reg = ; + power-domains =<&pd_dma0_chan20>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpspi0: PD_DMA_SPI_0 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan0: PD_LPSPI0_RX { + reg = ; + power-domains =<&pd_dma_lpspi0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan1: PD_LPSPI0_TX { + reg = ; + power-domains =<&pd_dma0_chan0>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_lpspi1: PD_DMA_SPI_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi2: PD_DMA_SPI_2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + pd_dma_lpspi3: PD_DMA_SPI_3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan6: PD_LPSPI3_RX { + reg = ; + power-domains =<&pd_dma_lpspi3>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan7: PD_LPSPI3_TX { + reg = ; + power-domains =<&pd_dma0_chan6>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + pd_dma_emvsim0: PD_DMA_EMVSIM_0 { + reg = ; + power-domains = <&pd_dma>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_ldo1_sim: LDO1_SIM { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma_emvsim0>; + }; + }; + pd_dma_emvsim1: PD_DMA_EMVSIM_1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_dma>; + }; + }; + + + pd_isi_ch0: PD_IMAGING { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_rx: PD_HDMI_RX { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_isi_ch0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_rx_bypass: PD_HDMI_RX_BYPASS { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_rx>; + #address-cells = <1>; + #size-cells = <0>; + + pd_hdmi_rx_i2c0: PD_HDMI_RX_I2C { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_rx_bypass>; + }; + + pd_hdmi_rx_pwm0: PD_HDMI_RX_PWM { + reg = ; + #power-domain-cells = <0>; + power-domains =<&pd_hdmi_rx_bypass>; + }; + }; + }; + + }; + + pd_caam: PD_CAAM { + compatible = "nxp,imx8-pd"; + reg = ; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_caam_jr1: PD_CAAM_JR1 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr2: PD_CAAM_JR2 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + pd_caam_jr3: PD_CAAM_JR3 { + reg = ; + #power-domain-cells = <0>; + power-domains = <&pd_caam>; + }; + }; + }; + + tsens: thermal-sensor { + compatible = "nxp,imx8qm-sc-tsens"; + u-boot,dm-pre-reloc; + /* number of the temp sensor on the chip */ + tsens-num = <5>; + #thermal-sensor-cells = <1>; + }; + + thermal_zones: thermal-zones { + /* cpu thermal */ + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + /*the slope and offset of the temp sensor */ + thermal-sensors = <&tsens 0>; + trips { + cpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 1>; + trips { + cpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + trips { + gpu_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + gpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 3>; + trips { + gpu_alert1: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + gpu_crit1: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + drc-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 4>; + trips { + drc_alert0: trip0 { + temperature = <107000>; + hysteresis = <2000>; + type = "passive"; + }; + drc_crit0: trip1 { + temperature = <127000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + rtc: rtc { + compatible = "fsl,imx-sc-rtc"; + }; + + dpu1_intsteer: dpu_intsteer@56000000 { + compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; + reg = <0x0 0x56000000 0x0 0x10000>; + }; + + dpu1: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-dpu"; + reg = <0x0 0x56180000 0x0 0x40000>; + intsteer = <&dpu1_intsteer>; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", /* to M4? */ + "irq_stream1a", + "irq_stream1b", /* to M4? */ + "irq_reserved0", + "irq_reserved1", + "irq_blit", + "irq_dpr0", + "irq_dpr1"; + clocks = <&clk IMX8QM_DC0_PLL0_CLK>, + <&clk IMX8QM_DC0_PLL1_CLK>, + <&clk IMX8QM_DC0_BYPASS_0_DIV>, + <&clk IMX8QM_DC0_DISP0_SEL>, + <&clk IMX8QM_DC0_DISP1_SEL>, + <&clk IMX8QM_DC0_DISP0_CLK>, + <&clk IMX8QM_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "bypass0", + "disp0_sel", "disp1_sel", "disp0", "disp1"; + power-domains = <&pd_dc0_pll1>; + status = "disabled"; + + dpu1_disp0: port@0 { + reg = <0>; + + dpu1_disp0_hdmi: endpoint@0 { + remote-endpoint = <&hdmi_disp>; + }; + + dpu1_disp0_mipi_dsi: endpoint@1 { + remote-endpoint = <&mipi_dsi1_in>; + }; + }; + + dpu1_disp1: port@1 { + reg = <1>; + + dpu1_disp1_lvds0: endpoint@0 { + remote-endpoint = <&ldb1_lvds0>; + }; + + dpu1_disp1_lvds1: endpoint@1 { + remote-endpoint = <&ldb1_lvds1>; + }; + }; + }; + + hdmi:hdmi@56268000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x56268000 0x0 0x100000>, /* HDP Controller */ + <0x0 0x56261000 0x0 0x1000>; /* HDP SubSystem CSR */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "plug_in", "plug_out"; + interrupt-parent = <&irqsteer_hdmi>; + status = "disabled"; + clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_IPG_CLK>, + <&clk IMX8QM_HDMI_HDP_CORE_CLK>, + <&clk IMX8QM_HDMI_PXL_CLK>, + <&clk IMX8QM_HDMI_PXL_MUX_CLK>, + <&clk IMX8QM_HDMI_PXL_LINK_CLK>, + <&clk IMX8QM_HDMI_HDP_CLK>, + <&clk IMX8QM_HDMI_HDP_PHY_CLK>, + <&clk IMX8QM_HDMI_APB_CLK>, + <&clk IMX8QM_HDMI_LIS_IPG_CLK>, + <&clk IMX8QM_HDMI_MSI_HCLK>, + <&clk IMX8QM_HDMI_PXL_LPCG_CLK>, + <&clk IMX8QM_HDMI_PXL_EVEN_CLK>, + <&clk IMX8QM_HDMI_PXL_DBL_CLK>, + <&clk IMX8QM_HDMI_VIF_CLK>, + <&clk IMX8QM_HDMI_APB_MUX_CSR_CLK>, + <&clk IMX8QM_HDMI_APB_MUX_CTRL_CLK>, + <&clk IMX8QM_HDMI_I2S_CLK>, + <&clk IMX8QM_HDMI_I2S_BYPASS_CLK>; + clock-names = "dig_pll", "av_pll", "clk_ipg", + "clk_core", "clk_pxl", "clk_pxl_mux", + "clk_pxl_link", "clk_hdp", "clk_phy", + "clk_apb", "clk_lis","clk_msi", + "clk_lpcg", "clk_even","clk_dbl", + "clk_vif", "clk_apb_csr","clk_apb_ctrl", + "clk_i2s", "clk_i2s_bypass"; + power-domains = <&pd_hdmi_i2s>; + + port@0 { + reg = <0>; + hdmi_disp: endpoint { + remote-endpoint = <&dpu1_disp0_hdmi>; + }; + }; + }; + + irqsteer_dsi0: irqsteer@56220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56220000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_MIPI0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi0>; + }; + + i2c0_mipi_dsi0: i2c@56226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi0>; + clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>, + <&clk IMX8QM_MIPI0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_MIPI0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi0_i2c0>; + status = "disabled"; + }; + + mipi_dsi_csr1: csr@56221000 { + compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon"; + reg = <0x0 0x56221000 0x0 0x1000>; + }; + + mipi_dsi_phy1: dsi_phy@56228300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8qm-mipi-dsi-phy"; + reg = <0x0 0x56228300 0x0 0x100>; + power-domains = <&pd_mipi0>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi1: mipi_dsi@56228000 { + compatible = "fsl,imx8qm-mipi-dsi"; + clocks = + <&clk IMX8QM_MIPI0_PXL_CLK>, + <&clk IMX8QM_MIPI0_BYPASS_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi0>; + csr = <&mipi_dsi_csr1>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + pwr-delay = <100>; + status = "disabled"; + + port@0 { + mipi_dsi1_in: endpoint { + remote-endpoint = <&dpu1_disp0_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi1_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_in>; + }; + }; + }; + + mipi_dsi_bridge1: mipi_dsi_bridge@56228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x56228000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi0>; + clocks = + <&clk IMX8QM_MIPI0_BYPASS_CLK>, + <&clk IMX8QM_MIPI0_DSI_TX_ESC_CLK>, + <&clk IMX8QM_MIPI0_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = <&clk IMX8QM_MIPI0_DSI_TX_ESC_DIV>, + <&clk IMX8QM_MIPI0_DSI_RX_ESC_DIV>; + assigned-clock-rates = <18000000>, <72000000>; + power-domains = <&pd_mipi0>; + phys = <&mipi_dsi_phy1>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge1_in: endpoint { + remote-endpoint = <&mipi_dsi1_out>; + }; + }; + }; + + lvds_region1: lvds_region@56240000 { + compatible = "fsl,imx8qm-lvds-region", "syscon"; + reg = <0x0 0x56240000 0x0 0x10000>; + }; + + ldb1_phy: ldb_phy@56241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x56241000 0x0 0x100>; + clocks = <&clk IMX8QM_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_lvds0>; + status = "disabled"; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb1: ldb@562410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX8QM_LVDS0_PIXEL_CLK>, + <&clk IMX8QM_LVDS0_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_lvds0>; + gpr = <&lvds_region1>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb1_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_lvds0: endpoint { + remote-endpoint = <&dpu1_disp1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb1_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb1_lvds1: endpoint { + remote-endpoint = <&dpu1_disp1_lvds1>; + }; + }; + }; + }; + + lvds0_pwm: pwm@56244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x56244000 0 0x1000>; + clocks = <&clk IMX8QM_LVDS0_PWM0_IPG_CLK>, + <&clk IMX8QM_LVDS0_PWM0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_LVDS0_PWM0_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lvds0_pwm>; + status = "disabled"; + }; + + dpu2_intsteer: dpu_intsteer@57000000 { + compatible = "fsl,imx8qm-dpu-intsteer", "syscon"; + reg = <0x0 0x57000000 0x0 0x10000>; + }; + + dpu2: dpu@57180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-dpu"; + reg = <0x0 0x57180000 0x0 0x40000>; + intsteer = <&dpu2_intsteer>; + interrupts = , + , + , + , + , + , + , + , + , + ; + interrupt-names = "irq_common", + "irq_stream0a", + "irq_stream0b", /* to M4? */ + "irq_stream1a", + "irq_stream1b", /* to M4? */ + "irq_reserved0", + "irq_reserved1", + "irq_blit", + "irq_dpr0", + "irq_dpr1"; + clocks = <&clk IMX8QM_DC1_PLL0_CLK>, + <&clk IMX8QM_DC1_PLL1_CLK>, + <&clk IMX8QM_DC1_BYPASS_0_DIV>, + <&clk IMX8QM_DC1_DISP0_SEL>, + <&clk IMX8QM_DC1_DISP1_SEL>, + <&clk IMX8QM_DC1_DISP0_CLK>, + <&clk IMX8QM_DC1_DISP1_CLK>; + clock-names = "pll0", "pll1", "bypass0", + "disp0_sel", "disp1_sel", "disp0", "disp1"; + power-domains = <&pd_dc1_pll1>; + status = "disabled"; + + dpu2_disp0: port@0 { + reg = <0>; + + dpu2_disp0_mipi_dsi: endpoint { + remote-endpoint = <&mipi_dsi2_in>; + }; + }; + + dpu2_disp1: port@1 { + reg = <1>; + + dpu2_disp1_lvds0: endpoint@0 { + remote-endpoint = <&ldb2_lvds0>; + }; + + dpu2_disp1_lvds1: endpoint@1 { + remote-endpoint = <&ldb2_lvds1>; + }; + }; + }; + + irqsteer_dsi1: irqsteer@57220000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x57220000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_MIPI1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_mipi1>; + }; + + i2c0_mipi_dsi1: i2c@57226000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x57226000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi1>; + clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>, + <&clk IMX8QM_MIPI1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_MIPI1_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_mipi1_i2c0>; + status = "disabled"; + }; + + mipi_dsi_csr2: csr@57221000 { + compatible = "fsl,imx8qm-mipi-dsi-csr", "syscon"; + reg = <0x0 0x57221000 0x0 0x1000>; + }; + + mipi_dsi_phy2: mipi_phy@57228300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,imx8qm-mipi-dsi-phy"; + reg = <0x0 0x57228300 0x0 0x100>; + power-domains = <&pd_mipi1>; + #phy-cells = <0>; + status = "disabled"; + }; + + mipi_dsi2: mipi_dsi@57228000 { + compatible = "fsl,imx8qm-mipi-dsi"; + clocks = + <&clk IMX8QM_MIPI1_PXL_CLK>, + <&clk IMX8QM_MIPI1_BYPASS_CLK>, + <&clk IMX8QM_CLK_DUMMY>; + clock-names = "pixel", "bypass", "phy_ref"; + power-domains = <&pd_mipi1>; + csr = <&mipi_dsi_csr2>; + phys = <&mipi_dsi_phy2>; + phy-names = "dphy"; + pwr-delay = <100>; + status = "disabled"; + + port@0 { + mipi_dsi2_in: endpoint { + remote-endpoint = <&dpu2_disp0_mipi_dsi>; + }; + }; + + port@1 { + mipi_dsi2_out: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_in>; + }; + }; + }; + + mipi_dsi_bridge2: mipi_dsi_bridge@57228000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nwl,mipi-dsi"; + reg = <0x0 0x57228000 0x0 0x300>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_dsi1>; + clocks = + <&clk IMX8QM_MIPI1_BYPASS_CLK>, + <&clk IMX8QM_MIPI1_DSI_TX_ESC_CLK>, + <&clk IMX8QM_MIPI1_DSI_RX_ESC_CLK>; + clock-names = "phy_ref", "tx_esc", "rx_esc"; + assigned-clocks = <&clk IMX8QM_MIPI1_DSI_TX_ESC_DIV>, + <&clk IMX8QM_MIPI1_DSI_RX_ESC_DIV>; + assigned-clock-rates = <18000000>, <72000000>; + power-domains = <&pd_mipi1>; + phys = <&mipi_dsi_phy2>; + phy-names = "dphy"; + status = "disabled"; + + port@0 { + mipi_dsi_bridge2_in: endpoint { + remote-endpoint = <&mipi_dsi2_out>; + }; + }; + }; + + lvds_region2: lvds_region@57240000 { + compatible = "fsl,imx8qm-lvds-region", "syscon"; + reg = <0x0 0x57240000 0x0 0x10000>; + }; + + ldb2_phy: ldb_phy@57241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x57241000 0x0 0x100>; + clocks = <&clk IMX8QM_LVDS1_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd_lvds1>; + status = "disabled"; + + ldb2_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb2_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + + ldb2: ldb@572410e0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qm-ldb"; + clocks = <&clk IMX8QM_LVDS1_PIXEL_CLK>, + <&clk IMX8QM_LVDS1_BYPASS_CLK>; + clock-names = "pixel", "bypass"; + power-domains = <&pd_lvds1>; + gpr = <&lvds_region2>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&ldb2_phy1>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_lvds0: endpoint { + remote-endpoint = <&dpu2_disp1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&ldb2_phy2>; + phy-names = "ldb_phy"; + status = "disabled"; + + port@0 { + reg = <0>; + + ldb2_lvds1: endpoint { + remote-endpoint = <&dpu2_disp1_lvds1>; + }; + }; + }; + }; + + lvds1_pwm: pwm@57244000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x57244000 0 0x1000>; + clocks = <&clk IMX8QM_LVDS1_PWM0_IPG_CLK>, + <&clk IMX8QM_LVDS1_PWM0_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QM_LVDS1_PWM0_CLK>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lvds1_pwm>; + status = "disabled"; + }; + + camera: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x0 0x58100000 0x0 0x10000>; + interrupts = <0 297 0>; + interface = <2 0 2>; /* + Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM */ + clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; + clock-names = "per"; + assigned-clocks = <&clk IMX8QM_IMG_PDMA_0_CLK>; + assigned-clock-rates = <600000000>; + power-domains =<&pd_isi_ch0>; + status = "disabled"; + }; + + hdmi_rx: hdmi_rx@58268000 { + compatible = "fsl,imx-hdmi-rx"; + reg = <0x0 0x58268000 0x0 0x10000>, /* HDP Controller */ + <0x0 0x58261000 0x0 0x1000>; /* HDP SubSystem CSR */ + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, + <13 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "plug_in", "plug_out"; + + interrupt-parent = <&irqsteer_hdmi_rx>; + clocks = <&clk IMX8QM_HDMI_RX_HD_REF_CLK>, + <&clk IMX8QM_HDMI_RX_HD_CORE_CLK>, + <&clk IMX8QM_HDMI_RX_PXL_CLK>, + <&clk IMX8QM_HDMI_RX_SINK_PCLK>, + <&clk IMX8QM_HDMI_RX_SINK_SCLK>, + <&clk IMX8QM_HDMI_RX_PXL_ENC_CLK>, + <&clk IMX8QM_HDMI_RX_I2S_CLK>, + <&clk IMX8QM_HDMI_RX_SPDIF_CLK>, + <&clk IMX8QM_IMG_PXL_LINK_HDMI_IN_CLK>; + clock-names = "ref_clk", "core_clk", "pxl_clk", + "pclk", "sclk", "enc_clk", + "i2s_clk", "spdif_clk", + "pxl_link_clk"; + power-domains = <&pd_hdmi_rx_bypass>; + status = "disabled"; + }; + }; + + i2c0: i2c@5a800000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a800000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C0_CLK>, + <&clk IMX8QM_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c0>; + status = "disabled"; + }; + + i2c1: i2c@5a810000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a810000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C1_CLK>, + <&clk IMX8QM_I2C1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C1_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c1>; + status = "disabled"; + }; + + i2c2: i2c@5a820000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a820000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C2_CLK>, + <&clk IMX8QM_I2C2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c2>; + status = "disabled"; + }; + + i2c3: i2c@5a830000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a830000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C3_CLK>, + <&clk IMX8QM_I2C3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C3_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c3>; + status = "disabled"; + }; + + i2c4: i2c@5a840000 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; + reg = <0x0 0x5a840000 0x0 0x4000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_I2C4_CLK>, + <&clk IMX8QM_I2C4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_I2C4_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma_lpi2c4>; + status = "disabled"; + }; + + irqsteer_hdmi: irqsteer@56260000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56260000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_HDMI_LIS_IPG_CLK>; + clock-names = "ipg"; + assigned-clocks = <&clk IMX8QM_HDMI_DIG_PLL_CLK>, + <&clk IMX8QM_HDMI_LIS_IPG_CLK>; + assigned-clock-rates = <675000000>, <84375000>; + power-domains = <&pd_hdmi>; + status = "disabled"; + }; + + irqsteer_hdmi_rx: irqsteer@58260000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x58260000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_HDMI_RX_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_hdmi_rx>; + }; + + + i2c0_hdmi: i2c@56266000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56266000 0x0 0x1000>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_hdmi>; + clocks = <&clk IMX8QM_HDMI_I2C0_CLK>, + <&clk IMX8QM_HDMI_I2C_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_HDMI_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_hdmi_i2c0>; + status = "disabled"; + }; + + irqsteer_lvds0: irqsteer@562400000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x56240000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_LVDS0_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lvds0>; + }; + + + i2c1_lvds0: i2c@56247000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x56247000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_lvds0>; + clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>, + <&clk IMX8QM_LVDS0_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_LVDS0_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_lvds0_i2c0>; + status = "disabled"; + }; + + irqsteer_lvds1: irqsteer@572400000 { + compatible = "nxp,imx-irqsteer"; + reg = <0x0 0x57240000 0x0 0x1000>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + clocks = <&clk IMX8QM_LVDS1_LIS_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lvds1>; + }; + + i2c1_lvds1: i2c@57247000 { + compatible = "fsl,imx8qm-lpi2c"; + reg = <0x0 0x57247000 0x0 0x1000>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&irqsteer_lvds1>; + clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>, + <&clk IMX8QM_LVDS1_I2C0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_LVDS1_I2C0_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_lvds1_i2c0>; + status = "disabled"; + }; + + lpspi0: lpspi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a000000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_SPI0_CLK>, + <&clk IMX8QM_SPI0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_SPI0_CLK>; + assigned-clock-rates = <20000000>; + power-domains = <&pd_dma0_chan1>; + dma-names = "tx","rx"; + dmas = <&edma0 1 0 0>, <&edma0 0 0 1>; + status = "disabled"; + }; + + lpspi3: lpspi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a030000 0x0 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_SPI3_CLK>, + <&clk IMX8QM_SPI3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_SPI3_CLK>; + assigned-clock-rates = <60000000>; + power-domains = <&pd_dma0_chan7>; + dma-names = "tx","rx"; + dmas = <&edma0 7 0 0>, <&edma0 6 0 1>; + status = "disabled"; + }; + + lpuart0: serial@5a060000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a060000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART0_CLK>, + <&clk IMX8QM_UART0_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART0_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma_lpuart0>; + status = "disabled"; + }; + + lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART1_CLK>, + <&clk IMX8QM_UART1_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan15>; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; + }; + + lpuart2: serial@5a080000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a080000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART2_CLK>, + <&clk IMX8QM_UART2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART2_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan17>; + dma-names = "tx","rx"; + dmas = <&edma0 17 0 0>, + <&edma0 16 0 1>; + status = "disabled"; + }; + + lpuart3: serial@5a090000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a090000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART3_CLK>, + <&clk IMX8QM_UART3_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART3_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan19>; + dma-names = "tx","rx"; + dmas = <&edma0 19 0 0>, + <&edma0 18 0 1>; + status = "disabled"; + }; + + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a0a0000 0x0 0x1000>; + interrupts = ; + interrupt-parent = <&wu>; + clocks = <&clk IMX8QM_UART4_CLK>, + <&clk IMX8QM_UART4_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_UART4_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd_dma0_chan21>; + dma-names = "tx","rx"; + dmas = <&edma0 21 0 0>, + <&edma0 20 0 1>; + status = "disabled"; + }; + + edma0: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */ + <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */ + <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */ + <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */ + <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>, /* channel15 UART1 tx */ + <0x0 0x5a300000 0x0 0x10000>, /* channel16 UART2 rx */ + <0x0 0x5a310000 0x0 0x10000>, /* channel17 UART2 tx */ + <0x0 0x5a320000 0x0 0x10000>, /* channel18 UART3 rx */ + <0x0 0x5a330000 0x0 0x10000>, /* channel19 UART3 tx */ + <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ + <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ + #dma-cells = <3>; + dma-channels = <14>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan6-rx", "edma0-chan7-tx", + "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx", + "edma0-chan16-rx", "edma0-chan17-tx", + "edma0-chan18-rx", "edma0-chan19-tx", + "edma0-chan20-rx", "edma0-chan21-tx"; + status = "okay"; + }; + + edma2: dma-controller@591F0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ + <0x0 0x59210000 0x0 0x10000>, + <0x0 0x59220000 0x0 0x10000>, + <0x0 0x59230000 0x0 0x10000>, + <0x0 0x59240000 0x0 0x10000>, + <0x0 0x59250000 0x0 0x10000>, + <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ + <0x0 0x59270000 0x0 0x10000>, /* esai0 tx */ + <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */ + <0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */ + <0x0 0x592A0000 0x0 0x10000>, /* spdif1 rx */ + <0x0 0x592B0000 0x0 0x10000>, /* spdif1 tx */ + <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ + <0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */ + <0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */ + <0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */ + <0x0 0x59320000 0x0 0x10000>, /* sai4 rx */ + <0x0 0x59330000 0x0 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <18>; + interrupts = , /* asrc0 */ + , + , + , + , + , + , /* esai0 */ + , + , /* spdif0 */ + , + , /* spdif1 */ + , + , /* sai0 */ + , + , /* sai1 */ + , + , /* sai4 */ + ; /* sai5 */ + interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ + "edma2-chan2-rx", "edma2-chan3-tx", + "edma2-chan4-tx", "edma2-chan5-tx", + "edma2-chan6-rx", "edma2-chan7-tx", /* esai0 */ + "edma2-chan8-rx", "edma2-chan9-tx", /* spdif0 */ + "edma2-chan10-rx", "edma2-chan11-tx", /* spdif1 */ + "edma2-chan12-rx", "edma2-chan13-tx", /* sai0 */ + "edma2-chan14-rx", "edma2-chan15-tx", /* sai1 */ + "edma2-chan18-rx", "edma2-chan19-tx"; /* sai4, sai5 */ + status = "okay"; + }; + + edma3: dma-controller@599F0000 { + compatible = "fsl,imx8qm-adma"; + reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ + <0x0 0x59A10000 0x0 0x10000>, + <0x0 0x59A20000 0x0 0x10000>, + <0x0 0x59A30000 0x0 0x10000>, + <0x0 0x59A40000 0x0 0x10000>, + <0x0 0x59A50000 0x0 0x10000>, + <0x0 0x59A80000 0x0 0x10000>, /* sai6 rx */ + <0x0 0x59A90000 0x0 0x10000>, /* sai6 tx */ + <0x0 0x59AA0000 0x0 0x10000>; /* sai7 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = , /* asrc1 */ + , + , + , + , + , + , /* sai6 */ + , + ; /* sai7 */ + interrupt-names = "edma3-chan0-rx", "edma3-chan1-rx", /* asrc1 */ + "edma3-chan2-rx", "edma3-chan3-tx", + "edma3-chan4-tx", "edma3-chan5-tx", + "edma3-chan8-rx", "edma3-chan9-tx", /* sai6 */ + "edma3-chan10-tx"; /* sai7 */ + status = "okay"; + }; + + wu: wu { + compatible = "fsl,imx8-wu"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + }; + + gpio0: gpio@5d080000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d080000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio0>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@5d090000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d090000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@5d0a0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0a0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@5d0b0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0b0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio3>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@5d0c0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0c0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio4>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@5d0d0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0d0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio5>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@5d0e0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0e0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio6>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@5d0f0000 { + compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg = <0x0 0x5d0f0000 0x0 0x10000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + power-domains = <&pd_lsio_gpio7>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + clock-names = "mlb", "hclk", "ipg"; + assigned-clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + assigned-clock-rates = <333333333>, <333333333>, <83333333>; + power-domains = <&pd_conn_mlb0>; + status = "disabled"; + }; + + usdhc1: usdhc@5b010000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b010000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, + <&clk IMX8QM_SDHC0_CLK>, + <&clk IMX8QM_SDHC0_AHB_CLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; + assigned-clock-rates = <400000000>; + power-domains = <&pd_conn_sdch0>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + iommus = <&smmu 0x11 0x7f80>; + status = "disabled"; + }; + + usdhc2: usdhc@5b020000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b020000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC1_IPG_CLK>, + <&clk IMX8QM_SDHC1_CLK>, + <&clk IMX8QM_SDHC1_AHB_CLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC1_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch1>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + iommus = <&smmu 0x11 0x7f80>; + status = "disabled"; + }; + + usdhc3: usdhc@5b030000 { + compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; + interrupt-parent = <&gic>; + interrupts = ; + reg = <0x0 0x5b030000 0x0 0x10000>; + clocks = <&clk IMX8QM_SDHC2_IPG_CLK>, + <&clk IMX8QM_SDHC2_CLK>, + <&clk IMX8QM_SDHC2_AHB_CLK>; + clock-names = "ipg", "per", "ahb"; + assigned-clocks = <&clk IMX8QM_SDHC2_DIV>; + assigned-clock-rates = <200000000>; + power-domains = <&pd_conn_sdch2>; + iommus = <&smmu 0x11 0x7f80>; + status = "disabled"; + }; + + fec1: ethernet@5b040000 { + compatible = "fsl,imx8qm-fec"; + reg = <0x0 0x5b040000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QM_ENET0_IPG_CLK>, <&clk IMX8QM_ENET0_AHB_CLK>, <&clk IMX8QM_ENET0_RGMII_TX_CLK>, + <&clk IMX8QM_ENET0_PTP_CLK>, <&clk IMX8QM_ENET0_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>, + <&clk IMX8QM_ENET0_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; + power-domains = <&pd_conn_enet0>; + iommus = <&smmu 0x12 0x7f80>; + status = "disabled"; + }; + + fec2: ethernet@5b050000 { + compatible = "fsl,imx8qm-fec"; + reg = <0x0 0x5b050000 0x0 0x10000>; + interrupt-parent = <&wu>; + interrupts = , + , + , + ; + clocks = <&clk IMX8QM_ENET1_IPG_CLK>, <&clk IMX8QM_ENET1_AHB_CLK>, <&clk IMX8QM_ENET1_RGMII_TX_CLK>, + <&clk IMX8QM_ENET1_PTP_CLK>, <&clk IMX8QM_ENET1_TX_CLK>; + clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk"; + assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>, + <&clk IMX8QM_ENET1_REF_DIV>; + assigned-clock-rates = <250000000>, <125000000>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + fsl,wakeup_irq = <0>; + power-domains = <&pd_conn_enet1>; + iommus = <&smmu 0x12 0x7f80>; + status = "disabled"; + }; + + usbmisc1: usbmisc@5b0d0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x5b0d0200 0x0 0x200>; + }; + + usbmisc2: usbmisc@5b0e0200 { + #index-cells = <1>; + compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc"; + reg = <0x0 0x5b0e0200 0x0 0x200>; + }; + + usbphy1: usbphy@0x5b100000 { + compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; + reg = <0x0 0x5b100000 0x0 0x1000>; + clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>; + power-domains = <&pd_conn_usbotg0_phy>; + }; + + usbphynop1: usbphynop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8QM_USB3_PHY_CLK>; + clock-names = "main_clk"; + power-domains = <&pd_conn_usb2_phy>; + }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8QM_USB2_PHY_IPG_CLK>; + clock-names = "main_clk"; + power-domains = <&pd_conn_usbotg0_phy>; + }; + + usbotg1: usb@5b0d0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0d0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = ; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbotg0>; + status = "disabled"; + }; + + usbh1: usb@5b0e0000 { + compatible = "fsl,imx8qm-usb", "fsl,imx27-usb"; + reg = <0x0 0x5b0e0000 0x0 0x200>; + interrupt-parent = <&wu>; + interrupts = ; + phy_type = "hsic"; + dr_mode = "host"; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + clocks = <&clk IMX8QM_USB2_OH_AHB_CLK>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; + #stream-id-cells = <1>; + power-domains = <&pd_conn_usbh1>; + status = "disabled"; + }; + + usbotg3: usb3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>, + <0x0 0x5B120000 0x0 0x10000>; + reg-names = "none-core", "xhci", "dev", "phy", "otg"; + interrupt-parent = <&wu>; + interrupts = ; + clocks = <&clk IMX8QM_USB3_LPM_CLK>, + <&clk IMX8QM_USB3_BUS_CLK>, + <&clk IMX8QM_USB3_ACLK>, + <&clk IMX8QM_USB3_IPG_CLK>, + <&clk IMX8QM_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + assigned-clocks = <&clk IMX8QM_USB3_ACLK_DIV>, + <&clk IMX8QM_USB3_LPM_DIV>, + <&clk IMX8QM_USB3_BUS_DIV>; + assigned-clock-rates = <125000000>, <12000000>, <250000000>; + power-domains = <&pd_conn_usb2>; + cdns3,usbphy = <&usbphynop1>; + status = "disabled"; + }; + + ddr_pmu0: ddr_pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c020000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + ddr_pmu1: ddr_pmu@5c120000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x0 0x5c120000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + flexspi0: flexspi@05d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8qxp-fspi"; + reg = <0x0 0x5d120000 0x0 0x10000>, + <0x0 0x08000000 0x0 0x19ffffff>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8QM_FSPI0_CLK>, + <&clk IMX8QM_FSPI0_CLK>; + assigned-clocks = <&clk IMX8QM_FSPI0_DIV>; + assigned-clock-rates = <29000000>; + power-domains = <&pd_lsio_flexspi0>; + clock-names = "fspi", "fspi_en"; + status = "disabled"; + }; + + display: display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&dpu1_disp0>, <&dpu1_disp1>, + <&dpu2_disp0>, <&dpu2_disp1>; + }; + + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + + hsio: hsio@5f080000 { + compatible = "fsl,imx8qm-hsio", "syscon"; + reg = <0x0 0x5f080000 0x0 0xF0000>; /* lpcg, csr, msic, gpio */ + }; + + ocotp: ocotp { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx8qm-ocotp", "syscon"; + }; + + pciea: pcie@0x5f000000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x0 0x5f000000 0x0 0x10000>, /* Controller reg */ + <0x0 0x6ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi", + "phy_per", "misc_per"; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 73 4>, + <0 0 0 2 &gic 0 74 4>, + <0 0 0 3 &gic 0 75 4>, + <0 0 0 4 &gic 0 76 4>; + power-domains = <&pd_pcie1>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + hsio = <&hsio>; + ctrl-id = <0>; /* pciea */ + cpu-base-addr = <0x40000000>; + status = "disabled"; + }; + + pcieb: pcie@0x5f010000 { + compatible = "fsl,imx8qm-pcie","snps,dw-pcie"; + reg = <0x0 0x5f010000 0x0 0x10000>, /* Controller reg */ + <0x0 0x7ff00000 0x0 0x80000>; /* PCI cfg space */ + reg-names = "dbi", "config"; + reserved-region = <&rpmsg_reserved>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + + #interrupt-cells = <1>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi"; + + /* + * Set these clocks in default, then clocks should be + * refined for exact hw design of imx8 pcie. + */ + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PHY_X2_PER_CLK>, + <&clk IMX8QM_HSIO_MISC_PER_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi", + "pciex2_per", "pcie_phy_pclk", "phy_per", "misc_per"; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 105 4>, + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; + power-domains = <&pd_pcie1>; + fsl,max-link-speed = <3>; + hsio-cfg = ; + hsio = <&hsio>; + ctrl-id = <1>; /* pcieb */ + cpu-base-addr = <0x80000000>; + status = "disabled"; + }; + + sata: sata@5f020000 { + compatible = "fsl,imx8qm-ahci"; + reg = <0x0 0x5f020000 0x0 0x10000>, /* Controller reg */ + <0x0 0x5f1a0000 0x0 0x10000>; /* PHY reg */ + reg-names = "ctl", "phy"; + interrupts = ; + clocks = <&clk IMX8QM_HSIO_SATA_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>; + clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "phy_pclk0", "phy_pclk1", "phy_apbclk"; + hsio = <&hsio>; + power-domains = <&pd_sata0>; + iommus = <&smmu 0x13 0x7f80>; + status = "disabled"; + }; + + imx_rpmsg: imx_rpmsg { + compatible = "fsl,rpmsg-bus", "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mu_rpmsg: mu_rpmsg@5d200000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x0 0x5d200000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_LSIO_MU5A_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lsio_mu5a>; + status = "okay"; + }; + + rpmsg: rpmsg { + compatible = "fsl,imx8qm-rpmsg"; + power-domains = <&pd_lsio_mu5a>; + mub-partition = <3>; + memory-region = <&rpmsg_dma_reserved>; + status = "disabled"; + }; + + mu_rpmsg1: mu_rpmsg1@5d210000 { + compatible = "fsl,imx-mu-rpmsg1"; + reg = <0x0 0x5d210000 0x0 0x10000>; + interrupts = ; + clocks = <&clk IMX8QM_LSIO_MU6A_IPG_CLK>; + clock-names = "ipg"; + power-domains = <&pd_lsio_mu6a>; + status = "okay"; + }; + + rpmsg1: rpmsg1{ + compatible = "fsl,imx8qm-rpmsg"; + multi-core-id = <1>; + mub-partition = <4>; + power-domains = <&pd_lsio_mu6a>; + memory-region = <&rpmsg_dma_reserved>; + status = "disabled"; + }; + }; + + crypto: caam@0x31400000 { + compatible = "fsl,sec-v4.0"; + reg = <0 0x31400000 0 0x400000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x31400000 0x400000>; + fsl,first-jr-index = <2>; + fsl,sec-era = <9>; + + sec_jr1: jr1@0x20000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr1>; + status = "disabled"; + }; + + sec_jr2: jr2@30000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr2>; + status = "okay"; + }; + + sec_jr3: jr3@40000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x1000>; + interrupts = ; + power-domains = <&pd_caam_jr3>; + status = "okay"; + }; + }; + + caam_sm: caam-sm@31800000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0 0x31800000 0 0x10000>; + }; + + i2c_rpbus_0: i2c-rpbus-0 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + i2c_rpbus_1: i2c-rpbus-1 { + compatible = "fsl,i2c-rpbus"; + status = "disabled"; + }; + + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = ; + wakeup-source; + }; + + wdog: wdog { + compatible = "fsl,imx8-wdt"; + }; diff --git a/arch/arm/dts/fsl-imx8qm-lpddr4-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-lpddr4-val-u-boot.dtsi new file mode 100644 index 00000000000..beed9d85d69 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-lpddr4-val-u-boot.dtsi @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8qm-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qm-val} { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-spl; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&usdhc3 { + u-boot,dm-spl; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&wu { + u-boot,dm-spl; +}; + +&fec1 { + phy-mode = "rgmii-id"; +}; + +&fec2 { + phy-mode = "rgmii-id"; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/fsl-imx8qm-lpddr4-val.dts b/arch/arm/dts/fsl-imx8qm-lpddr4-val.dts new file mode 100644 index 00000000000..2434c8d7754 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-lpddr4-val.dts @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017~2019 NXP + * + */ + +/dts-v1/; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "NXP i.MX8QM LPDDR4 VAL"; + compatible = "fsl,imx8qm-val", "fsl,imx8qm"; + + aliases { + gpio8 = &pca9557_a; + gpio9 = &pca9557_b; + gpio10 = &pca9557_c; + gpio11 = &pca9557_d; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + user { + label = "heartbeat"; + gpios = <&gpio2 15 0>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <4800>; + enable-active-high; + }; + + }; + +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qm-val { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x06000021 + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x06000021 + SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x06000021 + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x06000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + /* WP */ + SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 + /* CD */ + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0x06000020 + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x06000020 + /* + * Change the default alt function from SCL/SDA to others, + * to avoid select input conflict with GPT0 + */ + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0700004c + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0700004c + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0700004c + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0700004c + >; + }; + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c + SC_P_SPI0_CS1_DMA_SPI0_CS1 0x0600004c + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + >; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + phy-reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_d: gpio@1f { + compatible = "nxp,pca9557"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + }; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <4000000>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { + status = "okay"; +}; + diff --git a/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53-u-boot.dtsi new file mode 100644 index 00000000000..f87a4f6bcfb --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53-u-boot.dtsi @@ -0,0 +1,206 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8qm-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qm-mek} { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-spl; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&wu { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53.dts b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53.dts new file mode 100644 index 00000000000..5c8f8169b73 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a53.dts @@ -0,0 +1,471 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qm-cockpit-a53.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + u-boot,off-on-delay-us = <12000>; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&gpio1 13 0>; + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qm-mek { + pinctrl_hog: hoggrp { + fsl,pins = < + SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x06000021 + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x06000021 + SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x06000021 + SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x06000021 + SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x06000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + }; +}; + +&gpio0 { +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio3 { +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio6 { +}; + +&gpio7 { +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + /delete-property/ iommus; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + /delete-property/ iommus; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + }; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on = <&epdev_on>; + status = "okay"; +}; + +&sata { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + /delete-property/ iommus; + status = "okay"; +}; + +&tsens { + tsens-num = <6>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 5>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&pmic_alert0>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&display { + ports = <&dpu1_disp0>, <&dpu1_disp1>; +}; + +/delete-node/ &dpu2; +/delete-node/ &fec2; +/delete-node/ &ldb2; +/delete-node/ &isi_0; +/delete-node/ &lpuart2; +/delete-node/ &i2c1; +/delete-node/ &usdhc1; +/delete-node/ &i2c0; +/delete-node/ &i2c1_lvds1; +/delete-node/ &dpu2_intsteer; +/delete-node/ &lvds_region2; +/delete-node/ &ldb2_phy; +/delete-node/ &irqsteer_lvds1; +/delete-node/ &mipi_dsi2; +/delete-node/ &mipi_dsi_bridge2; +/delete-node/ &pinctrl_lvds1_lpi2c1; diff --git a/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72-u-boot.dtsi new file mode 100644 index 00000000000..b64b21fa450 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72-u-boot.dtsi @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8qm-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +&{/mu@5d1d0000/iomuxc/imx8qm-mek} { + u-boot,dm-spl; +}; + +&pinctrl_lpuart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio1 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio2 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio5 { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart2 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&lpuart2 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + u-boot,dm-spl; +}; + +&usbphynop1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&wu { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72.dts b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72.dts new file mode 100644 index 00000000000..ce3e2a1d99e --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek-cockpit-a72.dts @@ -0,0 +1,406 @@ +/* + * Copyright 2017-2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "fsl-imx8qm-cockpit-a72.dtsi" + +/ { + model = "Freescale i.MX8QM MEK"; + compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + + aliases { + gpio8 = &max7322; + }; + + chosen { + bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200"; + stdout-path = &lpuart2; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + status = "disabled"; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&gpio1 13 0>; + enable-active-high; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8qm-mek { + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART0_RTS_B_DMA_UART2_RX 0x06000020 + SC_P_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { +}; + +&gpio2 { +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { +}; + +&gpio5 { +}; + +&gpio6 { + status = "okay"; +}; + +&gpio7 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "disabled"; +}; + +&usbotg3 { + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + /delete-property/ iommus; + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + +&lpuart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + }; +}; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on = <&epdev_on>; + status = "okay"; +}; + +&sata { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + /delete-property/ iommus; + status = "okay"; +}; + +&tsens { + tsens-num = <6>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 5>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&pmic_alert0>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&display { + ports = <&dpu2_disp0>, <&dpu2_disp1>; +}; + + +/delete-node/ &dpu1; +/delete-node/ &fec1; +/delete-node/ &ldb1; +/delete-node/ &isi_0; +/delete-node/ &lpuart0; +/delete-node/ &lpuart1; +/delete-node/ &lpuart3; +/delete-node/ &lpuart4; +/delete-node/ &i2c2; +/delete-node/ &i2c3; +/delete-node/ &i2c4; +/delete-node/ &i2c1_lvds0; +/delete-node/ &usdhc2; +/delete-node/ &usdhc3; +/delete-node/ &flexspi0; +/delete-node/ &dpu1_intsteer; +/delete-node/ &lvds_region1; +/delete-node/ &ldb1_phy; +/delete-node/ &hdmi; +/delete-node/ &i2c0_hdmi; +/delete-node/ &irqsteer_lvds0; +/delete-node/ &mipi_dsi1; +/delete-node/ &mipi_dsi_bridge1; +/delete-node/ &i2c0_mipi_dsi0; +/delete-node/ &lpspi0; +/delete-node/ &mlb; +/delete-node/ &pciea; +/delete-node/ &pcieb; +/delete-node/ &pinctrl_lvds0_lpi2c1; diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi index 9e0d264b71f..13f29109a1d 100644 --- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi @@ -3,6 +3,29 @@ * Copyright 2018 NXP */ +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; +}; + &{/imx8qm-pm} { u-boot,dm-spl; @@ -20,6 +43,38 @@ u-boot,dm-spl; }; +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qm-mek} { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + &pd_lsio { u-boot,dm-spl; }; @@ -56,6 +111,10 @@ u-boot,dm-spl; }; +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + &pd_conn { u-boot,dm-spl; }; @@ -80,6 +139,38 @@ u-boot,dm-spl; }; +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&pd_caam { + u-boot,dm-spl; +}; + +&pd_caam_jr1 { + u-boot,dm-spl; +}; + +&pd_caam_jr2 { + u-boot,dm-spl; +}; + +&pd_caam_jr3 { + u-boot,dm-spl; +}; + &gpio0 { u-boot,dm-spl; }; @@ -116,6 +207,30 @@ u-boot,dm-spl; }; +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-spl; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-spl; +}; + &usdhc1 { u-boot,dm-spl; mmc-hs400-1_8v; @@ -126,3 +241,55 @@ sd-uhs-sdr104; sd-uhs-ddr50; }; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&wu { + u-boot,dm-spl; +}; + +&fec1 { + phy-mode = "rgmii-id"; +}; + +&fec2 { + phy-mode = "rgmii-id"; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qm-mek-xen.dts b/arch/arm/dts/fsl-imx8qm-mek-xen.dts new file mode 100644 index 00000000000..56a3e085269 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qm-mek-xen.dts @@ -0,0 +1,86 @@ +/* + * Copyright 2018-2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "fsl-imx8qm-mek.dts" +#include "fsl-imx8qm-mek-u-boot.dtsi" + +/ { + chosen { + bootargs = "console=hvc0 earlycon=hvc0 androidboot.console=hvc0 androidboot.android_dt_dir=/proc/device-tree/firmware/android/ androidboot.selinux=permissive"; + }; +}; + +&usdhc2 { + status = "disabled"; +}; + +&gpio1 { + /delete-property/ power-domains; +}; + +&gpio2 { + status = "disabled"; +}; + +&gpio4 { + /delete-property/ power-domains; + status = "okay"; +}; + +&gpio5 { + status = "disabled"; +}; + +&usbotg3 { + status = "disabled"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + status = "disabled"; +}; + +&flexspi0 { + status = "disabled"; +}; + +&i2c0 { + status = "disabled"; +}; + +&i2c1_lvds0 { + status = "disabled"; +}; + +&i2c1_lvds1 { + status = "disabled"; +}; + +&lpspi0 { + status = "disabled"; +}; + +&lpuart0 { + compatible = "xen,xen"; + /delete-property/ power-domains; + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&mu { + reg = <0x0 0x5d1d0000 0x0 0x10000>; +}; diff --git a/arch/arm/dts/fsl-imx8qm-mek.dts b/arch/arm/dts/fsl-imx8qm-mek.dts index 63908ba6bf1..9df4ab47f0c 100644 --- a/arch/arm/dts/fsl-imx8qm-mek.dts +++ b/arch/arm/dts/fsl-imx8qm-mek.dts @@ -6,25 +6,56 @@ /dts-v1/; #include "fsl-imx8qm.dtsi" -#include "fsl-imx8qm-mek-u-boot.dtsi" / { - model = "Freescale i.MX8QM MEK"; + model = "NXP i.MX8QM MEK"; compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; + aliases { + gpio8 = &max7322; + }; + chosen { - bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + bootargs = "console=ttyLP0,115200 earlycon"; stdout-path = &lpuart0; }; - reg_usdhc2_vmmc: usdhc2_vmmc { - compatible = "regulator-fixed"; - regulator-name = "sw-3p3-sd1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; - off-on-delay = <4800>; - enable-active-high; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <4800>; + enable-active-high; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_wlreg_on>; + pinctrl-1 = <&pinctrl_wlreg_on_sleep>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&gpio1 13 0>; + enable-active-high; + }; }; }; @@ -35,9 +66,12 @@ imx8qm-mek { pinctrl_hog: hoggrp { fsl,pins = < - SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c - SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c - SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x06000021 + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x06000021 + SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x06000021 + SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x06000021 + SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x06000021 >; }; @@ -79,6 +113,27 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + pinctrl_lpuart0: lpuart0grp { fsl,pins = < SC_P_UART0_RX_DMA_UART0_RX 0x06000020 @@ -86,6 +141,36 @@ >; }; + pinctrl_i2c0: i2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 + >; + }; + + pinctrl_pciea: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + >; + }; + + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 @@ -122,20 +207,79 @@ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 >; }; + + pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c + SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c + SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_wlreg_on: wlregongrp{ + fsl,pins = < + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 + >; + }; + + pinctrl_wlreg_on_sleep: wlregon_sleepgrp{ + fsl,pins = < + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x07800000 + >; + }; }; }; +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + &usdhc1 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; non-removable; status = "okay"; }; &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; @@ -168,17 +312,202 @@ reg = <1>; at803x,eee-disabled; at803x,vddio-1p8v; - status = "disabled"; }; }; }; +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + typec_ptn5110: typec@50 { + compatible = "usb,tcpci"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + reg = <0x51>; + interrupt-parent = <&gpio4>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + src-pdos = <0x380190c8 0x3803c0c8>; + port-type = "drp"; + sink-disable; + default-role = "source"; + status = "okay"; + }; +}; + &lpuart0 { /* console */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; status = "okay"; }; -&gpio1 { +&i2c1_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0_lpi2c1>; + clock-frequency = <100000>; status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + clock-lanes = <3>; + data-lanes = <0 1 2 4>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&i2c1_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + }; }; + +&pciea{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + disable-gpio = <&gpio4 9 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + epdev_on = <&epdev_on>; + status = "okay"; +}; + +&sata { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pciea>; + clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&tsens { + tsens-num = <6>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 5>; + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&pmic_alert0>; + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&dpu1 { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hfront-porch = <220>; + hback-porch = <110>; + hsync-len = <40>; + vback-porch = <5>; + vfront-porch = <20>; + vsync-len = <5>; + }; + }; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; + diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi index 88aeaf65b31..1e2314b0fe2 100644 --- a/arch/arm/dts/fsl-imx8qm.dtsi +++ b/arch/arm/dts/fsl-imx8qm.dtsi @@ -5,12 +5,15 @@ #include #include "fsl-imx8-ca53.dtsi" +#include "fsl-imx8-ca72.dtsi" #include #include #include +#include #include #include #include +#include / { compatible = "fsl,imx8qm"; @@ -21,6 +24,15 @@ aliases { ethernet0 = &fec1; ethernet1 = &fec2; + dsiphy0 = &mipi_dsi_phy1; + dsiphy1 = &mipi_dsi_phy2; + mipidsi0 = &mipi_dsi1; + mipidsi1 = &mipi_dsi2; + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; gpio0 = &gpio0; gpio1 = &gpio1; gpio2 = &gpio2; @@ -29,19 +41,25 @@ gpio5 = &gpio5; gpio6 = &gpio6; gpio7 = &gpio7; - serial0 = &lpuart0; - serial1 = &lpuart1; - serial2 = &lpuart2; - serial3 = &lpuart3; - serial4 = &lpuart4; mmc0 = &usdhc1; mmc1 = &usdhc2; mmc2 = &usdhc3; + usb0 = &usbotg1; + usbphy0 = &usbphy1; + usb1 = &usbotg3; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; + i2c6 = &i2c1_lvds0; + i2c8 = &i2c1_lvds1; + spi0 = &flexspi0; + pci0 = &pciea; + display0 = &ldb1; + display1 = &ldb2; + video0 = &dpu1; + video1 = &dpu2; }; memory@80000000 { @@ -50,6 +68,63 @@ /* DRAM space - 1, size : 1 GB DRAM */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * reserved-memory layout + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + + decoder_boot: decoder_boot@0x84000000 { + no-map; + reg = <0 0x84000000 0 0x2000000>; + }; + encoder_boot: encoder_boot@0x86000000 { + no-map; + reg = <0 0x86000000 0 0x400000>; + }; + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; + }; + rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; + }; + decoder_rpc: decoder_rpc@0x92000000 { + no-map; + reg = <0 0x92000000 0 0x200000>; + }; + encoder_rpc: encoder_rpc@0x92200000 { + no-map; + reg = <0 0x92200000 0 0x200000>; + }; + dsp_reserved: dsp@0x92400000 { + no-map; + reg = <0 0x92400000 0 0x2000000>; + }; + encoder_reserved: encoder_reserved@0x94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x96000000 0 0x3c000000>; + linux,cma-default; + }; + + }; + gic: interrupt-controller@51a00000 { compatible = "arm,gic-v3"; reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ @@ -64,12 +139,28 @@ interrupt-parent = <&gic>; }; + mu8: mu@5d230000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d230000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu8a>; + status = "okay"; + }; + + mu9: mu@5d240000 { + compatible = "fsl,imx-m4-mu"; + reg = <0x0 0x5d240000 0x0 0x10000>; + interrupts = ; + power-domains = <&pd_lsio_mu9a>; + status = "okay"; + }; + mu: mu@5d1c0000 { compatible = "fsl,imx8-mu"; reg = <0x0 0x5d1c0000 0x0 0x10000>; interrupts = ; interrupt-parent = <&gic>; - fsl,scu_ap_mu_id = <0>; + #mbox-cells = <4>; status = "okay"; clk: clk { @@ -82,482 +173,131 @@ }; }; - imx8qm-pm { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - pd_lsio: PD_LSIO { - compatible = "nxp,imx8-pd"; - reg = ; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pd_lsio_gpio0: PD_LSIO_GPIO_0 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio1: PD_LSIO_GPIO_1 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio2: PD_LSIO_GPIO_2 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio3: PD_LSIO_GPIO_3 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio4: PD_LSIO_GPIO_4 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio5: PD_LSIO_GPIO_5{ - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio6:PD_LSIO_GPIO_6 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - pd_lsio_gpio7: PD_LSIO_GPIO_7 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_lsio>; - }; - }; - - pd_conn: PD_CONN { - compatible = "nxp,imx8-pd"; - reg = ; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pd_conn_sdch0: PD_CONN_SDHC_0 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - }; - pd_conn_sdch1: PD_CONN_SDHC_1 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - }; - pd_conn_sdch2: PD_CONN_SDHC_2 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - }; - pd_conn_enet0: PD_CONN_ENET_0 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - wakeup-irq = <258>; - }; - pd_conn_enet1: PD_CONN_ENET_1 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_conn>; - fsl,wakeup_irq = <262>; - }; - }; - - pd_dma: PD_DMA { - compatible = "nxp,imx8-pd"; - reg = ; - #power-domain-cells = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pd_dma_lpi2c0: PD_DMA_I2C_0 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpi2c1: PD_DMA_I2C_1 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpi2c2:PD_DMA_I2C_2 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpi2c3: PD_DMA_I2C_3 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpi2c4: PD_DMA_I2C_4 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - }; - pd_dma_lpuart0: PD_DMA_UART0 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - wakeup-irq = <345>; - }; - pd_dma_lpuart1: PD_DMA_UART1 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - wakeup-irq = <346>; - }; - pd_dma_lpuart2: PD_DMA_UART2 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - wakeup-irq = <347>; - }; - pd_dma_lpuart3: PD_DMA_UART3 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - wakeup-irq = <348>; - }; - pd_dma_lpuart4: PD_DMA_UART4 { - reg = ; - #power-domain-cells = <0>; - power-domains = <&pd_dma>; - wakeup-irq = <349>; - }; - }; + mu13: mu13@5d280000 { + compatible = "fsl,imx8-mu-dsp"; + reg = <0x0 0x5d280000 0x0 0x10000>; + interrupts = ; + fsl,dsp_ap_mu_id = <13>; + status = "okay"; }; - i2c0: i2c@5a800000 { - compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x0 0x5a800000 0x0 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&clk IMX8QM_I2C0_CLK>, - <&clk IMX8QM_I2C0_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_I2C0_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c0>; - status = "disabled"; + mu_m0: mu_m0@2d000000 { + compatible = "fsl,imx8-mu0-vpu-m0"; + reg = <0x0 0x2d000000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <16>; + status = "okay"; }; - i2c1: i2c@5a810000 { - compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x0 0x5a810000 0x0 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&clk IMX8QM_I2C1_CLK>, - <&clk IMX8QM_I2C1_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_I2C1_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c1>; - status = "disabled"; + mu1_m0: mu1_m0@2d020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x0 0x2d020000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <17>; + status = "okay"; }; - i2c2: i2c@5a820000 { - compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x0 0x5a820000 0x0 0x4000>; - interrupts = ; - interrupt-parent = <&gic>; - clocks = <&clk IMX8QM_I2C2_CLK>, - <&clk IMX8QM_I2C2_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_I2C2_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c2>; - status = "disabled"; + mu2_m0: mu2_m0@2d040000 { + compatible = "fsl,imx8-mu2-vpu-m0"; + reg = <0x0 0x2d040000 0x0 0x20000>; + interrupts = ; + fsl,vpu_ap_mu_id = <18>; + status = "okay"; }; - i2c3: i2c@5a830000 { - compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x0 0x5a830000 0x0 0x4000>; - interrupts = ; + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ + clock-frequency = <8000000>; interrupt-parent = <&gic>; - clocks = <&clk IMX8QM_I2C3_CLK>, - <&clk IMX8QM_I2C3_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_I2C3_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c3>; - status = "disabled"; }; - i2c4: i2c@5a840000 { - compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c"; - reg = <0x0 0x5a840000 0x0 0x4000>; - interrupts = ; + smmu: iommu@51400000 { + compatible = "arm,mmu-500"; interrupt-parent = <&gic>; - clocks = <&clk IMX8QM_I2C4_CLK>, - <&clk IMX8QM_I2C4_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_I2C4_CLK>; - assigned-clock-rates = <24000000>; - power-domains = <&pd_dma_lpi2c4>; - status = "disabled"; - }; - - gpio0: gpio@5d080000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d080000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio0>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@5d090000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d090000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio1>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@5d0a0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0a0000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@5d0b0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0b0000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio3>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio4: gpio@5d0c0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0c0000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio4>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio5: gpio@5d0d0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0d0000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio5>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio6: gpio@5d0e0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0e0000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio6>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio7: gpio@5d0f0000 { - compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio"; - reg = <0x0 0x5d0f0000 0x0 0x10000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - power-domains = <&pd_lsio_gpio7>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - lpuart0: serial@5a060000 { - compatible = "fsl,imx8qm-lpuart"; - reg = <0x0 0x5a060000 0x0 0x1000>; - interrupts = ; - clocks = <&clk IMX8QM_UART0_CLK>, - <&clk IMX8QM_UART0_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_UART0_CLK>; - assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart0>; - status = "disabled"; + reg = <0 0x51400000 0 0x40000>; + #global-interrupts = <1>; + #iommu-cells = <2>; + interrupts = <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>, + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>; }; - lpuart1: serial@5a070000 { - compatible = "fsl,imx8qm-lpuart"; - reg = <0x0 0x5a070000 0x0 0x1000>; - interrupts = ; - clocks = <&clk IMX8QM_UART1_CLK>, - <&clk IMX8QM_UART1_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_UART1_CLK>; - assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart1>; - status = "disabled"; - }; - - lpuart2: serial@5a080000 { - compatible = "fsl,imx8qm-lpuart"; - reg = <0x0 0x5a080000 0x0 0x1000>; - interrupts = ; - clocks = <&clk IMX8QM_UART2_CLK>, - <&clk IMX8QM_UART2_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_UART2_CLK>; - assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart2>; - status = "disabled"; - }; - - lpuart3: serial@5a090000 { - compatible = "fsl,imx8qm-lpuart"; - reg = <0x0 0x5a090000 0x0 0x1000>; - interrupts = ; - clocks = <&clk IMX8QM_UART3_CLK>, - <&clk IMX8QM_UART3_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_UART3_CLK>; - assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart3>; - status = "disabled"; + cci: cci@52090000 { + compatible = "arm,cci-400"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x52090000 0 0x1000>; + ranges = <0 0 0x52090000 0x10000>; + + pmu@9000 { + compatible = "arm,cci-400-pmu,r1", + "arm,cci-400-pmu"; + reg = <0x9000 0x4000>; + interrupts = , + , + , + , + , + ; + interrupt-parent = <&gic>; + }; }; - lpuart4: serial@5a0a0000 { - compatible = "fsl,imx8qm-lpuart"; - reg = <0x0 0x5a0a0000 0x0 0x1000>; - interrupts = ; - clocks = <&clk IMX8QM_UART4_CLK>, - <&clk IMX8QM_UART4_IPG_CLK>; - clock-names = "per", "ipg"; - assigned-clocks = <&clk IMX8QM_UART4_CLK>; - assigned-clock-rates = <80000000>; - power-domains = <&pd_dma_lpuart4>; - status = "disabled"; - }; + #include "fsl-imx8qm-device.dtsi" +}; - usdhc1: usdhc@5b010000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x0 0x5b010000 0x0 0x10000>; - clocks = <&clk IMX8QM_SDHC0_IPG_CLK>, - <&clk IMX8QM_SDHC0_CLK>, - <&clk IMX8QM_CLK_DUMMY>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX8QM_SDHC0_DIV>; - assigned-clock-rates = <400000000>; - power-domains = <&pd_conn_sdch0>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; +&A53_0 { + operating-points = < + /* kHz uV */ + /* voltage is maintained by SCFW, so no need here */ + 1200000 0 + 1104000 0 + 900000 0 + 600000 0 + >; + clocks = <&clk IMX8QM_A53_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; + /delete-property/ cpu-idle-states; +}; - usdhc2: usdhc@5b020000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x0 0x5b020000 0x0 0x10000>; - clocks = <&clk IMX8QM_SDHC1_IPG_CLK>, - <&clk IMX8QM_SDHC1_CLK>, - <&clk IMX8QM_CLK_DUMMY>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX8QM_SDHC1_DIV>; - assigned-clock-rates = <200000000>; - power-domains = <&pd_conn_sdch1>; - fsl,tuning-start-tap = <20>; - fsl,tuning-step= <2>; - status = "disabled"; - }; +&A72_0 { + operating-points = < + /* kHz uV */ + /* voltage is maintained by SCFW, so no need here */ + 1596000 0 + 1296000 0 + 1056000 0 + 600000 0 + >; + clocks = <&clk IMX8QM_A72_DIV>; + clock-latency = <61036>; + #cooling-cells = <2>; + /delete-property/ cpu-idle-states; +}; - usdhc3: usdhc@5b030000 { - compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; - interrupt-parent = <&gic>; - interrupts = ; - reg = <0x0 0x5b030000 0x0 0x10000>; - clocks = <&clk IMX8QM_SDHC2_IPG_CLK>, - <&clk IMX8QM_SDHC2_CLK>, - <&clk IMX8QM_CLK_DUMMY>; - clock-names = "ipg", "per", "ahb"; - assigned-clocks = <&clk IMX8QM_SDHC2_DIV>; - assigned-clock-rates = <200000000>; - power-domains = <&pd_conn_sdch2>; - status = "disabled"; - }; +&A53_1 { + /delete-property/ cpu-idle-states; +}; - fec1: ethernet@5b040000 { - compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec"; - reg = <0x0 0x5b040000 0x0 0x10000>; - interrupts = , - , - , - ; - clocks = <&clk IMX8QM_ENET0_IPG_CLK>, - <&clk IMX8QM_ENET0_AHB_CLK>, - <&clk IMX8QM_ENET0_RGMII_TX_CLK>, - <&clk IMX8QM_ENET0_PTP_CLK>, - <&clk IMX8QM_ENET0_TX_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", - "enet_2x_txclk"; - assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>, - <&clk IMX8QM_ENET0_REF_DIV>; - assigned-clock-rates = <250000000>, <125000000>; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - fsl,wakeup_irq = <0>; - power-domains = <&pd_conn_enet0>; - status = "disabled"; - }; +&A53_2 { + /delete-property/ cpu-idle-states; +}; - fec2: ethernet@5b050000 { - compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec"; - reg = <0x0 0x5b050000 0x0 0x10000>; - interrupts = , - , - , - ; - clocks = <&clk IMX8QM_ENET1_IPG_CLK>, - <&clk IMX8QM_ENET1_AHB_CLK>, - <&clk IMX8QM_ENET1_RGMII_TX_CLK>, - <&clk IMX8QM_ENET1_PTP_CLK>, - <&clk IMX8QM_ENET1_TX_CLK>; - clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", - "enet_2x_txclk"; - assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>, - <&clk IMX8QM_ENET1_REF_DIV>; - assigned-clock-rates = <250000000>, <125000000>; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; - fsl,wakeup_irq = <0>; - power-domains = <&pd_conn_enet1>; - status = "disabled"; - }; +&A53_3 { + /delete-property/ cpu-idle-states; }; -&A53_0 { - clocks = <&clk IMX8QM_A53_DIV>; +&A72_1 { + /delete-property/ cpu-idle-states; }; diff --git a/arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi new file mode 100644 index 00000000000..ee88f322b60 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-17x17-val-u-boot.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/ { + aliases { + usbgadget0 = &usbg1; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; +}; + +&{/imx8qx-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qxp-val} { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&fec1 { + phy-mode = "rgmii-id"; +}; + +&fec2 { + phy-mode = "rgmii-id"; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/fsl-imx8qxp-17x17-val.dts b/arch/arm/dts/fsl-imx8qxp-17x17-val.dts new file mode 100644 index 00000000000..4ee085f9f19 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-17x17-val.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + * + */ + +#include "fsl-imx8qxp-lpddr4-val.dts" + +/ { + model = "NXP i.MX8QXP 17x17 Validation board"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c3 { + status = "disabled"; + + /delete-node/ gpio@18; + /delete-node/ gpio@19; +}; + +&usdhc2 { + status = "disabled"; +}; + +&usbotg3 { + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts new file mode 100644 index 00000000000..b9175345f90 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-gpmi-nand.dts @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + */ + +#include "fsl-imx8qxp-lpddr4-val.dts" +#include "fsl-imx8qxp-lpddr4-val-u-boot.dtsi" + +&iomuxc { + imx8qxp-val { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_NAND_READY_B 0x0e00004c + SC_P_EMMC0_DATA0_CONN_NAND_DATA00 0x0e00004c + SC_P_EMMC0_DATA1_CONN_NAND_DATA01 0x0e00004c + SC_P_EMMC0_DATA2_CONN_NAND_DATA02 0x0e00004c + SC_P_EMMC0_DATA3_CONN_NAND_DATA03 0x0e00004c + SC_P_EMMC0_DATA4_CONN_NAND_DATA04 0x0e00004c + SC_P_EMMC0_DATA5_CONN_NAND_DATA05 0x0e00004c + SC_P_EMMC0_DATA6_CONN_NAND_DATA06 0x0e00004c + SC_P_EMMC0_DATA7_CONN_NAND_DATA07 0x0e00004c + SC_P_EMMC0_STROBE_CONN_NAND_CLE 0x0e00004c + SC_P_EMMC0_RESET_B_CONN_NAND_WP_B 0x0e00004c + + SC_P_USDHC1_DATA0_CONN_NAND_CE1_B 0x0e00004c + SC_P_USDHC1_DATA2_CONN_NAND_WE_B 0x0e00004c + SC_P_USDHC1_DATA3_CONN_NAND_ALE 0x0e00004c + SC_P_USDHC1_CMD_CONN_NAND_CE0_B 0x0e00004c + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + SC_P_USDHC1_CD_B_CONN_NAND_DQS 0x0e00004c + SC_P_USDHC1_VSELECT_CONN_NAND_RE_B 0x0e00004c + + >; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +/* Disabled the usdhc1/usdhc2 since pin conflict */ +&usdhc1 { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi new file mode 100644 index 00000000000..b54ee4d8495 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val-u-boot.dtsi @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; + +}; + +&{/imx8qx-pm} { + + u-boot,dm-spl; +}; + +&mu { + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qxp-val} { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + +&pd_lsio { + u-boot,dm-spl; +}; + +&pd_lsio_gpio0 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio3 { + u-boot,dm-spl; +}; + +&pd_lsio_gpio4 { + u-boot,dm-spl; +}; + +&pd_conn { + u-boot,dm-spl; +}; + +&pd_dma { + u-boot,dm-spl; +}; + +&pd_dma_lpuart0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch0 { + u-boot,dm-spl; +}; + +&pd_conn_sdch1 { + u-boot,dm-spl; +}; + +&pd_conn_sdch2 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&gpio0 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&lpuart0 { + u-boot,dm-spl; +}; + +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-spl; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&wu { + u-boot,dm-spl; +}; + +&fec1 { + phy-mode = "rgmii-id"; +}; + +&fec2 { + phy-mode = "rgmii-id"; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts b/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts new file mode 100644 index 00000000000..77e27a02058 --- /dev/null +++ b/arch/arm/dts/fsl-imx8qxp-lpddr4-val.dts @@ -0,0 +1,470 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "fsl-imx8qxp.dtsi" + +/ { + model = "NXP i.MX8QXP LPDDR4 VAL"; + compatible = "fsl,imx8qxp-lpddr4-val", "fsl,imx8qxp"; + + aliases { + gpio8 = &pca9557_a; + gpio9 = &pca9557_b; + gpio10 = &pca9557_c; + }; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <300>; + off-on-delay-us = <5000>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx8qxp-val { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 + >; + }; + + pinctrl_lpi2c1: lpi1cgrp { + fsl,pins = < + SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 + >; + }; + + pinctrl_lpi2c3: lpi2cgrp { + fsl,pins = < + SC_P_SPI3_CS1_ADMA_I2C3_SCL 0x06000020 + SC_P_MCLK_IN1_ADMA_I2C3_SDA 0x06000020 + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x0600002c + SC_P_UART0_TX_ADMA_UART0_TX 0x0600002c + >; + }; + + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_ADMA_SPI0_SCK 0x600004c + SC_P_SPI0_SDO_ADMA_SPI0_SDO 0x600004c + SC_P_SPI0_SDI_ADMA_SPI0_SDI 0x600004c + >; + }; + + pinctrl_lpspi0_cs: lpspi0cs { + fsl,pins = < + SC_P_SPI0_CS0_LSIO_GPIO1_IO08 0x21 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0 &pinctrl_lpspi0_cs>; + cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>, <0>, <0>, <0>; + spi-max-frequency = <1000000>; + status = "okay"; + + flash: at45db041e@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <1000000>; + reg = <0>; + }; +}; + + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "okay"; + phy-reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + at803x,eee-disabled; + at803x,vddio-1p8v; + status = "disabled"; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + status = "disabled"; + phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; +}; + +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + status = "okay"; + + pca9557_a: gpio@18 { + compatible = "nxp,pca9557"; + reg = <0x18>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_b: gpio@19 { + compatible = "nxp,pca9557"; + reg = <0x19>; + gpio-controller; + #gpio-cells = <2>; + }; + + pca9557_c: gpio@1b { + compatible = "nxp,pca9557"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + it6263-0@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; + + it6263-1@4c { + compatible = "ITE,it6263"; + reg = <0x4c>; + }; +}; + +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi index 701af4434d5..5327485bfad 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi +++ b/arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi @@ -3,6 +3,30 @@ * Copyright 2018 NXP */ +/ { + + aliases { + usbhost1 = &usbh3; + usbgadget0 = &usbg1; + }; + + usbh3: usbh3 { + compatible = "Cadence,usb3-host"; + dr_mode = "host"; + cdns3,usb = <&usbotg3>; + status = "okay"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + u-boot,dm-spl; + }; + +}; + &{/imx8qx-pm} { u-boot,dm-spl; @@ -20,6 +44,38 @@ u-boot,dm-spl; }; +&{/regulators} { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&{/mu@5d1c0000/iomuxc/imx8qxp-mek} { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_lpuart0 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_flexspi0 { + u-boot,dm-spl; +}; + &pd_lsio { u-boot,dm-spl; }; @@ -80,6 +136,42 @@ u-boot,dm-spl; }; +&pd_conn_usbotg0 { + u-boot,dm-spl; +}; + +&pd_conn_usbotg0_phy { + u-boot,dm-spl; +}; + +&pd_lsio_flexspi0 { + u-boot,dm-spl; +}; + +&pd_conn_usb2 { + u-boot,dm-spl; +}; + +&pd_conn_usb2_phy { + u-boot,dm-spl; +}; + +&pd_caam { + u-boot,dm-spl; +}; + +&pd_caam_jr1 { + u-boot,dm-spl; +}; + +&pd_caam_jr2 { + u-boot,dm-spl; +}; + +&pd_caam_jr3 { + u-boot,dm-spl; +}; + &gpio0 { u-boot,dm-spl; }; @@ -116,6 +208,30 @@ u-boot,dm-spl; }; +&usbmisc1 { + u-boot,dm-spl; +}; + +&usbphy1 { + u-boot,dm-spl; +}; + +&usbotg1 { + u-boot,dm-spl; +}; + +&usbotg3 { + phys = <&usbphynop1>; + u-boot,dm-spl; +}; + +&usbphynop1 { + compatible = "cdns,usb3-phy"; + reg = <0x0 0x5B160000 0x0 0x40000>; + #phy-cells = <0>; + u-boot,dm-spl; +}; + &usdhc1 { u-boot,dm-spl; mmc-hs400-1_8v; @@ -126,3 +242,64 @@ sd-uhs-sdr104; sd-uhs-ddr50; }; + +&flexspi0 { + u-boot,dm-spl; +}; + +&flash0 { + u-boot,dm-spl; +}; + +&i2c1 { + compatible = "fsl,imx8qm-lpi2c", "fsl,imx-virt-i2c"; +}; + +&{/i2c@5a810000/i2cswitch@71} { + compatible = "nxp,pca9646", "fsl,imx-virt-i2c-mux"; + virtual-bus-seq = <12>; +}; + +&wu { + u-boot,dm-spl; +}; + +&fec1 { + phy-mode = "rgmii-id"; +}; + +&fec2 { + phy-mode = "rgmii-id"; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&sec_jr3 { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/fsl-imx8qxp-mek.dts b/arch/arm/dts/fsl-imx8qxp-mek.dts index 4f35fbe31db..86aa8684798 100644 --- a/arch/arm/dts/fsl-imx8qxp-mek.dts +++ b/arch/arm/dts/fsl-imx8qxp-mek.dts @@ -6,25 +6,59 @@ /dts-v1/; #include "fsl-imx8qxp.dtsi" -#include "fsl-imx8qxp-mek-u-boot.dtsi" / { - model = "Freescale i.MX8QXP MEK"; + model = "NXP i.MX8QXP MEK"; compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; + aliases { + i2c4 = &bb_i2c1; + i2c5 = &mfi_i2c1; + i2c6 = &i2cexp1_i2c1; + i2c7 = &i2cexp2_i2c1; + gpio8 = &pca9557_a; + gpio9 = &pca9557_b; + }; + chosen { - bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + bootargs = "console=ttyLP0,115200 earlycon"; stdout-path = &lpuart0; }; - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { - compatible = "regulator-fixed"; - regulator-name = "SD1_SPWR"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; - off-on-delay = <3480>; - enable-active-high; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3480>; + }; + + epdev_on: fixedregulator@100 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "epdev_on"; + gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; }; @@ -40,45 +74,41 @@ >; }; - pinctrl_ioexp_rst: ioexp-rst-grp { - fsl,pins = < - SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 - >; - }; - pinctrl_fec1: fec1grp { fsl,pins = < - SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 - SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 - SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048 - SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048 - SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048 - SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048 - SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048 - SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048 - SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048 - SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048 - SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048 - SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048 - SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048 - SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 >; }; pinctrl_fec2: fec2grp { fsl,pins = < - SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048 - SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048 - SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048 - SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048 - SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048 - SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048 - SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048 - SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048 - SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048 - SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048 - SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048 - SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 + SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 + SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 + SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 + SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 + SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 >; }; @@ -131,6 +161,49 @@ SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 >; }; + + pinctrl_pcieb: pcieagrp{ + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 + SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 + SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 + SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 + SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 + SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 + SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 + SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 + SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 + SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 + SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 + SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 + SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 + SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 + SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 + SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 + >; + }; + + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 + >; + }; + + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 + >; + }; }; }; @@ -144,18 +217,49 @@ status = "okay"; }; +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +&flexspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; + pinctrl-0 = <&pinctrl_lpi2c1>; status = "okay"; i2cswitch@71 { compatible = "nxp,pca9646"; reg = <0x71>; + u-boot,i2c-offset-len = <0>; #address-cells = <1>; #size-cells = <0>; - reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; bb_i2c1: i2c@0 { #address-cells = <1>; @@ -196,17 +300,53 @@ }; }; -&usdhc1 { +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "okay"; + + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; + + port { + it6263_0_in: endpoint { + clock-lanes = <4>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1>; bus-width = <8>; non-removable; status = "okay"; }; &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; @@ -214,6 +354,17 @@ status = "okay"; }; +&pcieb{ + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb>; + clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; + power-on-gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + epdev_on = <&epdev_on>; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -240,3 +391,69 @@ }; }; }; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec2>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,ar8031-phy-fixup; + fsl,magic-packet; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hfront-porch = <220>; + hback-porch = <110>; + hsync-len = <40>; + vback-porch = <5>; + vfront-porch = <20>; + vsync-len = <5>; + }; + }; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&it6263_0_in>; + }; + }; + }; +}; diff --git a/arch/arm/dts/fsl-imx8qxp.dtsi b/arch/arm/dts/fsl-imx8qxp.dtsi index 1bffff1314e..5f4fde1ca7c 100644 --- a/arch/arm/dts/fsl-imx8qxp.dtsi +++ b/arch/arm/dts/fsl-imx8qxp.dtsi @@ -16,7 +16,7 @@ #include "fsl-imx8dxp.dtsi" / { - model = "Freescale i.MX8QXP"; + model = "NXP i.MX8QXP"; compatible = "fsl,imx8qxp"; cpus { diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi index 2894842cf25..7cfb8f10871 100644 --- a/arch/arm/dts/fsl-ls1012a.dtsi +++ b/arch/arm/dts/fsl-ls1012a.dtsi @@ -71,6 +71,50 @@ bus-width = <4>; }; + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", + "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x1700000 0x100000>; + reg = <0x00 0x1700000 0x0 0x100000>; + interrupts = <0 75 0x4>; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <0 71 0x4>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <0 72 0x4>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <0 73 0x4>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <0 74 0x4>; + }; + }; + gpio0: gpio@2300000 { compatible = "fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi new file mode 100644 index 00000000000..23816da8eeb --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 1xxx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC + * port 0 USXGMII. + */ +&slot1 { + #include "fsl-sch-30842.dtsi" +}; + +&enetc0 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi new file mode 100644 index 00000000000..c6558ae2e07 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 6xxx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using SCH-30842 cards with AQR112 PHY. + */ +&slot1 { + #include "fsl-sch-30842.dtsi" +}; + +&enetc0 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi new file mode 100644 index 00000000000..fb1836a8aef --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 7777 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using a SCH-30841 card with AQR412 10G quad PHY. + * + * Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1. + * Bottom port is port 0. + * Note that this is only usable for: + * - QDS boards WITHOUT lane B rework, + * - AQR412 card WITHOUT lane A -> lane C rework + * + * The following DTS assumes DIP SW5[1-3] = 000b. + */ +&slot1 { +#include "fsl-sch-30841.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi new file mode 100644 index 00000000000..1d02a3e11de --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 7xx7 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +&slot1 { +#include "fsl-sch-30841.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi new file mode 100644 index 00000000000..7d4702e4ff2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 8xxx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY in slot 1. + */ +&slot1 { + #include "fsl-sch-24801.dtsi" +}; + +&enetc0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi new file mode 100644 index 00000000000..c92dd1bd2e9 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 9999 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY. + * LS1028A QDS boards with lane B rework require two cards for the 4 switch + * ports, QDS boards without the lane B rework only require one card. + * + * Switch ports are routed as follows: + * Port 0 goes to 1st port of VSC8234 quad card in slot 1, + * Port 1: + * - if the QDS has had lane B rework, it is 1st port in slot 2, + * - otherwise it is 2nd port in slot 1. + * Port 2: + * - if DIP SW5[1] = 0 it is 3rd port in slot 1, + * - otherwise it is 1st port in slot 3. + * Port 3: + * - if DIP SW5[2-3] = 00b it is 4th port in slot 1, + * - if DIP SW5[2-3] = 01b it is 2nd port in slot 3, + * - if DIP SW5[2-3] = 11b it is 1st port in slot 4. + * + * The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two + * SCH-24801 cards are required in slots 1 and 2. + */ +&slot1 { + #include "fsl-sch-24801.dtsi" +}; + +&slot2 { + #include "fsl-sch-24801.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi new file mode 100644 index 00000000000..941f7472eb0 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 9999 + * + * Copyright 2019-2021 NXP Semiconductors + * + */ + +/* + * This set-up is using SCH-24801 cards with VSC8234 quad SGMII PHY. + * + * Switch ports are mapped 1:1 to VSC8234 card ports seated in slot 1. + * Top port is port 0. + * + * The following DTS assumes DIP SW5[1-3] = 000b. + */ + +&slot1 { + #include "fsl-sch-24801.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi new file mode 100644 index 00000000000..7e483e656e2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW x3xx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This + * is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up. + * + * We're including the normal .dsti file, not the reworked card .dtsi + * intentionally. We are using multiplexing of the 4 interfaces on a single + * lane and the rework doesn't actually disable any port. The rework is in fact + * needed, otherwise the PHY won't work with the default wiring on the QDS/PHY + * card. + */ +&slot2 { +#include "fsl-sch-30841.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi new file mode 100644 index 00000000000..49fffdb9cb2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW x5xx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2. + * This is only available on LS1028A QDS boards with lane B rework. + */ +&slot2 { + #include "fsl-sch-28021.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi new file mode 100644 index 00000000000..8347462f4cb --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 7777 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +&slot2 { +#include "fsl-sch-30842.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi new file mode 100644 index 00000000000..6be3b5094c8 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 7777 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +&slot3 { +#include "fsl-sch-30842.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 6cdcce1b92f..da89ff96e98 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -258,3 +258,6 @@ &mdio0 { status = "okay"; }; + +#include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi" +#include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi" diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index c7c725a4fc8..ad232c133c3 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -123,6 +123,45 @@ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = ; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + }; + pcie@1f0000000 { compatible = "pci-host-ecam-generic"; /* ECAM bus 0, HW has more space reserved but not populated */ diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index d8171bd03b4..6218fa68591 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -125,6 +125,49 @@ interrupts = <0 43 0x4>; }; + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", + "fsl,sec-v4.0"; + fsl,sec-era = <3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x1700000 0x100000>; + reg = <0x00 0x1700000 0x0 0x100000>; + interrupts = <0 75 0x4>; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <0 71 0x4>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <0 72 0x4>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <0 73 0x4>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <0 74 0x4>; + }; + }; + i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 9df419a87d8..ffc4082b52d 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -124,6 +124,49 @@ interrupts = <0 43 0x4>; }; + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", + "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x1700000 0x100000>; + reg = <0x00 0x1700000 0x0 0x100000>; + interrupts = <0 75 0x4>; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <0 71 0x4>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <0 72 0x4>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <0 73 0x4>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.4-job-ring", + "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <0 74 0x4>; + }; + }; + i2c0: i2c@2180000 { compatible = "fsl,vf610-i2c"; #address-cells = <1>; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 64caa600ad7..5c2d7eeac24 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -180,6 +180,45 @@ dr_mode = "host"; }; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = ; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + }; + pcie1: pcie@3400000 { compatible = "fsl,ls-pcie", "snps,dw-pcie"; reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */ diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index 7374d580e07..aa739279a8d 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -245,6 +245,45 @@ status = "disabled"; }; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <8>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <0 139 0x4>; /* Level high type */ + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <0 140 0x4>; /* Level high type */ + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <0 141 0x4>; /* Level high type */ + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <0 142 0x4>; /* Level high type */ + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <0 143 0x4>; /* Level high type */ + }; + }; + fsl_mc: fsl-mc@80c000000 { compatible = "fsl,qoriq-mc", "simple-mfd"; reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ diff --git a/arch/arm/dts/fsl-lx2160a-rdb.dts b/arch/arm/dts/fsl-lx2160a-rdb.dts index 5fbdd907017..a647d77a232 100644 --- a/arch/arm/dts/fsl-lx2160a-rdb.dts +++ b/arch/arm/dts/fsl-lx2160a-rdb.dts @@ -5,7 +5,7 @@ * Author: Priyanka Jain * Sriram Dash * - * Copyright 2018 NXP + * Copyright 2018-2021 NXP * */ @@ -21,6 +21,12 @@ }; }; +&dpmac2 { + status = "okay"; + phy-handle = <&cortina_phy>; + phy-connection-type = "xlaui4"; +}; + &dpmac3 { status = "okay"; phy-handle = <&aquantia_phy1>; @@ -33,6 +39,18 @@ phy-connection-type = "usxgmii"; }; +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy>; + phy-connection-type = "25g-aui"; +}; + &dpmac17 { status = "okay"; phy-handle = <&rgmii_phy1>; @@ -47,6 +65,11 @@ &emdio1 { status = "okay"; + + cortina_phy: ethernet-phy@0 { + reg = <0x0>; + }; + rgmii_phy1: ethernet-phy@1 { /* AR8035 PHY - "compatible" property not strictly needed */ compatible = "ethernet-phy-id004d.d072"; @@ -73,6 +96,14 @@ }; }; +&emdio2 { + status = "okay"; + inphi_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; +}; + &esdhc0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.dtsi index a6f0e9bc56b..1b1ef683b70 100644 --- a/arch/arm/dts/fsl-lx2160a.dtsi +++ b/arch/arm/dts/fsl-lx2160a.dtsi @@ -27,6 +27,45 @@ clock-output-names = "sysclk"; }; + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = ; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + }; + clockgen: clocking@1300000 { compatible = "fsl,ls2080a-clockgen"; reg = <0 0x1300000 0 0xa0000>; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi index 60f5a4ee435..d1e4a8567fc 100644 --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi @@ -5,7 +5,7 @@ * Some assumptions are made: * * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6) * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -56,3 +56,9 @@ reg = <0x3>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi index 8e11b0680a9..e9a743b3a24 100644 --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi @@ -6,7 +6,7 @@ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) * * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -59,3 +59,9 @@ reg = <0x1>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi index faf4285eaba..d9ad1c6a4b3 100644 --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi @@ -6,7 +6,7 @@ * * Mezzanine card M8 is connected to IO SLOT1 * (xlaui4 for DPMAC 1) * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -24,3 +24,9 @@ reg = <0x0>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts index 341610ccf4a..0ca30df8620 100644 --- a/arch/arm/dts/fsl-lx2162a-qds.dts +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -2,7 +2,7 @@ /* * NXP LX2162AQDS device tree source * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -135,3 +135,9 @@ reg = <2>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-sch-24801.dtsi b/arch/arm/dts/fsl-sch-24801.dtsi new file mode 100644 index 00000000000..304afdabc59 --- /dev/null +++ b/arch/arm/dts/fsl-sch-24801.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device tree fragment for RCW SCH-24801 card + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * SCH-24801 is a 4xSGMII add-on card used with various FSL QDS boards. + * It integrates a VSC8234 quad PHY which supports 4 SGMII interfaces. + * PHY addresses are 0x1c - 0x1f. + * On the card the first port is the top port (farthest from PEX connector). + */ +phy@1c { + reg = <0x1c>; +}; + +phy@1d { + reg = <0x1d>; +}; + +phy@1e { + reg = <0x1e>; +}; + +phy@1f { + reg = <0x1f>; +}; diff --git a/arch/arm/dts/fsl-sch-28021.dtsi b/arch/arm/dts/fsl-sch-28021.dtsi new file mode 100644 index 00000000000..584f3fa68cd --- /dev/null +++ b/arch/arm/dts/fsl-sch-28021.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device tree fragment for RCW SCH-28021 card + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * SCH-28021 is a QSGMII add-on card used with various FSL QDS boards. + * It integrates a VSC8514 quad PHY which supports 4 interfaces muxed on a + * single QSGMII lane. + * PHY addresses are 0x08 - 0x0b. + * On the card the first port is the top port (farthest from PEX connector). + */ +phy@08 { + reg = <0x08>; +}; + +phy@09 { + reg = <0x09>; +}; + +phy@0a { + reg = <0x0a>; +}; + +phy@0b { + reg = <0x0b>; +}; diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi new file mode 100644 index 00000000000..ca437d17828 --- /dev/null +++ b/arch/arm/dts/fsl-sch-30841.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device tree fragment for RCW SCH-30841 card + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * SCH-30841 is a 4 port add-on card used with various FSL QDS boards. + * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed + * together on a single lane or mapped 1:1 to serdes lanes. + * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI. + * PHY addresses are 0x00 - 0x03. + * On the card the first port is the bottom port (closest to PEX connector). + */ +phy@00 { + reg = <0x00>; + mdi-reversal = <1>; + smb-addr = <0x25>; +}; + +phy@01 { + reg = <0x01>; + mdi-reversal = <1>; + smb-addr = <0x26>; +}; + +phy@02 { + reg = <0x02>; + mdi-reversal = <1>; + smb-addr = <0x27>; +}; + +phy@03 { + reg = <0x03>; + mdi-reversal = <1>; + smb-addr = <0x28>; +}; diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi new file mode 100644 index 00000000000..fa0f2cdb109 --- /dev/null +++ b/arch/arm/dts/fsl-sch-30842.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device tree fragment for RCW SCH-30842 card + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * SCH-30842 is a single port add-on card used with various FSL QDS boards. + * It integrates a AQR112 PHY, which supports several protocols - SGMII, + * SGMII-2500, USXGMII, XFI. + * PHY address is 0x02. + */ +phy@02 { + reg = <0x02>; + mdi-reversal = <1>; + smb-addr = <0x25>; +}; diff --git a/arch/arm/dts/imx6dl-arm2.dts b/arch/arm/dts/imx6dl-arm2.dts new file mode 100644 index 00000000000..46abada5f4d --- /dev/null +++ b/arch/arm/dts/imx6dl-arm2.dts @@ -0,0 +1,260 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include +#include "imx6dl.dtsi" + +/ { + model = "i.MX6 DualLite Armadillo2 Board"; + compatible = "fsl,imx6q-arm2", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + + debug-led { + label = "Heartbeat"; + gpios = <&gpio3 25 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "disabled"; /* gpmi nand conflicts with SD */ + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbh2_1: usbh2grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 + >; + }; + + pinctrl_usbh2_2: usbh2grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 + >; + }; + + pinctrl_usbh3_1: usbh3grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 + >; + }; + + pinctrl_usbh3_2: usbh3grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc3 { + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + status = "okay"; +}; + +&usdhc4 { + non-removable; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dte-mode; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-sabreauto-ecspi.dts b/arch/arm/dts/imx6dl-sabreauto-ecspi.dts new file mode 100644 index 00000000000..45ae1628362 --- /dev/null +++ b/arch/arm/dts/imx6dl-sabreauto-ecspi.dts @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-sabreauto-gpmi-weim.dts b/arch/arm/dts/imx6dl-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000..ad2e937d4ff --- /dev/null +++ b/arch/arm/dts/imx6dl-sabreauto-gpmi-weim.dts @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6dl-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl-sabreauto.dts b/arch/arm/dts/imx6dl-sabreauto.dts index 660d52a245b..a2d11d1d83c 100644 --- a/arch/arm/dts/imx6dl-sabreauto.dts +++ b/arch/arm/dts/imx6dl-sabreauto.dts @@ -8,6 +8,35 @@ #include "imx6qdl-sabreauto.dtsi" / { - model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; + model = "i.MX6 DualLite/Solo SABRE Automotive Board"; compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; +&mxcfb1 { + status = "okay"; +}; +&mxcfb2 { + status = "okay"; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1200000 + 792000 1175000 + 396000 1175000 + >; +}; diff --git a/arch/arm/dts/imx6dl-sabresd.dts b/arch/arm/dts/imx6dl-sabresd.dts index cd6bbf22a16..8e8481ff59f 100644 --- a/arch/arm/dts/imx6dl-sabresd.dts +++ b/arch/arm/dts/imx6dl-sabresd.dts @@ -8,11 +8,146 @@ #include "imx6qdl-sabresd.dtsi" / { - model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; + model = "i.MX6 DualLite SABRE Smart Device Board"; compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; }; +&battery { + offset-charger = <1485>; + offset-discharger = <1464>; + offset-usb-charger = <1285>; +}; + +&iomuxc { + epdc { + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x80000000 + MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x80000000 + MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x80000000 + MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x80000000 + MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x80000000 + MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x80000000 + MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x80000000 + MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x80000000 + MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x80000000 + MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x80000000 + MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x80000000 + MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x80000000 + MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x80000000 + MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x80000000 + MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x80000000 + MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x80000000 + MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x80000000 + MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x80000000 + MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x80000000 + MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x80000000 + >; + }; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&i2c3 { + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <1>; + vpos_pwrup = <2>; + gvdd_pwrup = <1>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <1>; + vneg_pwrdn = <1>; + SENSOR-supply = <®_sensor>; + gpio_pmic_pwrgood = <&gpio2 21 0>; + gpio_pmic_vcom_ctrl = <&gpio3 17 0>; + gpio_pmic_wakeup = <&gpio3 20 0>; + gpio_pmic_v3p3 = <&gpio2 20 0>; + gpio_pmic_intr = <&gpio2 25 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + &ipu1_csi1_from_ipu1_csi1_mux { clock-lanes = <0>; data-lanes = <1 2>; }; + +&ldb { + lvds-channel@0 { + crtc = "ipu1-di0"; + }; + + lvds-channel@1 { + crtc = "ipu1-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&pxp { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6dl.dtsi b/arch/arm/dts/imx6dl.dtsi index f0607eb41df..269b451cf89 100644 --- a/arch/arm/dts/imx6dl.dtsi +++ b/arch/arm/dts/imx6dl.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // // Copyright 2013 Freescale Semiconductor, Inc. +// Copyright 2018 NXP #include #include "imx6dl-pinfunc.h" @@ -15,7 +16,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <0>; @@ -33,14 +34,17 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; @@ -51,56 +55,107 @@ device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 996000 1250000 - 792000 1175000 - 396000 1150000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; }; }; soc { - ocram: sram@900000 { + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, + <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>, + <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>, + <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>, + <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> , + <&clks IMX6QDL_CLK_PLL3_PFD1_540M>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m"; + interrupts = <0 107 0x04>, <0 112 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + fsl,max_ddr_freq = <400000000>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x905000 0x1B000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips1: aips-bus@2000000 { - iomuxc: iomuxc@20e0000 { - compatible = "fsl,imx6dl-iomuxc"; - }; + ocram_optee: sram@918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x918000 0x8000>; + overw_reg = <&ocram 0x905000 0x13000>; + }; + gpu: gpu@00130000 { + compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x10000000 0x0>, <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "phys_baseaddr", "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d"; + clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>, + <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>, + <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", + "gpu2d_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>; + reset-names = "gpu3d", "gpu2d"; + power-domains = <&pd_pu>; + }; + + aips1: aips-bus@2000000 { pxp: pxp@20f0000 { - reg = <0x020f0000 0x4000>; + compatible = "fsl,imx6dl-pxp-dma"; + reg = <0x20f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@20f4000 { - reg = <0x020f4000 0x4000>; + compatible = "fsl,imx6dl-epdc"; + reg = <0x20f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>; + clock-names = "epdc_axi", "epdc_pix"; + }; + + lcdif: lcdif@20f8000 { + reg = <0x20f8000 0x4000>; + interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; }; }; aips2: aips-bus@2100000 { + mipi_dsi: mipi@21e0000 { + compatible = "fsl,imx6dl-mipi-dsi"; + reg = <0x21e0000 0x4000>; + interrupts = <0 102 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; + }; + i2c4: i2c@21f8000 { #address-cells = <1>; #size-cells = <0>; @@ -122,6 +177,17 @@ compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>; }; + + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu_2d>, <&gpu_3d>; + }; +}; + +&dcic2 { + clocks = <&clks IMX6QDL_CLK_DCIC1 >, + <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/ + clock-names = "dcic", "disp-axi"; }; &gpio1 { @@ -295,6 +361,10 @@ compatible = "fsl,imx6dl-hdmi"; }; +&iomuxc { + compatible = "fsl,imx6dl-iomuxc"; +}; + &ipu1_csi1 { ipu1_csi1_from_ipu1_csi1_mux: endpoint { remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; @@ -302,12 +372,19 @@ }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb"; + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", "di0_sel", "di1_sel", - "di0", "di1"; + "di2_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; }; &mipi_csi { @@ -389,3 +466,7 @@ &vpu { compatible = "fsl,imx6dl-vpu", "cnm,coda960"; }; + +&vpu_fsl { + iramsize = <0>; +}; diff --git a/arch/arm/dts/imx6q-arm2.dts b/arch/arm/dts/imx6q-arm2.dts new file mode 100644 index 00000000000..e33f4f57f63 --- /dev/null +++ b/arch/arm/dts/imx6q-arm2.dts @@ -0,0 +1,260 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include +#include "imx6q.dtsi" + +/ { + model = "i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-arm2", "fsl,imx6q"; + + memory { + reg = <0x10000000 0x80000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + }; + + leds { + compatible = "gpio-leds"; + + debug-led { + label = "Heartbeat"; + gpios = <&gpio3 25 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "disabled"; /* gpmi nand conflicts with SD */ + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usbh2_1: usbh2grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030 + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030 + >; + }; + + pinctrl_usbh2_2: usbh2grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030 + >; + }; + + pinctrl_usbh3_1: usbh3grp-1 { + fsl,pins = < + MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030 + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030 + >; + }; + + pinctrl_usbh3_2: usbh3grp-2 { + fsl,pins = < + MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc3 { + cd-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + status = "okay"; +}; + +&usdhc4 { + non-removable; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dte-mode; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-pop-arm2.dts b/arch/arm/dts/imx6q-pop-arm2.dts new file mode 100644 index 00000000000..aee4f08b333 --- /dev/null +++ b/arch/arm/dts/imx6q-pop-arm2.dts @@ -0,0 +1,439 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include +#include "imx6q.dtsi" + +/ { + model = "i.MX6 Quad Armadillo2 Board"; + compatible = "fsl,imx6q-pop-arm2", "fsl,imx6q"; + + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + }; + + pwm-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 50000>; + power-supply = <®_lvds_3p3v>; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <94>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + power { + label = "Power Button"; + gpios = <&gpio3 30 1>; + linux,code = <116>; + gpio-key,wakeup; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds_share { + gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + linux,usable-memory = <0x10000000 0x20000000>, + <0x80000000 0x20000000>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str = "1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "okay"; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 0>; + enable-active-high; + }; + + reg_lvds_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "LVDS-3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + }; +}; + +&cpu0 { + fsl,arm-soc-shared = <1>; +}; + +&busfreq { + fsl,max_ddr_freq = <400000000>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds0"; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio3>; + interrupts = <31 2>; + wakeup-gpios = <&gpio3 31 0>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + max7310_a: gpio@1b { + compatible = "maxim,max7310"; + reg = <0x1b>; + gpio-controller; + #gpio-cells = <2>; + }; + + max7310_b: gpio@1f { + compatible = "maxim,max7310"; + reg = <0x1f>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx6q-arm2 { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000 + MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_cdwp: usdhc3cdwp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "ipu2-di0"; + primary; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,dte-mode; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc3 { + cd-gpios = <&gpio6 11 0>; + wp-gpios = <&gpio6 14 0>; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3 + &pinctrl_usdhc3_cdwp>; + status = "okay"; +}; + +&usdhc4 { + non-removable; + vmmc-supply = <®_3p3v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-sabreauto-ecspi.dts b/arch/arm/dts/imx6q-sabreauto-ecspi.dts new file mode 100644 index 00000000000..3cf99ed9be6 --- /dev/null +++ b/arch/arm/dts/imx6q-sabreauto-ecspi.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff --git a/arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts b/arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000..579aeb26e05 --- /dev/null +++ b/arch/arm/dts/imx6q-sabreauto-gpmi-weim.dts @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6q-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6q-sabreauto.dts b/arch/arm/dts/imx6q-sabreauto.dts index 6e981a3e0a8..08889239eb7 100644 --- a/arch/arm/dts/imx6q-sabreauto.dts +++ b/arch/arm/dts/imx6q-sabreauto.dts @@ -9,10 +9,30 @@ #include "imx6qdl-sabreauto.dtsi" / { - model = "Freescale i.MX6 Quad SABRE Automotive Board"; + model = "i.MX6 Quad SABRE Automotive Board"; compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; +&mxcfb1 { + status = "okay"; +}; +&mxcfb2 { + status = "okay"; +}; +&mxcfb3 { + status = "okay"; +}; +&mxcfb4 { + status = "okay"; +}; &sata { status = "okay"; }; diff --git a/arch/arm/dts/imx6q-sabresd.dts b/arch/arm/dts/imx6q-sabresd.dts index eec944673c0..e3cd664a225 100644 --- a/arch/arm/dts/imx6q-sabresd.dts +++ b/arch/arm/dts/imx6q-sabresd.dts @@ -9,10 +9,42 @@ #include "imx6qdl-sabresd.dtsi" / { - model = "Freescale i.MX6 Quad SABRE Smart Device Board"; + model = "i.MX6 Quad SABRE Smart Device Board"; compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; }; +&battery { + offset-charger = <1900>; + offset-discharger = <1694>; + offset-usb-charger = <1685>; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &sata { status = "okay"; }; diff --git a/arch/arm/dts/imx6q.dtsi b/arch/arm/dts/imx6q.dtsi index 71543a4a684..24d7e1a955d 100644 --- a/arch/arm/dts/imx6q.dtsi +++ b/arch/arm/dts/imx6q.dtsi @@ -39,129 +39,107 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; clocks = <&clks IMX6QDL_CLK_ARM>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, <&clks IMX6QDL_CLK_STEP>, <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; + <&clks IMX6QDL_CLK_PLL1_SYS>, + <&clks IMX6QDL_CLK_PLL1>, + <&clks IMX6QDL_PLL1_BYPASS>, + <&clks IMX6QDL_PLL1_BYPASS_SRC>, + <&clks IMX6QDL_CLK_VPU_AXI_PODF>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src", + "vpu_axi_podf"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; }; - cpu1: cpu@1 { + cpu@1 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <1>; next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; }; - cpu2: cpu@2 { + cpu@2 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <2>; next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; }; - cpu3: cpu@3 { + cpu@3 { compatible = "arm,cortex-a9"; device_type = "cpu"; reg = <3>; next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < - /* ARM kHz SOC-PU uV */ - 1200000 1275000 - 996000 1250000 - 852000 1250000 - 792000 1175000 - 396000 1175000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6QDL_CLK_ARM>, - <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, - <&clks IMX6QDL_CLK_STEP>, - <&clks IMX6QDL_CLK_PLL1_SW>, - <&clks IMX6QDL_CLK_PLL1_SYS>; - clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; - arm-supply = <®_arm>; - pu-supply = <®_pu>; - soc-supply = <®_soc>; + }; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; }; }; soc { - ocram: sram@900000 { + busfreq: busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>, + <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc"; + interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3"; + fsl,max_ddr_freq = <528000000>; + }; + + gpu: gpu@00130000 { + compatible = "fsl,imx6q-gpu"; + reg = <0x00130000 0x4000>, <0x00134000 0x4000>, + <0x02204000 0x4000>, <0x10000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "iobase_2d", + "iobase_vg", "phys_baseaddr", + "contiguous_mem"; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, + <0 10 IRQ_TYPE_LEVEL_HIGH>, + <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_3d", "irq_2d", "irq_vg"; + clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, <&clks IMX6QDL_CLK_OPENVG_AXI>, + <&clks IMX6QDL_CLK_GPU3D_AXI>, <&clks IMX6QDL_CLK_GPU2D_CORE>, + <&clks IMX6QDL_CLK_GPU3D_CORE>, <&clks IMX6QDL_CLK_GPU3D_SHADER>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu3d_axi_clk", "gpu2d_clk", + "gpu3d_clk", "gpu3d_shader_clk"; + resets = <&src 0>, <&src 3>, <&src 3>; + reset-names = "gpu3d", "gpu2d", "gpuvg"; + power-domains = <&pd_pu>; + }; + + ocram: sram@905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x40000>; + reg = <0x905000 0x3B000>; clocks = <&clks IMX6QDL_CLK_OCRAM>; }; + ocram_optee: sram@938000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x938000 0x8000>; + overw_reg = <&ocram 0x905000 0x33000>; + }; + aips-bus@2000000 { /* AIPS1 */ spba-bus@2000000 { ecspi5: spi@2018000 { @@ -173,14 +151,22 @@ clocks = <&clks IMX6Q_CLK_ECSPI5>, <&clks IMX6Q_CLK_ECSPI5>; clock-names = "ipg", "per"; - dmas = <&sdma 11 8 1>, <&sdma 12 8 2>; + dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; }; + }; - iomuxc: iomuxc@20e0000 { - compatible = "fsl,imx6q-iomuxc"; + aips-bus@2100000 { /* AIPS2 */ + mipi_dsi: mipi@21e0000 { + compatible = "fsl,imx6q-mipi-dsi"; + reg = <0x21e0000 0x4000>; + interrupts = <0 102 0x4>; + gpr = <&gpr>; + clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; + clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; + status = "disabled"; }; }; @@ -192,6 +178,7 @@ <&clks IMX6QDL_CLK_SATA_REF_100M>, <&clks IMX6QDL_CLK_AHB>; clock-names = "sata", "sata_ref", "ahb"; + gpr = <&gpr>; status = "disabled"; }; @@ -215,9 +202,18 @@ <0 7 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI0>, - <&clks IMX6QDL_CLK_IPU2_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, + <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, + <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; + resets = <&src 4>; + bypass_reset = <0>; ipu2_csi0: port@0 { reg = <0>; @@ -302,6 +298,11 @@ compatible = "fsl,imx-display-subsystem"; ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>; }; + + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>; + }; }; &gpio1 { @@ -423,6 +424,10 @@ }; }; +&iomuxc { + compatible = "fsl,imx6q-iomuxc"; +}; + &ipu1_csi1 { ipu1_csi1_from_mipi_vc1: endpoint { remote-endpoint = <&mipi_vc1_to_ipu1_csi1>; @@ -430,13 +435,19 @@ }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; + <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; + clock-names = "ldb_di0", "ldb_di1", + "di0_sel", "di1_sel", + "di2_sel", "di3_sel", + "ldb_di0_div_3_5", "ldb_di1_div_3_5", + "ldb_di0_div_7", "ldb_di1_div_7", + "ldb_di0_div_sel", "ldb_di1_div_sel"; lvds-channel@0 { port@2 { diff --git a/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi index ea90f40a426..7c078e166fe 100644 --- a/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-sabreauto-u-boot.dtsi @@ -5,12 +5,6 @@ #include "imx6qdl-u-boot.dtsi" -/ { - aliases { - mmc0 = &usdhc3; - }; -}; - &usdhc3 { no-1-8-v; u-boot,dm-spl; diff --git a/arch/arm/dts/imx6qdl-sabreauto.dtsi b/arch/arm/dts/imx6qdl-sabreauto.dtsi index 28a7fdb0f1e..25e8f447f50 100644 --- a/arch/arm/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/dts/imx6qdl-sabreauto.dtsi @@ -2,68 +2,76 @@ // // Copyright 2012 Freescale Semiconductor, Inc. // Copyright 2011 Linaro Ltd. +// Copyright 2017 NXP. #include #include / { - chosen { - stdout-path = &uart4; - }; - - memory@10000000 { - reg = <0x10000000 0x80000000>; + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; }; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - user { - label = "debug"; - gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; - }; + chosen { + stdout-path = &uart4; }; gpio-keys { - compatible = "gpio-keys"; + compatible = "gpio-keys1"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; home { label = "Home"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; linux,code = ; - wakeup-source; }; back { label = "Back"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; linux,code = ; - wakeup-source; }; program { label = "Program"; gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; linux,code = ; - wakeup-source; }; volume-up { label = "Volume Up"; gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; linux,code = ; - wakeup-source; }; volume-down { label = "Volume Down"; gpios = <&gpio5 14 GPIO_ACTIVE_LOW>; + gpio-key,wakeup; linux,code = ; - wakeup-source; + }; + }; + + memory: memory { + reg = <0x10000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + user { + label = "debug"; + gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; }; }; @@ -89,6 +97,14 @@ regulator-always-on; }; + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_usb_h1_vbus: regulator@1 { compatible = "regulator-fixed"; reg = <1>; @@ -108,28 +124,159 @@ gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_si4763_vio1: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vio2: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_vd: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_si4763_va: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_sd3_vmmc: regulator@7 { + compatible = "regulator-fixed"; + regulator-name = "P3V3_SDa_SWITCHED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + /* remove below line to enable this regulator */ + status = "disabled"; + }; + + reg_can_en: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_stby: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds_share { + gpios = <&max7310_a 0 GPIO_ACTIVE_HIGH>; + }; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + clocks { + codec_osc: anaclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; }; sound-cs42888 { compatible = "fsl,imx6-sabreauto-cs42888", - "fsl,imx-audio-cs42888"; + "fsl,imx-audio-cs42888"; model = "imx-cs42888"; - audio-cpu = <&esai>; - audio-asrc = <&asrc>; + esai-controller = <&esai>; + asrc-controller = <&asrc>; audio-codec = <&codec>; - audio-routing = - "Line Out Jack", "AOUT1L", - "Line Out Jack", "AOUT1R", - "Line Out Jack", "AOUT2L", - "Line Out Jack", "AOUT2R", - "Line Out Jack", "AOUT3L", - "Line Out Jack", "AOUT3R", - "Line Out Jack", "AOUT4L", - "Line Out Jack", "AOUT4R", - "AIN1L", "Line In Jack", - "AIN1R", "Line In Jack", - "AIN2L", "Line In Jack", - "AIN2R", "Line In Jack"; + }; + + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + ssi-controller = <&ssi2>; + fm-controller = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; }; sound-spdif { @@ -163,19 +310,22 @@ #size-cells = <0>; reg = <1>; - adv7180: camera@21 { - compatible = "adi,adv7180"; + adv7180: adv7180@21 { + compatible = "adv,adv7180"; reg = <0x21>; - powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>; - interrupt-parent = <&gpio1>; - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; - - port { - adv7180_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - }; - }; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_1>; + clocks = <&clks IMX6QDL_CLK_CKO>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v, enabled via 2.8 VGEN6 */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + pwn-gpios = <&max7310_b 2 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + cvbs = <1>; }; max7310_a: gpio@30 { @@ -202,28 +352,45 @@ #gpio-cells = <2>; }; - light-sensor@44 { - compatible = "isil,isl29023"; + isl29023@44 { + compatible = "fsl,isl29023"; reg = <0x44>; + rext = <499>; interrupt-parent = <&gpio5>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; + interrupts = <17 2>; }; - magnetometer@e { + mag3110@0e { compatible = "fsl,mag3110"; reg = <0x0e>; + position = <2>; interrupt-parent = <&gpio2>; - interrupts = <29 IRQ_TYPE_EDGE_RISING>; + interrupts = <29 1>; }; - accelerometer@1c { + mma8451@1c { compatible = "fsl,mma8451"; reg = <0x1c>; + position = <7>; interrupt-parent = <&gpio6>; - interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + interrupts = <31 8>; + interrupt-route = <1>; }; }; }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; }; &ipu1_csi0_from_ipu1_csi0_mux { @@ -231,7 +398,10 @@ }; &ipu1_csi0_mux_from_parallel_sensor { + /* Downstream driver doesn't use endpoints */ + /* remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; + */ bus-width = <8>; }; @@ -240,6 +410,12 @@ pinctrl-0 = <&pinctrl_ipu1_csi0>; }; +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + &clks { assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>, <&clks IMX6QDL_PLL4_BYPASS>, @@ -248,12 +424,25 @@ <&clks IMX6QDL_CLK_PLL4_POST_DIV>; assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>, <&clks IMX6QDL_PLL4_BYPASS_SRC>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>; }; +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds0"; + status = "okay"; +}; + &ecspi1 { + fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio3 19 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; @@ -282,31 +471,85 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; - interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + phy-handle = <&phy>; + fsl,magic-packet; fsl,err006687-workaround-present; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-assert-gpios = <&max7310_b 3 GPIO_ACTIVE_HIGH>; /* TX */ + xceiver-supply = <®_can_stby>; + status = "disabled"; /* pin conflict with fec */ +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; }; &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "disabled"; /* pin conflict with uart3 */ + nand-on-flash-bbt; +}; + +&hdmi_audio { status = "okay"; }; -&hdmi { +&hdmi_cec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "okay"; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; status = "okay"; + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio2>; + interrupts = <28 2>; + wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + }; + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -352,6 +595,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { @@ -406,6 +650,11 @@ }; }; + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + codec: cs42888@48 { compatible = "cirrus,cs42888"; reg = <0x48>; @@ -417,20 +666,27 @@ VLC-supply = <®_audio>; }; - touchscreen@4 { - compatible = "eeti,egalax_ts"; - reg = <0x04>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_egalax_int>; - interrupt-parent = <&gpio2>; - interrupts = <28 IRQ_TYPE_EDGE_FALLING>; - wakeup-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <®_si4763_va>; + vd-supply = <®_si4763_vd>; + vio1-supply = <®_si4763_vio1>; + vio2-supply = <®_si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; }; }; &i2c3 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -439,11 +695,25 @@ pinctrl-0 = <&pinctrl_hog>; imx6qdl-sabreauto { + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1f059 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059 + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x80000000 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x80000000 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x17059 + MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x17059 >; }; @@ -461,9 +731,9 @@ >; }; - pinctrl_egalax_int: egalax-intgrp { + pinctrl_egalax_int: egalax_intgrp { fsl,pins = < - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x80000000 >; }; @@ -484,6 +754,12 @@ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + >; + }; + + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; @@ -503,13 +779,27 @@ >; }; - pinctrl_gpio_keys: gpiokeysgrp { + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x17059 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x17059 + >; + }; + + pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 - MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x17059 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x17059 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b0 >; }; @@ -541,16 +831,41 @@ >; }; - pinctrl_hdmi_cec: hdmicecgrp { + pinctrl_i2c2: i2c2grp { fsl,pins = < - MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 >; }; - pinctrl_i2c2: i2c2grp { + pinctrl_i2c2_gpio: i2c2grp_gpio { fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b8b1 + >; + }; + + pinctrl_ipu1_1: ipu1grp-1 { /* parallel port 16-bit */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 >; }; @@ -561,6 +876,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b1 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b8b1 + >; + }; + pinctrl_i2c3mux: i2c3muxgrp { fsl,pins = < MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1 @@ -589,6 +911,14 @@ >; }; + pinctrl_mlb: mlb { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x80000000 + MX6QDL_PAD_GPIO_6__MLB_SIG 0x80000000 + MX6QDL_PAD_GPIO_2__MLB_DATA 0x80000000 + >; + }; + pinctrl_pwm3: pwm1grp { fsl,pins = < MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 @@ -613,6 +943,24 @@ >; }; + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 @@ -626,6 +974,17 @@ >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -724,6 +1083,12 @@ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1 >; }; + + pinctrl_hdmi_cec: hdmicecgrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; }; }; @@ -733,6 +1098,7 @@ lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; + primary; status = "okay"; display-timings { @@ -750,6 +1116,33 @@ }; }; }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb>; + status = "okay"; }; &pwm3 { @@ -758,12 +1151,44 @@ status = "okay"; }; +&pcie { + status = "okay"; +}; + &spdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6QDL_CLK_SPDIF_SEL>, + <&clks IMX6QDL_CLK_SPDIF_PODF>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_PFD3_454M>; + assigned-clock-rates = <0>, <227368421>; status = "okay"; }; +&snvs_poweroff { + status = "okay"; +}; + +&ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>; + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */ + <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */ + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -779,6 +1204,19 @@ vbus-supply = <®_usb_otg_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -789,6 +1227,20 @@ pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + /* + * Due to board issue, we can not use external regulator for card slot + * by default since the card power is shared with card detect pullup. + * Disabling the vmmc regulator will cause unexpected card detect + * interrupts. + * HW rework is needed to fix this isssue. Remove R695 first, then you + * can open below line to enable the using of external regulator. + * Then you will be able to power off the card during suspend. This is + * especially needed for a SD3.0 card re-enumeration working on UHS mode + * Note: reg_sd3_vmmc is also need to be enabled + */ + /* vmmc-supply = <®_sd3_vmmc>; */ + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-sabresd.dtsi b/arch/arm/dts/imx6qdl-sabresd.dtsi index eddb3901745..2c1d0288bf8 100644 --- a/arch/arm/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/dts/imx6qdl-sabresd.dtsi @@ -2,21 +2,49 @@ // // Copyright 2012 Freescale Semiconductor, Inc. // Copyright 2011 Linaro Ltd. +// Copyright 2017 NXP. #include + #include #include / { aliases { - mmc1 = &usdhc3; + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; + + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio2 24 1>; + uok_input = <&gpio1 27 1>; + chg_input = <&gpio3 23 1>; + flt_input = <&gpio5 2 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,usb_valid; + status = "okay"; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds0 { + gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + }; + lvds1 { + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; }; chosen { stdout-path = &uart1; }; - memory@10000000 { + memory: memory { reg = <0x10000000 0x40000000>; }; @@ -64,6 +92,36 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 19 0>; + regulator-always-on; + enable-active-high; + }; + + reg_sensor: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "sensor-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 31 0>; + startup-delay-us = <500>; + regulator-always-on; + enable-active-high; + }; + + reg_hdmi: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "hdmi-5v-supply"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + hdmi-5v-supply = <&swbst_reg>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio6 14 0>; enable-active-high; }; }; @@ -99,20 +157,89 @@ compatible = "fsl,imx6q-sabresd-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; + asrc-controller = <&asrc>; audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", - "IN3R", "AMIC"; + "IN3R", "AMIC", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC", + "CPU-Playback", "ASRC-Playback", + "Playback", "CPU-Playback", + "ASRC-Capture", "CPU-Capture", + "CPU-Capture", "Capture"; mux-int-port = <2>; mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio7 8 1>; + mic-det-gpios = <&gpio1 9 1>; + }; + + sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <24>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; }; - backlight_lvds: backlight-lvds { + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + status = "okay"; + }; + + backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; @@ -125,21 +252,32 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - red { + charger-led { gpios = <&gpio1 2 0>; - default-state = "on"; + linux,default-trigger = "max8903-charger-charging"; + retain-state-suspended; }; }; - panel { - compatible = "hannstar,hsd100pxn1"; - backlight = <&backlight_lvds>; + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; + v4l2_cap_1 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; }; }; @@ -151,7 +289,10 @@ }; &ipu1_csi0_mux_from_parallel_sensor { + /* Downstream driver doesn't use endpoints */ + /* remote-endpoint = <&ov5642_to_ipu1_csi0_mux>; + */ }; &ipu1_csi0 { @@ -161,16 +302,6 @@ &mipi_csi { status = "okay"; - - port@0 { - reg = <0>; - - mipi_csi2_in: endpoint { - remote-endpoint = <&ov5640_to_mipi_csi2>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; }; &audmux { @@ -182,11 +313,12 @@ &clks { assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>; - assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + assigned-clock-parents = <&clks IMX6QDL_CLK_PLL2_PFD0_352M>, + <&clks IMX6QDL_CLK_PLL2_PFD0_352M>; }; &ecspi1 { + fsl,spi-num-chipselects = <1>; cs-gpios = <&gpio4 9 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; @@ -206,20 +338,67 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + reg = <1>; + qca,clk-out-frequency = <125000000>; + }; + }; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-hdmi"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds1"; + status = "okay"; +}; + +&hdmi_audio { status = "okay"; }; -&hdmi { +&hdmi_cec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hdmi_cec>; - ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + HDMI-supply = <®_hdmi>; status = "okay"; }; &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8962@1a { @@ -242,61 +421,64 @@ 0x8014 /* 4:FN_DMICCDAT */ 0x0000 /* 5:Default */ >; + amic-mono; }; - ov5642: camera@3c { - compatible = "ovti,ov5642"; + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <0>; + vdd-supply = <®_sensor>; + vddio-supply = <®_sensor>; + interrupt-parent = <&gpio1>; + interrupts = <18 8>; + interrupt-route = <1>; + }; + + ov564x: ov564x@3c { + compatible = "ovti,ov564x"; + reg = <0x3c>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5642>; + pinctrl-0 = <&pinctrl_ipu1_2>; clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - reg = <0x3c>; + clock-names = "csi_mclk"; DOVDD-supply = <&vgen4_reg>; /* 1.8v */ - AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 - rev B board is VGEN5 */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, on rev C board is VGEN3, + on rev B board is VGEN5 */ DVDD-supply = <&vgen2_reg>; /* 1.5v*/ - powerdown-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; - status = "disabled"; - - port { - ov5642_to_ipu1_csi0_mux: endpoint { - remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; - bus-width = <8>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; + pwn-gpios = <&gpio1 16 1>; /* active low: SD1_DAT0 */ + rst-gpios = <&gpio1 17 0>; /* active high: SD1_DAT1 */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; }; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; status = "okay"; - ov5640: camera@3c { - compatible = "ovti,ov5640"; + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ov5640>; - reg = <0x3c>; - clocks = <&clks IMX6QDL_CLK_CKO>; - clock-names = "xclk"; - DOVDD-supply = <&vgen4_reg>; /* 1.8v */ - AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 - rev B board is VGEN5 */ - DVDD-supply = <&vgen2_reg>; /* 1.5v*/ - powerdown-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; - - port { - ov5640_to_mipi_csi2: endpoint { - remote-endpoint = <&mipi_csi2_in>; - clock-lanes = <0>; - data-lanes = <1 2>; - }; - }; + pinctrl-0 = <&pinctrl_i2c2_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <8 2>; + wakeup-gpios = <&gpio6 8 0>; + }; + + max11801@48 { + compatible = "maxim,max11801"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <26 2>; + work-mode = <1>;/*DCM mode*/ }; pmic: pfuze100@8 { @@ -399,21 +581,66 @@ }; }; }; + + hdmi_edid: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + + ov564x_mipi: ov564x_mipi@3c { /* i2c2 driver */ + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks 201>; + clock-names = "csi_mclk"; + DOVDD-supply = <&vgen4_reg>; /* 1.8v */ + AVDD-supply = <&vgen3_reg>; /* 2.8v, rev C board is VGEN3 + rev B board is VGEN5 */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 19 1>; /* active low: SD1_CLK */ + rst-gpios = <&gpio1 20 0>; /* active high: SD1_DAT2 */ + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; status = "okay"; - egalax_ts@4 { + egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_egalax_int>; interrupt-parent = <&gpio6>; interrupts = <7 2>; wakeup-gpios = <&gpio6 7 0>; }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + vdd-supply = <®_sensor>; + interrupt-parent = <&gpio3>; + interrupts = <9 2>; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + vdd-supply = <®_sensor>; + vddio-supply = <®_sensor>; + interrupt-parent = <&gpio3>; + interrupts = <16 1>; + }; }; &iomuxc { @@ -423,15 +650,29 @@ imx6qdl-sabresd { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x80000000 + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x80000000 + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x80000000 + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x80000000 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x80000000 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 + MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x80000000 >; }; @@ -453,6 +694,18 @@ >; }; + pinctrl_i2c2_egalax_int: egalax_i2c2_intgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 + >; + }; + + pinctrl_i2c3_egalax_int: egalax_i2c3_intgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 + >; + }; + pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 @@ -474,6 +727,12 @@ >; }; + pinctrl_enet_irq: enetirqgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 + >; + }; + pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 @@ -484,7 +743,14 @@ pinctrl_hdmi_cec: hdmicecgrp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x108b0 + >; + }; + + pinctrl_hdmi_hdcp: hdmihdcpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 >; }; @@ -495,6 +761,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b8b1 + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b8b1 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 @@ -502,6 +775,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2_gpio_grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 @@ -509,6 +789,66 @@ >; }; + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b8b1 + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b8b1 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; + + pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */ + fsl,pins = < + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000 + MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000 + MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000 + MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 + >; + }; + pinctrl_ipu1_csi0: ipu1csi0grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 @@ -564,6 +904,24 @@ >; }; + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x1b0b1 + MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 @@ -617,7 +975,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX6QDL_PAD_GPIO_1__WDOG2_B 0x1b0b0 + MX6QDL_PAD_GPIO_1__WDOG2_B 0x80000000 >; }; }; @@ -634,26 +992,72 @@ &ldb { status = "okay"; - lvds-channel@1 { + lvds-channel@0 { fsl,data-mapping = "spwg"; fsl,data-width = <18>; status = "okay"; - port@4 { - reg = <4>; + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; + }; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + primary; + status = "okay"; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; }; }; }; }; +&mipi_csi { + status = "okay"; + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; +}; + +&mipi_dsi { + dev_id = <0>; + disp_id = <1>; + lcd_panel = "TRULY-WVGA"; + disp-power-on-supply = <®_mipi_dsi_pwr_on>; + reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + reset-delay-us = <50>; + status = "okay"; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie>; status = "okay"; }; @@ -680,6 +1084,13 @@ }; &ssi2 { + assigned-clocks = <&clks IMX6QDL_CLK_PLL4>, + <&clks IMX6QDL_PLL4_BYPASS>, + <&clks IMX6QDL_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6QDL_CLK_OSC>, + <&clks IMX6QDL_CLK_PLL4>, + <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <737280000>, <0>, <0>; status = "okay"; }; @@ -699,15 +1110,29 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; disable-over-current; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; bus-width = <8>; cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -717,6 +1142,9 @@ bus-width = <8>; cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -726,6 +1154,7 @@ bus-width = <8>; non-removable; no-1-8-v; + keep-power-in-suspend; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi index e4daf150881..9d18d0d94e3 100644 --- a/arch/arm/dts/imx6qdl.dtsi +++ b/arch/arm/dts/imx6qdl.dtsi @@ -16,7 +16,7 @@ * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; + memory { device_type = "memory"; reg = <0 0>; }; aliases { ethernet0 = &fec; @@ -48,9 +48,16 @@ spi3 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg; + usb1 = &usbh1; + usbgadget0 = &usbg1; + pci0 = &pcie; }; clocks { + #address-cells = <1>; + #size-cells = <0>; + ckil { compatible = "fsl,imx-ckil", "fixed-clock"; #clock-cells = <0>; @@ -70,75 +77,6 @@ }; }; - tempmon: tempmon { - compatible = "fsl,imx6q-tempmon"; - interrupt-parent = <&gpc>; - interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - }; - - ldb: ldb { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; - gpr = <&gpr>; - status = "disabled"; - - lvds-channel@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds0_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@1 { - reg = <1>; - - lvds0_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds0>; - }; - }; - }; - - lvds-channel@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - status = "disabled"; - - port@0 { - reg = <0>; - - lvds1_mux_0: endpoint { - remote-endpoint = <&ipu1_di0_lvds1>; - }; - }; - - port@1 { - reg = <1>; - - lvds1_mux_1: endpoint { - remote-endpoint = <&ipu1_di1_lvds1>; - }; - }; - }; - }; - - pmu: pmu { - compatible = "arm,cortex-a9-pmu"; - interrupt-parent = <&gpc>; - interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; - }; - soc { #address-cells = <1>; #size-cells = <1>; @@ -146,6 +84,11 @@ interrupt-parent = <&gpc>; ranges; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x4000>; + }; + dma_apbh: dma-apbh@110000 { compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x00110000 0x2000>; @@ -159,7 +102,17 @@ clocks = <&clks IMX6QDL_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@112000 { + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <0 20 0x04>; + secvio_src = <0x8000001d>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + gpmi: nand-controller@112000 { compatible = "fsl,imx6q-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -228,6 +181,18 @@ power-domains = <&pd_pu>; }; + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + clocks = <&clks IMX6QDL_CLK_OCRAM>; + }; + timer@a00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0x00a00600 0x20>; @@ -245,7 +210,7 @@ interrupt-parent = <&intc>; }; - L2: l2-cache@a02000 { + L2: cache-controller@a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; @@ -280,6 +245,52 @@ <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_REF_125M>; clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + gpr = <&gpr>; + status = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + }; + + hdmi_core: hdmi_core@00120000 { + compatible = "fsl,imx6q-hdmi-core"; + reg = <0x00120000 0x9000>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_video: hdmi_video@020e0000 { + compatible = "fsl,imx6q-hdmi-video"; + reg = <0x020e0000 0x1000>; + reg-names = "hdmi_gpr"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + status = "disabled"; + }; + + hdmi_audio: hdmi_audio@00120000 { + compatible = "fsl,imx6q-hdmi-audio"; + clocks = <&clks IMX6QDL_CLK_HDMI_ISFR>, + <&clks IMX6QDL_CLK_HDMI_IAHB>, + <&clks IMX6QDL_CLK_HSI_TX>; + clock-names = "hdmi_isfr", "hdmi_iahb", "mipi_core"; + dmas = <&sdma 2 25 0>; + dma-names = "tx"; + status = "disabled"; + }; + + hdmi_cec: hdmi_cec@00120000 { + compatible = "fsl,imx6q-hdmi-cec"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -307,7 +318,7 @@ clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, + <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; clock-names = "core", "rxtx0", "rxtx1", "rxtx2", @@ -326,7 +337,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI1>, <&clks IMX6QDL_CLK_ECSPI1>; clock-names = "ipg", "per"; - dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -340,7 +351,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI2>, <&clks IMX6QDL_CLK_ECSPI2>; clock-names = "ipg", "per"; - dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -354,7 +365,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI3>, <&clks IMX6QDL_CLK_ECSPI3>; clock-names = "ipg", "per"; - dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -368,7 +379,7 @@ clocks = <&clks IMX6QDL_CLK_ECSPI4>, <&clks IMX6QDL_CLK_ECSPI4>; clock-names = "ipg", "per"; - dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -491,6 +502,24 @@ power-domains = <&pd_pu>; resets = <&src 1>; iram = <&ocram>; + status = "disabled"; + }; + + vpu_fsl: vpu_fsl@2040000 { + compatible = "fsl,imx6-vpu"; + reg = <0x2040000 0x3c000>; + reg-names = "vpu_regs"; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq"; + clocks = <&clks IMX6QDL_CLK_VPU_AXI>, + <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, + <&clks IMX6QDL_CLK_OCRAM>; + clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram"; + iramsize = <0x21000>; + iram = <&ocram>; + resets = <&src 1>; + power-domains = <&pd_pu>; }; aipstz@207c000 { /* AIPSTZ1 */ @@ -548,6 +577,7 @@ clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, <&clks IMX6QDL_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x34 28 0x10 17>; status = "disabled"; }; @@ -558,10 +588,11 @@ clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, <&clks IMX6QDL_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x34 29 0x10 18>; status = "disabled"; }; - gpt: gpt@2098000 { + gpt: timer@2098000 { compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; @@ -648,7 +679,7 @@ #interrupt-cells = <2>; }; - kpp: kpp@20b8000 { + kpp: keypad@20b8000 { compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; @@ -656,22 +687,22 @@ status = "disabled"; }; - wdog1: wdog@20bc000 { + wdog1: watchdog@20bc000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020bc000 0x4000>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_DUMMY>; + clocks = <&clks IMX6QDL_CLK_IPG>; }; - wdog2: wdog@20c0000 { + wdog2: watchdog@20c0000 { compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; reg = <0x020c0000 0x4000>; interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_DUMMY>; + clocks = <&clks IMX6QDL_CLK_IPG>; status = "disabled"; }; - clks: ccm@20c4000 { + clks: clock-controller@20c4000 { compatible = "fsl,imx6q-ccm"; reg = <0x020c4000 0x4000>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, @@ -701,12 +732,11 @@ anatop-enable-bit = <0>; }; - regulator-3p0 { + anatop_reg_3p0: regulator-3p0@120 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; anatop-vol-bit-width = <5>; @@ -746,6 +776,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_pu: regulator-vddpu { @@ -763,6 +794,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_soc: regulator-vddsoc { @@ -780,14 +812,24 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; }; + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; + }; + usbphy1: usbphy@20c9000 { compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBPHY1>; + phy-3p0-supply = <&anatop_reg_3p0>; fsl,anatop = <&anatop>; }; @@ -796,9 +838,27 @@ reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_USBPHY2>; + phy-3p0-supply = <&anatop_reg_3p0>; fsl,anatop = <&anatop>; }; + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + + usbphy_nop2: usbphy_nop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6QDL_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + + caam_snvs: caam-snvs@20cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x20cc000 0x4000>; + }; + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -819,10 +879,6 @@ mask = <0x60>; status = "disabled"; }; - - snvs_lpgpr: snvs-lpgpr { - compatible = "fsl,imx6q-snvs-lpgpr"; - }; }; epit1: epit@20d0000 { /* EPIT1 */ @@ -835,7 +891,7 @@ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - src: src@20d8000 { + src: reset-controller@20d8000 { compatible = "fsl,imx6q-src", "fsl,imx51-src"; reg = <0x020d8000 0x4000>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, @@ -848,8 +904,7 @@ reg = <0x020dc000 0x4000>; interrupt-controller; #interrupt-cells = <3>; - interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, - <0 90 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; clocks = <&clks IMX6QDL_CLK_IPG>; clock-names = "ipg"; @@ -886,26 +941,90 @@ }; }; - iomuxc: iomuxc@20e0000 { + iomuxc: pinctrl@20e0000 { compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; reg = <0x20e0000 0x4000>; }; + ldb: ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; + gpr = <&gpr>; + status = "disabled"; + + lvds-channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds0_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_lvds0>; + }; + }; + + port@1 { + reg = <1>; + + lvds0_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_lvds0>; + }; + }; + }; + + lvds-channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + status = "disabled"; + + port@0 { + reg = <0>; + + lvds1_mux_0: endpoint { + remote-endpoint = <&ipu1_di0_lvds1>; + }; + }; + + port@1 { + reg = <1>; + + lvds1_mux_1: endpoint { + remote-endpoint = <&ipu1_di1_lvds1>; + }; + }; + }; + }; + dcic1: dcic@20e4000 { - reg = <0x020e4000 0x4000>; + compatible = "fsl,imx6q-dcic"; + reg = <0x20e4000 0x4000>; interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC1>, <&clks IMX6QDL_CLK_DCIC1>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; dcic2: dcic@20e8000 { - reg = <0x020e8000 0x4000>; + compatible = "fsl,imx6q-dcic"; + reg = <0x20e8000 0x4000>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_DCIC2>, <&clks IMX6QDL_CLK_DCIC2>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; }; sdma: sdma@20ec000 { compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SDMA>, + clocks = <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; @@ -920,25 +1039,35 @@ reg = <0x02100000 0x100000>; ranges; - crypto: caam@2100000 { + crypto: crypto@2100000 { compatible = "fsl,sec-v4.0"; #address-cells = <1>; #size-cells = <1>; reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; + ranges = <0 0x2100000 0x40000>; + interrupt-parent = <&intc>; /* interrupts = <0 92 0x4>; */ clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, <&clks IMX6QDL_CLK_CAAM_ACLK>, <&clks IMX6QDL_CLK_CAAM_IPG>, <&clks IMX6QDL_CLK_EIM_SLOW>; clock-names = "mem", "aclk", "ipg", "emi_slow"; - sec_jr0: jr0@1000 { + sec_ctrl: ctrl@0 { + /* CAAM Page 0 only accessible */ + /* by secure world */ + compatible = "fsl,sec-v4.0-ctrl"; + reg = <0x2100000 0x1000>; + secure-status = "okay"; + status = "disabled"; + }; + + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = ; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = ; @@ -949,7 +1078,14 @@ reg = <0x0217c000 0x4000>; }; - usbotg: usb@2184000 { + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg>; + status = "okay"; + }; + + usbotg: usb@02184000 { compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; @@ -959,6 +1095,7 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -986,6 +1123,9 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop1>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -999,6 +1139,9 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop2>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -1012,25 +1155,31 @@ fec: ethernet@2188000 { compatible = "fsl,imx6q-fec"; reg = <0x02188000 0x4000>; - interrupt-names = "int0", "pps"; interrupts-extended = - <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, - <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + <&gpc 0 118 IRQ_TYPE_LEVEL_HIGH>, + <&gpc 0 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp"; + stop-mode = <&gpr 0x34 27>; + fsl,wakeup_irq = <0>; status = "disabled"; }; - mlb@218c000 { + mlb: mlb@218c000 { + compatible = "fsl,imx6q-mlb150"; reg = <0x0218c000 0x4000>; interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, <0 117 IRQ_TYPE_LEVEL_HIGH>, <0 126 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_MLB>; + clock-names = "mlb"; + iram = <&ocram>; + status = "disabled"; }; - usdhc1: usdhc@2190000 { + usdhc1: mmc@2190000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02190000 0x4000>; interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; @@ -1042,7 +1191,7 @@ status = "disabled"; }; - usdhc2: usdhc@2194000 { + usdhc2: mmc@2194000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02194000 0x4000>; interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; @@ -1054,7 +1203,7 @@ status = "disabled"; }; - usdhc3: usdhc@2198000 { + usdhc3: mmc@2198000 { compatible = "fsl,imx6q-usdhc"; reg = <0x02198000 0x4000>; interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; @@ -1066,7 +1215,7 @@ status = "disabled"; }; - usdhc4: usdhc@219c000 { + usdhc4: mmc@219c000 { compatible = "fsl,imx6q-usdhc"; reg = <0x0219c000 0x4000>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; @@ -1112,13 +1261,20 @@ reg = <0x021ac000 0x4000>; }; - mmdc0: mmdc@21b0000 { /* MMDC0 */ + mmdc0-1@021b0000 { /* MMDC0-1 */ + compatible = "fsl,imx6q-mmdc-combine"; + reg = <0x021b0000 0x8000>; + }; + + mmdc0: memory-controller@21b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; }; - mmdc1: mmdc@21b4000 { /* MMDC1 */ + mmdc1: memory-controller@21b4000 { /* MMDC1 */ + compatible = "fsl,imx6q-mmdc"; reg = <0x021b4000 0x4000>; + status = "disabled"; }; weim: weim@21b8000 { @@ -1132,7 +1288,7 @@ status = "disabled"; }; - ocotp: ocotp@21bc000 { + ocotp: efuse@21bc000 { compatible = "fsl,imx6q-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6QDL_CLK_IIM>; @@ -1155,15 +1311,15 @@ }; mipi_csi: mipi@21dc000 { - compatible = "fsl,imx6-mipi-csi2"; + compatible = "fsl,imx6q-mipi-csi2"; reg = <0x021dc000 0x4000>; #address-cells = <1>; #size-cells = <0>; interrupts = <0 100 0x04>, <0 101 0x04>; clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>, - <&clks IMX6QDL_CLK_EIM_PODF>; - clock-names = "dphy", "ref", "pix"; + <&clks IMX6QDL_CLK_EIM_SEL>; + clock-names = "dphy_clk", "cfg_clk", "pixel_clk"; status = "disabled"; }; @@ -1198,6 +1354,7 @@ reg = <0x021e4000 0x4000>; interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_VDOA>; + iram = <&ocram>; }; uart2: serial@21e8000 { @@ -1257,10 +1414,15 @@ interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, <0 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_IPU1>, - <&clks IMX6QDL_CLK_IPU1_DI0>, - <&clks IMX6QDL_CLK_IPU1_DI1>; - clock-names = "bus", "di0", "di1"; + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1"; resets = <&src 2>; + bypass_reset = <0>; ipu1_csi0: port@0 { reg = <0>; diff --git a/arch/arm/dts/imx6qp-sabreauto-ecspi.dts b/arch/arm/dts/imx6qp-sabreauto-ecspi.dts new file mode 100644 index 00000000000..8846739a555 --- /dev/null +++ b/arch/arm/dts/imx6qp-sabreauto-ecspi.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&i2c3 { + /* pin conflict with ecspi1 */ + status = "disabled"; +}; + +&uart3 { + /* the uart3 depends on the i2c3, so disable it too. */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; diff --git a/arch/arm/dts/imx6qp-sabreauto-gpmi-weim.dts b/arch/arm/dts/imx6qp-sabreauto-gpmi-weim.dts new file mode 100644 index 00000000000..b91ebad6111 --- /dev/null +++ b/arch/arm/dts/imx6qp-sabreauto-gpmi-weim.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6qp-sabreauto.dts" + +&ecspi1 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&can2 { + /* max7310_c on i2c3 is gone */ + status = "disabled"; +}; + +&gpmi { + compatible = "fsl,imx6qp-gpmi-nand"; + status = "okay"; +}; + +&i2c3 { + /* pin conflict with weim */ + status = "disabled"; +}; + +&uart3 { + /* pin conflict with gpmi and weim */ + status = "disabled"; +}; + +&usbh1 { + /* max7310_b on i2c3 is gone */ + status = "disabled"; +}; + +&usbotg { + /* max7310_c on i2c3 is gone */ + status = "okay"; + dr_mode = "peripheral"; +}; + +&weim { + pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6qp-sabreauto.dts b/arch/arm/dts/imx6qp-sabreauto.dts index d4caeeb0af7..46560263bd9 100644 --- a/arch/arm/dts/imx6qp-sabreauto.dts +++ b/arch/arm/dts/imx6qp-sabreauto.dts @@ -8,10 +8,44 @@ #include "imx6qdl-sabreauto.dtsi" / { - model = "Freescale i.MX6 Quad Plus SABRE Automotive Board"; + model = "i.MX6 Quad Plus SABRE Automotive Board"; compatible = "fsl,imx6qp-sabreauto", "fsl,imx6qp"; }; +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + prefetch; + status = "okay"; +}; + +&mxcfb2 { + prefetch; + status = "okay"; +}; + +&mxcfb3 { + prefetch; + status = "okay"; +}; + +&mxcfb4 { + prefetch; + status = "okay"; +}; + +&fec { + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; +}; + &i2c2 { max7322: gpio@68 { compatible = "maxim,max7322"; @@ -21,33 +55,47 @@ }; }; -&iomuxc { - imx6qdl-sabreauto { - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b018 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b018 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b018 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b018 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b018 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b018 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b018 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b018 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b018 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b018 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b018 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b018 - MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 - MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 - >; - }; - }; +&pcie { + reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; + status = "okay"; }; -&pcie { - status = "disabled"; +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +®_sd3_vmmc { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&usdhc3 { + vmmc-supply = <®_sd3_vmmc>; }; &vgen3_reg { diff --git a/arch/arm/dts/imx6qp-sabresd.dts b/arch/arm/dts/imx6qp-sabresd.dts index f1b9cb104fd..c131bbd9050 100644 --- a/arch/arm/dts/imx6qp-sabresd.dts +++ b/arch/arm/dts/imx6qp-sabresd.dts @@ -8,7 +8,7 @@ #include "imx6qdl-sabresd.dtsi" / { - model = "Freescale i.MX6 Quad Plus SABRE Smart Device Board"; + model = "i.MX6 Quad Plus SABRE Smart Device Board"; compatible = "fsl,imx6qp-sabresd", "fsl,imx6qp"; }; @@ -50,6 +50,112 @@ }; }; +&iomuxc { + imx6qdl-sabresd { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10071 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10071 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 + >; + }; + }; +}; + +&ldb { + lvds-channel@0 { + crtc = "ipu2-di0"; + }; + + lvds-channel@1 { + crtc = "ipu2-di1"; + }; +}; + +&mxcfb1 { + prefetch; + status = "okay"; +}; + +&mxcfb2 { + prefetch; + status = "okay"; +}; + +&mxcfb3 { + prefetch; + status = "okay"; +}; + +&mxcfb4 { + prefetch; + status = "okay"; +}; + +&ov564x { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + +&ov564x_mipi { + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DOVDD-supply = <&sw4_reg>; /* 1.8v */ +}; + &pcie { - status = "disabled"; + pcie-bus-supply = <&vgen3_reg>; /* 1.8v pwr up pcie ext osc on revb */ + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pre1 { + status = "okay"; +}; + +&pre2 { + status = "okay"; +}; + +&pre3 { + status = "okay"; +}; + +&pre4 { + status = "okay"; +}; + +&prg1 { + memory-region = <&memory>; + status = "okay"; +}; + +&prg2 { + memory-region = <&memory>; + status = "okay"; +}; + +&sata { + status = "okay"; }; diff --git a/arch/arm/dts/imx6qp.dtsi b/arch/arm/dts/imx6qp.dtsi index 5f51f8e5c1f..8ef74f78528 100644 --- a/arch/arm/dts/imx6qp.dtsi +++ b/arch/arm/dts/imx6qp.dtsi @@ -5,6 +5,15 @@ #include "imx6q.dtsi" / { + aliases { + pre0 = &pre1; + pre1 = &pre2; + pre2 = &pre3; + pre3 = &pre4; + prg0 = &prg1; + prg1 = &prg2; + }; + soc { ocram2: sram@940000 { compatible = "mmio-sram"; @@ -18,59 +27,87 @@ clocks = <&clks IMX6QDL_CLK_OCRAM>; }; - aips-bus@2100000 { + pcie: pcie@1ffc000 { + compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; + reg = <0x01ffc000 0x4000>, <0x01f00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 120 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_PCIE_REF_125M>, <&clks IMX6QDL_PLL6_BYPASS>, + <&clks IMX6QDL_PLL6_BYPASS_SRC>, + <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_AXI>; + clock-names = "pcie_phy", "pcie_ext", "pcie_ext_src", "pcie_bus", "pcie"; + status = "disabled"; + }; + + aips-bus@2100000 { /* AIPS2 */ pre1: pre@21c8000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021c8000 0x1000>; - interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE0>; - clock-names = "axi"; - fsl,iram = <&ocram2>; + interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram2>; + status = "disabled"; }; pre2: pre@21c9000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021c9000 0x1000>; - interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE1>; - clock-names = "axi"; - fsl,iram = <&ocram2>; + interrupts = <0 97 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram2>; + status = "disabled"; }; pre3: pre@21ca000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021ca000 0x1000>; - interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE2>; - clock-names = "axi"; - fsl,iram = <&ocram3>; + interrupts = <0 98 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram3>; + status = "disabled"; }; pre4: pre@21cb000 { - compatible = "fsl,imx6qp-pre"; + compatible = "fsl,imx6q-pre"; reg = <0x021cb000 0x1000>; - interrupts = ; clocks = <&clks IMX6QDL_CLK_PRE3>; - clock-names = "axi"; - fsl,iram = <&ocram3>; + interrupts = <0 99 IRQ_TYPE_EDGE_RISING>; + ocram = <&ocram3>; + status = "disabled"; }; prg1: prg@21cc000 { - compatible = "fsl,imx6qp-prg"; + compatible = "fsl,imx6q-prg"; reg = <0x021cc000 0x1000>; - clocks = <&clks IMX6QDL_CLK_PRG0_APB>, - <&clks IMX6QDL_CLK_PRG0_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre1>, <&pre2>, <&pre3>; + clocks = <&clks IMX6QDL_CLK_PRG0_AXI>, + <&clks IMX6QDL_CLK_PRG0_APB>; + clock-names = "axi", "apb"; + gpr = <&gpr>; + status = "disabled"; }; prg2: prg@21cd000 { - compatible = "fsl,imx6qp-prg"; + compatible = "fsl,imx6q-prg"; reg = <0x021cd000 0x1000>; - clocks = <&clks IMX6QDL_CLK_PRG1_APB>, - <&clks IMX6QDL_CLK_PRG1_AXI>; - clock-names = "ipg", "axi"; - fsl,pres = <&pre4>, <&pre2>, <&pre3>; + clocks = <&clks IMX6QDL_CLK_PRG1_AXI>, + <&clks IMX6QDL_CLK_PRG1_APB>; + clock-names = "axi", "apb"; + gpr = <&gpr>; + status = "disabled"; }; }; }; @@ -88,22 +125,34 @@ &ipu1 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU1>, + <&clks IMX6QDL_CLK_IPU1_DI0>, <&clks IMX6QDL_CLK_IPU1_DI1>, + <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG0_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; fsl,prg = <&prg1>; }; &ipu2 { compatible = "fsl,imx6qp-ipu", "fsl,imx6q-ipu"; + clocks = <&clks IMX6QDL_CLK_IPU2>, + <&clks IMX6QDL_CLK_IPU2_DI0>, <&clks IMX6QDL_CLK_IPU2_DI1>, + <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, + <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>, + <&clks IMX6QDL_CLK_PRG1_APB>; + clock-names = "bus", + "di0", "di1", + "di0_sel", "di1_sel", + "ldb_di0", "ldb_di1", "prg"; fsl,prg = <&prg2>; }; &ldb { - clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, - <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>, - <&clks IMX6QDL_CLK_LDB_DI0_PODF>, <&clks IMX6QDL_CLK_LDB_DI1_PODF>; - clock-names = "di0_pll", "di1_pll", - "di0_sel", "di1_sel", "di2_sel", "di3_sel", - "di0", "di1"; + compatible = "fsl,imx6qp-ldb", "fsl,imx6q-ldb", "fsl,imx53-ldb"; }; &mmdc0 { diff --git a/arch/arm/dts/imx6sl-evk.dts b/arch/arm/dts/imx6sl-evk.dts index 0a90eea1701..893e6791ae5 100644 --- a/arch/arm/dts/imx6sl-evk.dts +++ b/arch/arm/dts/imx6sl-evk.dts @@ -1,5 +1,6 @@ /* * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -13,9 +14,26 @@ #include "imx6sl.dtsi" / { - model = "Freescale i.MX6 SoloLite EVK Board"; + model = "i.MX6 SoloLite EVK Board"; compatible = "fsl,imx6sl-evk", "fsl,imx6sl"; + battery: max8903@0 { + compatible = "fsl,max8903-charger"; + pinctrl-names = "default"; + dok_input = <&gpio4 13 1>; + uok_input = <&gpio4 13 1>; + chg_input = <&gpio4 15 1>; + flt_input = <&gpio4 14 1>; + fsl,dcm_always_high; + fsl,dc_valid; + fsl,adc_disable; + status = "okay"; + }; + + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x80000000 0x40000000>; }; @@ -39,6 +57,11 @@ }; }; + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -96,7 +119,7 @@ sound { compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -107,6 +130,23 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 19 1>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sl-evk-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; + + sii902x_reset: sii902x-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio2 19 1>; + reset-delay-us = <100000>; + #reset-cells = <0>; }; }; @@ -116,6 +156,29 @@ status = "okay"; }; +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +®_pu { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&csi { + port { + csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + &ecspi1 { cs-gpios = <&gpio4 11 0>; pinctrl-names = "default"; @@ -131,6 +194,15 @@ }; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + &fec { pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_fec>; @@ -139,13 +211,20 @@ status = "okay"; }; +&gpc { + fsl,ldo-bypass = <1>; +}; + &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -190,6 +269,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { @@ -244,12 +324,98 @@ }; }; }; + + elan@10 { + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio2>; + interrupts = <10 2>; + gpio_elan_cs = <&gpio2 9 0>; + gpio_elan_rst = <&gpio4 4 0>; + gpio_intr = <&gpio2 10 0>; + status = "okay"; + }; + + mma8450@1c { + compatible = "fsl,mma8450"; + reg = <0x1c>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8962@1a { @@ -264,6 +430,45 @@ PLLVDD-supply = <&vgen3_reg>; SPKVDD1-supply = <®_aud4v>; SPKVDD2-supply = <®_aud4v>; + amic-mono; + }; + + sii902x@39 { + compatible = "SiI,sii902x"; + interrupt-parent = <&gpio2>; + interrupts = <10 2>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + resets = <&sii902x_reset>; + reg = <0x39>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "disabled"; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 25 1>; + rst-gpios = <&gpio1 26 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi_ep>; + }; + }; }; }; @@ -282,6 +487,17 @@ MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000 MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b0b0 + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x17000 + MX6SL_PAD_EPDC_PWRCTRL2__GPIO2_IO09 0x80000000 + MX6SL_PAD_KEY_COL6__GPIO4_IO04 0x110b0 + MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x1b0b0 + MX6SL_PAD_ECSPI2_MISO__GPIO4_IO14 0x17000 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x17000 + MX6SL_PAD_ECSPI2_SS0__GPIO4_IO15 0x17000 >; }; @@ -303,6 +519,39 @@ >; }; + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_D0__EPDC_DATA00 0x80000000 + MX6SL_PAD_EPDC_D1__EPDC_DATA01 0x80000000 + MX6SL_PAD_EPDC_D2__EPDC_DATA02 0x80000000 + MX6SL_PAD_EPDC_D3__EPDC_DATA03 0x80000000 + MX6SL_PAD_EPDC_D4__EPDC_DATA04 0x80000000 + MX6SL_PAD_EPDC_D5__EPDC_DATA05 0x80000000 + MX6SL_PAD_EPDC_D6__EPDC_DATA06 0x80000000 + MX6SL_PAD_EPDC_D7__EPDC_DATA07 0x80000000 + MX6SL_PAD_EPDC_D8__EPDC_DATA08 0x80000000 + MX6SL_PAD_EPDC_D9__EPDC_DATA09 0x80000000 + MX6SL_PAD_EPDC_D10__EPDC_DATA10 0x80000000 + MX6SL_PAD_EPDC_D11__EPDC_DATA11 0x80000000 + MX6SL_PAD_EPDC_D12__EPDC_DATA12 0x80000000 + MX6SL_PAD_EPDC_D13__EPDC_DATA13 0x80000000 + MX6SL_PAD_EPDC_D14__EPDC_DATA14 0x80000000 + MX6SL_PAD_EPDC_D15__EPDC_DATA15 0x80000000 + MX6SL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x80000000 + MX6SL_PAD_EPDC_GDSP__EPDC_GDSP 0x80000000 + MX6SL_PAD_EPDC_GDOE__EPDC_GDOE 0x80000000 + MX6SL_PAD_EPDC_GDRL__EPDC_GDRL 0x80000000 + MX6SL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x80000000 + MX6SL_PAD_EPDC_SDOE__EPDC_SDOE 0x80000000 + MX6SL_PAD_EPDC_SDLE__EPDC_SDLE 0x80000000 + MX6SL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x80000000 + MX6SL_PAD_EPDC_BDR0__EPDC_BDR0 0x80000000 + MX6SL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x80000000 + MX6SL_PAD_EPDC_SDCE1__EPDC_SDCE1 0x80000000 + MX6SL_PAD_EPDC_SDCE2__EPDC_SDCE2 0x80000000 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0 @@ -337,6 +586,12 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1 + MX6SL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1 + >; + }; pinctrl_i2c2: i2c2grp { fsl,pins = < @@ -345,6 +600,20 @@ >; }; + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__GPIO3_IO14 0x1b8b1 + MX6SL_PAD_I2C2_SDA__GPIO3_IO15 0x1b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_EPDC_SDCE2__I2C3_SCL 0x4001b8b1 + MX6SL_PAD_EPDC_SDCE3__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_kpp: kppgrp { fsl,pins = < MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 @@ -356,7 +625,7 @@ >; }; - pinctrl_lcd: lcdgrp { + pinctrl_lcdif_dat: lcdifdatgrp { fsl,pins = < MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 @@ -382,6 +651,11 @@ MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 @@ -401,6 +675,12 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT4__SPDIF_OUT 0x80000000 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 @@ -408,6 +688,24 @@ >; }; + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT4__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT5__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4dte_1: uart4dtegrp-1 { + fsl,pins = < + MX6SL_PAD_SD1_DAT5__UART4_RX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT4__UART4_TX_DATA 0x1b0b1 + MX6SL_PAD_SD1_DAT6__UART4_CTS_B 0x1b0b1 + MX6SL_PAD_SD1_DAT7__UART4_RTS_B 0x1b0b1 + >; + }; + pinctrl_usbotg1: usbotg1grp { fsl,pins = < MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 @@ -524,9 +822,34 @@ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 >; }; + + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SL_PAD_EPDC_GDRL__CSI_MCLK 0x110b0 + MX6SL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x110b0 + MX6SL_PAD_EPDC_GDSP__CSI_VSYNC 0x110b0 + MX6SL_PAD_EPDC_GDOE__CSI_HSYNC 0x110b0 + MX6SL_PAD_EPDC_SDLE__CSI_DATA09 0x110b0 + MX6SL_PAD_EPDC_SDCLK__CSI_DATA08 0x110b0 + MX6SL_PAD_EPDC_D7__CSI_DATA07 0x110b0 + MX6SL_PAD_EPDC_D6__CSI_DATA06 0x110b0 + MX6SL_PAD_EPDC_D5__CSI_DATA05 0x110b0 + MX6SL_PAD_EPDC_D4__CSI_DATA04 0x110b0 + MX6SL_PAD_EPDC_D3__CSI_DATA03 0x110b0 + MX6SL_PAD_EPDC_D2__CSI_DATA02 0x110b0 + MX6SL_PAD_EPDC_D1__CSI_DATA01 0x110b0 + MX6SL_PAD_EPDC_D0__CSI_DATA00 0x110b0 + MX6SL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; }; }; +&pxp { + status = "okay"; +}; + &kpp { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_kpp>; @@ -545,13 +868,14 @@ &lcdif { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; lcd-supply = <®_lcd_3v3>; display = <&display0>; status = "okay"; - display0: display0 { - bits-per-pixel = <32>; + display0: display@0 { + bits-per-pixel = <16>; bus-width = <24>; display-timings { @@ -585,7 +909,21 @@ status = "okay"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + assigned-clocks = <&clks IMX6SL_CLK_SPDIF0_SEL>, + <&clks IMX6SL_CLK_SPDIF0_PODF>; + assigned-clock-parents = <&clks IMX6SL_CLK_PLL3_PFD3>; + assigned-clock-rates = <0>, <227368421>; + status = "okay"; +}; + &ssi2 { + fsl,mode = "i2s-slave"; + assigned-clocks = <&clks IMX6SL_CLK_SSI2_SEL>, + <&clks IMX6SL_CLK_SSI2>; + assigned-clock-rates = <0>, <24000000>; status = "okay"; }; @@ -600,6 +938,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg1>; disable-over-current; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; @@ -610,6 +951,14 @@ status = "okay"; }; +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -618,6 +967,8 @@ bus-width = <8>; cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -628,6 +979,8 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; @@ -637,5 +990,7 @@ pinctrl-1 = <&pinctrl_usdhc3_100mhz>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>; cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; status = "okay"; }; diff --git a/arch/arm/dts/imx6sl.dtsi b/arch/arm/dts/imx6sl.dtsi index cc9572ea286..5de9e8edf92 100644 --- a/arch/arm/dts/imx6sl.dtsi +++ b/arch/arm/dts/imx6sl.dtsi @@ -1,5 +1,6 @@ /* - * Copyright 2013 Freescale Semiconductor, Inc. + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -30,6 +31,10 @@ gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; @@ -41,6 +46,10 @@ spi3 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg1; + usb1 = &usbotg2; + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; }; cpus { @@ -65,17 +74,37 @@ 396000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ - clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, - <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, - <&clks IMX6SL_CLK_PLL1_SYS>; + clocks = <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_STEP>, + <&clks IMX6SL_CLK_PLL1_SW>, + <&clks IMX6SL_CLK_PLL1_SYS>, + <&clks IMX6SL_CLK_PLL1>, + <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", "pll1_bypass", + "pll1_bypass_src"; arm-supply = <®_arm>; pu-supply = <®_pu>; soc-supply = <®_soc>; }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + intc: interrupt-controller@00a01000 { compatible = "arm,cortex-a9-gic"; #interrupt-cells = <3>; @@ -102,6 +131,10 @@ }; }; + reg_vbus_wakeup: usb_vbus_wakeup { + compatible = "fsl,imx6-dummy-ldo2p5"; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -109,12 +142,51 @@ interrupt-parent = <&gpc>; ranges; - ocram: sram@00900000 { + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SL_CLK_PLL2_BUS>, <&clks IMX6SL_CLK_PLL2_PFD2>, + <&clks IMX6SL_CLK_PLL2_198M>, <&clks IMX6SL_CLK_ARM>, + <&clks IMX6SL_CLK_PLL3_USB_OTG>, <&clks IMX6SL_CLK_PERIPH>, + <&clks IMX6SL_CLK_PRE_PERIPH_SEL>, <&clks IMX6SL_CLK_PERIPH_CLK2_PODF>, + <&clks IMX6SL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SL_CLK_OSC>, + <&clks IMX6SL_CLK_PLL1_SYS>, <&clks IMX6SL_CLK_PERIPH2>, + <&clks IMX6SL_CLK_AHB>, <&clks IMX6SL_CLK_OCRAM_PODF>, + <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>, + <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>, + <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>, + <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>, + <&clks IMX6SL_PLL1_BYPASS_SRC>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", + "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb", + "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src", + "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src"; + fsl,max_ddr_freq = <400000000>; + }; + + ocrams: sram@00900000 { + compatible = "fsl,lpm-sram"; + reg = <0x00900000 0x4000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocrams_ddr: sram@00904000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00904000 0x1000>; + clocks = <&clks IMX6SL_CLK_OCRAM>; + }; + + ocram: sram@00905000 { compatible = "mmio-sram"; - reg = <0x00900000 0x20000>; + reg = <0x00905000 0x1B000>; clocks = <&clks IMX6SL_CLK_OCRAM>; }; + ocram_optee: sram@00918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x00918000 0x8000>; + overw_reg = <&ocram 0x00905000 0x13000>; + }; + L2: l2-cache@00a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; @@ -174,6 +246,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI1>, <&clks IMX6SL_CLK_ECSPI1>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -186,6 +260,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI2>, <&clks IMX6SL_CLK_ECSPI2>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -198,6 +274,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI3>, <&clks IMX6SL_CLK_ECSPI3>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -210,6 +288,8 @@ clocks = <&clks IMX6SL_CLK_ECSPI4>, <&clks IMX6SL_CLK_ECSPI4>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -261,8 +341,8 @@ clocks = <&clks IMX6SL_CLK_SSI1_IPG>, <&clks IMX6SL_CLK_SSI1>; clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, - <&sdma 38 1 0>; + dmas = <&sdma 37 22 0>, + <&sdma 38 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -277,8 +357,8 @@ clocks = <&clks IMX6SL_CLK_SSI2_IPG>, <&clks IMX6SL_CLK_SSI2>; clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, - <&sdma 42 1 0>; + dmas = <&sdma 41 22 0>, + <&sdma 42 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -293,8 +373,8 @@ clocks = <&clks IMX6SL_CLK_SSI3_IPG>, <&clks IMX6SL_CLK_SSI3>; clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, - <&sdma 46 1 0>; + dmas = <&sdma 45 22 0>, + <&sdma 46 22 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -530,20 +610,21 @@ anatop-min-bit-val = <4>; anatop-min-voltage = <800000>; anatop-max-voltage = <1375000>; + anatop-enable-bit = <0>; }; - regulator-3p0 { + reg_3p0: regulator-3p0@120 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; anatop-vol-bit-width = <5>; anatop-min-bit-val = <0>; anatop-min-voltage = <2625000>; anatop-max-voltage = <3400000>; + anatop-enable-bit = <0>; }; regulator-2p5 { @@ -558,6 +639,7 @@ anatop-min-bit-val = <0>; anatop-min-voltage = <2100000>; anatop-max-voltage = <2850000>; + anatop-enable-bit = <0>; }; reg_arm: regulator-vddcore { @@ -575,6 +657,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_pu: regulator-vddpu { @@ -582,7 +665,8 @@ regulator-name = "vddpu"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; - regulator-always-on; + regulator-enable-ramp-delay = <150>; + regulator-boot-on; anatop-reg-offset = <0x140>; anatop-vol-bit-shift = <9>; anatop-vol-bit-width = <5>; @@ -592,6 +676,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; reg_soc: regulator-vddsoc { @@ -609,6 +694,7 @@ anatop-min-bit-val = <1>; anatop-min-voltage = <725000>; anatop-max-voltage = <1450000>; + regulator-allow-bypass; }; }; @@ -625,6 +711,7 @@ reg = <0x020c9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; @@ -633,9 +720,16 @@ reg = <0x020ca000 0x1000>; interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6SL_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -652,7 +746,8 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - mask = <0x60>; + value = <0x61>; + mask = <0x61>; status = "disabled"; }; }; @@ -683,8 +778,12 @@ interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&intc>; pu-supply = <®_pu>; - clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, - <&clks IMX6SL_CLK_GPU2D_PODF>; + clocks = <&clks IMX6SL_CLK_GPU2D_PODF>, <&clks IMX6SL_CLK_GPU2D_OVG>, + <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_LCDIF_PIX>, <&clks IMX6SL_CLK_EPDC_AXI>, + <&clks IMX6SL_CLK_EPDC_PIX>, <&clks IMX6SL_CLK_PXP_AXI>; + clock-names = "gpu2d_podf", "gpu2d_ovg", "ipg", "lcd_axi", + "lcd_pix", "epdc_axi", "epdc_pix", "pxp_axi"; #power-domain-cells = <1>; }; @@ -700,8 +799,14 @@ }; csi: csi@020e4000 { + compatible = "fsl,imx6sl-csi"; reg = <0x020e4000 0x4000>; interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>, + <&clks IMX6SL_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; }; spdc: spdc@020e8000 { @@ -717,18 +822,26 @@ <&clks IMX6SL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; + iram = <&ocram>; /* imx6sl reuses imx6q sdma firmware */ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; }; pxp: pxp@020f0000 { + compatible = "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; reg = <0x020f0000 0x4000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_PXP_AXI>, <&clks IMX6SL_CLK_DUMMY>; + clock-names = "pxp-axi", "disp-axi"; + status = "disabled"; }; epdc: epdc@020f4000 { + compatible = "fsl,imx6sl-epdc", "fsl,imx6dl-epdc"; reg = <0x020f4000 0x4000>; interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_EPDC_AXI>, <&clks IMX6SL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; }; lcdif: lcdif@020f8000 { @@ -748,6 +861,10 @@ interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, <0 100 IRQ_TYPE_LEVEL_HIGH>, <0 101 IRQ_TYPE_LEVEL_HIGH>; + /* DCP clock always on */ + clocks = <&clks IMX6SL_CLK_DUMMY>; + clock-names = "dcp"; + status = "okay"; }; }; @@ -758,6 +875,20 @@ reg = <0x02100000 0x100000>; ranges; + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + usbotg1: usb@02184000 { compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; @@ -768,6 +899,7 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -794,6 +926,9 @@ ahb-burst-config = <0x0>; tx-burst-size-dword = <0x10>; rx-burst-size-dword = <0x10>; + phy_type = "hsic"; + fsl,usbphy = <&usbphy_nop1>; + fsl,anatop = <&anatop>; status = "disabled"; }; @@ -802,6 +937,7 @@ compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; reg = <0x02184800 0x200>; clocks = <&clks IMX6SL_CLK_USBOH3>; + vbus-wakeup-supply = <®_vbus_wakeup>; }; fec: ethernet@02188000 { @@ -897,9 +1033,11 @@ reg = <0x021b0000 0x4000>; }; - rngb: rngb@021b4000 { + rng: rng@021b4000 { + compatible = "fsl,imx6sl-rng", "fsl,imx-rng", "imx-rng"; reg = <0x021b4000 0x4000>; interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_DUMMY>; }; weim: weim@021b8000 { @@ -922,6 +1060,24 @@ reg = <0x021d8000 0x4000>; status = "disabled"; }; + + gpu: gpu@02200000 { + compatible = "fsl,imx6sl-gpu", "fsl,imx6q-gpu"; + reg = <0x02200000 0x4000>, <0x02204000 0x4000>, + <0x80000000 0x0>, <0x0 0x8000000>; + reg-names = "iobase_2d", "iobase_vg", + "phys_baseaddr", "contiguous_mem"; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>, <0 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_2d", "irq_vg"; + clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_MMDC_ROOT>, + <&clks IMX6SL_CLK_GPU2D_OVG>; + clock-names = "gpu2d_axi_clk", "openvg_axi_clk", + "gpu2d_clk"; + resets = <&src 3>, <&src 3>; + reset-names = "gpu2d", "gpuvg"; + power-domains = <&gpc 1>; + }; }; }; }; diff --git a/arch/arm/dts/imx6sll-evk.dts b/arch/arm/dts/imx6sll-evk.dts index b4af007c983..b5f06c8ffbe 100644 --- a/arch/arm/dts/imx6sll-evk.dts +++ b/arch/arm/dts/imx6sll-evk.dts @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -13,9 +14,13 @@ #include "imx6sll.dtsi" / { - model = "Freescale i.MX6SLL EVK Board"; + model = "i.MX6SLL EVK Board"; compatible = "fsl,imx6sll-evk", "fsl,imx6sll"; + chosen { + stdout-path = &uart1; + }; + memory { reg = <0x80000000 0x80000000>; }; @@ -93,7 +98,7 @@ compatible = "regulator-fixed"; reg = <4>; regulator-name = "lcd-pwr"; - gpio = <&gpio4 8 0>; + gpio = <&gpio4 3 0>; enable-active-high; }; @@ -103,6 +108,8 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <10000>; + startup-delay-us = <2000>; enable-active-high; }; @@ -120,6 +127,8 @@ regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <10000>; + startup-delay-us = <2000>; enable-active-high; }; @@ -162,11 +171,14 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; status = "okay"; - pmic: pfuze100@08 { + pmic: pfuze100@8 { compatible = "fsl,pfuze100"; reg = <0x08>; @@ -211,6 +223,7 @@ sw4_reg: sw4 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; swbst_reg: swbst { @@ -314,10 +327,10 @@ VCOM_reg: VCOM { regulator-name = "VCOM"; - /* 2's-compliment, -4325000 */ - regulator-min-microvolt = <0xffbe0178>; - /* 2's-compliment, -500000 */ - regulator-max-microvolt = <0xfff85ee0>; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; }; VNEG_reg: VNEG { @@ -339,8 +352,11 @@ &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8962@1a { @@ -485,8 +501,8 @@ MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 - MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 - MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79 + MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x17059 + MX6SLL_PAD_KEY_ROW5__GPIO4_IO03 0x17059 >; }; @@ -534,34 +550,34 @@ pinctrl_usdhc1: usdhc1grp { fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17061 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13061 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17061 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17061 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17061 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17061 >; }; pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 - MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170a1 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130a1 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170a1 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170a1 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170a1 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170a1 >; }; pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { fsl,pins = < - MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170e9 MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9 - MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 - MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 - MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 - MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170e9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170e9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170e9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170e9 >; }; @@ -615,34 +631,34 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13059 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059 + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17061 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x13061 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17061 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17061 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17061 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17061 >; }; pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130b9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170a1 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130a1 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170a1 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170a1 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170a1 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170a1 >; }; pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { fsl,pins = < - MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170e9 MX6SLL_PAD_SD3_CLK__SD3_CLK 0x130f9 - MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 - MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 - MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 - MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170e9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170e9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170e9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170e9 >; }; @@ -659,6 +675,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1 + MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6SLL_PAD_AUD_RXFS__I2C3_SCL 0x4041b8b1 @@ -666,11 +689,24 @@ >; }; + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX6SLL_PAD_AUD_RXFS__GPIO1_IO00 0x41b8b1 + MX6SLL_PAD_AUD_RXC__GPIO1_IO01 0x41b8b1 + >; + }; + pinctrl_pwm1: pmw1grp { fsl,pins = < MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 >; }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX6SLL_PAD_WDOG_B__WDOG1_B 0x170b0 + >; + }; }; }; @@ -679,11 +715,11 @@ pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; lcd-supply = <®_lcd>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { - bits-per-pixel = <16>; + display0: display@0 { + bits-per-pixel = <24>; bus-width = <24>; display-timings { @@ -753,7 +789,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>; vqmmc-supply = <®_sd2_vmmc>; bus-width = <8>; - no-removable; + non-removable; status = "okay"; }; @@ -799,3 +835,9 @@ &ssi2 { status = "okay"; }; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/dts/imx6sll-lpddr2-val.dts b/arch/arm/dts/imx6sll-lpddr2-val.dts new file mode 100644 index 00000000000..66111b85fb1 --- /dev/null +++ b/arch/arm/dts/imx6sll-lpddr2-val.dts @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-lpddr3-val.dts" + diff --git a/arch/arm/dts/imx6sll-lpddr3-val-ecspi.dts b/arch/arm/dts/imx6sll-lpddr3-val-ecspi.dts new file mode 100644 index 00000000000..60b90bd0232 --- /dev/null +++ b/arch/arm/dts/imx6sll-lpddr3-val-ecspi.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sll-lpddr3-val.dts" + +&ecspi1 { + status = "okay"; +}; + +&lcdif { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6sll-lpddr3-val.dts b/arch/arm/dts/imx6sll-lpddr3-val.dts new file mode 100644 index 00000000000..458789a394b --- /dev/null +++ b/arch/arm/dts/imx6sll-lpddr3-val.dts @@ -0,0 +1,857 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" + +/ { + model = "i.MX6SLL Validation Board"; + compatible = "fsl,imx6sll-lpddr3-val", "fsl,imx6sll"; + + memory { + reg = <0x80000000 0x80000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + users { + label = "debug"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&swbst_reg>; + }; + + reg_aud3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "wm8962-supply-3v15"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-boot-on; + }; + + reg_aud4v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "wm8962-supply-4v2"; + regulator-min-microvolt = <4325000>; + regulator-max-microvolt = <4325000>; + regulator-boot-on; + }; + + reg_lcd: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-pwr"; + gpio = <&gpio4 8 0>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + startup-delay-us = <2000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "eMMC-VCCQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD3_WIFI"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + startup-delay-us = <2000>; + enable-active-high; + }; + + }; + + sound { + compatible = "fsl,imx6sl-evk-wm8962", "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "AMIC", "MICBIAS", + "IN3R", "AMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + codec-master; + hp-det-gpios = <&gpio4 24 1>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux3>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <393216000>; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; + soc-supply = <&sw1c_reg>; +}; + +&csi { + status = "disabled"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "okay"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 13 0>; + gpio_pmic_vcom_ctrl = <&gpio2 3 0>; + gpio_pmic_wakeup = <&gpio2 14 0>; + gpio_pmic_v3p3 = <&gpio2 7 0>; + gpio_pmic_intr = <&gpio2 12 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + status = "okay"; + + codec: wm8962@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&clks IMX6SLL_CLK_EXTERN_AUDIO>; + DCVDD-supply = <&vgen3_reg>; + DBVDD-supply = <®_aud3v>; + AVDD-supply = <&vgen3_reg>; + CPVDD-supply = <&vgen3_reg>; + MICVDD-supply = <®_aud3v>; + PLLVDD-supply = <&vgen3_reg>; + SPKVDD1-supply = <®_aud4v>; + SPKVDD2-supply = <®_aud4v>; + amic-mono; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi1>; + clocks = <&clks IMX6SLL_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen6_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio1 25 1>; + rst-gpios = <&gpio1 26 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog_sd2_reset>; + + imx6sll-lpddr3-val { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x17059 + MX6SLL_PAD_GPIO4_IO22__GPIO4_IO22 0x17059 + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059 + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 + MX6SLL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059 /* SD3 CD */ + MX6SLL_PAD_KEY_COL6__GPIO4_IO04 0x17059 /*SD3 RESET */ + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* HP DETECT */ + >; + }; + + pinctrl_hog_sd2_reset: hoggrp-1 { + fsl,pins = < + MX6SLL_PAD_SD2_RESET__GPIO4_IO27 0x417059 + >; + }; + + pinctrl_audmux3: audmux3grp { + fsl,pins = < + MX6SLL_PAD_AUD_TXC__AUD3_TXC 0x4130b0 + MX6SLL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0 + MX6SLL_PAD_AUD_TXD__AUD3_TXD 0x4110b0 + MX6SLL_PAD_AUD_RXD__AUD3_RXD 0x4130b0 + MX6SLL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x4130b0 + >; + }; + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_GDRL__CSI_MCLK 0x1b088 + MX6SLL_PAD_EPDC_GDCLK__CSI_PIXCLK 0x1b088 + MX6SLL_PAD_EPDC_GDSP__CSI_VSYNC 0x1b088 + MX6SLL_PAD_EPDC_GDOE__CSI_HSYNC 0x1b088 + MX6SLL_PAD_EPDC_DATA02__CSI_DATA02 0x1b088 + MX6SLL_PAD_EPDC_DATA03__CSI_DATA03 0x1b088 + MX6SLL_PAD_EPDC_DATA04__CSI_DATA04 0x1b088 + MX6SLL_PAD_EPDC_DATA05__CSI_DATA05 0x1b088 + MX6SLL_PAD_EPDC_DATA06__CSI_DATA06 0x1b088 + MX6SLL_PAD_EPDC_DATA07__CSI_DATA07 0x1b088 + MX6SLL_PAD_EPDC_SDCLK__CSI_DATA08 0x1b088 + MX6SLL_PAD_EPDC_SDLE__CSI_DATA09 0x1b088 + MX6SLL_PAD_EPDC_SDSHR__GPIO1_IO26 0x80000000 + MX6SLL_PAD_EPDC_SDOE__GPIO1_IO25 0x80000000 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SLL_PAD_EPDC_VCOM1__GPIO2_IO04 0x17059 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 + MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 + MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 + MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 + MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 + MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 + MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 + MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 + MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 + MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 + MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 + MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 + MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 + MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 + MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 + MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 + MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 + MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 + MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 + MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 + MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 + MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 + MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 + MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 + MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA00__LCD_DATA00 0x79 + MX6SLL_PAD_LCD_DATA01__LCD_DATA01 0x79 + MX6SLL_PAD_LCD_DATA02__LCD_DATA02 0x79 + MX6SLL_PAD_LCD_DATA03__LCD_DATA03 0x79 + MX6SLL_PAD_LCD_DATA04__LCD_DATA04 0x79 + MX6SLL_PAD_LCD_DATA05__LCD_DATA05 0x79 + MX6SLL_PAD_LCD_DATA06__LCD_DATA06 0x79 + MX6SLL_PAD_LCD_DATA07__LCD_DATA07 0x79 + MX6SLL_PAD_LCD_DATA08__LCD_DATA08 0x79 + MX6SLL_PAD_LCD_DATA09__LCD_DATA09 0x79 + MX6SLL_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX6SLL_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX6SLL_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX6SLL_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX6SLL_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX6SLL_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX6SLL_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX6SLL_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX6SLL_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX6SLL_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX6SLL_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX6SLL_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX6SLL_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX6SLL_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6SLL_PAD_LCD_CLK__LCD_CLK 0x79 + MX6SLL_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX6SLL_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + MX6SLL_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX6SLL_PAD_LCD_RESET__LCD_RESET 0x79 + MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x79 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ + MX6SLL_PAD_EPDC_VCOM0__GPIO2_IO03 0x80000000 /* vcom_ctrl */ + MX6SLL_PAD_EPDC_PWR_WAKE__GPIO2_IO14 0x80000000 /* wakeup */ + MX6SLL_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 0x80000000 /* v3p3 */ + MX6SLL_PAD_EPDC_PWR_IRQ__GPIO2_IO12 0x80000000 /* pwr int */ + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SLL_PAD_SD2_RESET__SPDIF_OUT 0x4130b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x13059 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x17059 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x17059 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x17059 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x17059 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x17059 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x17059 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x17059 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x17059 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x413059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170b9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130b9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170b9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170b9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170b9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170b9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170b9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170b9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170b9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170b9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD2_CMD__SD2_CMD 0x170f9 + MX6SLL_PAD_SD2_CLK__SD2_CLK 0x130f9 + MX6SLL_PAD_SD2_DATA0__SD2_DATA0 0x170f9 + MX6SLL_PAD_SD2_DATA1__SD2_DATA1 0x170f9 + MX6SLL_PAD_SD2_DATA2__SD2_DATA2 0x170f9 + MX6SLL_PAD_SD2_DATA3__SD2_DATA3 0x170f9 + MX6SLL_PAD_SD2_DATA4__SD2_DATA4 0x170f9 + MX6SLL_PAD_SD2_DATA5__SD2_DATA5 0x170f9 + MX6SLL_PAD_SD2_DATA6__SD2_DATA6 0x170f9 + MX6SLL_PAD_SD2_DATA7__SD2_DATA7 0x170f9 + MX6SLL_PAD_GPIO4_IO21__SD2_STROBE 0x4130f9 + >; + }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x17059 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x17059 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x17059 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x17059 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__GPIO3_IO12 0x1b8b1 + MX6SLL_PAD_I2C1_SDA__GPIO3_IO13 0x1b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_EPDC_SDCE2__I2C3_SCL 0x4041b8b1 + MX6SLL_PAD_EPDC_SDCE3__I2C3_SDA 0x4041b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX6SLL_PAD_EPDC_SDCE2__GPIO1_IO29 0x41b8b1 + MX6SLL_PAD_EPDC_SDCE3__GPIO1_IO30 0x41b8b1 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6SLL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6SLL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1 + MX6SLL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1 + MX6SLL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1 + MX6SLL_PAD_ECSPI1_SS0__GPIO4_IO11 0x100b1 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + lcd-supply = <®_lcd>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pxp { + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vqmmc-supply = <®_sd2_vmmc>; + bus-width = <8>; + no-removable; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 11 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + flash: m25p80@0 { + compatible = "st,m25p32", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6sll.dtsi b/arch/arm/dts/imx6sll.dtsi index 349c47a03a2..f05fe3eb600 100644 --- a/arch/arm/dts/imx6sll.dtsi +++ b/arch/arm/dts/imx6sll.dtsi @@ -1,5 +1,6 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -37,6 +38,11 @@ spi4 = &ecspi4; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + usb0 = &usbotg1; + usb1 = &usbotg2; + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + video0 = &lcdif; }; cpus { @@ -50,14 +56,14 @@ next-level-cache = <&L2>; operating-points = < /* kHz uV */ - 996000 1225000 + 996000 1275000 792000 1175000 396000 1075000 198000 975000 >; fsl,soc-operating-points = < /* ARM kHz SOC-PU uV */ - 996000 1225000 + 996000 1175000 792000 1175000 396000 1175000 198000 1175000 @@ -166,6 +172,12 @@ reg = <0x00905000 0x1B000>; }; + ocram_optee: sram@00918000 { + compatible = "fsl,optee-lpm-sram"; + reg = <0x00918000 0x8000>; + overw_reg = <&ocram 0x00905000 0x13000>; + }; + L2: l2-cache@00a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; @@ -210,7 +222,7 @@ "rxtx1", "rxtx2", "rxtx3", "rxtx4", "rxtx5", "rxtx6", - "rxtx7", "dma"; + "rxtx7", "spba"; status = "disabled"; }; @@ -395,8 +407,8 @@ reg = <0x02098000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_GPT_BUS>, - <&clks IMX6SLL_CLK_GPT_SERIAL>; - clock-names = "ipg", "per"; + <&clks IMX6SLL_CLK_GPT_3M>; + clock-names = "ipg", "osc_per"; }; gpio1: gpio@0209c000 { @@ -528,7 +540,6 @@ fsl,tempmon = <&anatop>; fsl,tempmon-data = <&ocotp>; clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>; - status = "disabled"; }; usbphy1: usbphy@020c9000 { @@ -574,7 +585,7 @@ regmap = <&snvs>; interrupts = ; linux,keycode = ; - wakeup; + wakeup-source; }; }; @@ -629,7 +640,7 @@ }; sdma: sdma@020ec000 { - compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; + compatible = "fsl,imx6ul-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_SDMA>, @@ -689,6 +700,20 @@ reg = <0x02100000 0x100000>; ranges; + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + usbotg1: usb@02184000 { compatible = "fsl,imx6sll-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; @@ -726,7 +751,7 @@ }; usdhc1: usdhc@02190000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02190000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC1>, @@ -740,7 +765,7 @@ }; usdhc2: usdhc@02194000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02194000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC2>, @@ -754,7 +779,7 @@ }; usdhc3: usdhc@02198000 { - compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-usdhc"; + compatible = "fsl,imx6sll-usdhc", "fsl,imx7d-usdhc"; reg = <0x02198000 0x4000>; interrupts = ; clocks = <&clks IMX6SLL_CLK_USDHC3>, diff --git a/arch/arm/dts/imx6sx-14x14-val.dts b/arch/arm/dts/imx6sx-14x14-val.dts new file mode 100644 index 00000000000..25c924286bc --- /dev/null +++ b/arch/arm/dts/imx6sx-14x14-val.dts @@ -0,0 +1,1372 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "i.MX6 SoloX 14x14 VAL Board"; + compatible = "fsl,imx6sx-14x14-lpddr2-val", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sdb_vmmc: sdb_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + off-on-delay-us = <20000>; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_vref_3v3: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound { + compatible = "fsl,imx6sx-arm2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6sx-arm2-sgtl5000"; + cpu-dai = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-id = <1>; + fsl,num_tx_queues=<3>; + fsl,num_rx_queues=<3>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-id = <0>; + fsl,num_tx_queues=<3>; + fsl,num_rx_queues=<3>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; +}; + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4_1>; + pinctrl-1 = <&pinctrl_i2c4_1_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000 + /* CAN1_2_EN */ + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + /* CAN1_2_STBY_B */ + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + /* CAN1_ERR_B */ + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059 + /* CAN2_ERR_B */ + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059 + /* SD2_PWROFF */ + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_1>; + status = "disabled";/* pin conflict with usdhc2*/ +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_1>; + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + /* + * Pin conflict with others, need to switch R580 & R579 + * to B and disable pwm3 to enable it. + */ + vbus-supply = <®_usb_otg2_vbus>; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_1>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 0>; + wp-gpios = <&gpio2 15 0>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sdb_vmmc>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + bus-width = <8>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,wdog_b; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + + pinctrl_esai_2: esaigrp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_1_gpio: i2c4grp-1-gpio { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 + MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 + >; + }; + + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + + pinctrl_mlb_2: mlbgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31 + MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31 + MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31 + >; + }; + }; + + mqs { + pinctrl_mqs_1: mqsgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 + MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x70a1 + MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x70a1 + MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x70a1 + MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x70a1 + MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x70a1 + MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x70a1 + MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x70a1 + MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x70a1 + MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x70a1 + MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x70a1 + MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x70a1 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + pinctrl_usdhc4_3: usdhc4grp-3 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17071 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17071 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17071 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17071 + >; + }; + + }; + + wdog { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-17x17-val-ecspi.dts b/arch/arm/dts/imx6sx-17x17-val-ecspi.dts new file mode 100644 index 00000000000..36875a4aa90 --- /dev/null +++ b/arch/arm/dts/imx6sx-17x17-val-ecspi.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-17x17-val.dts" + +&usdhc3 { + status = "disabled"; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "okay"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts b/arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts new file mode 100644 index 00000000000..11568f441d4 --- /dev/null +++ b/arch/arm/dts/imx6sx-17x17-val-gpmi-weim.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-17x17-val.dts" + +&qspi2 { + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; diff --git a/arch/arm/dts/imx6sx-17x17-val.dts b/arch/arm/dts/imx6sx-17x17-val.dts new file mode 100644 index 00000000000..fe6750efbd6 --- /dev/null +++ b/arch/arm/dts/imx6sx-17x17-val.dts @@ -0,0 +1,1317 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "i.MX6 SoloX 17x17 VAL Board"; + compatible = "fsl,imx6sx-17x17-val", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_sdb_vmmc: sdb_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_LOW>; + off-on-delay-us = <20000>; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_vref_3v3: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound { + compatible = "fsl,imx6sx-arm2-sgtl5000", + "fsl,imx-audio-sgtl5000"; + model = "imx6sx-arm2-sgtl5000"; + cpu-dai = <&ssi1>; + audio-codec = <&codec>; + audio-routing = + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + mux-int-port = <1>; + mux-ext-port = <4>; + }; +}; + +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_2>; + status = "okay"; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 24 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_1>; + trx-en-gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + trx-stby-gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; + trx-err-gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x2>; + fsl,cpu_pupscr_sw = <0x1>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,wdog-reset = <1>; /* watchdog select of reset source */ + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; +}; + + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4_1>; + pinctrl-1 = <&pinctrl_i2c4_1_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x1f059 + MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x1f059 + MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x80000000 + /* CAN1_2_EN */ + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + /* CAN1_2_STBY_B */ + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + /* CAN1_ERR_B */ + MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x17059 + /* CAN2_ERR_B */ + MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x17059 + /* SD2_PWROFF */ + MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 + /* WDOG_B reset */ + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_1>; + status = "disabled";/* pin conflict with usdhc2*/ +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_1>; + status = "disabled"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_1>; + status = "disabled"; +}; + +&ssi1 { + fsl,mode = "i2s-slave"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + /* + * Pin conflict with others, need to switch R580 & R579 + * to B and disable pwm3 to enable it. + */ + vbus-supply = <®_usb_otg2_vbus>; + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_1>; + status = "disabled"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio2 10 0>; + wp-gpios = <&gpio2 15 0>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sdb_vmmc>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + bus-width = <8>; + non-removable; + /* need hw rework to enable signal voltage switch */ + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + canfd1 { + pinctrl_canfd1_1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + }; + + canfd2 { + pinctrl_canfd2_1: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_1_gpio: i2c4grp-1-gpio { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 + MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 + >; + }; + + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x1b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-19x19-val-ecspi.dts b/arch/arm/dts/imx6sx-19x19-val-ecspi.dts new file mode 100644 index 00000000000..fcbaf3526b7 --- /dev/null +++ b/arch/arm/dts/imx6sx-19x19-val-ecspi.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-19x19-val.dts" + +&usdhc3 { + status = "disabled"; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio7 4 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "okay"; /* pin conflict with USDHC3 */ + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts b/arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts new file mode 100644 index 00000000000..eb9738aff6e --- /dev/null +++ b/arch/arm/dts/imx6sx-19x19-val-gpmi-weim.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-19x19-val.dts" + +&qspi2 { + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; /* pin conflict with qspi*/ + nand-on-flash-bbt; +}; diff --git a/arch/arm/dts/imx6sx-19x19-val.dts b/arch/arm/dts/imx6sx-19x19-val.dts new file mode 100644 index 00000000000..76891b9ce9b --- /dev/null +++ b/arch/arm/dts/imx6sx-19x19-val.dts @@ -0,0 +1,1308 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx6sx.dtsi" + +/ { + model = "i.MX6 SoloX 19x19 VAL Board"; + compatible = "fsl,imx6sx-19x19-val", "fsl,imx6sx"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + + hannstar_cabc { + compatible = "hannstar,cabc"; + + lvds0 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + }; + }; + + clocks { + codec_osc: codec_osc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio6 18 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg1_vbus"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&cs42888>; + }; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai_1>; + status = "okay"; +}; + +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1075000 + 198000 975000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1175000 + 792000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1c_reg>; + regulator-allow-bypass; +}; + +&gpc { + fsl,ldo-bypass = <1>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + pinctrl-assert-gpios = <&max7322_1 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + pinctrl-assert-gpios = <&max7322_2 0 GPIO_ACTIVE_HIGH>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322_1: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + max7322_2: gpio@69 { + compatible = "maxim,max7322"; + reg = <0x69>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_1>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio3 26 1>; + rst-gpios = <&gpio3 25 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4_2>; + pinctrl-1 = <&pinctrl_i2c4_2_gpio>; + scl-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + clocks = <&codec_osc>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <®_3p3v>; + }; + + cs42888: cs42888@048 { + compatible = "cirrus,cs42888"; + reg = <0x048>; + clocks = <&clks IMX6SX_CLK_ESAI_EXTAL>; + clock-names = "mclk"; + VA-supply = <®_3p3v>; + VD-supply = <®_3p3v>; + VLS-supply = <®_3p3v>; + VLC-supply = <®_3p3v>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + hog { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x1b0b0 + MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x1b0b0 + >; + }; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat_0 + &pinctrl_lcdif_ctrl_0>; + display = <&display0>; + status = "disabled"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + + display1: display { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_1>; + status = "disabled"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&qspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi2_1>; + status = "okay"; + ddrsmp=<2>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + reg = <1>; + }; +}; + +&usbh { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usbh_1>; + pinctrl-1 = <&pinctrl_usbh_2>; + osc-clkgate-delay = <0x3>; + pad-supply = <&vgen1_reg>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_1>; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + bus-width = <4>; + keep-power-in-suspend; + enable-sdio-wakeup; + no-1-8-v; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0x50000000 0x08000000>; + status = "disabled"; /* pin conflict with qspi, nand and lcd1 */ + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x02000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00610081 0x00000001 0x1c022000 + 0x0000c000 0x1404a38e 0x00000000>; + }; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130B0 + MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130B0 + MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120B0 + MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + + pinctrl_audmux_2: audmuxgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x130b0 + MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x130b0 + MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x130b0 + MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x130b0 + >; + }; + }; + + ecspi4 { + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x80000000 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x100b1 + MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x100b1 + MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x100b1 + >; + }; + }; + + canfd1 { + pinctrl_canfd1_1: canfd1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x1b0b0 + >; + }; + }; + + canfd2 { + pinctrl_canfd2_1: canfd2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x1b0b0 + >; + }; + }; + + csi { + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_csi_1: csigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x110b0 + MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x110b0 + MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x110b0 + MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x110b0 + MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x110b0 + MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x110b0 + MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x110b0 + MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x110b0 + MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x110b0 + MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x110b0 + MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x110b0 + + MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x80000000 + MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x80000000 + >; + }; + }; + + enet1 { + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet1_clkout_1: enet1_clkoutgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + }; + + enet2 { + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + }; + + esai { + pinctrl_esai_1: esaigrp-1 { + fsl,pins = < + MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x1b030 + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + }; + + flexcan1 { + pinctrl_flexcan1_1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0 + >; + }; + }; + + flexcan2 { + pinctrl_flexcan2_1: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0 + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1 + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_i2c3_2: i2c3grp-2 { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + }; + + i2c4 { + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_2: i2c4grp-2 { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x4001b8b1 + MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c4_2_gpio: i2c4grp-2-gpio { + fsl,pins = < + MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x1b8b1 + MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x1b8b1 + >; + }; + }; + + lcdif1 { + pinctrl_lcdif_dat_0: lcdifdatgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl_0: lcdifctrlgrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + }; + + mlb { + pinctrl_mlb_1: mlbgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_DATA3__MLB_DATA 0x31 + MX6SX_PAD_SD2_CLK__MLB_SIG 0x31 + MX6SX_PAD_SD2_CMD__MLB_CLK 0x31 + >; + }; + }; + + mqs { + pinctrl_mqs_1: mqsgrp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x80000000 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x80000000 + >; + }; + }; + + pwm3 { + pinctrl_pwm3_0: pwm3grp-0 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x110b0 + >; + }; + + pinctrl_pwm3_1: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + }; + + pwm4 { + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + }; + + qspi2 { + pinctrl_qspi2_1: qspi2grp_1 { + fsl,pins = < + MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70a1 + MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70a1 + MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70a1 + MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70a1 + MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70a1 + MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70a1 + MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70a1 + MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70a1 + MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70a1 + MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70a1 + MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70a1 + MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70a1 + >; + }; + }; + + sai1 { + pinctrl_sai1_1: sai1grp_1 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x1b030 + MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x1b030 + MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x1b030 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x1b030 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x1b030 + >; + }; + + pinctrl_sai1_2: sai1grp_2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x130B0 + MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x130B0 + MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x120B0 + MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x130B0 + MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130B0 + >; + }; + }; + + sai2 { + pinctrl_sai2_1: sai2grp_1 { + fsl,pins = < + MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x1b030 + MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x1b030 + MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x1b030 + MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x1b030 + >; + }; + }; + + + spdif { + pinctrl_spdif_1: spdifgrp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x1b0b0 + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_spdif_2: spdifgrp-2 { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 + MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1 + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1 + MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1 + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1 + MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1 + >; + }; + }; + + uart5 { + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + }; + + usbh { + pinctrl_usbh_1: usbhgrp-1 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40013030 + MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x40013030 + >; + }; + + pinctrl_usbh_2: usbhgrp-2 { + fsl,pins = < + MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x40017030 + >; + }; + }; + + usbotg1 { + pinctrl_usb_otg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usbotg1_1: usbotg1grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_2: usbotg1grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg1_3: usbotg1grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x17059 + >; + }; + }; + + usbotg2 { + pinctrl_usbotg2_1: usbotg2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_2: usbotg2grp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x17059 + >; + }; + + pinctrl_usbotg2_3: usbotg2grp-3 { + fsl,pins = < + MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x17059 + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059 + MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059 + MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059 + MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059 + MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059 + MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059 + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9 + >; + }; + + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + >; + }; + + }; + + wdog { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x10b0 + >; + }; + }; + + weim { + pinctrl_weim_cs0_1: weim_cs0grp-1 { + fsl,pins = < + MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0xb0b1 + >; + }; + + pinctrl_weim_nor_1: weim_norgrp-1 { + fsl,pins = < + MX6SX_PAD_NAND_CE1_B__WEIM_OE 0xb0b1 + MX6SX_PAD_NAND_RE_B__WEIM_RW 0xb0b1 + MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0xb060 + /* data */ + MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x1b0b0 + MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x1b0b0 + MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x1b0b0 + MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x1b0b0 + MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x1b0b0 + MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x1b0b0 + MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x1b0b0 + MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x1b0b0 + MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x1b0b0 + MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x1b0b0 + /* address */ + MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0xb0b1 + MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0xb0b1 + MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0xb0b1 + MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0xb0b1 + MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0xb0b1 + MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0xb0b1 + MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0xb0b1 + MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0xb0b1 + MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0xb0b1 + MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0xb0b1 + MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0xb0b1 + MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0xb0b1 + MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0xb0b1 + MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0xb0b1 + MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0xb0b1 + MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0xb0b1 + MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0xb0b1 + MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0xb0b1 + MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0xb0b1 + MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0xb0b1 + MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0xb0b1 + MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0xb0b1 + MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0xb0b1 + MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0xb0b1 + MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0xb0b1 + MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0xb0b1 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-pinfunc.h b/arch/arm/dts/imx6sx-pinfunc.h index aa194a2fdd5..a3e51b1411f 100644 --- a/arch/arm/dts/imx6sx-pinfunc.h +++ b/arch/arm/dts/imx6sx-pinfunc.h @@ -66,6 +66,7 @@ #define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0 #define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO06__UART1_CTS_B 0x002C 0x0374 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0 @@ -75,6 +76,7 @@ #define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0 #define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO07__UART1_RTS_B 0x0030 0x0378 0x082C 0x4 0x1 #define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0 @@ -84,6 +86,7 @@ #define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0 #define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1 #define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO08__UART2_CTS_B 0x0034 0x037C 0x0000 0x4 0x0 #define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0 @@ -93,6 +96,7 @@ #define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0 #define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0 #define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0000 0x4 0x0 +#define MX6SX_PAD_GPIO1_IO09__UART2_RTS_B 0x0038 0x0380 0x0834 0x4 0x1 #define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0 #define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0 #define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0 @@ -200,6 +204,7 @@ #define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2 #define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0 #define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0 +#define MX6SX_PAD_CSI_DATA06__UART6_CTS_B 0x0064 0x03AC 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0 @@ -210,6 +215,7 @@ #define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2 #define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0 #define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0000 0x4 0x0 +#define MX6SX_PAD_CSI_DATA07__UART6_RTS_B 0x0068 0x03B0 0x0854 0x4 0x1 #define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0 #define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0 @@ -219,6 +225,7 @@ #define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1 #define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1 #define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2 +#define MX6SX_PAD_CSI_HSYNC__UART4_CTS_B 0x006C 0x03B4 0x0000 0x3 0x0 #define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0 @@ -251,6 +258,7 @@ #define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1 #define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1 #define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0000 0x3 0x0 +#define MX6SX_PAD_CSI_VSYNC__UART4_RTS_B 0x0078 0x03C0 0x0844 0x3 0x3 #define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0 #define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0 #define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0 @@ -304,20 +312,6 @@ #define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 #define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 #define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 -/* - * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is - * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a - * PHY in RMII mode. This configuration is valid if: - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set - * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset - * It seems to be a silicon bug that in this configuration ENET1_TX reference - * clock isn't provided automatically. According to i.MX6SX reference manual - * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it - * should be the case. - * So this might have unwanted side effects for other hardware units that are - * also connected to that pin and using respective function as input (e.g. - * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). - */ #define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 #define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 #define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 @@ -353,6 +347,7 @@ #define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0 #define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1 #define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2 +#define MX6SX_PAD_ENET2_RX_CLK__UART1_CTS_B 0x009C 0x03E4 0x0000 0x3 0x0 #define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1 #define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1 @@ -363,6 +358,7 @@ #define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1 #define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1 #define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x0000 0x3 0x0 +#define MX6SX_PAD_ENET2_TX_CLK__UART1_RTS_B 0x00A0 0x03E8 0x082C 0x3 0x3 #define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1 #define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0 #define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0 @@ -372,6 +368,7 @@ #define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2 +#define MX6SX_PAD_KEY_COL0__UART6_CTS_B 0x00A4 0x03EC 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0 #define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0 #define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0 @@ -390,6 +387,7 @@ #define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1 #define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2 +#define MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x00AC 0x03F4 0x0000 0x2 0x0 #define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0 #define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0 #define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0 @@ -415,6 +413,7 @@ #define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0 #define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW0__UART6_RTS_B 0x00B8 0x0400 0x0854 0x2 0x3 #define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0 #define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0 #define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0 @@ -434,6 +433,7 @@ #define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0 #define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1 #define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x0000 0x2 0x0 +#define MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x00C0 0x0408 0x084C 0x2 0x3 #define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1 #define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1 #define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0 @@ -816,6 +816,7 @@ #define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0 +#define MX6SX_PAD_NAND_DATA04__UART3_CTS_B 0x0160 0x04A8 0x0000 0x3 0x0 #define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0 #define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0 @@ -826,6 +827,7 @@ #define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0 #define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0 #define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x0000 0x3 0x0 +#define MX6SX_PAD_NAND_DATA05__UART3_RTS_B 0x0164 0x04AC 0x083C 0x3 0x1 #define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0 #define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0 #define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0 @@ -968,6 +970,7 @@ #define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0 #define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x0000 0x1 0x0 +#define MX6SX_PAD_QSPI1B_DATA0__UART3_RTS_B 0x01A0 0x04E8 0x083C 0x1 0x4 #define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1 @@ -976,6 +979,7 @@ #define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0 #define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0 #define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5 +#define MX6SX_PAD_QSPI1B_DATA1__UART3_CTS_B 0x01A4 0x04EC 0x0000 0x1 0x0 #define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1 #define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2 #define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1 @@ -1247,6 +1251,7 @@ #define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0 #define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0000 0x4 0x0 +#define MX6SX_PAD_SD1_DATA2__UART2_RTS_B 0x0230 0x0578 0x0834 0x4 0x2 #define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0 @@ -1256,6 +1261,7 @@ #define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2 #define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0 #define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3 +#define MX6SX_PAD_SD1_DATA3__UART2_CTS_B 0x0234 0x057C 0x0000 0x4 0x0 #define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0 #define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0 #define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2 @@ -1326,6 +1332,7 @@ #define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0000 0x1 0x0 +#define MX6SX_PAD_SD3_CLK__UART4_RTS_B 0x0250 0x0598 0x0844 0x1 0x0 #define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0 #define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0 #define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0 @@ -1365,6 +1372,7 @@ #define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0 #define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0 #define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1 +#define MX6SX_PAD_SD3_DATA2__UART4_CTS_B 0x0260 0x05A8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0 #define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0 #define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0 @@ -1410,6 +1418,7 @@ #define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0 #define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0 #define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2 +#define MX6SX_PAD_SD3_DATA6__UART3_CTS_B 0x0270 0x05B8 0x0000 0x3 0x0 #define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0 @@ -1420,6 +1429,7 @@ #define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0 #define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0 #define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x0000 0x3 0x0 +#define MX6SX_PAD_SD3_DATA7__UART3_RTS_B 0x0274 0x05BC 0x083C 0x3 0x3 #define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0 #define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0 #define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0 @@ -1511,6 +1521,7 @@ #define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0 +#define MX6SX_PAD_SD4_DATA6__UART5_CTS_B 0x0298 0x05E0 0x0000 0x2 0x0 #define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0 #define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0 @@ -1521,6 +1532,7 @@ #define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0 #define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0 #define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x0000 0x2 0x0 +#define MX6SX_PAD_SD4_DATA7__UART5_RTS_B 0x029C 0x05E4 0x084C 0x2 0x1 #define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0 #define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0 #define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0 diff --git a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi index 549461df71e..6196231f800 100644 --- a/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi +++ b/arch/arm/dts/imx6sx-sabreauto-u-boot.dtsi @@ -14,3 +14,19 @@ compatible = "jedec,spi-nor"; }; }; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; diff --git a/arch/arm/dts/imx6sx-sabreauto.dts b/arch/arm/dts/imx6sx-sabreauto.dts index 9643d1fe064..6c9f1dedbf7 100644 --- a/arch/arm/dts/imx6sx-sabreauto.dts +++ b/arch/arm/dts/imx6sx-sabreauto.dts @@ -1,5 +1,6 @@ /* * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -11,18 +12,86 @@ #include "imx6sx.dtsi" / { - model = "Freescale i.MX6 SoloX Sabre Auto Board"; + model = "i.MX6 SoloX Sabre Auto Board"; compatible = "fsl,imx6sx-sabreauto", "fsl,imx6sx"; + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; + }; + + clocks { + codec_osc: anaclk2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + }; + + max7310_reset: max7310-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + memory { reg = <0x80000000 0x80000000>; }; + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; + reg_audio: cs42888_supply { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vio1: vio1_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vio2: vio2_tnr { + compatible = "regulator-fixed"; + regulator-name = "vio2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_vd: f3v3_tnr { + compatible = "regulator-fixed"; + regulator-name = "vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + si4763_va: f5v_tnr { + compatible = "regulator-fixed"; + regulator-name = "va"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + vcc_sd3: regulator@0 { compatible = "regulator-fixed"; reg = <0>; @@ -34,51 +103,349 @@ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_usb_otg1_vbus: usb_otg1_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 0>; + enable-active-high; + }; + + reg_usb_otg2_vbus: usb_otg2_vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2_vbus>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 0>; + enable-active-high; + }; + + reg_can_wake: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "can-wake"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can_en: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_wake>; + }; + + reg_can_stby: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&max7310_b 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_can_en>; + }; + + reg_vref_3v3: regulator@4 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + }; + + sound-cs42888 { + compatible = "fsl,imx6-sabreauto-cs42888", + "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + esai-controller = <&esai>; + asrc-controller = <&asrc>; + audio-codec = <&codec>; + }; + + sound-fm { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si4763"; + + ssi-controller = <&ssi2>; + fm-controller = <&si476x_codec>; + mux-int-port = <2>; + mux-ext-port = <5>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-in; }; }; -&uart1 { +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&audmux { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; + pinctrl-0 = <&pinctrl_audmux_3>; status = "okay"; }; -&usdhc3 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>; - bus-width = <8>; - cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; - keep-power-in-suspend; - wakeup-source; - vmmc-supply = <&vcc_sd3>; +&clks { + assigned-clocks = <&clks IMX6SX_PLL4_BYPASS_SRC>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_PLL4_POST_DIV>; + assigned-clock-parents = <&clks IMX6SX_CLK_LVDS2_IN>, + <&clks IMX6SX_PLL4_BYPASS_SRC>; + assigned-clock-rates = <0>, <0>, <24576000>; +}; + +&esai { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai_2>; + assigned-clocks = <&clks IMX6SX_CLK_ESAI_SEL>, + <&clks IMX6SX_CLK_ESAI_EXTAL>; + assigned-clock-parents = <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <24576000>; status = "okay"; }; -&usdhc4 { +&fec1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc4>; - bus-width = <8>; - cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; + pinctrl-0 = <&pinctrl_enet1_1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2_1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can_stby>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + nand-on-flash-bbt; status = "okay"; }; &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; status = "okay"; + + codec: cs42888@048 { + compatible = "cirrus,cs42888"; + reg = <0x048>; + clocks = <&codec_osc 0>; + clock-names = "mclk"; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + }; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio6>; + interrupts = <22 2>; + wakeup-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; + }; + + si4763: si4763@63 { + compatible = "si4761"; + reg = <0x63>; + va-supply = <&si4763_va>; + vd-supply = <&si4763_vd>; + vio1-supply = <&si4763_vio1>; + vio2-supply = <&si4763_vio2>; + revision-a10; /* set to default A10 compatible command set */ + + si476x_codec: si476x-codec { + compatible = "si476x-codec"; + }; + }; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + out-default = /bits/ 16 <0x1 0x1>; + }; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; }; &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3_2>; + pinctrl-1 = <&pinctrl_i2c3_2_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; status = "okay"; max7310_a: gpio@30 { @@ -86,6 +453,7 @@ reg = <0x30>; gpio-controller; #gpio-cells = <2>; + resets = <&max7310_reset>; }; max7310_b: gpio@32 { @@ -93,9 +461,84 @@ reg = <0x32>; gpio-controller; #gpio-cells = <2>; + resets = <&max7310_reset>; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <7>; + interrupt-parent = <&gpio3>; + interrupts = <24 8>; + interrupt-route = <1>; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <6 1>; + }; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio3>; + interrupts = <23 2>; + }; + +}; + +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; + status = "okay"; + + display1: display@1 { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; }; }; +&mlb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mlb_2>; + status = "okay"; +}; + +&pcie { + reset-gpio = <&max7310_b 3 0>; + status = "okay"; +}; + &qspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi1_1>; @@ -119,8 +562,192 @@ }; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_3>; + status = "okay"; +}; + +&ssi2 { + fsl,mode = "i2s-master"; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + status = "okay"; +}; + +&uart5 { /* for bluetooth */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_1>; + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + cd-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <&vcc_sd3>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4_0>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + &iomuxc { imx6x-sabreauto { + pinctrl_audmux_3: audmux-3 { + fsl,pins = < + MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x130b0 + MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x130b0 + MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x130b0 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x80000000 + >; + }; + + pinctrl_enet1_1: enet1grp-1 { + fsl,pins = < + MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 + MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1 + MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081 + MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + >; + }; + + pinctrl_enet2_1: enet2grp-1 { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 + >; + }; + + pinctrl_esai_2: esaigrp-2 { + fsl,pins = < + MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x1b030 + MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x1b030 + MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x1b030 + MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x1b030 + MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x1b030 + MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x1b030 + MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x1b030 + MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x1b030 + MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x1b030 + >; + }; + + pinctrl_flexcan1: flexcan1grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b020 + MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp-1 { + fsl,pins = < + MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b020 + MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b020 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + pinctrl_i2c2_1: i2c2grp-1 { fsl,pins = < MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 @@ -128,6 +755,13 @@ >; }; + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; + pinctrl_i2c3_2: i2c3grp-2 { fsl,pins = < MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 @@ -135,6 +769,27 @@ >; }; + pinctrl_i2c3_2_gpio: i2c3grp-2-gpio { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 + >; + }; + + pinctrl_mlb_2: mlbgrp-2 { + fsl,pins = < + MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x31 + MX6SX_PAD_ENET2_CRS__MLB_SIG 0x31 + MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x31 + >; + }; + + pinctrl_pwm4_0: pwm4grp-0 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + pinctrl_qspi1_1: qspi1grp_1 { fsl,pins = < MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x70a1 @@ -152,6 +807,12 @@ >; }; + pinctrl_spdif_3: spdifgrp-3 { + fsl,pins = < + MX6SX_PAD_ENET2_COL__SPDIF_IN 0x1b0b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1 @@ -159,6 +820,49 @@ >; }; + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1 + MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1 + >; + }; + + pinctrl_uart5_1: uart5grp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 @@ -171,8 +875,8 @@ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 - MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ - MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ + MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x17059 /* CD */ + MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x17059 /* WP */ >; }; @@ -208,14 +912,13 @@ pinctrl_usdhc4: usdhc4grp { fsl,pins = < - MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 - MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 - MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 - MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 - MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 - MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 - MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */ - MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */ + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17071 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10071 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17071 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17071 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17071 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17071 + MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x17071 /* CD */ >; }; @@ -224,5 +927,48 @@ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; }; }; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/dts/imx6sx-sdb-emmc.dts b/arch/arm/dts/imx6sx-sdb-emmc.dts new file mode 100644 index 00000000000..6a2a07b0e2b --- /dev/null +++ b/arch/arm/dts/imx6sx-sdb-emmc.dts @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6sx-sdb.dts" + +/* + * The eMMC chip on imx6sx sdb board is DNP by default. + * Need do hw rework to burn the eMMC4.5 chip on the eMMC socket on uSDHC4 + * and connect eMMC signals as well as disconnect BOOT SD CARD slot signals + */ +&usdhc4 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc4_1>; + pinctrl-1 = <&pinctrl_usdhc4_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc4_1_200mhz>; + bus-width = <8>; + /* + * overwrite cd-gpios and wp-gpios since they are reused as eMMC DATA + * signals after rework + */ + cd-gpios = <>; + wp-gpios = <>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6sx-sdb-u-boot.dtsi b/arch/arm/dts/imx6sx-sdb-u-boot.dtsi new file mode 100644 index 00000000000..226d8c4a71b --- /dev/null +++ b/arch/arm/dts/imx6sx-sdb-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +ðphy1 { + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +ðphy2 { + vddio2: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; diff --git a/arch/arm/dts/imx6sx-sdb.dts b/arch/arm/dts/imx6sx-sdb.dts index 5a63ca61572..d1d9e0b7613 100644 --- a/arch/arm/dts/imx6sx-sdb.dts +++ b/arch/arm/dts/imx6sx-sdb.dts @@ -5,116 +5,56 @@ #include "imx6sx-sdb.dtsi" / { - model = "Freescale i.MX6 SoloX SDB RevB Board"; -}; + model = "NXP i.MX6 SoloX SDB RevB Board"; -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic: pfuze100@8 { - compatible = "fsl,pfuze200"; - reg = <0x08>; - - regulators { - sw1a_reg: sw1ab { - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1875000>; - regulator-boot-on; - regulator-always-on; - regulator-ramp-delay = <6250>; - }; - - sw2_reg: sw2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3a_reg: sw3a { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3b_reg: sw3b { - regulator-min-microvolt = <400000>; - regulator-max-microvolt = <1975000>; - regulator-boot-on; - regulator-always-on; - }; - - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; - }; - - snvs_reg: vsnvs { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <3000000>; - regulator-boot-on; - regulator-always-on; - }; - - vref_reg: vrefddr { - regulator-boot-on; - regulator-always-on; - }; - - vgen1_reg: vgen1 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - regulator-always-on; - }; - - vgen2_reg: vgen2 { - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1550000>; - }; - - vgen3_reg: vgen3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen4_reg: vgen4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen5_reg: vgen5 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vgen6_reg: vgen6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + regulators { + /* Transceiver EN/STBY is active low on RevB board */ + reg_can_stby: regulator@10 { + gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; }; }; }; +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC uV */ + 996000 1250000 + 792000 1175000 + 396000 1175000 + >; + + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + &qspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi2>; status = "okay"; +#ifndef SPANSIONFLASH + ddrsmp=<0>; + flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; reg = <0>; }; @@ -123,18 +63,17 @@ #size-cells = <1>; compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; reg = <2>; }; +#endif }; -®_arm { - vin-supply = <&sw1a_reg>; +&usbphy1 { + fsl,tx-d-cal = <106>; }; -®_soc { - vin-supply = <&sw1a_reg>; +&usbphy2 { + fsl,tx-d-cal = <106>; }; ®_vdd1p1 { diff --git a/arch/arm/dts/imx6sx-sdb.dtsi b/arch/arm/dts/imx6sx-sdb.dtsi index f6972deb5e3..e53b40fb060 100644 --- a/arch/arm/dts/imx6sx-sdb.dtsi +++ b/arch/arm/dts/imx6sx-sdb.dtsi @@ -9,7 +9,7 @@ #include "imx6sx.dtsi" / { - model = "Freescale i.MX6 SoloX SDB Board"; + model = "NXP i.MX6 SoloX SDB Board"; compatible = "fsl,imx6sx-sdb", "fsl,imx6sx"; chosen { @@ -21,11 +21,19 @@ reg = <0x80000000 0x40000000>; }; - backlight_display: backlight-display { + backlight1 { compatible = "pwm-backlight"; pwms = <&pwm3 0 5000000>; brightness-levels = <0 4 8 16 32 64 128 255>; default-brightness-level = <6>; + fb-names = "mxs-lcdif0"; + }; + backlight2 { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + fb-names = "mxs-lcdif1"; }; gpio-keys { @@ -48,113 +56,143 @@ }; }; - vcc_sd3: regulator-vcc-sd3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_vcc_sd3>; - regulator-name = "VCC_SD3"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; - enable-active-high; + hannstar_cabc { + compatible = "hannstar,cabc"; + lvds0 { + gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; + }; }; - reg_usb_otg1_vbus: regulator-usb-otg1-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + pxp_v4l2_out { + compatible = "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg2>; - regulator-name = "usb_otg2_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_psu_5v: regulator-psu-5v { - compatible = "regulator-fixed"; - regulator-name = "PSU-5V0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + vcc_sd3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_vcc_sd3>; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; - reg_lcd_3v3: regulator-lcd-3v3 { - compatible = "regulator-fixed"; - regulator-name = "lcd-3v3"; - gpio = <&gpio3 27 0>; - enable-active-high; - }; + reg_usb_otg1_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_peri_3v3: regulator-peri-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_peri_3v3>; - regulator-name = "peri_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - }; + reg_usb_otg2_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg2>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; - reg_enet_3v3: regulator-enet-3v3 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet_3v3>; - regulator-name = "enet_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 6 GPIO_ACTIVE_LOW>; - regulator-boot-on; - regulator-always-on; - }; + reg_psu_5v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "PSU-5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; - reg_pcie_gpio: regulator-pcie-gpio { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcie_reg>; - regulator-name = "MPCIE_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio2 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; + reg_lcd_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + status = "disabled"; + }; - reg_lcd_5v: regulator-lcd-5v { - compatible = "regulator-fixed"; - regulator-name = "lcd-5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + reg_peri_3v3: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_peri_3v3>; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; - reg_can_en: regulator-can-en { - compatible = "regulator-fixed"; - regulator-name = "can-en"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + reg_enet_3v3: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_3v3>; + regulator-name = "enet_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_pcie: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 1 0>; + regulator-always-on; + enable-active-high; + }; + + reg_can_en: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "can-en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; - reg_can_stby: regulator-can-stby { - compatible = "regulator-fixed"; - regulator-name = "can-stby"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + reg_can_stby: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "can-stby"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; sound { compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962"; model = "wm8962-audio"; - ssi-controller = <&ssi2>; + cpu-dai = <&ssi2>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HPOUTL", @@ -165,28 +203,48 @@ "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <6>; + codec-master; + hp-det-gpios = <&gpio1 17 1>; }; - panel { - compatible = "sii,43wvf1g"; - backlight = <&backlight_display>; - dvdd-supply = <®_lcd_3v3>; - avdd-supply = <®_lcd_5v>; + sound-spdif { + compatible = "fsl,imx-audio-spdif", + "fsl,imx6sx-sdb-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif>; + spdif-out; + }; - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; + sii902x_reset: sii902x-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 27 1>; + reset-delay-us = <100000>; + #reset-cells = <0>; + status = "disabled"; }; }; +&adc1 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_3v3>; + status = "okay"; +}; + &audmux { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; status = "okay"; }; + +&gpc { + fsl,ldo-bypass = <1>; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; @@ -210,10 +268,41 @@ }; }; +&csi1 { + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +&csi2 { + status = "okay"; + port { + csi2_ep: endpoint { + remote-endpoint = <&vadc_ep>; + }; + }; +}; + +&dcic1 { + dcic_id = <0>; + dcic_mux = "dcic-lcdif1"; + status = "okay"; +}; + +&dcic2 { + dcic_id = <1>; + dcic_mux = "dcic-lvds"; + status = "okay"; +}; + &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-handle = <ðphy2>; status = "okay"; }; @@ -232,17 +321,200 @@ status = "okay"; }; +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + ov5640: ov5640@3c { + compatible = "ovti,ov5640"; + reg = <0x3c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_0>; + clocks = <&clks IMX6SX_CLK_CSI>; + clock-names = "csi_mclk"; + AVDD-supply = <&vgen3_reg>; /* 2.8v */ + DVDD-supply = <&vgen2_reg>; /* 1.5v*/ + pwn-gpios = <&gpio3 28 1>; + rst-gpios = <&gpio3 27 0>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_ep: endpoint { + remote-endpoint = <&csi1_ep>; + }; + }; + }; + + sii902x@39 { + compatible = "SiI,sii902x"; + interrupt-parent = <&gpio4>; + interrupts = <21 2>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + resets = <&sii902x_reset>; + reg = <0x39>; + status = "disabled"; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + egalax_ts@04 { + compatible = "eeti,egalax_ts"; + reg = <0x04>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_egalax_int>; + interrupt-parent = <&gpio4>; + interrupts = <19 2>; + wakeup-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + }; +}; + &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; status = "okay"; + + isl29023@44 { + compatible = "fsl,isl29023"; + reg = <0x44>; + rext = <499>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mag3110@0e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + interrupt-parent = <&gpio6>; + interrupts = <5 1>; + shared-interrupt; + }; + + mma8451@1c { + compatible = "fsl,mma8451"; + reg = <0x1c>; + position = <1>; + interrupt-parent = <&gpio6>; + interrupts = <2 8>; + interrupt-route = <2>; + }; }; &i2c4 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8962@1a { @@ -257,6 +529,39 @@ PLLVDD-supply = <&vgen4_reg>; SPKVDD1-supply = <®_psu_5v>; SPKVDD2-supply = <®_psu_5v>; + amic-mono; + }; +}; + +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "disabled"; + + display0: display@0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; }; }; @@ -264,18 +569,38 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie_gpio>; status = "okay"; }; -&lcdif1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcd>; +&lcdif2 { + display = <&display1>; + disp-dev = "ldb"; status = "okay"; - - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; + display1: display@1 { + bits-per-pixel = <16>; + bus-width = <18>; + }; +}; +&ldb { + status = "okay"; + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "lcdif2"; + status = "okay"; + display-timings { + native-mode = <&timing1>; + timing1: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; }; }; }; @@ -286,6 +611,16 @@ status = "okay"; }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + &snvs_poweroff { status = "okay"; }; @@ -296,7 +631,20 @@ status = "disabled"; }; +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + &ssi2 { + assigned-clocks = <&clks IMX6SX_CLK_PLL4>, + <&clks IMX6SX_PLL4_BYPASS>, + <&clks IMX6SX_CLK_SSI2_SEL>; + assigned-clock-parents = <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_PLL4>, + <&clks IMX6SX_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <737280000>, <0>, <0>; status = "okay"; }; @@ -311,12 +659,18 @@ pinctrl-0 = <&pinctrl_uart5>; uart-has-rtscts; status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart5dte_1>; */ }; &usbotg1 { vbus-supply = <®_usb_otg1_vbus>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; status = "okay"; }; @@ -373,7 +727,25 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_can_gpios>; + imx6x-sdb { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x17059 + MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0xb000 + MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x17059 + >; + }; + + pinctrl_can_gpios: can-gpios { + fsl,pins = < + MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x17059 + MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x17059 + >; + }; + pinctrl_audmux: audmuxgrp { fsl,pins = < MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0 @@ -384,11 +756,38 @@ >; }; + pinctrl_csi_0: csigrp-0 { + fsl,pins = < + MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x110b0 + MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x110b0 + MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x110b0 + MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x110b0 + MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x110b0 + MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x110b0 + MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x110b0 + MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x110b0 + MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x110b0 + MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x110b0 + MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x110b0 + MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x110b0 + MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x110b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x80000000 + MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x80000000 + >; + }; + + pinctrl_egalax_int: egalax_intgrp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x80000000 + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1 - MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1 + MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1 @@ -457,10 +856,37 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x1b8b1 + MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x1b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1 + MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x1b8b1 + MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x1b8b1 + >; + }; pinctrl_i2c3: i2c3grp { fsl,pins = < - MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 - MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1 + MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x1b8b1 + MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x1b8b1 >; }; @@ -471,6 +897,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4grp-gpio { + fsl,pins = < + MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x1b8b1 + MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x1b8b1 + >; + }; + pinctrl_lcd: lcdgrp { fsl,pins = < MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 @@ -505,6 +938,13 @@ >; }; + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x120b0 + MX6SX_PAD_SD2_CMD__MQS_LEFT 0x120b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x10b0 @@ -529,6 +969,12 @@ >; }; + pinctrl_pwm4: pwm4grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x110b0 + >; + }; + pinctrl_qspi2: qspi2grp { fsl,pins = < MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1 @@ -546,6 +992,12 @@ >; }; + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x1b0b0 + >; + }; + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 @@ -578,6 +1030,15 @@ >; }; + pinctrl_uart5dte_1: uart5dtegrp-1 { + fsl,pins = < + MX6SX_PAD_KEY_ROW3__UART5_TX 0x1b0b1 + MX6SX_PAD_KEY_COL3__UART5_RX 0x1b0b1 + MX6SX_PAD_KEY_ROW2__UART5_RTS_B 0x1b0b1 + MX6SX_PAD_KEY_COL2__UART5_CTS_B 0x1b0b1 + >; + }; + pinctrl_usb_otg1: usbotg1grp { fsl,pins = < MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0 @@ -609,16 +1070,16 @@ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059 - MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059 - MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059 - MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059 - MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059 - MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059 - MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059 - MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059 - MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059 - MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059 + MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17069 + MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10071 + MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17069 + MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17069 + MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17069 + MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17069 + MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17069 + MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17069 + MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17069 + MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17069 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */ >; @@ -667,6 +1128,51 @@ >; }; + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059 + >; + }; + + pinctrl_usdhc4_1_100mhz: usdhc4grp-1-100mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc4_1_200mhz: usdhc4grp-1-200mhz { + fsl,pins = < + MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9 + MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9 + MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9 + MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9 + MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9 + MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9 + MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9 + MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9 + MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9 + MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0 @@ -674,3 +1180,14 @@ }; }; }; + +&vadc { + vadc_in = <0>; + csi_id = <1>; + status = "okay"; + port { + vadc_ep: endpoint { + remote-endpoint = <&csi2_ep>; + }; + }; +}; diff --git a/arch/arm/dts/imx6sx-softing-vining-2000.dts b/arch/arm/dts/imx6sx-softing-vining-2000.dts index 78dd5755a37..e050f29a50a 100644 --- a/arch/arm/dts/imx6sx-softing-vining-2000.dts +++ b/arch/arm/dts/imx6sx-softing-vining-2000.dts @@ -270,7 +270,7 @@ status = "okay"; }; -®_pcie { +®_pcie_phy { regulator-always-on; }; diff --git a/arch/arm/dts/imx6sx.dtsi b/arch/arm/dts/imx6sx.dtsi index 531a52c1e98..0b5d25d6446 100644 --- a/arch/arm/dts/imx6sx.dtsi +++ b/arch/arm/dts/imx6sx.dtsi @@ -1,6 +1,11 @@ -// SPDX-License-Identifier: GPL-2.0 -// -// Copyright 2014 Freescale Semiconductor, Inc. +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ #include #include @@ -15,8 +20,10 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. + * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; + memory { device_type = "memory"; reg = <0 0>; }; aliases { can0 = &flexcan1; @@ -44,13 +51,22 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; - spi3 = &ecspi4; - spi4 = &ecspi5; + spi0 = &qspi1; + spi1 = &qspi2; + spi2 = &ecspi1; + spi3 = &ecspi2; + spi4 = &ecspi3; + spi5 = &ecspi4; + spi6 = &ecspi5; usbphy0 = &usbphy1; usbphy1 = &usbphy2; + lcdif0 = &lcdif1; + lcdif1 = &lcdif2; + usb0 = &usbotg1; + usb1 = &usbotg2; + pci0 = &pcie; + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; }; cpus { @@ -82,14 +98,41 @@ <&clks IMX6SX_CLK_PLL2_PFD2>, <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_PLL1_SW>, - <&clks IMX6SX_CLK_PLL1_SYS>; + <&clks IMX6SX_CLK_PLL1_SYS>, + <&clks IMX6SX_CLK_PLL1>, + <&clks IMX6SX_PLL1_BYPASS>, + <&clks IMX6SX_PLL1_BYPASS_SRC>; clock-names = "arm", "pll2_pfd2_396m", "step", - "pll1_sw", "pll1_sys"; + "pll1_sw", "pll1_sys", "pll1", + "pll1_bypass", "pll1_bypass_src"; arm-supply = <®_arm>; soc-supply = <®_soc>; }; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + interrupt-parent = <&intc>; + }; + ckil: clock-ckil { compatible = "fixed-clock"; #clock-cells = <0>; @@ -160,28 +203,67 @@ interrupt-parent = <&gpc>; ranges; - ocram_s: sram@8f8000 { - compatible = "mmio-sram"; + busfreq { + compatible = "fsl,imx_busfreq"; + clocks = <&clks IMX6SX_CLK_PLL2_BUS>, <&clks IMX6SX_CLK_PLL2_PFD2>, + <&clks IMX6SX_CLK_PLL2_198M>, <&clks IMX6SX_CLK_ARM>, + <&clks IMX6SX_CLK_PLL3_USB_OTG>, <&clks IMX6SX_CLK_PERIPH>, + <&clks IMX6SX_CLK_PERIPH_PRE>, <&clks IMX6SX_CLK_PERIPH_CLK2>, + <&clks IMX6SX_CLK_PERIPH_CLK2_SEL>, <&clks IMX6SX_CLK_OSC>, + <&clks IMX6SX_CLK_PLL1_SYS>, <&clks IMX6SX_CLK_PERIPH2>, + <&clks IMX6SX_CLK_AHB>, <&clks IMX6SX_CLK_OCRAM_PODF>, + <&clks IMX6SX_CLK_PLL1_SW>, <&clks IMX6SX_CLK_PERIPH2_PRE>, + <&clks IMX6SX_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SX_CLK_PERIPH2_CLK2>, + <&clks IMX6SX_CLK_STEP>, <&clks IMX6SX_CLK_MMDC_PODF>, + <&clks IMX6SX_CLK_M4>; + clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", + "pll3_usb_otg", "periph", "periph_pre", "periph_clk2", + "periph_clk2_sel", "osc", "pll1_sys", "periph2", + "ahb", "ocram", "pll1_sw", "periph2_pre", + "periph2_clk2_sel", "periph2_clk2", "step", "mmdc", + "m4"; + fsl,max_ddr_freq = <400000000>; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = ; + }; + + ocrams: sram@008f8000 { + compatible = "fsl,lpm-sram"; reg = <0x008f8000 0x4000>; clocks = <&clks IMX6SX_CLK_OCRAM_S>; }; - ocram: sram@900000 { + ocrams_ddr: sram@00900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00900000 0x1000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram: sram@00901000 { compatible = "mmio-sram"; + reg = <0x00901000 0x1F000>; + clocks = <&clks IMX6SX_CLK_OCRAM>; + }; + + ocram_mf: sram-mf@00900000 { + compatible = "fsl,mega-fast-sram"; reg = <0x00900000 0x20000>; clocks = <&clks IMX6SX_CLK_OCRAM>; }; - intc: interrupt-controller@a01000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, - <0x00a00100 0x100>; - interrupt-parent = <&intc>; + ocram_optee { + compatible = "fsl,optee-lpm-sram"; + reg = <0x008f8000 0x4000>; + overw_reg = <&ocrams_ddr 0x00904000 0x1000>, + <&ocram 0x00905000 0x1b000>, + <&ocrams 0x00900000 0x4000>; + overw_clock = <&ocrams &clks IMX6SX_CLK_OCRAM>; }; - L2: l2-cache@a02000 { + L2: l2-cache@00a02000 { compatible = "arm,pl310-cache"; reg = <0x00a02000 0x1000>; interrupts = ; @@ -215,7 +297,38 @@ clocks = <&clks IMX6SX_CLK_APBH_DMA>; }; - gpmi: gpmi-nand@1806000{ + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x8000>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <0 20 0x04>; + secvio_src = <0x8000001d>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + gpu3d: gpu3d@01800000 { + compatible = "fsl,imx6sx-gpu", "fsl,imx6q-gpu"; + reg = <0x01800000 0x4000>, <0x80000000 0x0>, + <0x0 0x8000000>; + reg-names = "iobase_3d", "phys_baseaddr", "contiguous_mem"; + interrupts = ; + interrupt-names = "irq_3d"; + clocks = <&clks IMX6SX_CLK_GPU_AXI_PODF>, <&clks IMX6SX_CLK_GPU>, + <&clks 0>; + clock-names = "gpu3d_axi_clk", "gpu3d_clk", + "gpu3d_shader_clk"; + resets = <&src 0>; + reset-names = "gpu3d"; + power-domains = <&pd_pu>; + }; + + gpmi: gpmi-nand@01806000{ compatible = "fsl,imx6sx-gpmi-nand"; #address-cells = <1>; #size-cells = <1>; @@ -280,6 +393,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI1>, <&clks IMX6SX_CLK_ECSPI1>; clock-names = "ipg", "per"; + dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -292,6 +407,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI2>, <&clks IMX6SX_CLK_ECSPI2>; clock-names = "ipg", "per"; + dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -304,6 +421,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI3>, <&clks IMX6SX_CLK_ECSPI3>; clock-names = "ipg", "per"; + dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -316,6 +435,8 @@ clocks = <&clks IMX6SX_CLK_ECSPI4>, <&clks IMX6SX_CLK_ECSPI4>; clock-names = "ipg", "per"; + dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -333,6 +454,7 @@ }; esai: esai@2024000 { + compatible = "fsl,imx35-esai"; reg = <0x02024000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_ESAI_IPG>, @@ -342,6 +464,9 @@ <&clks IMX6SX_CLK_SPBA>; clock-names = "core", "mem", "extal", "fsys", "spba"; + dmas = <&sdma 23 21 0>, + <&sdma 24 21 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -353,7 +478,7 @@ clocks = <&clks IMX6SX_CLK_SSI1_IPG>, <&clks IMX6SX_CLK_SSI1>; clock-names = "ipg", "baud"; - dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; + dmas = <&sdma 37 26 0>, <&sdma 38 26 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -367,7 +492,7 @@ clocks = <&clks IMX6SX_CLK_SSI2_IPG>, <&clks IMX6SX_CLK_SSI2>; clock-names = "ipg", "baud"; - dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; + dmas = <&sdma 41 26 0>, <&sdma 42 26 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; @@ -381,25 +506,34 @@ clocks = <&clks IMX6SX_CLK_SSI3_IPG>, <&clks IMX6SX_CLK_SSI3>; clock-names = "ipg", "baud"; - dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; + dmas = <&sdma 45 26 0>, <&sdma 46 26 0>; dma-names = "rx", "tx"; fsl,fifo-depth = <15>; status = "disabled"; }; asrc: asrc@2034000 { + compatible = "fsl,imx53-asrc"; reg = <0x02034000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_ASRC_MEM>, - <&clks IMX6SX_CLK_ASRC_IPG>, - <&clks IMX6SX_CLK_SPDIF>, - <&clks IMX6SX_CLK_SPBA>; - clock-names = "mem", "ipg", "asrck", "spba"; - dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, - <&sdma 19 20 1>, <&sdma 20 20 1>, - <&sdma 21 20 1>, <&sdma 22 20 1>; + clocks = <&clks IMX6SX_CLK_ASRC_IPG>, + <&clks IMX6SX_CLK_ASRC_MEM>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPDIF>, <&clks 0>, <&clks 0>, + <&clks IMX6SX_CLK_SPBA>; + clock-names = "mem", "ipg", "asrck_0", + "asrck_1", "asrck_2", "asrck_3", "asrck_4", + "asrck_5", "asrck_6", "asrck_7", "asrck_8", + "asrck_9", "asrck_a", "asrck_b", "asrck_c", + "asrck_d", "asrck_e", "asrck_f", "spba"; + dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, + <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; + fsl,asrc-rate = <48000>; + fsl,asrc-width = <16>; status = "okay"; }; }; @@ -451,7 +585,7 @@ clocks = <&clks IMX6SX_CLK_CAN1_IPG>, <&clks IMX6SX_CLK_CAN1_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 1 0x10 17>; + stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -462,7 +596,7 @@ clocks = <&clks IMX6SX_CLK_CAN2_IPG>, <&clks IMX6SX_CLK_CAN2_SERIAL>; clock-names = "ipg", "per"; - fsl,stop-mode = <&gpr 0x10 2 0x10 18>; + stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; @@ -559,6 +693,12 @@ gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; }; + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + kpp: kpp@20b8000 { compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; reg = <0x020b8000 0x4000>; @@ -615,12 +755,11 @@ anatop-enable-bit = <0>; }; - reg_vdd3p0: regulator-3p0 { + reg_3p0: regulator-3p0@120 { compatible = "fsl,anatop-regulator"; regulator-name = "vdd3p0"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; - regulator-always-on; + regulator-min-microvolt = <2625000>; + regulator-max-microvolt = <3400000>; anatop-reg-offset = <0x120>; anatop-vol-bit-shift = <8>; anatop-vol-bit-width = <5>; @@ -662,9 +801,9 @@ anatop-max-voltage = <1450000>; }; - reg_pcie: regulator-vddpcie { + reg_pcie_phy: regulator-vddpcie-phy@140 { compatible = "fsl,anatop-regulator"; - regulator-name = "vddpcie"; + regulator-name = "vddpcie-phy"; regulator-min-microvolt = <725000>; regulator-max-microvolt = <1450000>; anatop-reg-offset = <0x140>; @@ -701,6 +840,7 @@ reg = <0x020c9000 0x1000>; interrupts = ; clocks = <&clks IMX6SX_CLK_USBPHY1>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; @@ -709,9 +849,21 @@ reg = <0x020ca000 0x1000>; interrupts = ; clocks = <&clks IMX6SX_CLK_USBPHY2>; + phy-3p0-supply = <®_3p0>; fsl,anatop = <&anatop>; }; + usbphy_nop1: usbphy_nop1 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX6SX_CLK_USBPHY1>; + clock-names = "main_clk"; + }; + + caam_snvs: caam-snvs@20cc000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x020cc000 0x4000>; + }; + snvs: snvs@20cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>; @@ -727,8 +879,8 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - value = <0x60>; - mask = <0x60>; + value = <0x61>; + mask = <0x61>; status = "disabled"; }; @@ -767,8 +919,10 @@ #interrupt-cells = <3>; interrupts = ; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x7c00000 0x3d00 0x0 0x400240>; clocks = <&clks IMX6SX_CLK_IPG>; clock-names = "ipg"; + pcie-phy-supply = <®_pcie_phy>; pgc { #address-cells = <1>; @@ -797,12 +951,6 @@ <&clks IMX6SX_CLK_CSI>, <&clks IMX6SX_CLK_VADC>; }; - - pd_pci: power-domain@3 { - reg = <3>; - #power-domain-cells = <0>; - power-supply = <®_pcie>; - }; }; }; @@ -817,8 +965,32 @@ reg = <0x020e4000 0x4000>; }; + ldb: ldb@20e0014 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6sx-ldb", "fsl,imx53-ldb"; + gpr = <&gpr>; + status = "disabled"; + clocks = <&clks IMX6SX_CLK_LDB_DI0>, + <&clks IMX6SX_CLK_LCDIF1_SEL>, + <&clks IMX6SX_CLK_LCDIF2_SEL>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_3_5>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_7>, + <&clks IMX6SX_CLK_LDB_DI0_DIV_SEL>; + clock-names = "ldb_di0", + "di0_sel", + "di1_sel", + "ldb_di0_div_3_5", + "ldb_di0_div_7", + "ldb_di0_div_sel"; + lvds-channel@0 { + reg = <0>; + status = "disabled"; + }; + }; + sdma: sdma@20ec000 { - compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; + compatible = "fsl,imx6sx-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>, @@ -841,15 +1013,23 @@ compatible = "fsl,sec-v4.0"; #address-cells = <1>; #size-cells = <1>; - reg = <0x2100000 0x10000>; - ranges = <0 0x2100000 0x10000>; - interrupt-parent = <&intc>; + reg = <0x2100000 0x40000>; + ranges = <0 0x2100000 0x40000>; clocks = <&clks IMX6SX_CLK_CAAM_MEM>, <&clks IMX6SX_CLK_CAAM_ACLK>, <&clks IMX6SX_CLK_CAAM_IPG>, <&clks IMX6SX_CLK_EIM_SLOW>; clock-names = "mem", "aclk", "ipg", "emi_slow"; + sec_ctrl: ctrl@0 { + /* CAAM Page 0 only accessible */ + /* by secure world */ + compatible = "fsl,sec-v4.0-ctrl"; + reg = <0x2100000 0x1000>; + secure-status = "okay"; + status = "disabled"; + }; + sec_jr0: jr0@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; @@ -863,6 +1043,20 @@ }; }; + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + usbotg1: usb@2184000 { compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; @@ -926,17 +1120,22 @@ <&clks IMX6SX_CLK_ENET_PTP>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; - fsl,num-tx-queues = <3>; - fsl,num-rx-queues = <3>; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <0>; status = "disabled"; }; - mlb: mlb@218c000 { + mlb: mlb@0218c000 { + compatible = "fsl,imx6sx-mlb50"; reg = <0x0218c000 0x4000>; interrupts = , , ; clocks = <&clks IMX6SX_CLK_MLB>; + clock-names = "mlb"; + iram = <&ocram>; status = "disabled"; }; @@ -1037,6 +1236,10 @@ <&clks IMX6SX_CLK_ENET_PTP>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; + stop-mode = <&gpr 0x10 4>; + fsl,wakeup_irq = <0>; status = "disabled"; }; @@ -1067,16 +1270,23 @@ }; }; + romcp@21ac000 { + compatible = "fsl,imx6sx-romcp", "syscon"; + reg = <0x021ac000 0x4000>; + }; + sai1: sai@21d4000 { compatible = "fsl,imx6sx-sai"; reg = <0x021d4000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SAI1_IPG>, + <&clks IMX6SX_CLK_DUMMY>, <&clks IMX6SX_CLK_SAI1>, <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; + dma-source = <&gpr 0 15 0 16>; status = "disabled"; }; @@ -1091,9 +1301,10 @@ reg = <0x021dc000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_SAI2_IPG>, + <&clks IMX6SX_CLK_DUMMY>, <&clks IMX6SX_CLK_SAI2>, <&clks 0>, <&clks 0>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dma-names = "rx", "tx"; dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; status = "disabled"; @@ -1125,6 +1336,12 @@ status = "disabled"; }; + qspi_m4: qspi-m4 { + compatible = "fsl,imx6sx-qspi-m4-restore"; + reg = <0x021e4000 0x4000>; + status = "disabled"; + }; + uart2: serial@21e8000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; @@ -1186,6 +1403,11 @@ clocks = <&clks IMX6SX_CLK_I2C4>; status = "disabled"; }; + + qosc: qosc@021fc000 { + compatible = "fsl,imx6sx-qosc"; + reg = <0x021fc000 0x4000>; + }; }; aips3: aips-bus@2200000 { @@ -1203,32 +1425,57 @@ ranges; csi1: csi@2214000 { + compatible = "fsl,imx6s-csi"; reg = <0x02214000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, <&clks IMX6SX_CLK_CSI>, <&clks IMX6SX_CLK_DCIC1>; - clock-names = "disp-axi", "csi_mclk", "dcic"; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + dcic1: dcic@0220c000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x0220c000 0x4000>; + interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC1>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; + status = "disabled"; + }; + + dcic2: dcic@02210000 { + compatible = "fsl,imx6sx-dcic"; + reg = <0x02210000 0x4000>; + interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SX_CLK_DCIC2>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "dcic", "disp-axi"; + gpr = <&gpr>; status = "disabled"; }; pxp: pxp@2218000 { - compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; + compatible = "fsl,imx6sx-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma"; reg = <0x02218000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_PXP_AXI>; - clock-names = "axi"; + clocks = <&clks IMX6SX_CLK_PXP_AXI>, + <&clks IMX6SX_CLK_DISPLAY_AXI>; + clock-names = "pxp-axi", "disp-axi"; power-domains = <&pd_disp>; status = "disabled"; }; csi2: csi@221c000 { + compatible = "fsl,imx6s-csi"; reg = <0x0221c000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, <&clks IMX6SX_CLK_CSI>, <&clks IMX6SX_CLK_DCIC2>; - clock-names = "disp-axi", "csi_mclk", "dcic"; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; status = "disabled"; }; @@ -1257,12 +1504,14 @@ }; vadc: vadc@2228000 { + compatible = "fsl,imx6sx-vadc"; reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; reg-names = "vadc-vafe", "vadc-vdec"; clocks = <&clks IMX6SX_CLK_VADC>, <&clks IMX6SX_CLK_CSI>; clock-names = "vadc", "csi"; power-domains = <&pd_disp>; + gpr = <&gpr>; status = "disabled"; }; }; @@ -1272,6 +1521,7 @@ reg = <0x02280000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; + num-channels = <4>; clock-names = "adc"; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; @@ -1283,6 +1533,7 @@ reg = <0x02284000 0x4000>; interrupts = ; clocks = <&clks IMX6SX_CLK_IPG>; + num-channels = <4>; clock-names = "adc"; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; @@ -1309,6 +1560,25 @@ status = "disabled"; }; + sema4: sema4@02290000 { /* sema4 */ + compatible = "fsl,imx6sx-sema4"; + reg = <0x02290000 0x4000>; + interrupts = <0 116 0x04>; + status = "okay"; + }; + + mu: mu@02294000 { /* mu */ + compatible = "fsl,imx6sx-mu"; + reg = <0x02294000 0x4000>; + interrupts = <0 90 0x04>; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx6sx-rpmsg"; + status = "disabled"; + }; + uart6: serial@22a0000 { compatible = "fsl,imx6sx-uart", "fsl,imx6q-uart", "fsl,imx21-uart"; @@ -1365,30 +1635,35 @@ pcie: pcie@8ffc000 { compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; - reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; + reg = <0x08ffc000 0x4000>, <0x08f00000 0x80000>; reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + ranges = < + /* downstream I/O */ + 0x81000000 0 0 0x08f80000 0 0x00010000 + /* non-prefetchable memory */ + 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_PCIE_AXI>, <&clks IMX6SX_CLK_LVDS1_OUT>, <&clks IMX6SX_CLK_PCIE_REF_125M>, <&clks IMX6SX_CLK_DISPLAY_AXI>; clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; - power-domains = <&pd_disp>, <&pd_pci>; - power-domain-names = "pcie", "pcie_phy"; + pcie-phy-supply = <®_pcie_phy>; + power-domains = <&pd_disp>; + fsl,max-link-speed = <2>; + gpr = <&gpr>; status = "disabled"; }; }; diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts b/arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts new file mode 100644 index 00000000000..336f0a4e0ca --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-ddr3-val-emmc.dts @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-val.dts" + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1_8bit>; + pinctrl-1 = <&pinctrl_usdhc1_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_8bit_200mhz>; + bus-width = <8>; + cd-gpios = <>; + wp-gpios = <>; + vmmc-supply = <>; + tuning-step = <2>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts b/arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts new file mode 100644 index 00000000000..fd5b550c9a0 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-ddr3-val-gpmi-weim.dts @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ul-14x14-ddr3-val.dts" + +/* + * solve pin conflict with NAND + * + * USDHC2_CD, SD2_RST_B, USDHC2_WP conflict with RAWNAND CE pins , also + * overwritten the conflict of SD2_RST_B with RAWNAND ALE in hog + * QSPI CLK, CE and DATA pins conflict with RAWNAND data pins and CE, CLE, RB, + * WP, DQS pin + * + */ +&iomuxc { + pinctrl-0 = <&pinctrl_hog>; +}; + +&qspi{ + status = "disabled"; +}; + +&gpmi{ + status = "okay"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-ddr3-val.dts b/arch/arm/dts/imx6ul-14x14-ddr3-val.dts new file mode 100644 index 00000000000..ded6a55496c --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-ddr3-val.dts @@ -0,0 +1,775 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "i.MX6 UltraLite DDR3 VAL Board"; + compatible = "fsl,imx6ul-14x14-ddr3-val", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + u-boot,off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + u-boot,off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_can2_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "okay"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "mii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog1 &pinctrl_hog_sd>; + + imx6ul-ddr3-val { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x17059 /* SD2 CD */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x17059 /* SD2 WP */ + >; + }; + + pinctrl_hog1: hoggrp1 { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESECT */ + >; + }; + + pinctrl_hog_sd: hoggrp_sd { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_bt: btgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a8 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0b0 + MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088 + MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0 + MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0 + MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 + MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x1f0b8 + MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x10059 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170b9 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100b9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x170f9 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x100f9 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 + &pinctrl_bt>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-evk-emmc.dts b/arch/arm/dts/imx6ul-14x14-evk-emmc.dts new file mode 100644 index 00000000000..bc4e53f2556 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk-emmc.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "imx6ul-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + diff --git a/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000..b7fe014619d --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-evk-gpmi-weim.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2015 Freescale Semiconductor, Inc. + +#include "imx6ul-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi index d0cbf79e33f..25e54b0582a 100644 --- a/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-14x14-evk-u-boot.dtsi @@ -25,33 +25,3 @@ &iomuxc { u-boot,dm-pre-reloc; }; - -&lcdif { - display = <&display0>; - u-boot,dm-pre-reloc; - - display0: display@0 { - bits-per-pixel = <24>; - bus-width = <24>; - - display-timings { - native-mode = <&timing0>; - - timing0: timing0 { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6ul-14x14-evk.dtsi b/arch/arm/dts/imx6ul-14x14-evk.dtsi index 463d7ca124b..0789ca6ed6a 100644 --- a/arch/arm/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/dts/imx6ul-14x14-evk.dtsi @@ -16,21 +16,13 @@ reg = <0x80000000 0x20000000>; }; - backlight_display: backlight-display { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; - status = "okay"; - }; - - reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -47,6 +39,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; status = "okay"; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; gpio-sck = <&gpio5 11 0>; gpio-mosi = <&gpio5 10 0>; cs-gpios = <&gpio5 7 0>; @@ -60,20 +53,10 @@ #gpio-cells = <2>; reg = <0>; registers-number = <1>; + registers-default = /bits/ 8 <0x57>; spi-max-frequency = <100000>; }; }; - - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight_display>; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; }; &clks { @@ -82,7 +65,7 @@ }; &i2c2 { - clock_frequency = <100000>; + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; @@ -160,16 +143,35 @@ }; &lcdif { - assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif_dat &pinctrl_lcdif_ctrl>; + + display = <&display0>; status = "okay"; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; }; }; }; @@ -188,10 +190,8 @@ flash0: n25q256a@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "micron,n25q256a"; + compatible = "micron,n25q256a", "jedec,spi-nor"; spi-max-frequency = <29000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; reg = <0>; }; }; @@ -235,6 +235,8 @@ &usbotg1 { dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; status = "okay"; }; @@ -476,10 +478,16 @@ >; }; + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 @@ -524,6 +532,51 @@ >; }; + pinctrl_usdhc2_8bit: usdhc2grp_8bit { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 diff --git a/arch/arm/dts/imx6ul-14x14-lpddr2-val.dts b/arch/arm/dts/imx6ul-14x14-lpddr2-val.dts new file mode 100644 index 00000000000..695cb107468 --- /dev/null +++ b/arch/arm/dts/imx6ul-14x14-lpddr2-val.dts @@ -0,0 +1,779 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ul.dtsi" + +/ { + model = "i.MX6 UltraLite 14X14 LPDDR2 VAL Board"; + compatible = "fsl,imx6ul-14x14-lpddr2-val", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x14000000>; + linux,cma-default; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 11 GPIO_ACTIVE_HIGH>; + u-boot,off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 22 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2_1 &pinctrl_ecspi2_cs_1>; + status = "disabled"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&cpu0 { + /* + * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "disabled"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + keep-power-in-suspend; + vmmc-supply = <®_sd2_vmmc>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog &pinctrl_hog_nand>; + + imx6ul-14x14-lpddr2-val { + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x17059 /* SD1 CD */ + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x17059 /* SD1 WP */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x17059 /* SD2 VSELECT */ + >; + }; + + pinctrl_hog_nand: hoggrp_nand { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x17059 /* SD1 RESET */ + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ + >; + }; + + pinctrl_ecspi2_cs_1: ecspi2_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 + >; + }; + + pinctrl_ecspi2_1: ecspi2grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x10b0 + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 + MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x1b0b0 + MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x4b01b0a8 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x1b0b0 + MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x4b01b0a8 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x1b0b0 + MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x1b0b0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b0a8 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp{ + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x11088 + MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x1b0b0 + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x1b0b0 + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x110b0 + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x1f0b8 + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_SD1_CLK__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2_8bit_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi b/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi index 77cb461a215..4a8311dd378 100644 --- a/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi +++ b/arch/arm/dts/imx6ul-9x9-evk-u-boot.dtsi @@ -3,8 +3,29 @@ * Copyright 2018 NXP */ +&{/aliases} { + u-boot,dm-pre-reloc; + display0 = &lcdif; +}; + &qspi { flash0: n25q256a@0 { compatible = "jedec,spi-nor"; }; -}; \ No newline at end of file +}; + +&{/soc} { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&lcdif { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6ul-9x9-evk.dts b/arch/arm/dts/imx6ul-9x9-evk.dts index 2270451121b..55b85e02a6e 100644 --- a/arch/arm/dts/imx6ul-9x9-evk.dts +++ b/arch/arm/dts/imx6ul-9x9-evk.dts @@ -9,7 +9,7 @@ #include "imx6ul.dtsi" / { - model = "Freescale i.MX6 UltraLite 9x9 EVK Board"; + model = "i.MX6 UltraLite 9x9 EVK Board"; compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul"; aliases { @@ -56,7 +56,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; - off-on-delay = <20000>; + off-on-delay-us = <20000>; enable-active-high; }; }; @@ -126,7 +126,7 @@ sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; status = "okay"; - pmic: pfuze3000@08 { + pmic: pfuze3000@8 { compatible = "fsl,pfuze3000"; reg = <0x08>; @@ -217,7 +217,7 @@ }; }; - mag3110@0e { + mag3110@e { compatible = "fsl,mag3110"; reg = <0x0e>; position = <2>; @@ -318,6 +318,46 @@ >; }; + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + /* used for lcd reset */ + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + pinctrl_qspi: qspigrp { fsl,pins = < MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 @@ -404,6 +444,41 @@ }; }; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + &qspi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi>; diff --git a/arch/arm/dts/imx6ul.dtsi b/arch/arm/dts/imx6ul.dtsi index 5644b0f34d5..81c78ff2298 100644 --- a/arch/arm/dts/imx6ul.dtsi +++ b/arch/arm/dts/imx6ul.dtsi @@ -52,6 +52,8 @@ usbphy1 = &usbphy2; usb0 = &usbotg1; usb1 = &usbotg2; + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; }; cpus { @@ -800,6 +802,20 @@ }; }; + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + usbotg1: usb@2184000 { compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x02184000 0x200>; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-emmc.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-emmc.dts new file mode 100644 index 00000000000..966ce614f96 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-emmc.dts @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-val.dts" + +&usdhc1 { + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <>; + wp-gpios = <>; + vmmc-supply = <>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-epdc.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-epdc.dts new file mode 100644 index 00000000000..5d521dafaff --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-epdc.dts @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-val.dts" + +&epdc { + status = "okay"; +}; + +&fec2 { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; + +&max17135 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-gpmi-weim.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-gpmi-weim.dts new file mode 100644 index 00000000000..3c6cdf00171 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-gpmi-weim.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-val.dts" + +&gpmi { + status ="okay"; +}; + +&qspi { + status ="disabled"; +}; + +&usdhc2{ + status ="disabled"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-lcdif.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-lcdif.dts new file mode 100644 index 00000000000..cb7f1d9cbcd --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-lcdif.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* DTS file for LCDIF at imx6ull ddr3 val board */ + +#include "imx6ull-14x14-ddr3-val.dts" + +/ { + backlight { + status = "okay"; + }; +}; + +&fec1 { + status = "disabled"; +}; + +&lcdif { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val-tsc.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val-tsc.dts new file mode 100644 index 00000000000..95084f5a780 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-val-tsc.dts @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx6ull-14x14-ddr3-val-lcdif.dts" + +&i2c1 { + status = "disabled"; +}; + +®_usb_otg1_vbus { + pinctrl-0 = < >; + gpio = < >; +}; + +&usbotg1 { + status = "disabled"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + status = "okay"; + xnur-gpio = <&gpio1 3 0>; + measure_delay_time = <0xfff>; + pre_charge_time = <0xffff>; +}; diff --git a/arch/arm/dts/imx6ull-14x14-ddr3-val.dts b/arch/arm/dts/imx6ull-14x14-ddr3-val.dts new file mode 100644 index 00000000000..dde366f1bd2 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-ddr3-val.dts @@ -0,0 +1,1008 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "i.MX6 ULL DDR3 VAL Board"; + compatible = "fsl,imx6ull-ddr3-val", "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x40000000>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "disabled"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD1_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + u-boot,off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "SD2_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 10 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + + reg_can2_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 15 GPIO_ACTIVE_LOW>; + }; + + reg_vref_3v3: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vref-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg1_vbus: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; +}; + +&clks { + /* For bringup, comments this. + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; + */ +}; + +&cpu0 { + /* + * on i.MX6ULL, no seperated VDD_ARM_IN and VDD_SOC_IN, + * to align with other platform and use the same cpufreq + * driver, still use the seperated OPP define for arm + * and soc. + */ + operating-points = < + /* kHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; + fsl,arm-soc-shared = <1>; +}; + +®_arm { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +®_soc { + vin-supply = <&sw1a_reg>; + regulator-allow-bypass; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + flash: n25q032@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,n25q032", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "mii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + }; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0xf>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <1>; /* use ldo-bypass, u-boot will check it and configure */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze200"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3a { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw3b_reg: sw3b { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "disabled"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio3 16 0>; + gpio_pmic_vcom_ctrl = <&gpio3 24 0>; + gpio_pmic_wakeup = <&gpio3 14 0>; + gpio_pmic_v3p3 = <&gpio3 17 0>; + gpio_pmic_intr = <&gpio3 13 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; +}; + +&iomuxc { + imx6ull-ddr3-val { + pinctrl_adc1: adc1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0xb0 + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + >; + }; + + + pinctrl_csi1: csi1grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 + MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 + MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 + MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 + MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 + MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 + MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 + MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 + MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 + MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 + MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 + MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x10b0 + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x10b0 + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x10b0 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b0a0 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b098 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0a0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0a0 + MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x1b0a0 + MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x1b0a0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x4001b0a8 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x1b0b0 + MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x4001b0a8 + MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x1b0b0 + MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x1b0b0 + >; + }; + + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6ULL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x10b1 + MX6ULL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x10b1 + MX6ULL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x10b1 + MX6ULL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x10b1 + MX6ULL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x10b1 + MX6ULL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x10b1 + MX6ULL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x10b1 + MX6ULL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x10b1 + MX6ULL_PAD_LCD_CLK__EPDC_SDCLK 0x10b1 + MX6ULL_PAD_LCD_ENABLE__EPDC_SDLE 0x10b1 + MX6ULL_PAD_LCD_HSYNC__EPDC_SDOE 0x10b1 + MX6ULL_PAD_LCD_VSYNC__EPDC_SDCE0 0x10b1 + MX6ULL_PAD_LCD_DATA00__EPDC_SDDO00 0x10b1 + MX6ULL_PAD_LCD_DATA01__EPDC_SDDO01 0x10b1 + MX6ULL_PAD_LCD_DATA02__EPDC_SDDO02 0x10b1 + MX6ULL_PAD_LCD_DATA03__EPDC_SDDO03 0x10b1 + MX6ULL_PAD_LCD_DATA04__EPDC_SDDO04 0x10b1 + MX6ULL_PAD_LCD_DATA05__EPDC_SDDO05 0x10b1 + MX6ULL_PAD_LCD_DATA06__EPDC_SDDO06 0x10b1 + MX6ULL_PAD_LCD_DATA07__EPDC_SDDO07 0x10b1 + MX6ULL_PAD_LCD_DATA14__EPDC_SDSHR 0x10b1 + MX6ULL_PAD_LCD_DATA15__EPDC_GDRL 0x10b1 + MX6ULL_PAD_LCD_DATA16__EPDC_GDCLK 0x10b1 + MX6ULL_PAD_LCD_DATA17__EPDC_GDSP 0x10b1 + MX6ULL_PAD_LCD_RESET__EPDC_GDOE 0x10b1 + >; + }; + + pinctrl_esai: esaigrp { + fsl,pins = < + MX6ULL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x1b0b0 + MX6ULL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x1b0b0 + MX6ULL_PAD_CSI_DATA04__ESAI_TX_FS 0x1b0b0 + MX6ULL_PAD_CSI_DATA05__ESAI_TX_CLK 0x1b0b0 + MX6ULL_PAD_CSI_DATA07__ESAI_T0 0x1b0b0 + MX6ULL_PAD_CSI_HSYNC__ESAI_TX1 0x1b0b0 + MX6ULL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x1b0b0 + MX6ULL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x1b0b0 + MX6ULL_PAD_CSI_DATA02__ESAI_RX_FS 0x1b0b0 + MX6ULL_PAD_CSI_DATA03__ESAI_RX_CLK 0x1b0b0 + MX6ULL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x1b0b0 + MX6ULL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp{ + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x17059 /* STBY */ + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x4001b8b1 + MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x1b8b1 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001b8b0 + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c4_gpio: i2c4grp_gpio { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x1b8b0 + MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x1b8b0 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x80000000 /* pwrgood */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x80000000 /* vcom_ctrl */ + MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x80000000 /* wakeup */ + MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x80000000 /* v3p3 */ + MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x80000000 /* pwr int */ + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x11088 + MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x11088 + >; + }; + + pinctrl_pwm1: pmw1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 +#ifdef REWORKED_ENABLE_ALL_QSPI + MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x70a1 + MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x70a1 + MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x70a1 + MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x70a1 + MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x70a1 + MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x70a1 + MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x70a1 + MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x70a1 +#endif + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x1b0b0 + MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x1b0b0 + MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x110b0 + MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x110b0 + MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x1b0b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x1b0b0 + MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x1b0b0 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_uart2dte: uart2dtegrp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usb_otg1: usbotg1grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x10b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_8bit: usdhc1_8bit_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_8bit_100mhz: usdhc1_8bit_100mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170b9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170b9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170b9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_8bit_200mhz: usdhc1_8bit_200mhz_grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x170f9 + MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x170f9 + MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x170f9 + MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x170f9 + >; + }; + + pinctrl_usdhc1_cd_wp: usdhc1_cd_wp_grp { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x17059 /* SD1 WP */ + >; + }; + + pinctrl_usdhc1_rst: usdhc1_rst_grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_usdhc1_vselect: usdhc1_vselect_grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100a9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170a9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170a9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170a9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170a9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2_rst: usdhc2_rst_grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x17059 /* SD2 RESET */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + imx6ull-ddr3-val { + pinctrl_bt: btgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x80000000 + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x80000000 + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x80000000 + >; + }; + + pinctrl_sai2_hp_det_b: sai2_hp_det_grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x17059 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "disabled"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "disabled"; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; +#ifdef REWORKED_ENABLE_ALL_QSPI + fsl,qspi-has-second-chip = <1>; +#endif + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + +#ifdef REWORKED_ENABLE_ALL_QSPI + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +#endif +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2 + &pinctrl_bt>; + fsl,uart-has-rtscts; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart2dte>; */ + status = "disabled"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_cd_wp>, <&pinctrl_usdhc1_rst>, <&pinctrl_usdhc1_vselect>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_rst>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_rst>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_rst>; + non-removable; + no-1-8-v; /* VSELECT not connected by default */ + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/dts/imx6ull-14x14-evk-emmc.dts b/arch/arm/dts/imx6ull-14x14-evk-emmc.dts new file mode 100644 index 00000000000..d6dc9121b74 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-evk-emmc.dts @@ -0,0 +1,21 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + */ + +#include "imx6ull-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + diff --git a/arch/arm/dts/imx6ull-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ull-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000..4391182e613 --- /dev/null +++ b/arch/arm/dts/imx6ull-14x14-evk-gpmi-weim.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2016 Freescale Semiconductor, Inc. + +#include "imx6ull-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ull-14x14-evk.dts b/arch/arm/dts/imx6ull-14x14-evk.dts index 74aaa8a56a3..1542335f9ab 100644 --- a/arch/arm/dts/imx6ull-14x14-evk.dts +++ b/arch/arm/dts/imx6ull-14x14-evk.dts @@ -6,9 +6,10 @@ #include "imx6ull.dtsi" #include "imx6ul-14x14-evk.dtsi" +#include "imx6ul-14x14-evk-u-boot.dtsi" / { - model = "Freescale i.MX6 UltraLiteLite 14x14 EVK Board"; + model = "i.MX6 ULL 14x14 EVK Board"; compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; }; diff --git a/arch/arm/dts/imx6ull-9x9-evk-u-boot.dtsi b/arch/arm/dts/imx6ull-9x9-evk-u-boot.dtsi new file mode 100644 index 00000000000..4b692694402 --- /dev/null +++ b/arch/arm/dts/imx6ull-9x9-evk-u-boot.dtsi @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +&{/aliases} { + u-boot,dm-pre-reloc; + display0 = &lcdif; +}; + +&qspi { + flash0: n25q256a@0 { + compatible = "jedec,spi-nor"; + }; +}; + +&{/soc} { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&iomuxc_snvs { + u-boot,dm-pre-reloc; +}; + +&lcdif { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6ull-9x9-evk.dts b/arch/arm/dts/imx6ull-9x9-evk.dts new file mode 100644 index 00000000000..7fab500dad8 --- /dev/null +++ b/arch/arm/dts/imx6ull-9x9-evk.dts @@ -0,0 +1,561 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP + */ + +/dts-v1/; + +#include +#include "imx6ull.dtsi" + +/ { + model = "i.MX6 ULL 9x9 EVK Board"; + compatible = "fsl,imx6ull-9x9-evk", "fsl,imx6ull"; + + aliases { + spi5 = &soft_spi; + }; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_can_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "can-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; + }; + + reg_gpio_dvfs: regulator-gpio { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvfs>; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 1400000 0x0>; + }; + + reg_sd1_vmmc: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; + + soft_spi: soft-spi { + compatible = "spi-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi4>; + pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + status = "okay"; + gpio-sck = <&gpio5 11 0>; + gpio-mosi = <&gpio5 10 0>; + cs-gpios = <&gpio5 7 0>; + num-chipselects = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio_spi: gpio_spi@0 { + compatible = "fairchild,74hc595"; + gpio-controller; + #gpio-cells = <2>; + reg = <0>; + registers-number = <1>; + registers-default = /bits/ 8 <0x57>; + spi-max-frequency = <100000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + mag3110@e { + compatible = "fsl,mag3110"; + reg = <0x0e>; + position = <2>; + }; + + fxls8471@1e { + compatible = "fsl,fxls8471"; + reg = <0x1e>; + position = <0>; + interrupt-parent = <&gpio5>; + interrupts = <0 8>; + }; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + imx6ul-evk { + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ + MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; +}; + +&iomuxc_snvs { + pinctrl-names = "default_snvs"; + pinctrl-0 = <&pinctrl_hog_2>; + imx6ull-evk { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 + >; + }; + + pinctrl_dvfs: dvfsgrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; + + pinctrl_lcdif_reset: lcdifresetgrp { + fsl,pins = < + /* used for lcd reset */ + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 + >; + }; + + pinctrl_spi4: spi4grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl + &pinctrl_lcdif_reset>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + status = "okay"; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + enable-sdio-wakeup; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/dts/imx6ull.dtsi b/arch/arm/dts/imx6ull.dtsi index 22e4a307fa5..b900060bab4 100644 --- a/arch/arm/dts/imx6ull.dtsi +++ b/arch/arm/dts/imx6ull.dtsi @@ -36,10 +36,16 @@ &usdhc1 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; &usdhc2 { compatible = "fsl,imx6ull-usdhc", "fsl,imx6sx-usdhc"; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <132000000>; }; / { @@ -76,6 +82,18 @@ clock-names = "ipg", "per"; status = "disabled"; }; + + epdc: epdc@228c000 { + compatible = "fsl,imx7d-epdc"; + interrupts = ; + reg = <0x228c000 0x4000>; + clocks = <&clks IMX6ULL_CLK_EPDC_ACLK>, + <&clks IMX6ULL_CLK_EPDC_PIX>; + clock-names = "epdc_axi", "epdc_pix"; + /* Need to fix epdc-ram */ + /* epdc-ram = <&gpr 0x4 30>; */ + status = "disabled"; + }; }; }; }; diff --git a/arch/arm/dts/imx6ulz-14x14-evk-emmc.dts b/arch/arm/dts/imx6ulz-14x14-evk-emmc.dts new file mode 100644 index 00000000000..e477952759e --- /dev/null +++ b/arch/arm/dts/imx6ulz-14x14-evk-emmc.dts @@ -0,0 +1,25 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx6ulz-14x14-evk.dts" + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_8bit>; + pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ulz-14x14-evk-gpmi-weim.dts b/arch/arm/dts/imx6ulz-14x14-evk-gpmi-weim.dts new file mode 100644 index 00000000000..12635e83e34 --- /dev/null +++ b/arch/arm/dts/imx6ulz-14x14-evk-gpmi-weim.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright 2018 NXP + +#include "imx6ulz-14x14-evk.dts" + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; +}; + +&qspi { + status = "disabled"; +}; + +&usdhc2 { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx6ulz-14x14-evk.dts b/arch/arm/dts/imx6ulz-14x14-evk.dts index 483d9732c00..78e1db8e660 100644 --- a/arch/arm/dts/imx6ulz-14x14-evk.dts +++ b/arch/arm/dts/imx6ulz-14x14-evk.dts @@ -15,7 +15,7 @@ /delete-node/ &tsc; / { - model = "Freescale i.MX6 ULZ 14x14 EVK Board"; + model = "i.MX6 ULZ 14x14 EVK Board"; compatible = "fsl,imx6ulz-14x14-evk", "fsl,imx6ull", "fsl,imx6ulz"; /delete-node/ panel; diff --git a/arch/arm/dts/imx7d-12x12-ddr3-val.dts b/arch/arm/dts/imx7d-12x12-ddr3-val.dts new file mode 100644 index 00000000000..7081183acff --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-ddr3-val.dts @@ -0,0 +1,578 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "i.MX7 DDR3 12x12 VAL Board"; + compatible = "fsl,imx7d-12x12-ddr3-val", "fsl,imx7d"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio6 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_can1_3v3: can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <4>; + cs-gpios = <&gpio5 3 0>, <&gpio5 4 0>, <&gpio5 5 0>, <&gpio5 6 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4_1 &pinctrl_ecspi4_cs_1>; + status = "disabled"; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epxp { + status = "okay"; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-12x12-ddr3-val { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + >; + }; + + pinctrl_ecspi4_cs_1: ecspi4_cs_grp-1 { + fsl,pins = < + MX7D_PAD_SD1_CLK__GPIO5_IO3 0x2 + MX7D_PAD_SD1_CMD__GPIO5_IO4 0x2 + MX7D_PAD_SD1_DATA0__GPIO5_IO5 0x2 + MX7D_PAD_SD1_DATA1__GPIO5_IO6 0x2 + >; + }; + + pinctrl_ecspi4_1: ecspi4grp-1 { + fsl,pins = < + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK 0x2 + MX7D_PAD_SD1_WP__ECSPI4_MOSI 0x2 + MX7D_PAD_SD1_CD_B__ECSPI4_MISO 0x2 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_SD3_DATA5__FLEXCAN1_TX 0x59 + MX7D_PAD_SD3_DATA7__FLEXCAN1_RX 0x59 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_SD3_DATA6__FLEXCAN2_TX 0x59 + MX7D_PAD_SD3_DATA4__FLEXCAN2_RX 0x59 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA12__GPIO3_IO17 0x32 + MX7D_PAD_LCD_DATA13__GPIO3_IO18 0x32 + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD0__I2C3_SCL 0x4000007f + MX7D_PAD_ENET1_RGMII_RD1__I2C3_SDA 0x4000007f + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x7f + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x7f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__LCD_DATA0 0x4001b0b0 + MX7D_PAD_EPDC_DATA01__LCD_DATA1 0x4001b0b0 + MX7D_PAD_EPDC_DATA02__LCD_DATA2 0x4001b0b0 + MX7D_PAD_EPDC_DATA03__LCD_DATA3 0x4001b0b0 + MX7D_PAD_EPDC_DATA04__LCD_DATA4 0x4001b0b0 + MX7D_PAD_EPDC_DATA05__LCD_DATA5 0x4001b0b0 + MX7D_PAD_EPDC_DATA06__LCD_DATA6 0x4001b0b0 + MX7D_PAD_EPDC_DATA07__LCD_DATA7 0x4001b0b0 + MX7D_PAD_EPDC_DATA08__LCD_DATA8 0x4001b0b0 + MX7D_PAD_EPDC_DATA09__LCD_DATA9 0x4001b0b0 + MX7D_PAD_EPDC_DATA10__LCD_DATA10 0x4001b0b0 + MX7D_PAD_EPDC_DATA11__LCD_DATA11 0x4001b0b0 + MX7D_PAD_EPDC_DATA12__LCD_DATA12 0x4001b0b0 + MX7D_PAD_EPDC_DATA13__LCD_DATA13 0x4001b0b0 + MX7D_PAD_EPDC_DATA14__LCD_DATA14 0x4001b0b0 + MX7D_PAD_EPDC_DATA15__LCD_DATA15 0x4001b0b0 + MX7D_PAD_EPDC_SDLE__LCD_DATA16 0x4001b0b0 + MX7D_PAD_EPDC_SDOE__LCD_DATA17 0x4001b0b0 + MX7D_PAD_EPDC_SDSHR__LCD_DATA18 0x4001b0b0 + MX7D_PAD_EPDC_SDCE0__LCD_DATA19 0x4001b0b0 + MX7D_PAD_EPDC_SDCE1__LCD_DATA20 0x4001b0b0 + MX7D_PAD_EPDC_SDCE2__LCD_DATA21 0x4001b0b0 + MX7D_PAD_EPDC_SDCE3__LCD_DATA22 0x4001b0b0 + MX7D_PAD_EPDC_GDCLK__LCD_DATA23 0x4001b0b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_EPDC_SDCLK__LCD_CLK 0x4001b0b0 + MX7D_PAD_EPDC_BDR1__LCD_ENABLE 0x4001b0b0 + MX7D_PAD_EPDC_PWR_STAT__LCD_VSYNC 0x4001b0b0 + MX7D_PAD_EPDC_PWR_COM__LCD_HSYNC 0x4001b0b0 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x59 + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x59 + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x59 + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x59 + >; + }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5a + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5a + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5a + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x5a + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 0x5b + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 0x5b + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 0x5b + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 0x5b + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-12x12-ddr3-val { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 /* flexcan stby1 */ + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 /* flexcan stby2 */ + MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x80000000 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__I2C1_SCL 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x7f + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__I2C2_SCL 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO07__I2C2_SDA 0x4000007f + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&sdma { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC2_ROOT_CLK>; + assigned-clocks-rates = <400000000>; + bus-width = <8>; + tuning-step = <2>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + vmmc-supply = <®_sd3_vmmc>; + cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + no-1-8-v; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-val-ecspi.dts b/arch/arm/dts/imx7d-12x12-lpddr3-val-ecspi.dts new file mode 100644 index 00000000000..29abc2c86b3 --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-val-ecspi.dts @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-val.dts" + +&epdc { + status = "disabled"; +}; + +&ecspi1{ + status = "okay"; +}; + +/* + * pin conflict with ecspi1 + * default hog setting conflicts with ECSPI1 MOSI and MISO + * EPDC PWRCTRL conflicts with ECSPI1 CS pin + */ +&iomuxc { + pinctrl-0 = <&pinctrl_hog_1>; + pinctrl-1 = <&pinctrl_hog_1>; +}; diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-val-qspi.dts b/arch/arm/dts/imx7d-12x12-lpddr3-val-qspi.dts new file mode 100644 index 00000000000..5ceccd2ba0d --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-val-qspi.dts @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-12x12-lpddr3-val.dts" + +/* disable epdc, conflict with qspi */ +&epdc { + status = "disabled"; +}; + +&iomuxc { + qspi1 { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51 + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51 + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51 + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51 + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51 + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51 + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51 + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51 + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51 + >; + }; + }; +}; + +&qspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_qspi1_1>; + pinctrl-1 = <&pinctrl_qspi1_1>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q256a@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q256a@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q256a@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q256a@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q256a", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; diff --git a/arch/arm/dts/imx7d-12x12-lpddr3-val.dts b/arch/arm/dts/imx7d-12x12-lpddr3-val.dts new file mode 100644 index 00000000000..4b6257c57c7 --- /dev/null +++ b/arch/arm/dts/imx7d-12x12-lpddr3-val.dts @@ -0,0 +1,1047 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7d.dtsi" + +/ { + model = "i.MX7 LPDDR3 12x12 VAL Board"; + compatible = "fsl,imx7d-12x12-lpddr3-val", "fsl,imx7d"; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_gpio_keys>; + pinctrl-1 = <&pinctrl_gpio_keys_sleep>; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can1_3v3: can1-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + + reg_can2_3v3: can2-3v3 { + compatible = "regulator-fixed"; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 11 GPIO_ACTIVE_LOW>; + }; + + reg_coedc_5v: coedc_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd1_vmmc: sd1_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_mipi_dsi_pwr_on: mipi_dsi_pwr_on { + compatible = "regulator-fixed"; + regulator-name = "mipi_dsi_pwr_on"; + gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&epdc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_epdc_0>; + pinctrl-1 = <&pinctrl_epdc_0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + pinctrl-1 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "disabled"; + + spi_flash1: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p32", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + + vddio1: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-1 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-txid"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "disabled"; +}; + +&flexcan1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-1 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_3v3>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-1 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_3v3>; + status = "disabled"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1>; + pinctrl-2 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + fsl,lpsr-mode; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "sleep", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1>; + pinctrl-2 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + }; + + max17135@48 { + compatible = "maxim,max17135"; + reg = <0x48>; + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio4 23 0>; + gpio_pmic_v3p3 = <&gpio4 20 0>; + gpio_pmic_intr = <&gpio4 18 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; + + codec: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_1v8>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_coedc_5v>; + SPKVDD2-supply = <®_coedc_5v>; + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&iomuxc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + pinctrl-1 = <&pinctrl_hog_1 &pinctrl_hog_sd2_vselect &pinctrl_hog_mipi>; + + imx7d-12x12-lpddr3-val { + + pinctrl_bt: btgrp-1 { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x80000000 /* BT REG on */ + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_epdc_0: epdcgrp-0 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 0x2 + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 0x2 + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 0x2 + MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x80000000 /* pwr int */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59 + MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59 + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x59 /* STBY */ + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59 + MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59 + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x59 /* STBY */ + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpio_keys_sleep: gpio_keysgrp_sleep { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x14 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x14 + >; + }; + + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x80000000 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x80000000 + MX7D_PAD_ECSPI2_MISO__GPIO4_IO22 0x80000000 + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x80000000 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_hog_mipi: hoggrp_mipi { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59 + MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17 0x59 + >; + }; + + pinctrl_hog_sd2_vselect: hoggrp_sd2vselect { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x59 + >; + }; + + pinctrl_hog_headphone_det: hoggrp_headphone_det { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_mqs: mqsgrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_SYNC__MQS_RIGHT 0x0 + MX7D_PAD_SAI1_RX_BCLK__MQS_LEFT 0x0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19 0x2 + MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21 0x2 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x1f + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_1_100mhz: usdhc2grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_1_200mhz: usdhc2grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_1_100mhz: usdhc3grp-1_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_1_200mhz: usdhc3grp-1_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_SAI1_TX_SYNC__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_SAI1_RX_SYNC__SIM1_PORT1_PD 0x77 + MX7D_PAD_SAI1_TX_DATA__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_SAI1_TX_BCLK__SIM1_PORT1_CLK 0x73 + MX7D_PAD_SAI1_RX_DATA__SIM1_PORT1_TRXD 0x73 + >; + }; + + }; +}; + +&iomuxc_lpsr { + imx7d-12x12-lpddr3-val { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 + >; + }; + + pinctrl_usbotg1_vbus: usbotg1vbusgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_usbotg2_vbus: usbotg2vbusgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + pinctrl-1 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ocrams { + fsl,enable-lpsr; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio6 21 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio6 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sim1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_sim1_1>; + pinctrl-1 = <&pinctrl_sim1_1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart1_1>; + pinctrl-1 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_uart3_1 + &pinctrl_bt>; + pinctrl-1 = <&pinctrl_uart3_1 + &pinctrl_bt>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_1>; + pinctrl-1 = <&pinctrl_usdhc1_1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_1>; + pinctrl-1 = <&pinctrl_usdhc2_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc2_1>; + cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc3_1>; + pinctrl-1 = <&pinctrl_usdhc3_1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_1>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; diff --git a/arch/arm/dts/imx7d-19x19-ddr3-val.dts b/arch/arm/dts/imx7d-19x19-ddr3-val.dts new file mode 100644 index 00000000000..47cfaa0ddb2 --- /dev/null +++ b/arch/arm/dts/imx7d-19x19-ddr3-val.dts @@ -0,0 +1,882 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "i.MX7 DDR3L 19x19 VAL Board"; + compatible = "fsl,imx7d-19x19-ddr3-val", "fsl,imx7d"; + + max7322_reset: max7322-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + reset-delay-us = <1>; + #reset-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + /* gpios disconnected see resistors R601, R583 */ + status = "disabled"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_lcd_reset: lcd-reset { + compatible = "regulator-fixed"; + regulator-name = "lcd-reset"; + gpio = <&gpio3 4 0>; + enable-active-high; + }; + + reg_sd2_vmmc: sd2_vmmc{ + compatible = "regulator-fixed"; + regulator-name = "VCC_SD2"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_sd3_vmmc: sd3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio6 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_coedc_5v: coedc_5v { + compatible = "regulator-fixed"; + regulator-name = "CODEC_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud_3v3: aud_3v3 { + compatible = "regulator-fixed"; + regulator-name = "AUD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_aud_1v8: aud_1v8 { + compatible = "regulator-fixed"; + regulator-name = "AUD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&gpio6 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio4 19 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_cs_1>; + status = "okay"; + + flash: at45@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&epxp { + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy1>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-assert-gpios = <&max7322 0 GPIO_ACTIVE_HIGH>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3_1>; + pinctrl-1 = <&pinctrl_i2c3_1_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; + + max7322: gpio@68 { + compatible = "maxim,max7322"; + reg = <0x68>; + gpio-controller; + #gpio-cells = <2>; + resets = <&max7322_reset>; + }; + codec: wm8958@1a { + compatible = "wlf,wm8958"; + reg = <0x1a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "mclk1", "mclk2"; + + DBVDD1-supply = <®_aud_1v8>; + DBVDD2-supply = <®_aud_1v8>; + DBVDD3-supply = <®_aud_3v3>; + AVDD2-supply = <®_aud_1v8>; + CPVDD-supply = <®_aud_1v8>; + SPKVDD1-supply = <®_coedc_5v>; + SPKVDD2-supply = <®_coedc_5v>; + + wlf,ldo1ena; + wlf,ldo2ena; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_sd3_vselect>; + + imx7d-19x19-ddr3-val { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__SD2_VSELECT 0x59 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x59 + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + MX7D_PAD_SD3_STROBE__GPIO6_IO10 0x59 + + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x7F + MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x7F + >; + }; + + pinctrl_hog_sd3_vselect: hoggrp_sd3vselect { + fsl,pins = < + MX7D_PAD_GPIO1_IO13__SD3_VSELECT 0x59 + >; + }; + + pinctrl_csi: csigrp-1 { + fsl,pins = < + MX7D_PAD_LCD_DATA04__CSI_VSYNC 0x0F + MX7D_PAD_LCD_DATA05__CSI_HSYNC 0x0F + MX7D_PAD_LCD_DATA06__CSI_PIXCLK 0x0F + MX7D_PAD_LCD_DATA07__CSI_MCLK 0x0F + MX7D_PAD_LCD_DATA08__CSI_DATA9 0x0F + MX7D_PAD_LCD_DATA09__CSI_DATA8 0x0F + MX7D_PAD_LCD_DATA10__CSI_DATA7 0x0F + MX7D_PAD_LCD_DATA11__CSI_DATA6 0x0F + MX7D_PAD_LCD_DATA12__CSI_DATA5 0x0F + MX7D_PAD_LCD_DATA13__CSI_DATA4 0x0F + MX7D_PAD_LCD_DATA14__CSI_DATA3 0x0F + MX7D_PAD_LCD_DATA15__CSI_DATA2 0x0F + MX7D_PAD_LCD_DATA02__GPIO3_IO7 0x0F + MX7D_PAD_LCD_DATA03__GPIO3_IO8 0x0F + >; + }; + + pinctrl_ecspi1_cs_1: ecspi1_cs_grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x2 + >; + }; + + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_1_gpio: i2c3grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f + >; + }; + + pinctrl_i2c4_1: i2c4grp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 + MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 + MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 + MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 + MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 + MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 + MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 + MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 + MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 + MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 + MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 + MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 + MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 + MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 + MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 + MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 + MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 + MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 + MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 + MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 + MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 + MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 + MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 + MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX7D_PAD_LCD_CLK__LCD_CLK 0x79 + MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 + MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 + MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_RX_SYNC__SAI1_RX_SYNC 0x1f + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0 + MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 0x59 + MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 0x59 + MX7D_PAD_ECSPI2_MISO__SD1_DATA6 0x59 + MX7D_PAD_ECSPI2_SS0__SD1_DATA7 0x59 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x59 + MX7D_PAD_SD2_CLK__SD2_CLK 0x19 + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5a + MX7D_PAD_SD2_CLK__SD2_CLK 0x1a + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { + fsl,pins = < + MX7D_PAD_SD2_CMD__SD2_CMD 0x5b + MX7D_PAD_SD2_CLK__SD2_CLK 0x1b + MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b + MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b + MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b + MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + >; + }; + + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x51 + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 0x51 + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 0x51 + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 0x51 + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 0x51 + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS 0x51 + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK 0x51 + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B 0x51 + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B 0x51 + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-19x19-ddr3-val { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x80000000 + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x80000000 + >; + }; + + pinctrl_mipi_csi: mipicsigrp-1 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__ANATOP_24M_OUT 0x3 + >; + }; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "disabled"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + status = "disabled"; +}; + +&sdma { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + pinctrl-0 = <&pinctrl_uart3dte_1>; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + cd-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + tuning-step = <2>; + vmmc-supply = <®_sd2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + keep-power-in-suspend; + enable-sdio-wakeup; + tuning-step = <2>; + vmmc-supply = <®_sd3_vmmc>; + status = "okay"; +}; + +&qspi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_qspi1_1>; + pinctrl-1 = <&pinctrl_qspi1_1>; + status = "okay"; + fsl,qspi-has-second-chip = <1>; + ddrsmp=<0>; + + flash0: n25q512ax3@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q512ax3", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <0>; + }; + + flash1: n25q512ax3@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q512ax3", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <1>; + }; + + flash2: n25q512ax3@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q512ax3", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <2>; + }; + + flash3: n25q512ax3@3 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q512ax3", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + reg = <3>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx7d-19x19-lpddr2-val.dts b/arch/arm/dts/imx7d-19x19-lpddr2-val.dts new file mode 100644 index 00000000000..2475ad46b91 --- /dev/null +++ b/arch/arm/dts/imx7d-19x19-lpddr2-val.dts @@ -0,0 +1,395 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "i.MX7D LPDDR2 19x19 VAL Board"; + compatible = "fsl,imx7d-19x19-lpddr2-val", "fsl,imx7d"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-19x19-lpddr3-val { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-19x19-lpddr3-val { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + }; +}; + +&sdma { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + pinctrl-0 = <&pinctrl_uart3dte_1>; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7d-19x19-lpddr3-val.dts b/arch/arm/dts/imx7d-19x19-lpddr3-val.dts new file mode 100644 index 00000000000..eda09a592fd --- /dev/null +++ b/arch/arm/dts/imx7d-19x19-lpddr3-val.dts @@ -0,0 +1,402 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include +#include "imx7d.dtsi" + +/ { + model = "i.MX7 LPDDR3 19x19 VAL Board"; + compatible = "fsl,imx7d-19x19-lpddr3-val", "fsl,imx7d"; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + volume-up { + label = "Volume Up"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + volume-down { + label = "Volume Down"; + gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_sd1_vmmc: sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC_SD1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + memory { + reg = <0x80000000 0x80000000>; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&sw1a_reg>; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1_1>; + pinctrl-1 = <&pinctrl_i2c1_1_gpio>; + scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze3000@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2_1>; + pinctrl-1 = <&pinctrl_i2c2_1_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7d-19x19-lpddr3-val { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x59 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x59 + >; + }; + + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 0x32 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 0x32 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_1_gpio: i2c1grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_1_gpio: i2c2grp-1-gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DTE_CTS 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DTE_RTS 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + }; +}; + +&iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2>; + + imx7d-19x19-lpddr3-val { + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 + >; + }; + }; +}; + +&sdma { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + fsl,uart-has-rtscts; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode;*/ + pinctrl-0 = <&pinctrl_uart3dte_1>; +}; + +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + no-1-8-v; + keep-power-in-suspend; + enable-sdio-wakeup; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7d-pinfunc.h b/arch/arm/dts/imx7d-pinfunc.h index f2493bc63da..aa9dbead4b8 100644 --- a/arch/arm/dts/imx7d-pinfunc.h +++ b/arch/arm/dts/imx7d-pinfunc.h @@ -592,7 +592,7 @@ #define MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0130 0x03A0 0x06FC 0x0 0x2 #define MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0130 0x03A0 0x0000 0x0 0x0 #define MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x0130 0x03A0 0x05DC 0x1 0x0 -#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x0000 0x2 0x0 +#define MX7D_PAD_UART2_RX_DATA__SAI3_RX_BCLK 0x0130 0x03A0 0x06C4 0x2 0x0 #define MX7D_PAD_UART2_RX_DATA__ECSPI1_SS3 0x0130 0x03A0 0x0000 0x3 0x0 #define MX7D_PAD_UART2_RX_DATA__ENET2_1588_EVENT1_IN 0x0130 0x03A0 0x0000 0x4 0x0 #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x0130 0x03A0 0x0000 0x5 0x0 @@ -1112,13 +1112,13 @@ #define MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x0250 0x04C0 0x0000 0x5 0x0 #define MX7D_PAD_ENET1_RGMII_TD3__CAAM_RNG_OSC_OBS 0x0250 0x04C0 0x0000 0x7 0x0 #define MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x0254 0x04C4 0x0000 0x0 0x0 -#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TX_CTL__SAI1_RX_SYNC 0x0254 0x04C4 0x06A4 0x2 0x1 #define MX7D_PAD_ENET1_RGMII_TX_CTL__GPT2_COMPARE1 0x0254 0x04C4 0x0000 0x3 0x0 #define MX7D_PAD_ENET1_RGMII_TX_CTL__EPDC_PWR_CTRL2 0x0254 0x04C4 0x0000 0x4 0x0 #define MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0254 0x04C4 0x0000 0x5 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x0258 0x04C8 0x0000 0x0 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__ENET1_TX_ER 0x0258 0x04C8 0x0000 0x1 0x0 -#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x0000 0x2 0x0 +#define MX7D_PAD_ENET1_RGMII_TXC__SAI1_RX_BCLK 0x0258 0x04C8 0x069C 0x2 0x1 #define MX7D_PAD_ENET1_RGMII_TXC__GPT2_COMPARE2 0x0258 0x04C8 0x0000 0x3 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__EPDC_PWR_CTRL3 0x0258 0x04C8 0x0000 0x4 0x0 #define MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x0258 0x04C8 0x0000 0x5 0x0 diff --git a/arch/arm/dts/imx7d-sdb-epdc.dts b/arch/arm/dts/imx7d-sdb-epdc.dts new file mode 100644 index 00000000000..8183a254142 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-epdc.dts @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + */ + +#include "imx7d-sdb.dts" + +&epdc { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&fec2 { + status = "disabled"; +}; + +®_can2_3v3 { + status = "disabled"; +}; + +®_fec2_3v3 { + status = "disabled"; +}; + +&flexcan2 { + status = "disabled"; +}; + +&max17135 { + status = "okay"; +}; + +&sii902x { + status = "disabled"; +}; + +&sim1 { + status = "disabled"; +}; + +&uart5 { + status = "disabled"; +}; + +&i2c3 { + elan@10 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc_elan_touch>; + compatible = "elan,elan-touch"; + reg = <0x10>; + interrupt-parent = <&gpio6>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + gpio_elan_cs = <&gpio6 13 0>; + gpio_elan_rst = <&gpio6 15 0>; + gpio_intr = <&gpio6 12 0>; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/imx7d-sdb-gpmi-weim.dts b/arch/arm/dts/imx7d-sdb-gpmi-weim.dts new file mode 100644 index 00000000000..cba5f52f3a7 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-gpmi-weim.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ + +#include "imx7d-sdb.dts" + +&gpmi{ + status = "okay"; +}; + +&sai1{ + status = "disabled"; +}; + +&usdhc3{ + status = "disabled"; +}; + +&uart5{ + status = "disabled"; +}; diff --git a/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi deleted file mode 100644 index 585af6d211f..00000000000 --- a/arch/arm/dts/imx7d-sdb-qspi-u-boot.dtsi +++ /dev/null @@ -1,10 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2018 NXP - */ - -&qspi1 { - flash0: mx25l51245g@0 { - compatible = "jedec,spi-nor"; - }; -}; diff --git a/arch/arm/dts/imx7d-sdb-qspi.dts b/arch/arm/dts/imx7d-sdb-qspi.dts index 9bb4c743c14..e88564fc902 100644 --- a/arch/arm/dts/imx7d-sdb-qspi.dts +++ b/arch/arm/dts/imx7d-sdb-qspi.dts @@ -12,17 +12,15 @@ }; &iomuxc { - qspi1 { - pinctrl_qspi1_1: qspi1grp_1 { - fsl,pins = < - MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 - MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 - MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 - MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 - MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 - MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 - >; - }; + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51 + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51 + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51 + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51 + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51 + >; }; }; @@ -35,10 +33,8 @@ flash0: mx25l51245g@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "macronix,mx25l51245g"; + compatible = "jedec,spi-nor"; spi-max-frequency = <29000000>; - /* take off one dummy cycle */ - spi-nor,ddr-quad-read-dummy = <5>; reg = <0>; }; }; diff --git a/arch/arm/dts/imx7d-sdb-reva.dts b/arch/arm/dts/imx7d-sdb-reva.dts new file mode 100644 index 00000000000..df06df09647 --- /dev/null +++ b/arch/arm/dts/imx7d-sdb-reva.dts @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7d-sdb.dts" + +/ { + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg_reva>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + }; +}; + +&fec2 { + /delete-property/phy-supply; +}; + +&iomuxc { + imx7d-sdb { + pinctrl_tsc2046_pendown: tsc2046_pendown { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ + >; + }; + + pinctrl_usb_otg2_vbus_reg_reva: usbotg2vbusregrevagrp { + fsl,pins = < + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 + >; + }; + }; +}; diff --git a/arch/arm/dts/imx7d-sdb-u-boot.dtsi b/arch/arm/dts/imx7d-sdb-u-boot.dtsi deleted file mode 100644 index b78358fa139..00000000000 --- a/arch/arm/dts/imx7d-sdb-u-boot.dtsi +++ /dev/null @@ -1,7 +0,0 @@ -&fec2 { - status = "disable"; -}; - -&usbotg1 { - dr_mode = "peripheral"; -}; diff --git a/arch/arm/dts/imx7d-sdb.dts b/arch/arm/dts/imx7d-sdb.dts index 8191ac7c334..2b15ce2709e 100644 --- a/arch/arm/dts/imx7d-sdb.dts +++ b/arch/arm/dts/imx7d-sdb.dts @@ -8,9 +8,14 @@ #include "imx7d.dtsi" / { - model = "Freescale i.MX7 SabreSD Board"; + model = "i.MX7 SabreSD Board"; compatible = "fsl,imx7d-sdb", "fsl,imx7d"; + aliases { + spi5 = &soft_spi; + gpio7 = &extended_io; + }; + chosen { stdout-path = &uart1; }; @@ -20,6 +25,13 @@ reg = <0x80000000 0x80000000>; }; + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + #reset-cells = <0>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -40,13 +52,13 @@ }; }; - spi4 { + soft_spi: soft-spi { compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi4>; - gpio-sck = <&gpio1 13 GPIO_ACTIVE_LOW>; - gpio-mosi = <&gpio1 9 GPIO_ACTIVE_LOW>; - cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; num-chipselects = <1>; #address-cells = <1>; #size-cells = <0>; @@ -57,6 +69,7 @@ #gpio-cells = <2>; reg = <0>; registers-number = <1>; + registers-default = /bits/ 8 <0x74>; /* Enable PERI_3V3, SENSOR_RST_B and HDMI_RST*/ spi-max-frequency = <100000>; }; }; @@ -88,16 +101,15 @@ regulator-max-microvolt = <1800000>; }; - reg_brcm: regulator-brcm { + reg_sd1_vmmc: regulator-sd1-vmmc { compatible = "regulator-fixed"; - gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-name = "brcm_reg"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "VDD_SD1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; startup-delay-us = <200000>; + off-on-delay-us = <20000>; + enable-active-high; }; reg_lcd_3v3: regulator-lcd-3v3 { @@ -136,16 +148,48 @@ status = "okay"; }; - panel { - compatible = "innolux,at043tn24"; - backlight = <&backlight>; - power-supply = <®_lcd_3v3>; + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; + sound { + compatible = "fsl,imx7d-evk-wm8960", "fsl,imx-audio-wm8960"; + model = "wm8960-audio"; + cpu-dai = <&sai1>; + audio-codec = <&codec>; + codec-master; + /* JD2: hp detect high for headphone*/ + hp-det = <2 0>; + hp-det-gpios = <&gpio2 28 0>; + audio-routing = + "Headphone Jack", "HP_L", + "Headphone Jack", "HP_R", + "Ext Spk", "SPK_LP", + "Ext Spk", "SPK_LN", + "Ext Spk", "SPK_RP", + "Ext Spk", "SPK_RN", + "LINPUT1", "Main MIC", + "Main MIC", "MICB"; + assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>, + <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <12288000>; + }; + + sound-hdmi { + compatible = "fsl,imx7d-sdb-sii902x", + "fsl,imx-audio-sii902x"; + model = "sii902x-audio"; + cpu-dai = <&sai3>; + hdmi-controller = <&sii902x>; + }; + + usdhc2_pwrseq: usdhc2_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + reset-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; }; }; @@ -163,6 +207,23 @@ cpu-supply = <&sw1a_reg>; }; +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&csi1 { + csi-mux-mipi = <&gpr 0x14 4>; + fsl,mipi-mode; + status = "okay"; + + port { + csi_ep: endpoint { + remote-endpoint = <&csi_mipi_ep>; + }; + }; +}; + &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; @@ -188,13 +249,32 @@ }; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0 &pinctrl_enet2_reg>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + en-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&epxp { + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; - assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, - <&clks IMX7D_ENET1_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; phy-mode = "rgmii"; phy-handle = <ðphy0>; fsl,magic-packet; @@ -218,10 +298,15 @@ &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; - assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, - <&clks IMX7D_ENET2_TIME_ROOT_CLK>; - assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; - assigned-clock-rates = <0>, <100000000>; + assigned-clocks = <&clks IMX7D_ENET_PHY_REF_ROOT_SRC>, + <&clks IMX7D_ENET_AXI_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>, + <&clks IMX7D_ENET_AXI_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_25M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <0>, <0>, <100000000>, <250000000>; phy-mode = "rgmii"; phy-handle = <ðphy1>; phy-supply = <®_fec2_3v3>; @@ -236,6 +321,31 @@ status = "okay"; }; +&mipi_csi { + clock-frequency = <240000000>; + status = "okay"; + port { + mipi_sensor_ep: endpoint@1 { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <2>; + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + }; + + csi_mipi_ep: endpoint@2 { + remote-endpoint = <&csi_ep>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "disabled"; + nand-on-flash-bbt; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -333,10 +443,24 @@ }; &i2c2 { - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; status = "okay"; + fxas2100x@20 { + compatible = "fsl,fxas2100x"; + reg = <0x20>; + }; + + fxos8700@1e { + compatible = "fsl,fxos8700"; + reg = <0x1e>; + }; + mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; @@ -344,14 +468,104 @@ }; &i2c3 { - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; status = "okay"; + + sii902x: sii902x@39 { + compatible = "SiI,sii902x"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sii902x>; + interrupt-parent = <&gpio2>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + mode_str ="1280x720M@60"; + bits-per-pixel = <16>; + reg = <0x39>; + status = "okay"; + }; + + max17135: max17135@48 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max17135>; + compatible = "maxim,max17135"; + reg = <0x48>; + status = "disabled"; + + vneg_pwrup = <1>; + gvee_pwrup = <2>; + vpos_pwrup = <10>; + gvdd_pwrup = <12>; + gvdd_pwrdn = <1>; + vpos_pwrdn = <2>; + gvee_pwrdn = <8>; + vneg_pwrdn = <10>; + gpio_pmic_pwrgood = <&gpio2 31 0>; + gpio_pmic_vcom_ctrl = <&gpio4 14 0>; + gpio_pmic_wakeup = <&gpio2 23 0>; + gpio_pmic_v3p3 = <&gpio2 30 0>; + gpio_pmic_intr = <&gpio2 22 0>; + + regulators { + DISPLAY_reg: DISPLAY { + regulator-name = "DISPLAY"; + }; + + GVDD_reg: GVDD { + /* 20v */ + regulator-name = "GVDD"; + }; + + GVEE_reg: GVEE { + /* -22v */ + regulator-name = "GVEE"; + }; + + HVINN_reg: HVINN { + /* -22v */ + regulator-name = "HVINN"; + }; + + HVINP_reg: HVINP { + /* 20v */ + regulator-name = "HVINP"; + }; + + VCOM_reg: VCOM { + regulator-name = "VCOM"; + /* Real max value: -500000 */ + regulator-max-microvolt = <4325000>; + /* Real min value: -4325000 */ + regulator-min-microvolt = <500000>; + }; + + VNEG_reg: VNEG { + /* -15v */ + regulator-name = "VNEG"; + }; + + VPOS_reg: VPOS { + /* 15v */ + regulator-name = "VPOS"; + }; + + V3P3_reg: V3P3 { + regulator-name = "V3P3"; + }; + }; + }; }; &i2c4 { - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; status = "okay"; codec: wm8960@1a { @@ -361,20 +575,103 @@ clock-names = "mclk"; wlf,shared-lrclk; }; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; + clocks = <&clks IMX7D_CLK_DUMMY>; + clock-names = "csi_mclk"; + csi_id = <0>; + pwn-gpios = <&extended_io 6 GPIO_ACTIVE_HIGH>; + AVDD-supply = <&vgen6_reg>; + mclk = <24000000>; + mclk_source = <0>; + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_sensor_ep>; + }; + }; + }; }; &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcdif>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; status = "okay"; - port { - display_out: endpoint { - remote-endpoint = <&panel_in>; + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + + timing0: timing0 { + clock-frequency = <9200000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <8>; + hback-porch = <4>; + hsync-len = <41>; + vback-porch = <2>; + vfront-porch = <4>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; }; }; }; +&pcie { + reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +®_1p0d { + vin-supply = <&sw2_reg>; +}; + +®_1p2 { + vin-supply = <&sw2_reg>; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sim1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sim1_1>; + port = <0>; + sven_low_active; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + &snvs_pwrkey { status = "okay"; }; @@ -383,7 +680,18 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart5dte>; */ status = "okay"; }; @@ -393,6 +701,7 @@ assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; uart-has-rtscts; + resets = <&modem_reset>; status = "okay"; }; @@ -408,26 +717,35 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; - wakeup-source; - keep-power-in-suspend; + vmmc-supply = <®_sd1_vmmc>; status = "okay"; }; &usdhc2 { + #address-cells = <1>; + #size-cells = <0>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - wakeup-source; + pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz &pinctrl_wifi>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz &pinctrl_wifi>; keep-power-in-suspend; non-removable; - vmmc-supply = <®_brcm>; + mmc-pwrseq = <&usdhc2_pwrseq>; fsl,tuning-step = <2>; - status = "okay"; + pm-ignore-notify; + cap-power-off-card; + status = "disabled"; + + brcmf: bcrmf@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; }; &usdhc3 { @@ -438,8 +756,8 @@ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; assigned-clock-rates = <400000000>; bus-width = <8>; - fsl,tuning-step = <2>; non-removable; + auto-cmd23-broken; status = "okay"; }; @@ -460,6 +778,19 @@ >; }; + pinctrl_epdc_elan_touch: epdc_elan_touch_grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x59 + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13 0x80000000 + >; + }; + pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15 0x1b + >; + }; + pinctrl_ecspi3: ecspi3grp { fsl,pins = < MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 @@ -505,9 +836,34 @@ >; }; - pinctrl_enet2_reg: enet2reggrp { + pinctrl_epdc0: epdcgrp0 { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x14 + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 0x2 + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 0x2 + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 0x2 + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 0x2 + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 0x2 + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 0x2 + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 0x2 + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 0x2 + MX7D_PAD_EPDC_DATA08__EPDC_DATA8 0x2 + MX7D_PAD_EPDC_DATA09__EPDC_DATA9 0x2 + MX7D_PAD_EPDC_DATA10__EPDC_DATA10 0x2 + MX7D_PAD_EPDC_DATA11__EPDC_DATA11 0x2 + MX7D_PAD_EPDC_DATA12__EPDC_DATA12 0x2 + MX7D_PAD_EPDC_DATA13__EPDC_DATA13 0x2 + MX7D_PAD_EPDC_DATA14__EPDC_DATA14 0x2 + MX7D_PAD_EPDC_DATA15__EPDC_DATA15 0x2 + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK 0x2 + MX7D_PAD_EPDC_SDLE__EPDC_SDLE 0x2 + MX7D_PAD_EPDC_SDOE__EPDC_SDOE 0x2 + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR 0x2 + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 0x2 + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 0x2 + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK 0x2 + MX7D_PAD_EPDC_GDOE__EPDC_GDOE 0x2 + MX7D_PAD_EPDC_GDRL__EPDC_GDRL 0x2 + MX7D_PAD_EPDC_GDSP__EPDC_GDSP 0x2 >; }; @@ -531,6 +887,27 @@ >; }; + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX7D_PAD_SD3_CLK__NAND_CLE 0x71 + MX7D_PAD_SD3_CMD__NAND_ALE 0x71 + MX7D_PAD_SAI1_MCLK__NAND_WP_B 0x71 + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 + MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 + MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 + MX7D_PAD_SD3_DATA0__NAND_DATA00 0x71 + MX7D_PAD_SD3_DATA1__NAND_DATA01 0x71 + MX7D_PAD_SD3_DATA2__NAND_DATA02 0x71 + MX7D_PAD_SD3_DATA3__NAND_DATA03 0x71 + MX7D_PAD_SD3_DATA4__NAND_DATA04 0x71 + MX7D_PAD_SD3_DATA5__NAND_DATA05 0x71 + MX7D_PAD_SD3_DATA6__NAND_DATA06 0x71 + MX7D_PAD_SD3_DATA7__NAND_DATA07 0x71 + >; + }; + pinctrl_hog: hoggrp { fsl,pins = < MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ @@ -544,6 +921,13 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp_gpio { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x7f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x7f + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f @@ -551,6 +935,13 @@ >; }; + pinctrl_i2c2_gpio: i2c2grp_gpio { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x7f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x7f + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f @@ -558,6 +949,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3grp_gpio { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x7f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x7f + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f @@ -565,6 +963,13 @@ >; }; + pinctrl_i2c4_gpio: i2c4grp_gpio { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x7f + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x7f + >; + }; + pinctrl_lcdif: lcdifgrp { fsl,pins = < MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 @@ -595,7 +1000,44 @@ MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 - MX7D_PAD_LCD_RESET__LCD_RESET 0x79 + MX7D_PAD_LCD_RESET__GPIO3_IO4 0x80000000 + >; + }; + + pinctrl_max17135: max17135grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x80000000 /* pwrgood */ + MX7D_PAD_I2C4_SCL__GPIO4_IO14 0x80000000 /* vcom_ctrl */ + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 0x80000000 /* wakeup */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x80000000 /* v3p3 */ + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x80000000 /* pwr int */ + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f + MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 + MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0 0x1f + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 >; }; @@ -613,6 +1055,22 @@ >; }; + pinctrl_sii902x: hdmigrp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x59 + >; + }; + + pinctrl_sim1_1: sim1grp-1 { + fsl,pins = < + MX7D_PAD_EPDC_DATA10__SIM1_PORT1_RST_B 0x77 + MX7D_PAD_EPDC_DATA12__SIM1_PORT1_PD 0x77 + MX7D_PAD_EPDC_DATA11__SIM1_PORT1_SVEN 0x77 + MX7D_PAD_EPDC_DATA09__SIM1_PORT1_CLK 0x73 + MX7D_PAD_EPDC_DATA08__SIM1_PORT1_TRXD 0x73 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 @@ -624,8 +1082,13 @@ fsl,pins = < MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 - MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 - MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 + >; + }; + + pinctrl_uart5dte: uart5dtegrp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__UART5_DTE_RX 0x79 + MX7D_PAD_SAI1_RX_DATA__UART5_DTE_TX 0x79 >; }; @@ -638,6 +1101,15 @@ >; }; + pinctrl_usdhc1_gpio: usdhc1_gpiogrp { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */ + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 @@ -646,9 +1118,28 @@ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b >; }; @@ -733,6 +1224,12 @@ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b >; }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x19 /* WL_HOST_WAKE */ + >; + }; }; }; @@ -743,6 +1240,21 @@ }; &iomuxc_lpsr { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_2 &pinctrl_usb_otg2_vbus_reg>; + + pinctrl_hog_2: hoggrp-2 { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 + >; + }; + + pinctrl_enet2_reg: enet2reggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x80000000 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 @@ -760,4 +1272,11 @@ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14 >; }; + + pinctrl_sai3_mclk: sai3grp_mclk { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK 0x1f + >; + }; + }; diff --git a/arch/arm/dts/imx7d.dtsi b/arch/arm/dts/imx7d.dtsi index 75566c780a4..0b54fa23428 100644 --- a/arch/arm/dts/imx7d.dtsi +++ b/arch/arm/dts/imx7d.dtsi @@ -42,19 +42,27 @@ */ #include "imx7s.dtsi" +#include / { aliases { + spi0 = &qspi1; + spi1 = &ecspi1; + spi2 = &ecspi2; + spi3 = &ecspi3; + spi4 = &ecspi4; ethernet1 = &fec2; + usb1 = &usbotg2; + usbgadget1 = &usbg2; }; + cpus { cpu0: cpu@0 { - operating-points = < - /* KHz uV */ - 996000 1075000 - 792000 975000 - >; clock-frequency = <996000000>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; }; cpu1: cpu@1 { @@ -62,10 +70,103 @@ device_type = "cpu"; reg = <1>; clock-frequency = <996000000>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + + cpu0_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-792000000 { + opp-hz = /bits/ 64 <792000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0xf>, <0xf>; + }; + + opp-996000000 { + opp-hz = /bits/ 64 <996000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0xc>, <0xf>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1225000>; + clock-latency-ns = <150000>; + opp-supported-hw = <0x8>, <0xf>; }; }; + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX7D_USB_PHY2_CLK>; + clock-names = "main_clk"; + #phy-cells = <0>; + }; + soc { + busfreq { + compatible = "fsl,imx_busfreq"; + fsl,max_ddr_freq = <533000000>; + clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, + <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, + <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, + <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, + <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_DIV>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>; + clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", + "dram_alt_sel", "pll_dram", "dram_alt_root", "pfd2_270m", + "pfd1_332m", "ahb", "axi"; + interrupts = <0 112 0x04>, <0 113 0x04>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + }; + + ocrams_ddr: sram@900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x900000 0x1000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocram: sram@901000 { + compatible = "mmio-sram"; + reg = <0x901000 0x1f000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocrams: sram@180000 { + compatible = "fsl,lpm-sram"; + reg = <0x180000 0x8000>; + clocks = <&clks IMX7D_OCRAM_S_CLK>; + status = "disabled"; + }; + + ocram_optee { + compatible = "fsl,optee-lpm-sram"; + reg = <0x180000 0x8000>; + overw_reg = <&ocrams_ddr 0x904000 0x1000>, + <&ocram 0x905000 0x1b000>, + <&ocrams 0x900000 0x4000>; + overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>; + }; + + ocrams_mf: sram-mf@900000 { + compatible = "fsl,mega-fast-sram"; + reg = <0x900000 0x20000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + etm@3007d000 { compatible = "arm,coresight-etm3x", "arm,primecell"; reg = <0x3007d000 0x1000>; @@ -80,16 +181,59 @@ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; - port { - etm1_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port1>; + out-ports { + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; }; }; }; + + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + interrupts = ; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + reg = <0x31001000 0x1000>, + <0x31002000 0x2000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; + }; }; }; +/delete-node/&csi; +/delete-node/&video_mux; + &aips2 { + pcie_phy: pcie-phy@306d0000 { + compatible = "fsl,imx7d-pcie-phy"; + reg = <0x306d0000 0x10000>; + status = "disabled"; + }; + + system_counter_rd: system-counter-rd@306a0000 { + compatible = "fsl,imx7d-system-counter-rd"; + reg = <0x306a0000 0x10000>; + status = "disabled"; + }; + + system_counter_cmp: system-counter-cmp@306b0000 { + compatible = "fsl,imx7d-system-counter-cmp"; + reg = <0x306b0000 0x10000>; + status = "disabled"; + }; + + system_counter_ctrl: system-counter-ctrl@306c0000 { + compatible = "fsl,imx7d-system-counter-ctrl"; + reg = <0x306c0000 0x10000>; + interrupts = , + ; + status = "disabled"; + }; + epdc: epdc@306f0000 { compatible = "fsl,imx7d-epdc"; interrupts = ; @@ -97,11 +241,127 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_EPDC_PIXEL_ROOT_CLK>; clock-names = "epdc_axi", "epdc_pix"; epdc-ram = <&gpr 0x4 30>; + qos = <&qosc>; + status = "disabled"; + }; + + epxp: epxp@30700000 { + compatible = "fsl,imx7d-pxp-dma"; + interrupts = , + ; + reg = <0x30700000 0x10000>; + clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + csi1: csi1@30710000 { + compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7d-mipi-csi"; + reg = <0x30750000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_clk", "phy_clk"; + mipi-phy-supply = <®_1p0d>; + csis-phy-reset = <&src 0x28 2>; + bus-width = <4>; + status = "disabled"; + /delete-node/ port@0; + /delete-node/ port@1; + }; + + mipi_dsi: mipi-dsi@30760000 { + compatible = "fsl,imx7d-mipi-dsi"; + reg = <0x30760000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; + power-domains = <&pgc_mipi_phy>; status = "disabled"; }; + + qosc: qosc@307f0000 { + compatible = "fsl,imx7d-qosc", "syscon"; + reg = <0x307f0000 0x4000>; + }; }; &aips3 { + mu: mu@30aa0000 { + compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + #mbox-cells = <2>; + }; + + mu_lp: mu_lp@30aa0000 { + compatible = "fsl,imx7d-mu-lp", "fsl,imx6sx-mu-lp"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + status = "okay"; + }; + + sema4: sema4@30ac0000 { + compatible = "fsl,imx7d-sema4"; + reg = <0x30ac0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; + clock-names = "sema4"; + status = "okay"; + }; + + sim1: sim@30b90000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30b90000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SIM1_ROOT_CLK>; + clock-names = "sim"; + status = "disabled"; + }; + + qspi1: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-qspi"; + reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; + reg-names = "QuadSPI", "QuadSPI-memory"; + interrupts = ; + clocks = <&clks IMX7D_QSPI_ROOT_CLK>, + <&clks IMX7D_QSPI_ROOT_CLK>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + sim2: sim@30ba0000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30ba0000 0x10000>; + interrupts = ; + status = "disabled"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + usbotg2: usb@30b20000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b20000 0x200>; @@ -119,36 +379,92 @@ reg = <0x30b20200 0x200>; }; - usbphynop2: usbphynop2 { - compatible = "usb-nop-xceiv"; - clocks = <&clks IMX7D_USB_PHY2_CLK>; - clock-names = "main_clk"; - }; - fec2: ethernet@30bf0000 { compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; reg = <0x30bf0000 0x10000>; - interrupts = , + interrupt-names = "int0", "int1", "int2", "pps"; + interrupts = , + , , - ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + ; + clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET2_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; + status = "disabled"; + }; + + pcie: pcie@33800000 { + compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x4000>, + <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + /* + * Reference manual lists pci irqs incorrectly + * Real hardware ordering is same as imx6: D+MSI, C, B, A + */ + interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, + <&clks IMX7D_PCIE_PHY_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX7_RESET_PCIEPHY>, + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + status = "disabled"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7d-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; status = "disabled"; }; }; -&ca_funnel_ports { +&ca_funnel_in_ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { reg = <1>; ca_funnel_in_port1: endpoint { - slave-mode; remote-endpoint = <&etm1_out_port>; }; }; diff --git a/arch/arm/dts/imx7s.dtsi b/arch/arm/dts/imx7s.dtsi index 967023fde19..c32e7d1085b 100644 --- a/arch/arm/dts/imx7s.dtsi +++ b/arch/arm/dts/imx7s.dtsi @@ -46,6 +46,7 @@ #include #include #include +#include #include "imx7d-pinfunc.h" / { @@ -55,10 +56,8 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; - memory { device_type = "memory"; }; aliases { gpio0 = &gpio1; @@ -82,12 +81,14 @@ serial4 = &uart5; serial5 = &uart6; serial6 = &uart7; - spi0 = &qspi1; - spi1 = &ecspi1; - spi2 = &ecspi2; - spi3 = &ecspi3; - spi4 = &ecspi4; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; + spi3 = &ecspi4; ethernet0 = &fec1; + usb0 = &usbotg1; + usbgadget0 = &usbg1; + video0 = &lcdif; }; cpus { @@ -144,9 +145,9 @@ * non-configurable replicators don't show up on the * AMBA bus. As such no need to add "arm,primecell" */ - compatible = "arm,coresight-replicator"; + compatible = "arm,coresight-static-replicator"; - ports { + out-ports { #address-cells = <1>; #size-cells = <0>; /* replicator output ports */ @@ -163,25 +164,26 @@ remote-endpoint = <&etr_in_port>; }; }; + }; - /* replicator input port */ - port@2 { - reg = <0>; + in-ports { + port { replicator_in_port0: endpoint { - slave-mode; remote-endpoint = <&etf_out_port>; }; }; }; }; - timer { - compatible = "arm,armv7-timer"; - interrupt-parent = <&intc>; - interrupts = , - , - , - ; + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupt-parent = <&gpc>; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, + <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; }; soc { @@ -192,33 +194,28 @@ ranges; funnel@30041000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x30041000 0x1000>; clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; - ca_funnel_ports: ports { - #address-cells = <1>; - #size-cells = <0>; - - /* funnel input ports */ - port@0 { - reg = <0>; + ca_funnel_in_ports: in-ports { + port { ca_funnel_in_port0: endpoint { - slave-mode; remote-endpoint = <&etm0_out_port>; }; }; - /* funnel output port */ - port@2 { - reg = <0>; + /* the other input ports are not connect to anything */ + }; + + out-ports { + port { ca_funnel_out_port0: endpoint { remote-endpoint = <&hugo_funnel_in_port0>; }; }; - /* the other input ports are not connect to anything */ }; }; @@ -229,28 +226,33 @@ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; - port { - etm0_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port0>; + out-ports { + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; }; }; }; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + funnel@30083000 { - compatible = "arm,coresight-funnel", "arm,primecell"; + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x30083000 0x1000>; clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; - ports { + in-ports { #address-cells = <1>; #size-cells = <0>; - /* funnel input ports */ port@0 { reg = <0>; hugo_funnel_in_port0: endpoint { - slave-mode; remote-endpoint = <&ca_funnel_out_port0>; }; }; @@ -258,18 +260,18 @@ port@1 { reg = <1>; hugo_funnel_in_port1: endpoint { - slave-mode; /* M4 input */ + /* M4 input */ }; }; + /* the other input ports are not connect to anything */ + }; - port@2 { - reg = <0>; + out-ports { + port { hugo_funnel_out_port0: endpoint { remote-endpoint = <&etf_in_port>; }; }; - - /* the other input ports are not connect to anything */ }; }; @@ -279,20 +281,16 @@ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; + in-ports { + port { etf_in_port: endpoint { - slave-mode; remote-endpoint = <&hugo_funnel_out_port0>; }; }; + }; - port@1 { - reg = <0>; + out-ports { + port { etf_out_port: endpoint { remote-endpoint = <&replicator_in_port0>; }; @@ -306,10 +304,11 @@ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; - port { - etr_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; + in-ports { + port { + etr_in_port: endpoint { + remote-endpoint = <&replicator_out_port1>; + }; }; }; }; @@ -320,17 +319,18 @@ clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; clock-names = "apb_pclk"; - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port0>; + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint = <&replicator_out_port0>; + }; }; }; }; intc: interrupt-controller@31001000 { compatible = "arm,cortex-a7-gic"; - interrupts = ; + interrupts = ; #interrupt-cells = <3>; interrupt-controller; interrupt-parent = <&intc>; @@ -340,6 +340,17 @@ <0x31006000 0x2000>; }; + timer { + compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + clock-frequency = <8000000>; + }; + aips1: aips-bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -472,16 +483,17 @@ compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x302d0000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_GPT1_ROOT_CLK>; - clock-names = "ipg", "per"; + clocks = <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT1_ROOT_CLK>, + <&clks IMX7D_GPT_3M_CLK>; + clock-names = "ipg", "per", "osc_per"; }; gpt2: gpt@302e0000 { compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x302e0000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_GPT2_ROOT_CLK>, <&clks IMX7D_GPT2_ROOT_CLK>; clock-names = "ipg", "per"; status = "disabled"; @@ -491,7 +503,7 @@ compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x302f0000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_GPT3_ROOT_CLK>, <&clks IMX7D_GPT3_ROOT_CLK>; clock-names = "ipg", "per"; status = "disabled"; @@ -501,7 +513,7 @@ compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; reg = <0x30300000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_CLK_DUMMY>, + clocks = <&clks IMX7D_GPT4_ROOT_CLK>, <&clks IMX7D_GPT4_ROOT_CLK>; clock-names = "ipg", "per"; status = "disabled"; @@ -522,8 +534,43 @@ gpr: iomuxc-gpr@30340000 { compatible = "fsl,imx7d-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; + "fsl,imx6q-iomuxc-gpr", "syscon", + "simple-mfd"; reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <0>; + mux-reg-masks = <0x14 0x00000010>; + }; + + video_mux: csi-mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + csi_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_csi_mux>; + }; + }; + + port@2 { + reg = <2>; + + csi_mux_to_csi: endpoint { + remote-endpoint = <&csi_from_csi_mux>; + }; + }; + }; }; ocotp: ocotp-ctrl@30350000 { @@ -540,16 +587,10 @@ tempmon_temp_grade: temp-grade@10 { reg = <0x10 0x4>; }; - }; - tempmon: tempmon { - compatible = "fsl,imx7d-tempmon"; - interrupts = ; - fsl,tempmon =<&anatop>; - nvmem-cells = <&tempmon_calib>, - <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; + cpu_speed_grade: speed-grade@10 { + reg = <0x10 0x4>; + }; }; anatop: anatop@30360000 { @@ -558,11 +599,8 @@ reg = <0x30360000 0x10000>; interrupts = , ; - #address-cells = <1>; - #size-cells = <0>; - reg_1p0d: regulator-vdd1p0d@30360210 { - reg = <0x30360210>; + reg_1p0d: regulator-vdd1p0d { compatible = "fsl,anatop-regulator"; regulator-name = "vdd1p0d"; regulator-min-microvolt = <800000>; @@ -575,6 +613,34 @@ anatop-max-voltage = <1200000>; anatop-enable-bit = <0>; }; + + reg_1p2: regulator-vdd1p2 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p2"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + anatop-reg-offset = <0x220>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0x14>; + anatop-min-voltage = <1100000>; + anatop-max-voltage = <1300000>; + anatop-enable-bit = <0>; + }; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; }; snvs: snvs@30370000 { @@ -597,14 +663,18 @@ offset = <0x38>; value = <0x60>; mask = <0x60>; + status = "disabled"; }; snvs_pwrkey: snvs-powerkey { compatible = "fsl,sec-v4.0-pwrkey"; regmap = <&snvs>; interrupts = ; + clocks = <&clks IMX7D_SNVS_CLK>; + clock-names = "snvs"; linux,keycode = ; wakeup-source; + status = "disabled"; }; }; @@ -619,7 +689,7 @@ }; src: src@30390000 { - compatible = "fsl,imx7d-src", "syscon"; + compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon"; reg = <0x30390000 0x10000>; interrupts = ; #reset-cells = <1>; @@ -632,17 +702,30 @@ interrupts = ; #interrupt-cells = <3>; interrupt-parent = <&intc>; + fsl,mf-mix-wakeup-irq = <0x54010000 0xc00 0x0 0x1040640>; #power-domain-cells = <1>; pgc { #address-cells = <1>; #size-cells = <0>; - pgc_pcie_phy: pgc-power-domain@1 { + pgc_mipi_phy: power-domain@0 { + #power-domain-cells = <0>; + reg = <0>; + power-supply = <®_1p0d>; + }; + + pgc_pcie_phy: power-domain@1 { #power-domain-cells = <0>; reg = <1>; power-supply = <®_1p0d>; }; + + pgc_hsic_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = <2>; + power-supply = <®_1p2>; + }; }; }; }; @@ -669,10 +752,11 @@ interrupts = ; clocks = <&clks IMX7D_ADC_ROOT_CLK>; clock-names = "adc"; + #io-channel-cells = <1>; status = "disabled"; }; - ecspi4: ecspi@30630000 { + ecspi4: spi@30630000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; @@ -728,15 +812,67 @@ status = "disabled"; }; + csi: csi@30710000 { + compatible = "fsl,imx7-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "axi", "mclk", "dcic"; + status = "disabled"; + + port { + csi_from_csi_mux: endpoint { + remote-endpoint = <&csi_mux_to_csi>; + }; + }; + }; + lcdif: lcdif@30730000 { compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; reg = <0x30730000 0x10000>; interrupts = ; clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, - <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; - clock-names = "pix", "axi"; + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; status = "disabled"; }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7-mipi-csi2"; + reg = <0x30750000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "pclk", "wrap", "phy"; + power-domains = <&pgc_mipi_phy>; + phy-supply = <®_1p0d>; + resets = <&src IMX7_RESET_MIPI_PHY_MRST>; + reset-names = "mrst"; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_vc0_to_csi_mux: endpoint { + remote-endpoint = <&csi_mux_from_mipi_vc0>; + }; + }; + }; + + ddrc: ddrc@307a0000 { + compatible = "fsl,imx7-ddrc"; + reg = <0x307a0000 0x10000>; + }; }; aips3: aips-bus@30800000 { @@ -753,7 +889,7 @@ reg = <0x30800000 0x100000>; ranges; - ecspi1: ecspi@30820000 { + ecspi1: spi@30820000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; @@ -765,7 +901,7 @@ status = "disabled"; }; - ecspi2: ecspi@30830000 { + ecspi2: spi@30830000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; @@ -777,7 +913,7 @@ status = "disabled"; }; - ecspi3: ecspi@30840000 { + ecspi3: spi@30840000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; @@ -808,6 +944,8 @@ clocks = <&clks IMX7D_UART2_ROOT_CLK>, <&clks IMX7D_UART2_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 24 4 0>, <&sdma 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -819,6 +957,8 @@ clocks = <&clks IMX7D_UART3_ROOT_CLK>, <&clks IMX7D_UART3_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 26 4 0>, <&sdma 27 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -905,6 +1045,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN1_ROOT_CLK>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 1 0x10 17>; status = "disabled"; }; @@ -915,6 +1056,7 @@ clocks = <&clks IMX7D_CLK_DUMMY>, <&clks IMX7D_CAN2_ROOT_CLK>; clock-names = "ipg", "per"; + fsl,stop-mode = <&gpr 0x10 2 0x10 18>; status = "disabled"; }; @@ -966,6 +1108,8 @@ clocks = <&clks IMX7D_UART4_ROOT_CLK>, <&clks IMX7D_UART4_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 28 4 0>, <&sdma 29 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -977,6 +1121,8 @@ clocks = <&clks IMX7D_UART5_ROOT_CLK>, <&clks IMX7D_UART5_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 30 4 0>, <&sdma 31 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -988,6 +1134,8 @@ clocks = <&clks IMX7D_UART6_ROOT_CLK>, <&clks IMX7D_UART6_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 32 4 0>, <&sdma 33 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -999,9 +1147,37 @@ clocks = <&clks IMX7D_UART7_ROOT_CLK>, <&clks IMX7D_UART7_ROOT_CLK>; clock-names = "ipg", "per"; + dmas = <&sdma 34 4 0>, <&sdma 35 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; + mu0a: mailbox@30aa0000 { + compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + #mbox-cells = <2>; + status = "disabled"; + }; + + mu0b: mailbox@30ab0000 { + compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; + reg = <0x30ab0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + #mbox-cells = <2>; + fsl,mu-side-b; + status = "disabled"; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + usbotg1: usb@30b10000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b10000 0x200>; @@ -1017,6 +1193,7 @@ compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b30000 0x200>; interrupts = ; + power-domains = <&pgc_hsic_phy>; clocks = <&clks IMX7D_USB_CTRL_CLK>; fsl,usbphy = <&usbphynop3>; fsl,usbmisc = <&usbmisc3 0>; @@ -1047,6 +1224,8 @@ <&clks IMX7D_USDHC1_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; status = "disabled"; }; @@ -1059,6 +1238,8 @@ <&clks IMX7D_USDHC2_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; status = "disabled"; }; @@ -1071,19 +1252,8 @@ <&clks IMX7D_USDHC3_ROOT_CLK>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; - status = "disabled"; - }; - - qspi1: qspi@30bb0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-qspi"; - reg = <0x30bb0000 0x10000>, <0x60000000 0x10000000>; - reg-names = "QuadSPI", "QuadSPI-memory"; - interrupts = ; - clocks = <&clks IMX7D_QSPI_ROOT_CLK>, - <&clks IMX7D_QSPI_ROOT_CLK>; - clock-names = "qspi_en", "qspi"; + fsl,tuning-step = <2>; + fsl,tuning-start-tap = <20>; status = "disabled"; }; @@ -1091,8 +1261,8 @@ compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_SDMA_CORE_CLK>, - <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_SDMA_CORE_CLK>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; @@ -1106,15 +1276,15 @@ , , ; - clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, + clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; - fsl,num-tx-queues=<3>; - fsl,num-rx-queues=<3>; + fsl,num-tx-queues = <3>; + fsl,num-rx-queues = <3>; status = "disabled"; }; }; diff --git a/arch/arm/dts/imx7ulp-10x10-val.dts b/arch/arm/dts/imx7ulp-10x10-val.dts new file mode 100644 index 00000000000..47a4b56c043 --- /dev/null +++ b/arch/arm/dts/imx7ulp-10x10-val.dts @@ -0,0 +1,91 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP 10x10 val"; + compatible = "fsl,imx7ulp-10x10-val", "fsl,imx7ulp", "Generic DT based system"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x40A60000,115200"; + stdout-path = &lpuart6; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; +}; + +&iomuxc1 { + pinctrl-names = "default"; + + imx7ulp-10x10-val { + pinctrl_lpuart6: lpuart6grp { + fsl,pins = < + IMX7ULP_PAD_PTE11__LPUART6_RX 0x400 + IMX7ULP_PAD_PTE10__LPUART6_TX 0x400 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x843 + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x843 + IMX7ULP_PAD_PTE4__SDHC1_D3 0x843 + IMX7ULP_PAD_PTE5__SDHC1_D2 0x843 + IMX7ULP_PAD_PTE0__SDHC1_D1 0x843 + IMX7ULP_PAD_PTE1__SDHC1_D0 0x843 + >; + }; + + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + IMX7ULP_PAD_PTB14__QSPIA_SS1_B 0x43 /* SS1 */ + IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */ + IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */ + IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x43 /* D3 */ + IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */ + IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */ + IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x43 /* D0 */ + IMX7ULP_PAD_PTB5__PTB5 0x20003 + >; + }; + }; +}; + +&lpuart6 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart6>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + non-removable; + status = "okay"; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + + flash0: n25q512ax3@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q512ax3", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + }; +}; diff --git a/arch/arm/dts/imx7ulp-14x14-val.dts b/arch/arm/dts/imx7ulp-14x14-val.dts new file mode 100644 index 00000000000..0b392cf71c7 --- /dev/null +++ b/arch/arm/dts/imx7ulp-14x14-val.dts @@ -0,0 +1,98 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; + +#include "imx7ulp.dtsi" + +/ { + model = "NXP i.MX7ULP 14x14 val"; + compatible = "fsl,imx7ulp-14x14-val", "fsl,imx7ulp", "Generic DT based system"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200"; + stdout-path = &lpuart4; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; +}; + +&iomuxc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_1>; + + imx7ulp-14x14-val { + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + IMX7ULP_PAD_PTC10__PTC10 0x30100 + IMX7ULP_PAD_PTC1__PTC1 0x20100 + >; + }; + + pinctrl_lpuart4: lpuart4grp { + fsl,pins = < + IMX7ULP_PAD_PTC3__LPUART4_RX 0x400 + IMX7ULP_PAD_PTC2__LPUART4_TX 0x400 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX7ULP_PAD_PTE3__SDHC1_CMD 0x843 + IMX7ULP_PAD_PTE2__SDHC1_CLK 0x843 + IMX7ULP_PAD_PTE4__SDHC1_D3 0x843 + IMX7ULP_PAD_PTE5__SDHC1_D2 0x843 + IMX7ULP_PAD_PTE0__SDHC1_D1 0x843 + IMX7ULP_PAD_PTE1__SDHC1_D0 0x843 + >; + }; + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */ + IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */ + IMX7ULP_PAD_PTB9__QSPIA_DQS 0x43 /* DQS */ + IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x43 /* D3 */ + IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */ + IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */ + IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x43 /* D0 */ + IMX7ULP_PAD_PTB12__PTB12 0x20003 + >; + }; + }; +}; + +&lpuart4 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart4>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + non-removable; + status = "okay"; +}; + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + + flash0: mt35xu512aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt35xu512aba", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx7ulp-evk-emmc.dts b/arch/arm/dts/imx7ulp-evk-emmc.dts new file mode 100644 index 00000000000..9407d198c38 --- /dev/null +++ b/arch/arm/dts/imx7ulp-evk-emmc.dts @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk-qspi.dts" + +/* To support eMMC HS200/HS400, need to do the following reowrk: + * 1,remove TF sd slot, replace eMMC chip + * 2,fix eMMC I/O voltage to 1.8v, remove R183, short TP3 and TP89 + * 3,add R107, make eMMC boot work + */ +&usdhc0 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc0_8bit>; + pinctrl-1 = <&pinctrl_usdhc0_8bit>; + pinctrl-2 = <&pinctrl_usdhc0_8bit>; + pinctrl-3 = <&pinctrl_usdhc0_8bit>; + non-removable; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/dts/imx7ulp-evk-qspi.dts b/arch/arm/dts/imx7ulp-evk-qspi.dts new file mode 100644 index 00000000000..982a172d568 --- /dev/null +++ b/arch/arm/dts/imx7ulp-evk-qspi.dts @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "imx7ulp-evk.dts" + +&qspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi1_1>; + status = "okay"; + + flash0: mx25r6435f@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "macronix,mx25r6435f", "jedec,spi-nor"; + spi-max-frequency = <29000000>; + }; +}; + +&iomuxc { + status = "okay"; +}; + +&iomuxc { + imx7ulp-evk { + pinctrl_qspi1_1: qspi1grp_1 { + fsl,pins = < + IMX7ULP_PAD_PTB7__QSPIA_SS1_B 0x43 /* SS1 */ + IMX7ULP_PAD_PTB8__QSPIA_SS0_B 0x43 /* SS0 */ + IMX7ULP_PAD_PTB15__QSPIA_SCLK 0x43 /* SCLK */ + IMX7ULP_PAD_PTB9__QSPIA_DQS 0x43 /* DQS */ + IMX7ULP_PAD_PTB16__QSPIA_DATA3 0x43 /* D3 */ + IMX7ULP_PAD_PTB17__QSPIA_DATA2 0x43 /* D2 */ + IMX7ULP_PAD_PTB18__QSPIA_DATA1 0x43 /* D1 */ + IMX7ULP_PAD_PTB19__QSPIA_DATA0 0x43 /* D0 */ + >; + }; + }; +}; + diff --git a/arch/arm/dts/imx7ulp-evk.dts b/arch/arm/dts/imx7ulp-evk.dts index 8f6a935e241..f1b009c6636 100644 --- a/arch/arm/dts/imx7ulp-evk.dts +++ b/arch/arm/dts/imx7ulp-evk.dts @@ -31,7 +31,7 @@ reg = <0x60000000 0x40000000>; }; - backlight { + backlight: backlight { compatible = "gpio-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; @@ -47,6 +47,24 @@ #reset-cells = <0>; }; + dsi_host: dsi-host { + compatible = "northwest,mipi-dsi"; + status = "okay"; + }; + + rm68200_panel { + compatible = "raydium,rm68200"; + reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + status = "okay"; + + port { + rm68200_from_dsim: endpoint { + remote-endpoint = <&dsim_to_rm68200>; + }; + }; + }; + regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -240,7 +258,7 @@ IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0 IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0 IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0 - IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0 + IMX7ULP_PAD_PTF19__PTF19 0x0 >; }; @@ -285,32 +303,21 @@ }; &lcdif { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; - disp-dev = "mipi_dsi_northwest"; display = <&display0>; display0: display@0 { - bits-per-pixel = <16>; + bits-per-pixel = <24>; bus-width = <24>; + }; - display-timings { - native-mode = <&timing0>; - timing0: timing0 { - clock-frequency = <9200000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <8>; - hback-porch = <4>; - hsync-len = <41>; - vback-porch = <2>; - vfront-porch = <4>; - vsync-len = <10>; - - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <0>; - }; + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; }; }; }; @@ -335,21 +342,31 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpspi3>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>, <0>, <0>, <0>; + spi-max-frequency = <1000000>; status = "okay"; - - spidev0: spi@0 { - reg = <0>; - compatible = "rohm,dh2228fv"; - spi-max-frequency = <1000000>; - }; }; &mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mipi_dsi_reset>; lcd_panel = "TRULY-WVGA-TFT3P5581E"; resets = <&mipi_dsi_reset>; status = "okay"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + + port@1 { + dsim_to_rm68200: endpoint { + remote-endpoint = <&rm68200_from_dsim>; + }; + }; }; &lpuart4 { /* console */ diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi index 7bcd2cc3469..642a1e0517a 100644 --- a/arch/arm/dts/imx7ulp.dtsi +++ b/arch/arm/dts/imx7ulp.dtsi @@ -30,11 +30,13 @@ serial3 = &lpuart7; usbphy0 = &usbphy1; usb0 = &usbotg1; + usbgadget0 = &usbg1; i2c4 = &lpi2c4; i2c5 = &lpi2c5; i2c6 = &lpi2c6; i2c7 = &lpi2c7; spi0 = &qspi1; + spi3 = &lpspi3; }; cpus { @@ -198,6 +200,29 @@ }; }; + crypto: crypto@40240000 { + compatible = "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40240000 0x10000>; + ranges = <0 0x40240000 0x10000>; + clocks = <&clks IMX7ULP_CLK_CAAM>, + <&clks IMX7ULP_CLK_NIC1_BUS_DIV>; + clock-names = "aclk", "ipg"; + + sec_jr0: jr@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + sec_jr1: jr@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + tpm5: tpm@40260000 { compatible = "fsl,imx7ulp-tpm"; reg = <0x40260000 0x1000>; @@ -244,8 +269,9 @@ compatible = "fsl,imx7ulp-spi"; reg = <0x40290000 0x10000>; interrupts = ; - clocks = <&clks IMX7ULP_CLK_LPSPI2>; - clock-names = "ipg"; + clocks = <&clks IMX7ULP_CLK_LPSPI2>, + <&clks IMX7ULP_CLK_DUMMY>; + clock-names = "per", "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPSPI2>; assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; @@ -256,8 +282,9 @@ compatible = "fsl,imx7ulp-spi"; reg = <0x402A0000 0x10000>; interrupts = ; - clocks = <&clks IMX7ULP_CLK_LPSPI3>; - clock-names = "ipg"; + clocks = <&clks IMX7ULP_CLK_LPSPI3>, + <&clks IMX7ULP_CLK_DUMMY>; + clock-names = "per", "ipg"; assigned-clocks = <&clks IMX7ULP_CLK_LPSPI3>; assigned-clock-parents = <&clks IMX7ULP_CLK_FIRC>; assigned-clock-rates = <48000000>; @@ -290,6 +317,13 @@ status = "disabled"; }; + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + usbotg1: usb@40330000 { compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; @@ -480,6 +514,9 @@ interrupts = ; clocks = <&clks IMX7ULP_CLK_DSI>; clock-names = "mipi_dsi_clk"; + data-lanes-num = <2>; + phy-ref-clkfreq = <24000000>; + max-data-rate = <800000000>; sim = <&sim>; status = "disabled"; }; diff --git a/arch/arm/dts/imx8mm-ddr3l-val.dts b/arch/arm/dts/imx8mm-ddr3l-val.dts new file mode 100644 index 00000000000..24965134f09 --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr3l-val.dts @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +/dts-v1/; + +#include "imx8mm.dtsi" + +/ { + model = "NXP i.MX8MM DDR3L Validation board"; + compatible = "fsl,imx8mm-val", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-val { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; diff --git a/arch/arm/dts/imx8mm-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-ddr4-evk-u-boot.dtsi new file mode 100644 index 00000000000..30b78ceaa36 --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr4-evk-u-boot.dtsi @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&fec1 { + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&lcdif { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/imx8mm-ddr4-evk.dts b/arch/arm/dts/imx8mm-ddr4-evk.dts new file mode 100644 index 00000000000..696fcf23672 --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr4-evk.dts @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2018 NXP + */ + +/dts-v1/; + +#include "imx8mm-evk.dtsi" + +/ { + model = "NXP i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; + compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +/delete-node/ &pmic; + +&i2c1 { + pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-ddr4-val.dts b/arch/arm/dts/imx8mm-ddr4-val.dts new file mode 100644 index 00000000000..de0b8da4e8b --- /dev/null +++ b/arch/arm/dts/imx8mm-ddr4-val.dts @@ -0,0 +1,530 @@ +/* + * Copyright 2018 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include +#include "imx8mm.dtsi" + +/ { + model = "NXP i.MX8MM DDR4 Validation board"; + compatible = "fsl,imx8mm-val", "fsl,imx8mm"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mm-val { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + }; + + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_uart2: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: bd71837@4b { + reg = <0x4b>; + compatible = "rohm,bd71837"; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck7_reg: regulator@6 { + reg = <6>; + regulator-compatible = "buck7"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck8_reg: regulator@7 { + reg = <7>; + regulator-compatible = "buck8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@11 { + reg = <11>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@12 { + reg = <12>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6_reg: regulator@13 { + reg = <13>; + regulator-compatible = "ldo6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo7_reg: regulator@14 { + reg = <14>; + regulator-compatible = "ldo7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110"; + reg = <0x50>; + status = "okay"; + + typec1_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; + + ptn5110_2: tcpc@52 { + compatible = "nxp,ptn5110"; + reg = <0x52>; + status = "okay"; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: n25q256a@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <8>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-okay; + at803x,vddio-1p8v; + }; + }; +}; + +&uart2 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&usbotg2 { + status = "okay"; + extcon = <&ptn5110_2>; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + non-removable; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; diff --git a/arch/arm/dts/imx8mm-evk-qca-wifi-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-qca-wifi-u-boot.dtsi new file mode 100644 index 00000000000..dab32ea1d83 --- /dev/null +++ b/arch/arm/dts/imx8mm-evk-qca-wifi-u-boot.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2020 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&fec1 { + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&lcdif { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/imx8mm-evk-qca-wifi.dts b/arch/arm/dts/imx8mm-evk-qca-wifi.dts new file mode 100644 index 00000000000..b4a08fed832 --- /dev/null +++ b/arch/arm/dts/imx8mm-evk-qca-wifi.dts @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2020 NXP + */ + +/dts-v1/; + +#include +#include "imx8mm-evk.dtsi" + +/ { + model = "NXP i.MX8MM LPDDR4 EVK QCA-WIFI board"; + compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + + aliases { + spi0 = &flexspi; + }; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&usdhc3 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + }; +}; + +/delete-node/ &pmic; + +&i2c1 { + pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 GPIO_ACTIVE_LOW>; + rohm,reset-snvs-powered; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <900000>; + }; + + buck3_reg: BUCK3 { + // BUCK5 in datasheet + regulator-name = "BUCK3"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + // BUCK6 in datasheet + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + // BUCK7 in datasheet + regulator-name = "BUCK5"; + regulator-min-microvolt = <1605000>; + regulator-max-microvolt = <1995000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: BUCK6 { + // BUCK8 in datasheet + regulator-name = "BUCK6"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi index e843a5648e8..6f7b37cba2b 100644 --- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi @@ -9,6 +9,32 @@ wdt = <&wdog1>; u-boot,dm-spl; }; + + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; &{/soc@0} { @@ -48,6 +74,7 @@ ®_usdhc2_vmmc { u-boot,off-on-delay-us = <20000>; + u-boot,dm-spl; }; &pinctrl_reg_usdhc2_vmmc { @@ -96,29 +123,39 @@ &usdhc1 { u-boot,dm-spl; + assigned-clocks = <&clk IMX8MM_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; }; &usdhc2 { u-boot,dm-spl; sd-uhs-sdr104; sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; + fsl,signal-voltage-switch-extra-delay-ms = <8>; }; &usdhc3 { u-boot,dm-spl; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MM_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>; }; &i2c1 { u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { u-boot,dm-spl; }; -&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { u-boot,dm-spl; }; @@ -134,6 +171,31 @@ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; }; +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + &wdog1 { u-boot,dm-spl; }; + +&usbotg1 { + status = "okay"; + extcon = <&ptn5110>; +}; + +&lcdif { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts index 4e2820d1924..c07eb8be8e4 100644 --- a/arch/arm/dts/imx8mm-evk.dts +++ b/arch/arm/dts/imx8mm-evk.dts @@ -9,9 +9,13 @@ #include "imx8mm-evk.dtsi" / { - model = "FSL i.MX8MM EVK board"; + model = "NXP i.MX8MM EVK board"; compatible = "fsl,imx8mm-evk", "fsl,imx8mm"; + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + }; + aliases { spi0 = &flexspi; }; diff --git a/arch/arm/dts/imx8mm-evk.dtsi b/arch/arm/dts/imx8mm-evk.dtsi index 6518f088b2c..097fdce9e1f 100644 --- a/arch/arm/dts/imx8mm-evk.dtsi +++ b/arch/arm/dts/imx8mm-evk.dtsi @@ -81,6 +81,32 @@ clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; }; }; + + dsi_host: dsi-host { + compatible = "samsung,sec-mipi-dsi"; + status = "okay"; + }; + + rm67191_panel { + compatible = "raydium,rm67191"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + + port { + rm67191_from_dsim: endpoint { + remote-endpoint = <&dsim_to_rm67191>; + }; + }; + }; }; &A53_0 { @@ -99,6 +125,23 @@ cpu-supply = <&buck2_reg>; }; + +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spi@0 { + reg = <0>; + compatible = "rohm,dh2228fv"; + spi-max-frequency = <500000>; + }; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -122,129 +165,153 @@ &i2c1 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@4b { - compatible = "rohm,bd71847"; - reg = <0x4b>; - pinctrl-names = "default"; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450a"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ pinctrl-0 = <&pinctrl_pmic>; - interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - rohm,reset-snvs-powered; - - #clock-cells = <0>; - clocks = <&osc_32k 0>; - clock-output-names = "clk-32k-out"; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; regulators { - buck1_reg: BUCK1 { - regulator-name = "buck1"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; + regulator-ramp-delay = <3125>; }; - buck2_reg: BUCK2 { - regulator-name = "buck2"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1300000>; + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; - regulator-ramp-delay = <1250>; - rohm,dvs-run-voltage = <1000000>; - rohm,dvs-idle-voltage = <900000>; + regulator-ramp-delay = <3125>; }; - buck3_reg: BUCK3 { - // BUCK5 in datasheet - regulator-name = "buck3"; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1350000>; + buck3_reg: regulator@2 { + reg = <2>; + regulator-compatible = "buck3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; regulator-boot-on; regulator-always-on; }; - buck4_reg: BUCK4 { - // BUCK6 in datasheet - regulator-name = "buck4"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3300000>; + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck5_reg: BUCK5 { - // BUCK7 in datasheet - regulator-name = "buck5"; - regulator-min-microvolt = <1605000>; - regulator-max-microvolt = <1995000>; + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - buck6_reg: BUCK6 { - // BUCK8 in datasheet - regulator-name = "buck6"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1400000>; + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; regulator-boot-on; regulator-always-on; }; - ldo1_reg: LDO1 { - regulator-name = "ldo1"; + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo2_reg: LDO2 { - regulator-name = "ldo2"; + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <900000>; + regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; - ldo3_reg: LDO3 { - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo4_reg: LDO4 { - regulator-name = "ldo4"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; - ldo6_reg: LDO6 { - regulator-name = "ldo6"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; }; + }; }; }; &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3c>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; @@ -276,9 +343,12 @@ }; &i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; status = "okay"; pca6416: gpio@20 { @@ -314,6 +384,7 @@ srp-disable; adp-disable; usb-role-switch; + disable-over-current; samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; @@ -345,7 +416,47 @@ status = "okay"; }; +&lcdif { + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + }; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + }; + }; + + port@2 { + dsim_to_rm67191: endpoint { + remote-endpoint = <&rm67191_from_dsim>; + }; + }; +}; + &iomuxc { + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + >; + }; + + pinctrl_ecspi2_cs: ecspi2cs { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 @@ -405,6 +516,27 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 @@ -483,7 +615,13 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 >; }; }; diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi index c824f2615fe..3ea4cd32fe4 100644 --- a/arch/arm/dts/imx8mm.dtsi +++ b/arch/arm/dts/imx8mm.dtsi @@ -4,9 +4,11 @@ */ #include +#include #include #include #include +#include #include #include "imx8mm-pinfunc.h" @@ -37,6 +39,9 @@ spi0 = &ecspi1; spi1 = &ecspi2; spi2 = &ecspi3; + usb0 = &usbotg1; + usb1 = &usbotg2; + video0 = &lcdif; }; cpus { @@ -194,16 +199,120 @@ pmu { compatible = "arm,armv8-pmuv3"; interrupts = ; + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; }; + power-domains { + compatible = "simple-bus"; + /* HSIO SS */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <0>; + domain-name = "hsiomix"; + clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; + }; + + pcie_pd: pcie-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <1>; + domain-name = "pcie"; + parent-domains = <&hsiomix_pd>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; + }; + + usb_otg1_pd: usbotg1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg2_pd: usbotg2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <3>; + domain-name = "usb_otg2"; + parent-domains = <&hsiomix_pd>; + }; + + /* GPU SS */ + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <4>; + domain-name = "gpumix"; + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + }; + + /* VPU SS */ + vpumix_pd: vpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <5>; + domain-name = "vpumix"; + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + }; + + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + }; + + vpu_g2_pd: vpug2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <7>; + domain-name = "vpu_g2"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; + }; + + vpu_h1_pd: vpuh1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <8>; + domain-name = "vpu_h1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_H1_ROOT>; + }; + + /* DISP SS */ + dispmix_pd: dispmix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <9>; + domain-name = "dispmix"; + clocks = <&clk IMX8MM_CLK_DISP_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: mipi-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <10>; + domain-name = "mipi"; + parent-domains = <&dispmix_pd>; + }; + }; + timer { compatible = "arm,armv8-timer"; - interrupts = , /* Physical Secure */ - , /* Physical Non-Secure */ - , /* Virtual */ - ; /* Hypervisor */ + interrupts = , /* Physical Secure */ + , /* Physical Non-Secure */ + , /* Virtual */ + ; /* Hypervisor */ clock-frequency = <8000000>; arm,no-tick-in-suspend; }; @@ -262,6 +371,11 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -274,12 +388,13 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30010000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI1_IPG>, + clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0xff 0xff>; status = "disabled"; }; @@ -288,10 +403,10 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30020000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI2_IPG>, + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI2_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -302,10 +417,10 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30030000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI3_IPG>, + clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI3_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; dma-names = "rx", "tx"; status = "disabled"; @@ -316,12 +431,13 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30050000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI5_IPG>, + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; dma-names = "rx", "tx"; + fsl,dataline = <0 0xf 0xf>; status = "disabled"; }; @@ -330,16 +446,16 @@ compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai"; reg = <0x30060000 0x10000>; interrupts = ; - clocks = <&clk IMX8MM_CLK_SAI6_IPG>, + clocks = <&clk IMX8MM_CLK_SAI6_IPG>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_SAI6_ROOT>, <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; dma-names = "rx", "tx"; status = "disabled"; }; - micfil: audio-controller@30080000 { + micfil: micfil@30080000 { compatible = "fsl,imx8mm-micfil"; reg = <0x30080000 0x10000>; interrupts = , @@ -359,7 +475,7 @@ }; spdif1: spdif@30090000 { - compatible = "fsl,imx35-spdif"; + compatible = "fsl,imx8mm-spdif"; reg = <0x30090000 0x10000>; interrupts = ; clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */ @@ -506,7 +622,7 @@ }; gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mm-iomuxc-gpr", "syscon"; + compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -521,6 +637,10 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@640 { + reg = <0x90 6>; + }; }; anatop: anatop@30360000 { @@ -528,6 +648,22 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MM_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -823,6 +959,7 @@ reg = <0x30aa0000 0x10000>; interrupts = ; clocks = <&clk IMX8MM_CLK_MU_ROOT>; + clock-names = "mu"; #mbox-cells = <2>; }; @@ -893,7 +1030,7 @@ }; fec1: ethernet@30be0000 { - compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = , , @@ -909,18 +1046,47 @@ assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>, <&clk IMX8MM_CLK_ENET_TIMER>, <&clk IMX8MM_CLK_ENET_REF>, - <&clk IMX8MM_CLK_ENET_TIMER>; + <&clk IMX8MM_CLK_ENET_PHY_REF>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, <&clk IMX8MM_SYS_PLL2_100M>, - <&clk IMX8MM_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + <&clk IMX8MM_SYS_PLL2_125M>, + <&clk IMX8MM_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + fsl,stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; }; + noc: interconnect@32700000 { + compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; + reg = <0x32700000 0x100000>; + clocks = <&clk IMX8MM_CLK_NOC>; + fsl,ddrc = <&ddrc>; + #interconnect-cells = <1>; + operating-points-v2 = <&noc_opp_table>; + + noc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150M { + opp-hz = /bits/ 64 <150000000>; + }; + opp-375M { + opp-hz = /bits/ 64 <375000000>; + }; + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; + }; + aips4: bus@32c00000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x32c00000 0x400000>; @@ -928,14 +1094,110 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + lcdif: lcdif@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = ; + lcdif-gpr = <&dispmix_gpr>; + resets = <&lcdif_resets>; + power-domains = <&dispmix_pd>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: mipi_dsi@32e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <266000000>, <12000000>; + interrupts = ; + dsi-gpr = <&dispmix_gpr>; + resets = <&mipi_dsi_resets>; + power-domains = <&mipi_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + csi1_bridge: csi1_bridge@32e20000 { + compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi"; + reg = <0x32e20000 0x1000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + power-domains = <&dispmix_pd>; + status = "disabled"; + }; + + mipi_csi_1: mipi_csi@32e30000 { + compatible = "fsl,imx8mm-mipi-csi"; + reg = <0x32e30000 0x1000>; + interrupts = ; + clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb"; + bus-width = <4>; + power-domains = <&mipi_pd>; + status = "disabled"; + }; + + dispmix_gpr: display-gpr@32e28000 { + compatible = "fsl, imx8mm-iomuxc-gpr", "syscon"; + reg = <0x32e28000 0x100>; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; + }; + usbotg1: usb@32e40000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, + <&clk IMX8MM_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; status = "disabled"; @@ -948,13 +1210,15 @@ }; usbotg2: usb@32e50000 { - compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e50000 0x200>; interrupts = ; clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>, + <&clk IMX8MM_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>, + <&clk IMX8MM_SYS_PLL1_100M>; fsl,usbphy = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; status = "disabled"; @@ -966,6 +1230,10 @@ reg = <0x32e50200 0x200>; }; + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx7d-pcie-phy"; + reg = <0x32f00000 0x10000>; + }; }; dma_apbh: dma-controller@33000000 { @@ -997,6 +1265,60 @@ status = "disabled"; }; + pcie0: pcie@33800000 { + compatible = "fsl,imx8mm-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x400000>, + <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + num-viewport = <4>; + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + linux,pci-domain = <0>; + fsl,max-link-speed = <2>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + status = "disabled"; + }; + + pcie0_ep: pcie_ep@33800000 { + compatible = "fsl,imx8mm-pcie-ep"; + reg = <0x33800000 0x000400000>, + <0x18000000 0x08000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + interrupts = ; /* eDMA */ + interrupt-names = "dma"; + fsl,max-link-speed = <2>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "clkreq", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ @@ -1022,4 +1344,79 @@ interrupts = ; }; }; + + dispmix-reset { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mm-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mm-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mm-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + }; + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-soft-resetn { + compatible = "lcdif,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MM_BUS_RSTN_BLK_SYNC>; + }; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MM_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MM_LCDIF_PIXEL_CLK_EN>; + }; + }; + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-soft-resetn { + compatible = "dsi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MM_MIPI_DSI_I_PRESET>; + }; + + dsi-clk-enable { + compatible = "dsi,clk-enable"; + resets = <&dispmix_clk_en IMX8MM_MIPI_DSI_CLKREF_EN>, + <&dispmix_clk_en IMX8MM_MIPI_DSI_PCLK_EN>; + }; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MM_MIPI_M_RESET>; + }; + }; }; diff --git a/arch/arm/dts/imx8mn-ddr3l-evk.dts b/arch/arm/dts/imx8mn-ddr3l-evk.dts new file mode 100644 index 00000000000..57e30f7427a --- /dev/null +++ b/arch/arm/dts/imx8mn-ddr3l-evk.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2020 NXP + */ + +#include "imx8mn-evk.dts" +#include "imx8mn-evk-u-boot.dtsi" + +/ { + model = "NXP i.MX8MNano DDR3L EVK board"; +}; + +&dsi_host { + status = "disabled"; +}; + +&{/rm67191_panel} { + status = "disabled"; +}; + +&lcdif { + status = "disabled"; +}; + +&mipi_dsi { + status = "disabled"; +}; diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi index 025090fff4d..c7d8dae2be6 100644 --- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi @@ -9,6 +9,32 @@ wdt = <&wdog1>; u-boot,dm-spl; }; + + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; &{/soc@0} { @@ -19,6 +45,9 @@ &clk { u-boot,dm-spl; u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; }; &osc_24m { @@ -43,12 +72,13 @@ u-boot,dm-spl; }; -&pinctrl_reg_usdhc2_vmmc { +®_usdhc2_vmmc { u-boot,dm-spl; + u-boot,off-on-delay-us = <20000>; }; -®_usdhc2_vmmc { - u-boot,off-on-delay-us = <20000>; +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; }; &pinctrl_uart2 { @@ -91,22 +121,95 @@ u-boot,dm-spl; }; +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + &usdhc1 { u-boot,dm-spl; + assigned-clocks = <&clk IMX8MN_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; }; &usdhc2 { u-boot,dm-spl; sd-uhs-sdr104; sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; }; &usdhc3 { u-boot,dm-spl; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MN_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; }; &wdog1 { u-boot,dm-spl; }; + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&fec1 { + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&lcdif { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/imx8mn-evk-u-boot.dtsi b/arch/arm/dts/imx8mn-evk-u-boot.dtsi new file mode 100644 index 00000000000..20e2ffccce1 --- /dev/null +++ b/arch/arm/dts/imx8mn-evk-u-boot.dtsi @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + aliases { + usbgadget0 = &usbg1; + usbgadget1 = &usbg2; + }; + + usbg1: usbg1 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg1>; + status = "okay"; + }; + + usbg2: usbg2 { + compatible = "fsl,imx27-usb-gadget"; + dr_mode = "peripheral"; + chipidea,usb = <&usbotg2>; + status = "okay"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; + u-boot,off-on-delay-us = <20000>; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&usdhc1 { + u-boot,dm-spl; + assigned-clocks = <&clk IMX8MN_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MN_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&fec1 { + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&lcdif { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/imx8mn-evk.dts b/arch/arm/dts/imx8mn-evk.dts new file mode 100644 index 00000000000..853c53f2ce8 --- /dev/null +++ b/arch/arm/dts/imx8mn-evk.dts @@ -0,0 +1,132 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2019 NXP + */ + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-evk.dtsi" +#include + +/ { + model = "NXP i.MX8MNano EVK board"; + compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + pmic: pca9450@25 { + compatible = "nxp,pca9450b"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1{ + regulator-name = "BUCK1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + buck4: BUCK4{ + regulator-name = "BUCK4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5{ + regulator-name = "BUCK5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "LDO4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx8mn-evk.dtsi b/arch/arm/dts/imx8mn-evk.dtsi index 76d042a4cf0..a4583848247 100644 --- a/arch/arm/dts/imx8mn-evk.dtsi +++ b/arch/arm/dts/imx8mn-evk.dtsi @@ -8,6 +8,7 @@ / { chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; stdout-path = &uart2; }; @@ -46,6 +47,32 @@ pinctrl-0 = <&pinctrl_ir>; linux,autosuspend-period = <125>; }; + + dsi_host: dsi-host { + compatible = "samsung,sec-mipi-dsi"; + status = "okay"; + }; + + rm67191_panel { + compatible = "raydium,rm67191"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + + port { + rm67191_from_dsim: endpoint { + remote-endpoint = <&dsim_to_rm67191>; + }; + }; + }; }; &fec1 { @@ -69,17 +96,37 @@ &i2c1 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; }; &i2c2 { clock-frequency = <400000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; status = "okay"; + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3c>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; + ptn5110: tcpc@50 { compatible = "nxp,ptn5110"; pinctrl-names = "default"; @@ -108,12 +155,40 @@ self-powered; }; }; + + ptn5110_2: tcpc@52 { + compatible = "nxp,ptn5110"; + reg = <0x52>; + status = "okay"; + + port { + typec2_dr_sw: endpoint { + remote-endpoint = <&usb2_drd_sw>; + }; + }; + + typec2_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <15000000>; + self-powered; + }; + }; }; &i2c3 { - clock-frequency = <400000>; - pinctrl-names = "default"; + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; status = "okay"; pca6416: gpio@20 { @@ -124,6 +199,46 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: display@0 { + bits-per-pixel = <24>; + bus-width = <24>; + }; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + }; + }; + + port@2 { + dsim_to_rm67191: endpoint { + remote-endpoint = <&rm67191_from_dsim>; + }; + }; +}; + &snvs_pwrkey { status = "okay"; }; @@ -140,9 +255,11 @@ srp-disable; adp-disable; usb-role-switch; + disable-over-current; samsung,picophy-pre-emp-curr-control = <3>; samsung,picophy-dc-vol-level-adjust = <7>; status = "okay"; + extcon = <&ptn5110>; port { usb1_drd_sw: endpoint { @@ -151,6 +268,17 @@ }; }; +&usbotg2 { + status = "okay"; + extcon = <&ptn5110_2>; + + port { + usb2_drd_sw: endpoint { + remote-endpoint = <&typec2_dr_sw>; + }; + }; +}; + &usdhc2 { assigned-clocks = <&clk IMX8MN_CLK_USDHC2>; assigned-clock-rates = <200000000>; @@ -204,6 +332,18 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84 + MX8MN_IOMUXC_NAND_DQS_QSPI_A_DQS 0x40000084 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 @@ -237,6 +377,27 @@ >; }; + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x1c3 + MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3 + MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3 + MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 @@ -357,4 +518,10 @@ MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16 + >; + }; }; diff --git a/arch/arm/dts/imx8mn.dtsi b/arch/arm/dts/imx8mn.dtsi index ee179023049..1f3286e19c7 100644 --- a/arch/arm/dts/imx8mn.dtsi +++ b/arch/arm/dts/imx8mn.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -34,9 +35,10 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; + spi0 = &flexspi; + usb0 = &usbotg1; + usb1 = &usbotg2; + video0 = &lcdif; }; cpus { @@ -186,6 +188,72 @@ clock-output-names = "clk_ext4"; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MN_DRAM_PLL_OUT>, <&clk IMX8MN_CLK_DRAM_ALT>, + <&clk IMX8MN_CLK_DRAM_APB>, <&clk IMX8MN_CLK_DRAM_APB>, + <&clk IMX8MN_CLK_DRAM_CORE>, <&clk IMX8MN_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MN_SYS_PLL1_40M>, <&clk IMX8MN_SYS_PLL1_100M>, + <&clk IMX8MN_SYS_PLL2_333M>, <&clk IMX8MN_CLK_NOC>, + <&clk IMX8MN_CLK_AHB>, <&clk IMX8MN_CLK_MAIN_AXI>, + <&clk IMX8MN_CLK_24M>, <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + + power-domains { + compatible = "simple-bus"; + + /* HSIOMIX */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <0>; + #power-domain-cells = <0>; + domain-name = "hsiomix"; + clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; + }; + + usb_otg1_pd: usbotg1-pd{ + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + /* GPU2D&3D */ + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <4>; + #power-domain-cells = <0>; + domain-name = "gpumix"; + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, + <&clk IMX8MN_CLK_GPU_AHB>; + }; + + dispmix_pd: dispmix-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <9>; + #power-domain-cells = <0>; + domain-name = "dispmix"; + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + }; + + mipi_pd: mipi-pd { + compatible = "fsl,imx8m-pm-domain"; + domain-index = <10>; + #power-domain-cells = <0>; + domain-name = "mipi"; + parent-domains = <&dispmix_pd>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; ranges = <0x0 0x0 0x0 0x3e000000>; + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -465,6 +538,7 @@ compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + u-boot,dm-pre-reloc; #thermal-sensor-cells = <0>; }; @@ -542,6 +616,20 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -875,6 +963,22 @@ status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MN_CLK_QSPI_ROOT>, + <&clk IMX8MN_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MN_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_400M>; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; @@ -887,7 +991,7 @@ }; fec1: ethernet@30be0000 { - compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec"; + compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; interrupts = , , @@ -910,6 +1014,8 @@ assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + stop-mode = <&gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; @@ -922,16 +1028,82 @@ #size-cells = <1>; ranges; + lcdif: lcd-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, + <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MN_CLK_DISP_PIXEL>, + <&clk IMX8MN_CLK_DISP_AXI>, + <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_VIDEO_PLL1_OUT>, + <&clk IMX8MN_SYS_PLL2_1000M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, + <500000000>, + <200000000>; + interrupts = ; + resets = <&lcdif_resets>; + power-domains = <&dispmix_pd>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: dsi_controller@32e10000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mn-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>, + <&clk IMX8MN_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>, + <&clk IMX8MN_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, + <594000000>; + interrupts = ; + resets = <&mipi_dsi_resets>; + power-domains = <&mipi_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + display-subsystem { + compatible = "fsl,imx-display-subsystem"; + ports = <&lcdif_disp0>; + }; + usbotg1: usb@32e40000 { - compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; + compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x32e40000 0x200>; interrupts = ; clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; clock-names = "usb1_ctrl_root_clk"; - assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>; - assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>; + assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, + <&clk IMX8MN_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, + <&clk IMX8MN_SYS_PLL1_100M>; fsl,usbphy = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&usb_otg1_pd>; status = "disabled"; }; @@ -940,6 +1112,28 @@ #index-cells = <1>; reg = <0x32e40200 0x200>; }; + + usbotg2: usb@32e50000 { + compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; + reg = <0x32e50000 0x200>; + interrupts = ; + clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>; + clock-names = "usb1_ctrl_root_clk"; + assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>, + <&clk IMX8MN_CLK_USB_CORE_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>, + <&clk IMX8MN_SYS_PLL1_100M>; + fsl,usbphy = <&usbphynop2>; + fsl,usbmisc = <&usbmisc2 0>; + status = "disabled"; + }; + + usbmisc2: usbmisc@32e50200 { + compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc"; + #index-cells = <1>; + reg = <0x32e50200 0x200>; + }; + }; dma_apbh: dma-controller@33000000 { @@ -1004,4 +1198,90 @@ assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; clock-names = "main_clk"; }; + + usbphynop2: usbphynop2 { + compatible = "usb-nop-xceiv"; + clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; + assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>; + clock-names = "main_clk"; + }; + + + dispmix-reset { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mn-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mn-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mn-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp_apb_root_clk"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + }; + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-soft-resetn { + compatible = "lcdif,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>; + }; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>; + }; + }; + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-soft-resetn { + compatible = "dsi,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_MIPI_DSI_CLKREF_RESET>, + <&dispmix_sft_rstn IMX8MN_MIPI_DSI_PCLK_RESET>; + }; + + dsi-clk-enable { + compatible = "dsi,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_MIPI_DSI_CLKREF_EN>, + <&dispmix_clk_en IMX8MN_MIPI_DSI_PCLK_EN>; + }; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>; + }; + }; }; diff --git a/arch/arm/dts/imx8mp-ddr4-evk.dts b/arch/arm/dts/imx8mp-ddr4-evk.dts new file mode 100644 index 00000000000..9ef9b2d5981 --- /dev/null +++ b/arch/arm/dts/imx8mp-ddr4-evk.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright 2020 NXP + */ + +#include "imx8mp-evk.dts" +#include "imx8mp-evk-u-boot.dtsi" + +/ { + model = "NXP i.MX8MPlus DDR4 EVK board"; +}; + +&flexspi { + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; + +&usdhc3 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x00000096 + MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x00000096 + MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x00000096 + MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x00000096 + MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x00000096 + MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x00000096 + MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x00000096 + MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x00000096 + MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x00000096 + MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x00000096 + MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x00000096 + MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x00000096 + MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x00000096 + MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x00000096 + MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x00000096 + MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x00000056 + MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x00000096 + MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x00000096 + >; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi b/arch/arm/dts/imx8mp-evk-u-boot.dtsi index 6a91404d7b1..20ae101cad5 100644 --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi @@ -9,6 +9,13 @@ wdt = <&wdog1>; u-boot,dm-spl; }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; }; &{/soc@0} { @@ -19,6 +26,10 @@ &clk { u-boot,dm-spl; u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + }; &osc_32k { @@ -48,12 +59,13 @@ u-boot,dm-spl; }; -®_usdhc2_vmmc { - u-boot,off-on-delay-us = <20000>; +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; }; ®_usdhc2_vmmc { u-boot,dm-spl; + u-boot,off-on-delay-us = <20000>; }; &pinctrl_uart2 { @@ -96,52 +108,112 @@ u-boot,dm-spl; }; -&i2c1 { +&crypto { u-boot,dm-spl; }; -&i2c2 { +&sec_jr0 { u-boot,dm-spl; }; -&i2c3 { +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { u-boot,dm-spl; }; -&i2c4 { +&i2c3 { u-boot,dm-spl; }; -&i2c5 { +&pinctrl_i2c1 { u-boot,dm-spl; }; -&i2c6 { +&pinctrl_i2c1_gpio { u-boot,dm-spl; }; &usdhc1 { u-boot,dm-spl; + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; }; &usdhc2 { u-boot,dm-spl; sd-uhs-sdr104; sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; }; &usdhc3 { u-boot,dm-spl; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; }; &wdog1 { u-boot,dm-spl; }; +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + + phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + &fec { phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; phy-reset-duration = <15>; phy-reset-post-delay = <100>; }; + +&flexspi { + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&lcdif1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/imx8mp-evk.dts b/arch/arm/dts/imx8mp-evk.dts index b10dce8767a..f0159d499ed 100644 --- a/arch/arm/dts/imx8mp-evk.dts +++ b/arch/arm/dts/imx8mp-evk.dts @@ -5,13 +5,15 @@ /dts-v1/; +#include #include "imx8mp.dtsi" / { - model = "NXP i.MX8MPlus EVK board"; + model = "NXP i.MX8MPlus LPDDR4 EVK board"; compatible = "fsl,imx8mp-evk", "fsl,imx8mp"; chosen { + bootargs = "console=ttymxc1,115200"; stdout-path = &uart2; }; @@ -55,6 +57,18 @@ enable-active-high; }; + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -64,6 +78,54 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + dsi_host: dsi-host { + compatible = "samsung,sec-mipi-dsi"; + status = "okay"; + }; + + rm67191_panel { + compatible = "raydium,rm67191"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mipi_dsi_en>; + reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + video-mode = <2>; /* 0: burst mode + * 1: non-burst mode with sync event + * 2: non-burst mode with sync pulse + */ + panel-width-mm = <68>; + panel-height-mm = <121>; + status = "okay"; + + port { + rm67191_from_dsim: endpoint { + remote-endpoint = <&dsim_to_rm67191>; + }; + }; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; }; }; @@ -74,6 +136,26 @@ status = "okay"; }; +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + eee-broken-1000t; + }; + }; +}; + &flexcan2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; @@ -97,7 +179,200 @@ compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; eee-broken-1000t; - reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: mt25qu256aba@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + adv_bridge: adv7535@3d { + compatible = "adi,adv7533"; + reg = <0x3d>; + adi,addr-cec = <0x3c>; + adi,dsi-lanes = <4>; + status = "okay"; + + port { + adv7535_from_dsim: endpoint { + remote-endpoint = <&dsim_to_adv7535>; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca6416: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&lcdif1 { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + }; + }; + + port@2 { + dsim_to_rm67191: endpoint { + remote-endpoint = <&rm67191_from_dsim>; }; }; }; @@ -127,9 +402,29 @@ status = "okay"; }; +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + &usdhc2 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; - assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; @@ -141,8 +436,6 @@ }; &usdhc3 { - assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; - assigned-clock-rates = <400000000>; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>; @@ -160,6 +453,28 @@ }; &iomuxc { + pinctrl-names = "default"; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 + >; + }; + pinctrl_fec: fecgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 @@ -206,20 +521,90 @@ >; }; + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 - MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 >; }; - pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c3 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c3 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c3 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c3 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c3 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c3 + >; + }; + + pinctrl_mipi_dsi_en: mipi_dsi_en { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x16 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + >; + }; + + pinctrl_typec: typec1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + >; + }; + + pinctrl_typec_mux: typec1muxgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 >; @@ -232,6 +617,12 @@ >; }; + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 @@ -324,7 +715,7 @@ pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 >; }; }; diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi index ecccfbb4f5a..82f671ab9cc 100644 --- a/arch/arm/dts/imx8mp.dtsi +++ b/arch/arm/dts/imx8mp.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -18,6 +19,7 @@ aliases { ethernet0 = &fec; + ethernet1 = &eqos; gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; @@ -36,6 +38,10 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; + usb0 = &usb_dwc3_0; + usb1 = &usb_dwc3_1; + spi0 = &flexspi; + video0 = &lcdif1; }; cpus { @@ -91,6 +97,16 @@ }; }; + gic: interrupt-controller@38800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */ + <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */ + #interrupt-cells = <3>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + }; + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; @@ -133,10 +149,200 @@ clock-output-names = "clk_ext4"; }; + busfreq { /* BUSFREQ */ + compatible = "fsl,imx_busfreq"; + clocks = <&clk IMX8MP_DRAM_PLL_OUT>, <&clk IMX8MP_CLK_DRAM_ALT>, + <&clk IMX8MP_CLK_DRAM_APB>, <&clk IMX8MP_CLK_DRAM_APB>, + <&clk IMX8MP_CLK_DRAM_CORE>, <&clk IMX8MP_CLK_DRAM_ALT_ROOT>, + <&clk IMX8MP_SYS_PLL1_40M>, <&clk IMX8MP_SYS_PLL1_100M>, + <&clk IMX8MP_SYS_PLL2_333M>, <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_AHB>, <&clk IMX8MP_CLK_MAIN_AXI>, + <&clk IMX8MP_CLK_24M>, <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_DRAM_PLL>; + clock-names = "dram_pll", "dram_alt_src", "dram_apb_src", "dram_apb_pre_div", + "dram_core", "dram_alt_root", "sys_pll1_40m", "sys_pll1_100m", + "sys_pll2_333m", "noc_div", "ahb_div", "main_axi_src", "osc_24m", + "sys_pll1_800m", "dram_pll_div"; + }; + + power-domains { + compatible = "simple-bus"; + + /* HSIO SS */ + hsiomix_pd: hsiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + active-wakeup; + rpm-always-on; + #power-domain-cells = <0>; + domain-index = <0>; + domain-name = "hsiomix"; + }; + + pcie_pd: pcie-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <1>; + domain-name = "pcie"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg1_pd: usbotg1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <2>; + domain-name = "usb_otg1"; + parent-domains = <&hsiomix_pd>; + }; + + usb_otg2_pd: usbotg2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <3>; + domain-name = "usb_otg2"; + parent-domains = <&hsiomix_pd>; + }; + + /* MLMIX */ + mlmix_pd: mlmix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <4>; + domain-name = "mlmix"; + clocks = <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>, + <&clk IMX8MP_CLK_NPU_ROOT>; + }; + + audiomix_pd: audiomix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <5>; + domain-name = "audiomix"; + clocks = <&clk IMX8MP_CLK_AUDIO_AHB_ROOT>, + <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; + }; + + gpumix_pd: gpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "gpumix"; + clocks = <&clk IMX8MP_CLK_GPU_ROOT>, <&clk IMX8MP_CLK_GPU_AHB>, + <&clk IMX8MP_CLK_GPU_AXI>; + }; + + gpu2d_pd: gpu2d-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <7>; + domain-name = "gpu2d"; + parent-domains = <&gpumix_pd>; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; + }; + + gpu3d_pd: gpu3d-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <8>; + domain-name = "gpu3d"; + parent-domains = <&gpumix_pd>; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; + }; + + vpumix_pd: vpumix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <9>; + domain-name = "vpumix"; + clocks =<&clk IMX8MP_CLK_VPU_ROOT>; + }; + + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <10>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; + }; + + vpu_g2_pd: vpug2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <11>; + domain-name = "vpu_g2"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; + }; + + vpu_h1_pd: vpuh1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <12>; + domain-name = "vpu_h1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; + }; + + mediamix_pd: mediamix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <13>; + domain-name = "mediamix"; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + }; + + ispdwp_pd: power-domain@14 { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <14>; + domain-name = "ispdwp"; + parent-domains = <&mediamix_pd>; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP>; + }; + + mipi_phy1_pd: mipiphy1-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <15>; + domain-name = "mipi_phy1"; + parent-domains = <&mediamix_pd>; + }; + + mipi_phy2_pd: mipiphy2-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <16>; + domain-name = "mipi_phy2"; + parent-domains = <&mediamix_pd>; + }; + + hdmimix_pd: hdmimix-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <17>; + domain-name = "hdmimix"; + clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, + <&clk IMX8MP_CLK_HDMI_APB>, + <&clk IMX8MP_CLK_HDMI_REF_266M>; + }; + + hdmi_phy_pd: hdmiphy-pd { + compatible = "fsl,imx8m-pm-domain"; + #power-domain-cells = <0>; + domain-index = <18>; + domain-name = "hdmi_phy"; + parent-domains = <&hdmimix_pd>; + }; + }; + pmu { - compatible = "arm,cortex-a53-pmu"; + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&gic>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>; }; @@ -209,12 +415,13 @@ timer { compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; + interrupts = , + , + , + ; clock-frequency = <8000000>; arm,no-tick-in-suspend; + interrupt-parent = <&gic>; }; soc@0 { @@ -223,6 +430,11 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x3e000000>; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + aips1: bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -292,7 +504,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 114 30>; }; tmu: tmu@30260000 { @@ -316,7 +527,8 @@ }; gpr: iomuxc-gpr@30340000 { - compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; + compatible = "fsl,imx8mp-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x30340000 0x10000>; }; @@ -339,6 +551,22 @@ reg = <0x30360000 0x10000>; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; + clock-names = "ipg"; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -382,7 +610,8 @@ <&clk IMX8MP_CLK_AUDIO_AXI_SRC>, <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MP_AUDIO_PLL1>, - <&clk IMX8MP_AUDIO_PLL2>; + <&clk IMX8MP_AUDIO_PLL2>, + <&clk IMX8MP_VIDEO_PLL1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_ARM_PLL_OUT>, <&clk IMX8MP_SYS_PLL2_1000M>, @@ -398,7 +627,8 @@ <800000000>, <400000000>, <393216000>, - <361267200>; + <361267200>, + <1039500000>; }; src: reset-controller@30390000 { @@ -485,6 +715,9 @@ clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, <&clk IMX8MP_CLK_ECSPI1_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -499,6 +732,9 @@ clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, <&clk IMX8MP_CLK_ECSPI2_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -513,6 +749,9 @@ clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, <&clk IMX8MP_CLK_ECSPI3_ROOT>; clock-names = "ipg", "per"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; dma-names = "rx", "tx"; status = "disabled"; @@ -562,8 +801,8 @@ assigned-clocks = <&clk IMX8MP_CLK_CAN1>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&gpr 0x10 4>; + fsl,clk-source= <0>; + fsl,stop-mode = <&gpr 0x10 4 0x10 20>; status = "disabled"; }; @@ -577,8 +816,8 @@ assigned-clocks = <&clk IMX8MP_CLK_CAN2>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; assigned-clock-rates = <40000000>; - fsl,clk-source = /bits/ 8 <0>; - fsl,stop-mode = <&gpr 0x10 5>; + fsl,clk-source= <0>; + fsl,stop-mode = <&gpr 0x10 5 0x10 21>; status = "disabled"; }; @@ -597,6 +836,7 @@ compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = ; + status = "disabled"; }; sec_jr1: jr@2000 { @@ -692,6 +932,15 @@ status = "disabled"; }; + flexspi_nand: flexspi_nand@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-fspi-nand"; + reg = <0 0x30bb0000 0 0x10000>, <0 0x08000000 0 0x10000000>; + reg-names = "FlexSPI", "FlexSPI-memory"; + status = "disabled"; + }; + usdhc1: mmc@30b40000 { compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; @@ -700,6 +949,8 @@ <&clk IMX8MP_CLK_NAND_USDHC_BUS>, <&clk IMX8MP_CLK_USDHC1_ROOT>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; + assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -714,6 +965,8 @@ <&clk IMX8MP_CLK_NAND_USDHC_BUS>, <&clk IMX8MP_CLK_USDHC2_ROOT>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; @@ -728,12 +981,29 @@ <&clk IMX8MP_CLK_NAND_USDHC_BUS>, <&clk IMX8MP_CLK_USDHC3_ROOT>; clock-names = "ipg", "ahb", "per"; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step= <2>; bus-width = <4>; status = "disabled"; }; + flexspi: spi@30bb0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mm-fspi"; + reg = <0x30bb0000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, + <&clk IMX8MP_CLK_QSPI_ROOT>; + clock-names = "fspi", "fspi_en"; + assigned-clock-rates = <80000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + status = "disabled"; + }; + sdma1: dma-controller@30bd0000 { compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; reg = <0x30bd0000 0x10000>; @@ -762,25 +1032,105 @@ assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, <&clk IMX8MP_CLK_ENET_TIMER>, <&clk IMX8MP_CLK_ENET_REF>, - <&clk IMX8MP_CLK_ENET_TIMER>; + <&clk IMX8MP_CLK_ENET_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, <&clk IMX8MP_SYS_PLL2_100M>, - <&clk IMX8MP_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <0>, <125000000>, <100000000>; + <&clk IMX8MP_SYS_PLL2_125M>, + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; status = "disabled"; }; + + eqos: ethernet@30bf0000 { + compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x30bf0000 0x10000>; + interrupts = , + ; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, + <&clk IMX8MP_CLK_QOS_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <100000000>, <125000000>; + intf_mode = <&gpr 0x4>; + status = "disabled"; + }; }; - gic: interrupt-controller@38800000 { - compatible = "arm,gic-v3"; - reg = <0x38800000 0x10000>, - <0x38880000 0xc0000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = ; - interrupt-parent = <&gic>; + aips4: bus@32c00000 { + compatible = "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mipi_dsi: mipi_dsi@32e60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-mipi-dsim"; + reg = <0x32e60000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + assigned-clock-rates = <594000000>; + interrupts = ; + power-domains = <&mipi_phy1_pd>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + + lcdif1: lcd-controller@32e80000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mp-lcdif1"; + reg = <0x32e80000 0x10000>; + clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "pix", "disp-axi", "disp-apb"; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <594000000>, <500000000>, <200000000>; + interrupts = ; + blk-ctl = <&mediamix_blk_ctl>; + power-domains = <&mediamix_pd>; + status = "disabled"; + + lcdif_disp0: port@0 { + reg = <0>; + + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mediamix_blk_ctl: blk-ctl@32ec0000 { + compatible = "fsl,imx8mp-mediamix-blk-ctl", + "syscon"; + reg = <0x32ec0000 0x10000>; + }; + }; ddr-pmu@3d800000 { @@ -789,4 +1139,119 @@ interrupts = ; }; }; + + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x0 0x32f00000 0x0 0x10000>; + clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + status = "disabled"; + }; + + hsio_mix: hsio-mix@32f10000 { + compatible = "fsl,imx8mp-hsio-mix"; + reg = <0x0 0x32f10000 0x0 0x8>; + }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0 0x33000000 0 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x33002000 0 0x2000>, <0 0x33004000 0 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8MP_CLK_NAND_ROOT>, + <&clk IMX8MP_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + pcie: pcie@33800000 { + compatible = "fsl,imx8mp-pcie", "snps,dw-pcie"; + reg = <0x0 0x33800000 0x0 0x400000>, + <0x0 0x1ff00000 0x0 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x0 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x0 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; + fsl,max-link-speed = <3>; + power-domains = <&pcie_pd>; + resets = <&src IMX8MP_RESET_PCIEPHY>, + <&src IMX8MP_RESET_PCIEPHY_PERST>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_CLK_REQ>, + <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "pciephy_perst", "apps", "clkreq", "turnoff"; + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + fsl,imx8mp-hsio-mix = <&hsio_mix>; + status = "disabled"; + }; + + usb_dwc3_0: usb@38100000 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + reg = <0x0 0x38100000 0x0 0x10000>; + interrupts = ; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + usb3-resume-missing-cas; + snps,power-down-scale = <2>; + status = "disabled"; + }; + + usb3_phy0: usb-phy@381f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x0 0x381f0040 0x0 0x40>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb_dwc3_1: usb@38200000 { + compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + reg = <0x0 0x38200000 0x0 0x10000>; + interrupts = ; + phys = <&usb3_phy1>, <&usb3_phy1>; + phy-names = "usb2-phy", "usb3-phy"; + usb3-resume-missing-cas; + snps,power-down-scale = <2>; + status = "disabled"; + }; + + usb3_phy1: usb-phy@382f0040 { + compatible = "fsl,imx8mq-usb-phy"; + reg = <0x0 0x382f0040 0x0 0x40>; + #phy-cells = <0>; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/imx8mq-ddr3l-val.dts b/arch/arm/dts/imx8mq-ddr3l-val.dts new file mode 100644 index 00000000000..38c948b678d --- /dev/null +++ b/arch/arm/dts/imx8mq-ddr3l-val.dts @@ -0,0 +1,484 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model = "NXP i.MX8MQ DDR3L VAL"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: audio-codec { + #sound-dai-cells = <0>; + compatible = "wlf,wm8524"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-val { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56 + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x56 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER 0x56 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x56 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x56 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f + MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f + MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_qspi: qspigrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK 0x82 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x82 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x82 + MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x82 + MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x82 + MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x82 + + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x79 + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x79 + MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x79 + MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x79 + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&qspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi>; + num-cs =<2>; + status = "okay"; + + flash0: gd25q16@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; + + flash1: gd25q16@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <29000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +}; + +&uart3 { /* BT */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MQ_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; + fsl,uart-has-rtscts; + resets = <&modem_reset>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/dts/imx8mq-ddr4-val.dts b/arch/arm/dts/imx8mq-ddr4-val.dts new file mode 100644 index 00000000000..dd62a995b56 --- /dev/null +++ b/arch/arm/dts/imx8mq-ddr4-val.dts @@ -0,0 +1,447 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + */ + +/dts-v1/; + +#include "imx8mq.dtsi" + +/ { + model = "NXP i.MX8MQ DDR4 VAL"; + compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; + + chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; + stdout-path = &uart1; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; + enable-active-high; + }; + }; + + modem_reset: modem-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; + reset-delay-us = <2000>; + reset-post-delay-ms = <40>; + #reset-cells = <0>; + }; + + wm8524: audio-codec { + #sound-dai-cells = <0>; + compatible = "wlf,wm8524"; + wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + pwmleds { + compatible = "pwm-leds"; + + ledpwm2 { + label = "PWM2"; + pwms = <&pwm2 0 50000>; + max-brightness = <255>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + imx8mq-val { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f + MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f + MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x79 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 + MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 + MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 + MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 + MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 + MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 + MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 + MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 + MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 + MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 + MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 + MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 + MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 + MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 + MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 + >; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + at803x,led-act-blind-workaround; + at803x,eee-disabled; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pfuze100@8 { + compatible = "fsl,pfuze100"; + reg = <0x8>; + + regulators { + sw1a_reg: sw1ab { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw1c_reg: sw1c { + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sw3a_reg: sw3ab { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1975000>; + regulator-always-on; + }; + + sw4_reg: sw4 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-always-on; + }; + + vgen1_reg: vgen1 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen2_reg: vgen2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: vgen4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vgen5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vgen6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand_1>; + status = "okay"; + nand-on-flash-bbt; +}; diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi b/arch/arm/dts/imx8mq-evk-u-boot.dtsi index 2cfc12b7e0a..523c713f0a0 100644 --- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi @@ -8,3 +8,16 @@ sd-uhs-sdr104; sd-uhs-ddr50; }; + +&fec1 { + phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; +}; + +ðphy0 { + vddio0: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; \ No newline at end of file diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts index 85b045253a0..de709088e51 100644 --- a/arch/arm/dts/imx8mq-evk.dts +++ b/arch/arm/dts/imx8mq-evk.dts @@ -13,9 +13,17 @@ compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; chosen { + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; stdout-path = &uart1; }; + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + memory@40000000 { device_type = "memory"; reg = <0x00000000 0x40000000 0 0xc0000000>; @@ -35,6 +43,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <20000>; enable-active-high; }; @@ -169,6 +178,7 @@ reg = <0>; reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; reset-assert-us = <10000>; + at803x,eee-disabled; }; }; }; @@ -186,12 +196,16 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; status = "okay"; pmic@8 { compatible = "fsl,pfuze100"; + fsl,pfuze-support-disable-sw; reg = <0x8>; regulators { @@ -309,6 +323,16 @@ }; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; @@ -318,6 +342,7 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + hard-wired = <1>; status = "okay"; }; @@ -330,12 +355,15 @@ pinctrl-0 = <&pinctrl_qspi>; status = "okay"; - n25q256a: flash@0 { + flash0: n25q256a@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; - compatible = "micron,n25q256a", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; spi-max-frequency = <29000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-nor,ddr-quad-read-dummy = <6>; }; }; @@ -371,6 +399,23 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clk IMX8MQ_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; status = "okay"; }; @@ -417,7 +462,47 @@ status = "okay"; }; +&dcss { + status = "okay"; + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; +}; + +&hdmi { + compatible = "fsl,imx8mq-hdmi"; + status = "okay"; + + display-timings { + native-mode = <&timing1>; + + timing1: timing1 { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hfront-porch = <110>; + hback-porch = <220>; + hsync-len = <40>; + vback-porch = <20>; + vfront-porch = <5>; + vsync-len = <5>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port@0 { + hdmi_in: endpoint { + remote-endpoint = <&dcss_out>; + }; + }; +}; + &iomuxc { + pinctrl-names = "default"; + pinctrl_buck2: vddarmgrp { fsl,pins = < MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 @@ -464,6 +549,27 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14 0x7f + MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15 0x7f + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16 0x7f + MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17 0x7f + >; + }; + pinctrl_pcie0: pcie0grp { fsl,pins = < MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 @@ -485,6 +591,7 @@ pinctrl_reg_usdhc2: regusdhc2gpiogrp { fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 >; }; @@ -506,6 +613,18 @@ >; }; + pinctrl_ss_sel: usb3ssgrp{ + fsl,pins = < + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi index a841a023e8e..0ed72c382c8 100644 --- a/arch/arm/dts/imx8mq.dtsi +++ b/arch/arm/dts/imx8mq.dtsi @@ -36,9 +36,9 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; - spi0 = &ecspi1; - spi1 = &ecspi2; - spi2 = &ecspi3; + usb0 = &usb_dwc3_0; + usb1 = &usb_dwc3_1; + spi0 = &qspi0; }; ckil: clock-ckil { @@ -204,7 +204,7 @@ cpu_thermal: cpu-thermal { polling-delay-passive = <250>; polling-delay = <2000>; - thermal-sensors = <&tmu 0>; + thermal-sensors = <&tmu>; trips { cpu_alert: cpu-alert { @@ -231,48 +231,6 @@ }; }; }; - - gpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 1>; - - trips { - gpu_alert: gpu-alert { - temperature = <80000>; - hysteresis = <2000>; - type = "passive"; - }; - - gpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&gpu_alert>; - cooling-device = - <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - vpu-thermal { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tmu 2>; - - trips { - vpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - }; }; timer { @@ -292,6 +250,11 @@ ranges = <0x0 0x0 0x0 0x3e000000>; dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x8000>; + }; + bus@30000000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; reg = <0x30000000 0x400000>; @@ -426,6 +389,7 @@ interrupts = ; clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; little-endian; + u-boot,dm-pre-reloc; fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; fsl,tmu-calibration = <0x00000000 0x00000023 0x00000001 0x00000029 @@ -470,7 +434,7 @@ 0x00030005 0x00000053 0x00030006 0x0000005f 0x00030007 0x00000071>; - #thermal-sensor-cells = <1>; + #thermal-sensor-cells = <0>; }; wdog1: watchdog@30280000 { @@ -558,6 +522,10 @@ cpu_speed_grade: speed-grade@10 { reg = <0x10 4>; }; + + fec_mac_address: mac-address@640 { + reg = <0x90 6>; + }; }; anatop: syscon@30360000 { @@ -566,6 +534,20 @@ interrupts = ; }; + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = ; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + snvs: snvs@30370000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x30370000 0x10000>; @@ -606,25 +588,20 @@ "clk_ext3", "clk_ext4"; assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, <&clk IMX8MQ_CLK_A53_CORE>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, <&clk IMX8MQ_CLK_NOC>, <&clk IMX8MQ_CLK_AUDIO_AHB>, - <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, - <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; - assigned-clock-rates = <0>, <0>, - <800000000>, - <0>, - <0>, - <0>, + assigned-clock-rates = <0>, <0>, <266000000>, + <800000000>, <0>, <786432000>, <722534400>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_ARM_PLL_OUT>, <0>, - <&clk IMX8MQ_SYS2_PLL_500M>, - <&clk IMX8MQ_AUDIO_PLL1>, - <&clk IMX8MQ_AUDIO_PLL2>; + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS2_PLL_500M>; }; src: reset-controller@30390000 { @@ -975,14 +952,20 @@ <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>, <&clk IMX8MQ_CLK_DSI_PHY_REF>, + <&clk IMX8MQ_VIDEO_PLL1>, <&clk IMX8MQ_CLK_LCDIF_PIXEL>; - clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; - assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, + clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "video_pll", "lcdif"; + assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>, <&clk IMX8MQ_CLK_DSI_CORE>, + <&clk IMX8MQ_CLK_DSI_AHB>, <&clk IMX8MQ_CLK_DSI_IPG_DIV>; - assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, - <&clk IMX8MQ_SYS1_PLL_266M>; - assigned-clock-rates = <80000000>, <266000000>, <20000000>; + assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>, + <&clk IMX8MQ_SYS1_PLL_266M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <27000000>, + <266000000>, + <80000000>, + <20000000>; interrupts = ; mux-controls = <&mux 0>; power-domains = <&pgc_mipi>; @@ -1154,6 +1137,11 @@ "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; fsl,num-rx-queues = <3>; + nvmem-cells = <&fec_mac_address>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + stop-mode = <&iomuxc_gpr 0x10 3>; + fsl,wakeup_irq = <2>; status = "disabled"; }; }; @@ -1165,6 +1153,14 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + hdmi: hdmi@32c00000 { + reg = <0x32c00000 0x100000>, + <0x32e40000 0x40000>; + interrupts = , + ; + interrupt-names = "plug_in", "plug_out"; + }; + irqsteer: interrupt-controller@32e2d000 { compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; reg = <0x32e2d000 0x1000>; @@ -1176,6 +1172,35 @@ interrupt-controller; #interrupt-cells = <1>; }; + + dcss: display-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>, <16>, <17>; + interrupt-names = "ctx_ld", "ctxld_kick", "vblank", + "dtrc_ch1", "dtrc_ch2"; + interrupt-parent = <&irqsteer>; + clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, + <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, + <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, + <&clk IMX8MQ_VIDEO2_PLL_OUT>, + <&clk IMX8MQ_CLK_DISP_DTRC>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>, + <&clk IMX8MQ_CLK_PHY_27MHZ>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", "pll_src", + "pll_phy_ref"; + assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, + <&clk IMX8MQ_CLK_DISP_RTRM>, + <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>; + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_CLK_27M>; + assigned-clock-rates = <800000000>, + <400000000>; + status = "disabled"; + }; }; gpu: gpu@38000000 { @@ -1201,10 +1226,11 @@ assigned-clock-rates = <800000000>, <800000000>, <800000000>, <800000000>, <0>; power-domains = <&pgc_gpu>; + status = "disabled"; }; usb_dwc3_0: usb@38100000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + compatible = "fsl,imx8mq-dwc3"; reg = <0x38100000 0x10000>; clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, <&clk IMX8MQ_CLK_USB_CORE_REF>, @@ -1220,6 +1246,7 @@ phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg1>; usb3-resume-missing-cas; + snps,power-down-scale = <2>; status = "disabled"; }; @@ -1236,7 +1263,7 @@ }; usb_dwc3_1: usb@38200000 { - compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; + compatible = "fsl,imx8mq-dwc3"; reg = <0x38200000 0x10000>; clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, <&clk IMX8MQ_CLK_USB_CORE_REF>, @@ -1252,6 +1279,7 @@ phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg2>; usb3-resume-missing-cas; + snps,power-down-scale = <2>; status = "disabled"; }; @@ -1267,30 +1295,33 @@ status = "disabled"; }; - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = , - ; - interrupt-names = "g1", "g2"; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, - <&clk IMX8MQ_CLK_VPU_G2>, - <&clk IMX8MQ_CLK_VPU_BUS>, - <&clk IMX8MQ_VPU_PLL_BYPASS>; - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_VPU_PLL_OUT>, - <&clk IMX8MQ_SYS1_PLL_800M>, - <&clk IMX8MQ_VPU_PLL>; - assigned-clock-rates = <600000000>, <600000000>, - <800000000>, <0>; - power-domains = <&pgc_vpu>; + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = , + , + , + ; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = ; + interrupt-names = "bch"; + clocks = <&clk IMX8MQ_CLK_RAWNAND_ROOT>, + <&clk IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; }; pcie0: pcie@33800000 { @@ -1306,8 +1337,9 @@ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, @@ -1335,8 +1367,9 @@ 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; num-viewport = <4>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; /* eDMA */ + interrupt-names = "msi", "dma"; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0x7>; interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, @@ -1381,5 +1414,20 @@ interrupt-parent = <&gic>; interrupts = ; }; + + vpu: vpu@38300000 { + compatible = "nxp,imx8mq-hantro"; + reg = <0x38300000 0x200000>; + reg-names = "regs_hantro"; + interrupts = , ; + interrupt-names = "irq_hantro_g1", "irq_hantro_g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, <&clk IMX8MQ_CLK_VPU_G2_ROOT>, <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "clk_hantro_g1", "clk_hantro_g2", "clk_hantro_bus"; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, <&clk IMX8MQ_CLK_VPU_G2>, <&clk IMX8MQ_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_VPU_PLL_OUT>, <&clk IMX8MQ_SYS1_PLL_800M>; + assigned-clock-rates = <600000000>, <600000000>, <800000000>; + power-domains = <&pgc_vpu>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/iot-gate-imx8.dts b/arch/arm/dts/iot-gate-imx8.dts new file mode 100644 index 00000000000..6b6b2d69c73 --- /dev/null +++ b/arch/arm/dts/iot-gate-imx8.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2020 CompuLab + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "cpl-imx8m-mini.dtsi" + +/ { + model = "CompuLab IOT-GATE-iMX8"; + compatible = "sb-iotgimx8", "cpl,ucm-imx8m-mini", "fsl,imx8mm-evk", "fsl,imx8mm"; + + reg_vusb_5v: regulator-usdhc2 { + compatible = "regulator-fixed"; + regulator-name = "VUSB_5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctl_usb_gpio>; + dr_mode = "host"; + status = "okay"; +}; + +&iomuxc { + sb-iotgimx8 { + pinctl_usb_gpio: usb_gpio_grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x00 + >; + }; + }; +}; diff --git a/arch/arm/dts/iot-gate-imx8plus-u-boot.dtsi b/arch/arm/dts/iot-gate-imx8plus-u-boot.dtsi new file mode 100644 index 00000000000..f42cf95e4e1 --- /dev/null +++ b/arch/arm/dts/iot-gate-imx8plus-u-boot.dtsi @@ -0,0 +1,198 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2022 CompuLab + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + +}; + +&osc_32k { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_usb_hub_rst { + u-boot,dm-spl; +}; + +&pinctrl_usb2_vbus { + u-boot,dm-spl; +}; + +&pinctrl_usb_mux_sel { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&i2c5 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_i2c2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c3_gpio { + u-boot,dm-spl; +}; + +&pinctrl_i2c5 { + u-boot,dm-spl; +}; + +&pinctrl_i2c5_gpio { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&flexspi { + assigned-clock-rates = <100000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_100M>; +}; diff --git a/arch/arm/dts/iot-gate-imx8plus.dts b/arch/arm/dts/iot-gate-imx8plus.dts new file mode 100644 index 00000000000..598fec8d7cc --- /dev/null +++ b/arch/arm/dts/iot-gate-imx8plus.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 CompuLab + */ + +#include "ucm-imx8m-plus.dtsi" +#include "sb-iotgimx8plus.dtsi" + +/ { + model = "CompuLab IOT-GATE-IMX8PLUS"; + compatible = "compulab,iot-gate-imx8plus", "compulab,ucm-imx8m-plus-som", "fsl,imx8mp"; +}; diff --git a/arch/arm/dts/iotdin-imx8p-u-boot.dtsi b/arch/arm/dts/iotdin-imx8p-u-boot.dtsi new file mode 100644 index 00000000000..fc1f6a6d27e --- /dev/null +++ b/arch/arm/dts/iotdin-imx8p-u-boot.dtsi @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2024 CompuLab + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + +}; + +&osc_32k { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_usb_hub_rst { + u-boot,dm-spl; +}; + +&pinctrl_usb2_vbus { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&i2c5 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_i2c2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c3_gpio { + u-boot,dm-spl; +}; + +&pca9555_sb { + u-boot,dm-spl; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/iotdin-imx8p.dts b/arch/arm/dts/iotdin-imx8p.dts new file mode 100644 index 00000000000..e3689d26fc0 --- /dev/null +++ b/arch/arm/dts/iotdin-imx8p.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 CompuLab + */ + +#include "ucm-imx8m-plus.dtsi" +#include "sb-iotdimx8p.dtsi" + +/ { + model = "CompuLab IOTDIN-IMX8P"; + compatible = "compulab,iotdin-imx8p", "compulab,iot-gate-imx8plus", "compulab,ucm-imx8m-plus-som", "fsl,imx8mp"; +}; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 7b99ce02b35..204c6e09a38 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -144,6 +144,45 @@ big-endian; }; + crypto: crypto@1700000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <7>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1700000 0x100000>; + ranges = <0x0 0x1700000 0x100000>; + interrupts = ; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = ; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = ; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = ; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = ; + }; + + }; + clockgen: clocking@1ee1000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/mcm-imx8m-mini.dts b/arch/arm/dts/mcm-imx8m-mini.dts new file mode 100644 index 00000000000..060e51793c0 --- /dev/null +++ b/arch/arm/dts/mcm-imx8m-mini.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2018 CompuLab + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "cpl-imx8m-mini.dtsi" + +/ { + model = "CompuLab MCM-iMX8M-Mini board"; + compatible = "cpl,mcm-imx8m-mini", "fsl,imx8mm-evk", "fsl,imx8mm"; +}; diff --git a/arch/arm/dts/mcm-imx8m-plus-u-boot.dtsi b/arch/arm/dts/mcm-imx8m-plus-u-boot.dtsi new file mode 100644 index 00000000000..9186cbe4dff --- /dev/null +++ b/arch/arm/dts/mcm-imx8m-plus-u-boot.dtsi @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2021 CompuLab + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + +}; + +&osc_32k { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_gpio4_20_hog { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_i2c2_gpio { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&flexspi { + assigned-clock-rates = <100000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_100M>; +}; + +&lcdif1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/mcm-imx8m-plus.dts b/arch/arm/dts/mcm-imx8m-plus.dts new file mode 100644 index 00000000000..e2450494edc --- /dev/null +++ b/arch/arm/dts/mcm-imx8m-plus.dts @@ -0,0 +1,717 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 CompuLab + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "CompuLab MCM-iMX8M-Plus"; + compatible = "compulab,mcm-imx8m-plus", "fsl,imx8mp"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 console=tty0"; + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>, + <0x1 0x00000000 0 0x00000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + default-state = "on"; /* LED GREEN */ + }; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + dsi_host: dsi-host { + compatible = "samsung,sec-mipi-dsi"; + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 3000000 0>; + + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 + 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 + 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 + 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 + 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 + 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 + 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 + 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 + 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 + 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 + 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 + 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 + 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 + 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 + 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; + default-brightness-level = <222>; + status = "okay"; + }; + + ili9881c_panel { + compatible = "startek,ili9881c"; + reset-gpio = <&pca9555 4 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + panel-width-mm = <63>; + panel-height-mm = <115>; + status = "okay"; + + port { + ili9881c_from_dsim: endpoint { + remote-endpoint = <&ili9881c_to_dsim>; + }; + }; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + eee-broken-1000t; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: w25q64dw@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&gpio4 { + gpio4_20_hog { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4_20_hog>; + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + pagesize = <16>; + }; + + pca9555:pca9555@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&i2c5 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; + status = "disabled"; + +}; + +&lcdif1 { + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + port@1 { + ili9881c_to_dsim: endpoint { + remote-endpoint = <&ili9881c_from_dsim>; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x19 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x19 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + /* gpio */ + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x10 /* WOL */ + MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x10 /* INT */ + MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x10 /* RST */ + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x400001c2 + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x1c2 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1c2 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + pinctrl_typec: typec1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + >; + }; + + pinctrl_gpio4_20_hog: gpio420hoggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x116 + >; + }; +}; + +&cpu_alert0 { + temperature = <125000>; +}; + +&cpu_crit0 { + temperature = <155000>; +}; + +&soc_alert0 { + temperature = <125000>; +}; + +&soc_crit0 { + temperature = <155000>; +}; diff --git a/arch/arm/dts/sb-iotdimx8p.dtsi b/arch/arm/dts/sb-iotdimx8p.dtsi new file mode 100644 index 00000000000..4212af12fc9 --- /dev/null +++ b/arch/arm/dts/sb-iotdimx8p.dtsi @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 CompuLab + */ + +#include + +/ { + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 console=tty0"; + stdout-path = &uart2; + }; + + leds { + pinctrl-0 = <&pinctrl_gpio_led>, <&pinctrl_user_leds>; + + pled_amber: power-led-abmer { + label = "PowerLED_Amber"; + color = ; + gpios = <&pca9555_sb 7 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + power-led-blue { + label = "PowerLED_Blue"; + color = ; + gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy_reset>; + phy-mode = "rgmii-id"; + phy-handle = <&fecphy>; + phy-reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + fecphy: fec-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&gpio2 { + usb_hub_reset { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub_rst>; + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "usb_hub_reset"; + output-high; + }; +}; + +&gpio4 { + usb_vbus_ena { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2_vbus>; + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + line-name = "usb2_host_vbus"; + output-high; + }; +}; + +&i2c3 { + status = "okay"; + + pca9555_sb: pca9555-sb@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + + gpio-line-names = + "WLAN_PDn", "ULED2_GREEN", "ULED1_GREEN", "ULED2_RED", + "ULED1_RED", "MODEM_RSTn", "RF_KILLn", "LED_AMBR_CNTL", + "PWR_EN", "USB_RESET1", "USB_RESET2", "USB_RESET3", + "B2B_GPIO0", "B2B_GPIO1", "B2B_GPIO2", "B2B_GPIO3"; + }; + + eeprom_sb: eeprom-sb@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; + +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&cpu_alert0 { + temperature = <100000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + +&soc_alert0 { + temperature = <100000>; +}; + +&soc_crit0 { + temperature = <105000>; +}; + +&iomuxc { + pinctrl_fec_phy_reset: fecphyrstgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x10 + >; + }; + + pinctrl_usb_hub_rst: usbhubrstgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x100 + >; + }; + + pinctrl_usb2_vbus: usb2vbusgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x154 + >; + }; + + pinctrl_user_leds: userledsgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x140 + >; + }; +}; diff --git a/arch/arm/dts/sb-iotgimx8plus.dtsi b/arch/arm/dts/sb-iotgimx8plus.dtsi new file mode 100644 index 00000000000..c7090a30f9c --- /dev/null +++ b/arch/arm/dts/sb-iotgimx8plus.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 CompuLab + */ + +/ { + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 console=tty0"; + stdout-path = &uart2; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>, <&pinctrl_fec_phy_reset>; + phy-mode = "rgmii-id"; + phy-handle = <&fecphy>; + phy-reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + fecphy: fec-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&gpio1 { + sd_vsel_m2emmc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_gpio>; + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + line-name = "sd-vsel-m2emmc"; + output-low; + }; +}; + +&gpio2 { + usb_hub_reset { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub_rst>; + gpio-hog; + gpios = <10 GPIO_ACTIVE_HIGH>; + line-name = "usb_hub_reset"; + output-high; + }; +}; + +&gpio4 { + usb_vbus_ena { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2_vbus>; + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + line-name = "usb2_host_vbus"; + output-high; + }; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_mux_sel>; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&cpu_alert0 { + temperature = <100000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + +&soc_alert0 { + temperature = <100000>; +}; + +&soc_crit0 { + temperature = <105000>; +}; + +&iomuxc { + pinctrl_fec_phy_reset: fecphyrstgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x10 + >; + }; + + pinctrl_usb_hub_rst: usbhubrstgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x100 + >; + }; + + pinctrl_usb_mux_sel: usbmuxselgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x114 + >; + }; + + pinctrl_usb2_vbus: usb2vbusgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x154 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x100 + >; + }; +}; diff --git a/arch/arm/dts/som-imx8m-plus-u-boot.dtsi b/arch/arm/dts/som-imx8m-plus-u-boot.dtsi new file mode 100644 index 00000000000..0c2737338e0 --- /dev/null +++ b/arch/arm/dts/som-imx8m-plus-u-boot.dtsi @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2021 CompuLab + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + +}; + +&osc_32k { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; + u-boot,off-on-delay-us = <20000>; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_i2c2_gpio { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + + phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&fec { + phy-reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + phy-reset-duration = <15>; + phy-reset-post-delay = <100>; +}; + +&flexspi { + assigned-clock-rates = <100000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_100M>; +}; + +&lcdif1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/som-imx8m-plus.dts b/arch/arm/dts/som-imx8m-plus.dts new file mode 100644 index 00000000000..fa3c6a59ba7 --- /dev/null +++ b/arch/arm/dts/som-imx8m-plus.dts @@ -0,0 +1,753 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 CompuLab + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "CompuLab SOM-iMX8M-Plus"; + compatible = "compulab,som-imx8m-plus", "fsl,imx8mp"; + + chosen { + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200"; + stdout-path = &uart2; + }; + + aliases { + ethphy0 = ðphy0; + ethphy1 = ðphy1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>, + <0x1 0x00000000 0 0x00000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + default-state = "on"; /* LED GREEN */ + }; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + reg_3v3_exp: regulator-3v3-exp { + compatible = "regulator-fixed"; + regulator-name = "3V3_EXP"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_3v3_exp>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + dsi_host: dsi-host { + compatible = "samsung,sec-mipi-dsi"; + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 3000000 0>; + + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 + 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 + 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 + 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 + 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 + 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 + 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 + 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 + 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 + 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 + 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 + 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 + 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 + 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 + 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; + default-brightness-level = <222>; + status = "okay"; + }; + + ili9881c_panel { + compatible = "startek,ili9881c"; + reset-gpio = <&pca9555 4 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + panel-width-mm = <63>; + panel-height-mm = <115>; + status = "okay"; + + port { + ili9881c_from_dsim: endpoint { + remote-endpoint = <&ili9881c_to_dsim>; + }; + }; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + eee-broken-1000t; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + fsl,magic-packet; + phy-reset-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: w25q128dw@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; + + rtc@69 { + compatible = "ab1805"; + reg = <0x69>; + pagesize = <16>; + status = "okay"; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pca9555:pca9555@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + pagesize = <16>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&i2c5 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; + status = "disabled"; + +}; + +&lcdif1 { + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + port@1 { + ili9881c_to_dsim: endpoint { + remote-endpoint = <&ili9881c_from_dsim>; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x16 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x16 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 + MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x16 + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x16 + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x16 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x400001c2 + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x1c2 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x1c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x1c2 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1c2 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + pinctrl_typec: typec1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + >; + }; + + pinctrl_typec_mux: typec1muxgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10 + >; + }; + + pinctrl_3v3_exp: exp1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x10 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x116 + >; + }; +}; + +&cpu_alert0 { + temperature = <125000>; +}; + +&cpu_crit0 { + temperature = <155000>; +}; + +&soc_alert0 { + temperature = <125000>; +}; + +&soc_crit0 { + temperature = <155000>; +}; diff --git a/arch/arm/dts/ucm-imx8m-mini.dts b/arch/arm/dts/ucm-imx8m-mini.dts new file mode 100644 index 00000000000..7b81e8a75b9 --- /dev/null +++ b/arch/arm/dts/ucm-imx8m-mini.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2018 CompuLab + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +#include "cpl-imx8m-mini.dtsi" + +/ { + model = "CompuLab UCM-iMX8M-Mini board"; + compatible = "cpl,ucm-imx8m-mini", "fsl,imx8mm-evk", "fsl,imx8mm"; +}; diff --git a/arch/arm/dts/ucm-imx8m-plus-pinctrl.dtsi b/arch/arm/dts/ucm-imx8m-plus-pinctrl.dtsi new file mode 100644 index 00000000000..2ee43e6d3da --- /dev/null +++ b/arch/arm/dts/ucm-imx8m-plus-pinctrl.dtsi @@ -0,0 +1,225 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 CompuLab + */ + +&iomuxc { + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x2 + MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x2 + MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x90 + MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x90 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x16 + MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x16 + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x400001c2 + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x1c2 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1c2 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm/dts/ucm-imx8m-plus-u-boot.dtsi b/arch/arm/dts/ucm-imx8m-plus-u-boot.dtsi new file mode 100644 index 00000000000..9186cbe4dff --- /dev/null +++ b/arch/arm/dts/ucm-imx8m-plus-u-boot.dtsi @@ -0,0 +1,200 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2021 CompuLab + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + u-boot,dm-pre-reloc; + u-boot,dm-spl; +}; + +&clk { + u-boot,dm-spl; + u-boot,dm-pre-reloc; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + +}; + +&osc_32k { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&osc_24m { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-spl; +}; + +&aips3 { + u-boot,dm-spl; +}; + +&iomuxc { + u-boot,dm-spl; +}; + +&pinctrl_reg_usdhc2_vmmc { + u-boot,dm-spl; +}; + +®_usdhc2_vmmc { + u-boot,dm-spl; +}; + +&pinctrl_uart2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2_gpio { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc3 { + u-boot,dm-spl; +}; + +&pinctrl_gpio4_20_hog { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; +}; + +&i2c2 { + u-boot,dm-spl; +}; + +&i2c3 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1_gpio { + u-boot,dm-spl; +}; + +&pinctrl_i2c2 { + u-boot,dm-spl; +}; + +&pinctrl_i2c2_gpio { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; + sd-uhs-sdr104; + sd-uhs-ddr50; + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&usdhc3 { + u-boot,dm-spl; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&eqos { + compatible = "fsl,imx-eqos"; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&flexspi { + assigned-clock-rates = <100000000>; + assigned-clocks = <&clk IMX8MP_CLK_QSPI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_100M>; +}; + +&lcdif1 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; + +&mipi_dsi { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; +}; diff --git a/arch/arm/dts/ucm-imx8m-plus.dts b/arch/arm/dts/ucm-imx8m-plus.dts new file mode 100644 index 00000000000..f45802e5953 --- /dev/null +++ b/arch/arm/dts/ucm-imx8m-plus.dts @@ -0,0 +1,685 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 CompuLab + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" + +/ { + model = "CompuLab UCM-iMX8M-Plus"; + compatible = "compulab,ucm-imx8m-plus", "fsl,imx8mp"; + + chosen { +#ifdef CONFIG_COMPULAB_DEBUG_UART1 + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30860000,115200 console=tty0"; + stdout-path = &uart1; +#else + bootargs = "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 console=tty0"; + stdout-path = &uart2; +#endif + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>, + <0x1 0x00000000 0 0x00000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + default-state = "on"; /* LED GREEN */ + }; + }; + + reg_usb1_host_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_host_vbus"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <100>; + off-on-delay-us = <12000>; + }; + + dsi_host: dsi-host { + compatible = "samsung,sec-mipi-dsi"; + status = "okay"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm2 0 3000000 0>; + + brightness-levels = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 + 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 + 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 + 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 + 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 + 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 + 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 + 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 + 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 + 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 + 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 + 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 + 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 + 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 + 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255>; + default-brightness-level = <222>; + status = "okay"; + }; + + ili9881c_panel { + compatible = "startek,ili9881c"; + reset-gpio = <&pca9555 4 GPIO_ACTIVE_LOW>; + dsi-lanes = <4>; + panel-width-mm = <63>; + panel-height-mm = <115>; + status = "okay"; + + port { + ili9881c_from_dsim: endpoint { + remote-endpoint = <&ili9881c_to_dsim>; + }; + }; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: w25q64dw@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&gpio4 { + gpio4_20_hog { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio4_20_hog>; + gpio-hog; + gpios = <20 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@54 { + compatible = "atmel,24c08"; + reg = <0x54>; + pagesize = <16>; + }; + + pca9555:pca9555@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&i2c5 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; + status = "disabled"; + +}; + +&lcdif1 { + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; + port@1 { + ili9881c_to_dsim: endpoint { + remote-endpoint = <&ili9881c_from_dsim>; + }; + }; +}; + +&snvs_pwrkey { + status = "okay"; +}; + + +#ifdef CONFIG_COMPULAB_DEBUG_UART1 +&uart1 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; +#else +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; +#endif + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x10 + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x10 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x10 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2 + MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82 + MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82 + MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82 + MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82 + MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x400001c2 + MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x400001c2 + >; + }; + + pinctrl_i2c1_gpio: i2c1grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x1c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x1c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x1c2 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1c2 + >; + }; + + pinctrl_pmic: pmicirq { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0 + >; + }; + + pinctrl_typec: typec1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1c4 + >; + }; + + pinctrl_gpio4_20_hog: gpio420hoggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x16 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_usb1_vbus: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grp-gpio { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x116 + >; + }; +}; + +&cpu_alert0 { + temperature = <125000>; +}; + +&cpu_crit0 { + temperature = <155000>; +}; + +&soc_alert0 { + temperature = <125000>; +}; + +&soc_crit0 { + temperature = <155000>; +}; diff --git a/arch/arm/dts/ucm-imx8m-plus.dtsi b/arch/arm/dts/ucm-imx8m-plus.dtsi new file mode 100644 index 00000000000..97c443b555c --- /dev/null +++ b/arch/arm/dts/ucm-imx8m-plus.dtsi @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 CompuLab + */ + +/dts-v1/; + +#include +#include "imx8mp.dtsi" +#include "ucm-imx8m-plus-pinctrl.dtsi" + +/ { + model = "CompuLab UCM-iMX8M-Plus"; + compatible = "compulab,ucm-imx8m-plus-som", "fsl,imx8mp"; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>, + <0x1 0x00000000 0 0x00000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + status { + label = "status"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + default-state = "on"; /* LED GREEN */ + }; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <&eqosphy>; + phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <150>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eqosphy: eqos-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + eee-broken-1000t; + }; + }; +}; + +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + + flash0: w25q64dw@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450c"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4_reg: regulator@3 { + reg = <3>; + regulator-compatible = "buck4"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5_reg: regulator@4 { + reg = <4>; + regulator-compatible = "buck5"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6_reg: regulator@5 { + reg = <5>; + regulator-compatible = "buck6"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: regulator@6 { + reg = <6>; + regulator-compatible = "ldo1"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: regulator@7 { + reg = <7>; + regulator-compatible = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: regulator@8 { + reg = <8>; + regulator-compatible = "ldo3"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4_reg: regulator@9 { + reg = <9>; + regulator-compatible = "ldo4"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: regulator@10 { + reg = <10>; + regulator-compatible = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +&i2c5 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; + status = "disabled"; + +}; + +&snvs_pwrkey { + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + status = "disabled"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index f37fe214460..1f58b7e3e9f 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018-2020 NXP */ #define MXC_CPU_MX23 0x23 @@ -40,13 +41,17 @@ #define MXC_CPU_IMX8MNL 0x8e /* dummy ID */ #define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */ #define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */ -#define MXC_CPU_IMX8MP 0x182/* dummy ID */ -#define MXC_CPU_IMX8MP6 0x184 /* dummy ID */ -#define MXC_CPU_IMX8MPL 0x186 /* dummy ID */ -#define MXC_CPU_IMX8MPD 0x187 /* dummy ID */ +#define MXC_CPU_IMX8MNUQ 0x182 /* dummy ID */ +#define MXC_CPU_IMX8MNUD 0x183 /* dummy ID */ +#define MXC_CPU_IMX8MNUS 0x184 /* dummy ID */ +#define MXC_CPU_IMX8MP 0x185/* dummy ID */ +#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */ +#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */ +#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ +#define MXC_CPU_IMX8DXL 0x9E /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ @@ -59,15 +64,19 @@ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 #define CHIP_REV_1_2 0x12 +#define CHIP_REV_1_3 0x13 #define CHIP_REV_1_5 0x15 #define CHIP_REV_2_0 0x20 #define CHIP_REV_2_1 0x21 +#define CHIP_REV_2_2 0x22 #define CHIP_REV_2_5 0x25 #define CHIP_REV_3_0 0x30 #define CHIP_REV_A 0x0 #define CHIP_REV_B 0x1 #define CHIP_REV_C 0x2 +#define CHIP_REV_A1 0x11 +#define CHIP_REV_A2 0x12 #define BOARD_REV_1_0 0x0 #define BOARD_REV_2_0 0x1 diff --git a/arch/arm/include/asm/arch-imx8/clock.h b/arch/arm/include/asm/arch-imx8/clock.h index bea157171fb..4435259d610 100644 --- a/arch/arm/include/asm/arch-imx8/clock.h +++ b/arch/arm/include/asm/arch-imx8/clock.h @@ -23,5 +23,13 @@ enum mxc_clock { }; u32 mxc_get_clock(enum mxc_clock clk); +u32 get_lpuart_clk(void); +int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +u32 imx_get_i2cclk(unsigned i2c_num); +void enable_usboh3_clk(unsigned char enable); +u32 imx_get_fecclk(void); +void init_clk_usdhc(u32 index); +void init_clk_gpmi_nand(void); +void init_clk_usb3(int index); #endif /* __ASM_ARCH_IMX8_CLOCK_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/i2c.h b/arch/arm/include/asm/arch-imx8/i2c.h new file mode 100644 index 00000000000..ea2b83ee7e9 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/i2c.h @@ -0,0 +1,47 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#ifndef __ASM_ARCH_IMX8_I2C_H__ +#define __ASM_ARCH_IMX8_I2C_H__ + +#include +#include + +struct imx_i2c_map { + unsigned index; + sc_rsrc_t rsrc; + u32 lpcg[4]; +}; + +static struct imx_i2c_map imx_i2c_desc[] = { + {0, SC_R_I2C_0, {LPI2C_0_LPCG}}, + {1, SC_R_I2C_1, {LPI2C_1_LPCG}}, + {2, SC_R_I2C_2, {LPI2C_2_LPCG}}, + {3, SC_R_I2C_3, {LPI2C_3_LPCG}}, +#ifdef CONFIG_IMX8QM + {4, SC_R_I2C_4, {LPI2C_4_LPCG}}, + {5, SC_R_LVDS_0_I2C_0, {DI_LVDS_0_LPCG + 0x10}}, /* lvds0 i2c0 */ + {6, SC_R_LVDS_0_I2C_1, {DI_LVDS_0_LPCG + 0x14}}, /* lvds0 i2c1 */ + {7, SC_R_LVDS_1_I2C_0, {DI_LVDS_1_LPCG + 0x10}}, /* lvds1 i2c0 */ + {8, SC_R_LVDS_1_I2C_1, {DI_LVDS_1_LPCG + 0x14}}, /* lvds1 i2c1 */ +#endif + {9, SC_R_CSI_0_I2C_0, {MIPI_CSI_0_LPCG + 0x14}}, +#ifdef CONFIG_IMX8QM + {10, SC_R_CSI_1_I2C_0, {MIPI_CSI_1_LPCG + 0x14}}, + {11, SC_R_HDMI_I2C_0, {DI_HDMI_LPCG}}, + {12, SC_R_HDMI_RX_I2C_0, {RX_HDMI_LPCG + 0x10, RX_HDMI_LPCG + 0x14, RX_HDMI_LPCG + 0x18, RX_HDMI_LPCG + 0x1C}}, + {13, SC_R_MIPI_0_I2C_0, {MIPI_DSI_0_LPCG + 0x14, MIPI_DSI_0_LPCG + 0x18, MIPI_DSI_0_LPCG + 0x1c}}, + {14, SC_R_MIPI_0_I2C_1, {MIPI_DSI_0_LPCG + 0x24, MIPI_DSI_0_LPCG + 0x28, MIPI_DSI_0_LPCG + 0x2c}}, + {15, SC_R_MIPI_1_I2C_0, {MIPI_DSI_1_LPCG + 0x14, MIPI_DSI_1_LPCG + 0x18, MIPI_DSI_1_LPCG + 0x1c}}, + {16, SC_R_MIPI_1_I2C_1, {MIPI_DSI_1_LPCG + 0x24, MIPI_DSI_1_LPCG + 0x28, MIPI_DSI_1_LPCG + 0x2c}}, +#else + {13, SC_R_MIPI_0_I2C_0, {DI_MIPI0_LPCG + 0x10}}, + {14, SC_R_MIPI_0_I2C_1, {DI_MIPI0_LPCG + 0x14}}, + {15, SC_R_MIPI_1_I2C_0, {DI_MIPI1_LPCG + 0x10}}, + {16, SC_R_MIPI_1_I2C_1, {DI_MIPI1_LPCG + 0x14}}, +#endif +}; +#endif /* __ASM_ARCH_IMX8_I2C_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/image.h b/arch/arm/include/asm/arch-imx8/image.h index c1e5700859d..547beeb9860 100644 --- a/arch/arm/include/asm/arch-imx8/image.h +++ b/arch/arm/include/asm/arch-imx8/image.h @@ -53,4 +53,15 @@ struct signature_block_hdr { u16 signature_offset; u32 reserved; } __packed; + +struct generate_key_blob_hdr { + u8 version; + u8 length_lsb; + u8 length_msb; + u8 tag; + u8 flags; + u8 size; + u8 algorithm; + u8 mode; +} __packed; #endif diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index ed6e05e5569..bcf971e0aa2 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -6,6 +6,8 @@ #ifndef __ASM_ARCH_IMX8_REGS_H__ #define __ASM_ARCH_IMX8_REGS_H__ +#include + #define ARCH_MXC #define LPUART_BASE 0x5A060000 @@ -35,6 +37,13 @@ #define MIPI1_SS_BASE 0x56240000 #endif +#ifdef CONFIG_IMX8QM +#define LVDS0_PHYCTRL_BASE 0x56241000 +#define LVDS1_PHYCTRL_BASE 0x57241000 +#define MIPI0_SS_BASE 0x56220000 +#define MIPI1_SS_BASE 0x57220000 +#endif + #define APBH_DMA_ARB_BASE_ADDR 0x5B810000 #define APBH_DMA_ARB_END_ADDR 0x5B81FFFF #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR @@ -46,5 +55,88 @@ #define USB_BASE_ADDR 0x5b0d0000 #define USB_PHY0_BASE_ADDR 0x5b100000 +#define USB_PHY1_BASE_ADDR 0x5b110000 + +#define CAAM_ARB_BASE_ADDR (0x31800000) +#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include +#include + +bool is_usb_boot(void); +void disconnect_from_pc(void); +#define is_boot_from_usb is_usb_boot + +struct usbphy_regs { + u32 usbphy_pwd; /* 0x000 */ + u32 usbphy_pwd_set; /* 0x004 */ + u32 usbphy_pwd_clr; /* 0x008 */ + u32 usbphy_pwd_tog; /* 0x00c */ + u32 usbphy_tx; /* 0x010 */ + u32 usbphy_tx_set; /* 0x014 */ + u32 usbphy_tx_clr; /* 0x018 */ + u32 usbphy_tx_tog; /* 0x01c */ + u32 usbphy_rx; /* 0x020 */ + u32 usbphy_rx_set; /* 0x024 */ + u32 usbphy_rx_clr; /* 0x028 */ + u32 usbphy_rx_tog; /* 0x02c */ + u32 usbphy_ctrl; /* 0x030 */ + u32 usbphy_ctrl_set; /* 0x034 */ + u32 usbphy_ctrl_clr; /* 0x038 */ + u32 usbphy_ctrl_tog; /* 0x03c */ + u32 usbphy_status; /* 0x040 */ + u32 reserved0[3]; + u32 usbphy_debug0; /* 0x050 */ + u32 usbphy_debug0_set; /* 0x054 */ + u32 usbphy_debug0_clr; /* 0x058 */ + u32 usbphy_debug0_tog; /* 0x05c */ + u32 reserved1[4]; + u32 usbphy_debug1; /* 0x070 */ + u32 usbphy_debug1_set; /* 0x074 */ + u32 usbphy_debug1_clr; /* 0x078 */ + u32 usbphy_debug1_tog; /* 0x07c */ + u32 usbphy_version; /* 0x080 */ + u32 reserved2[7]; + u32 usb1_pll_480_ctrl; /* 0x0a0 */ + u32 usb1_pll_480_ctrl_set; /* 0x0a4 */ + u32 usb1_pll_480_ctrl_clr; /* 0x0a8 */ + u32 usb1_pll_480_ctrl_tog; /* 0x0ac */ + u32 reserved3[4]; + u32 usb1_vbus_detect; /* 0xc0 */ + u32 usb1_vbus_detect_set; /* 0xc4 */ + u32 usb1_vbus_detect_clr; /* 0xc8 */ + u32 usb1_vbus_detect_tog; /* 0xcc */ + u32 usb1_vbus_det_stat; /* 0xd0 */ + u32 reserved4[3]; + u32 usb1_chrg_detect; /* 0xe0 */ + u32 usb1_chrg_detect_set; /* 0xe4 */ + u32 usb1_chrg_detect_clr; /* 0xe8 */ + u32 usb1_chrg_detect_tog; /* 0xec */ + u32 usb1_chrg_det_stat; /* 0xf0 */ + u32 reserved5[3]; + u32 usbphy_anactrl; /* 0x100 */ + u32 usbphy_anactrl_set; /* 0x104 */ + u32 usbphy_anactrl_clr; /* 0x108 */ + u32 usbphy_anactrl_tog; /* 0x10c */ + u32 usb1_loopback; /* 0x110 */ + u32 usb1_loopback_set; /* 0x114 */ + u32 usb1_loopback_clr; /* 0x118 */ + u32 usb1_loopback_tog; /* 0x11c */ + u32 usb1_loopback_hsfscnt; /* 0x120 */ + u32 usb1_loopback_hsfscnt_set; /* 0x124 */ + u32 usb1_loopback_hsfscnt_clr; /* 0x128 */ + u32 usb1_loopback_hsfscnt_tog; /* 0x12c */ + u32 usphy_trim_override_en; /* 0x130 */ + u32 usphy_trim_override_en_set; /* 0x134 */ + u32 usphy_trim_override_en_clr; /* 0x138 */ + u32 usphy_trim_override_en_tog; /* 0x13c */ + u32 usb1_pfda_ctrl1; /* 0x140 */ + u32 usb1_pfda_ctrl1_set; /* 0x144 */ + u32 usb1_pfda_ctrl1_clr; /* 0x148 */ + u32 usb1_pfda_ctrl1_tog; /* 0x14c */ +}; +#endif #endif /* __ASM_ARCH_IMX8_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/imx8-pins.h b/arch/arm/include/asm/arch-imx8/imx8-pins.h index 2130298163a..6b1123b1079 100644 --- a/arch/arm/include/asm/arch-imx8/imx8-pins.h +++ b/arch/arm/include/asm/arch-imx8/imx8-pins.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 NXP + * Copyright 2018-2020 NXP */ #ifndef __ASM_ARCH_IMX8_PINS_H__ @@ -10,6 +10,8 @@ #include #elif defined(CONFIG_IMX8QM) #include +#elif defined(CONFIG_IMX8DXL) +#include #else #error "No pin header" #endif diff --git a/arch/arm/include/asm/arch-imx8/imx8_lvds.h b/arch/arm/include/asm/arch-imx8/imx8_lvds.h new file mode 100644 index 00000000000..68fbf6d41e6 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8_lvds.h @@ -0,0 +1,115 @@ +/* + * Copyright 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX8_LVDS_H_ +#define _IMX8_LVDS_H_ + +#define IMX_LVDS_SET_FIELD(__field__, __value__) (((__value__) << (__field__ ## _SHIFT)) & (__field__ ## _MASK)) +#define IMX_LVDS_GET_FIELD(__field__, __reg__) (((__reg__) & (__field__ ## _MASK)) >> (__field__ ## _SHIFT)) + +#define IMX_LVDS_SET(__reg__) (reg+0x4) +#define IMX_LVDS_CLEAR(__reg__) (reg+0x8) +#define IMX_LVDS_TOGGLE(__reg__)(reg+0x4) + +#define LVDS_CTRL 0x0e0 +#define LVDS_CTRL_CH0_MODE_MASK 0x03U +#define LVDS_CTRL_CH0_MODE_SHIFT 0U +#define LVDS_CTRL_CH0_MODE__DISABLED 0x00U +#define LVDS_CTRL_CH0_MODE__DI0 0x01U +#define LVDS_CTRL_CH0_MODE__RESERVED 0x02U +#define LVDS_CTRL_CH0_MODE__DI1 0x03U + +#define LVDS_CTRL_CH1_MODE_MASK 0x0cU +#define LVDS_CTRL_CH1_MODE_SHIFT 2U +#define LVDS_CTRL_CH1_MODE__DISABLED 0x00U +#define LVDS_CTRL_CH1_MODE__DI0 0x01U +#define LVDS_CTRL_CH1_MODE__RESERVED 0x02U +#define LVDS_CTRL_CH1_MODE__DI1 0x03U + +#define LVDS_CTRL_SPLIT_MODE_MASK 0x10U +#define LVDS_CTRL_SPLIT_MODE_SHIFT 4U +#define LVDS_CTRL_SPLIT_MODE__DISABLE 0x00U +#define LVDS_CTRL_SPLIT_MODE__ENABLE 0x01U + +#define LVDS_CTRL_CH0_DATA_WIDTH_MASK 0x20U +#define LVDS_CTRL_CH0_DATA_WIDTH_SHIFT 5U +#define LVDS_CTRL_CH0_DATA_WIDTH__18BIT 0x00U +#define LVDS_CTRL_CH0_DATA_WIDTH__24BIT 0x01U + +#define LVDS_CTRL_CH0_BIT_MAP_MASK 0x40U +#define LVDS_CTRL_CH0_BIT_MAP_SHIFT 6U +#define LVDS_CTRL_CH0_BIT_MAP__SWWG 0x00U +#define LVDS_CTRL_CH0_BIT_MAP__JEIDA 0x01U + +#define LVDS_CTRL_CH1_DATA_WIDTH_MASK 0x80U +#define LVDS_CTRL_CH1_DATA_WIDTH_SHIFT 7U +#define LVDS_CTRL_CH1_DATA_WIDTH__18BIT 0x00U +#define LVDS_CTRL_CH1_DATA_WIDTH__24BIT 0x01U + +#define LVDS_CTRL_CH1_BIT_MAP_MASK 0x100U +#define LVDS_CTRL_CH1_BIT_MAP_SHIFT 8U +#define LVDS_CTRL_CH1_BIT_MAP__SWWG 0x00U +#define LVDS_CTRL_CH1_BIT_MAP__JEIDA 0x01U + +#define LVDS_CTRL_DI0_VSYNC_POL_MASK 0x200U +#define LVDS_CTRL_DI0_VSYNC_POL_SHIFT 9U +#define LVDS_CTRL_DI0_VSYNC_POL__ACTIVE_LOW 0x00U +#define LVDS_CTRL_DI0_VSYNC_POL__ACTIVE_HIGH 0x01U + +#define LVDS_CTRL_DI1_VSYNC_POL_MASK 0x400U +#define LVDS_CTRL_DI1_VSYNC_POL_SHIFT 10U +#define LVDS_CTRL_DI1_VSYNC_POL__ACTIVE_LOW 0x00U +#define LVDS_CTRL_DI1_VSYNC_POL__ACTIVE_HIGH 0x01U + +#define LVDS_CTRL_CH0_10BIT_ENABLE_MASK 0x400000U +#define LVDS_CTRL_CH0_10BIT_ENABLE_SHIFT 22U +#define LVDS_CTRL_CH0_10BIT_ENABLE__USE_DATA_WIDTH 0x00U +#define LVDS_CTRL_CH0_10BIT_ENABLE__10BIT 0x01U + +#define LVDS_CTRL_CH1_10BIT_ENABLE_MASK 0x800000U +#define LVDS_CTRL_CH1_10BIT_ENABLE_SHIFT 23U +#define LVDS_CTRL_CH1_10BIT_ENABLE__USE_DATA_WIDTH 0x00U +#define LVDS_CTRL_CH1_10BIT_ENABLE__10BIT 0x01U + +#define LVDS_CTRL_DI0_DATA_WIDTH_MASK 0x03000000U +#define LVDS_CTRL_DI0_DATA_WIDTH_SHIFT 24U +#define LVDS_CTRL_DI0_DATA_WIDTH__USE_18BIT 0x00U +#define LVDS_CTRL_DI0_DATA_WIDTH__USE_24BIT 0x1U +#define LVDS_CTRL_DI0_DATA_WIDTH__USE_30BIT 0x2U + +#define LVDS_CTRL_DI1_DATA_WIDTH_MASK 0x0C000000U +#define LVDS_CTRL_DI1_DATA_WIDTH_SHIFT 26U +#define LVDS_CTRL_DI1_DATA_WIDTH__USE_18BIT 0x00U +#define LVDS_CTRL_DI1_DATA_WIDTH__USE_24BIT 0x1U +#define LVDS_CTRL_DI1_DATA_WIDTH__USE_30BIT 0x2U + +#define LVDS_PHY_CTRL (0x0) + +#define LVDS_PHY_CTRL_PD_MASK (1<<0) +#define LVDS_PHY_CTRL_PD_SHIFT (0) +#define LVDS_PHY_CTRL_RFB_MASK (1<<1) +#define LVDS_PHY_CTRL_RFB_SHIFT (1) +#define LVDS_PHY_CTRL_NB_MASK (1<<2) +#define LVDS_PHY_CTRL_NB_SHIFT (2) +#define LVDS_PHY_CTRL_CH0_EN_MASK (1<<3) +#define LVDS_PHY_CTRL_CH0_EN_SHIFT (3) +#define LVDS_PHY_CTRL_CH1_EN_MASK (1<<4) +#define LVDS_PHY_CTRL_CH1_EN_SHIFT (4) + +#define LVDS_PHY_CTRL_TST_MASK (0x3f<<5) +#define LVDS_PHY_CTRL_TST_SHIFT (5) + +#define LVDS_PHY_CTRL_CA_MASK (0x7<<11) +#define LVDS_PHY_CTRL_CA_SHIFT (11) + +#define LVDS_PHY_CTRL_CCM_MASK (0x7<<14) +#define LVDS_PHY_CTRL_CCM_SHIFT (14) + +#define LVDS_PHY_CTRL_M_MASK (0x3<<17) +#define LVDS_PHY_CTRL_M_SHIFT (17) + +#endif /* _IMX8_LVDS_H_ */ diff --git a/arch/arm/include/asm/arch-imx8/imx8_mipi_dsi.h b/arch/arm/include/asm/arch-imx8/imx8_mipi_dsi.h new file mode 100644 index 00000000000..63024f3fc5f --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8_mipi_dsi.h @@ -0,0 +1,394 @@ +/* + * Copyright 2015-2017 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _IMX8_MIPI_DSI_H_ +#define _IMX8_MIPI_DSI_H_ + +#define MIPI_CSR_OFFSET 0x1000 /* Subsystem Control Status Registers (CSR) */ +#define MIPI_CSR_TX_ULPS 0x0 +#define MIPIv2_CSR_TX_ULPS 0x30 +#define MIPI_CSR_TX_ULPS_VALUE 0x1F + +#define MIPI_CSR_PXL2DPI 0x4 +#define MIPIv2_CSR_PXL2DPI 0x40 + +#define MIPI_CSR_PXL2DPI_16_BIT_PACKED 0x0 +#define MIPI_CSR_PXL2DPI_16_BIT_565_ALIGNED 0x1 +#define MIPI_CSR_PXL2DPI_16_BIT_565_SHIFTED 0x2 +#define MIPI_CSR_PXL2DPI_18_BIT_PACKED 0x3 +#define MIPI_CSR_PXL2DPI_18_BIT_ALIGNED 0x4 +#define MIPI_CSR_PXL2DPI_24_BIT 0x5 + +#define DSI_CMD_BUF_MAXSIZE (128) + +#define MIPI_DSI_OFFSET 0x8000 /* MIPI DSI Controller */ + +/* DPI interface pixel color coding map */ +enum mipi_dsi_dpi_fmt { + MIPI_RGB565_PACKED = 0, + MIPI_RGB565_LOOSELY, + MIPI_RGB565_CONFIG3, + MIPI_RGB666_PACKED, + MIPI_RGB666_LOOSELY, + MIPI_RGB888, +}; + +struct mipi_dsi_context { + char *NAME; + uint32_t REGS_BASE; + uint32_t CSR_REGS_BASE; +}; + +struct dsi_cfg_csr_object { + uint32_t dsi_host_cfg_num_lanes; + uint32_t dsi_host_cfg_noncont_clk; + uint32_t dsi_host_cfg_t_pre; + uint32_t dsi_host_cfg_t_post; + uint32_t dsi_host_cfg_tx_gap; + uint32_t dsi_host_cfg_autoinsert_eotp; + uint32_t dsi_host_cfg_extrcmd_after_eotp; + uint32_t dsi_host_cfg_htx_to_cnt; + uint32_t dsi_host_cfg_lrx_h_to_cnt; + uint32_t dsi_host_cfg_bta_h_to_cnt; + uint32_t dsi_host_cfg_twakeup; +}; + +struct dsi_cfg_dpi_object { + uint32_t dsi_host_cfg_dpi_pxl_payld_size; + uint32_t dsi_host_cfg_dpi_pxl_fifo_send_lev; + uint32_t dsi_host_cfg_dpi_if_color_coding; + uint32_t dsi_host_cfg_dpi_pxl_format; + uint32_t dsi_host_cfg_dpi_vsync_pol; + uint32_t dsi_host_cfg_dpi_hsync_pol; + uint32_t dsi_host_cfg_dpi_video_mode; + uint32_t dsi_host_cfg_dpi_hfp; + uint32_t dsi_host_cfg_dpi_hbp; + uint32_t dsi_host_cfg_dpi_hsa; + uint32_t dsi_host_cfg_dpi_en_mult_pkt; + uint32_t dsi_host_cfg_dpi_vbp; + uint32_t dsi_host_cfg_dpi_vfp; + uint32_t dsi_host_cfg_dpi_bllp_mode; + uint32_t dsi_host_cfg_dpi_null_pkt_bllp; + uint32_t dsi_host_cfg_dpi_vactive; + uint32_t dsi_host_cfg_dpi_vc; +}; + +struct dsi_cfg_pkt_object { + uint32_t dsi_host_pkt_ctrl; + uint32_t dsi_host_send_pkt; + uint32_t dsi_host_irq_mask; + uint32_t dsi_host_irq_mask2; +}; + +struct dsi_cfg_dphy_object { + uint32_t dphy_pd_tx; + uint32_t dphy_m_prg_hs_prepare; + uint32_t dphy_mc_prg_hs_prepare; + uint32_t dphy_m_prg_hs_zero; + uint32_t dphy_mc_prg_hs_zero; + uint32_t dphy_m_prg_hs_trial; + uint32_t dphy_mc_prg_hs_trial; + uint32_t dphy_pd_pll; + uint32_t dphy_tst; + uint32_t dphy_cn; + uint32_t dphy_cm; + uint32_t dphy_co; + uint32_t dphy_lock; + uint32_t dphy_lock_byp; + uint32_t dphy_tx_rcal; + uint32_t dphy_auto_pd_en; + uint32_t dphy_rxlprp; + uint32_t dphy_rxcdrp; +}; + +/* dphy */ +#define DPHY_PD_TX 0x300 +#define DPHY_M_PRG_HS_PREPARE 0x304 +#define DPHY_MC_PRG_HS_PREPARE 0x308 +#define DPHY_M_PRG_HS_ZERO 0x30c +#define DPHY_MC_PRG_HS_ZERO 0x310 +#define DPHY_M_PRG_HS_TRAIL 0x314 +#define DPHY_MC_PRG_HS_TRAIL 0x318 +#define DPHY_PD_PLL 0x31c +#define DPHY_TST 0x320 +#define DPHY_CN 0x324 +#define DPHY_CM 0x328 +#define DPHY_CO 0x32c +#define DPHY_LOCK 0x330 +#define DPHY_LOCK_BYP 0x334 +#define DPHY_RTERM_SEL 0x338 +#define DPHY_AUTO_PD_EN 0x33c +#define DPHY_RXLPRP 0x340 +#define DPHY_RXCDRP 0x344 + +/* host */ +#define HOST_CFG_NUM_LANES 0x0 +#define HOST_CFG_NONCONTINUOUS_CLK 0x4 +#define HOST_CFG_T_PRE 0x8 +#define HOST_CFG_T_POST 0xc +#define HOST_CFG_TX_GAP 0x10 +#define HOST_CFG_AUTOINSERT_EOTP 0x14 +#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 +#define HOST_CFG_HTX_TO_COUNT 0x1c +#define HOST_CFG_LRX_H_TO_COUNT 0x20 +#define HOST_CFG_BTA_H_TO_COUNT 0x24 +#define HOST_CFG_TWAKEUP 0x28 +#define HOST_CFG_STATUS_OUT 0x2c +#define HOST_RX_ERROR_STATUS 0x30 + +/* dpi */ +#define DPI_PIXEL_PAYLOAD_SIZE 0x200 +#define DPI_PIXEL_FIFO_SEND_LEVEL 0x204 +#define DPI_INTERFACE_COLOR_CODING 0x208 +#define DPI_PIXEL_FORMAT 0x20c +#define DPI_VSYNC_POLARITY 0x210 +#define DPI_HSYNC_POLARITY 0x214 +#define DPI_VIDEO_MODE 0x218 +#define DPI_HFP 0x21c +#define DPI_HBP 0x220 +#define DPI_HSA 0x224 +#define DPI_ENABLE_MULT_PKTS 0x228 +#define DPI_VBP 0x22c +#define DPI_VFP 0x230 +#define DPI_BLLP_MODE 0x234 +#define DPI_USE_NULL_PKT_BLLP 0x238 +#define DPI_VACTIVE 0x23c +#define DPI_VC 0x240 + +/* apb pkt */ +#define HOST_TX_PAYLOAD 0x280 + +#define HOST_PKT_CONTROL 0x284 +#define HOST_PKT_CONTROL_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_CONTROL_VC(x) (((x) & 0x3) << 16) +#define HOST_PKT_CONTROL_DT(x) (((x) & 0x3f) << 18) +#define HOST_PKT_CONTROL_HS_SEL(x) (((x) & 0x1) << 24) +#define HOST_PKT_CONTROL_BTA_TX(x) (((x) & 0x1) << 25) +#define HOST_PKT_CONTROL_BTA_NO_TX(x) (((x) & 0x1) << 26) + +#define HOST_SEND_PACKET 0x288 +#define HOST_PKT_STATUS 0x28c +#define HOST_PKT_FIFO_WR_LEVEL 0x290 +#define HOST_PKT_FIFO_RD_LEVEL 0x294 +#define HOST_PKT_RX_PAYLOAD 0x298 + +#define HOST_PKT_RX_PKT_HEADER 0x29c +#define HOST_PKT_RX_PKT_HEADER_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_RX_PKT_HEADER_DT(x) (((x) & 0x3f) << 16) +#define HOST_PKT_RX_PKT_HEADER_VC(x) (((x) & 0x3) << 22) + +#define HOST_IRQ_STATUS 0x2a0 +#define HOST_IRQ_STATUS_SM_NOT_IDLE (1 << 0) +#define HOST_IRQ_STATUS_TX_PKT_DONE (1 << 1) +#define HOST_IRQ_STATUS_DPHY_DIRECTION (1 << 2) +#define HOST_IRQ_STATUS_TX_FIFO_OVFLW (1 << 3) +#define HOST_IRQ_STATUS_TX_FIFO_UDFLW (1 << 4) +#define HOST_IRQ_STATUS_RX_FIFO_OVFLW (1 << 5) +#define HOST_IRQ_STATUS_RX_FIFO_UDFLW (1 << 6) +#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD (1 << 7) +#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD (1 << 8) +#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT (1 << 29) +#define HOST_IRQ_STATUS_LP_RX_TIMEOUT (1 << 30) +#define HOST_IRQ_STATUS_HS_TX_TIMEOUT (1 << 31) + +#define HOST_IRQ_STATUS2 0x2a4 +#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR (1 << 0) +#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR (1 << 1) +#define HOST_IRQ_STATUS2_CRC_ERR (1 << 2) + +#define HOST_IRQ_MASK 0x2a8 +#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK (1 << 0) +#define HOST_IRQ_MASK_TX_PKT_DONE_MASK (1 << 1) +#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK (1 << 2) +#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK (1 << 3) +#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK (1 << 4) +#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK (1 << 5) +#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK (1 << 6) +#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK (1 << 7) +#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK (1 << 8) +#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK (1 << 29) +#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK (1 << 30) +#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK (1 << 31) + +#define HOST_IRQ_MASK2 0x2ac +#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK (1 << 0) +#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK (1 << 1) +#define HOST_IRQ_MASK2_CRC_ERR_MASK (1 << 2) + +/* ------------------------------------- end -------------------------------- */ +#define BITSLICE(x, a, b) (((x) >> (b)) & ((1 << ((a)-(b)+1)) - 1)) + +#ifdef DEBUG +#define W32(reg, val) \ +do {printf("%s():%d reg 0x%p val 0x%08x\n",\ + __func__, __LINE__, reg, val);\ + __raw_writel(val, reg); } while (0) +#else +#define W32(reg, val) __raw_writel(val, reg) +#endif + +#define R32(reg) __raw_readl(reg) + +/* helper functions */ +inline void dsi_host_ctrl_csr_setup(void __iomem *base, + struct dsi_cfg_csr_object *dsi_config, + uint16_t csr_setup_mask) +{ + if (BITSLICE(csr_setup_mask, 0, 0)) + W32(base + HOST_CFG_NUM_LANES, + dsi_config->dsi_host_cfg_num_lanes); + if (BITSLICE(csr_setup_mask, 1, 1)) + W32(base + HOST_CFG_NONCONTINUOUS_CLK, + dsi_config->dsi_host_cfg_noncont_clk); + if (BITSLICE(csr_setup_mask, 2, 2)) + W32(base + HOST_CFG_T_PRE, dsi_config->dsi_host_cfg_t_pre); + if (BITSLICE(csr_setup_mask, 3, 3)) + W32(base + HOST_CFG_T_POST, + dsi_config->dsi_host_cfg_t_post); + if (BITSLICE(csr_setup_mask, 4, 4)) + W32(base + HOST_CFG_TX_GAP, + dsi_config->dsi_host_cfg_tx_gap); + if (BITSLICE(csr_setup_mask, 5, 5)) + W32(base + HOST_CFG_AUTOINSERT_EOTP, + dsi_config->dsi_host_cfg_autoinsert_eotp); + if (BITSLICE(csr_setup_mask, 6, 6)) + W32(base + HOST_CFG_EXTRA_CMDS_AFTER_EOTP, + dsi_config->dsi_host_cfg_extrcmd_after_eotp); + if (BITSLICE(csr_setup_mask, 7, 7)) + W32(base + HOST_CFG_HTX_TO_COUNT, + dsi_config->dsi_host_cfg_htx_to_cnt); + if (BITSLICE(csr_setup_mask, 8, 8)) + W32(base + HOST_CFG_LRX_H_TO_COUNT, + dsi_config->dsi_host_cfg_lrx_h_to_cnt); + if (BITSLICE(csr_setup_mask, 9, 9)) + W32(base + HOST_CFG_BTA_H_TO_COUNT, + dsi_config->dsi_host_cfg_bta_h_to_cnt); + if (BITSLICE(csr_setup_mask, 10, 10)) + W32(base + HOST_CFG_TWAKEUP, + dsi_config->dsi_host_cfg_twakeup); +} + +inline void dsi_host_ctrl_dpi_setup(void __iomem *base, + struct dsi_cfg_dpi_object *dsi_config, + uint32_t dpi_setup_mask) +{ + if (BITSLICE(dpi_setup_mask, 0, 0)) + W32(base + DPI_PIXEL_PAYLOAD_SIZE, + dsi_config->dsi_host_cfg_dpi_pxl_payld_size); + if (BITSLICE(dpi_setup_mask, 1, 1)) + W32(base + DPI_PIXEL_FIFO_SEND_LEVEL, + dsi_config->dsi_host_cfg_dpi_pxl_fifo_send_lev); + if (BITSLICE(dpi_setup_mask, 2, 2)) + W32(base + DPI_INTERFACE_COLOR_CODING, + dsi_config->dsi_host_cfg_dpi_if_color_coding); + if (BITSLICE(dpi_setup_mask, 3, 3)) + W32(base + DPI_PIXEL_FORMAT, + dsi_config->dsi_host_cfg_dpi_pxl_format); + if (BITSLICE(dpi_setup_mask, 4, 4)) + W32(base + DPI_VSYNC_POLARITY, + dsi_config->dsi_host_cfg_dpi_vsync_pol); + if (BITSLICE(dpi_setup_mask, 5, 5)) + W32(base + DPI_HSYNC_POLARITY, + dsi_config->dsi_host_cfg_dpi_hsync_pol); + if (BITSLICE(dpi_setup_mask, 6, 6)) + W32(base + DPI_VIDEO_MODE, + dsi_config->dsi_host_cfg_dpi_video_mode); + if (BITSLICE(dpi_setup_mask, 7, 7)) + W32(base + DPI_HFP, dsi_config->dsi_host_cfg_dpi_hfp); + if (BITSLICE(dpi_setup_mask, 8, 8)) + W32(base + DPI_HBP, dsi_config->dsi_host_cfg_dpi_hbp); + if (BITSLICE(dpi_setup_mask, 9, 9)) + W32(base + DPI_HSA, dsi_config->dsi_host_cfg_dpi_hsa); + if (BITSLICE(dpi_setup_mask, 10, 10)) + W32(base + DPI_ENABLE_MULT_PKTS, + dsi_config->dsi_host_cfg_dpi_en_mult_pkt); + if (BITSLICE(dpi_setup_mask, 11, 11)) + W32(base + DPI_VBP, dsi_config->dsi_host_cfg_dpi_vbp); + if (BITSLICE(dpi_setup_mask, 12, 12)) + W32(base + DPI_VFP, dsi_config->dsi_host_cfg_dpi_vfp); + if (BITSLICE(dpi_setup_mask, 13, 13)) + W32(base + DPI_BLLP_MODE, + dsi_config->dsi_host_cfg_dpi_bllp_mode); + if (BITSLICE(dpi_setup_mask, 14, 14)) + W32(base + DPI_USE_NULL_PKT_BLLP, + dsi_config->dsi_host_cfg_dpi_null_pkt_bllp); + if (BITSLICE(dpi_setup_mask, 15, 15)) + W32(base + DPI_VACTIVE, + dsi_config->dsi_host_cfg_dpi_vactive); + if (BITSLICE(dpi_setup_mask, 16, 16)) + W32(base + DPI_VC, dsi_config->dsi_host_cfg_dpi_vc); +} + +inline void dsi_host_ctrl_pkt_setup(void __iomem *base, + struct dsi_cfg_pkt_object *dsi_config, + uint8_t pkt_setup_mask) +{ + if (BITSLICE(pkt_setup_mask, 0, 0)) + W32(base + HOST_PKT_CONTROL, + dsi_config->dsi_host_pkt_ctrl); + if (BITSLICE(pkt_setup_mask, 2, 2)) + W32(base + HOST_IRQ_MASK, dsi_config->dsi_host_irq_mask); + if (BITSLICE(pkt_setup_mask, 3, 3)) + W32(base + HOST_IRQ_MASK2, dsi_config->dsi_host_irq_mask2); + if (BITSLICE(pkt_setup_mask, 1, 1)) + W32(base + HOST_SEND_PACKET, + dsi_config->dsi_host_send_pkt); +} + +inline void dsi_host_ctrl_dphy_setup(void __iomem *base, + struct dsi_cfg_dphy_object *dsi_config, + uint32_t dphy_setup_mask) +{ + int i; + + if (BITSLICE(dphy_setup_mask, 8, 8)) + W32(base + DPHY_TST, dsi_config->dphy_tst); + if (BITSLICE(dphy_setup_mask, 9, 9)) + W32(base + DPHY_CN, dsi_config->dphy_cn); + if (BITSLICE(dphy_setup_mask, 10, 10)) + W32(base + DPHY_CM, dsi_config->dphy_cm); + if (BITSLICE(dphy_setup_mask, 11, 11)) + W32(base + DPHY_CO, dsi_config->dphy_co); + if (BITSLICE(dphy_setup_mask, 7, 7)) + W32(base + DPHY_PD_PLL, dsi_config->dphy_pd_pll); + /* todo: disable on zebu */ + /*Polling of DPHY Lock status / wait for PLL lock */ + for (i = 0; i < 100; i++) { + u32 lock; + udelay(10); + /*todo: zebu abort when reading DPHY LOCK */ + lock = R32(DPHY_LOCK); + printf("DPHY PLL Lock = 0x%08x\n", lock); + } + /*todo: Need to wait for lock here */ + + if (BITSLICE(dphy_setup_mask, 1, 1)) + W32(base + DPHY_M_PRG_HS_PREPARE, + dsi_config->dphy_m_prg_hs_prepare); + if (BITSLICE(dphy_setup_mask, 2, 2)) + W32(base + DPHY_MC_PRG_HS_PREPARE, + dsi_config->dphy_mc_prg_hs_prepare); + if (BITSLICE(dphy_setup_mask, 3, 3)) + W32(base + DPHY_M_PRG_HS_ZERO, + dsi_config->dphy_m_prg_hs_zero); + if (BITSLICE(dphy_setup_mask, 4, 4)) + W32(base + DPHY_MC_PRG_HS_ZERO, + dsi_config->dphy_mc_prg_hs_zero); + if (BITSLICE(dphy_setup_mask, 5, 5)) + W32(base + DPHY_M_PRG_HS_TRAIL, + dsi_config->dphy_m_prg_hs_trial); + if (BITSLICE(dphy_setup_mask, 6, 6)) + W32(base + DPHY_MC_PRG_HS_TRAIL, + dsi_config->dphy_mc_prg_hs_trial); + if (BITSLICE(dphy_setup_mask, 0, 0)) + W32(base + DPHY_PD_TX, dsi_config->dphy_pd_tx); + if (BITSLICE(dphy_setup_mask, 12, 12)) + W32(base + DPHY_LOCK, dsi_config->dphy_lock); + if (BITSLICE(dphy_setup_mask, 13, 13)) + W32(base + DPHY_LOCK_BYP, dsi_config->dphy_lock_byp); +} +#endif /* _IMX8_MIPI_DSI_H_ */ diff --git a/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h new file mode 100644 index 00000000000..692c27f7d30 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qm_lpcg.h @@ -0,0 +1,200 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_1_LPCG 0x5AC90000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_4_LPCG 0x5AC40000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define EMVSIM_1_LPCG 0x5A4E0000 +#define EMVSIM_0_LPCG 0x5A4D0000 +#define LPUART_4_LPCG 0x5A4A0000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* MIPI DSI SS */ +#define MIPI_DSI_0_LPCG 0x56223000 +#define MIPI_DSI_1_LPCG 0x57223000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SPDIF_1_LPCG 0x59430000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_HDMI_RX_SAI_0_LPCG 0x59480000 +#define AUD_HDMI_TX_SAI_0_LPCG 0x59490000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_ESAI_1_LPCG 0x59c10000 +#define AUD_SAI_6_LPCG 0x59c20000 +#define AUD_SAI_7_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + +/* CM41 SS */ +#define CM41_I2C_LPCG 0x3B630000 + +#endif diff --git a/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h new file mode 100644 index 00000000000..5fed5140c1a --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/imx8qxp_lpcg.h @@ -0,0 +1,195 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SC_LPCG_H +#define _SC_LPCG_H + +/*LSIO SS */ +#define PWM_0_LPCG 0x5D400000 +#define PWM_1_LPCG 0x5D410000 +#define PWM_2_LPCG 0x5D420000 +#define PWM_3_LPCG 0x5D430000 +#define PWM_4_LPCG 0x5D440000 +#define PWM_5_LPCG 0x5D450000 +#define PWM_6_LPCG 0x5D460000 +#define PWM_7_LPCG 0x5D470000 +#define GPIO_0_LPCG 0x5D480000 +#define GPIO_1_LPCG 0x5D490000 +#define GPIO_2_LPCG 0x5D4A0000 +#define GPIO_3_LPCG 0x5D4B0000 +#define GPIO_4_LPCG 0x5D4C0000 +#define GPIO_5_LPCG 0x5D4D0000 +#define GPIO_6_LPCG 0x5D4E0000 +#define GPIO_7_LPCG 0x5D4F0000 +#define FSPI_0_LPCG 0x5D520000 +#define FSPI_1_LPCG 0x5D530000 +#define GPT_0_LPCG 0x5D540000 +#define GPT_1_LPCG 0x5D550000 +#define GPT_2_LPCG 0x5D560000 +#define GPT_3_LPCG 0x5D570000 +#define GPT_4_LPCG 0x5D580000 +#define OCRAM_LPCG 0x5D590000 +#define KPP_LPCG 0x5D5A0000 +#define ROMCP_LPCG 0x5D500000 +#define MU_5A_LPCG 0x5D600000 +#define MU_6A_LPCG 0x5D610000 +#define MU_7A_LPCG 0x5D620000 +#define MU_8A_LPCG 0x5D630000 +#define MU_9A_LPCG 0x5D640000 +#define MU_10A_LPCG 0x5D650000 +#define MU_11A_LPCG 0x5D660000 +#define MU_12A_LPCG 0x5D670000 +#define MU_13A_LPCG 0x5D680000 + +/* HSIO SS */ +#define CRR_5_LPCG 0x5F0F0000 +#define CRR_4_LPCG 0x5F0E0000 +#define CRR_3_LPCG 0x5F0D0000 +#define CRR_2_LPCG 0x5F0C0000 +#define CRR_1_LPCG 0x5F0B0000 +#define CRR_0_LPCG 0x5F0A0000 +#define PHY_1_LPCG 0x5F090000 +#define PHY_2_LPCG 0x5F080000 +#define SATA_0_LPCG 0x5F070000 +#define PCIE_B_LPCG 0x5F060000 +#define PCIE_A_LPCG 0x5F050000 + +/* DMA SS */ +#define FLEX_CAN_2_LPCG 0x5ACF0000 +#define FLEX_CAN_1_LPCG 0x5ACE0000 +#define FLEX_CAN_0_LPCG 0x5ACD0000 +#define FTM_1_LPCG 0x5ACB0000 +#define FTM_0_LPCG 0x5ACA0000 +#define ADC_0_LPCG 0x5AC80000 +#define LPI2C_3_LPCG 0x5AC30000 +#define LPI2C_2_LPCG 0x5AC20000 +#define LPI2C_1_LPCG 0x5AC10000 +#define LPI2C_0_LPCG 0x5AC00000 +#define PWM_LPCG 0x5A590000 +#define LCD_LPCG 0x5A580000 +#define LPUART_3_LPCG 0x5A490000 +#define LPUART_2_LPCG 0x5A480000 +#define LPUART_1_LPCG 0x5A470000 +#define LPUART_0_LPCG 0x5A460000 +#define LPSPI_3_LPCG 0x5A430000 +#define LPSPI_2_LPCG 0x5A420000 +#define LPSPI_1_LPCG 0x5A410000 +#define LPSPI_0_LPCG 0x5A400000 + +/* Display SS */ +#define DC_0_LPCG 0x56010000 +#define DC_1_LPCG 0x57010000 + +/* LVDS */ +#define DI_LVDS_0_LPCG 0x56243000 +#define DI_LVDS_1_LPCG 0x57243000 + +/* DI HDMI */ +#define DI_HDMI_LPCG 0x56263000 + +/* RX-HDMI */ +#define RX_HDMI_LPCG 0x58263000 + +/* MIPI CSI SS */ +#define MIPI_CSI_0_LPCG 0x58223000 +#define MIPI_CSI_1_LPCG 0x58243000 + +/* PARALLEL CSI SS */ +#define PARALLEL_CSI_LPCG 0x58263000 + +/* Display MIPI SS */ +#define DI_MIPI0_LPCG 0x56223000 +#define DI_MIPI1_LPCG 0x56243000 + +/* Imaging SS */ +#define IMG_JPEG_ENC_LPCG 0x585F0000 +#define IMG_JPEG_DEC_LPCG 0x585D0000 +#define IMG_PXL_LINK_DC1_LPCG 0x585C0000 +#define IMG_PXL_LINK_DC0_LPCG 0x585B0000 +#define IMG_PXL_LINK_HDMI_LPCG 0x585A0000 +#define IMG_PXL_LINK_CSI1_LPCG 0x58590000 +#define IMG_PXL_LINK_CSI0_LPCG 0x58580000 +#define IMG_PDMA_7_LPCG 0x58570000 +#define IMG_PDMA_6_LPCG 0x58560000 +#define IMG_PDMA_5_LPCG 0x58550000 +#define IMG_PDMA_4_LPCG 0x58540000 +#define IMG_PDMA_3_LPCG 0x58530000 +#define IMG_PDMA_2_LPCG 0x58520000 +#define IMG_PDMA_1_LPCG 0x58510000 +#define IMG_PDMA_0_LPCG 0x58500000 + +/* HSIO SS */ +#define HSIO_GPIO_LPCG 0x5F100000 +#define HSIO_MISC_LPCG 0x5F0F0000 +#define HSIO_SATA_CRR4_LPCG 0x5F0E0000 +#define HSIO_PCIE_X1_CRR3_LPCG 0x5F0D0000 +#define HSIO_PCIE_X2_CRR2_LPCG 0x5F0C0000 +#define HSIO_PHY_X1_CRR1_LPCG 0x5F0B0000 +#define HSIO_PHY_X2_CRR0_LPCG 0x5F0A0000 +#define HSIO_PHY_X1_LPCG 0x5F090000 +#define HSIO_PHY_X2_LPCG 0x5F080000 +#define HSIO_SATA_LPCG 0x5F070000 +#define HSIO_PCIE_X1_LPCG 0x5F060000 +#define HSIO_PCIE_X2_LPCG 0x5F050000 + +/* M4 SS */ +#define M4_0_I2C_LPCG 0x37630000 +#define M4_0_LPUART_LPCG 0x37620000 +#define M4_0_LPIT_LPCG 0x37610000 +#define M4_1_I2C_LPCG 0x3B630000 +#define M4_1_LPUART_LPCG 0x3B620000 +#define M4_1_LPIT_LPCG 0x3B610000 + +/* Audio SS */ +#define AUD_ASRC_0_LPCG 0x59400000 +#define AUD_ESAI_0_LPCG 0x59410000 +#define AUD_SPDIF_0_LPCG 0x59420000 +#define AUD_SAI_0_LPCG 0x59440000 +#define AUD_SAI_1_LPCG 0x59450000 +#define AUD_SAI_2_LPCG 0x59460000 +#define AUD_SAI_3_LPCG 0x59470000 +#define AUD_GPT_5_LPCG 0x594B0000 +#define AUD_GPT_6_LPCG 0x594C0000 +#define AUD_GPT_7_LPCG 0x594D0000 +#define AUD_GPT_8_LPCG 0x594E0000 +#define AUD_GPT_9_LPCG 0x594F0000 +#define AUD_GPT_10_LPCG 0x59500000 +#define AUD_DSP_LPCG 0x59580000 +#define AUD_OCRAM_LPCG 0x59590000 +#define AUD_EDMA_0_LPCG 0x595f0000 +#define AUD_ASRC_1_LPCG 0x59c00000 +#define AUD_SAI_4_LPCG 0x59c20000 +#define AUD_SAI_5_LPCG 0x59c30000 +#define AUD_AMIX_LPCG 0x59c40000 +#define AUD_MQS_LPCG 0x59c50000 +#define AUD_ACM_LPCG 0x59c60000 +#define AUD_REC_CLK0_LPCG 0x59d00000 +#define AUD_REC_CLK1_LPCG 0x59d10000 +#define AUD_PLL_CLK0_LPCG 0x59d20000 +#define AUD_PLL_CLK1_LPCG 0x59d30000 +#define AUD_MCLKOUT0_LPCG 0x59d50000 +#define AUD_MCLKOUT1_LPCG 0x59d60000 +#define AUD_EDMA_1_LPCG 0x59df0000 + + +/* Connectivity SS */ +#define USDHC_0_LPCG 0x5B200000 +#define USDHC_1_LPCG 0x5B210000 +#define USDHC_2_LPCG 0x5B220000 +#define ENET_0_LPCG 0x5B230000 +#define ENET_1_LPCG 0x5B240000 +#define DTCP_LPCG 0x5B250000 +#define MLB_LPCG 0x5B260000 +#define USB_2_LPCG 0x5B270000 +#define USB_3_LPCG 0x5B280000 +#define NAND_LPCG 0x5B290000 +#define EDMA_LPCG 0x5B2A0000 + +/* CM40 SS */ +#define CM40_I2C_LPCG 0x37630000 + + +#endif diff --git a/arch/arm/include/asm/arch-imx8/lpcg.h b/arch/arm/include/asm/arch-imx8/lpcg.h new file mode 100644 index 00000000000..85cb5b30c19 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/lpcg.h @@ -0,0 +1,28 @@ +/* + * Copyright 2018-2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_IMX8_LPCG_H__ +#define __ASM_ARCH_IMX8_LPCG_H__ + +#if defined(CONFIG_IMX8QM) +#include "imx8qm_lpcg.h" +#elif defined(CONFIG_IMX8QXP) +#include "imx8qxp_lpcg.h" +#elif defined(CONFIG_IMX8DXL) +#include "imx8qxp_lpcg.h" +#else +#error "No lpcg header" +#endif + +void lpcg_clock_off(u32 lpcg_addr, u8 clk); +void lpcg_clock_on(u32 lpcg_addr, u8 clk); +void lpcg_clock_autogate(u32 lpcg_addr, u8 clk); +bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk); +void lpcg_all_clock_off(u32 lpcg_addr); +void lpcg_all_clock_on(u32 lpcg_addr); +void lpcg_all_clock_autogate(u32 lpcg_addr); + +#endif /* __ASM_ARCH_IMX8_LPCG_H__ */ diff --git a/arch/arm/include/asm/arch-imx8/sci/rpc.h b/arch/arm/include/asm/arch-imx8/sci/rpc.h index 9f55904f442..041e4d002dc 100644 --- a/arch/arm/include/asm/arch-imx8/sci/rpc.h +++ b/arch/arm/include/asm/arch-imx8/sci/rpc.h @@ -11,7 +11,7 @@ /* Defines */ #define SCFW_API_VERSION_MAJOR 1U -#define SCFW_API_VERSION_MINOR 15U +#define SCFW_API_VERSION_MINOR 21U #define SC_RPC_VERSION 1U @@ -22,13 +22,13 @@ #define RPC_SVC(MSG) ((MSG)->svc) #define RPC_FUNC(MSG) ((MSG)->func) #define RPC_R8(MSG) ((MSG)->func) -#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ - (s64)(RPC_U32((MSG), (IDX) + 4U)) +#define RPC_I64(MSG, IDX) ((s64)(RPC_U32((MSG), (IDX))) << 32ULL) \ + | (s64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_I32(MSG, IDX) ((MSG)->DATA.i32[(IDX) / 4U]) #define RPC_I16(MSG, IDX) ((MSG)->DATA.i16[(IDX) / 2U]) #define RPC_I8(MSG, IDX) ((MSG)->DATA.i8[(IDX)]) -#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) | \ - (u64)(RPC_U32((MSG), (IDX) + 4U)) +#define RPC_U64(MSG, IDX) ((u64)(RPC_U32((MSG), (IDX))) << 32ULL) \ + | (u64)(RPC_U32((MSG), (IDX) + 4U)) #define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U]) #define RPC_U16(MSG, IDX) ((MSG)->DATA.u16[(IDX) / 2U]) #define RPC_U8(MSG, IDX) ((MSG)->DATA.u8[(IDX)]) @@ -67,7 +67,9 @@ struct sc_rpc_msg_s { #define PM_FUNC_SET_SYS_POWER_MODE 19U #define PM_FUNC_SET_PARTITION_POWER_MODE 1U #define PM_FUNC_GET_SYS_POWER_MODE 2U +#define PM_FUNC_PARTITION_WAKE 28U #define PM_FUNC_SET_RESOURCE_POWER_MODE 3U +#define PM_FUNC_SET_RESOURCE_POWER_MODE_ALL 22U #define PM_FUNC_GET_RESOURCE_POWER_MODE 4U #define PM_FUNC_REQ_LOW_POWER_MODE 16U #define PM_FUNC_REQ_CPU_LOW_POWER_MODE 20U @@ -81,12 +83,15 @@ struct sc_rpc_msg_s { #define PM_FUNC_GET_CLOCK_PARENT 15U #define PM_FUNC_RESET 13U #define PM_FUNC_RESET_REASON 10U +#define PM_FUNC_GET_RESET_PART 26U #define PM_FUNC_BOOT 8U +#define PM_FUNC_SET_BOOT_PARM 27U #define PM_FUNC_REBOOT 9U #define PM_FUNC_REBOOT_PARTITION 12U +#define PM_FUNC_REBOOT_CONTINUE 25U #define PM_FUNC_CPU_START 11U -#define PM_FUNC_CPU_RESET 23U -#define PM_FUNC_RESOURCE_RESET 29U +#define PM_FUNC_CPU_RESET 23U +#define PM_FUNC_RESOURCE_RESET 29U #define PM_FUNC_IS_PARTITION_STARTED 24U /* MISC RPC */ @@ -95,16 +100,10 @@ struct sc_rpc_msg_s { #define MISC_FUNC_GET_CONTROL 2U #define MISC_FUNC_SET_MAX_DMA_GROUP 4U #define MISC_FUNC_SET_DMA_GROUP 5U -#define MISC_FUNC_SECO_IMAGE_LOAD 8U -#define MISC_FUNC_SECO_AUTHENTICATE 9U -#define MISC_FUNC_SECO_FUSE_WRITE 20U -#define MISC_FUNC_SECO_ENABLE_DEBUG 21U -#define MISC_FUNC_SECO_FORWARD_LIFECYCLE 22U -#define MISC_FUNC_SECO_RETURN_LIFECYCLE 23U -#define MISC_FUNC_SECO_BUILD_INFO 24U #define MISC_FUNC_DEBUG_OUT 10U #define MISC_FUNC_WAVEFORM_CAPTURE 6U #define MISC_FUNC_BUILD_INFO 15U +#define MISC_FUNC_API_VER 35U #define MISC_FUNC_UNIQUE_ID 19U #define MISC_FUNC_SET_ARI 3U #define MISC_FUNC_BOOT_STATUS 7U @@ -114,8 +113,11 @@ struct sc_rpc_msg_s { #define MISC_FUNC_SET_TEMP 12U #define MISC_FUNC_GET_TEMP 13U #define MISC_FUNC_GET_BOOT_DEV 16U -#define MISC_FUNC_GET_BUTTON_STATUS 18U +#define MISC_FUNC_GET_BOOT_TYPE 33U #define MISC_FUNC_GET_BOOT_CONTAINER 36U +#define MISC_FUNC_GET_BUTTON_STATUS 18U +#define MISC_FUNC_ROMPATCH_CHECKSUM 26U +#define MISC_FUNC_BOARD_IOCTL 34U /* PAD RPC */ #define PAD_FUNC_UNKNOWN 0 @@ -160,6 +162,7 @@ struct sc_rpc_msg_s { #define RM_FUNC_GET_RESOURCE_INFO 16U #define RM_FUNC_MEMREG_ALLOC 17U #define RM_FUNC_MEMREG_SPLIT 29U +#define RM_FUNC_MEMREG_FRAG 32U #define RM_FUNC_MEMREG_FREE 18U #define RM_FUNC_FIND_MEMREG 30U #define RM_FUNC_ASSIGN_MEMREG 19U @@ -190,6 +193,7 @@ struct sc_rpc_msg_s { #define SECO_FUNC_UPDATE_MPMR 14U /* Index for seco_update_mpmr() RPC call */ #define SECO_FUNC_GET_MP_SIGN 15U /* Index for seco_get_mp_sign() RPC call */ #define SECO_FUNC_BUILD_INFO 16U /* Index for seco_build_info() RPC call */ +#define SECO_FUNC_V2X_BUILD_INFO 30U /* Index for sc_seco_v2x_build_info() RPC call */ #define SECO_FUNC_CHIP_INFO 17U /* Index for seco_chip_info() RPC call */ #define SECO_FUNC_ENABLE_DEBUG 18U /* Index for seco_enable_debug() RPC call */ #define SECO_FUNC_GET_EVENT 19U /* Index for seco_get_event() RPC call */ @@ -210,6 +214,7 @@ struct sc_rpc_msg_s { #define TIMER_FUNC_UNKNOWN 0 /* Unknown function */ #define TIMER_FUNC_SET_WDOG_TIMEOUT 1U /* Index for sc_timer_set_wdog_timeout() RPC call */ #define TIMER_FUNC_SET_WDOG_PRE_TIMEOUT 12U /* Index for sc_timer_set_wdog_pre_timeout() RPC call */ +#define TIMER_FUNC_SET_WDOG_WINDOW 19U /* Index for sc_timer_set_wdog_window() RPC call */ #define TIMER_FUNC_START_WDOG 2U /* Index for sc_timer_start_wdog() RPC call */ #define TIMER_FUNC_STOP_WDOG 3U /* Index for sc_timer_stop_wdog() RPC call */ #define TIMER_FUNC_PING_WDOG 4U /* Index for sc_timer_ping_wdog() RPC call */ diff --git a/arch/arm/include/asm/arch-imx8/sci/sci.h b/arch/arm/include/asm/arch-imx8/sci/sci.h index 1c29209b399..94b62dc16d1 100644 --- a/arch/arm/include/asm/arch-imx8/sci/sci.h +++ b/arch/arm/include/asm/arch-imx8/sci/sci.h @@ -13,6 +13,8 @@ #include #include #include +#include +#include #include #include #include @@ -72,6 +74,7 @@ int sc_pm_set_clock_parent(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, sc_pm_clk_parent_t parent); int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, sc_faddr_t address); +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); sc_bool_t sc_pm_is_partition_started(sc_ipc_t ipc, sc_rm_pt_t pt); int sc_pm_resource_reset(sc_ipc_t ipc, sc_rsrc_t resource); @@ -87,6 +90,7 @@ void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, s16 *celsius, s8 *tenths); +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status); /* RM API */ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr); @@ -116,6 +120,9 @@ int sc_pad_get(sc_ipc_t ipc, sc_pad_t pad, uint32_t *val); /* SMMU API */ int sc_rm_set_master_sid(sc_ipc_t ipc, sc_rsrc_t resource, sc_rm_sid_t sid); +/* Timer API */ +int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window); + /* SECO API */ int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr); @@ -123,16 +130,20 @@ int sc_seco_forward_lifecycle(sc_ipc_t ipc, u32 change); int sc_seco_chip_info(sc_ipc_t ipc, u16 *lc, u16 *monotonic, u32 *uid_l, u32 *uid_h); void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); +int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit); int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event); int sc_seco_gen_key_blob(sc_ipc_t ipc, u32 id, sc_faddr_t load_addr, sc_faddr_t export_addr, u16 max_size); -int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, u16 dst_size); -int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, u8 size, u8 lock); +int sc_seco_get_mp_key(sc_ipc_t ipc, sc_faddr_t dst_addr, + u16 dst_size); +int sc_seco_update_mpmr(sc_ipc_t ipc, sc_faddr_t addr, + u8 size, u8 lock); int sc_seco_get_mp_sign(sc_ipc_t ipc, sc_faddr_t msg_addr, u16 msg_size, sc_faddr_t dst_addr, u16 dst_size); -int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data); int sc_seco_secvio_config(sc_ipc_t ipc, u8 id, u8 access, - u32 *data0, u32 *data1, u32 *data2, u32 *data3, - u32 *data4, u8 size); + u32 *data0, u32 *data1, u32 *data2, u32 *data3, + u32 *data4, u8 size); +int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, + u32 *data); #endif diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h new file mode 100644 index 00000000000..f701e601331 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/irq/api.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + +#ifndef SC_IRQ_API_H +#define SC_IRQ_API_H + +/* Defines */ + +#define SC_IRQ_NUM_GROUP 7U /* Number of groups */ + +/* Defines for sc_irq_group_t */ +#define SC_IRQ_GROUP_TEMP 0U /* Temp interrupts */ +#define SC_IRQ_GROUP_WDOG 1U /* Watchdog interrupts */ +#define SC_IRQ_GROUP_RTC 2U /* RTC interrupts */ +#define SC_IRQ_GROUP_WAKE 3U /* Wakeup interrupts */ +#define SC_IRQ_GROUP_SYSCTR 4U /* System counter interrupts */ +#define SC_IRQ_GROUP_REBOOTED 5U /* Partition reboot complete */ +#define SC_IRQ_GROUP_REBOOT 6U /* Partition reboot starting */ + +/* Defines for sc_irq_temp_t */ +#define SC_IRQ_TEMP_HIGH (1UL << 0U) /* Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_HIGH (1UL << 1U) /* CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_HIGH (1UL << 2U) /* CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_HIGH (1UL << 3U) /* GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_HIGH (1UL << 4U) /* GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_HIGH (1UL << 5U) /* DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_HIGH (1UL << 6U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_HIGH (1UL << 7U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_HIGH (1UL << 8U) /* PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_HIGH (1UL << 9U) /* PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_LOW (1UL << 10U) /* Temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU0_LOW (1UL << 11U) /* CPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_CPU1_LOW (1UL << 12U) /* CPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU0_LOW (1UL << 13U) /* GPU0 temp alarm interrupt */ +#define SC_IRQ_TEMP_GPU1_LOW (1UL << 14U) /* GPU1 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC0_LOW (1UL << 15U) /* DRC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_DRC1_LOW (1UL << 16U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_VPU_LOW (1UL << 17U) /* DRC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC0_LOW (1UL << 18U) /* PMIC0 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC1_LOW (1UL << 19U) /* PMIC1 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_HIGH (1UL << 20U) /* PMIC2 temp alarm interrupt */ +#define SC_IRQ_TEMP_PMIC2_LOW (1UL << 21U) /* PMIC2 temp alarm interrupt */ + +/* Defines for sc_irq_wdog_t */ +#define SC_IRQ_WDOG (1U << 0U) /* Watchdog interrupt */ + +/* Defines for sc_irq_rtc_t */ +#define SC_IRQ_RTC (1U << 0U) /* RTC interrupt */ + +/* Defines for sc_irq_wake_t */ +#define SC_IRQ_BUTTON (1U << 0U) /* Button interrupt */ +#define SC_IRQ_PAD (1U << 1U) /* Pad wakeup */ +#define SC_IRQ_USR1 (1U << 2U) /* User defined 1 */ +#define SC_IRQ_USR2 (1U << 3U) /* User defined 2 */ +#define SC_IRQ_BC_PAD (1U << 4U) /* Pad wakeup (broadcast to all partitions) */ +#define SC_IRQ_SW_WAKE (1U << 5U) /* Software requested wake */ +#define SC_IRQ_SECVIO (1U << 6U) /* Security violation */ + +/* Defines for sc_irq_sysctr_t */ +#define SC_IRQ_SYSCTR (1U << 0U) /* SYSCTR interrupt */ + +/* Types */ + +/* + * This type is used to declare an interrupt group. + */ +typedef u8 sc_irq_group_t; + +/* + * This type is used to declare a bit mask of temp interrupts. + */ +typedef u8 sc_irq_temp_t; + +/* + * This type is used to declare a bit mask of watchdog interrupts. + */ +typedef u8 sc_irq_wdog_t; + +/* + * This type is used to declare a bit mask of RTC interrupts. + */ +typedef u8 sc_irq_rtc_t; + +/* + * This type is used to declare a bit mask of wakeup interrupts. + */ +typedef u8 sc_irq_wake_t; + +#endif /* SC_IRQ_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h index 3629eb68d7a..a4b92b86cc6 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/misc/api.h @@ -5,27 +5,45 @@ #ifndef SC_MISC_API_H #define SC_MISC_API_H +/* Defines for type widths */ +#define SC_MISC_DMA_GRP_W 5U /* Width of sc_misc_dma_group_t */ +/* Max DMA channel priority group */ +#define SC_MISC_DMA_GRP_MAX 31U /* Defines for sc_misc_boot_status_t */ #define SC_MISC_BOOT_STATUS_SUCCESS 0U /* Success */ #define SC_MISC_BOOT_STATUS_SECURITY 1U /* Security violation */ -/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_SECO_AUTH_SECO_FW 0U /* SECO Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_TX_FW 1U /* HDMI TX Firmware */ -#define SC_MISC_SECO_AUTH_HDMI_RX_FW 2U /* HDMI RX Firmware */ - /* Defines for sc_misc_temp_t */ -#define SC_MISC_TEMP 0U /* Temp sensor */ -#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ -#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ +#define SC_MISC_TEMP 0U /* Temp sensor */ +#define SC_MISC_TEMP_HIGH 1U /* Temp high alarm */ +#define SC_MISC_TEMP_LOW 2U /* Temp low alarm */ + +/* Defines for sc_misc_bt_t */ +#define SC_MISC_BT_PRIMARY 0U /* Primary boot */ +#define SC_MISC_BT_SECONDARY 1U /* Secondary boot */ +#define SC_MISC_BT_RECOVERY 2U /* Recovery boot */ +#define SC_MISC_BT_MANUFACTURE 3U /* Manufacture boot */ +#define SC_MISC_BT_SERIAL 4U /* Serial boot */ +/* Types */ -/* Defines for sc_misc_seco_auth_cmd_t */ -#define SC_MISC_AUTH_CONTAINER 0U /* Authenticate container */ -#define SC_MISC_VERIFY_IMAGE 1U /* Verify image */ -#define SC_MISC_REL_CONTAINER 2U /* Release container */ +/* + * This type is used to store a DMA channel priority group. + */ +typedef u8 sc_misc_dma_group_t; +/* + * This type is used report boot status. + */ typedef u8 sc_misc_boot_status_t; + +/* + * This type is used report boot status. + */ typedef u8 sc_misc_temp_t; +/* + * This type is used report the boot type. + */ +typedef u8 sc_misc_bt_t; #endif /* SC_MISC_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h index 9008b85c6f6..95956d74ffd 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/pm/api.h @@ -6,6 +6,14 @@ #ifndef SC_PM_API_H #define SC_PM_API_H +#include +/* Defines for type widths */ +#define SC_PM_POWER_MODE_W 2U /* Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3U /* Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2U /* Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 4U /* Width of sc_pm_reset_reason_t */ +/* Defines for ALL parameters */ +#define SC_PM_CLK_ALL ((sc_pm_clk_t) UINT8_MAX) /* All clocks */ /* Defines for sc_pm_power_mode_t */ #define SC_PM_PW_MODE_OFF 0U /* Power off */ #define SC_PM_PW_MODE_STBY 1U /* Power in standby */ @@ -35,10 +43,91 @@ #define SC_PM_CLK_MODE_AUTOGATE_HW 4U /* Clock is in HW autogate mode */ #define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5U /* Clock is in SW-HW autogate mode */ +/* Defines for sc_pm_clk_parent_t */ +#define SC_PM_PARENT_XTAL 0U /*!< Parent is XTAL. */ +#define SC_PM_PARENT_PLL0 1U /*!< Parent is PLL0 */ +#define SC_PM_PARENT_PLL1 2U /*!< Parent is PLL1 or PLL0/2 */ +#define SC_PM_PARENT_PLL2 3U /*!< Parent in PLL2 or PLL0/4 */ +#define SC_PM_PARENT_BYPS 4U /*!< Parent is a bypass clock. */ + +/* Defines for sc_pm_reset_type_t */ +#define SC_PM_RESET_TYPE_COLD 0U /* Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1U /* Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2U /* Board reset */ + +/* Defines for sc_pm_reset_reason_t */ +#define SC_PM_RESET_REASON_POR 0U /* Power on reset */ +#define SC_PM_RESET_REASON_JTAG 1U /* JTAG reset */ +#define SC_PM_RESET_REASON_SW 2U /* Software reset */ +#define SC_PM_RESET_REASON_WDOG 3U /* Partition watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4U /* SCU lockup reset */ +#define SC_PM_RESET_REASON_SNVS 5U /* SNVS reset */ +#define SC_PM_RESET_REASON_TEMP 6U /* Temp panic reset */ +#define SC_PM_RESET_REASON_MSI 7U /* MSI reset */ +#define SC_PM_RESET_REASON_UECC 8U /* ECC reset */ +#define SC_PM_RESET_REASON_SCFW_WDOG 9U /* SCFW watchdog reset */ +#define SC_PM_RESET_REASON_ROM_WDOG 10U /* SCU ROM watchdog reset */ +#define SC_PM_RESET_REASON_SECO 11U /* SECO reset */ +#define SC_PM_RESET_REASON_SCFW_FAULT 12U /* SCFW fault reset */ + +/* Defines for sc_pm_sys_if_t */ +#define SC_PM_SYS_IF_INTERCONNECT 0U /* System interconnect */ +#define SC_PM_SYS_IF_MU 1U /* AP -> SCU message units */ +#define SC_PM_SYS_IF_OCMEM 2U /* On-chip memory (ROM/OCRAM) */ +#define SC_PM_SYS_IF_DDR 3U /* DDR memory */ + +/* Defines for sc_pm_wake_src_t */ +#define SC_PM_WAKE_SRC_NONE 0U /* No wake source, used for self-kill */ +#define SC_PM_WAKE_SRC_SCU 1U /* Wakeup from SCU to resume CPU (IRQSTEER & GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER 2U /* Wakeup from IRQSTEER to resume CPU (GIC powered down) */ +#define SC_PM_WAKE_SRC_IRQSTEER_GIC 3U /* Wakeup from IRQSTEER+GIC to wake CPU (GIC clock gated) */ +#define SC_PM_WAKE_SRC_GIC 4U /* Wakeup from GIC to wake CPU */ +/* Types */ + +/* + * This type is used to declare a power mode. Note resources only use + * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only + * as system power modes. + */ typedef u8 sc_pm_power_mode_t; + +/* + * This type is used to declare a clock. + */ typedef u8 sc_pm_clk_t; + +/* + * This type is used to declare a clock mode. + */ typedef u8 sc_pm_clk_mode_t; + +/* + * This type is used to declare the clock parent. + */ typedef u8 sc_pm_clk_parent_t; + +/* + * This type is used to declare clock rates. + */ typedef u32 sc_pm_clock_rate_t; +/* + * This type is used to declare a desired reset type. + */ +typedef u8 sc_pm_reset_type_t; + +/* + * This type is used to declare a reason for a reset. + */ +typedef u8 sc_pm_reset_reason_t; + +/* + * This type is used to specify a system-level interface to be power managed. + */ +typedef u8 sc_pm_sys_if_t; + +/* + * This type is used to specify a wake source for CPU resources. + */ +typedef u8 sc_pm_wake_src_t; #endif /* SC_PM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h index ed303881e73..bbc9de90162 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/rm/api.h @@ -38,32 +38,36 @@ /* Types */ -/*! +/* * This type is used to declare a resource partition. */ typedef u8 sc_rm_pt_t; -/*! +/* * This type is used to declare a memory region. */ typedef u8 sc_rm_mr_t; -/*! +/* * This type is used to declare a resource domain ID used by the * isolation HW. */ typedef u8 sc_rm_did_t; -/*! +/* * This type is used to declare an SMMU StreamID. */ typedef u16 sc_rm_sid_t; -/*! +/* * This type is a used to declare master transaction attributes. */ typedef u8 sc_rm_spa_t; +/* + * This type is used to declare a resource/memory region access permission. + * Refer to the XRDC2 Block Guide for more information. + */ typedef u8 sc_rm_perm_t; #endif /* SC_RM_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h index 3ed05842d99..5963330d3ae 100644 --- a/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h +++ b/arch/arm/include/asm/arch-imx8/sci/svc/seco/api.h @@ -17,6 +17,7 @@ #define SC_SECO_AUTH_SECO_FW 3U /* SECO Firmware */ #define SC_SECO_AUTH_HDMI_TX_FW 4U /* HDMI TX Firmware */ #define SC_SECO_AUTH_HDMI_RX_FW 5U /* HDMI RX Firmware */ +#define SC_SECO_EVERIFY_IMAGE 6U /* Enhanced verify image */ #define SC_SECO_RNG_STAT_UNAVAILABLE 0U /* Unable to initialize the RNG */ #define SC_SECO_RNG_STAT_INPROGRESS 1U /* Initialization is on-going */ @@ -24,12 +25,12 @@ /* Types */ -/*! +/* * This type is used to issue SECO authenticate commands. */ typedef u8 sc_seco_auth_cmd_t; -/*! +/* * This type is used to return the RNG initialization status. */ typedef u32 sc_seco_rng_stat_t; diff --git a/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h new file mode 100644 index 00000000000..d5750444b30 --- /dev/null +++ b/arch/arm/include/asm/arch-imx8/sci/svc/timer/api.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018-2019 NXP + */ + + +#ifndef SC_TIMER_API_H +#define SC_TIMER_API_H + +/* Defines */ + +/* Defines for type widths */ +#define SC_TIMER_ACTION_W 3U /* Width of sc_timer_wdog_action_t */ + +/* Defines for sc_timer_wdog_action_t */ +#define SC_TIMER_WDOG_ACTION_PARTITION 0U /* Reset partition */ +#define SC_TIMER_WDOG_ACTION_WARM 1U /* Warm reset system */ +#define SC_TIMER_WDOG_ACTION_COLD 2U /* Cold reset system */ +#define SC_TIMER_WDOG_ACTION_BOARD 3U /* Reset board */ +#define SC_TIMER_WDOG_ACTION_IRQ 4U /* Only generate IRQs */ + +/* Types */ + +/* + * This type is used to configure the watchdog action. + */ +typedef u8 sc_timer_wdog_action_t; + +/* + * This type is used to declare a watchdog time value in milliseconds. + */ +typedef u32 sc_timer_wdog_time_t; + +#endif /* SC_TIMER_API_H */ diff --git a/arch/arm/include/asm/arch-imx8/sci/types.h b/arch/arm/include/asm/arch-imx8/sci/types.h index adfed13e330..36d5dee96e3 100644 --- a/arch/arm/include/asm/arch-imx8/sci/types.h +++ b/arch/arm/include/asm/arch-imx8/sci/types.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 NXP + * Copyright 2018-2020 NXP */ #ifndef SC_TYPES_H @@ -19,6 +19,7 @@ typedef u64 sc_ipc_t; /* Defines for common frequencies */ #define SC_32KHZ 32768U /* 32KHz */ #define SC_10MHZ 10000000U /* 10MHz */ +#define SC_16MHZ 16000000U /* 16MHz */ #define SC_20MHZ 20000000U /* 20MHz */ #define SC_25MHZ 25000000U /* 25MHz */ #define SC_27MHZ 27000000U /* 27MHz */ @@ -58,21 +59,33 @@ typedef u64 sc_ipc_t; #define SC_594MHZ 594000000U /* 594MHz */ #define SC_625MHZ 625000000U /* 625MHz */ #define SC_640MHZ 640000000U /* 640MHz */ +#define SC_648MHZ 648000000U /* 648MHz */ #define SC_650MHZ 650000000U /* 650MHz */ #define SC_667MHZ 666666667U /* 667MHz */ #define SC_675MHZ 675000000U /* 675MHz */ #define SC_700MHZ 700000000U /* 700MHz */ #define SC_720MHZ 720000000U /* 720MHz */ #define SC_750MHZ 750000000U /* 750MHz */ +#define SC_753MHZ 753000000U /* 753MHz */ +#define SC_793MHZ 793000000U /* 793MHz */ #define SC_800MHZ 800000000U /* 800MHz */ #define SC_850MHZ 850000000U /* 850MHz */ +#define SC_858MHZ 858000000U /* 858MHz */ #define SC_900MHZ 900000000U /* 900MHz */ +#define SC_953MHZ 953000000U /* 953MHz */ +#define SC_963MHZ 963000000U /* 963MHz */ #define SC_1000MHZ 1000000000U /* 1GHz */ #define SC_1060MHZ 1060000000U /* 1.06GHz */ +#define SC_1068MHZ 1068000000U /* 1.068GHz */ +#define SC_1121MHZ 1121000000U /* 1.121GHz */ +#define SC_1173MHZ 1173000000U /* 1.173GHz */ #define SC_1188MHZ 1188000000U /* 1.188GHz */ #define SC_1260MHZ 1260000000U /* 1.26GHz */ +#define SC_1278MHZ 1278000000U /* 1.278GHz */ #define SC_1280MHZ 1280000000U /* 1.28GHz */ #define SC_1300MHZ 1300000000U /* 1.3GHz */ +#define SC_1313MHZ 1313000000U /* 1.313GHz */ +#define SC_1345MHZ 1345000000U /* 1.345GHz */ #define SC_1400MHZ 1400000000U /* 1.4GHz */ #define SC_1500MHZ 1500000000U /* 1.5GHz */ #define SC_1600MHZ 1600000000U /* 1.6GHz */ @@ -119,7 +132,6 @@ typedef u64 sc_ipc_t; #define SC_755MHZ 755250000U /* 755.25MHz */ /* Defines for type widths */ -#define SC_FADDR_W 36U /* Width of sc_faddr_t */ #define SC_BOOL_W 1U /* Width of sc_bool_t */ #define SC_ERR_W 4U /* Width of sc_err_t */ #define SC_RSRC_W 10U /* Width of sc_rsrc_t */ @@ -191,9 +203,23 @@ typedef u64 sc_ipc_t; #define SC_C_RST0 43U #define SC_C_RST1 44U #define SC_C_SEL0 45U -#define SC_C_LAST 46U - -#define SC_P_ALL ((sc_pad_t)UINT16_MAX) /* All pads */ +#define SC_C_CALIB0 46U +#define SC_C_CALIB1 47U +#define SC_C_CALIB2 48U +#define SC_C_IPG_DEBUG 49U +#define SC_C_IPG_DOZE 50U +#define SC_C_IPG_WAIT 51U +#define SC_C_IPG_STOP 52U +#define SC_C_IPG_STOP_MODE 53U +#define SC_C_IPG_STOP_ACK 54U +#define SC_C_SYNC_CTRL 55U +#define SC_C_OFS_AUDIO_ALT 56U +#define SC_C_DSP_BYP 57U +#define SC_C_CLK_GEN_EN 58U +#define SC_C_INTF_SEL 59U +#define SC_C_RXC_DLY 60U +#define SC_C_TIMER_SEL 61U +#define SC_C_LAST 62U /* Types */ diff --git a/arch/arm/include/asm/arch-imx8/sys_proto.h b/arch/arm/include/asm/arch-imx8/sys_proto.h index 6f1fc8f999d..e4bd2961730 100644 --- a/arch/arm/include/asm/arch-imx8/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8/sys_proto.h @@ -21,7 +21,7 @@ struct pass_over_info_t { u32 g_ap_mu; }; -extern unsigned long boot_pointer[]; +extern unsigned long rom_pointer[]; void build_info(void); enum boot_device get_boot_device(void); int print_bootinfo(void); diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h index c545eb82b69..197b9b06269 100644 --- a/arch/arm/include/asm/arch-imx8m/clock.h +++ b/arch/arm/include/asm/arch-imx8m/clock.h @@ -253,11 +253,16 @@ void dram_pll_init(ulong pll_val); void dram_enable_bypass(ulong clk_val); void dram_disable_bypass(void); u32 imx_get_fecclk(void); +u32 imx_get_eqos_csr_clk(void); +int imx_eqos_txclk_set_rate(unsigned long rate); u32 imx_get_uartclk(void); int clock_init(void); void init_clk_usdhc(u32 index); +void init_nand_clk(void); void init_uart_clk(u32 index); +void init_usb_clk(void); void init_wdog_clk(void); +void init_clk_ecspi(u32 index); unsigned int mxc_get_clock(enum mxc_clock clk); int clock_enable(enum clk_ccgr_index index, bool enable); int clock_root_enabled(enum clk_root_index clock_id); @@ -271,7 +276,10 @@ int clock_get_postdiv(enum clk_root_index clock_id, int clock_get_src(enum clk_root_index clock_id, enum clk_root_src *p_clock_src); void mxs_set_lcdclk(u32 base_addr, u32 freq); int set_clk_qspi(void); +void init_clk_fspi(int index); void enable_ocotp_clk(unsigned char enable); int enable_i2c_clk(unsigned char enable, unsigned int i2c_num); int set_clk_enet(enum enet_freq type); int set_clk_eqos(enum enet_freq type); +void hab_caam_clock_enable(unsigned char enable); +void enable_usboh3_clk(unsigned char enable); diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 3f500146185..51717a172ee 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -13,57 +13,222 @@ #define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800 #define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800 -#define M4_BOOTROM_BASE_ADDR 0x007E0000 - -#define GPIO1_BASE_ADDR 0X30200000 +#define MCU_BOOTROM_BASE_ADDR 0x007E0000 + +#define SAI1_BASE_ADDR 0x30010000 +#define SAI6_BASE_ADDR 0x30030000 +#define SAI5_BASE_ADDR 0x30040000 +#define SAI4_BASE_ADDR 0x30050000 +#define SPBA2_BASE_ADDR 0x300F0000 +#define AIPS1_BASE_ADDR 0x301F0000 +#define GPIO1_BASE_ADDR 0x30200000 #define GPIO2_BASE_ADDR 0x30210000 #define GPIO3_BASE_ADDR 0x30220000 #define GPIO4_BASE_ADDR 0x30230000 #define GPIO5_BASE_ADDR 0x30240000 +#define ANA_TSENSOR_ADDR 0x30260000 +#define ANA_OSC_BASE_ADDR 0x30270000 #define WDOG1_BASE_ADDR 0x30280000 #define WDOG2_BASE_ADDR 0x30290000 #define WDOG3_BASE_ADDR 0x302A0000 +#ifdef CONFIG_IMX8MP +#define OCRAM_MECC_BASE_ADDR 0x302B0000 +#define OCRAM_S_MECC_BASE_ADDR 0x302C0000 +#else +#define SDMA3_BASE_ADDR 0x302B0000 +#define SDMA2_BASE_ADDR 0x302C0000 +#endif +#define GPT1_BASE_ADDR 0x302D0000 +#define GPT2_BASE_ADDR 0x302E0000 +#define GPT3_BASE_ADDR 0x302F0000 +#define ROMCP_BASE_ADDR 0x30310000 +#define LCDIF_BASE_ADDR_IMX8MQ 0x30320000 #define IOMUXC_BASE_ADDR 0x30330000 #define IOMUXC_GPR_BASE_ADDR 0x30340000 #define OCOTP_BASE_ADDR 0x30350000 #define ANATOP_BASE_ADDR 0x30360000 +#define SNVS_HP_BASE_ADDR 0x30370000 #define CCM_BASE_ADDR 0x30380000 #define SRC_BASE_ADDR 0x30390000 #define GPC_BASE_ADDR 0x303A0000 - +#define SEMA1_BASE_ADDR 0x303B0000 +#define SEMA2_BASE_ADDR 0x303C0000 +#define RDC_BASE_ADDR 0x303D0000 +#define CSU_BASE_ADDR 0x303E0000 + +#define AIPS2_BASE_ADDR 0x305F0000 +#define PWM1_BASE_ADDR 0x30660000 +#define PWM2_BASE_ADDR 0x30670000 +#define PWM3_BASE_ADDR 0x30680000 +#define PWM4_BASE_ADDR 0x30690000 #define SYSCNT_RD_BASE_ADDR 0x306A0000 #define SYSCNT_CMP_BASE_ADDR 0x306B0000 #define SYSCNT_CTRL_BASE_ADDR 0x306C0000 - +#define GPT6_BASE_ADDR 0x306E0000 +#define GPT5_BASE_ADDR 0x306F0000 +#define GPT4_BASE_ADDR 0x30700000 +#define PERFMON1_ADDR 0x307C0000 +#define PERFMON2_ADDR 0x307D0000 +#define QOSC_BASE_ADDR 0x307F0000 + +#define SPDIF1_BASE_ADDR 0x30810000 +#define ECSPI1_BASE_ADDR 0x30820000 +#define ECSPI2_BASE_ADDR 0x30830000 +#define ECSPI3_BASE_ADDR 0x30840000 #define UART1_BASE_ADDR 0x30860000 #define UART3_BASE_ADDR 0x30880000 #define UART2_BASE_ADDR 0x30890000 + +#define SPDIF2_BASE_ADDR 0x308A0000 +#define SAI2_BASE_ADDR 0x308B0000 +#define SAI3_BASE_ADDR 0x308C0000 +#define CANFD1_BASE_ADDR 0x308C0000 +#define CANFD2_BASE_ADDR 0x308D0000 +#define SPBA_BASE_ADDR 0x308F0000 +#define CAAM_BASE_ADDR 0x30900000 +#define AIPS3_BASE_ADDR 0x309F0000 +#define MIPI_PHY_BASE_ADDR_IMX8MQ 0x30A00000 +#define MIPI_DSI_BASE_ADDR_IMX8MQ 0x30A10000 #define I2C1_BASE_ADDR 0x30A20000 #define I2C2_BASE_ADDR 0x30A30000 #define I2C3_BASE_ADDR 0x30A40000 #define I2C4_BASE_ADDR 0x30A50000 #define UART4_BASE_ADDR 0x30A60000 +#define MIPI_CSI_BASE_ADDR_IMX8MQ 0x30A70000 +#define MIPI_CSI_PHY1_BASE_ADDR_IMX8MQ 0x30A80000 +#define IRQ_STEER_BASE_ADDR 0x30A80000 +#define CSI1_BASE_ADDR_IMX8MQ 0x30A90000 +#define MU_A_BASE_ADDR 0x30AA0000 +#define MU_B_BASE_ADDR 0x30AB0000 +#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000 +#define I2C5_BASE_ADDR 0x30AD0000 +#define I2C6_BASE_ADDR 0x30AE0000 #define USDHC1_BASE_ADDR 0x30B40000 #define USDHC2_BASE_ADDR 0x30B50000 -#ifdef CONFIG_IMX8MM #define USDHC3_BASE_ADDR 0x30B60000 -#endif +#define MIPI_CS2_BASE_ADDR 0x30B60000 +#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000 +#define CSI2_BASE_ADDR 0x30B80000 +#define QSPI0_BASE_ADDR 0x30BB0000 +#define QSPI0_AMBA_BASE 0x08000000 +#define SDMA1_BASE_ADDR 0x30BD0000 +#define ENET1_BASE_ADDR 0x30BE0000 +#define ENET2_TSN_BASE_ADDR 0x30BF0000 +#define HDMI_CTRL_BASE_ADDR 0x32C00000 +#define AIPS4_BASE_ADDR 0x32DF0000 +#ifdef CONFIG_IMX8MQ +#define DC1_BASE_ADDR 0x32E00000 +#define DC2_BASE_ADDR 0x32E10000 +#define DC3_BASE_ADDR 0x32E20000 +#define HDMI_SEC_BASE_ADDR 0x32E40000 +#define TZASC_BASE_ADDR 0x32F80000 +#define MTR_BASE_ADDR 0x32FB0000 +#define PLATFORM_CTRL_BASE_ADDR 0x32FE0000 + +#define USB1_BASE_ADDR 0x38100000 +#define USB2_BASE_ADDR 0x38200000 +#define USB1_PHY_BASE_ADDR 0x381F0000 +#define USB2_PHY_BASE_ADDR 0x382F0000 + +#elif defined(CONFIG_IMX8MP) +#define ISI_BASE_ADDR 0x32E00000 +#define ISP1_BASE_ADDR 0x32E10000 +#define ISP2_BASE_ADDR 0x32E20000 +#define IPS_DEWARP_BASE_ADDR 0x32E30000 +#define MIPI_CSI1_BASE_ADDR 0x32E40000 +#define MIPI_CSI2_BASE_ADDR 0x32E50000 +#define MIPI_DSI_BASE_ADDR 0x32E60000 +#define LCDIF1_BASE_ADDR 0x32E80000 +#define LCDIF2_BASE_ADDR 0x32E90000 +#define LCDIF_BASE_ADDR LCDIF1_BASE_ADDR +#define LVDS1_BASE_ADDR 0x32EA0000 +#define LVDS2_BASE_ADDR 0x32EB0000 +#define MEDIAMIX_CTRL_BASE_ADDR 0x32EC0000 +#define PCIE_PHY1_BASE_ADDR 0x32F00000 +#define HSIOMIX_CTRL_BASE_ADDR 0x32F10000 +#define TZASC_BASE_ADDR 0x32F80000 +#define HDMI_TX_BASE_ADDR 0x32FC0000 +#define NOC_CTRL_BASE_ADDR 0x32FE0000 +#define USB1_BASE_ADDR 0x38100000 +#define USB2_BASE_ADDR 0x38200000 +#define USB1_PHY_BASE_ADDR 0x381F0000 +#define USB2_PHY_BASE_ADDR 0x382F0000 + +#else +#define LCDIF_BASE_ADDR 0x32E00000 +#define MIPI_DSI_BASE_ADDR 0x32E10000 +#define CSI_BASE_ADDR 0x32E20000 +#define ISI_BASE_ADDR 0x32E20000 +#define MIPI_CSI_BASE_ADDR 0x32E30000 +#define USB1_BASE_ADDR 0x32E40000 +#define USB2_BASE_ADDR 0x32E50000 +#define PCIE_PHY1_BASE_ADDR 0x32F00000 #define TZASC_BASE_ADDR 0x32F80000 +#define PLAT_CTRL_BASE_ADDR 0x32FE0000 +#endif + +#define MXS_APBH_BASE 0x33000000 +#define MXS_GPMI_BASE 0x33002000 +#define MXS_BCH_BASE 0x33004000 + + +#define USB_BASE_ADDR USB1_BASE_ADDR #define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \ - 0x30320000 : 0x32e00000 + LCDIF_BASE_ADDR_IMX8MQ : LCDIF_BASE_ADDR + +#define IOMUXC_GPR0 (IOMUXC_GPR_BASE_ADDR + 0x00) +#define IOMUXC_GPR1 (IOMUXC_GPR_BASE_ADDR + 0x04) +#define IOMUXC_GPR2 (IOMUXC_GPR_BASE_ADDR + 0x08) +#define IOMUXC_GPR3 (IOMUXC_GPR_BASE_ADDR + 0x0c) +#define IOMUXC_GPR4 (IOMUXC_GPR_BASE_ADDR + 0x10) +#define IOMUXC_GPR5 (IOMUXC_GPR_BASE_ADDR + 0x14) +#define IOMUXC_GPR6 (IOMUXC_GPR_BASE_ADDR + 0x18) +#define IOMUXC_GPR7 (IOMUXC_GPR_BASE_ADDR + 0x1c) +#define IOMUXC_GPR8 (IOMUXC_GPR_BASE_ADDR + 0x20) +#define IOMUXC_GPR9 (IOMUXC_GPR_BASE_ADDR + 0x24) +#define IOMUXC_GPR10 (IOMUXC_GPR_BASE_ADDR + 0x28) +#define IOMUXC_GPR11 (IOMUXC_GPR_BASE_ADDR + 0x2C) +#define IOMUXC_GPR22 (IOMUXC_GPR_BASE_ADDR + 0x58) + +#define CNTCR_OFF 0x00 +#define CNTFID0_OFF 0x20 +#define CNTFID1_OFF 0x24 + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + +#define IMX_CSPI1_BASE 0x30820000 +#define IMX_CSPI2_BASE 0x30830000 +#define IMX_CSPI3_BASE 0x30840000 + +#define MXC_SPI_BASE_ADDRESSES \ + IMX_CSPI1_BASE, \ + IMX_CSPI2_BASE, \ + IMX_CSPI3_BASE #define SRC_IPS_BASE_ADDR 0x30390000 #define SRC_DDRC_RCR_ADDR 0x30391000 #define SRC_DDRC2_RCR_ADDR 0x30391004 +#define SRC_DDR1_ENABLE_MASK 0x8F000000UL #define DDRC_DDR_SS_GPR0 0x3d000000 #define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000)) #define DDR_CSD1_BASE_ADDR 0x40000000 -#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 -#define FEC_QUIRK_ENET_MAC +#define CAAM_ARB_BASE_ADDR (0x00100000) +#define CAAM_ARB_END_ADDR (0x00107FFF) +#define CAAM_IPS_BASE_ADDR (0x30900000) +#define CONFIG_SYS_FSL_SEC_OFFSET (0) +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #if !defined(__ASSEMBLY__) #include @@ -84,8 +249,15 @@ #define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1) #define SRC_DDR1_RCR_PRESET_N_MASK BIT(0) +#define FEC_QUIRK_ENET_MAC +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u +#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000 + +#define SNVS_HPSR (SNVS_HP_BASE_ADDR + 0x14) + struct iomuxc_gpr_base_regs { - u32 gpr[47]; + u32 gpr[48]; }; struct ocotp_regs { @@ -120,6 +292,16 @@ struct ocotp_regs { } bank[0]; }; +#ifdef CONFIG_IMX8MP +struct fuse_bank0_regs { + u32 lock; + u32 rsvd0[7]; + u32 uid_low; + u32 rsvd1[3]; + u32 uid_high; + u32 rsvd2[3]; +}; +#else struct fuse_bank0_regs { u32 lock; u32 rsvd0[3]; @@ -128,6 +310,7 @@ struct fuse_bank0_regs { u32 uid_high; u32 rsvd2[7]; }; +#endif struct fuse_bank1_regs { u32 tester3; @@ -492,5 +675,17 @@ struct pgc_reg { u32 pgauxsw; u32 pgdr; }; + + +#include +bool is_usb_boot(void); +#define is_boot_from_usb is_usb_boot + +#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8MQ) +#define disconnect_from_pc(void) clrbits_le32(USB1_BASE_ADDR + 0xc704, (1 << 31)); +#else +#define disconnect_from_pc(void) writel(0x0, USB1_BASE_ADDR + 0x140) +#endif + #endif #endif diff --git a/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h b/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h new file mode 100644 index 00000000000..7a59b30d87d --- /dev/null +++ b/arch/arm/include/asm/arch-imx8m/imx8m_ddr.h @@ -0,0 +1,8 @@ +#ifndef __IMX8M_DDR_H_ +#define __IMX8M_DDR_H___ + +#include +#include +#include + +#endif /* __IMX8M_DDR_H___ */ diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h index 210e96e1dbe..a1111b92418 100644 --- a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h +++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h @@ -612,12 +612,12 @@ enum { IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0), IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0), IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), - IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0), + IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0), IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0), IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h index b4298f2b838..fd44f1b5cfe 100644 --- a/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h +++ b/arch/arm/include/asm/arch-imx8m/imx8mn_pins.h @@ -10,10 +10,10 @@ enum { IMX8MN_PAD_BOOT_MODE2__CCMSRCGPCMIX_BOOT_MODE2 = IOMUX_PAD(0x025C, 0x0020, 0, 0x0000, 0, 0), - IMX8MN_PAD_BOOT_MODE2__I2C1_SCL = IOMUX_PAD(0x025C, 0x0020, 1, 0x055C, 3, 0), + IMX8MN_PAD_BOOT_MODE2__I2C1_SCL = IOMUX_PAD(0x025C, 0x0020, 1 | IOMUX_CONFIG_SION, 0x055C, 3, 0), IMX8MN_PAD_BOOT_MODE3__CCMSRCGPCMIX_BOOT_MODE3 = IOMUX_PAD(0x0260, 0x0024, 0, 0x0000, 0, 0), - IMX8MN_PAD_BOOT_MODE3__I2C1_SDA = IOMUX_PAD(0x0260, 0x0024, 1, 0x056C, 3, 0), + IMX8MN_PAD_BOOT_MODE3__I2C1_SDA = IOMUX_PAD(0x0260, 0x0024, 1 | IOMUX_CONFIG_SION, 0x056C, 3, 0), IMX8MN_PAD_GPIO1_IO00__GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0), IMX8MN_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0), @@ -224,28 +224,28 @@ enum { IMX8MN_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0320, 0x00B8, 1, 0x0000, 0, 0), - IMX8MN_PAD_SD1_DATA4__I2C1_SCL = IOMUX_PAD(0x0320, 0x00B8, 3, 0x055C, 1, 0), + IMX8MN_PAD_SD1_DATA4__I2C1_SCL = IOMUX_PAD(0x0320, 0x00B8, 3 | IOMUX_CONFIG_SION, 0x055C, 1, 0), IMX8MN_PAD_SD1_DATA4__UART2_DCE_RTS_B = IOMUX_PAD(0x0320, 0x00B8, 4, 0x04F8, 4, 0), IMX8MN_PAD_SD1_DATA4__UART2_DTE_CTS_B = IOMUX_PAD(0x0320, 0x00B8, 4, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA4__GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA5__ENET1_TX_ER = IOMUX_PAD(0x0324, 0x00BC, 1, 0x0000, 0, 0), - IMX8MN_PAD_SD1_DATA5__I2C1_SDA = IOMUX_PAD(0x0324, 0x00BC, 3, 0x056C, 1, 0), + IMX8MN_PAD_SD1_DATA5__I2C1_SDA = IOMUX_PAD(0x0324, 0x00BC, 3 | IOMUX_CONFIG_SION, 0x056C, 1, 0), IMX8MN_PAD_SD1_DATA5__UART2_DCE_CTS_B = IOMUX_PAD(0x0324, 0x00BC, 4, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA5__UART2_DTE_RTS_B = IOMUX_PAD(0x0324, 0x00BC, 4, 0x04F8, 5, 0), IMX8MN_PAD_SD1_DATA5__GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x0328, 0x00C0, 1, 0x0574, 1, 0), - IMX8MN_PAD_SD1_DATA6__I2C2_SCL = IOMUX_PAD(0x0328, 0x00C0, 3, 0x05D0, 1, 0), + IMX8MN_PAD_SD1_DATA6__I2C2_SCL = IOMUX_PAD(0x0328, 0x00C0, 3 | IOMUX_CONFIG_SION, 0x05D0, 1, 0), IMX8MN_PAD_SD1_DATA6__UART3_DCE_TX = IOMUX_PAD(0x0328, 0x00C0, 4, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA6__UART3_DTE_RX = IOMUX_PAD(0x0328, 0x00C0, 4, 0x0504, 4, 0), IMX8MN_PAD_SD1_DATA6__GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA7__ENET1_RX_ER = IOMUX_PAD(0x032C, 0x00C4, 1, 0x05C8, 1, 0), - IMX8MN_PAD_SD1_DATA7__I2C2_SDA = IOMUX_PAD(0x032C, 0x00C4, 3, 0x0560, 1, 0), + IMX8MN_PAD_SD1_DATA7__I2C2_SDA = IOMUX_PAD(0x032C, 0x00C4, 3 | IOMUX_CONFIG_SION, 0x0560, 1, 0), IMX8MN_PAD_SD1_DATA7__UART3_DCE_RX = IOMUX_PAD(0x032C, 0x00C4, 4, 0x0504, 5, 0), IMX8MN_PAD_SD1_DATA7__UART3_DTE_TX = IOMUX_PAD(0x032C, 0x00C4, 4, 0x0000, 0, 0), IMX8MN_PAD_SD1_DATA7__GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0), @@ -253,13 +253,13 @@ enum { IMX8MN_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0), IMX8MN_PAD_SD1_RESET_B__ENET1_TX_CLK = IOMUX_PAD(0x0330, 0x00C8, 1, 0x05A4, 1, 0), IMX8MN_PAD_SD1_RESET_B__CCMSRCGPCMIX_ENET_REF_CLK_ROOT = IOMUX_PAD(0x0330, 0x00C8, 1, 0x05A4, 0, 0), - IMX8MN_PAD_SD1_RESET_B__I2C3_SCL = IOMUX_PAD(0x0330, 0x00C8, 3, 0x0588, 1, 0), + IMX8MN_PAD_SD1_RESET_B__I2C3_SCL = IOMUX_PAD(0x0330, 0x00C8, 3 | IOMUX_CONFIG_SION, 0x0588, 1, 0), IMX8MN_PAD_SD1_RESET_B__UART3_DCE_RTS_B = IOMUX_PAD(0x0330, 0x00C8, 4, 0x0500, 2, 0), IMX8MN_PAD_SD1_RESET_B__UART3_DTE_CTS_B = IOMUX_PAD(0x0330, 0x00C8, 4, 0x0000, 0, 0), IMX8MN_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0), IMX8MN_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0), - IMX8MN_PAD_SD1_STROBE__I2C3_SDA = IOMUX_PAD(0x0334, 0x00CC, 3, 0x05BC, 1, 0), + IMX8MN_PAD_SD1_STROBE__I2C3_SDA = IOMUX_PAD(0x0334, 0x00CC, 3 | IOMUX_CONFIG_SION, 0x05BC, 1, 0), IMX8MN_PAD_SD1_STROBE__UART3_DCE_CTS_B = IOMUX_PAD(0x0334, 0x00CC, 4, 0x0000, 0, 0), IMX8MN_PAD_SD1_STROBE__UART3_DTE_RTS_B = IOMUX_PAD(0x0334, 0x00CC, 4, 0x0500, 3, 0), IMX8MN_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0), @@ -288,7 +288,7 @@ enum { IMX8MN_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0), IMX8MN_PAD_SD2_DATA0__SAI5_RX_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 1, 0x04D4, 1, 0), - IMX8MN_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0344, 0x00DC, 2, 0x058C, 1, 0), + IMX8MN_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0344, 0x00DC, 2 | IOMUX_CONFIG_SION, 0x058C, 1, 0), IMX8MN_PAD_SD2_DATA0__UART2_DCE_RX = IOMUX_PAD(0x0344, 0x00DC, 3, 0x04FC, 6, 0), IMX8MN_PAD_SD2_DATA0__UART2_DTE_TX = IOMUX_PAD(0x0344, 0x00DC, 3, 0x0000, 0, 0), IMX8MN_PAD_SD2_DATA0__PDM_BIT_STREAM0 = IOMUX_PAD(0x0344, 0x00DC, 4, 0x0534, 2, 0), @@ -297,7 +297,7 @@ enum { IMX8MN_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0), IMX8MN_PAD_SD2_DATA1__SAI5_TX_SYNC = IOMUX_PAD(0x0348, 0x00E0, 1, 0x04EC, 1, 0), - IMX8MN_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x0348, 0x00E0, 2, 0x05D4, 1, 0), + IMX8MN_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x0348, 0x00E0, 2 | IOMUX_CONFIG_SION, 0x05D4, 1, 0), IMX8MN_PAD_SD2_DATA1__UART2_DCE_TX = IOMUX_PAD(0x0348, 0x00E0, 3, 0x0000, 0, 0), IMX8MN_PAD_SD2_DATA1__UART2_DTE_RX = IOMUX_PAD(0x0348, 0x00E0, 3, 0x04FC, 7, 0), IMX8MN_PAD_SD2_DATA1__PDM_BIT_STREAM1 = IOMUX_PAD(0x0348, 0x00E0, 4, 0x0538, 4, 0), @@ -348,7 +348,7 @@ enum { IMX8MN_PAD_NAND_CE1_B__QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0), IMX8MN_PAD_NAND_CE1_B__USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x059C, 0, 0), IMX8MN_PAD_NAND_CE1_B__PDM_BIT_STREAM0 = IOMUX_PAD(0x0364, 0x00FC, 3, 0x0534, 4, 0), - IMX8MN_PAD_NAND_CE1_B__I2C4_SCL = IOMUX_PAD(0x0364, 0x00FC, 4, 0x05D4, 2, 0), + IMX8MN_PAD_NAND_CE1_B__I2C4_SCL = IOMUX_PAD(0x0364, 0x00FC, 4 | IOMUX_CONFIG_SION, 0x05D4, 2, 0), IMX8MN_PAD_NAND_CE1_B__GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0), IMX8MN_PAD_NAND_CE1_B__CORESIGHT_TRACE0 = IOMUX_PAD(0x0364, 0x00FC, 6, 0x0000, 0, 0), @@ -356,7 +356,7 @@ enum { IMX8MN_PAD_NAND_CE2_B__QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0), IMX8MN_PAD_NAND_CE2_B__USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0550, 0, 0), IMX8MN_PAD_NAND_CE2_B__PDM_BIT_STREAM1 = IOMUX_PAD(0x0368, 0x0100, 3, 0x0538, 6, 0), - IMX8MN_PAD_NAND_CE2_B__I2C4_SDA = IOMUX_PAD(0x0368, 0x0100, 4, 0x058C, 2, 0), + IMX8MN_PAD_NAND_CE2_B__I2C4_SDA = IOMUX_PAD(0x0368, 0x0100, 4 | IOMUX_CONFIG_SION, 0x058C, 2, 0), IMX8MN_PAD_NAND_CE2_B__GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0), IMX8MN_PAD_NAND_CE2_B__CORESIGHT_TRACE1 = IOMUX_PAD(0x0368, 0x0100, 6, 0x0000, 0, 0), @@ -364,7 +364,7 @@ enum { IMX8MN_PAD_NAND_CE3_B__QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0), IMX8MN_PAD_NAND_CE3_B__USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0584, 0, 0), IMX8MN_PAD_NAND_CE3_B__PDM_BIT_STREAM2 = IOMUX_PAD(0x036C, 0x0104, 3, 0x053C, 5, 0), - IMX8MN_PAD_NAND_CE3_B__I2C3_SDA = IOMUX_PAD(0x036C, 0x0104, 4, 0x05BC, 2, 0), + IMX8MN_PAD_NAND_CE3_B__I2C3_SDA = IOMUX_PAD(0x036C, 0x0104, 4 | IOMUX_CONFIG_SION, 0x05BC, 2, 0), IMX8MN_PAD_NAND_CE3_B__GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0), IMX8MN_PAD_NAND_CE3_B__CORESIGHT_TRACE2 = IOMUX_PAD(0x036C, 0x0104, 6, 0x0000, 0, 0), @@ -393,7 +393,7 @@ enum { IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0), IMX8MN_PAD_NAND_DATA02__QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0), IMX8MN_PAD_NAND_DATA02__USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0598, 0, 0), - IMX8MN_PAD_NAND_DATA02__I2C4_SDA = IOMUX_PAD(0x037C, 0x0114, 4, 0x058C, 3, 0), + IMX8MN_PAD_NAND_DATA02__I2C4_SDA = IOMUX_PAD(0x037C, 0x0114, 4 | IOMUX_CONFIG_SION, 0x058C, 3, 0), IMX8MN_PAD_NAND_DATA02__GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0), IMX8MN_PAD_NAND_DATA02__CORESIGHT_TRACE6 = IOMUX_PAD(0x037C, 0x0114, 6, 0x0000, 0, 0), @@ -430,7 +430,7 @@ enum { IMX8MN_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0), IMX8MN_PAD_NAND_DQS__QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0), IMX8MN_PAD_NAND_DQS__PDM_CLK = IOMUX_PAD(0x0394, 0x012C, 3, 0x0000, 0, 0), - IMX8MN_PAD_NAND_DQS__I2C3_SCL = IOMUX_PAD(0x0394, 0x012C, 4, 0x0588, 2, 0), + IMX8MN_PAD_NAND_DQS__I2C3_SCL = IOMUX_PAD(0x0394, 0x012C, 4 | IOMUX_CONFIG_SION, 0x0588, 2, 0), IMX8MN_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0), IMX8MN_PAD_NAND_DQS__CORESIGHT_TRACE12 = IOMUX_PAD(0x0394, 0x012C, 6, 0x0000, 0, 0), @@ -444,19 +444,19 @@ enum { IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0), IMX8MN_PAD_NAND_READY_B__USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0), IMX8MN_PAD_NAND_READY_B__PDM_BIT_STREAM3 = IOMUX_PAD(0x039C, 0x0134, 3, 0x0540, 6, 0), - IMX8MN_PAD_NAND_READY_B__I2C3_SCL = IOMUX_PAD(0x039C, 0x0134, 4, 0x0588, 3, 0), + IMX8MN_PAD_NAND_READY_B__I2C3_SCL = IOMUX_PAD(0x039C, 0x0134, 4 | IOMUX_CONFIG_SION, 0x0588, 3, 0), IMX8MN_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0), IMX8MN_PAD_NAND_READY_B__CORESIGHT_TRACE14 = IOMUX_PAD(0x039C, 0x0134, 6, 0x0000, 0, 0), IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0), - IMX8MN_PAD_NAND_WE_B__USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x05A0, 0, 0), - IMX8MN_PAD_NAND_WE_B__I2C3_SDA = IOMUX_PAD(0x03A0, 0x0138, 4, 0x05BC, 3, 0), + IMX8MN_PAD_NAND_WE_B__USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x05A0, 0, 0), + IMX8MN_PAD_NAND_WE_B__I2C3_SDA = IOMUX_PAD(0x03A0, 0x0138, 4 | IOMUX_CONFIG_SION, 0x05BC, 3, 0), IMX8MN_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0), IMX8MN_PAD_NAND_WE_B__CORESIGHT_TRACE15 = IOMUX_PAD(0x03A0, 0x0138, 6, 0x0000, 0, 0), IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0), IMX8MN_PAD_NAND_WP_B__USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x05DC, 0, 0), - IMX8MN_PAD_NAND_WP_B__I2C4_SDA = IOMUX_PAD(0x03A4, 0x013C, 4, 0x058C, 4, 0), + IMX8MN_PAD_NAND_WP_B__I2C4_SDA = IOMUX_PAD(0x03A4, 0x013C, 4 | IOMUX_CONFIG_SION, 0x058C, 4, 0), IMX8MN_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0), IMX8MN_PAD_NAND_WP_B__CORESIGHT_EVENTO = IOMUX_PAD(0x03A4, 0x013C, 6, 0x0000, 0, 0), @@ -609,28 +609,28 @@ enum { IMX8MN_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x05D8, 0, 0), IMX8MN_PAD_ECSPI1_SCLK__UART3_DCE_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0), IMX8MN_PAD_ECSPI1_SCLK__UART3_DTE_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0), - IMX8MN_PAD_ECSPI1_SCLK__I2C1_SCL = IOMUX_PAD(0x045C, 0x01F4, 2, 0x055C, 2, 0), + IMX8MN_PAD_ECSPI1_SCLK__I2C1_SCL = IOMUX_PAD(0x045C, 0x01F4, 2 | IOMUX_CONFIG_SION, 0x055C, 2, 0), IMX8MN_PAD_ECSPI1_SCLK__SAI5_RX_SYNC = IOMUX_PAD(0x045C, 0x01F4, 3, 0x04DC, 2, 0), IMX8MN_PAD_ECSPI1_SCLK__GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0), IMX8MN_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x05A8, 0, 0), IMX8MN_PAD_ECSPI1_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0), IMX8MN_PAD_ECSPI1_MOSI__UART3_DTE_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0), - IMX8MN_PAD_ECSPI1_MOSI__I2C1_SDA = IOMUX_PAD(0x0460, 0x01F8, 2, 0x056C, 2, 0), + IMX8MN_PAD_ECSPI1_MOSI__I2C1_SDA = IOMUX_PAD(0x0460, 0x01F8, 2 | IOMUX_CONFIG_SION, 0x056C, 2, 0), IMX8MN_PAD_ECSPI1_MOSI__SAI5_RX_BCLK = IOMUX_PAD(0x0460, 0x01F8, 3, 0x04D0, 3, 0), IMX8MN_PAD_ECSPI1_MOSI__GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0), IMX8MN_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x05C4, 0, 0), IMX8MN_PAD_ECSPI1_MISO__UART3_DCE_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0), IMX8MN_PAD_ECSPI1_MISO__UART3_DTE_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0), - IMX8MN_PAD_ECSPI1_MISO__I2C2_SCL = IOMUX_PAD(0x0464, 0x01FC, 2, 0x05D0, 2, 0), + IMX8MN_PAD_ECSPI1_MISO__I2C2_SCL = IOMUX_PAD(0x0464, 0x01FC, 2 | IOMUX_CONFIG_SION, 0x05D0, 2, 0), IMX8MN_PAD_ECSPI1_MISO__SAI5_RX_DATA0 = IOMUX_PAD(0x0464, 0x01FC, 3, 0x04D4, 3, 0), IMX8MN_PAD_ECSPI1_MISO__GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0), IMX8MN_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0564, 0, 0), IMX8MN_PAD_ECSPI1_SS0__UART3_DCE_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0), IMX8MN_PAD_ECSPI1_SS0__UART3_DTE_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0), - IMX8MN_PAD_ECSPI1_SS0__I2C2_SDA = IOMUX_PAD(0x0468, 0x0200, 2, 0x0560, 2, 0), + IMX8MN_PAD_ECSPI1_SS0__I2C2_SDA = IOMUX_PAD(0x0468, 0x0200, 2 | IOMUX_CONFIG_SION, 0x0560, 2, 0), IMX8MN_PAD_ECSPI1_SS0__SAI5_RX_DATA1 = IOMUX_PAD(0x0468, 0x0200, 3, 0x04D8, 2, 0), IMX8MN_PAD_ECSPI1_SS0__SAI5_TX_SYNC = IOMUX_PAD(0x0468, 0x0200, 4, 0x04EC, 3, 0), IMX8MN_PAD_ECSPI1_SS0__GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0), @@ -638,7 +638,7 @@ enum { IMX8MN_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0580, 0, 0), IMX8MN_PAD_ECSPI2_SCLK__UART4_DCE_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0), IMX8MN_PAD_ECSPI2_SCLK__UART4_DTE_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0), - IMX8MN_PAD_ECSPI2_SCLK__I2C3_SCL = IOMUX_PAD(0x046C, 0x0204, 2, 0x0588, 4, 0), + IMX8MN_PAD_ECSPI2_SCLK__I2C3_SCL = IOMUX_PAD(0x046C, 0x0204, 2 | IOMUX_CONFIG_SION, 0x0588, 4, 0), IMX8MN_PAD_ECSPI2_SCLK__SAI5_RX_DATA2 = IOMUX_PAD(0x046C, 0x0204, 3, 0x0000, 0, 0), IMX8MN_PAD_ECSPI2_SCLK__SAI5_TX_BCLK = IOMUX_PAD(0x046C, 0x0204, 4, 0x04E8, 3, 0), IMX8MN_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0), @@ -646,7 +646,7 @@ enum { IMX8MN_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0590, 0, 0), IMX8MN_PAD_ECSPI2_MOSI__UART4_DCE_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0), IMX8MN_PAD_ECSPI2_MOSI__UART4_DTE_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0), - IMX8MN_PAD_ECSPI2_MOSI__I2C3_SDA = IOMUX_PAD(0x0470, 0x0208, 2, 0x05BC, 4, 0), + IMX8MN_PAD_ECSPI2_MOSI__I2C3_SDA = IOMUX_PAD(0x0470, 0x0208, 2 | IOMUX_CONFIG_SION, 0x05BC, 4, 0), IMX8MN_PAD_ECSPI2_MOSI__SAI5_RX_DATA3 = IOMUX_PAD(0x0470, 0x0208, 3, 0x04E0, 2, 0), IMX8MN_PAD_ECSPI2_MOSI__SAI5_TX_DATA0 = IOMUX_PAD(0x0470, 0x0208, 4, 0x0000, 0, 0), IMX8MN_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0), @@ -654,14 +654,14 @@ enum { IMX8MN_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0578, 0, 0), IMX8MN_PAD_ECSPI2_MISO__UART4_DCE_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0), IMX8MN_PAD_ECSPI2_MISO__UART4_DTE_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0), - IMX8MN_PAD_ECSPI2_MISO__I2C4_SCL = IOMUX_PAD(0x0474, 0x020C, 2, 0x05D4, 3, 0), + IMX8MN_PAD_ECSPI2_MISO__I2C4_SCL = IOMUX_PAD(0x0474, 0x020C, 2 | IOMUX_CONFIG_SION, 0x05D4, 3, 0), IMX8MN_PAD_ECSPI2_MISO__SAI5_MCLK = IOMUX_PAD(0x0474, 0x020C, 3, 0x0594, 4, 0), IMX8MN_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0), IMX8MN_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0570, 0, 0), IMX8MN_PAD_ECSPI2_SS0__UART4_DCE_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0), IMX8MN_PAD_ECSPI2_SS0__UART4_DTE_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0), - IMX8MN_PAD_ECSPI2_SS0__I2C4_SDA = IOMUX_PAD(0x0478, 0x0210, 2, 0x058C, 5, 0), + IMX8MN_PAD_ECSPI2_SS0__I2C4_SDA = IOMUX_PAD(0x0478, 0x0210, 2 | IOMUX_CONFIG_SION, 0x058C, 5, 0), IMX8MN_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0), IMX8MN_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x055C, 0, 0), @@ -674,36 +674,36 @@ enum { IMX8MN_PAD_I2C1_SDA__ECSPI1_MOSI = IOMUX_PAD(0x0480, 0x0218, 3, 0x05A8, 1, 0), IMX8MN_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0), - IMX8MN_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x05D0, 0, 0), + IMX8MN_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0 | IOMUX_CONFIG_SION, 0x05D0, 0, 0), IMX8MN_PAD_I2C2_SCL__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0), IMX8MN_PAD_I2C2_SCL__USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0598, 1, 0), IMX8MN_PAD_I2C2_SCL__ECSPI1_MISO = IOMUX_PAD(0x0484, 0x021C, 3, 0x05C4, 1, 0), IMX8MN_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0), - IMX8MN_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0560, 0, 0), + IMX8MN_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0 | IOMUX_CONFIG_SION, 0x0560, 0, 0), IMX8MN_PAD_I2C2_SDA__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0), IMX8MN_PAD_I2C2_SDA__USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x05B8, 1, 0), IMX8MN_PAD_I2C2_SDA__ECSPI1_SS0 = IOMUX_PAD(0x0488, 0x0220, 3, 0x0564, 1, 0), IMX8MN_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0), - IMX8MN_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0588, 0, 0), + IMX8MN_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0 | IOMUX_CONFIG_SION, 0x0588, 0, 0), IMX8MN_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0), IMX8MN_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0), IMX8MN_PAD_I2C3_SCL__ECSPI2_SCLK = IOMUX_PAD(0x048C, 0x0224, 3, 0x0580, 2, 0), IMX8MN_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0), - IMX8MN_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x05BC, 0, 0), + IMX8MN_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0 | IOMUX_CONFIG_SION, 0x05BC, 0, 0), IMX8MN_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0), IMX8MN_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0), IMX8MN_PAD_I2C3_SDA__ECSPI2_MOSI = IOMUX_PAD(0x0490, 0x0228, 3, 0x0590, 2, 0), IMX8MN_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0), - IMX8MN_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x05D4, 0, 0), + IMX8MN_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0 | IOMUX_CONFIG_SION, 0x05D4, 0, 0), IMX8MN_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0), IMX8MN_PAD_I2C4_SCL__ECSPI2_MISO = IOMUX_PAD(0x0494, 0x022C, 3, 0x0578, 2, 0), IMX8MN_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0), - IMX8MN_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x058C, 0, 0), + IMX8MN_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0 | IOMUX_CONFIG_SION, 0x058C, 0, 0), IMX8MN_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0), IMX8MN_PAD_I2C4_SDA__ECSPI2_SS0 = IOMUX_PAD(0x0498, 0x0230, 3, 0x0570, 1, 0), IMX8MN_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h index e7f32218233..309453e1a97 100644 --- a/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h +++ b/arch/arm/include/asm/arch-imx8m/imx8mp_pins.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP + * Copyright 2019-2020 NXP */ #ifndef __ASM_ARCH_IMX8MP_PINS_H__ @@ -10,210 +10,176 @@ enum { MX8MP_PAD_GPIO1_IO00__GPIO1_IO00 = IOMUX_PAD(0x0274, 0x0014, 0, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0274, 0x0014, 1, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO00__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0274, 0x0014, 3, 0x05D4, 0, 0), - MX8MP_PAD_GPIO1_IO00__ANAMIX_REF_CLK_32K = IOMUX_PAD(0x0274, 0x0014, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO00__CCMSRCGPCMIX_EXT_CLK1 = IOMUX_PAD(0x0274, 0x0014, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO00__SJC_FAIL = IOMUX_PAD(0x0274, 0x0014, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0274, 0x0014, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO00__ISP_FL_TRIG_0 = IOMUX_PAD(0x0274, 0x0014, 3, 0x05D4, 0, 0), + MX8MP_PAD_GPIO1_IO00__CCM_EXT_CLK1 = IOMUX_PAD(0x0274, 0x0014, 6, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO01__GPIO1_IO01 = IOMUX_PAD(0x0278, 0x0018, 0, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO01__PWM1_OUT = IOMUX_PAD(0x0278, 0x0018, 1, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO01__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0278, 0x0018, 3, 0x05DC, 0, 0), - MX8MP_PAD_GPIO1_IO01__ANAMIX_REF_CLK_24M = IOMUX_PAD(0x0278, 0x0018, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO01__CCMSRCGPCMIX_EXT_CLK2 = IOMUX_PAD(0x0278, 0x0018, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO01__SJC_ACTIVE = IOMUX_PAD(0x0278, 0x0018, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO01__ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0278, 0x0018, 3, 0x05DC, 0, 0), + MX8MP_PAD_GPIO1_IO01__CCM_EXT_CLK2 = IOMUX_PAD(0x0278, 0x0018, 6, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO02__GPIO1_IO02 = IOMUX_PAD(0x027C, 0x001C, 0, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B = IOMUX_PAD(0x027C, 0x001C, 1, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO02__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x027C, 0x001C, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO02__ISP_FLASH_TRIG_0 = IOMUX_PAD(0x027C, 0x001C, 3, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_ANY = IOMUX_PAD(0x027C, 0x001C, 5, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO02__SJC_DE_B = IOMUX_PAD(0x027C, 0x001C, 7, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x0280, 0x0020, 0, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO03__USDHC1_VSELECT = IOMUX_PAD(0x0280, 0x0020, 1, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO03__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x0280, 0x0020, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x0280, 0x0020, 3, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO03__SDMA1_EXT_EVENT00 = IOMUX_PAD(0x0280, 0x0020, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO03__ANAMIX_XTAL_OK = IOMUX_PAD(0x0280, 0x0020, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO03__SJC_DONE = IOMUX_PAD(0x0280, 0x0020, 7, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x0284, 0x0024, 0, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO04__USDHC2_VSELECT = IOMUX_PAD(0x0284, 0x0024, 1, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO04__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0284, 0x0024, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO04__ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0284, 0x0024, 3, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO04__SDMA1_EXT_EVENT01 = IOMUX_PAD(0x0284, 0x0024, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO04__ANAMIX_XTAL_OK_LV = IOMUX_PAD(0x0284, 0x0024, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO04__USDHC1_TEST_TRIG = IOMUX_PAD(0x0284, 0x0024, 7, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO05__GPIO1_IO05 = IOMUX_PAD(0x0288, 0x0028, 0, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO05__M7_NMI = IOMUX_PAD(0x0288, 0x0028, 1, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO05__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0288, 0x0028, 3, 0x05D8, 0, 0), - MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x0288, 0x0028, 5, 0x0554, 0, 0), - MX8MP_PAD_GPIO1_IO05__CCMSRCGPCMIX_INT_BOOT = IOMUX_PAD(0x0288, 0x0028, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO05__USDHC2_TEST_TRIG = IOMUX_PAD(0x0288, 0x0028, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO05__ISP_FL_TRIG_1 = IOMUX_PAD(0x0288, 0x0028, 3, 0x05D8, 0, 0), + MX8MP_PAD_GPIO1_IO05__CCM_PMIC_READY = IOMUX_PAD(0x0288, 0x0028, 5, 0x0554, 0, 0), MX8MP_PAD_GPIO1_IO06__GPIO1_IO06 = IOMUX_PAD(0x028C, 0x002C, 0, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO06__ENET_QOS_MDC = IOMUX_PAD(0x028C, 0x002C, 1, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO06__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x028C, 0x002C, 3, 0x05E0, 0, 0), + MX8MP_PAD_GPIO1_IO06__ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x028C, 0x002C, 3, 0x05E0, 0, 0), MX8MP_PAD_GPIO1_IO06__USDHC1_CD_B = IOMUX_PAD(0x028C, 0x002C, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO06__CCMSRCGPCMIX_EXT_CLK3 = IOMUX_PAD(0x028C, 0x002C, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO06__ECSPI1_TEST_TRIG = IOMUX_PAD(0x028C, 0x002C, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO06__CCM_EXT_CLK3 = IOMUX_PAD(0x028C, 0x002C, 6, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO07__GPIO1_IO07 = IOMUX_PAD(0x0290, 0x0030, 0, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO07__ENET_QOS_MDIO = IOMUX_PAD(0x0290, 0x0030, 1, 0x0590, 0, 0), - MX8MP_PAD_GPIO1_IO07__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x0290, 0x0030, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__ISP_FLASH_TRIG_1 = IOMUX_PAD(0x0290, 0x0030, 3, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO07__USDHC1_WP = IOMUX_PAD(0x0290, 0x0030, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO07__CCMSRCGPCMIX_EXT_CLK4 = IOMUX_PAD(0x0290, 0x0030, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO07__ECSPI2_TEST_TRIG = IOMUX_PAD(0x0290, 0x0030, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO07__CCM_EXT_CLK4 = IOMUX_PAD(0x0290, 0x0030, 6, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO08__GPIO1_IO08 = IOMUX_PAD(0x0294, 0x0034, 0, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN = IOMUX_PAD(0x0294, 0x0034, 1, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO08__PWM1_OUT = IOMUX_PAD(0x0294, 0x0034, 2, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO08__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0294, 0x0034, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0294, 0x0034, 3, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN = IOMUX_PAD(0x0294, 0x0034, 4, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO08__USDHC2_RESET_B = IOMUX_PAD(0x0294, 0x0034, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO08__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x0294, 0x0034, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO08__FLEXSPI_TEST_TRIG = IOMUX_PAD(0x0294, 0x0034, 7, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO09__GPIO1_IO09 = IOMUX_PAD(0x0298, 0x0038, 0, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT = IOMUX_PAD(0x0298, 0x0038, 1, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO09__PWM2_OUT = IOMUX_PAD(0x0298, 0x0038, 2, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO09__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0298, 0x0038, 3, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0298, 0x0038, 3, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO09__USDHC3_RESET_B = IOMUX_PAD(0x0298, 0x0038, 4, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO09__AUDIOMIX_EXT_EVENT00 = IOMUX_PAD(0x0298, 0x0038, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO09__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0298, 0x0038, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO09__RAWNAND_TEST_TRIG = IOMUX_PAD(0x0298, 0x0038, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO09__SDMA2_EXT_EVENT00 = IOMUX_PAD(0x0298, 0x0038, 5, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO10__GPIO1_IO10 = IOMUX_PAD(0x029C, 0x003C, 0, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO10__HSIOMIX_usb1_OTG_ID = IOMUX_PAD(0x029C, 0x003C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO10__USB1_OTG_ID = IOMUX_PAD(0x029C, 0x003C, 1, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO10__PWM3_OUT = IOMUX_PAD(0x029C, 0x003C, 2, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO10__OCOTP_FUSE_LATCHED = IOMUX_PAD(0x029C, 0x003C, 7, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO11__GPIO1_IO11 = IOMUX_PAD(0x02A0, 0x0040, 0, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO11__HSIOMIX_usb2_OTG_ID = IOMUX_PAD(0x02A0, 0x0040, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__USB2_OTG_ID = IOMUX_PAD(0x02A0, 0x0040, 1, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO11__PWM2_OUT = IOMUX_PAD(0x02A0, 0x0040, 2, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO11__USDHC3_VSELECT = IOMUX_PAD(0x02A0, 0x0040, 4, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_PMIC_READY = IOMUX_PAD(0x02A0, 0x0040, 5, 0x0554, 1, 0), - MX8MP_PAD_GPIO1_IO11__CCMSRCGPCMIX_OUT0 = IOMUX_PAD(0x02A0, 0x0040, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO11__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02A0, 0x0040, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO11__CCM_PMIC_READY = IOMUX_PAD(0x02A0, 0x0040, 5, 0x0554, 1, 0), MX8MP_PAD_GPIO1_IO12__GPIO1_IO12 = IOMUX_PAD(0x02A4, 0x0044, 0, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO12__HSIOMIX_usb1_OTG_PWR = IOMUX_PAD(0x02A4, 0x0044, 1, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO12__AUDIOMIX_EXT_EVENT01 = IOMUX_PAD(0x02A4, 0x0044, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO12__CCMSRCGPCMIX_OUT1 = IOMUX_PAD(0x02A4, 0x0044, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT00 = IOMUX_PAD(0x02A4, 0x0044, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__USB1_OTG_PWR = IOMUX_PAD(0x02A4, 0x0044, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO12__SDMA2_EXT_EVENT01 = IOMUX_PAD(0x02A4, 0x0044, 5, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO13__GPIO1_IO13 = IOMUX_PAD(0x02A8, 0x0048, 0, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO13__HSIOMIX_usb1_OTG_OC = IOMUX_PAD(0x02A8, 0x0048, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO13__USB1_OTG_OC = IOMUX_PAD(0x02A8, 0x0048, 1, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO13__PWM2_OUT = IOMUX_PAD(0x02A8, 0x0048, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO13__CCMSRCGPCMIX_OUT2 = IOMUX_PAD(0x02A8, 0x0048, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT01 = IOMUX_PAD(0x02A8, 0x0048, 7, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO14__GPIO1_IO14 = IOMUX_PAD(0x02AC, 0x004C, 0, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO14__HSIOMIX_usb2_OTG_PWR = IOMUX_PAD(0x02AC, 0x004C, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__USB2_OTG_PWR = IOMUX_PAD(0x02AC, 0x004C, 1, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO14__USDHC3_CD_B = IOMUX_PAD(0x02AC, 0x004C, 4, 0x0608, 0, 0), MX8MP_PAD_GPIO1_IO14__PWM3_OUT = IOMUX_PAD(0x02AC, 0x004C, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO14__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x02AC, 0x004C, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO14__CSU_CSU_ALARM_AUT02 = IOMUX_PAD(0x02AC, 0x004C, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO14__CCM_CLKO1 = IOMUX_PAD(0x02AC, 0x004C, 6, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO15__GPIO1_IO15 = IOMUX_PAD(0x02B0, 0x0050, 0, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO15__HSIOMIX_usb2_OTG_OC = IOMUX_PAD(0x02B0, 0x0050, 1, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__USB2_OTG_OC = IOMUX_PAD(0x02B0, 0x0050, 1, 0x0000, 0, 0), MX8MP_PAD_GPIO1_IO15__USDHC3_WP = IOMUX_PAD(0x02B0, 0x0050, 4, 0x0634, 0, 0), MX8MP_PAD_GPIO1_IO15__PWM4_OUT = IOMUX_PAD(0x02B0, 0x0050, 5, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO15__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x02B0, 0x0050, 6, 0x0000, 0, 0), - MX8MP_PAD_GPIO1_IO15__CSU_CSU_INT_DEB = IOMUX_PAD(0x02B0, 0x0050, 7, 0x0000, 0, 0), + MX8MP_PAD_GPIO1_IO15__CCM_CLKO2 = IOMUX_PAD(0x02B0, 0x0050, 6, 0x0000, 0, 0), MX8MP_PAD_ENET_MDC__ENET_QOS_MDC = IOMUX_PAD(0x02B4, 0x0054, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 = IOMUX_PAD(0x02B4, 0x0054, 2, 0x0000, 0, 0), MX8MP_PAD_ENET_MDC__GPIO1_IO16 = IOMUX_PAD(0x02B4, 0x0054, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_MDC__USDHC3_STROBE = IOMUX_PAD(0x02B4, 0x0054, 6, 0x0630, 0, 0), - MX8MP_PAD_ENET_MDC__SIM_M_HADDR15 = IOMUX_PAD(0x02B4, 0x0054, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_MDIO__ENET_QOS_MDIO = IOMUX_PAD(0x02B8, 0x0058, 0, 0x0590, 1, 0), MX8MP_PAD_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC = IOMUX_PAD(0x02B8, 0x0058, 2, 0x0528, 0, 0), + MX8MP_PAD_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03 = IOMUX_PAD(0x02B8, 0x0058, 3, 0x04CC, 0, 0), MX8MP_PAD_ENET_MDIO__GPIO1_IO17 = IOMUX_PAD(0x02B8, 0x0058, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_MDIO__USDHC3_DATA5 = IOMUX_PAD(0x02B8, 0x0058, 6, 0x0624, 0, 0), - MX8MP_PAD_ENET_MDIO__SIM_M_HADDR16 = IOMUX_PAD(0x02B8, 0x0058, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_TD3__ENET_QOS_RGMII_TD3 = IOMUX_PAD(0x02BC, 0x005C, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK = IOMUX_PAD(0x02BC, 0x005C, 2, 0x0524, 0, 0), + MX8MP_PAD_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02 = IOMUX_PAD(0x02BC, 0x005C, 3, 0x04C8, 0, 0), MX8MP_PAD_ENET_TD3__GPIO1_IO18 = IOMUX_PAD(0x02BC, 0x005C, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_TD3__USDHC3_DATA6 = IOMUX_PAD(0x02BC, 0x005C, 6, 0x0628, 0, 0), - MX8MP_PAD_ENET_TD3__SIM_M_HADDR17 = IOMUX_PAD(0x02BC, 0x005C, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_TD2__ENET_QOS_RGMII_TD2 = IOMUX_PAD(0x02C0, 0x0060, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x02C0, 0x0060, 1, 0x0000, 0, 0), MX8MP_PAD_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 = IOMUX_PAD(0x02C0, 0x0060, 2, 0x051C, 0, 0), + MX8MP_PAD_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01 = IOMUX_PAD(0x02C0, 0x0060, 3, 0x04C4, 0, 0), MX8MP_PAD_ENET_TD2__GPIO1_IO19 = IOMUX_PAD(0x02C0, 0x0060, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_TD2__USDHC3_DATA7 = IOMUX_PAD(0x02C0, 0x0060, 6, 0x062C, 0, 0), - MX8MP_PAD_ENET_TD2__SIM_M_HADDR18 = IOMUX_PAD(0x02C0, 0x0060, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_TD1__ENET_QOS_RGMII_TD1 = IOMUX_PAD(0x02C4, 0x0064, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC = IOMUX_PAD(0x02C4, 0x0064, 2, 0x0520, 0, 0), + MX8MP_PAD_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00 = IOMUX_PAD(0x02C4, 0x0064, 3, 0x04C0, 0, 0), MX8MP_PAD_ENET_TD1__GPIO1_IO20 = IOMUX_PAD(0x02C4, 0x0064, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_TD1__USDHC3_CD_B = IOMUX_PAD(0x02C4, 0x0064, 6, 0x0608, 1, 0), - MX8MP_PAD_ENET_TD1__SIM_M_HADDR19 = IOMUX_PAD(0x02C4, 0x0064, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_TD0__ENET_QOS_RGMII_TD0 = IOMUX_PAD(0x02C8, 0x0068, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK = IOMUX_PAD(0x02C8, 0x0068, 2, 0x0518, 0, 0), + MX8MP_PAD_ENET_TD0__AUDIOMIX_PDM_CLK = IOMUX_PAD(0x02C8, 0x0068, 3, 0x0000, 0, 0), MX8MP_PAD_ENET_TD0__GPIO1_IO21 = IOMUX_PAD(0x02C8, 0x0068, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_TD0__USDHC3_WP = IOMUX_PAD(0x02C8, 0x0068, 6, 0x0634, 1, 0), - MX8MP_PAD_ENET_TD0__SIM_M_HADDR20 = IOMUX_PAD(0x02C8, 0x0068, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL = IOMUX_PAD(0x02CC, 0x006C, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x02CC, 0x006C, 2, 0x0514, 0, 0), - MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x02CC, 0x006C, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT = IOMUX_PAD(0x02CC, 0x006C, 3, 0x0000, 0, 0), MX8MP_PAD_ENET_TX_CTL__GPIO1_IO22 = IOMUX_PAD(0x02CC, 0x006C, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_TX_CTL__USDHC3_DATA0 = IOMUX_PAD(0x02CC, 0x006C, 6, 0x0610, 0, 0), - MX8MP_PAD_ENET_TX_CTL__SIM_M_HADDR21 = IOMUX_PAD(0x02CC, 0x006C, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK = IOMUX_PAD(0x02D0, 0x0070, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_TXC__ENET_QOS_TX_ER = IOMUX_PAD(0x02D0, 0x0070, 1, 0x0000, 0, 0), MX8MP_PAD_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x02D0, 0x0070, 2, 0x0000, 0, 0), MX8MP_PAD_ENET_TXC__GPIO1_IO23 = IOMUX_PAD(0x02D0, 0x0070, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_TXC__USDHC3_DATA1 = IOMUX_PAD(0x02D0, 0x0070, 6, 0x0614, 0, 0), - MX8MP_PAD_ENET_TXC__SIM_M_HADDR22 = IOMUX_PAD(0x02D0, 0x0070, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL = IOMUX_PAD(0x02D4, 0x0074, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x02D4, 0x0074, 2, 0x0540, 0, 0), - MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x02D4, 0x0074, 3, 0x04CC, 0, 0), + MX8MP_PAD_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03 = IOMUX_PAD(0x02D4, 0x0074, 3, 0x04CC, 1, 0), MX8MP_PAD_ENET_RX_CTL__GPIO1_IO24 = IOMUX_PAD(0x02D4, 0x0074, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_RX_CTL__USDHC3_DATA2 = IOMUX_PAD(0x02D4, 0x0074, 6, 0x0618, 0, 0), - MX8MP_PAD_ENET_RX_CTL__SIM_M_HADDR23 = IOMUX_PAD(0x02D4, 0x0074, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK = IOMUX_PAD(0x02D8, 0x0078, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_RXC__ENET_QOS_RX_ER = IOMUX_PAD(0x02D8, 0x0078, 1, 0x0000, 0, 0), MX8MP_PAD_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x02D8, 0x0078, 2, 0x053C, 0, 0), - MX8MP_PAD_ENET_RXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x02D8, 0x0078, 3, 0x04C8, 0, 0), + MX8MP_PAD_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02 = IOMUX_PAD(0x02D8, 0x0078, 3, 0x04C8, 1, 0), MX8MP_PAD_ENET_RXC__GPIO1_IO25 = IOMUX_PAD(0x02D8, 0x0078, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_RXC__USDHC3_DATA3 = IOMUX_PAD(0x02D8, 0x0078, 6, 0x061C, 0, 0), - MX8MP_PAD_ENET_RXC__SIM_M_HADDR24 = IOMUX_PAD(0x02D8, 0x0078, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_RD0__ENET_QOS_RGMII_RD0 = IOMUX_PAD(0x02DC, 0x007C, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x02DC, 0x007C, 2, 0x0534, 0, 0), - MX8MP_PAD_ENET_RD0__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x02DC, 0x007C, 3, 0x04C4, 0, 0), + MX8MP_PAD_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01 = IOMUX_PAD(0x02DC, 0x007C, 3, 0x04C4, 1, 0), MX8MP_PAD_ENET_RD0__GPIO1_IO26 = IOMUX_PAD(0x02DC, 0x007C, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_RD0__USDHC3_DATA4 = IOMUX_PAD(0x02DC, 0x007C, 6, 0x0620, 0, 0), - MX8MP_PAD_ENET_RD0__SIM_M_HADDR25 = IOMUX_PAD(0x02DC, 0x007C, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_RD1__ENET_QOS_RGMII_RD1 = IOMUX_PAD(0x02E0, 0x0080, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x02E0, 0x0080, 2, 0x0538, 0, 0), - MX8MP_PAD_ENET_RD1__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x02E0, 0x0080, 3, 0x04C0, 0, 0), + MX8MP_PAD_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00 = IOMUX_PAD(0x02E0, 0x0080, 3, 0x04C0, 1, 0), MX8MP_PAD_ENET_RD1__GPIO1_IO27 = IOMUX_PAD(0x02E0, 0x0080, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_RD1__USDHC3_RESET_B = IOMUX_PAD(0x02E0, 0x0080, 6, 0x0000, 0, 0), - MX8MP_PAD_ENET_RD1__SIM_M_HADDR26 = IOMUX_PAD(0x02E0, 0x0080, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_RD2__ENET_QOS_RGMII_RD2 = IOMUX_PAD(0x02E4, 0x0084, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x02E4, 0x0084, 2, 0x0530, 0, 0), - MX8MP_PAD_ENET_RD2__AUDIOMIX_CLK = IOMUX_PAD(0x02E4, 0x0084, 3, 0x0000, 0, 0), + MX8MP_PAD_ENET_RD2__AUDIOMIX_PDM_CLK = IOMUX_PAD(0x02E4, 0x0084, 3, 0x0000, 0, 0), MX8MP_PAD_ENET_RD2__GPIO1_IO28 = IOMUX_PAD(0x02E4, 0x0084, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_RD2__USDHC3_CLK = IOMUX_PAD(0x02E4, 0x0084, 6, 0x0604, 0, 0), - MX8MP_PAD_ENET_RD2__SIM_M_HADDR27 = IOMUX_PAD(0x02E4, 0x0084, 7, 0x0000, 0, 0), MX8MP_PAD_ENET_RD3__ENET_QOS_RGMII_RD3 = IOMUX_PAD(0x02E8, 0x0088, 0, 0x0000, 0, 0), MX8MP_PAD_ENET_RD3__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x02E8, 0x0088, 2, 0x052C, 0, 0), - MX8MP_PAD_ENET_RD3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x02E8, 0x0088, 3, 0x0544, 0, 0), + MX8MP_PAD_ENET_RD3__AUDIOMIX_SPDIF1_IN = IOMUX_PAD(0x02E8, 0x0088, 3, 0x0544, 0, 0), MX8MP_PAD_ENET_RD3__GPIO1_IO29 = IOMUX_PAD(0x02E8, 0x0088, 5, 0x0000, 0, 0), MX8MP_PAD_ENET_RD3__USDHC3_CMD = IOMUX_PAD(0x02E8, 0x0088, 6, 0x060C, 0, 0), - MX8MP_PAD_ENET_RD3__SIM_M_HADDR28 = IOMUX_PAD(0x02E8, 0x0088, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_CLK__USDHC1_CLK = IOMUX_PAD(0x02EC, 0x008C, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_CLK__ENET1_MDC = IOMUX_PAD(0x02EC, 0x008C, 1, 0x0000, 0, 0), @@ -221,7 +187,6 @@ enum { MX8MP_PAD_SD1_CLK__UART1_DCE_TX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_CLK__UART1_DTE_RX = IOMUX_PAD(0x02EC, 0x008C, 4, 0x05E8, 0, 0), MX8MP_PAD_SD1_CLK__GPIO2_IO00 = IOMUX_PAD(0x02EC, 0x008C, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_CLK__SIM_M_HADDR29 = IOMUX_PAD(0x02EC, 0x008C, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_CMD__USDHC1_CMD = IOMUX_PAD(0x02F0, 0x0090, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_CMD__ENET1_MDIO = IOMUX_PAD(0x02F0, 0x0090, 1, 0x057C, 0, 0), @@ -229,7 +194,6 @@ enum { MX8MP_PAD_SD1_CMD__UART1_DCE_RX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x05E8, 1, 0), MX8MP_PAD_SD1_CMD__UART1_DTE_TX = IOMUX_PAD(0x02F0, 0x0090, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_CMD__GPIO2_IO01 = IOMUX_PAD(0x02F0, 0x0090, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_CMD__SIM_M_HADDR30 = IOMUX_PAD(0x02F0, 0x0090, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA0__USDHC1_DATA0 = IOMUX_PAD(0x02F4, 0x0094, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA0__ENET1_RGMII_TD1 = IOMUX_PAD(0x02F4, 0x0094, 1, 0x0000, 0, 0), @@ -237,7 +201,6 @@ enum { MX8MP_PAD_SD1_DATA0__UART1_DCE_RTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x05E4, 0, 0), MX8MP_PAD_SD1_DATA0__UART1_DTE_CTS = IOMUX_PAD(0x02F4, 0x0094, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA0__GPIO2_IO02 = IOMUX_PAD(0x02F4, 0x0094, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_DATA0__SIM_M_HADDR31 = IOMUX_PAD(0x02F4, 0x0094, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA1__USDHC1_DATA1 = IOMUX_PAD(0x02F8, 0x0098, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA1__ENET1_RGMII_TD0 = IOMUX_PAD(0x02F8, 0x0098, 1, 0x0000, 0, 0), @@ -245,7 +208,6 @@ enum { MX8MP_PAD_SD1_DATA1__UART1_DCE_CTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA1__UART1_DTE_RTS = IOMUX_PAD(0x02F8, 0x0098, 4, 0x05E4, 1, 0), MX8MP_PAD_SD1_DATA1__GPIO2_IO03 = IOMUX_PAD(0x02F8, 0x0098, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_DATA1__SIM_M_HBURST00 = IOMUX_PAD(0x02F8, 0x0098, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA2__USDHC1_DATA2 = IOMUX_PAD(0x02FC, 0x009C, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA2__ENET1_RGMII_RD0 = IOMUX_PAD(0x02FC, 0x009C, 1, 0x0580, 0, 0), @@ -253,7 +215,6 @@ enum { MX8MP_PAD_SD1_DATA2__UART2_DCE_TX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA2__UART2_DTE_RX = IOMUX_PAD(0x02FC, 0x009C, 4, 0x05F0, 0, 0), MX8MP_PAD_SD1_DATA2__GPIO2_IO04 = IOMUX_PAD(0x02FC, 0x009C, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_DATA2__SIM_M_HBURST01 = IOMUX_PAD(0x02FC, 0x009C, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA3__USDHC1_DATA3 = IOMUX_PAD(0x0300, 0x00A0, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA3__ENET1_RGMII_RD1 = IOMUX_PAD(0x0300, 0x00A0, 1, 0x0584, 0, 0), @@ -261,7 +222,6 @@ enum { MX8MP_PAD_SD1_DATA3__UART2_DCE_RX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x05F0, 1, 0), MX8MP_PAD_SD1_DATA3__UART2_DTE_TX = IOMUX_PAD(0x0300, 0x00A0, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA3__GPIO2_IO05 = IOMUX_PAD(0x0300, 0x00A0, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_DATA3__SIM_M_HBURST02 = IOMUX_PAD(0x0300, 0x00A0, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA4__USDHC1_DATA4 = IOMUX_PAD(0x0304, 0x00A4, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA4__ENET1_RGMII_TX_CTL = IOMUX_PAD(0x0304, 0x00A4, 1, 0x0000, 0, 0), @@ -269,7 +229,6 @@ enum { MX8MP_PAD_SD1_DATA4__UART2_DCE_RTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x05EC, 0, 0), MX8MP_PAD_SD1_DATA4__UART2_DTE_CTS = IOMUX_PAD(0x0304, 0x00A4, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA4__GPIO2_IO06 = IOMUX_PAD(0x0304, 0x00A4, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_DATA4__SIM_M_HRESP = IOMUX_PAD(0x0304, 0x00A4, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA5__USDHC1_DATA5 = IOMUX_PAD(0x0308, 0x00A8, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA5__ENET1_TX_ER = IOMUX_PAD(0x0308, 0x00A8, 1, 0x0000, 0, 0), @@ -277,7 +236,6 @@ enum { MX8MP_PAD_SD1_DATA5__UART2_DCE_CTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA5__UART2_DTE_RTS = IOMUX_PAD(0x0308, 0x00A8, 4, 0x05EC, 1, 0), MX8MP_PAD_SD1_DATA5__GPIO2_IO07 = IOMUX_PAD(0x0308, 0x00A8, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_DATA5__TPSMP_HDATA05 = IOMUX_PAD(0x0308, 0x00A8, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA6__USDHC1_DATA6 = IOMUX_PAD(0x030C, 0x00AC, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA6__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x030C, 0x00AC, 1, 0x0588, 0, 0), @@ -285,7 +243,6 @@ enum { MX8MP_PAD_SD1_DATA6__UART3_DCE_TX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA6__UART3_DTE_RX = IOMUX_PAD(0x030C, 0x00AC, 4, 0x05F8, 0, 0), MX8MP_PAD_SD1_DATA6__GPIO2_IO08 = IOMUX_PAD(0x030C, 0x00AC, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_DATA6__TPSMP_HDATA06 = IOMUX_PAD(0x030C, 0x00AC, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA7__USDHC1_DATA7 = IOMUX_PAD(0x0310, 0x00B0, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA7__ENET1_RX_ER = IOMUX_PAD(0x0310, 0x00B0, 1, 0x058C, 0, 0), @@ -293,7 +250,6 @@ enum { MX8MP_PAD_SD1_DATA7__UART3_DCE_RX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x05F8, 1, 0), MX8MP_PAD_SD1_DATA7__UART3_DTE_TX = IOMUX_PAD(0x0310, 0x00B0, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_DATA7__GPIO2_IO09 = IOMUX_PAD(0x0310, 0x00B0, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_DATA7__TPSMP_HDATA07 = IOMUX_PAD(0x0310, 0x00B0, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_RESET_B__USDHC1_RESET_B = IOMUX_PAD(0x0314, 0x00B4, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_RESET_B__ENET1_TX_CLK = IOMUX_PAD(0x0314, 0x00B4, 1, 0x0578, 0, 0), @@ -301,152 +257,130 @@ enum { MX8MP_PAD_SD1_RESET_B__UART3_DCE_RTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x05F4, 0, 0), MX8MP_PAD_SD1_RESET_B__UART3_DTE_CTS = IOMUX_PAD(0x0314, 0x00B4, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_RESET_B__GPIO2_IO10 = IOMUX_PAD(0x0314, 0x00B4, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_RESET_B__ECSPI3_TEST_TRIG = IOMUX_PAD(0x0314, 0x00B4, 7, 0x0000, 0, 0), MX8MP_PAD_SD1_STROBE__USDHC1_STROBE = IOMUX_PAD(0x0318, 0x00B8, 0, 0x0000, 0, 0), MX8MP_PAD_SD1_STROBE__I2C3_SDA = IOMUX_PAD(0x0318, 0x00B8, 3 | IOMUX_CONFIG_SION, 0x05B8, 0, 0), MX8MP_PAD_SD1_STROBE__UART3_DCE_CTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x0000, 0, 0), MX8MP_PAD_SD1_STROBE__UART3_DTE_RTS = IOMUX_PAD(0x0318, 0x00B8, 4, 0x05F4, 1, 0), MX8MP_PAD_SD1_STROBE__GPIO2_IO11 = IOMUX_PAD(0x0318, 0x00B8, 5, 0x0000, 0, 0), - MX8MP_PAD_SD1_STROBE__USDHC3_TEST_TRIG = IOMUX_PAD(0x0318, 0x00B8, 7, 0x0000, 0, 0), MX8MP_PAD_SD2_CD_B__USDHC2_CD_B = IOMUX_PAD(0x031C, 0x00BC, 0, 0x0000, 0, 0), MX8MP_PAD_SD2_CD_B__GPIO2_IO12 = IOMUX_PAD(0x031C, 0x00BC, 5, 0x0000, 0, 0), - MX8MP_PAD_SD2_CD_B__CCMSRCGPCMIX_TESTER_ACK = IOMUX_PAD(0x031C, 0x00BC, 6, 0x0000, 0, 0), MX8MP_PAD_SD2_CLK__USDHC2_CLK = IOMUX_PAD(0x0320, 0x00C0, 0, 0x0000, 0, 0), MX8MP_PAD_SD2_CLK__ECSPI2_SCLK = IOMUX_PAD(0x0320, 0x00C0, 2, 0x0568, 0, 0), MX8MP_PAD_SD2_CLK__UART4_DCE_RX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0600, 0, 0), MX8MP_PAD_SD2_CLK__UART4_DTE_TX = IOMUX_PAD(0x0320, 0x00C0, 3, 0x0000, 0, 0), MX8MP_PAD_SD2_CLK__GPIO2_IO13 = IOMUX_PAD(0x0320, 0x00C0, 5, 0x0000, 0, 0), - MX8MP_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 = IOMUX_PAD(0x0320, 0x00C0, 6, 0x0000, 0, 0), - MX8MP_PAD_SD2_CLK__OBSERVE_MUX_OUT00 = IOMUX_PAD(0x0320, 0x00C0, 7, 0x0000, 0, 0), MX8MP_PAD_SD2_CMD__USDHC2_CMD = IOMUX_PAD(0x0324, 0x00C4, 0, 0x0000, 0, 0), MX8MP_PAD_SD2_CMD__ECSPI2_MOSI = IOMUX_PAD(0x0324, 0x00C4, 2, 0x0570, 0, 0), MX8MP_PAD_SD2_CMD__UART4_DCE_TX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0000, 0, 0), MX8MP_PAD_SD2_CMD__UART4_DTE_RX = IOMUX_PAD(0x0324, 0x00C4, 3, 0x0600, 1, 0), - MX8MP_PAD_SD2_CMD__AUDIOMIX_CLK = IOMUX_PAD(0x0324, 0x00C4, 4, 0x0000, 0, 0), + MX8MP_PAD_SD2_CMD__AUDIOMIX_PDM_CLK = IOMUX_PAD(0x0324, 0x00C4, 4, 0x0000, 0, 0), MX8MP_PAD_SD2_CMD__GPIO2_IO14 = IOMUX_PAD(0x0324, 0x00C4, 5, 0x0000, 0, 0), - MX8MP_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 = IOMUX_PAD(0x0324, 0x00C4, 6, 0x0000, 0, 0), - MX8MP_PAD_SD2_CMD__OBSERVE_MUX_OUT01 = IOMUX_PAD(0x0324, 0x00C4, 7, 0x0000, 0, 0), MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 = IOMUX_PAD(0x0328, 0x00C8, 0, 0x0000, 0, 0), MX8MP_PAD_SD2_DATA0__I2C4_SDA = IOMUX_PAD(0x0328, 0x00C8, 2 | IOMUX_CONFIG_SION, 0x05C0, 1, 0), MX8MP_PAD_SD2_DATA0__UART2_DCE_RX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x05F0, 2, 0), MX8MP_PAD_SD2_DATA0__UART2_DTE_TX = IOMUX_PAD(0x0328, 0x00C8, 3, 0x0000, 0, 0), - MX8MP_PAD_SD2_DATA0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0328, 0x00C8, 4, 0x04C0, 1, 0), + MX8MP_PAD_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00 = IOMUX_PAD(0x0328, 0x00C8, 4, 0x04C0, 2, 0), MX8MP_PAD_SD2_DATA0__GPIO2_IO15 = IOMUX_PAD(0x0328, 0x00C8, 5, 0x0000, 0, 0), - MX8MP_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 = IOMUX_PAD(0x0328, 0x00C8, 6, 0x0000, 0, 0), - MX8MP_PAD_SD2_DATA0__OBSERVE_MUX_OUT02 = IOMUX_PAD(0x0328, 0x00C8, 7, 0x0000, 0, 0), MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 = IOMUX_PAD(0x032C, 0x00CC, 0, 0x0000, 0, 0), MX8MP_PAD_SD2_DATA1__I2C4_SCL = IOMUX_PAD(0x032C, 0x00CC, 2 | IOMUX_CONFIG_SION, 0x05BC, 1, 0), MX8MP_PAD_SD2_DATA1__UART2_DCE_TX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x0000, 0, 0), MX8MP_PAD_SD2_DATA1__UART2_DTE_RX = IOMUX_PAD(0x032C, 0x00CC, 3, 0x05F0, 3, 0), - MX8MP_PAD_SD2_DATA1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x032C, 0x00CC, 4, 0x04C4, 1, 0), + MX8MP_PAD_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01 = IOMUX_PAD(0x032C, 0x00CC, 4, 0x04C4, 2, 0), MX8MP_PAD_SD2_DATA1__GPIO2_IO16 = IOMUX_PAD(0x032C, 0x00CC, 5, 0x0000, 0, 0), - MX8MP_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT = IOMUX_PAD(0x032C, 0x00CC, 6, 0x0000, 0, 0), - MX8MP_PAD_SD2_DATA1__OBSERVE_MUX_OUT03 = IOMUX_PAD(0x032C, 0x00CC, 7, 0x0000, 0, 0), MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 = IOMUX_PAD(0x0330, 0x00D0, 0, 0x0000, 0, 0), MX8MP_PAD_SD2_DATA2__ECSPI2_SS0 = IOMUX_PAD(0x0330, 0x00D0, 2, 0x0574, 0, 0), - MX8MP_PAD_SD2_DATA2__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0330, 0x00D0, 3, 0x0000, 0, 0), - MX8MP_PAD_SD2_DATA2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0330, 0x00D0, 4, 0x04C8, 1, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_SPDIF1_OUT = IOMUX_PAD(0x0330, 0x00D0, 3, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02 = IOMUX_PAD(0x0330, 0x00D0, 4, 0x04C8, 2, 0), MX8MP_PAD_SD2_DATA2__GPIO2_IO17 = IOMUX_PAD(0x0330, 0x00D0, 5, 0x0000, 0, 0), - MX8MP_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP = IOMUX_PAD(0x0330, 0x00D0, 6, 0x0000, 0, 0), - MX8MP_PAD_SD2_DATA2__OBSERVE_MUX_OUT04 = IOMUX_PAD(0x0330, 0x00D0, 7, 0x0000, 0, 0), MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 = IOMUX_PAD(0x0334, 0x00D4, 0, 0x0000, 0, 0), MX8MP_PAD_SD2_DATA3__ECSPI2_MISO = IOMUX_PAD(0x0334, 0x00D4, 2, 0x056C, 0, 0), - MX8MP_PAD_SD2_DATA3__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0334, 0x00D4, 3, 0x0544, 1, 0), - MX8MP_PAD_SD2_DATA3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0334, 0x00D4, 4, 0x04CC, 1, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_SPDIF1_IN = IOMUX_PAD(0x0334, 0x00D4, 3, 0x0544, 1, 0), + MX8MP_PAD_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 = IOMUX_PAD(0x0334, 0x00D4, 4, 0x04CC, 2, 0), MX8MP_PAD_SD2_DATA3__GPIO2_IO18 = IOMUX_PAD(0x0334, 0x00D4, 5, 0x0000, 0, 0), - MX8MP_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET = IOMUX_PAD(0x0334, 0x00D4, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_DATA3__SRC_EARLY_RESET = IOMUX_PAD(0x0334, 0x00D4, 6, 0x0000, 0, 0), MX8MP_PAD_SD2_RESET_B__USDHC2_RESET_B = IOMUX_PAD(0x0338, 0x00D8, 0, 0x0000, 0, 0), MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 = IOMUX_PAD(0x0338, 0x00D8, 5, 0x0000, 0, 0), - MX8MP_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET = IOMUX_PAD(0x0338, 0x00D8, 6, 0x0000, 0, 0), + MX8MP_PAD_SD2_RESET_B__SRC_SYSTEM_RESET = IOMUX_PAD(0x0338, 0x00D8, 6, 0x0000, 0, 0), MX8MP_PAD_SD2_WP__USDHC2_WP = IOMUX_PAD(0x033C, 0x00DC, 0, 0x0000, 0, 0), MX8MP_PAD_SD2_WP__GPIO2_IO20 = IOMUX_PAD(0x033C, 0x00DC, 5, 0x0000, 0, 0), MX8MP_PAD_SD2_WP__CORESIGHT_EVENTI = IOMUX_PAD(0x033C, 0x00DC, 6, 0x0000, 0, 0), - MX8MP_PAD_SD2_WP__SIM_M_HMASTLOCK = IOMUX_PAD(0x033C, 0x00DC, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_ALE__RAWNAND_ALE = IOMUX_PAD(0x0340, 0x00E0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_ALE__NAND_ALE = IOMUX_PAD(0x0340, 0x00E0, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_ALE__FLEXSPI_A_SCLK = IOMUX_PAD(0x0340, 0x00E0, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0340, 0x00E0, 2, 0x04E8, 0, 0), - MX8MP_PAD_NAND_ALE__MEDIAMIX_ISP_FL_TRIG_0 = IOMUX_PAD(0x0340, 0x00E0, 3, 0x05D4, 1, 0), + MX8MP_PAD_NAND_ALE__ISP_FL_TRIG_0 = IOMUX_PAD(0x0340, 0x00E0, 3, 0x05D4, 1, 0), MX8MP_PAD_NAND_ALE__UART3_DCE_RX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x05F8, 2, 0), MX8MP_PAD_NAND_ALE__UART3_DTE_TX = IOMUX_PAD(0x0340, 0x00E0, 4, 0x0000, 0, 0), MX8MP_PAD_NAND_ALE__GPIO3_IO00 = IOMUX_PAD(0x0340, 0x00E0, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_ALE__CORESIGHT_TRACE_CLK = IOMUX_PAD(0x0340, 0x00E0, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_ALE__SIM_M_HPROT00 = IOMUX_PAD(0x0340, 0x00E0, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_CE0_B__RAWNAND_CE0_B = IOMUX_PAD(0x0344, 0x00E4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE0_B__NAND_CE0_B = IOMUX_PAD(0x0344, 0x00E4, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_CE0_B__FLEXSPI_A_SS0_B = IOMUX_PAD(0x0344, 0x00E4, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x0344, 0x00E4, 2, 0x0000, 0, 0), - MX8MP_PAD_NAND_CE0_B__MEDIAMIX_ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0344, 0x00E4, 3, 0x05DC, 1, 0), + MX8MP_PAD_NAND_CE0_B__ISP_SHUTTER_TRIG_0 = IOMUX_PAD(0x0344, 0x00E4, 3, 0x05DC, 1, 0), MX8MP_PAD_NAND_CE0_B__UART3_DCE_TX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x0000, 0, 0), MX8MP_PAD_NAND_CE0_B__UART3_DTE_RX = IOMUX_PAD(0x0344, 0x00E4, 4, 0x05F8, 3, 0), MX8MP_PAD_NAND_CE0_B__GPIO3_IO01 = IOMUX_PAD(0x0344, 0x00E4, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_CE0_B__CORESIGHT_TRACE_CTL = IOMUX_PAD(0x0344, 0x00E4, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_CE0_B__SIM_M_HPROT01 = IOMUX_PAD(0x0344, 0x00E4, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_CE1_B__RAWNAND_CE1_B = IOMUX_PAD(0x0348, 0x00E8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE1_B__NAND_CE1_B = IOMUX_PAD(0x0348, 0x00E8, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_CE1_B__FLEXSPI_A_SS1_B = IOMUX_PAD(0x0348, 0x00E8, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_CE1_B__USDHC3_STROBE = IOMUX_PAD(0x0348, 0x00E8, 2, 0x0630, 1, 0), MX8MP_PAD_NAND_CE1_B__I2C4_SCL = IOMUX_PAD(0x0348, 0x00E8, 4 | IOMUX_CONFIG_SION, 0x05BC, 2, 0), MX8MP_PAD_NAND_CE1_B__GPIO3_IO02 = IOMUX_PAD(0x0348, 0x00E8, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_CE1_B__CORESIGHT_TRACE00 = IOMUX_PAD(0x0348, 0x00E8, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_CE1_B__SIM_M_HPROT02 = IOMUX_PAD(0x0348, 0x00E8, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_CE2_B__RAWNAND_CE2_B = IOMUX_PAD(0x034C, 0x00EC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE2_B__NAND_CE2_B = IOMUX_PAD(0x034C, 0x00EC, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_CE2_B__FLEXSPI_B_SS0_B = IOMUX_PAD(0x034C, 0x00EC, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 = IOMUX_PAD(0x034C, 0x00EC, 2, 0x0624, 1, 0), MX8MP_PAD_NAND_CE2_B__I2C4_SDA = IOMUX_PAD(0x034C, 0x00EC, 4 | IOMUX_CONFIG_SION, 0x05C0, 2, 0), MX8MP_PAD_NAND_CE2_B__GPIO3_IO03 = IOMUX_PAD(0x034C, 0x00EC, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_CE2_B__CORESIGHT_TRACE01 = IOMUX_PAD(0x034C, 0x00EC, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_CE2_B__SIM_M_HPROT03 = IOMUX_PAD(0x034C, 0x00EC, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_CE3_B__RAWNAND_CE3_B = IOMUX_PAD(0x0350, 0x00F0, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CE3_B__NAND_CE3_B = IOMUX_PAD(0x0350, 0x00F0, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_CE3_B__FLEXSPI_B_SS1_B = IOMUX_PAD(0x0350, 0x00F0, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 = IOMUX_PAD(0x0350, 0x00F0, 2, 0x0628, 1, 0), MX8MP_PAD_NAND_CE3_B__I2C3_SDA = IOMUX_PAD(0x0350, 0x00F0, 4 | IOMUX_CONFIG_SION, 0x05B8, 1, 0), MX8MP_PAD_NAND_CE3_B__GPIO3_IO04 = IOMUX_PAD(0x0350, 0x00F0, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_CE3_B__CORESIGHT_TRACE02 = IOMUX_PAD(0x0350, 0x00F0, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_CE3_B__SIM_M_HADDR00 = IOMUX_PAD(0x0350, 0x00F0, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_CLE__RAWNAND_CLE = IOMUX_PAD(0x0354, 0x00F4, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_CLE__NAND_CLE = IOMUX_PAD(0x0354, 0x00F4, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_CLE__FLEXSPI_B_SCLK = IOMUX_PAD(0x0354, 0x00F4, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_CLE__USDHC3_DATA7 = IOMUX_PAD(0x0354, 0x00F4, 2, 0x062C, 1, 0), MX8MP_PAD_NAND_CLE__UART4_DCE_RX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0600, 2, 0), MX8MP_PAD_NAND_CLE__UART4_DTE_TX = IOMUX_PAD(0x0354, 0x00F4, 4, 0x0000, 0, 0), MX8MP_PAD_NAND_CLE__GPIO3_IO05 = IOMUX_PAD(0x0354, 0x00F4, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_CLE__CORESIGHT_TRACE03 = IOMUX_PAD(0x0354, 0x00F4, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_CLE__SIM_M_HADDR01 = IOMUX_PAD(0x0354, 0x00F4, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA00__RAWNAND_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__NAND_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA00__FLEXSPI_A_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0358, 0x00F8, 2, 0x04E4, 0, 0), - MX8MP_PAD_NAND_DATA00__MEDIAMIX_ISP_FLASH_TRIG_0 = IOMUX_PAD(0x0358, 0x00F8, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA00__ISP_FLASH_TRIG_0 = IOMUX_PAD(0x0358, 0x00F8, 3, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA00__UART4_DCE_RX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0600, 3, 0), MX8MP_PAD_NAND_DATA00__UART4_DTE_TX = IOMUX_PAD(0x0358, 0x00F8, 4, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA00__GPIO3_IO06 = IOMUX_PAD(0x0358, 0x00F8, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA00__CORESIGHT_TRACE04 = IOMUX_PAD(0x0358, 0x00F8, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA00__SIM_M_HADDR02 = IOMUX_PAD(0x0358, 0x00F8, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA01__RAWNAND_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__NAND_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA01__FLEXSPI_A_DATA01 = IOMUX_PAD(0x035C, 0x00FC, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x035C, 0x00FC, 2, 0x04EC, 0, 0), - MX8MP_PAD_NAND_DATA01__MEDIAMIX_ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x035C, 0x00FC, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA01__ISP_PRELIGHT_TRIG_0 = IOMUX_PAD(0x035C, 0x00FC, 3, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA01__UART4_DCE_TX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA01__UART4_DTE_RX = IOMUX_PAD(0x035C, 0x00FC, 4, 0x0600, 4, 0), MX8MP_PAD_NAND_DATA01__GPIO3_IO07 = IOMUX_PAD(0x035C, 0x00FC, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA01__CORESIGHT_TRACE05 = IOMUX_PAD(0x035C, 0x00FC, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA01__SIM_M_HADDR03 = IOMUX_PAD(0x035C, 0x00FC, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA02__RAWNAND_DATA02 = IOMUX_PAD(0x0360, 0x0100, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA02__NAND_DATA02 = IOMUX_PAD(0x0360, 0x0100, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA02__FLEXSPI_A_DATA02 = IOMUX_PAD(0x0360, 0x0100, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA02__USDHC3_CD_B = IOMUX_PAD(0x0360, 0x0100, 2, 0x0608, 2, 0), MX8MP_PAD_NAND_DATA02__UART4_DCE_CTS = IOMUX_PAD(0x0360, 0x0100, 3, 0x0000, 0, 0), @@ -454,92 +388,81 @@ enum { MX8MP_PAD_NAND_DATA02__I2C4_SDA = IOMUX_PAD(0x0360, 0x0100, 4 | IOMUX_CONFIG_SION, 0x05C0, 3, 0), MX8MP_PAD_NAND_DATA02__GPIO3_IO08 = IOMUX_PAD(0x0360, 0x0100, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA02__CORESIGHT_TRACE06 = IOMUX_PAD(0x0360, 0x0100, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA02__SIM_M_HADDR04 = IOMUX_PAD(0x0360, 0x0100, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA03__RAWNAND_DATA03 = IOMUX_PAD(0x0364, 0x0104, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA03__NAND_DATA03 = IOMUX_PAD(0x0364, 0x0104, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA03__FLEXSPI_A_DATA03 = IOMUX_PAD(0x0364, 0x0104, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA03__USDHC3_WP = IOMUX_PAD(0x0364, 0x0104, 2, 0x0634, 2, 0), MX8MP_PAD_NAND_DATA03__UART4_DCE_RTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x05FC, 1, 0), MX8MP_PAD_NAND_DATA03__UART4_DTE_CTS = IOMUX_PAD(0x0364, 0x0104, 3, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA03__MEDIAMIX_ISP_FL_TRIG_1 = IOMUX_PAD(0x0364, 0x0104, 4, 0x05D8, 1, 0), + MX8MP_PAD_NAND_DATA03__ISP_FL_TRIG_1 = IOMUX_PAD(0x0364, 0x0104, 4, 0x05D8, 1, 0), MX8MP_PAD_NAND_DATA03__GPIO3_IO09 = IOMUX_PAD(0x0364, 0x0104, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA03__CORESIGHT_TRACE07 = IOMUX_PAD(0x0364, 0x0104, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA03__SIM_M_HADDR05 = IOMUX_PAD(0x0364, 0x0104, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA04__RAWNAND_DATA04 = IOMUX_PAD(0x0368, 0x0108, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA04__NAND_DATA04 = IOMUX_PAD(0x0368, 0x0108, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA04__FLEXSPI_B_DATA00 = IOMUX_PAD(0x0368, 0x0108, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 = IOMUX_PAD(0x0368, 0x0108, 2, 0x0610, 1, 0), MX8MP_PAD_NAND_DATA04__FLEXSPI_A_DATA04 = IOMUX_PAD(0x0368, 0x0108, 3, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA04__MEDIAMIX_ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x0368, 0x0108, 4, 0x05E0, 1, 0), + MX8MP_PAD_NAND_DATA04__ISP_SHUTTER_TRIG_1 = IOMUX_PAD(0x0368, 0x0108, 4, 0x05E0, 1, 0), MX8MP_PAD_NAND_DATA04__GPIO3_IO10 = IOMUX_PAD(0x0368, 0x0108, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA04__CORESIGHT_TRACE08 = IOMUX_PAD(0x0368, 0x0108, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA04__SIM_M_HADDR06 = IOMUX_PAD(0x0368, 0x0108, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA05__RAWNAND_DATA05 = IOMUX_PAD(0x036C, 0x010C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__NAND_DATA05 = IOMUX_PAD(0x036C, 0x010C, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA05__FLEXSPI_B_DATA01 = IOMUX_PAD(0x036C, 0x010C, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 = IOMUX_PAD(0x036C, 0x010C, 2, 0x0614, 1, 0), MX8MP_PAD_NAND_DATA05__FLEXSPI_A_DATA05 = IOMUX_PAD(0x036C, 0x010C, 3, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA05__MEDIAMIX_ISP_FLASH_TRIG_1 = IOMUX_PAD(0x036C, 0x010C, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA05__ISP_FLASH_TRIG_1 = IOMUX_PAD(0x036C, 0x010C, 4, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA05__GPIO3_IO11 = IOMUX_PAD(0x036C, 0x010C, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA05__CORESIGHT_TRACE09 = IOMUX_PAD(0x036C, 0x010C, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA05__SIM_M_HADDR07 = IOMUX_PAD(0x036C, 0x010C, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA06__RAWNAND_DATA06 = IOMUX_PAD(0x0370, 0x0110, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__NAND_DATA06 = IOMUX_PAD(0x0370, 0x0110, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA06__FLEXSPI_B_DATA02 = IOMUX_PAD(0x0370, 0x0110, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 = IOMUX_PAD(0x0370, 0x0110, 2, 0x0618, 1, 0), MX8MP_PAD_NAND_DATA06__FLEXSPI_A_DATA06 = IOMUX_PAD(0x0370, 0x0110, 3, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA06__MEDIAMIX_ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0370, 0x0110, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA06__ISP_PRELIGHT_TRIG_1 = IOMUX_PAD(0x0370, 0x0110, 4, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA06__GPIO3_IO12 = IOMUX_PAD(0x0370, 0x0110, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA06__CORESIGHT_TRACE10 = IOMUX_PAD(0x0370, 0x0110, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA06__SIM_M_HADDR08 = IOMUX_PAD(0x0370, 0x0110, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA07__RAWNAND_DATA07 = IOMUX_PAD(0x0374, 0x0114, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__NAND_DATA07 = IOMUX_PAD(0x0374, 0x0114, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA07__FLEXSPI_B_DATA03 = IOMUX_PAD(0x0374, 0x0114, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 = IOMUX_PAD(0x0374, 0x0114, 2, 0x061C, 1, 0), MX8MP_PAD_NAND_DATA07__FLEXSPI_A_DATA07 = IOMUX_PAD(0x0374, 0x0114, 3, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA07__MEDIAMIX_ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0374, 0x0114, 4, 0x0000, 0, 0), + MX8MP_PAD_NAND_DATA07__ISP_SHUTTER_OPEN_1 = IOMUX_PAD(0x0374, 0x0114, 4, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA07__GPIO3_IO13 = IOMUX_PAD(0x0374, 0x0114, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_DATA07__CORESIGHT_TRACE11 = IOMUX_PAD(0x0374, 0x0114, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_DATA07__SIM_M_HADDR09 = IOMUX_PAD(0x0374, 0x0114, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_DQS__RAWNAND_DQS = IOMUX_PAD(0x0378, 0x0118, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__NAND_DQS = IOMUX_PAD(0x0378, 0x0118, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_DQS__FLEXSPI_A_DQS = IOMUX_PAD(0x0378, 0x0118, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_DQS__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0378, 0x0118, 2, 0x04E0, 0, 0), - MX8MP_PAD_NAND_DQS__MEDIAMIX_ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0378, 0x0118, 3, 0x0000, 0, 0), + MX8MP_PAD_NAND_DQS__ISP_SHUTTER_OPEN_0 = IOMUX_PAD(0x0378, 0x0118, 3, 0x0000, 0, 0), MX8MP_PAD_NAND_DQS__I2C3_SCL = IOMUX_PAD(0x0378, 0x0118, 4 | IOMUX_CONFIG_SION, 0x05B4, 1, 0), MX8MP_PAD_NAND_DQS__GPIO3_IO14 = IOMUX_PAD(0x0378, 0x0118, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_DQS__CORESIGHT_TRACE12 = IOMUX_PAD(0x0378, 0x0118, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_DQS__SIM_M_HADDR10 = IOMUX_PAD(0x0378, 0x0118, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_RE_B__RAWNAND_RE_B = IOMUX_PAD(0x037C, 0x011C, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_RE_B__NAND_RE_B = IOMUX_PAD(0x037C, 0x011C, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_RE_B__FLEXSPI_B_DQS = IOMUX_PAD(0x037C, 0x011C, 1, 0x0000, 0, 0), MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 = IOMUX_PAD(0x037C, 0x011C, 2, 0x0620, 1, 0), MX8MP_PAD_NAND_RE_B__UART4_DCE_TX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0000, 0, 0), MX8MP_PAD_NAND_RE_B__UART4_DTE_RX = IOMUX_PAD(0x037C, 0x011C, 4, 0x0600, 5, 0), MX8MP_PAD_NAND_RE_B__GPIO3_IO15 = IOMUX_PAD(0x037C, 0x011C, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_RE_B__CORESIGHT_TRACE13 = IOMUX_PAD(0x037C, 0x011C, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_RE_B__SIM_M_HADDR11 = IOMUX_PAD(0x037C, 0x011C, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_READY_B__RAWNAND_READY_B = IOMUX_PAD(0x0380, 0x0120, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_READY_B__NAND_READY_B = IOMUX_PAD(0x0380, 0x0120, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_READY_B__USDHC3_RESET_B = IOMUX_PAD(0x0380, 0x0120, 2, 0x0000, 0, 0), MX8MP_PAD_NAND_READY_B__I2C3_SCL = IOMUX_PAD(0x0380, 0x0120, 4 | IOMUX_CONFIG_SION, 0x05B4, 2, 0), MX8MP_PAD_NAND_READY_B__GPIO3_IO16 = IOMUX_PAD(0x0380, 0x0120, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_READY_B__CORESIGHT_TRACE14 = IOMUX_PAD(0x0380, 0x0120, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_READY_B__SIM_M_HADDR12 = IOMUX_PAD(0x0380, 0x0120, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_WE_B__RAWNAND_WE_B = IOMUX_PAD(0x0384, 0x0124, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WE_B__NAND_WE_B = IOMUX_PAD(0x0384, 0x0124, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_WE_B__USDHC3_CLK = IOMUX_PAD(0x0384, 0x0124, 2, 0x0604, 1, 0), MX8MP_PAD_NAND_WE_B__I2C3_SDA = IOMUX_PAD(0x0384, 0x0124, 4 | IOMUX_CONFIG_SION, 0x05B8, 2, 0), MX8MP_PAD_NAND_WE_B__GPIO3_IO17 = IOMUX_PAD(0x0384, 0x0124, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_WE_B__CORESIGHT_TRACE15 = IOMUX_PAD(0x0384, 0x0124, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_WE_B__SIM_M_HADDR13 = IOMUX_PAD(0x0384, 0x0124, 7, 0x0000, 0, 0), - MX8MP_PAD_NAND_WP_B__RAWNAND_WP_B = IOMUX_PAD(0x0388, 0x0128, 0, 0x0000, 0, 0), + MX8MP_PAD_NAND_WP_B__NAND_WP_B = IOMUX_PAD(0x0388, 0x0128, 0, 0x0000, 0, 0), MX8MP_PAD_NAND_WP_B__USDHC3_CMD = IOMUX_PAD(0x0388, 0x0128, 2, 0x060C, 1, 0), MX8MP_PAD_NAND_WP_B__I2C4_SCL = IOMUX_PAD(0x0388, 0x0128, 4 | IOMUX_CONFIG_SION, 0x05BC, 3, 0), MX8MP_PAD_NAND_WP_B__GPIO3_IO18 = IOMUX_PAD(0x0388, 0x0128, 5, 0x0000, 0, 0), MX8MP_PAD_NAND_WP_B__CORESIGHT_EVENTO = IOMUX_PAD(0x0388, 0x0128, 6, 0x0000, 0, 0), - MX8MP_PAD_NAND_WP_B__SIM_M_HADDR14 = IOMUX_PAD(0x0388, 0x0128, 7, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x038C, 0x012C, 0, 0x0508, 0, 0), MX8MP_PAD_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x038C, 0x012C, 1, 0x0000, 0, 0), @@ -551,21 +474,21 @@ enum { MX8MP_PAD_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x0390, 0x0130, 1, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXC__PWM3_OUT = IOMUX_PAD(0x0390, 0x0130, 2, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXC__I2C6_SDA = IOMUX_PAD(0x0390, 0x0130, 3 | IOMUX_CONFIG_SION, 0x05D0, 1, 0), - MX8MP_PAD_SAI5_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x0390, 0x0130, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI5_RXC__AUDIOMIX_PDM_CLK = IOMUX_PAD(0x0390, 0x0130, 4, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXC__GPIO3_IO20 = IOMUX_PAD(0x0390, 0x0130, 5, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x0394, 0x0134, 0, 0x04F8, 0, 0), MX8MP_PAD_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x0394, 0x0134, 1, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD0__PWM2_OUT = IOMUX_PAD(0x0394, 0x0134, 2, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD0__I2C5_SCL = IOMUX_PAD(0x0394, 0x0134, 3 | IOMUX_CONFIG_SION, 0x05C4, 1, 0), - MX8MP_PAD_SAI5_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0394, 0x0134, 4, 0x04C0, 2, 0), + MX8MP_PAD_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 = IOMUX_PAD(0x0394, 0x0134, 4, 0x04C0, 3, 0), MX8MP_PAD_SAI5_RXD0__GPIO3_IO21 = IOMUX_PAD(0x0394, 0x0134, 5, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x0398, 0x0138, 0, 0x04FC, 0, 0), MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x0398, 0x0138, 1, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 2, 0x04D8, 0, 0), MX8MP_PAD_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x0398, 0x0138, 3, 0x0510, 0, 0), - MX8MP_PAD_SAI5_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0398, 0x0138, 4, 0x04C4, 2, 0), + MX8MP_PAD_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 = IOMUX_PAD(0x0398, 0x0138, 4, 0x04C4, 3, 0), MX8MP_PAD_SAI5_RXD1__GPIO3_IO22 = IOMUX_PAD(0x0398, 0x0138, 5, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD1__CAN1_TX = IOMUX_PAD(0x0398, 0x0138, 6, 0x0000, 0, 0), @@ -573,7 +496,7 @@ enum { MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 = IOMUX_PAD(0x039C, 0x013C, 1, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x039C, 0x013C, 2, 0x04D8, 1, 0), MX8MP_PAD_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x039C, 0x013C, 3, 0x050C, 0, 0), - MX8MP_PAD_SAI5_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x039C, 0x013C, 4, 0x04C8, 2, 0), + MX8MP_PAD_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 = IOMUX_PAD(0x039C, 0x013C, 4, 0x04C8, 3, 0), MX8MP_PAD_SAI5_RXD2__GPIO3_IO23 = IOMUX_PAD(0x039C, 0x013C, 5, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD2__CAN1_RX = IOMUX_PAD(0x039C, 0x013C, 6, 0x054C, 0, 0), @@ -581,7 +504,7 @@ enum { MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 = IOMUX_PAD(0x03A0, 0x0140, 1, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03A0, 0x0140, 2, 0x04D8, 2, 0), MX8MP_PAD_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03A0, 0x0140, 3, 0x0000, 0, 0), - MX8MP_PAD_SAI5_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03A0, 0x0140, 4, 0x04CC, 2, 0), + MX8MP_PAD_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 = IOMUX_PAD(0x03A0, 0x0140, 4, 0x04CC, 3, 0), MX8MP_PAD_SAI5_RXD3__GPIO3_IO24 = IOMUX_PAD(0x03A0, 0x0140, 5, 0x0000, 0, 0), MX8MP_PAD_SAI5_RXD3__CAN2_TX = IOMUX_PAD(0x03A0, 0x0140, 6, 0x0000, 0, 0), @@ -593,38 +516,32 @@ enum { MX8MP_PAD_SAI5_MCLK__CAN2_RX = IOMUX_PAD(0x03A4, 0x0144, 6, 0x0550, 0, 0), MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 0, 0x04D0, 0, 0), - MX8MP_PAD_SAI1_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0148, 1, 0x0508, 1, 0), MX8MP_PAD_SAI1_RXFS__ENET1_1588_EVENT0_IN = IOMUX_PAD(0x03A8, 0x0148, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXFS__GPIO4_IO00 = IOMUX_PAD(0x03A8, 0x0148, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_RXC__AUDIOMIX_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x014C, 1, 0x04F4, 1, 0), - MX8MP_PAD_SAI1_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x03AC, 0x014C, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_RXC__AUDIOMIX_PDM_CLK = IOMUX_PAD(0x03AC, 0x014C, 3, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXC__ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x03AC, 0x014C, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXC__GPIO4_IO01 = IOMUX_PAD(0x03AC, 0x014C, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI5_RX_DATA00 = IOMUX_PAD(0x03B0, 0x0150, 1, 0x04F8, 1, 0), MX8MP_PAD_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03B0, 0x0150, 2, 0x0000, 0, 0), - MX8MP_PAD_SAI1_RXD0__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x03B0, 0x0150, 3, 0x04C0, 3, 0), + MX8MP_PAD_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00 = IOMUX_PAD(0x03B0, 0x0150, 3, 0x04C0, 4, 0), MX8MP_PAD_SAI1_RXD0__ENET1_1588_EVENT1_IN = IOMUX_PAD(0x03B0, 0x0150, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXD0__GPIO4_IO02 = IOMUX_PAD(0x03B0, 0x0150, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_RXD1__AUDIOMIX_SAI5_RX_DATA01 = IOMUX_PAD(0x03B4, 0x0154, 1, 0x04FC, 1, 0), - MX8MP_PAD_SAI1_RXD1__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x03B4, 0x0154, 3, 0x04C4, 3, 0), + MX8MP_PAD_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01 = IOMUX_PAD(0x03B4, 0x0154, 3, 0x04C4, 4, 0), MX8MP_PAD_SAI1_RXD1__ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x03B4, 0x0154, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXD1__GPIO4_IO03 = IOMUX_PAD(0x03B4, 0x0154, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_RXD2__AUDIOMIX_SAI5_RX_DATA02 = IOMUX_PAD(0x03B8, 0x0158, 1, 0x0500, 1, 0), - MX8MP_PAD_SAI1_RXD2__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03B8, 0x0158, 3, 0x04C8, 3, 0), + MX8MP_PAD_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02 = IOMUX_PAD(0x03B8, 0x0158, 3, 0x04C8, 4, 0), MX8MP_PAD_SAI1_RXD2__ENET1_MDC = IOMUX_PAD(0x03B8, 0x0158, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXD2__GPIO4_IO04 = IOMUX_PAD(0x03B8, 0x0158, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_RXD3__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x03BC, 0x015C, 1, 0x0504, 1, 0), - MX8MP_PAD_SAI1_RXD3__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x03BC, 0x015C, 3, 0x04CC, 3, 0), + MX8MP_PAD_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03 = IOMUX_PAD(0x03BC, 0x015C, 3, 0x04CC, 4, 0), MX8MP_PAD_SAI1_RXD3__ENET1_MDIO = IOMUX_PAD(0x03BC, 0x015C, 4, 0x057C, 1, 0), MX8MP_PAD_SAI1_RXD3__GPIO4_IO05 = IOMUX_PAD(0x03BC, 0x015C, 5, 0x0000, 0, 0), @@ -655,32 +572,26 @@ enum { MX8MP_PAD_SAI1_RXD7__GPIO4_IO09 = IOMUX_PAD(0x03CC, 0x016C, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 0, 0x04D8, 4, 0), - MX8MP_PAD_SAI1_TXFS__AUDIOMIX_SAI5_TX_SYNC = IOMUX_PAD(0x03D0, 0x0170, 1, 0x0510, 1, 0), MX8MP_PAD_SAI1_TXFS__ENET1_RGMII_RX_CTL = IOMUX_PAD(0x03D0, 0x0170, 4, 0x0588, 1, 0), MX8MP_PAD_SAI1_TXFS__GPIO4_IO10 = IOMUX_PAD(0x03D0, 0x0170, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 0, 0x04D4, 1, 0), - MX8MP_PAD_SAI1_TXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x03D4, 0x0174, 1, 0x050C, 1, 0), MX8MP_PAD_SAI1_TXC__ENET1_RGMII_RXC = IOMUX_PAD(0x03D4, 0x0174, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXC__GPIO4_IO11 = IOMUX_PAD(0x03D4, 0x0174, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_TXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x03D8, 0x0178, 1, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD0__ENET1_RGMII_TD0 = IOMUX_PAD(0x03D8, 0x0178, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD0__GPIO4_IO12 = IOMUX_PAD(0x03D8, 0x0178, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_TXD1__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x03DC, 0x017C, 1, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD1__ENET1_RGMII_TD1 = IOMUX_PAD(0x03DC, 0x017C, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD1__GPIO4_IO13 = IOMUX_PAD(0x03DC, 0x017C, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_TXD2__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x03E0, 0x0180, 1, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD2__ENET1_RGMII_TD2 = IOMUX_PAD(0x03E0, 0x0180, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD2__GPIO4_IO14 = IOMUX_PAD(0x03E0, 0x0180, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_TXD3__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x03E4, 0x0184, 1, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD3__ENET1_RGMII_TD3 = IOMUX_PAD(0x03E4, 0x0184, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD3__GPIO4_IO15 = IOMUX_PAD(0x03E4, 0x0184, 5, 0x0000, 0, 0), @@ -704,12 +615,11 @@ enum { MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 = IOMUX_PAD(0x03F4, 0x0194, 0, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD7__AUDIOMIX_SAI6_MCLK = IOMUX_PAD(0x03F4, 0x0194, 1, 0x0514, 2, 0), - MX8MP_PAD_SAI1_TXD7__AUDIOMIX_CLK = IOMUX_PAD(0x03F4, 0x0194, 3, 0x0000, 0, 0), + MX8MP_PAD_SAI1_TXD7__AUDIOMIX_PDM_CLK = IOMUX_PAD(0x03F4, 0x0194, 3, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD7__ENET1_TX_ER = IOMUX_PAD(0x03F4, 0x0194, 4, 0x0000, 0, 0), MX8MP_PAD_SAI1_TXD7__GPIO4_IO19 = IOMUX_PAD(0x03F4, 0x0194, 5, 0x0000, 0, 0), MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_MCLK = IOMUX_PAD(0x03F8, 0x0198, 0, 0x0000, 0, 0), - MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x03F8, 0x0198, 1, 0x04F0, 1, 0), MX8MP_PAD_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK = IOMUX_PAD(0x03F8, 0x0198, 2, 0x04D4, 2, 0), MX8MP_PAD_SAI1_MCLK__ENET1_TX_CLK = IOMUX_PAD(0x03F8, 0x0198, 4, 0x0578, 1, 0), MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 = IOMUX_PAD(0x03F8, 0x0198, 5, 0x0000, 0, 0), @@ -721,8 +631,7 @@ enum { MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x0000, 0, 0), MX8MP_PAD_SAI2_RXFS__UART1_DTE_RX = IOMUX_PAD(0x03FC, 0x019C, 4, 0x05E8, 2, 0), MX8MP_PAD_SAI2_RXFS__GPIO4_IO21 = IOMUX_PAD(0x03FC, 0x019C, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI2_RXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x03FC, 0x019C, 6, 0x04C8, 4, 0), - MX8MP_PAD_SAI2_RXFS__SIM_M_HSIZE00 = IOMUX_PAD(0x03FC, 0x019C, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02 = IOMUX_PAD(0x03FC, 0x019C, 6, 0x04C8, 5, 0), MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 0, 0x0000, 0, 0), MX8MP_PAD_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK = IOMUX_PAD(0x0400, 0x01A0, 1, 0x050C, 2, 0), @@ -730,8 +639,7 @@ enum { MX8MP_PAD_SAI2_RXC__UART1_DCE_RX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x05E8, 3, 0), MX8MP_PAD_SAI2_RXC__UART1_DTE_TX = IOMUX_PAD(0x0400, 0x01A0, 4, 0x0000, 0, 0), MX8MP_PAD_SAI2_RXC__GPIO4_IO22 = IOMUX_PAD(0x0400, 0x01A0, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI2_RXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0400, 0x01A0, 6, 0x04C4, 4, 0), - MX8MP_PAD_SAI2_RXC__SIM_M_HSIZE01 = IOMUX_PAD(0x0400, 0x01A0, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01 = IOMUX_PAD(0x0400, 0x01A0, 6, 0x04C4, 5, 0), MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 0, 0x0000, 0, 0), MX8MP_PAD_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 = IOMUX_PAD(0x0404, 0x01A4, 1, 0x0000, 0, 0), @@ -740,8 +648,7 @@ enum { MX8MP_PAD_SAI2_RXD0__UART1_DCE_RTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x05E4, 2, 0), MX8MP_PAD_SAI2_RXD0__UART1_DTE_CTS = IOMUX_PAD(0x0404, 0x01A4, 4, 0x0000, 0, 0), MX8MP_PAD_SAI2_RXD0__GPIO4_IO23 = IOMUX_PAD(0x0404, 0x01A4, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI2_RXD0__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0404, 0x01A4, 6, 0x04CC, 4, 0), - MX8MP_PAD_SAI2_RXD0__SIM_M_HSIZE02 = IOMUX_PAD(0x0404, 0x01A4, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03 = IOMUX_PAD(0x0404, 0x01A4, 6, 0x04CC, 5, 0), MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC = IOMUX_PAD(0x0408, 0x01A8, 0, 0x0000, 0, 0), MX8MP_PAD_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 = IOMUX_PAD(0x0408, 0x01A8, 1, 0x0000, 0, 0), @@ -750,15 +657,13 @@ enum { MX8MP_PAD_SAI2_TXFS__UART1_DCE_CTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x0000, 0, 0), MX8MP_PAD_SAI2_TXFS__UART1_DTE_RTS = IOMUX_PAD(0x0408, 0x01A8, 4, 0x05E4, 3, 0), MX8MP_PAD_SAI2_TXFS__GPIO4_IO24 = IOMUX_PAD(0x0408, 0x01A8, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI2_TXFS__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0408, 0x01A8, 6, 0x04C8, 5, 0), - MX8MP_PAD_SAI2_TXFS__SIM_M_HWRITE = IOMUX_PAD(0x0408, 0x01A8, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02 = IOMUX_PAD(0x0408, 0x01A8, 6, 0x04C8, 6, 0), MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK = IOMUX_PAD(0x040C, 0x01AC, 0, 0x0000, 0, 0), MX8MP_PAD_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 = IOMUX_PAD(0x040C, 0x01AC, 1, 0x0000, 0, 0), MX8MP_PAD_SAI2_TXC__CAN1_RX = IOMUX_PAD(0x040C, 0x01AC, 3, 0x054C, 1, 0), MX8MP_PAD_SAI2_TXC__GPIO4_IO25 = IOMUX_PAD(0x040C, 0x01AC, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI2_TXC__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x040C, 0x01AC, 6, 0x04C4, 5, 0), - MX8MP_PAD_SAI2_TXC__SIM_M_HREADYOUT = IOMUX_PAD(0x040C, 0x01AC, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01 = IOMUX_PAD(0x040C, 0x01AC, 6, 0x04C4, 6, 0), MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 = IOMUX_PAD(0x0410, 0x01B0, 0, 0x0000, 0, 0), MX8MP_PAD_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 = IOMUX_PAD(0x0410, 0x01B0, 1, 0x0000, 0, 0), @@ -766,8 +671,6 @@ enum { MX8MP_PAD_SAI2_TXD0__CAN2_TX = IOMUX_PAD(0x0410, 0x01B0, 3, 0x0000, 0, 0), MX8MP_PAD_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN = IOMUX_PAD(0x0410, 0x01B0, 4, 0x0000, 0, 0), MX8MP_PAD_SAI2_TXD0__GPIO4_IO26 = IOMUX_PAD(0x0410, 0x01B0, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI2_TXD0__CCMSRCGPCMIX_BOOT_MODE04 = IOMUX_PAD(0x0410, 0x01B0, 6, 0x0000, 0, 0), - MX8MP_PAD_SAI2_TXD0__TPSMP_CLK = IOMUX_PAD(0x0410, 0x01B0, 7, 0x0000, 0, 0), MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI2_MCLK = IOMUX_PAD(0x0414, 0x01B4, 0, 0x0000, 0, 0), MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01B4, 1, 0x04F0, 2, 0), @@ -776,16 +679,14 @@ enum { MX8MP_PAD_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN = IOMUX_PAD(0x0414, 0x01B4, 4, 0x0000, 0, 0), MX8MP_PAD_SAI2_MCLK__GPIO4_IO27 = IOMUX_PAD(0x0414, 0x01B4, 5, 0x0000, 0, 0), MX8MP_PAD_SAI2_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0414, 0x01B4, 6, 0x04E0, 1, 0), - MX8MP_PAD_SAI2_MCLK__TPSMP_HDATA_DIR = IOMUX_PAD(0x0414, 0x01B4, 7, 0x0000, 0, 0), MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 0, 0x0000, 0, 0), MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 1, 0x04DC, 1, 0), MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC = IOMUX_PAD(0x0418, 0x01B8, 2, 0x0508, 2, 0), MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 = IOMUX_PAD(0x0418, 0x01B8, 3, 0x0000, 0, 0), - MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0418, 0x01B8, 4, 0x0544, 2, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_SPDIF1_IN = IOMUX_PAD(0x0418, 0x01B8, 4, 0x0544, 2, 0), MX8MP_PAD_SAI3_RXFS__GPIO4_IO28 = IOMUX_PAD(0x0418, 0x01B8, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI3_RXFS__AUDIOMIX_BIT_STREAM00 = IOMUX_PAD(0x0418, 0x01B8, 6, 0x04C0, 4, 0), - MX8MP_PAD_SAI3_RXFS__TPSMP_HTRANS00 = IOMUX_PAD(0x0418, 0x01B8, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 = IOMUX_PAD(0x0418, 0x01B8, 6, 0x04C0, 5, 0), MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK = IOMUX_PAD(0x041C, 0x01BC, 0, 0x0000, 0, 0), MX8MP_PAD_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 = IOMUX_PAD(0x041C, 0x01BC, 1, 0x0000, 0, 0), @@ -794,8 +695,7 @@ enum { MX8MP_PAD_SAI3_RXC__UART2_DCE_CTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x0000, 0, 0), MX8MP_PAD_SAI3_RXC__UART2_DTE_RTS = IOMUX_PAD(0x041C, 0x01BC, 4, 0x05EC, 2, 0), MX8MP_PAD_SAI3_RXC__GPIO4_IO29 = IOMUX_PAD(0x041C, 0x01BC, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI3_RXC__AUDIOMIX_CLK = IOMUX_PAD(0x041C, 0x01BC, 6, 0x0000, 0, 0), - MX8MP_PAD_SAI3_RXC__TPSMP_HTRANS01 = IOMUX_PAD(0x041C, 0x01BC, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXC__AUDIOMIX_PDM_CLK = IOMUX_PAD(0x041C, 0x01BC, 6, 0x0000, 0, 0), MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 = IOMUX_PAD(0x0420, 0x01C0, 0, 0x04E4, 1, 0), MX8MP_PAD_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 = IOMUX_PAD(0x0420, 0x01C0, 1, 0x0000, 0, 0), @@ -803,8 +703,7 @@ enum { MX8MP_PAD_SAI3_RXD__UART2_DCE_RTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x05EC, 3, 0), MX8MP_PAD_SAI3_RXD__UART2_DTE_CTS = IOMUX_PAD(0x0420, 0x01C0, 4, 0x0000, 0, 0), MX8MP_PAD_SAI3_RXD__GPIO4_IO30 = IOMUX_PAD(0x0420, 0x01C0, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI3_RXD__AUDIOMIX_BIT_STREAM01 = IOMUX_PAD(0x0420, 0x01C0, 6, 0x04C4, 6, 0), - MX8MP_PAD_SAI3_RXD__TPSMP_HDATA00 = IOMUX_PAD(0x0420, 0x01C0, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01 = IOMUX_PAD(0x0420, 0x01C0, 6, 0x04C4, 7, 0), MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC = IOMUX_PAD(0x0424, 0x01C4, 0, 0x04EC, 1, 0), MX8MP_PAD_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 = IOMUX_PAD(0x0424, 0x01C4, 1, 0x0000, 0, 0), @@ -813,8 +712,7 @@ enum { MX8MP_PAD_SAI3_TXFS__UART2_DCE_RX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x05F0, 4, 0), MX8MP_PAD_SAI3_TXFS__UART2_DTE_TX = IOMUX_PAD(0x0424, 0x01C4, 4, 0x0000, 0, 0), MX8MP_PAD_SAI3_TXFS__GPIO4_IO31 = IOMUX_PAD(0x0424, 0x01C4, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI3_TXFS__AUDIOMIX_BIT_STREAM03 = IOMUX_PAD(0x0424, 0x01C4, 6, 0x04CC, 5, 0), - MX8MP_PAD_SAI3_TXFS__TPSMP_HDATA01 = IOMUX_PAD(0x0424, 0x01C4, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03 = IOMUX_PAD(0x0424, 0x01C4, 6, 0x04CC, 6, 0), MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK = IOMUX_PAD(0x0428, 0x01C8, 0, 0x04E8, 1, 0), MX8MP_PAD_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 = IOMUX_PAD(0x0428, 0x01C8, 1, 0x0000, 0, 0), @@ -823,34 +721,30 @@ enum { MX8MP_PAD_SAI3_TXC__UART2_DCE_TX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x0000, 0, 0), MX8MP_PAD_SAI3_TXC__UART2_DTE_RX = IOMUX_PAD(0x0428, 0x01C8, 4, 0x05F0, 5, 0), MX8MP_PAD_SAI3_TXC__GPIO5_IO00 = IOMUX_PAD(0x0428, 0x01C8, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI3_TXC__AUDIOMIX_BIT_STREAM02 = IOMUX_PAD(0x0428, 0x01C8, 6, 0x04C8, 6, 0), - MX8MP_PAD_SAI3_TXC__TPSMP_HDATA02 = IOMUX_PAD(0x0428, 0x01C8, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02 = IOMUX_PAD(0x0428, 0x01C8, 6, 0x04C8, 7, 0), MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 = IOMUX_PAD(0x042C, 0x01CC, 0, 0x0000, 0, 0), MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 1, 0x0000, 0, 0), MX8MP_PAD_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 = IOMUX_PAD(0x042C, 0x01CC, 2, 0x0504, 2, 0), MX8MP_PAD_SAI3_TXD__GPT1_CAPTURE2 = IOMUX_PAD(0x042C, 0x01CC, 3, 0x0598, 0, 0), - MX8MP_PAD_SAI3_TXD__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x042C, 0x01CC, 4, 0x0548, 0, 0), + MX8MP_PAD_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK = IOMUX_PAD(0x042C, 0x01CC, 4, 0x0548, 0, 0), MX8MP_PAD_SAI3_TXD__GPIO5_IO01 = IOMUX_PAD(0x042C, 0x01CC, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI3_TXD__CCMSRCGPCMIX_BOOT_MODE05 = IOMUX_PAD(0x042C, 0x01CC, 6, 0x0000, 0, 0), - MX8MP_PAD_SAI3_TXD__TPSMP_HDATA03 = IOMUX_PAD(0x042C, 0x01CC, 7, 0x0000, 0, 0), MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI3_MCLK = IOMUX_PAD(0x0430, 0x01D0, 0, 0x04E0, 2, 0), MX8MP_PAD_SAI3_MCLK__PWM4_OUT = IOMUX_PAD(0x0430, 0x01D0, 1, 0x0000, 0, 0), MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01D0, 2, 0x04F0, 3, 0), - MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0430, 0x01D0, 4, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT = IOMUX_PAD(0x0430, 0x01D0, 4, 0x0000, 0, 0), MX8MP_PAD_SAI3_MCLK__GPIO5_IO02 = IOMUX_PAD(0x0430, 0x01D0, 5, 0x0000, 0, 0), - MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0430, 0x01D0, 6, 0x0544, 3, 0), - MX8MP_PAD_SAI3_MCLK__TPSMP_HDATA04 = IOMUX_PAD(0x0430, 0x01D0, 7, 0x0000, 0, 0), + MX8MP_PAD_SAI3_MCLK__AUDIOMIX_SPDIF1_IN = IOMUX_PAD(0x0430, 0x01D0, 6, 0x0544, 3, 0), - MX8MP_PAD_SPDIF_TX__AUDIOMIX_SPDIF_OUT = IOMUX_PAD(0x0434, 0x01D4, 0, 0x0000, 0, 0), + MX8MP_PAD_SPDIF_TX__AUDIOMIX_SPDIF1_OUT = IOMUX_PAD(0x0434, 0x01D4, 0, 0x0000, 0, 0), MX8MP_PAD_SPDIF_TX__PWM3_OUT = IOMUX_PAD(0x0434, 0x01D4, 1, 0x0000, 0, 0), MX8MP_PAD_SPDIF_TX__I2C5_SCL = IOMUX_PAD(0x0434, 0x01D4, 2 | IOMUX_CONFIG_SION, 0x05C4, 2, 0), MX8MP_PAD_SPDIF_TX__GPT1_COMPARE1 = IOMUX_PAD(0x0434, 0x01D4, 3, 0x0000, 0, 0), MX8MP_PAD_SPDIF_TX__CAN1_TX = IOMUX_PAD(0x0434, 0x01D4, 4, 0x0000, 0, 0), MX8MP_PAD_SPDIF_TX__GPIO5_IO03 = IOMUX_PAD(0x0434, 0x01D4, 5, 0x0000, 0, 0), - MX8MP_PAD_SPDIF_RX__AUDIOMIX_SPDIF_IN = IOMUX_PAD(0x0438, 0x01D8, 0, 0x0544, 4, 0), + MX8MP_PAD_SPDIF_RX__AUDIOMIX_SPDIF1_IN = IOMUX_PAD(0x0438, 0x01D8, 0, 0x0544, 4, 0), MX8MP_PAD_SPDIF_RX__PWM2_OUT = IOMUX_PAD(0x0438, 0x01D8, 1, 0x0000, 0, 0), MX8MP_PAD_SPDIF_RX__I2C5_SDA = IOMUX_PAD(0x0438, 0x01D8, 2 | IOMUX_CONFIG_SION, 0x05C8, 2, 0), MX8MP_PAD_SPDIF_RX__GPT1_COMPARE2 = IOMUX_PAD(0x0438, 0x01D8, 3, 0x0000, 0, 0), @@ -859,7 +753,7 @@ enum { MX8MP_PAD_SPDIF_EXT_CLK__GPT1_COMPARE3 = IOMUX_PAD(0x043C, 0x01DC, 3, 0x0000, 0, 0), MX8MP_PAD_SPDIF_EXT_CLK__GPIO5_IO05 = IOMUX_PAD(0x043C, 0x01DC, 5, 0x0000, 0, 0), - MX8MP_PAD_SPDIF_EXT_CLK__AUDIOMIX_SPDIF_EXT_CLK = IOMUX_PAD(0x043C, 0x01DC, 0, 0x0548, 1, 0), + MX8MP_PAD_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK = IOMUX_PAD(0x043C, 0x01DC, 0, 0x0548, 1, 0), MX8MP_PAD_SPDIF_EXT_CLK__PWM1_OUT = IOMUX_PAD(0x043C, 0x01DC, 1, 0x0000, 0, 0), MX8MP_PAD_ECSPI1_SCLK__ECSPI1_SCLK = IOMUX_PAD(0x0440, 0x01E0, 0, 0x0558, 0, 0), @@ -868,7 +762,6 @@ enum { MX8MP_PAD_ECSPI1_SCLK__I2C1_SCL = IOMUX_PAD(0x0440, 0x01E0, 2 | IOMUX_CONFIG_SION, 0x05A4, 1, 0), MX8MP_PAD_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC = IOMUX_PAD(0x0440, 0x01E0, 3, 0x0538, 1, 0), MX8MP_PAD_ECSPI1_SCLK__GPIO5_IO06 = IOMUX_PAD(0x0440, 0x01E0, 5, 0x0000, 0, 0), - MX8MP_PAD_ECSPI1_SCLK__TPSMP_HDATA08 = IOMUX_PAD(0x0440, 0x01E0, 7, 0x0000, 0, 0), MX8MP_PAD_ECSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x0444, 0x01E4, 0, 0x0560, 0, 0), MX8MP_PAD_ECSPI1_MOSI__UART3_DCE_TX = IOMUX_PAD(0x0444, 0x01E4, 1, 0x0000, 0, 0), @@ -876,7 +769,6 @@ enum { MX8MP_PAD_ECSPI1_MOSI__I2C1_SDA = IOMUX_PAD(0x0444, 0x01E4, 2 | IOMUX_CONFIG_SION, 0x05A8, 1, 0), MX8MP_PAD_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK = IOMUX_PAD(0x0444, 0x01E4, 3, 0x0530, 1, 0), MX8MP_PAD_ECSPI1_MOSI__GPIO5_IO07 = IOMUX_PAD(0x0444, 0x01E4, 5, 0x0000, 0, 0), - MX8MP_PAD_ECSPI1_MOSI__TPSMP_HDATA09 = IOMUX_PAD(0x0444, 0x01E4, 7, 0x0000, 0, 0), MX8MP_PAD_ECSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x0448, 0x01E8, 0, 0x055C, 0, 0), MX8MP_PAD_ECSPI1_MISO__UART3_DCE_CTS = IOMUX_PAD(0x0448, 0x01E8, 1, 0x0000, 0, 0), @@ -884,7 +776,6 @@ enum { MX8MP_PAD_ECSPI1_MISO__I2C2_SCL = IOMUX_PAD(0x0448, 0x01E8, 2 | IOMUX_CONFIG_SION, 0x05AC, 1, 0), MX8MP_PAD_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 = IOMUX_PAD(0x0448, 0x01E8, 3, 0x0534, 1, 0), MX8MP_PAD_ECSPI1_MISO__GPIO5_IO08 = IOMUX_PAD(0x0448, 0x01E8, 5, 0x0000, 0, 0), - MX8MP_PAD_ECSPI1_MISO__TPSMP_HDATA10 = IOMUX_PAD(0x0448, 0x01E8, 7, 0x0000, 0, 0), MX8MP_PAD_ECSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x044C, 0x01EC, 0, 0x0564, 0, 0), MX8MP_PAD_ECSPI1_SS0__UART3_DCE_RTS = IOMUX_PAD(0x044C, 0x01EC, 1, 0x05F4, 3, 0), @@ -892,7 +783,6 @@ enum { MX8MP_PAD_ECSPI1_SS0__I2C2_SDA = IOMUX_PAD(0x044C, 0x01EC, 2 | IOMUX_CONFIG_SION, 0x05B0, 1, 0), MX8MP_PAD_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC = IOMUX_PAD(0x044C, 0x01EC, 3, 0x0540, 1, 0), MX8MP_PAD_ECSPI1_SS0__GPIO5_IO09 = IOMUX_PAD(0x044C, 0x01EC, 5, 0x0000, 0, 0), - MX8MP_PAD_ECSPI1_SS0__TPSMP_HDATA11 = IOMUX_PAD(0x044C, 0x01EC, 7, 0x0000, 0, 0), MX8MP_PAD_ECSPI2_SCLK__ECSPI2_SCLK = IOMUX_PAD(0x0450, 0x01F0, 0, 0x0568, 1, 0), MX8MP_PAD_ECSPI2_SCLK__UART4_DCE_RX = IOMUX_PAD(0x0450, 0x01F0, 1, 0x0600, 6, 0), @@ -900,7 +790,6 @@ enum { MX8MP_PAD_ECSPI2_SCLK__I2C3_SCL = IOMUX_PAD(0x0450, 0x01F0, 2 | IOMUX_CONFIG_SION, 0x05B4, 3, 0), MX8MP_PAD_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK = IOMUX_PAD(0x0450, 0x01F0, 3, 0x053C, 1, 0), MX8MP_PAD_ECSPI2_SCLK__GPIO5_IO10 = IOMUX_PAD(0x0450, 0x01F0, 5, 0x0000, 0, 0), - MX8MP_PAD_ECSPI2_SCLK__TPSMP_HDATA12 = IOMUX_PAD(0x0450, 0x01F0, 7, 0x0000, 0, 0), MX8MP_PAD_ECSPI2_MOSI__ECSPI2_MOSI = IOMUX_PAD(0x0454, 0x01F4, 0, 0x0570, 1, 0), MX8MP_PAD_ECSPI2_MOSI__UART4_DCE_TX = IOMUX_PAD(0x0454, 0x01F4, 1, 0x0000, 0, 0), @@ -908,36 +797,31 @@ enum { MX8MP_PAD_ECSPI2_MOSI__I2C3_SDA = IOMUX_PAD(0x0454, 0x01F4, 2 | IOMUX_CONFIG_SION, 0x05B8, 3, 0), MX8MP_PAD_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 = IOMUX_PAD(0x0454, 0x01F4, 3, 0x0000, 0, 0), MX8MP_PAD_ECSPI2_MOSI__GPIO5_IO11 = IOMUX_PAD(0x0454, 0x01F4, 5, 0x0000, 0, 0), - MX8MP_PAD_ECSPI2_MOSI__TPSMP_HDATA13 = IOMUX_PAD(0x0454, 0x01F4, 7, 0x0000, 0, 0), MX8MP_PAD_ECSPI2_MISO__GPIO5_IO12 = IOMUX_PAD(0x0458, 0x01F8, 5, 0x0000, 0, 0), - MX8MP_PAD_ECSPI2_MISO__TPSMP_HDATA14 = IOMUX_PAD(0x0458, 0x01F8, 7, 0x0000, 0, 0), MX8MP_PAD_ECSPI2_MISO__ECSPI2_MISO = IOMUX_PAD(0x0458, 0x01F8, 0, 0x056C, 1, 0), MX8MP_PAD_ECSPI2_MISO__UART4_DCE_CTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x0000, 0, 0), MX8MP_PAD_ECSPI2_MISO__UART4_DTE_RTS = IOMUX_PAD(0x0458, 0x01F8, 1, 0x05FC, 2, 0), MX8MP_PAD_ECSPI2_MISO__I2C4_SCL = IOMUX_PAD(0x0458, 0x01F8, 2 | IOMUX_CONFIG_SION, 0x05BC, 4, 0), MX8MP_PAD_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK = IOMUX_PAD(0x0458, 0x01F8, 3, 0x052C, 1, 0), - MX8MP_PAD_ECSPI2_MISO__CCMSRCGPCMIX_CLKO1 = IOMUX_PAD(0x0458, 0x01F8, 4, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_MISO__CCM_CLKO1 = IOMUX_PAD(0x0458, 0x01F8, 4, 0x0000, 0, 0), MX8MP_PAD_ECSPI2_SS0__ECSPI2_SS0 = IOMUX_PAD(0x045C, 0x01FC, 0, 0x0574, 1, 0), MX8MP_PAD_ECSPI2_SS0__UART4_DCE_RTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x05FC, 3, 0), MX8MP_PAD_ECSPI2_SS0__UART4_DTE_CTS = IOMUX_PAD(0x045C, 0x01FC, 1, 0x0000, 0, 0), MX8MP_PAD_ECSPI2_SS0__I2C4_SDA = IOMUX_PAD(0x045C, 0x01FC, 2 | IOMUX_CONFIG_SION, 0x05C0, 4, 0), - MX8MP_PAD_ECSPI2_SS0__CCMSRCGPCMIX_CLKO2 = IOMUX_PAD(0x045C, 0x01FC, 4, 0x0000, 0, 0), + MX8MP_PAD_ECSPI2_SS0__CCM_CLKO2 = IOMUX_PAD(0x045C, 0x01FC, 4, 0x0000, 0, 0), MX8MP_PAD_ECSPI2_SS0__GPIO5_IO13 = IOMUX_PAD(0x045C, 0x01FC, 5, 0x0000, 0, 0), - MX8MP_PAD_ECSPI2_SS0__TPSMP_HDATA15 = IOMUX_PAD(0x045C, 0x01FC, 7, 0x0000, 0, 0), MX8MP_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x0460, 0x0200, 0 | IOMUX_CONFIG_SION, 0x05A4, 2, 0), MX8MP_PAD_I2C1_SCL__ENET_QOS_MDC = IOMUX_PAD(0x0460, 0x0200, 1, 0x0000, 0, 0), MX8MP_PAD_I2C1_SCL__ECSPI1_SCLK = IOMUX_PAD(0x0460, 0x0200, 3, 0x0558, 1, 0), MX8MP_PAD_I2C1_SCL__GPIO5_IO14 = IOMUX_PAD(0x0460, 0x0200, 5, 0x0000, 0, 0), - MX8MP_PAD_I2C1_SCL__TPSMP_HDATA16 = IOMUX_PAD(0x0460, 0x0200, 7, 0x0000, 0, 0), MX8MP_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0464, 0x0204, 0 | IOMUX_CONFIG_SION, 0x05A8, 2, 0), MX8MP_PAD_I2C1_SDA__ENET_QOS_MDIO = IOMUX_PAD(0x0464, 0x0204, 1, 0x0590, 2, 0), MX8MP_PAD_I2C1_SDA__ECSPI1_MOSI = IOMUX_PAD(0x0464, 0x0204, 3, 0x0560, 1, 0), MX8MP_PAD_I2C1_SDA__GPIO5_IO15 = IOMUX_PAD(0x0464, 0x0204, 5, 0x0000, 0, 0), - MX8MP_PAD_I2C1_SDA__TPSMP_HDATA17 = IOMUX_PAD(0x0464, 0x0204, 7, 0x0000, 0, 0), MX8MP_PAD_I2C2_SCL__I2C2_SCL = IOMUX_PAD(0x0468, 0x0208, 0 | IOMUX_CONFIG_SION, 0x05AC, 2, 0), MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_IN = IOMUX_PAD(0x0468, 0x0208, 1, 0x0000, 0, 0), @@ -945,55 +829,47 @@ enum { MX8MP_PAD_I2C2_SCL__ECSPI1_MISO = IOMUX_PAD(0x0468, 0x0208, 3, 0x055C, 1, 0), MX8MP_PAD_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN = IOMUX_PAD(0x0468, 0x0208, 4, 0x0000, 0, 0), MX8MP_PAD_I2C2_SCL__GPIO5_IO16 = IOMUX_PAD(0x0468, 0x0208, 5, 0x0000, 0, 0), - MX8MP_PAD_I2C2_SCL__TPSMP_HDATA18 = IOMUX_PAD(0x0468, 0x0208, 7, 0x0000, 0, 0), MX8MP_PAD_I2C2_SDA__I2C2_SDA = IOMUX_PAD(0x046C, 0x020C, 0 | IOMUX_CONFIG_SION, 0x05B0, 2, 0), MX8MP_PAD_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT = IOMUX_PAD(0x046C, 0x020C, 1, 0x0000, 0, 0), MX8MP_PAD_I2C2_SDA__USDHC3_WP = IOMUX_PAD(0x046C, 0x020C, 2, 0x0634, 3, 0), MX8MP_PAD_I2C2_SDA__ECSPI1_SS0 = IOMUX_PAD(0x046C, 0x020C, 3, 0x0564, 1, 0), MX8MP_PAD_I2C2_SDA__GPIO5_IO17 = IOMUX_PAD(0x046C, 0x020C, 5, 0x0000, 0, 0), - MX8MP_PAD_I2C2_SDA__TPSMP_HDATA19 = IOMUX_PAD(0x046C, 0x020C, 7, 0x0000, 0, 0), MX8MP_PAD_I2C3_SCL__I2C3_SCL = IOMUX_PAD(0x0470, 0x0210, 0 | IOMUX_CONFIG_SION, 0x05B4, 4, 0), MX8MP_PAD_I2C3_SCL__PWM4_OUT = IOMUX_PAD(0x0470, 0x0210, 1, 0x0000, 0, 0), MX8MP_PAD_I2C3_SCL__GPT2_CLK = IOMUX_PAD(0x0470, 0x0210, 2, 0x0000, 0, 0), MX8MP_PAD_I2C3_SCL__ECSPI2_SCLK = IOMUX_PAD(0x0470, 0x0210, 3, 0x0568, 2, 0), MX8MP_PAD_I2C3_SCL__GPIO5_IO18 = IOMUX_PAD(0x0470, 0x0210, 5, 0x0000, 0, 0), - MX8MP_PAD_I2C3_SCL__TPSMP_HDATA20 = IOMUX_PAD(0x0470, 0x0210, 7, 0x0000, 0, 0), MX8MP_PAD_I2C3_SDA__I2C3_SDA = IOMUX_PAD(0x0474, 0x0214, 0 | IOMUX_CONFIG_SION, 0x05B8, 4, 0), MX8MP_PAD_I2C3_SDA__PWM3_OUT = IOMUX_PAD(0x0474, 0x0214, 1, 0x0000, 0, 0), MX8MP_PAD_I2C3_SDA__GPT3_CLK = IOMUX_PAD(0x0474, 0x0214, 2, 0x0000, 0, 0), MX8MP_PAD_I2C3_SDA__ECSPI2_MOSI = IOMUX_PAD(0x0474, 0x0214, 3, 0x0570, 2, 0), MX8MP_PAD_I2C3_SDA__GPIO5_IO19 = IOMUX_PAD(0x0474, 0x0214, 5, 0x0000, 0, 0), - MX8MP_PAD_I2C3_SDA__TPSMP_HDATA21 = IOMUX_PAD(0x0474, 0x0214, 7, 0x0000, 0, 0), MX8MP_PAD_I2C4_SCL__I2C4_SCL = IOMUX_PAD(0x0478, 0x0218, 0 | IOMUX_CONFIG_SION, 0x05BC, 5, 0), MX8MP_PAD_I2C4_SCL__PWM2_OUT = IOMUX_PAD(0x0478, 0x0218, 1, 0x0000, 0, 0), - MX8MP_PAD_I2C4_SCL__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0478, 0x0218, 2, 0x05A0, 0, 0), + MX8MP_PAD_I2C4_SCL__PCIE_CLKREQ_B = IOMUX_PAD(0x0478, 0x0218, 2, 0x05A0, 0, 0), MX8MP_PAD_I2C4_SCL__ECSPI2_MISO = IOMUX_PAD(0x0478, 0x0218, 3, 0x056C, 2, 0), MX8MP_PAD_I2C4_SCL__GPIO5_IO20 = IOMUX_PAD(0x0478, 0x0218, 5, 0x0000, 0, 0), - MX8MP_PAD_I2C4_SCL__TPSMP_HDATA22 = IOMUX_PAD(0x0478, 0x0218, 7, 0x0000, 0, 0), MX8MP_PAD_I2C4_SDA__I2C4_SDA = IOMUX_PAD(0x047C, 0x021C, 0 | IOMUX_CONFIG_SION, 0x05C0, 5, 0), MX8MP_PAD_I2C4_SDA__PWM1_OUT = IOMUX_PAD(0x047C, 0x021C, 1, 0x0000, 0, 0), MX8MP_PAD_I2C4_SDA__ECSPI2_SS0 = IOMUX_PAD(0x047C, 0x021C, 3, 0x0574, 2, 0), MX8MP_PAD_I2C4_SDA__GPIO5_IO21 = IOMUX_PAD(0x047C, 0x021C, 5, 0x0000, 0, 0), - MX8MP_PAD_I2C4_SDA__TPSMP_HDATA23 = IOMUX_PAD(0x047C, 0x021C, 7, 0x0000, 0, 0), MX8MP_PAD_UART1_RXD__UART1_DCE_RX = IOMUX_PAD(0x0480, 0x0220, 0, 0x05E8, 4, 0), MX8MP_PAD_UART1_RXD__UART1_DTE_TX = IOMUX_PAD(0x0480, 0x0220, 0, 0x0000, 0, 0), MX8MP_PAD_UART1_RXD__ECSPI3_SCLK = IOMUX_PAD(0x0480, 0x0220, 1, 0x0000, 0, 0), MX8MP_PAD_UART1_RXD__GPIO5_IO22 = IOMUX_PAD(0x0480, 0x0220, 5, 0x0000, 0, 0), - MX8MP_PAD_UART1_RXD__TPSMP_HDATA24 = IOMUX_PAD(0x0480, 0x0220, 7, 0x0000, 0, 0), MX8MP_PAD_UART1_TXD__UART1_DCE_TX = IOMUX_PAD(0x0484, 0x0224, 0, 0x0000, 0, 0), MX8MP_PAD_UART1_TXD__UART1_DTE_RX = IOMUX_PAD(0x0484, 0x0224, 0, 0x05E8, 5, 0), MX8MP_PAD_UART1_TXD__ECSPI3_MOSI = IOMUX_PAD(0x0484, 0x0224, 1, 0x0000, 0, 0), MX8MP_PAD_UART1_TXD__GPIO5_IO23 = IOMUX_PAD(0x0484, 0x0224, 5, 0x0000, 0, 0), - MX8MP_PAD_UART1_TXD__TPSMP_HDATA25 = IOMUX_PAD(0x0484, 0x0224, 7, 0x0000, 0, 0), MX8MP_PAD_UART2_RXD__UART2_DCE_RX = IOMUX_PAD(0x0488, 0x0228, 0, 0x05F0, 6, 0), @@ -1001,7 +877,6 @@ enum { MX8MP_PAD_UART2_RXD__ECSPI3_MISO = IOMUX_PAD(0x0488, 0x0228, 1, 0x0000, 0, 0), MX8MP_PAD_UART2_RXD__GPT1_COMPARE3 = IOMUX_PAD(0x0488, 0x0228, 3, 0x0000, 0, 0), MX8MP_PAD_UART2_RXD__GPIO5_IO24 = IOMUX_PAD(0x0488, 0x0228, 5, 0x0000, 0, 0), - MX8MP_PAD_UART2_RXD__TPSMP_HDATA26 = IOMUX_PAD(0x0488, 0x0228, 7, 0x0000, 0, 0), MX8MP_PAD_UART2_TXD__UART2_DCE_TX = IOMUX_PAD(0x048C, 0x022C, 0, 0x0000, 0, 0), @@ -1009,7 +884,6 @@ enum { MX8MP_PAD_UART2_TXD__ECSPI3_SS0 = IOMUX_PAD(0x048C, 0x022C, 1, 0x0000, 0, 0), MX8MP_PAD_UART2_TXD__GPT1_COMPARE2 = IOMUX_PAD(0x048C, 0x022C, 3, 0x0000, 0, 0), MX8MP_PAD_UART2_TXD__GPIO5_IO25 = IOMUX_PAD(0x048C, 0x022C, 5, 0x0000, 0, 0), - MX8MP_PAD_UART2_TXD__TPSMP_HDATA27 = IOMUX_PAD(0x048C, 0x022C, 7, 0x0000, 0, 0), MX8MP_PAD_UART3_RXD__UART3_DCE_RX = IOMUX_PAD(0x0490, 0x0230, 0, 0x05F8, 6, 0), @@ -1020,7 +894,6 @@ enum { MX8MP_PAD_UART3_RXD__GPT1_CAPTURE2 = IOMUX_PAD(0x0490, 0x0230, 3, 0x0598, 1, 0), MX8MP_PAD_UART3_RXD__CAN2_TX = IOMUX_PAD(0x0490, 0x0230, 4, 0x0000, 0, 0), MX8MP_PAD_UART3_RXD__GPIO5_IO26 = IOMUX_PAD(0x0490, 0x0230, 5, 0x0000, 0, 0), - MX8MP_PAD_UART3_RXD__TPSMP_HDATA28 = IOMUX_PAD(0x0490, 0x0230, 7, 0x0000, 0, 0), MX8MP_PAD_UART3_TXD__UART3_DCE_TX = IOMUX_PAD(0x0494, 0x0234, 0, 0x0000, 0, 0), @@ -1031,18 +904,16 @@ enum { MX8MP_PAD_UART3_TXD__GPT1_CLK = IOMUX_PAD(0x0494, 0x0234, 3, 0x059C, 1, 0), MX8MP_PAD_UART3_TXD__CAN2_RX = IOMUX_PAD(0x0494, 0x0234, 4, 0x0550, 2, 0), MX8MP_PAD_UART3_TXD__GPIO5_IO27 = IOMUX_PAD(0x0494, 0x0234, 5, 0x0000, 0, 0), - MX8MP_PAD_UART3_TXD__TPSMP_HDATA29 = IOMUX_PAD(0x0494, 0x0234, 7, 0x0000, 0, 0), MX8MP_PAD_UART4_RXD__UART4_DCE_RX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0600, 8, 0), MX8MP_PAD_UART4_RXD__UART4_DTE_TX = IOMUX_PAD(0x0498, 0x0238, 0, 0x0000, 0, 0), MX8MP_PAD_UART4_RXD__UART2_DCE_CTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x0000, 0, 0), MX8MP_PAD_UART4_RXD__UART2_DTE_RTS = IOMUX_PAD(0x0498, 0x0238, 1, 0x05EC, 4, 0), - MX8MP_PAD_UART4_RXD__HSIOMIX_PCIE_CLKREQ_B = IOMUX_PAD(0x0498, 0x0238, 2, 0x05A0, 1, 0), + MX8MP_PAD_UART4_RXD__PCIE_CLKREQ_B = IOMUX_PAD(0x0498, 0x0238, 2, 0x05A0, 1, 0), MX8MP_PAD_UART4_RXD__GPT1_COMPARE1 = IOMUX_PAD(0x0498, 0x0238, 3, 0x0000, 0, 0), MX8MP_PAD_UART4_RXD__I2C6_SCL = IOMUX_PAD(0x0498, 0x0238, 4 | IOMUX_CONFIG_SION, 0x05CC, 2, 0), MX8MP_PAD_UART4_RXD__GPIO5_IO28 = IOMUX_PAD(0x0498, 0x0238, 5, 0x0000, 0, 0), - MX8MP_PAD_UART4_RXD__TPSMP_HDATA30 = IOMUX_PAD(0x0498, 0x0238, 7, 0x0000, 0, 0), MX8MP_PAD_UART4_TXD__UART4_DCE_TX = IOMUX_PAD(0x049C, 0x023C, 0, 0x0000, 0, 0), @@ -1052,27 +923,24 @@ enum { MX8MP_PAD_UART4_TXD__GPT1_CAPTURE1 = IOMUX_PAD(0x049C, 0x023C, 3, 0x0594, 1, 0), MX8MP_PAD_UART4_TXD__I2C6_SDA = IOMUX_PAD(0x049C, 0x023C, 4 | IOMUX_CONFIG_SION, 0x05D0, 2, 0), MX8MP_PAD_UART4_TXD__GPIO5_IO29 = IOMUX_PAD(0x049C, 0x023C, 5, 0x0000, 0, 0), - MX8MP_PAD_UART4_TXD__TPSMP_HDATA31 = IOMUX_PAD(0x049C, 0x023C, 7, 0x0000, 0, 0), - MX8MP_PAD_HDMI_DDC_SCL__HDMIMIX_EARC_SCL = IOMUX_PAD(0x04A0, 0x0240, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL = IOMUX_PAD(0x04A0, 0x0240, 0, 0x0000, 0, 0), MX8MP_PAD_HDMI_DDC_SCL__I2C5_SCL = IOMUX_PAD(0x04A0, 0x0240, 3 | IOMUX_CONFIG_SION, 0x05C4, 3, 0), MX8MP_PAD_HDMI_DDC_SCL__CAN1_TX = IOMUX_PAD(0x04A0, 0x0240, 4, 0x0000, 0, 0), MX8MP_PAD_HDMI_DDC_SCL__GPIO3_IO26 = IOMUX_PAD(0x04A0, 0x0240, 5, 0x0000, 0, 0), - MX8MP_PAD_HDMI_DDC_SCL__AUDIOMIX_test_out00 = IOMUX_PAD(0x04A0, 0x0240, 6, 0x0000, 0, 0), - MX8MP_PAD_HDMI_DDC_SDA__HDMIMIX_EARC_SDA = IOMUX_PAD(0x04A4, 0x0244, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA = IOMUX_PAD(0x04A4, 0x0244, 0, 0x0000, 0, 0), MX8MP_PAD_HDMI_DDC_SDA__I2C5_SDA = IOMUX_PAD(0x04A4, 0x0244, 3 | IOMUX_CONFIG_SION, 0x05C8, 3, 0), MX8MP_PAD_HDMI_DDC_SDA__CAN1_RX = IOMUX_PAD(0x04A4, 0x0244, 4, 0x054C, 3, 0), MX8MP_PAD_HDMI_DDC_SDA__GPIO3_IO27 = IOMUX_PAD(0x04A4, 0x0244, 5, 0x0000, 0, 0), - MX8MP_PAD_HDMI_DDC_SDA__AUDIOMIX_test_out01 = IOMUX_PAD(0x04A4, 0x0244, 6, 0x0000, 0, 0), - MX8MP_PAD_HDMI_CEC__HDMIMIX_EARC_CEC = IOMUX_PAD(0x04A8, 0x0248, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_CEC__HDMIMIX_HDMI_CEC = IOMUX_PAD(0x04A8, 0x0248, 0, 0x0000, 0, 0), MX8MP_PAD_HDMI_CEC__I2C6_SCL = IOMUX_PAD(0x04A8, 0x0248, 3 | IOMUX_CONFIG_SION, 0x05CC, 3, 0), MX8MP_PAD_HDMI_CEC__CAN2_TX = IOMUX_PAD(0x04A8, 0x0248, 4, 0x0000, 0, 0), MX8MP_PAD_HDMI_CEC__GPIO3_IO28 = IOMUX_PAD(0x04A8, 0x0248, 5, 0x0000, 0, 0), - MX8MP_PAD_HDMI_HPD__HDMIMIX_EARC_DC_HPD = IOMUX_PAD(0x04AC, 0x024C, 0, 0x0000, 0, 0), - MX8MP_PAD_HDMI_HPD__AUDIOMIX_EARC_HDMI_HPD_O = IOMUX_PAD(0x04AC, 0x024C, 1, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__HDMIMIX_HDMI_HPD = IOMUX_PAD(0x04AC, 0x024C, 0, 0x0000, 0, 0), + MX8MP_PAD_HDMI_HPD__AUDIOMIX_HDMI_HPD_O = IOMUX_PAD(0x04AC, 0x024C, 1, 0x0000, 0, 0), MX8MP_PAD_HDMI_HPD__I2C6_SDA = IOMUX_PAD(0x04AC, 0x024C, 3 | IOMUX_CONFIG_SION, 0x05D0, 3, 0), MX8MP_PAD_HDMI_HPD__CAN2_RX = IOMUX_PAD(0x04AC, 0x024C, 4, 0x0550, 3, 0), MX8MP_PAD_HDMI_HPD__GPIO3_IO29 = IOMUX_PAD(0x04AC, 0x024C, 5, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h index d328542ece2..3e54f9b6764 100644 --- a/arch/arm/include/asm/arch-imx8m/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h @@ -11,6 +11,7 @@ void set_wdog_reset(struct wdog_regs *wdog); void enable_tzc380(void); void restore_boot_params(void); +int imx8m_usb_power(int usb_id, bool on); extern unsigned long rom_pointer[]; enum boot_device get_boot_device(void); bool is_usb_boot(void); diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 8ae49715789..8b81f93a120 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -77,11 +77,14 @@ void disable_ipu_clock(void); int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); int enable_lcdif_clock(u32 base_addr, bool enable); +int enable_lvds_bridge(u32 lcd_base_addr); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); +void enable_epdc_clock(void); void mxs_set_lcdclk(u32 base_addr, u32 freq); void select_ldb_di_clock_source(enum ldb_di_clock clk); void enable_eim_clk(unsigned char enable); +void mxs_set_vadcclk(void); int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 4174f244afa..3aab69c18da 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -264,11 +264,20 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 -/* LCDIF on i.MX6SX/UL */ +/* LCDIF on i.MX6SX/UL/SLL */ #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 +#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_OFFSET 23 + +/* For i.MX6SL */ +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 29) +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 29 +#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_MASK (0x7 << 26) +#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_OFFSET 26 +#define MXC_CCM_CBCMR_EPDC_PIX_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_EPDC_PIX_PODF_OFFSET 23 + #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) @@ -290,6 +299,14 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 + +/* For i.MX6SL */ +#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_OFFSET 8 +#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_OFFSET 4 + + /* Exists on i.MX6QP */ #define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) @@ -431,15 +448,15 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ - ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + ((is_mx6dqp() || is_mx6ul() || is_mx6ull()) ? \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) @@ -499,7 +516,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 -/* i.MX6ULL */ +/* i.MX6ULL/SLL */ #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET 15 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK (0x7 << 12) @@ -516,13 +533,20 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) -/* LCDIF1 on i.MX6SX/UL */ +/* LCDIF1 on i.MX6SX/UL/SLL */ #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 + +/* EPDC on i.MX6SL */ +#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_OFFSET 15 +#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_MASK (0x7 << 12) +#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_OFFSET 12 + /* LCDIF2 on i.MX6SX */ #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 @@ -567,6 +591,16 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET 16 #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET 14 +#define MXC_CCM_CSCDR3_CSI_CORE_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR3_CSI_CORE_PODF_OFFSET 11 +#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_MASK (0x3 << 9) +#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_OFFSET 9 + +/* For i.MX6SLL */ +#define MXC_CCM_CSCDR3_PXP_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_PXP_PODF_OFFSET 16 +#define MXC_CCM_CSCDR3_PXP_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCDR3_PXP_CLK_SEL_OFFSET 14 /* Define the bits in register CDHIPR */ #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) @@ -769,7 +803,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) -/* i.MX6SX/UL LCD and PXP */ +/* i.MX6SX/UL/SLL LCD and PXP */ #define MXC_CCM_CCGR2_LCD_OFFSET 28 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) #define MXC_CCM_CCGR2_PXP_OFFSET 30 @@ -798,10 +832,18 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) /* i.MX6SL */ -#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6 -#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET) -#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8 -#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET) +#define MXC_CCM_CCGR3_CSI_CORE_OFFSET 0 +#define MXC_CCM_CCGR3_CSI_CORE_MASK (3 << MXC_CCM_CCGR3_CSI_CORE_OFFSET) +#define MXC_CCM_CCGR3_PXP_AXI_OFFSET 2 +#define MXC_CCM_CCGR3_PXP_AXI_MASK (3 << MXC_CCM_CCGR3_PXP_AXI_OFFSET) +#define MXC_CCM_CCGR3_EPDC_AXI_OFFSET 4 +#define MXC_CCM_CCGR3_EPDC_AXI_MASK (3 << MXC_CCM_CCGR3_EPDC_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET 6 +#define MXC_CCM_CCGR3_LCDIF_AXI_MASK (3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET 8 +#define MXC_CCM_CCGR3_LCDIF_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET) +#define MXC_CCM_CCGR3_EPDC_PIX_OFFSET 10 +#define MXC_CCM_CCGR3_EPDC_PIX_MASK (3 << MXC_CCM_CCGR3_EPDC_PIX_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index a8a5bf7a575..1a1159908dc 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -23,7 +23,7 @@ #define GPU_ARB_END_ADDR 0x01803FFF #define APBH_DMA_ARB_BASE_ADDR 0x01804000 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF -#define M4_BOOTROM_BASE_ADDR 0x007F8000 +#define MCU_BOOTROM_BASE_ADDR 0x007F8000 #elif !defined(CONFIG_MX6SLL) #define CAAM_ARB_BASE_ADDR 0x00100000 @@ -122,7 +122,7 @@ #define MMDC1_ARB_END_ADDR 0xFFFFFFFF #endif -#ifndef CONFIG_MX6SX +#if (!(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL))) #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR #define IPU_SOC_OFFSET 0x00200000 #endif @@ -158,12 +158,21 @@ #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) #define UART8_BASE (ATZ1_BASE_ADDR + 0x24000) +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define SAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) +#define SAI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) +#define SAI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#else #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#endif #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#ifndef CONFIG_MX6SX +#if defined(CONFIG_MX6UL) +#define TOUCH_CTRL_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) +#define BEE_BASE_ADDR (ATZ1_BASE_ADDR + 0x44000) +#elif !defined(CONFIG_MX6SX) #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) #endif @@ -185,8 +194,13 @@ #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) #define MX6UL_SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define SNVS_LP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#define ENET2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#else #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#endif #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) @@ -211,6 +225,7 @@ #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #elif defined(CONFIG_MX6SX) #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) @@ -218,10 +233,19 @@ #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) + +#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define GPT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define PWM5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define PWM6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define PWM7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define PWM8_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) #else #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) #endif #define MX6SL_LCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) @@ -231,12 +255,14 @@ #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) #define AIPS3_ON_BASE_ADDR (ATZ3_BASE_ADDR + 0x7C000) #define AIPS3_OFF_BASE_ADDR (ATZ3_BASE_ADDR + 0x80000) + #if defined(CONFIG_MX6UL) #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) +#define ARM_BASE_ADDR (ATZ2_BASE_ADDR) #else #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) +#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) #endif -#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) #define CONFIG_SYS_FSL_SEC_OFFSET 0 #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ @@ -252,6 +278,8 @@ #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) #ifdef CONFIG_MX6SL #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) +#elif defined(CONFIG_MX6UL) +#define SIM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) #else #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) #endif @@ -260,6 +288,9 @@ #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) + +#define MX6UL_ADC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) +#define MX6UL_ADC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) @@ -279,12 +310,16 @@ #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) -#ifdef CONFIG_MX6SLL +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define CSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) +#define PXP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) +#elif defined(CONFIG_MX6SLL) #define IOMUXC_GPR_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IOMUXC_SNVS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) -#endif +#else #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#endif #define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define MX6ULL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #ifdef CONFIG_MX6SX @@ -294,9 +329,10 @@ #endif #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) #if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define SCTR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) +#define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #elif defined(CONFIG_MX6SX) #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) @@ -314,9 +350,20 @@ #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) +/* i.MX6SLL */ +#define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) +/* i.MX6SX/UL */ #define I2C4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) +/* i.MX6UL */ +#define MX6UL_UART6_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) + +#define OTG_BASE_ADDR USB_BASE_ADDR + +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR +#endif /* i.MX6SLL */ #define MTR_MASTER_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) @@ -331,19 +378,18 @@ #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) -#define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) -#define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) +#define MX6SX_ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) +#define MX6SX_ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000) #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000) #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000) #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000) #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000) -#define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000) #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000) #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) -#elif (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) +#elif defined(CONFIG_MX6ULL) #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000) #define DCP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000) #define RNGB_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000) @@ -359,6 +405,7 @@ #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) #define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) +#define MX6SX_UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000) #if !(defined(CONFIG_MX6SX) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ @@ -368,6 +415,7 @@ #define IRAM_SIZE 0x00020000 #endif #define FEC_QUIRK_ENET_MAC +#define SNVS_LPGPR 0x68 #include #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) @@ -385,6 +433,12 @@ MX6UL_LCDIF1_BASE_ADDR : \ ((is_mx6ull()) ? \ MX6ULL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR))) +#define UART6_BASE_ADDR ((is_mx6ul() || is_mx6ull()) ? \ + MX6UL_UART6_BASE_ADDR : MX6SX_UART6_BASE_ADDR) + +#define MXS_LCDIF_BASE LCDIF1_BASE_ADDR + +#define MXS_LCDIF_BASE LCDIF1_BASE_ADDR extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); @@ -585,7 +639,12 @@ struct iomuxc { #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) u8 reserved[0x4000]; #endif + +#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) + u32 gpr[15]; +#else u32 gpr[14]; +#endif }; struct gpc { @@ -668,10 +727,19 @@ struct gpc { #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0< +bool is_usb_boot(void); +#define is_boot_from_usb is_usb_boot +#define is_usbphy_power_on(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) +#define disconnect_from_pc(void) writel(0x0, OTG_BASE_ADDR + 0x140) #endif /* __ASSEMBLY__ */ #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h index dbc97b25df8..b42af53e42d 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h @@ -6,7 +6,7 @@ #define __ASM_ARCH_MX6_DDR_H__ #ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_MX6Q +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QP) #include "mx6q-ddr.h" #else #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) @@ -26,7 +26,7 @@ #endif /* CONFIG_MX6UL */ #endif /* CONFIG_MX6SX */ #endif /* CONFIG_MX6DL or CONFIG_MX6S */ -#endif /* CONFIG_MX6Q */ +#endif /* CONFIG_MX6Q or CONFIG_MX6QP */ #else enum { diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h index 9a99a6b7047..e8c0bec2463 100644 --- a/arch/arm/include/asm/arch-mx6/mx6-pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h @@ -20,7 +20,7 @@ enum { MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc), #include "mx6dl_pins.h" }; -#elif defined(CONFIG_MX6Q) +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6QP) enum { #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \ MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc), diff --git a/arch/arm/include/asm/arch-mx6/mx6_bee.h b/arch/arm/include/asm/arch-mx6/mx6_bee.h new file mode 100644 index 00000000000..eb51dfef75d --- /dev/null +++ b/arch/arm/include/asm/arch-mx6/mx6_bee.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#define GPR0 0x0 +#define GPR1 0x4 +#define GPR2 0x8 +#define GPR3 0xC +#define GPR4 0x10 +#define GPR5 0x14 +#define GPR6 0x18 +#define GPR7 0x1C +#define GPR8 0x20 +#define GPR9 0x24 +#define GPR10 0x28 +#define GPR11 0x2C + +#define GPR0_CTRL_CLK_EN_LOCK (1 << 31) +#define GPR0_CTRL_CLK_EN (1 << 15) +#define GPR0_CTRL_SFTRST_N_LOCK (1 << 30) +#define GPR0_CTRL_SFTRST (0 << 14) +#define GPR0_CTRL_SFTRST_N (1 << 14) +#define GPR0_CTRL_AES_MODE_LOCK (1 << 29) +#define GPR0_CTRL_AES_MODE_ECB (0 << 13) +#define GPR0_CTRL_AES_MODE_CTR (1 << 13) +#define GPR0_SEC_LEVEL_LOCK (3 << 24) +#define GPR0_SEC_LEVEL (3 << 8) +#define GPR0_AES_KEY_SEL_LOCK (1 << 20) +#define GPR0_AES_KEY_SEL_SNVS (0 << 4) +#define GPR0_AES_KEY_SEL_SOFT (1 << 4) +#define GPR0_BEE_ENABLE_LOCK (1 << 16) +#define GPR0_BEE_ENABLE (1 << 0) + +/* + * SECURITY LEVEL + * Non-Secure User | Non-Secure Spvr | Secure User | Secure Spvr + * Level + * (0)00 RD + WR RD + WR RD + WR RD + WR + * (1)01 None RD + WR RD + WR RD + WR + * (2)10 None None RD + WR RD + WR + * (3)11 None None None RD + WR + */ +#define GPR0_SEC_LEVEL_0 (0 << 8) +#define GPR0_SEC_LEVEL_1 (1 << 8) +#define GPR0_SEC_LEVEL_2 (2 << 8) +#define GPR0_SEC_LEVEL_3 (3 << 8) diff --git a/arch/arm/include/asm/arch-mx6/mx6_plugin.S b/arch/arm/include/asm/arch-mx6/mx6_plugin.S index 7e61d22ca79..f9b3cffbf5c 100644 --- a/arch/arm/include/asm/arch-mx6/mx6_plugin.S +++ b/arch/arm/include/asm/arch-mx6/mx6_plugin.S @@ -63,12 +63,12 @@ plugin_start: before_calling_rom___pu_irom_hwcnfg_setup: ldr r3, =ROM_VERSION_OFFSET ldr r4, [r3] -#if defined(CONFIG_MX6SOLO) || defined(CONFIG_MX6DL) +#if defined(CONFIG_MX6S) || defined(CONFIG_MX6DL) ldr r3, =ROM_VERSION_TO12 cmp r4, r3 ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DL_TO12 ldrlt r3, =ROM_API_TABLE_BASE_ADDR_LEGACY -#elif defined(CONFIG_MX6Q) +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6QP) ldr r3, =ROM_VERSION_TO15 cmp r4, r3 ldrge r3, =ROM_API_TABLE_BASE_ADDR_MX6DQ_TO15 diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h index c76a9202023..009fbe3a71f 100644 --- a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h +++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h @@ -5,7 +5,7 @@ #ifndef __ASM_ARCH_MX6Q_DDR_H__ #define __ASM_ARCH_MX6Q_DDR_H__ -#ifndef CONFIG_MX6Q +#if !defined(CONFIG_MX6Q) && !defined(CONFIG_MX6QP) #error "wrong CPU" #endif diff --git a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h index 01b14d73dc9..6e01ca82816 100644 --- a/arch/arm/include/asm/arch-mx6/mx6sl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6sl_pins.h @@ -59,14 +59,70 @@ enum { MX6_PAD_FEC_RX_ER__GPIO_4_19 = IOMUX_PAD(0x0428, 0x0138, 5, 0x0000, 0, 0), MX6_PAD_FEC_TX_CLK__GPIO_4_21 = IOMUX_PAD(0x0434, 0x0144, 5, 0x0000, 0, 0), - MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + MX6_PAD_KEY_COL0__KPP_COL_0 = IOMUX_PAD(0x0474, 0x016C, 0, 0x0734, 0, 0), + MX6_PAD_KEY_COL1__KPP_COL_1 = IOMUX_PAD(0x0478, 0x0170, 0, 0x0738, 0, 0), + MX6_PAD_KEY_COL2__KPP_COL_2 = IOMUX_PAD(0x047C, 0x0174, 0, 0x073C, 0, 0), + MX6_PAD_KEY_COL3__KPP_COL_3 = IOMUX_PAD(0x0480, 0x0178, 0, 0x0740, 0, 0), + MX6_PAD_KEY_ROW0__KPP_ROW_0 = IOMUX_PAD(0x0494, 0x018C, 0, 0x0754, 0, 0), + MX6_PAD_KEY_ROW1__KPP_ROW_1 = IOMUX_PAD(0x0498, 0x0190, 0, 0x0758, 0, 0), + MX6_PAD_KEY_ROW2__KPP_ROW_2 = IOMUX_PAD(0x049C, 0x0194, 0, 0x075C, 0, 0), + MX6_PAD_KEY_ROW3__KPP_ROW_3 = IOMUX_PAD(0x04A0, 0x0198, 0, 0x0760, 0, 0), MX6_PAD_KEY_COL4__USB_USBOTG1_PWR = IOMUX_PAD(0x0484, 0x017C, 6, 0x0000, 0, 0), MX6_PAD_KEY_COL5__USB_USBOTG2_PWR = IOMUX_PAD(0x0488, 0x0180, 6, 0x0000, 0, 0), + MX6_PAD_KEY_COL6__GPIO_4_4 = IOMUX_PAD(0x048C, 0x0184, 5, 0x0000, 0, 0), MX6_PAD_I2C1_SDA__I2C1_SDA = IOMUX_PAD(0x0450, 0x0160, 0x10, 0x0720, 2, 0), MX6_PAD_I2C1_SDA__GPIO_3_13 = IOMUX_PAD(0x0450, 0x0160, 5, 0x0000, 0, 0), MX6_PAD_I2C1_SCL__I2C1_SCL = IOMUX_PAD(0x044C, 0x015C, 0x10, 0x071C, 2, 0), MX6_PAD_I2C1_SCL__GPIO_3_12 = IOMUX_PAD(0x044C, 0x015C, 5, 0x0000, 0, 0), + + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID = IOMUX_PAD(0x03D0, 0x00E0, 4, 0x05DC, 0, 0), + MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 = IOMUX_PAD(0x03DC, 0x00EC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 = IOMUX_PAD(0x03E0, 0x00F0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 = IOMUX_PAD(0x03E8, 0x00F8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_VCOM0__GPIO_2_3 = IOMUX_PAD(0x0410, 0x0120, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 = IOMUX_PAD(0x03EC, 0x00FC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 = IOMUX_PAD(0x03D4, 0x00E4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__EPDC_SDDO_0 = IOMUX_PAD(0x0380, 0x0090, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__EPDC_SDDO_1 = IOMUX_PAD(0x0384, 0x0094, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__EPDC_SDDO_2 = IOMUX_PAD(0x03A0, 0x00B0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__EPDC_SDDO_3 = IOMUX_PAD(0x03A4, 0x00B4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__EPDC_SDDO_4 = IOMUX_PAD(0x03A8, 0x00B8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__EPDC_SDDO_5 = IOMUX_PAD(0x03AC, 0x00BC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__EPDC_SDDO_6 = IOMUX_PAD(0x03B0, 0x00C0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__EPDC_SDDO_7 = IOMUX_PAD(0x03B4, 0x00C4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK = IOMUX_PAD(0x03C0, 0x00D0, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__EPDC_GDSP = IOMUX_PAD(0x03CC, 0x00DC, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__EPDC_GDOE = IOMUX_PAD(0x03C4, 0x00D4, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__EPDC_GDRL = IOMUX_PAD(0x03C8, 0x00D8, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK = IOMUX_PAD(0x0400, 0x0110, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__EPDC_SDOE = IOMUX_PAD(0x0408, 0x0118, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__EPDC_SDLE = IOMUX_PAD(0x0404, 0x0114, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR = IOMUX_PAD(0x040C, 0x011C, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__EPDC_BDR_0 = IOMUX_PAD(0x0378, 0x0088, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 = IOMUX_PAD(0x03F0, 0x0100, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 = IOMUX_PAD(0x03F4, 0x0104, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 = IOMUX_PAD(0x03F8, 0x0108, 0, 0x0000, 0, 0), + MX6_PAD_EPDC_D0__GPIO_1_7 = IOMUX_PAD(0x0380, 0x0090, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D1__GPIO_1_8 = IOMUX_PAD(0x0384, 0x0094, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D2__GPIO_1_9 = IOMUX_PAD(0x03A0, 0x00B0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D3__GPIO_1_10 = IOMUX_PAD(0x03A4, 0x00B4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D4__GPIO_1_11 = IOMUX_PAD(0x03A8, 0x00B8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D5__GPIO_1_12 = IOMUX_PAD(0x03AC, 0x00BC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D6__GPIO_1_13 = IOMUX_PAD(0x03B0, 0x00C0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_D7__GPIO_1_14 = IOMUX_PAD(0x03B4, 0x00C4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDCLK__GPIO_1_31 = IOMUX_PAD(0x03C0, 0x00D0, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDSP__GPIO_2_2 = IOMUX_PAD(0x03CC, 0x00DC, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDOE__GPIO_2_0 = IOMUX_PAD(0x03C4, 0x00D4, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_GDRL__GPIO_2_1 = IOMUX_PAD(0x03C8, 0x00D8, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCLK__GPIO_1_23 = IOMUX_PAD(0x0400, 0x0110, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDOE__GPIO_1_25 = IOMUX_PAD(0x0408, 0x0118, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDLE__GPIO_1_24 = IOMUX_PAD(0x0404, 0x0114, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDSHR__GPIO_1_26 = IOMUX_PAD(0x040C, 0x011C, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_BDR0__GPIO_2_5 = IOMUX_PAD(0x0378, 0x0088, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE0__GPIO_1_27 = IOMUX_PAD(0x03F0, 0x0100, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE1__GPIO_1_28 = IOMUX_PAD(0x03F4, 0x0104, 5, 0x0000, 0, 0), + MX6_PAD_EPDC_SDCE2__GPIO_1_29 = IOMUX_PAD(0x03F8, 0x0108, 5, 0x0000, 0, 0), }; #endif /* __ASM_ARCH_MX6_MX6SL_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h index 031b4a0a880..fdd63b920b1 100644 --- a/arch/arm/include/asm/arch-mx6/mx6ul_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6ul_pins.h @@ -66,6 +66,7 @@ enum { MX6_PAD_JTAG_TCK__SAI2_RX_DATA = IOMUX_PAD(0x02E0, 0x0054, 2, 0x05F4, 0, 0), MX6_PAD_JTAG_TCK__PWM7_OUT = IOMUX_PAD(0x02E0, 0x0054, 4, 0x0000, 0, 0), MX6_PAD_JTAG_TCK__GPIO1_IO14 = IOMUX_PAD(0x02E0, 0x0054, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TCK__REF_CLK_32K = IOMUX_PAD(0x02E0, 0x0054, 6, 0x0000, 0, 0), MX6_PAD_JTAG_TCK__SIM2_POWER_FAIL = IOMUX_PAD(0x02E0, 0x0054, 8, 0x0000, 0, 0), MX6_PAD_JTAG_TRST_B__SJC_TRSTB = IOMUX_PAD(0x02E4, 0x0058, 0, 0x0000, 0, 0), @@ -73,6 +74,7 @@ enum { MX6_PAD_JTAG_TRST_B__SAI2_TX_DATA = IOMUX_PAD(0x02E4, 0x0058, 2, 0x0000, 0, 0), MX6_PAD_JTAG_TRST_B__PWM8_OUT = IOMUX_PAD(0x02E4, 0x0058, 4, 0x0000, 0, 0), MX6_PAD_JTAG_TRST_B__GPIO1_IO15 = IOMUX_PAD(0x02E4, 0x0058, 5, 0x0000, 0, 0), + MX6_PAD_JTAG_TRST_B__REF_CLK_24M = IOMUX_PAD(0x02E4, 0x0058, 6, 0x0000, 0, 0), MX6_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS = IOMUX_PAD(0x02E4, 0x0058, 8, 0x0000, 0, 0), MX6_PAD_GPIO1_IO00__I2C2_SCL = IOMUX_PAD(0x02E8, 0x005C, IOMUX_CONFIG_SION | 0, 0x05AC, 1, 0), @@ -109,6 +111,7 @@ enum { MX6_PAD_GPIO1_IO03__I2C1_SDA = IOMUX_PAD(0x02F4, 0x0068, IOMUX_CONFIG_SION | 0, 0x05A8, 1, 0), MX6_PAD_GPIO1_IO03__GPT1_COMPARE3 = IOMUX_PAD(0x02F4, 0x0068, 1, 0x0000, 0, 0), MX6_PAD_GPIO1_IO03__USB_OTG2_OC = IOMUX_PAD(0x02F4, 0x0068, 2, 0x0660, 0, 0), + MX6_PAD_GPIO1_IO03__REF_CLK_32K = IOMUX_PAD(0x02F4, 0x0068, 3, 0x0000, 0, 0), MX6_PAD_GPIO1_IO03__USDHC1_CD_B = IOMUX_PAD(0x02F4, 0x0068, 4, 0x0668, 0, 0), MX6_PAD_GPIO1_IO03__GPIO1_IO03 = IOMUX_PAD(0x02F4, 0x0068, 5, 0x0000, 0, 0), MX6_PAD_GPIO1_IO03__CCM_DI0_EXT_CLK = IOMUX_PAD(0x02F4, 0x0068, 6, 0x0000, 0, 0), @@ -119,6 +122,7 @@ enum { MX6_PAD_GPIO1_IO04__ENET1_REF_CLK1 = IOMUX_PAD(0x02F8, 0x006C, 0, 0x0574, 1, 0), MX6_PAD_GPIO1_IO04__PWM3_OUT = IOMUX_PAD(0x02F8, 0x006C, 1, 0x0000, 0, 0), MX6_PAD_GPIO1_IO04__USB_OTG1_PWR = IOMUX_PAD(0x02F8, 0x006C, 2, 0x0000, 0, 0), + MX6_PAD_GPIO1_IO04__REF_CLK_24M = IOMUX_PAD(0x02F8, 0x006C, 3, 0x0000, 0, 0), MX6_PAD_GPIO1_IO04__USDHC1_RESET_B = IOMUX_PAD(0x02F8, 0x006C, 4, 0x0000, 0, 0), MX6_PAD_GPIO1_IO04__GPIO1_IO04 = IOMUX_PAD(0x02F8, 0x006C, 5, 0x0000, 0, 0), MX6_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN = IOMUX_PAD(0x02F8, 0x006C, 6, 0x0000, 0, 0), @@ -365,6 +369,7 @@ enum { MX6_PAD_ENET1_RX_EN__ENET1_RX_EN = IOMUX_PAD(0x0358, 0x00CC, 0, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__UART5_DCE_RTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0640, 3, 0), MX6_PAD_ENET1_RX_EN__UART5_DTE_CTS = IOMUX_PAD(0x0358, 0x00CC, 1, 0x0000, 0, 0), + MX6_PAD_ENET1_RX_EN__REF_CLK_32K = IOMUX_PAD(0x0358, 0x00CC, 2, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__CSI_DATA18 = IOMUX_PAD(0x0358, 0x00CC, 3, 0x050C, 0, 0), MX6_PAD_ENET1_RX_EN__FLEXCAN2_TX = IOMUX_PAD(0x0358, 0x00CC, 4, 0x0000, 0, 0), MX6_PAD_ENET1_RX_EN__GPIO2_IO02 = IOMUX_PAD(0x0358, 0x00CC, 5, 0x0000, 0, 0), @@ -374,6 +379,7 @@ enum { MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 = IOMUX_PAD(0x035C, 0x00D0, 0, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__UART5_DCE_CTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__UART5_DTE_RTS = IOMUX_PAD(0x035C, 0x00D0, 1, 0x0640, 4, 0), + MX6_PAD_ENET1_TX_DATA0__REF_CLK_24M = IOMUX_PAD(0x035C, 0x00D0, 2, 0x0000, 0, 0), MX6_PAD_ENET1_TX_DATA0__CSI_DATA19 = IOMUX_PAD(0x035C, 0x00D0, 3, 0x0510, 0, 0), MX6_PAD_ENET1_TX_DATA0__FLEXCAN2_RX = IOMUX_PAD(0x035C, 0x00D0, 4, 0x0588, 1, 0), MX6_PAD_ENET1_TX_DATA0__GPIO2_IO03 = IOMUX_PAD(0x035C, 0x00D0, 5, 0x0000, 0, 0), @@ -458,6 +464,7 @@ enum { MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__REF_CLK_24M = IOMUX_PAD(0x037C, 0x00F0, 8, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), @@ -545,6 +552,7 @@ enum { MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA00__CA7_MX6UL_TRACE0 = IOMUX_PAD(0x03A4, 0x0118, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN = IOMUX_PAD(0x03A4, 0x0118, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__I2C3_SDA = IOMUX_PAD(0x03A4, 0x0118, IOMUX_CONFIG_SION | 4, 0x05B8, 2, 0), MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), @@ -553,6 +561,7 @@ enum { MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA01__CA7_MX6UL_TRACE1 = IOMUX_PAD(0x03A8, 0x011C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT = IOMUX_PAD(0x03A8, 0x011C, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__I2C3_SCL = IOMUX_PAD(0x03A8, 0x011C, IOMUX_CONFIG_SION | 4, 0x05B4, 2, 0), MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), @@ -561,6 +570,7 @@ enum { MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA02__CA7_MX6UL_TRACE2 = IOMUX_PAD(0x03AC, 0x0120, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN = IOMUX_PAD(0x03AC, 0x0120, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__I2C4_SDA = IOMUX_PAD(0x03AC, 0x0120, IOMUX_CONFIG_SION | 4, 0x05C0, 2, 0), MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), @@ -569,6 +579,7 @@ enum { MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA03__CA7_MX6UL_TRACE3 = IOMUX_PAD(0x03B0, 0x0124, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT = IOMUX_PAD(0x03B0, 0x0124, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__I2C4_SCL = IOMUX_PAD(0x03B0, 0x0124, IOMUX_CONFIG_SION | 4, 0x05BC, 2, 0), MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), @@ -578,6 +589,7 @@ enum { MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__UART8_DTE_RTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0658, 2, 0), + MX6_PAD_LCD_DATA04__CA7_MX6UL_TRACE4 = IOMUX_PAD(0x03B4, 0x0128, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN = IOMUX_PAD(0x03B4, 0x0128, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__SPDIF_SR_CLK = IOMUX_PAD(0x03B4, 0x0128, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), @@ -587,6 +599,7 @@ enum { MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), MX6_PAD_LCD_DATA05__UART8_DTE_CTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__CA7_MX6UL_TRACE5 = IOMUX_PAD(0x03B8, 0x012C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT = IOMUX_PAD(0x03B8, 0x012C, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__SPDIF_OUT = IOMUX_PAD(0x03B8, 0x012C, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), @@ -596,6 +609,7 @@ enum { MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__UART7_DTE_RTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0650, 2, 0), + MX6_PAD_LCD_DATA06__CA7_MX6UL_TRACE6 = IOMUX_PAD(0x03BC, 0x0130, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN = IOMUX_PAD(0x03BC, 0x0130, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__SPDIF_LOCK = IOMUX_PAD(0x03BC, 0x0130, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), @@ -605,6 +619,7 @@ enum { MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), MX6_PAD_LCD_DATA07__UART7_DTE_CTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__CA7_MX6UL_TRACE7 = IOMUX_PAD(0x03C0, 0x0134, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT = IOMUX_PAD(0x03C0, 0x0134, 3, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__SPDIF_EXT_CLK = IOMUX_PAD(0x03C0, 0x0134, 4, 0x061C, 0, 0), MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), @@ -613,6 +628,7 @@ enum { MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), + MX6_PAD_LCD_DATA08__CA7_MX6UL_TRACE8 = IOMUX_PAD(0x03C4, 0x0138, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__CSI_DATA16 = IOMUX_PAD(0x03C4, 0x0138, 3, 0x0504, 1, 0), MX6_PAD_LCD_DATA08__EIM_DATA00 = IOMUX_PAD(0x03C4, 0x0138, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__GPIO3_IO13 = IOMUX_PAD(0x03C4, 0x0138, 5, 0x0000, 0, 0), @@ -621,6 +637,7 @@ enum { MX6_PAD_LCD_DATA09__LCDIF_DATA09 = IOMUX_PAD(0x03C8, 0x013C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA09__SAI3_MCLK = IOMUX_PAD(0x03C8, 0x013C, 1, 0x0600, 1, 0), + MX6_PAD_LCD_DATA09__CA7_MX6UL_TRACE9 = IOMUX_PAD(0x03C8, 0x013C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA09__CSI_DATA17 = IOMUX_PAD(0x03C8, 0x013C, 3, 0x0508, 1, 0), MX6_PAD_LCD_DATA09__EIM_DATA01 = IOMUX_PAD(0x03C8, 0x013C, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA09__GPIO3_IO14 = IOMUX_PAD(0x03C8, 0x013C, 5, 0x0000, 0, 0), @@ -629,6 +646,7 @@ enum { MX6_PAD_LCD_DATA10__LCDIF_DATA10 = IOMUX_PAD(0x03CC, 0x0140, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA10__SAI3_RX_SYNC = IOMUX_PAD(0x03CC, 0x0140, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA10__CA7_MX6UL_TRACE10 = IOMUX_PAD(0x03CC, 0x0140, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA10__CSI_DATA18 = IOMUX_PAD(0x03CC, 0x0140, 3, 0x050C, 1, 0), MX6_PAD_LCD_DATA10__EIM_DATA02 = IOMUX_PAD(0x03CC, 0x0140, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA10__GPIO3_IO15 = IOMUX_PAD(0x03CC, 0x0140, 5, 0x0000, 0, 0), @@ -637,6 +655,7 @@ enum { MX6_PAD_LCD_DATA11__LCDIF_DATA11 = IOMUX_PAD(0x03D0, 0x0144, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA11__SAI3_RX_BCLK = IOMUX_PAD(0x03D0, 0x0144, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA11__CA7_MX6UL_TRACE11 = IOMUX_PAD(0x03D0, 0x0144, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA11__CSI_DATA19 = IOMUX_PAD(0x03D0, 0x0144, 3, 0x0510, 1, 0), MX6_PAD_LCD_DATA11__EIM_DATA03 = IOMUX_PAD(0x03D0, 0x0144, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA11__GPIO3_IO16 = IOMUX_PAD(0x03D0, 0x0144, 5, 0x0000, 0, 0), @@ -645,6 +664,7 @@ enum { MX6_PAD_LCD_DATA12__LCDIF_DATA12 = IOMUX_PAD(0x03D4, 0x0148, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA12__SAI3_TX_SYNC = IOMUX_PAD(0x03D4, 0x0148, 1, 0x060C, 1, 0), + MX6_PAD_LCD_DATA12__CA7_MX6UL_TRACE12 = IOMUX_PAD(0x03D4, 0x0148, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA12__CSI_DATA20 = IOMUX_PAD(0x03D4, 0x0148, 3, 0x0514, 1, 0), MX6_PAD_LCD_DATA12__EIM_DATA04 = IOMUX_PAD(0x03D4, 0x0148, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA12__GPIO3_IO17 = IOMUX_PAD(0x03D4, 0x0148, 5, 0x0000, 0, 0), @@ -653,6 +673,7 @@ enum { MX6_PAD_LCD_DATA13__LCDIF_DATA13 = IOMUX_PAD(0x03D8, 0x014C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA13__SAI3_TX_BCLK = IOMUX_PAD(0x03D8, 0x014C, 1, 0x0608, 1, 0), + MX6_PAD_LCD_DATA13__CA7_MX6UL_TRACE13 = IOMUX_PAD(0x03D8, 0x014C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA13__CSI_DATA21 = IOMUX_PAD(0x03D8, 0x014C, 3, 0x0518, 1, 0), MX6_PAD_LCD_DATA13__EIM_DATA05 = IOMUX_PAD(0x03D8, 0x014C, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA13__GPIO3_IO18 = IOMUX_PAD(0x03D8, 0x014C, 5, 0x0000, 0, 0), @@ -661,6 +682,7 @@ enum { MX6_PAD_LCD_DATA14__LCDIF_DATA14 = IOMUX_PAD(0x03DC, 0x0150, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__SAI3_RX_DATA = IOMUX_PAD(0x03DC, 0x0150, 1, 0x0604, 1, 0), + MX6_PAD_LCD_DATA14__CA7_MX6UL_TRACE14 = IOMUX_PAD(0x03DC, 0x0150, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__CSI_DATA22 = IOMUX_PAD(0x03DC, 0x0150, 3, 0x051C, 1, 0), MX6_PAD_LCD_DATA14__EIM_DATA06 = IOMUX_PAD(0x03DC, 0x0150, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), @@ -669,6 +691,7 @@ enum { MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA15__CA7_MX6UL_TRACE15 = IOMUX_PAD(0x03E0, 0x0154, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__CSI_DATA23 = IOMUX_PAD(0x03E0, 0x0154, 3, 0x0520, 1, 0), MX6_PAD_LCD_DATA15__EIM_DATA07 = IOMUX_PAD(0x03E0, 0x0154, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), @@ -678,6 +701,7 @@ enum { MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__UART7_DTE_RX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0654, 2, 0), + MX6_PAD_LCD_DATA16__CA7_MX6UL_TRACE_CLK = IOMUX_PAD(0x03E4, 0x0158, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__CSI_DATA01 = IOMUX_PAD(0x03E4, 0x0158, 3, 0x04D4, 1, 0), MX6_PAD_LCD_DATA16__EIM_DATA08 = IOMUX_PAD(0x03E4, 0x0158, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), @@ -687,6 +711,7 @@ enum { MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), MX6_PAD_LCD_DATA17__UART7_DTE_TX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0000, 0, 0), + MX6_PAD_LCD_DATA17__CA7_MX6UL_TRACE_CTL = IOMUX_PAD(0x03E8, 0x015C, 2, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__CSI_DATA00 = IOMUX_PAD(0x03E8, 0x015C, 3, 0x04D0, 1, 0), MX6_PAD_LCD_DATA17__EIM_DATA09 = IOMUX_PAD(0x03E8, 0x015C, 4, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h index de4a1abc274..219c87eaa6c 100644 --- a/arch/arm/include/asm/arch-mx6/mx6ull_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6ull_pins.h @@ -429,6 +429,7 @@ enum { MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08 = IOMUX_PAD(0x0370, 0x00E4, 5, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA0__KPP_ROW04 = IOMUX_PAD(0x0370, 0x00E4, 6, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA0__USB_OTG1_PWR = IOMUX_PAD(0x0370, 0x00E4, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08 = IOMUX_PAD(0x0370, 0x00E4, 9, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 = IOMUX_PAD(0x0374, 0x00E8, 0, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA1__UART6_DCE_RX = IOMUX_PAD(0x0374, 0x00E8, 1, 0x064C, 2, 0), @@ -439,6 +440,7 @@ enum { MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09 = IOMUX_PAD(0x0374, 0x00E8, 5, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA1__KPP_COL04 = IOMUX_PAD(0x0374, 0x00E8, 6, 0x0000, 0, 0), MX6_PAD_ENET2_RX_DATA1__USB_OTG1_OC = IOMUX_PAD(0x0374, 0x00E8, 8, 0x0664, 1, 0), + MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09 = IOMUX_PAD(0x0374, 0x00E8, 9, 0x0000, 0, 0), MX6_PAD_ENET2_RX_EN__ENET2_RX_EN = IOMUX_PAD(0x0378, 0x00EC, 0, 0x0000, 0, 0), MX6_PAD_ENET2_RX_EN__UART7_DCE_TX = IOMUX_PAD(0x0378, 0x00EC, 1, 0x0000, 0, 0), @@ -449,6 +451,7 @@ enum { MX6_PAD_ENET2_RX_EN__GPIO2_IO10 = IOMUX_PAD(0x0378, 0x00EC, 5, 0x0000, 0, 0), MX6_PAD_ENET2_RX_EN__KPP_ROW05 = IOMUX_PAD(0x0378, 0x00EC, 6, 0x0000, 0, 0), MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M = IOMUX_PAD(0x0378, 0x00EC, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_EN__EPDC_SDDO10 = IOMUX_PAD(0x0378, 0x00EC, 9, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 = IOMUX_PAD(0x037C, 0x00F0, 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__UART7_DCE_RX = IOMUX_PAD(0x037C, 0x00F0, 1, 0x0654, 1, 0), @@ -458,6 +461,7 @@ enum { MX6_PAD_ENET2_TX_DATA0__EIM_EB_B02 = IOMUX_PAD(0x037C, 0x00F0, 4, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11 = IOMUX_PAD(0x037C, 0x00F0, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA0__KPP_COL05 = IOMUX_PAD(0x037C, 0x00F0, 6, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11 = IOMUX_PAD(0x037C, 0x00F0, 9, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 = IOMUX_PAD(0x0380, 0x00F4, 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__UART8_DCE_TX = IOMUX_PAD(0x0380, 0x00F4, 1, 0x0000, 0, 0), @@ -468,6 +472,7 @@ enum { MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12 = IOMUX_PAD(0x0380, 0x00F4, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__KPP_ROW06 = IOMUX_PAD(0x0380, 0x00F4, 6, 0x0000, 0, 0), MX6_PAD_ENET2_TX_DATA1__USB_OTG2_PWR = IOMUX_PAD(0x0380, 0x00F4, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12 = IOMUX_PAD(0x0380, 0x00F4, 9, 0x0000, 0, 0), MX6_PAD_ENET2_TX_EN__ENET2_TX_EN = IOMUX_PAD(0x0384, 0x00F8, 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_EN__UART8_DCE_RX = IOMUX_PAD(0x0384, 0x00F8, 1, 0x065C, 1, 0), @@ -478,6 +483,7 @@ enum { MX6_PAD_ENET2_TX_EN__GPIO2_IO13 = IOMUX_PAD(0x0384, 0x00F8, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_EN__KPP_COL06 = IOMUX_PAD(0x0384, 0x00F8, 6, 0x0000, 0, 0), MX6_PAD_ENET2_TX_EN__USB_OTG2_OC = IOMUX_PAD(0x0384, 0x00F8, 8, 0x0660, 1, 0), + MX6_PAD_ENET2_TX_EN__EPDC_SDDO13 = IOMUX_PAD(0x0384, 0x00F8, 9, 0x0000, 0, 0), MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK = IOMUX_PAD(0x0388, 0x00FC, IOMUX_CONFIG_SION | 0, 0x0000, 0, 0), MX6_PAD_ENET2_TX_CLK__UART8_DCE_CTS = IOMUX_PAD(0x0388, 0x00FC, 1, 0x0000, 0, 0), @@ -488,6 +494,7 @@ enum { MX6_PAD_ENET2_TX_CLK__GPIO2_IO14 = IOMUX_PAD(0x0388, 0x00FC, 5, 0x0000, 0, 0), MX6_PAD_ENET2_TX_CLK__KPP_ROW07 = IOMUX_PAD(0x0388, 0x00FC, 6, 0x0000, 0, 0), MX6_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID = IOMUX_PAD(0x0388, 0x00FC, 8, 0x04BC, 1, 0), + MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14 = IOMUX_PAD(0x0388, 0x00FC, 9, 0x0000, 0, 0), MX6_PAD_ENET2_RX_ER__ENET2_RX_ER = IOMUX_PAD(0x038C, 0x0100, 0, 0x0000, 0, 0), MX6_PAD_ENET2_RX_ER__UART8_DCE_RTS = IOMUX_PAD(0x038C, 0x0100, 1, 0x0658, 1, 0), @@ -498,6 +505,7 @@ enum { MX6_PAD_ENET2_RX_ER__GPIO2_IO15 = IOMUX_PAD(0x038C, 0x0100, 5, 0x0000, 0, 0), MX6_PAD_ENET2_RX_ER__KPP_COL07 = IOMUX_PAD(0x038C, 0x0100, 6, 0x0000, 0, 0), MX6_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY = IOMUX_PAD(0x038C, 0x0100, 8, 0x0000, 0, 0), + MX6_PAD_ENET2_RX_ER__EPDC_SDDO15 = IOMUX_PAD(0x038C, 0x0100, 9, 0x0000, 0, 0), MX6_PAD_LCD_CLK__LCDIF_CLK = IOMUX_PAD(0x0390, 0x0104, 0, 0x0000, 0, 0), MX6_PAD_LCD_CLK__LCDIF_WR_RWN = IOMUX_PAD(0x0390, 0x0104, 1, 0x0000, 0, 0), @@ -507,6 +515,7 @@ enum { MX6_PAD_LCD_CLK__EIM_CS2_B = IOMUX_PAD(0x0390, 0x0104, 4, 0x0000, 0, 0), MX6_PAD_LCD_CLK__GPIO3_IO00 = IOMUX_PAD(0x0390, 0x0104, 5, 0x0000, 0, 0), MX6_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB = IOMUX_PAD(0x0390, 0x0104, 8, 0x0000, 0, 0), + MX6_PAD_LCD_CLK__EPDC_SDCLK = IOMUX_PAD(0x0390, 0x0104, 9, 0x0000, 0, 0), MX6_PAD_LCD_ENABLE__LCDIF_ENABLE = IOMUX_PAD(0x0394, 0x0108, 0, 0x0000, 0, 0), MX6_PAD_LCD_ENABLE__LCDIF_RD_E = IOMUX_PAD(0x0394, 0x0108, 1, 0x0000, 0, 0), @@ -516,6 +525,7 @@ enum { MX6_PAD_LCD_ENABLE__EIM_CS3_B = IOMUX_PAD(0x0394, 0x0108, 4, 0x0000, 0, 0), MX6_PAD_LCD_ENABLE__GPIO3_IO01 = IOMUX_PAD(0x0394, 0x0108, 5, 0x0000, 0, 0), MX6_PAD_LCD_ENABLE__ECSPI2_RDY = IOMUX_PAD(0x0394, 0x0108, 8, 0x0000, 0, 0), + MX6_PAD_LCD_ENABLE__EPDC_SDLE = IOMUX_PAD(0x0394, 0x0108, 9, 0x0000, 0, 0), MX6_PAD_LCD_HSYNC__LCDIF_HSYNC = IOMUX_PAD(0x0398, 0x010C, 0, 0x05DC, 0, 0), MX6_PAD_LCD_HSYNC__LCDIF_RS = IOMUX_PAD(0x0398, 0x010C, 1, 0x0000, 0, 0), @@ -525,6 +535,7 @@ enum { MX6_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB = IOMUX_PAD(0x0398, 0x010C, 4, 0x0000, 0, 0), MX6_PAD_LCD_HSYNC__GPIO3_IO02 = IOMUX_PAD(0x0398, 0x010C, 5, 0x0000, 0, 0), MX6_PAD_LCD_HSYNC__ECSPI2_SS1 = IOMUX_PAD(0x0398, 0x010C, 8, 0x0000, 0, 0), + MX6_PAD_LCD_HSYNC__EPDC_SDOE = IOMUX_PAD(0x0398, 0x010C, 9, 0x0000, 0, 0), MX6_PAD_LCD_VSYNC__LCDIF_VSYNC = IOMUX_PAD(0x039C, 0x0110, 0, 0x0000, 0, 0), MX6_PAD_LCD_VSYNC__LCDIF_BUSY = IOMUX_PAD(0x039C, 0x0110, 1, 0x05DC, 1, 0), @@ -534,6 +545,7 @@ enum { MX6_PAD_LCD_VSYNC__WDOG2_WDOG_B = IOMUX_PAD(0x039C, 0x0110, 4, 0x0000, 0, 0), MX6_PAD_LCD_VSYNC__GPIO3_IO03 = IOMUX_PAD(0x039C, 0x0110, 5, 0x0000, 0, 0), MX6_PAD_LCD_VSYNC__ECSPI2_SS2 = IOMUX_PAD(0x039C, 0x0110, 8, 0x0000, 0, 0), + MX6_PAD_LCD_VSYNC__EPDC_SDCE0 = IOMUX_PAD(0x039C, 0x0110, 9, 0x0000, 0, 0), MX6_PAD_LCD_RESET__LCDIF_RESET = IOMUX_PAD(0x03A0, 0x0114, 0, 0x0000, 0, 0), MX6_PAD_LCD_RESET__LCDIF_CS = IOMUX_PAD(0x03A0, 0x0114, 1, 0x0000, 0, 0), @@ -542,6 +554,7 @@ enum { MX6_PAD_LCD_RESET__WDOG1_WDOG_ANY = IOMUX_PAD(0x03A0, 0x0114, 4, 0x0000, 0, 0), MX6_PAD_LCD_RESET__GPIO3_IO04 = IOMUX_PAD(0x03A0, 0x0114, 5, 0x0000, 0, 0), MX6_PAD_LCD_RESET__ECSPI2_SS3 = IOMUX_PAD(0x03A0, 0x0114, 8, 0x0000, 0, 0), + MX6_PAD_LCD_RESET__EPDC_GDOE = IOMUX_PAD(0x03A0, 0x0114, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__LCDIF_DATA00 = IOMUX_PAD(0x03A4, 0x0118, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__PWM1_OUT = IOMUX_PAD(0x03A4, 0x0118, 1, 0x0000, 0, 0), @@ -550,6 +563,7 @@ enum { MX6_PAD_LCD_DATA00__GPIO3_IO05 = IOMUX_PAD(0x03A4, 0x0118, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__SRC_BT_CFG00 = IOMUX_PAD(0x03A4, 0x0118, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA00__SAI1_MCLK = IOMUX_PAD(0x03A4, 0x0118, 8, 0x05E0, 1, 0), + MX6_PAD_LCD_DATA00__EPDC_SDDO00 = IOMUX_PAD(0x03A4, 0x0118, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__LCDIF_DATA01 = IOMUX_PAD(0x03A8, 0x011C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__PWM2_OUT = IOMUX_PAD(0x03A8, 0x011C, 1, 0x0000, 0, 0), @@ -558,6 +572,7 @@ enum { MX6_PAD_LCD_DATA01__GPIO3_IO06 = IOMUX_PAD(0x03A8, 0x011C, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__SRC_BT_CFG01 = IOMUX_PAD(0x03A8, 0x011C, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA01__SAI1_TX_SYNC = IOMUX_PAD(0x03A8, 0x011C, 8, 0x05EC, 0, 0), + MX6_PAD_LCD_DATA01__EPDC_SDDO01 = IOMUX_PAD(0x03A8, 0x011C, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__LCDIF_DATA02 = IOMUX_PAD(0x03AC, 0x0120, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__PWM3_OUT = IOMUX_PAD(0x03AC, 0x0120, 1, 0x0000, 0, 0), @@ -566,6 +581,7 @@ enum { MX6_PAD_LCD_DATA02__GPIO3_IO07 = IOMUX_PAD(0x03AC, 0x0120, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__SRC_BT_CFG02 = IOMUX_PAD(0x03AC, 0x0120, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA02__SAI1_TX_BCLK = IOMUX_PAD(0x03AC, 0x0120, 8, 0x05E8, 0, 0), + MX6_PAD_LCD_DATA02__EPDC_SDDO02 = IOMUX_PAD(0x03AC, 0x0120, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__LCDIF_DATA03 = IOMUX_PAD(0x03B0, 0x0124, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__PWM4_OUT = IOMUX_PAD(0x03B0, 0x0124, 1, 0x0000, 0, 0), @@ -574,6 +590,7 @@ enum { MX6_PAD_LCD_DATA03__GPIO3_IO08 = IOMUX_PAD(0x03B0, 0x0124, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__SRC_BT_CFG03 = IOMUX_PAD(0x03B0, 0x0124, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA03__SAI1_RX_DATA = IOMUX_PAD(0x03B0, 0x0124, 8, 0x05E4, 0, 0), + MX6_PAD_LCD_DATA03__EPDC_SDDO03 = IOMUX_PAD(0x03B0, 0x0124, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__LCDIF_DATA04 = IOMUX_PAD(0x03B4, 0x0128, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__UART8_DCE_CTS = IOMUX_PAD(0x03B4, 0x0128, 1, 0x0000, 0, 0), @@ -583,6 +600,7 @@ enum { MX6_PAD_LCD_DATA04__GPIO3_IO09 = IOMUX_PAD(0x03B4, 0x0128, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__SRC_BT_CFG04 = IOMUX_PAD(0x03B4, 0x0128, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA04__SAI1_TX_DATA = IOMUX_PAD(0x03B4, 0x0128, 8, 0x0000, 0, 0), + MX6_PAD_LCD_DATA04__EPDC_SDDO04 = IOMUX_PAD(0x03B4, 0x0128, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__LCDIF_DATA05 = IOMUX_PAD(0x03B8, 0x012C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__UART8_DCE_RTS = IOMUX_PAD(0x03B8, 0x012C, 1, 0x0658, 3, 0), @@ -592,6 +610,7 @@ enum { MX6_PAD_LCD_DATA05__GPIO3_IO10 = IOMUX_PAD(0x03B8, 0x012C, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__SRC_BT_CFG05 = IOMUX_PAD(0x03B8, 0x012C, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA05__ECSPI1_SS1 = IOMUX_PAD(0x03B8, 0x012C, 8, 0x0000, 0, 0), + MX6_PAD_LCD_DATA05__EPDC_SDDO05 = IOMUX_PAD(0x03B8, 0x012C, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__LCDIF_DATA06 = IOMUX_PAD(0x03BC, 0x0130, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__UART7_DCE_CTS = IOMUX_PAD(0x03BC, 0x0130, 1, 0x0000, 0, 0), @@ -601,6 +620,7 @@ enum { MX6_PAD_LCD_DATA06__GPIO3_IO11 = IOMUX_PAD(0x03BC, 0x0130, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__SRC_BT_CFG06 = IOMUX_PAD(0x03BC, 0x0130, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA06__ECSPI1_SS2 = IOMUX_PAD(0x03BC, 0x0130, 8, 0x0000, 0, 0), + MX6_PAD_LCD_DATA06__EPDC_SDDO06 = IOMUX_PAD(0x03BC, 0x0130, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__LCDIF_DATA07 = IOMUX_PAD(0x03C0, 0x0134, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__UART7_DCE_RTS = IOMUX_PAD(0x03C0, 0x0134, 1, 0x0650, 3, 0), @@ -610,6 +630,7 @@ enum { MX6_PAD_LCD_DATA07__GPIO3_IO12 = IOMUX_PAD(0x03C0, 0x0134, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__SRC_BT_CFG07 = IOMUX_PAD(0x03C0, 0x0134, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA07__ECSPI1_SS3 = IOMUX_PAD(0x03C0, 0x0134, 8, 0x0000, 0, 0), + MX6_PAD_LCD_DATA07__EPDC_SDDO07 = IOMUX_PAD(0x03C0, 0x0134, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__LCDIF_DATA08 = IOMUX_PAD(0x03C4, 0x0138, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA08__SPDIF_IN = IOMUX_PAD(0x03C4, 0x0138, 1, 0x0618, 2, 0), @@ -666,6 +687,7 @@ enum { MX6_PAD_LCD_DATA14__GPIO3_IO19 = IOMUX_PAD(0x03DC, 0x0150, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__SRC_BT_CFG14 = IOMUX_PAD(0x03DC, 0x0150, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA14__USDHC2_DATA4 = IOMUX_PAD(0x03DC, 0x0150, 8, 0x068C, 0, 0), + MX6_PAD_LCD_DATA14__EPDC_SDSHR = IOMUX_PAD(0x03DC, 0x0150, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__LCDIF_DATA15 = IOMUX_PAD(0x03E0, 0x0154, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__SAI3_TX_DATA = IOMUX_PAD(0x03E0, 0x0154, 1, 0x0000, 0, 0), @@ -674,6 +696,7 @@ enum { MX6_PAD_LCD_DATA15__GPIO3_IO20 = IOMUX_PAD(0x03E0, 0x0154, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__SRC_BT_CFG15 = IOMUX_PAD(0x03E0, 0x0154, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA15__USDHC2_DATA5 = IOMUX_PAD(0x03E0, 0x0154, 8, 0x0690, 0, 0), + MX6_PAD_LCD_DATA15__EPDC_GDRL = IOMUX_PAD(0x03E0, 0x0154, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__LCDIF_DATA16 = IOMUX_PAD(0x03E4, 0x0158, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__UART7_DCE_TX = IOMUX_PAD(0x03E4, 0x0158, 1, 0x0000, 0, 0), @@ -683,6 +706,7 @@ enum { MX6_PAD_LCD_DATA16__GPIO3_IO21 = IOMUX_PAD(0x03E4, 0x0158, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__SRC_BT_CFG24 = IOMUX_PAD(0x03E4, 0x0158, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA16__USDHC2_DATA6 = IOMUX_PAD(0x03E4, 0x0158, 8, 0x0694, 0, 0), + MX6_PAD_LCD_DATA16__EPDC_GDCLK = IOMUX_PAD(0x03E4, 0x0158, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__LCDIF_DATA17 = IOMUX_PAD(0x03E8, 0x015C, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__UART7_DCE_RX = IOMUX_PAD(0x03E8, 0x015C, 1, 0x0654, 3, 0), @@ -692,6 +716,7 @@ enum { MX6_PAD_LCD_DATA17__GPIO3_IO22 = IOMUX_PAD(0x03E8, 0x015C, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__SRC_BT_CFG25 = IOMUX_PAD(0x03E8, 0x015C, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA17__USDHC2_DATA7 = IOMUX_PAD(0x03E8, 0x015C, 8, 0x0698, 0, 0), + MX6_PAD_LCD_DATA17__EPDC_GDSP = IOMUX_PAD(0x03E8, 0x015C, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA18__LCDIF_DATA18 = IOMUX_PAD(0x03EC, 0x0160, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA18__PWM5_OUT = IOMUX_PAD(0x03EC, 0x0160, 1, 0x0000, 0, 0), @@ -730,6 +755,7 @@ enum { MX6_PAD_LCD_DATA21__GPIO3_IO26 = IOMUX_PAD(0x03F8, 0x016C, 5, 0x0000, 0, 0), MX6_PAD_LCD_DATA21__SRC_BT_CFG29 = IOMUX_PAD(0x03F8, 0x016C, 6, 0x0000, 0, 0), MX6_PAD_LCD_DATA21__USDHC2_DATA1 = IOMUX_PAD(0x03F8, 0x016C, 8, 0x0680, 1, 0), + MX6_PAD_LCD_DATA21__EPDC_SDCE1 = IOMUX_PAD(0x03F8, 0x016C, 9, 0x0000, 0, 0), MX6_PAD_LCD_DATA22__LCDIF_DATA22 = IOMUX_PAD(0x03FC, 0x0170, 0, 0x0000, 0, 0), MX6_PAD_LCD_DATA22__MQS_RIGHT = IOMUX_PAD(0x03FC, 0x0170, 1, 0x0000, 0, 0), diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 1e5fa1a75eb..75ba38716cd 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -38,4 +38,16 @@ static inline void iomuxc_set_rgmii_io_voltage(int io_vol) __raw_writel(io_vol, IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII); } +void set_wdog_reset(struct wdog_regs *wdog); +enum boot_device get_boot_device(void); + +#ifdef CONFIG_LDO_BYPASS_CHECK +int check_ldo_bypass(void); +int check_1_2G(void); +int set_anatop_bypass(int wdog_reset_pin); +void ldo_mode_set(int ldo_bypass); +void prep_anatop_bypass(void); +void finish_anatop_bypass(void); +#endif + #endif /* __SYS_PROTO_IMX6_ */ diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h index bfa68a9d2a0..a000ae05d77 100644 --- a/arch/arm/include/asm/arch-mx7/crm_regs.h +++ b/arch/arm/include/asm/arch-mx7/crm_regs.h @@ -1998,6 +1998,14 @@ struct mxc_ccm_anatop_reg { #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT 29 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))< +bool is_usb_boot(void); +#define is_boot_from_usb is_usb_boot + /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB * If boot from the other mode, USB0_PWD will keep reset value */ -#define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ +#define is_usbotg_boot_enabled(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ readl(USBOTG2_IPS_BASE_ADDR + 0x158)) #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140) diff --git a/arch/arm/include/asm/arch-mx7/snvs.h b/arch/arm/include/asm/arch-mx7/snvs.h new file mode 100644 index 00000000000..a18f8535109 --- /dev/null +++ b/arch/arm/include/asm/arch-mx7/snvs.h @@ -0,0 +1,41 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7_SNVS_H__ +#define __MX7_SNVS_H__ + +#define SNVS_HPCOMR SNVS_BASE_ADDR + 0x04 +#define SNVS_HPSICR SNVS_BASE_ADDR + 0x0C +#define SNVS_HPSVCR SNVS_BASE_ADDR + 0x10 +#define SNVS_HPSR SNVS_BASE_ADDR + 0x14 +#define SNVS_HPSVSR SNVS_BASE_ADDR + 0x18 +#define SNVS_LPCR SNVS_BASE_ADDR + 0x38 +#define SNVS_LPMKCR SNVS_BASE_ADDR + 0x3C +#define SNVS_LPTGFCR SNVS_BASE_ADDR + 0x44 +#define SNVS_LPTDCR SNVS_BASE_ADDR + 0x48 +#define SNVS_LPSR SNVS_BASE_ADDR + 0x4C +#define SNVS_LPPGDR SNVS_BASE_ADDR + 0x64 +#define SNVS_LPZMKR0 SNVS_BASE_ADDR + 0x6C +#define SNVS_LPZMKR1 SNVS_BASE_ADDR + 0x70 +#define SNVS_LPZMKR2 SNVS_BASE_ADDR + 0x74 +#define SNVS_LPZMKR3 SNVS_BASE_ADDR + 0x78 +#define SNVS_LPZMKR4 SNVS_BASE_ADDR + 0x7C +#define SNVS_LPZMKR5 SNVS_BASE_ADDR + 0x80 +#define SNVS_LPZMKR6 SNVS_BASE_ADDR + 0x84 +#define SNVS_LPZMKR7 SNVS_BASE_ADDR + 0x88 +#define SNVS_LPTDC2R SNVS_BASE_ADDR + 0xA0 +#define SNVS_LPTDSR SNVS_BASE_ADDR + 0xA4 +#define SNVS_LPTGF1CR SNVS_BASE_ADDR + 0xA8 +#define SNVS_LPTGF2CR SNVS_BASE_ADDR + 0xAC +#define SNVS_LPAT1CR SNVS_BASE_ADDR + 0xC0 +#define SNVS_LPATCTLR SNVS_BASE_ADDR + 0xE0 +#define SNVS_LPATCLKR SNVS_BASE_ADDR + 0xE4 +#define SNVS_LPATRC1R SNVS_BASE_ADDR + 0xE8 +#define SNVS_LPATRC2R SNVS_BASE_ADDR + 0xEC + +#define AT5_POLYSEED 0x12345678 + +#endif diff --git a/arch/arm/include/asm/arch-mx7ulp/clock.h b/arch/arm/include/asm/arch-mx7ulp/clock.h index 92d4463dff5..ca53abae2f8 100644 --- a/arch/arm/include/asm/arch-mx7ulp/clock.h +++ b/arch/arm/include/asm/arch-mx7ulp/clock.h @@ -15,7 +15,7 @@ enum mxc_clock { MXC_AHB_CLK, MXC_IPG_CLK, MXC_UART_CLK, - MXC_CSPI_CLK, + MXC_LPSPI_CLK, MXC_AXI_CLK, MXC_DDR_CLK, MXC_ESDHC_CLK, @@ -29,12 +29,18 @@ u32 get_lpuart_clk(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); u32 imx_get_i2cclk(unsigned i2c_num); #endif +#ifdef CONFIG_FSL_LPSPI +int enable_lpspi_clk(unsigned char enable, unsigned spi_num); +u32 imx_get_spiclk(unsigned spi_num); +#endif #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable); #endif #ifdef CONFIG_USB_EHCI_HCD void enable_usboh3_clk(unsigned char enable); #endif +void enable_mipi_dsi_clk(unsigned char enable); +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz); void init_clk_usdhc(u32 index); void clock_init(void); void hab_caam_clock_enable(unsigned char enable); diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index 9a420dc30bf..4103c6ec8a6 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -16,6 +16,8 @@ #define CAAM_SEC_SRAM_SIZE (SZ_32K) #define CAAM_SEC_SRAM_END (CAAM_SEC_SRAM_BASE + CAAM_SEC_SRAM_SIZE - 1) +#define CAAM_ARB_BASE_ADDR CAAM_SEC_SRAM_BASE + #define OCRAM_0_BASE (0x2F000000) #define OCRAM_0_SIZE (SZ_128K) #define OCRAM_0_END (OCRAM_0_BASE + OCRAM_0_SIZE - 1) @@ -65,6 +67,8 @@ #define SIM1_PCC1_SLOT (48) #define MMDC0_AIPS3_SLOT (43) #define IOMUXC_DDR_AIPS3_SLOT (45) +#define DSI_AIPS3_SLOT (41) +#define LCDIF_AIPS3_SLOT (42) #define LPI2C0_AIPS0_SLOT (51) #define LPI2C1_AIPS0_SLOT (52) @@ -127,6 +131,9 @@ #define SIM_SOPT1_PMIC_STBY_REQ (1<<2) #define SIM_SOPT1_A7_SW_RESET (1<<0) +#define WKPU_WAKEUP_EN 0x88 +#define WKPU_QSPI_CHANNEL BIT(20) + #define IOMUXC_PCR_MUX_ALT_SHIFT (8) #define IOMUXC_PCR_MUX_ALT_MASK (0xF00) #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0) @@ -178,6 +185,10 @@ #define USDHC0_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC0_AIPS2_SLOT))) #define USDHC1_RBASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * USDHC1_AIPS2_SLOT))) +#define LCDIF_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * LCDIF_AIPS3_SLOT))) +#define MXS_LCDIF_BASE LCDIF_RBASE + + #define SNVS_BASE ((AIPS2_BASE + (AIPS2_SLOT_SIZE * SNVS_AIPS2_SLOT))) #define SNVS_LP_LPCR (SNVS_BASE + 0x38) @@ -224,6 +235,16 @@ #define IOMUXC_DDR_RBASE ((AIPS3_BASE + (AIPS3_SLOT_SIZE * IOMUXC_DDR_AIPS3_SLOT))) #define MMDC0_PCC_REG (PCC3_RBASE + (4 * MMDC0_PCC3_SLOT)) +#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */ + +#define CONFIG_SYS_FSL_SEC_OFFSET 0 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CONFIG_SYS_FSL_SEC_OFFSET) +#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ + CONFIG_SYS_FSL_JR0_OFFSET) +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 + #define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) #define IOMUXC_DPCR_DDR_DQS2 ((IOMUXC_DDR_RBASE + (4 * 34))) @@ -945,12 +966,15 @@ #define SNVS_LPCR_DPEN (0x20) #define SNVS_LPCR_SRTC_ENV (0x1) +#define SNVS_BASE_REVB (0x41070000) +#define SNVS_HPSR_REVB (SNVS_BASE_REVB + 0x14) #define SRC_BASE_ADDR CMC1_RBASE #define IRAM_BASE_ADDR OCRAM_0_BASE #define IOMUXC_BASE_ADDR IOMUXC1_RBASE #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include #include @@ -1137,7 +1161,9 @@ struct bootrom_sw_info { u32 reserved_3[3]; }; -#define is_boot_from_usb(void) (!(readl(USB_PHY0_BASE_ADDR) & (1<<20))) +#include +bool is_usb_boot(void); +#define is_boot_from_usb is_usb_boot #define disconnect_from_pc(void) writel(0x0, USBOTG0_RBASE + 0x140) #endif diff --git a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h index 139b766c261..1e19745d145 100644 --- a/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h +++ b/arch/arm/include/asm/arch-mx7ulp/mx7ulp-pins.h @@ -12,7 +12,7 @@ enum { MX7ULP_PAD_PTA0__CMP0_IN1_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA0__PTA0 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA0__LPSPI0_PCS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x2, 0), - MX7ULP_PAD_PTA0__LPUART0_CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0), + MX7ULP_PAD_PTA0__LPUART0_CTS_B = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x2, 0), MX7ULP_PAD_PTA0__LPI2C0_SCL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x2, 0), MX7ULP_PAD_PTA0__TPM0_CLKIN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x2, 0), MX7ULP_PAD_PTA0__I2S0_RX_BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x2, 0), @@ -20,7 +20,7 @@ enum { MX7ULP_PAD_PTA1__CMP0_IN2_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA1__PTA1 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA1__LPSPI0_PCS2 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x1, 0), - MX7ULP_PAD_PTA1__LPUART0_RTS_b = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA1__LPUART0_RTS_B = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA1__LPI2C0_SDA = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x1, 0), MX7ULP_PAD_PTA1__TPM0_CH0 = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x1, 0), MX7ULP_PAD_PTA1__I2S0_RX_FS = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x1, 0), @@ -42,72 +42,72 @@ enum { MX7ULP_PAD_PTA4__ADC1_CH3A = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA4__PTA4 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA4__LPSPI0_SIN = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x1, 0), - MX7ULP_PAD_PTA4__LPUART1_CTS_b = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0), + MX7ULP_PAD_PTA4__LPUART1_CTS_B = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x1, 0), MX7ULP_PAD_PTA4__LPI2C1_SCL = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x1, 0), MX7ULP_PAD_PTA4__TPM0_CH3 = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x1, 0), MX7ULP_PAD_PTA4__I2S0_MCLK = IOMUX_PAD(0xD010, 0xD010, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x1, 0), MX7ULP_PAD_PTA5__ADC1_CH3B = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA5__PTA5 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA5__LPSPI0_SOUT = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x1, 0), - MX7ULP_PAD_PTA5__LPUART1_RTS_b = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA5__LPUART1_RTS_B = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA5__LPI2C1_SDA = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x1, 0), MX7ULP_PAD_PTA5__TPM0_CH4 = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x1, 0), MX7ULP_PAD_PTA5__I2S0_TX_BCLK = IOMUX_PAD(0xD014, 0xD014, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C0, 0x1, 0), - MX7ULP_PAD_PTA6__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA6__ADC1_CH4A = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA6__PTA6 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA6__LPSPI0_SCK = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x1, 0), MX7ULP_PAD_PTA6__LPUART1_TX = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x4, 0xD20C, 0x1, 0), MX7ULP_PAD_PTA6__LPI2C1_HREQ = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x5, 0xD184, 0x1, 0), MX7ULP_PAD_PTA6__TPM0_CH5 = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x6, 0xD14C, 0x1, 0), MX7ULP_PAD_PTA6__I2S0_TX_FS = IOMUX_PAD(0xD018, 0xD018, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x1, 0), - MX7ULP_PAD_PTA7__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA7__ADC1_CH4B = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA7__PTA7 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA7__LPUART1_RX = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x4, 0xD208, 0x1, 0), MX7ULP_PAD_PTA7__TPM1_CH1 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x1, 0), MX7ULP_PAD_PTA7__I2S0_TXD0 = IOMUX_PAD(0xD01C, 0xD01C, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA8__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA8__ADC1_CH5A = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA8__PTA8 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA8__LPSPI1_PCS1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x1, 0), - MX7ULP_PAD_PTA8__LPUART2_CTS_b = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0), + MX7ULP_PAD_PTA8__LPUART2_CTS_B = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x1, 0), MX7ULP_PAD_PTA8__LPI2C2_SCL = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x1, 0), MX7ULP_PAD_PTA8__TPM1_CLKIN = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x1, 0), MX7ULP_PAD_PTA8__I2S0_TXD1 = IOMUX_PAD(0xD020, 0xD020, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA9__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__ADC1_CH5B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA9__PTA9 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA9__LPSPI1_PCS2 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x1, 0), - MX7ULP_PAD_PTA9__LPUART2_RTS_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__LPUART2_RTS_B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA9__LPI2C2_SDA = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x1, 0), MX7ULP_PAD_PTA9__TPM1_CH0 = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x1, 0), - MX7ULP_PAD_PTA9__NMI0_b = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA10__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA9__NMI0_B = IOMUX_PAD(0xD024, 0xD024, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA10__ADC1_CH6A = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA10__PTA10 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA10__LPSPI1_PCS3 = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x1, 0), MX7ULP_PAD_PTA10__LPUART2_TX = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x1, 0), MX7ULP_PAD_PTA10__LPI2C2_HREQ = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x1, 0), MX7ULP_PAD_PTA10__TPM2_CLKIN = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x1, 0), MX7ULP_PAD_PTA10__I2S0_RX_BCLK = IOMUX_PAD(0xD028, 0xD028, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8, 0x1, 0), - MX7ULP_PAD_PTA11__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA11__ADC1_CH6B = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA11__PTA11 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA11__LPUART2_RX = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x1, 0), MX7ULP_PAD_PTA11__TPM2_CH0 = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x1, 0), MX7ULP_PAD_PTA11__I2S0_RX_FS = IOMUX_PAD(0xD02C, 0xD02C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1BC, 0x2, 0), - MX7ULP_PAD_PTA12__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA12__ADC1_CH7A = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA12__PTA12 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA12__LPSPI1_SIN = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x1, 0), - MX7ULP_PAD_PTA12__LPUART3_CTS_b = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0), + MX7ULP_PAD_PTA12__LPUART3_CTS_B = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x1, 0), MX7ULP_PAD_PTA12__LPI2C3_SCL = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x1, 0), MX7ULP_PAD_PTA12__TPM2_CH1 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x1, 0), MX7ULP_PAD_PTA12__I2S0_RXD0 = IOMUX_PAD(0xD030, 0xD030, IOMUX_CONFIG_MPORTS | 0x7, 0xD1DC, 0x2, 0), - MX7ULP_PAD_PTA13__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__ADC1_CH7B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA13__PTA13 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA13__LPSPI1_SOUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x2, 0), - MX7ULP_PAD_PTA13__LPUART3_RTS_b = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA13__LPUART3_RTS_B = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA13__LPI2C3_SDA = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x2, 0), MX7ULP_PAD_PTA13__TPM3_CLKIN = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x1, 0), MX7ULP_PAD_PTA13__I2S0_RXD1 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E0, 0x2, 0), MX7ULP_PAD_PTA13__CMP0_OUT = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTA13__LLWU0_P2 = IOMUX_PAD(0xD034, 0xD034, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA14__ADC1_CH4A_5A_6A_7A_8A = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA14__ADC1_CH8A = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA14__PTA14 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA14__LPSPI1_SCK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x3, 0xD12C, 0x2, 0), MX7ULP_PAD_PTA14__LPUART3_TX = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x4, 0xD224, 0x2, 0), @@ -115,7 +115,7 @@ enum { MX7ULP_PAD_PTA14__TPM3_CH0 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x1, 0), MX7ULP_PAD_PTA14__I2S0_MCLK = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B4, 0x2, 0), MX7ULP_PAD_PTA14__LLWU0_P3 = IOMUX_PAD(0xD038, 0xD038, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA15__ADC1_CH4B_5B_6B_7B_8B = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA15__ADC1_CH8B = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA15__PTA15 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA15__LPSPI1_PCS0 = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x3, 0xD11C, 0x1, 0), MX7ULP_PAD_PTA15__LPUART3_RX = IOMUX_PAD(0xD03C, 0xD03C, IOMUX_CONFIG_MPORTS | 0x4, 0xD220, 0x1, 0), @@ -125,7 +125,7 @@ enum { MX7ULP_PAD_PTA16__PTA16 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA16__FXIO0_D0 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA16__LPSPI0_SOUT = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x3, 0xD118, 0x2, 0), - MX7ULP_PAD_PTA16__LPUART0_CTS_b = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0), + MX7ULP_PAD_PTA16__LPUART0_CTS_B = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8, 0x1, 0), MX7ULP_PAD_PTA16__LPI2C0_SCL = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C, 0x1, 0), MX7ULP_PAD_PTA16__TPM3_CH2 = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x6, 0xD168, 0x1, 0), MX7ULP_PAD_PTA16__I2S0_TX_FS = IOMUX_PAD(0xD040, 0xD040, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C4, 0x2, 0), @@ -133,7 +133,7 @@ enum { MX7ULP_PAD_PTA17__PTA17 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA17__FXIO0_D1 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA17__LPSPI0_SCK = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x2, 0), - MX7ULP_PAD_PTA17__LPUART0_RTS_b = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA17__LPUART0_RTS_B = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA17__LPI2C0_SDA = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x5, 0xD180, 0x2, 0), MX7ULP_PAD_PTA17__TPM3_CH3 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x6, 0xD16C, 0x1, 0), MX7ULP_PAD_PTA17__I2S0_TXD0 = IOMUX_PAD(0xD044, 0xD044, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), @@ -154,23 +154,23 @@ enum { MX7ULP_PAD_PTA19__I2S1_RX_BCLK = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1CC, 0x1, 0), MX7ULP_PAD_PTA19__LPTMR0_ALT3 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTA19__LLWU0_P5 = IOMUX_PAD(0xD04C, 0xD04C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA20__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA20__ADC0_10A = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA20__PTA20 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA20__FXIO0_D4 = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA20__LPSPI0_SIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x3, 0xD114, 0x2, 0), - MX7ULP_PAD_PTA20__LPUART1_CTS_b = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0), + MX7ULP_PAD_PTA20__LPUART1_CTS_B = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x4, 0xD204, 0x2, 0), MX7ULP_PAD_PTA20__LPI2C1_SCL = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x5, 0xD188, 0x2, 0), MX7ULP_PAD_PTA20__TPM0_CLKIN = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8, 0x1, 0), MX7ULP_PAD_PTA20__I2S1_RX_FS = IOMUX_PAD(0xD050, 0xD050, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D0, 0x1, 0), - MX7ULP_PAD_PTA21__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__ADC0_CH10B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA21__PTA21 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA21__FXIO0_D5 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA21__LPSPI0_PCS1 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x3, 0xD104, 0x1, 0), - MX7ULP_PAD_PTA21__LPUART1_RTS_b = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA21__LPUART1_RTS_B = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA21__LPI2C1_SDA = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x5, 0xD18C, 0x2, 0), MX7ULP_PAD_PTA21__TPM0_CH0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x6, 0xD138, 0x2, 0), MX7ULP_PAD_PTA21__I2S1_RXD0 = IOMUX_PAD(0xD054, 0xD054, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E4, 0x1, 0), - MX7ULP_PAD_PTA22__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__ADC0_CH9A = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA22__PTA22 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA22__FXIO0_D6 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA22__LPSPI0_PCS2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x2, 0), @@ -179,8 +179,8 @@ enum { MX7ULP_PAD_PTA22__TPM0_CH1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x6, 0xD13C, 0x2, 0), MX7ULP_PAD_PTA22__I2S1_RXD1 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0x7, 0xD1E8, 0x1, 0), MX7ULP_PAD_PTA22__LPTMR0_ALT2 = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA22__EWM_OUT_b = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA23__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA22__EWM_OUT_B = IOMUX_PAD(0xD058, 0xD058, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA23__ADC0_CH9B = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA23__PTA23 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA23__FXIO0_D7 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA23__LPSPI0_PCS3 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x3, 0xD10C, 0x2, 0), @@ -188,19 +188,19 @@ enum { MX7ULP_PAD_PTA23__TPM0_CH2 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x6, 0xD140, 0x2, 0), MX7ULP_PAD_PTA23__I2S1_MCLK = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0x7, 0xD1C8, 0x1, 0), MX7ULP_PAD_PTA23__LLWU0_P6 = IOMUX_PAD(0xD05C, 0xD05C, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA24__ADC0_CH8A_9A_10A = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA24__ADC0_CH8A = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA24__PTA24 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA24__FXIO0_D8 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA24__LPSPI1_PCS1 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x3, 0xD120, 0x2, 0), - MX7ULP_PAD_PTA24__LPUART2_CTS_b = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0), + MX7ULP_PAD_PTA24__LPUART2_CTS_B = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x4, 0xD210, 0x2, 0), MX7ULP_PAD_PTA24__LPI2C2_SCL = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x5, 0xD194, 0x2, 0), MX7ULP_PAD_PTA24__TPM0_CH3 = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x6, 0xD144, 0x2, 0), MX7ULP_PAD_PTA24__I2S1_TX_BCLK = IOMUX_PAD(0xD060, 0xD060, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D4, 0x1, 0), - MX7ULP_PAD_PTA25__ADC0_CH8B_9B_10B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__ADC0_CH8B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA25__PTA25 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA25__FXIO0_D9 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA25__LPSPI1_PCS2 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x2, 0), - MX7ULP_PAD_PTA25__LPUART2_RTS_b = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA25__LPUART2_RTS_B = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA25__LPI2C2_SDA = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x5, 0xD198, 0x2, 0), MX7ULP_PAD_PTA25__TPM0_CH4 = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x6, 0xD148, 0x2, 0), MX7ULP_PAD_PTA25__I2S1_TX_FS = IOMUX_PAD(0xD064, 0xD064, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x1, 0), @@ -222,7 +222,7 @@ enum { MX7ULP_PAD_PTA28__JTAG_TDI = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTA28__FXIO0_D12 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA28__LPSPI1_SIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x3, 0xD130, 0x2, 0), - MX7ULP_PAD_PTA28__LPUART3_CTS_b = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0), + MX7ULP_PAD_PTA28__LPUART3_CTS_B = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x4, 0xD21C, 0x2, 0), MX7ULP_PAD_PTA28__LPI2C3_SCL = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x2, 0), MX7ULP_PAD_PTA28__TPM1_CLKIN = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x6, 0xD1AC, 0x2, 0), MX7ULP_PAD_PTA28__I2S1_TXD2 = IOMUX_PAD(0xD070, 0xD070, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), @@ -230,7 +230,7 @@ enum { MX7ULP_PAD_PTA29__JTAG_TCLK_SWD_CLK = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTA29__FXIO0_D13 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTA29__LPSPI1_SOUT = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x3, 0xD134, 0x1, 0), - MX7ULP_PAD_PTA29__LPUART3_RTS_b = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA29__LPUART3_RTS_B = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTA29__LPI2C3_SDA = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x1, 0), MX7ULP_PAD_PTA29__TPM1_CH0 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x2, 0), MX7ULP_PAD_PTA29__I2S1_TXD3 = IOMUX_PAD(0xD074, 0xD074, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), @@ -242,7 +242,7 @@ enum { MX7ULP_PAD_PTA30__LPI2C3_HREQ = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x1, 0), MX7ULP_PAD_PTA30__TPM2_CLKIN = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x2, 0), MX7ULP_PAD_PTA30__I2S1_TXD0 = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), - MX7ULP_PAD_PTA30__JTAG_TRST_b = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTA30__JTAG_TRST_B = IOMUX_PAD(0xD078, 0xD078, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTA31__ADC0_CH1B = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTA31__PTA31 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTA31__FXIO0_D15 = IOMUX_PAD(0xD07C, 0xD07C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), @@ -261,7 +261,7 @@ enum { MX7ULP_PAD_PTB0__TPM2_CH1 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x2, 0), MX7ULP_PAD_PTB0__CLKOUT0 = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTB0__CMP1_OUT = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB0__EWM_OUT_b = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB0__EWM_OUT_B = IOMUX_PAD(0xD080, 0xD080, IOMUX_CONFIG_MPORTS | 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTB1__ADC0_CH0B = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB1__PTB1 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB1__FXIO0_D17 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), @@ -272,7 +272,7 @@ enum { MX7ULP_PAD_PTB1__RTC_CLKOUT = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTB1__EWM_IN = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xc, 0xD228, 0x2, 0), MX7ULP_PAD_PTB1__LLWU0_P8 = IOMUX_PAD(0xD084, 0xD084, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB2__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB2__ADC0_CH6A = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB2__PTB2 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB2__FXIO0_D18 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB2__LPSPI0_SCK = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x3, 0xD110, 0x3, 0), @@ -280,7 +280,7 @@ enum { MX7ULP_PAD_PTB2__TPM3_CH0 = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x2, 0), MX7ULP_PAD_PTB2__I2S1_TX_FS = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0x7, 0xD1D8, 0x2, 0), MX7ULP_PAD_PTB2__TRACE_CLKOUT = IOMUX_PAD(0xD088, 0xD088, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB3__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB3__ADC0_CH6B = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB3__PTB3 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB3__FXIO0_D19 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB3__LPSPI0_PCS0 = IOMUX_PAD(0xD08C, 0xD08C, IOMUX_CONFIG_MPORTS | 0x3, 0xD100, 0x3, 0), @@ -299,6 +299,7 @@ enum { MX7ULP_PAD_PTB4__I2S1_TXD1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), MX7ULP_PAD_PTB4__QSPIA_DATA7 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTB4__TRACE_D1 = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB4__SEC_VIO_B = IOMUX_PAD(0xD090, 0xD090, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__PTB5 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__FXIO0_D21 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__LPSPI0_PCS2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x3, 0xD108, 0x3, 0), @@ -308,6 +309,7 @@ enum { MX7ULP_PAD_PTB5__I2S1_TXD2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x7, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__QSPIA_DATA6 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTB5__TRACE_D2 = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB5__RTC_CLKOUT = IOMUX_PAD(0xD094, 0xD094, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTB6__ADC1_CH1A = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB6__PTB6 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB6__FXIO0_D22 = IOMUX_PAD(0xD098, 0xD098, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), @@ -369,6 +371,7 @@ enum { MX7ULP_PAD_PTB12__PTB12 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB12__FXIO0_D28 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB12__LPSPI1_PCS2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x3, 0xD124, 0x3, 0), + MX7ULP_PAD_PTB12__LPUART2_TX = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x4, 0xD218, 0x4, 0), MX7ULP_PAD_PTB12__LPI2C3_SCL = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A0, 0x3, 0), MX7ULP_PAD_PTB12__TPM1_CH0 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x6, 0xD150, 0x3, 0), MX7ULP_PAD_PTB12__I2S1_RXD2 = IOMUX_PAD(0xD0B0, 0xD0B0, IOMUX_CONFIG_MPORTS | 0x7, 0xD1EC, 0x2, 0), @@ -377,6 +380,7 @@ enum { MX7ULP_PAD_PTB13__PTB13 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB13__FXIO0_D29 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTB13__LPSPI1_PCS3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x3, 0xD128, 0x3, 0), + MX7ULP_PAD_PTB13__LPUART2_RX = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x4, 0xD214, 0x4, 0), MX7ULP_PAD_PTB13__LPI2C3_SDA = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x5, 0xD1A4, 0x3, 0), MX7ULP_PAD_PTB13__TPM1_CH1 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x6, 0xD154, 0x3, 0), MX7ULP_PAD_PTB13__I2S1_RXD3 = IOMUX_PAD(0xD0B4, 0xD0B4, IOMUX_CONFIG_MPORTS | 0x7, 0xD1F0, 0x2, 0), @@ -388,7 +392,8 @@ enum { MX7ULP_PAD_PTB14__LPI2C2_HREQ = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x5, 0xD190, 0x3, 0), MX7ULP_PAD_PTB14__TPM2_CLKIN = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x6, 0xD1F4, 0x3, 0), MX7ULP_PAD_PTB14__QSPIA_SS1_B = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB14__QSPIA_SCLK_b = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__QSPIA_SCLK_B = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB14__RTC_CLKOUT = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTB14__LLWU0_P13 = IOMUX_PAD(0xD0B8, 0xD0B8, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), MX7ULP_PAD_PTB15__ADC1_CH2B = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB15__PTB15 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), @@ -396,70 +401,64 @@ enum { MX7ULP_PAD_PTB15__LPI2C3_HREQ = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x5, 0xD19C, 0x3, 0), MX7ULP_PAD_PTB15__TPM2_CH0 = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x6, 0xD158, 0x3, 0), MX7ULP_PAD_PTB15__QSPIA_SCLK = IOMUX_PAD(0xD0BC, 0xD0BC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB16__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB16__ADC0_CH4A = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB16__PTB16 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB16__TPM2_CH1 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x6, 0xD15C, 0x3, 0), MX7ULP_PAD_PTB16__QSPIA_DATA3 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTB16__LLWU0_P14 = IOMUX_PAD(0xD0C0, 0xD0C0, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB17__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB17__ADC0_CH4B = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB17__PTB17 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB17__TPM3_CLKIN = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x6, 0xD1B0, 0x2, 0), MX7ULP_PAD_PTB17__QSPIA_DATA2 = IOMUX_PAD(0xD0C4, 0xD0C4, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB18__ADC0_CH4A_5A_6A = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB18__ADC0_CH5A = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB18__PTB18 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB18__TPM3_CH0 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x6, 0xD160, 0x3, 0), MX7ULP_PAD_PTB18__QSPIA_DATA1 = IOMUX_PAD(0xD0C8, 0xD0C8, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__ADC0_CH4B_5B_6B = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__ADC0_CH5B = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x0, 0x0000, 0x0, 0), MX7ULP_PAD_PTB19__PTB19 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTB19__TPM3_CH1 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x6, 0xD164, 0x3, 0), MX7ULP_PAD_PTB19__QSPIA_DATA0 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTB19__USB0_ID = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0x0000, 0x0, 0), + MX7ULP_PAD_PTB19__USB0_ID = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xa, 0xD338, 0x0, 0), MX7ULP_PAD_PTB19__LLWU0_P15 = IOMUX_PAD(0xD0CC, 0xD0CC, IOMUX_CONFIG_MPORTS | 0xd, 0x0000, 0x0, 0), MX7ULP_PAD_PTC0__PTC0 = IOMUX_PAD(0x0000, 0x0000, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__LPUART4_CTS_b = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0), + MX7ULP_PAD_PTC0__LPUART4_CTS_B = IOMUX_PAD(0x0000, 0x0000, 0x4, 0x0244, 0x1, 0), MX7ULP_PAD_PTC0__LPI2C4_SCL = IOMUX_PAD(0x0000, 0x0000, 0x5, 0x0278, 0x1, 0), MX7ULP_PAD_PTC0__TPM4_CLKIN = IOMUX_PAD(0x0000, 0x0000, 0x6, 0x0298, 0x1, 0), MX7ULP_PAD_PTC0__FB_AD0 = IOMUX_PAD(0x0000, 0x0000, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC0__TRACE_D15 = IOMUX_PAD(0x0000, 0x0000, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC0__DEBUG_MUX0 = IOMUX_PAD(0x0000, 0x0000, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC1__PTC1 = IOMUX_PAD(0x0004, 0x0004, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__LPUART4_RTS_b = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC1__LPUART4_RTS_B = IOMUX_PAD(0x0004, 0x0004, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTC1__LPI2C4_SDA = IOMUX_PAD(0x0004, 0x0004, 0x5, 0x027C, 0x1, 0), MX7ULP_PAD_PTC1__TPM4_CH0 = IOMUX_PAD(0x0004, 0x0004, 0x6, 0x0280, 0x1, 0), MX7ULP_PAD_PTC1__FB_AD1 = IOMUX_PAD(0x0004, 0x0004, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC1__TRACE_D14 = IOMUX_PAD(0x0004, 0x0004, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC1__DEBUG_MUX1 = IOMUX_PAD(0x0004, 0x0004, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC2__PTC2 = IOMUX_PAD(0x0008, 0x0008, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC2__LPUART4_TX = IOMUX_PAD(0x0008, 0x0008, 0x4, 0x024C, 0x1, 0), MX7ULP_PAD_PTC2__LPI2C4_HREQ = IOMUX_PAD(0x0008, 0x0008, 0x5, 0x0274, 0x1, 0), MX7ULP_PAD_PTC2__TPM4_CH1 = IOMUX_PAD(0x0008, 0x0008, 0x6, 0x0284, 0x1, 0), MX7ULP_PAD_PTC2__FB_AD2 = IOMUX_PAD(0x0008, 0x0008, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC2__TRACE_D13 = IOMUX_PAD(0x0008, 0x0008, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC2__DEBUG_MUX2 = IOMUX_PAD(0x0008, 0x0008, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC3__PTC3 = IOMUX_PAD(0x000C, 0x000C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC3__LPUART4_RX = IOMUX_PAD(0x000C, 0x000C, 0x4, 0x0248, 0x1, 0), MX7ULP_PAD_PTC3__TPM4_CH2 = IOMUX_PAD(0x000C, 0x000C, 0x6, 0x0288, 0x1, 0), MX7ULP_PAD_PTC3__FB_AD3 = IOMUX_PAD(0x000C, 0x000C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC3__TRACE_D12 = IOMUX_PAD(0x000C, 0x000C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC3__DEBUG_MUX3 = IOMUX_PAD(0x000C, 0x000C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC4__PTC4 = IOMUX_PAD(0x0010, 0x0010, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC4__FXIO1_D0 = IOMUX_PAD(0x0010, 0x0010, 0x2, 0x0204, 0x1, 0), MX7ULP_PAD_PTC4__LPSPI2_PCS1 = IOMUX_PAD(0x0010, 0x0010, 0x3, 0x02A0, 0x1, 0), - MX7ULP_PAD_PTC4__LPUART5_CTS_b = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0), + MX7ULP_PAD_PTC4__LPUART5_CTS_B = IOMUX_PAD(0x0010, 0x0010, 0x4, 0x0250, 0x1, 0), MX7ULP_PAD_PTC4__LPI2C5_SCL = IOMUX_PAD(0x0010, 0x0010, 0x5, 0x02BC, 0x1, 0), MX7ULP_PAD_PTC4__TPM4_CH3 = IOMUX_PAD(0x0010, 0x0010, 0x6, 0x028C, 0x1, 0), MX7ULP_PAD_PTC4__FB_AD4 = IOMUX_PAD(0x0010, 0x0010, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC4__TRACE_D11 = IOMUX_PAD(0x0010, 0x0010, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC4__DEBUG_MUX4 = IOMUX_PAD(0x0010, 0x0010, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC5__PTC5 = IOMUX_PAD(0x0014, 0x0014, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC5__FXIO1_D1 = IOMUX_PAD(0x0014, 0x0014, 0x2, 0x0208, 0x1, 0), MX7ULP_PAD_PTC5__LPSPI2_PCS2 = IOMUX_PAD(0x0014, 0x0014, 0x3, 0x02A4, 0x1, 0), - MX7ULP_PAD_PTC5__LPUART5_RTS_b = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC5__LPUART5_RTS_B = IOMUX_PAD(0x0014, 0x0014, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTC5__LPI2C5_SDA = IOMUX_PAD(0x0014, 0x0014, 0x5, 0x02C0, 0x1, 0), MX7ULP_PAD_PTC5__TPM4_CH4 = IOMUX_PAD(0x0014, 0x0014, 0x6, 0x0290, 0x1, 0), MX7ULP_PAD_PTC5__FB_AD5 = IOMUX_PAD(0x0014, 0x0014, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC5__TRACE_D10 = IOMUX_PAD(0x0014, 0x0014, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC5__DEBUG_MUX5 = IOMUX_PAD(0x0014, 0x0014, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC6__PTC6 = IOMUX_PAD(0x0018, 0x0018, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC6__FXIO1_D2 = IOMUX_PAD(0x0018, 0x0018, 0x2, 0x020C, 0x1, 0), MX7ULP_PAD_PTC6__LPSPI2_PCS3 = IOMUX_PAD(0x0018, 0x0018, 0x3, 0x02A8, 0x1, 0), @@ -468,32 +467,28 @@ enum { MX7ULP_PAD_PTC6__TPM4_CH5 = IOMUX_PAD(0x0018, 0x0018, 0x6, 0x0294, 0x1, 0), MX7ULP_PAD_PTC6__FB_AD6 = IOMUX_PAD(0x0018, 0x0018, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC6__TRACE_D9 = IOMUX_PAD(0x0018, 0x0018, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC6__DEBUG_MUX6 = IOMUX_PAD(0x0018, 0x0018, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC7__PTC7 = IOMUX_PAD(0x001C, 0x001C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC7__FXIO1_D3 = IOMUX_PAD(0x001C, 0x001C, 0x2, 0x0210, 0x1, 0), MX7ULP_PAD_PTC7__LPUART5_RX = IOMUX_PAD(0x001C, 0x001C, 0x4, 0x0254, 0x1, 0), MX7ULP_PAD_PTC7__TPM5_CH1 = IOMUX_PAD(0x001C, 0x001C, 0x6, 0x02C8, 0x1, 0), MX7ULP_PAD_PTC7__FB_AD7 = IOMUX_PAD(0x001C, 0x001C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC7__TRACE_D8 = IOMUX_PAD(0x001C, 0x001C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC7__DEBUG_MUX7 = IOMUX_PAD(0x001C, 0x001C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC8__PTC8 = IOMUX_PAD(0x0020, 0x0020, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC8__FXIO1_D4 = IOMUX_PAD(0x0020, 0x0020, 0x2, 0x0214, 0x1, 0), MX7ULP_PAD_PTC8__LPSPI2_SIN = IOMUX_PAD(0x0020, 0x0020, 0x3, 0x02B0, 0x1, 0), - MX7ULP_PAD_PTC8__LPUART6_CTS_b = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0), + MX7ULP_PAD_PTC8__LPUART6_CTS_B = IOMUX_PAD(0x0020, 0x0020, 0x4, 0x025C, 0x1, 0), MX7ULP_PAD_PTC8__LPI2C6_SCL = IOMUX_PAD(0x0020, 0x0020, 0x5, 0x02FC, 0x1, 0), MX7ULP_PAD_PTC8__TPM5_CLKIN = IOMUX_PAD(0x0020, 0x0020, 0x6, 0x02CC, 0x1, 0), MX7ULP_PAD_PTC8__FB_AD8 = IOMUX_PAD(0x0020, 0x0020, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC8__TRACE_D7 = IOMUX_PAD(0x0020, 0x0020, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC8__DEBUG_MUX8 = IOMUX_PAD(0x0020, 0x0020, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC9__PTC9 = IOMUX_PAD(0x0024, 0x0024, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC9__FXIO1_D5 = IOMUX_PAD(0x0024, 0x0024, 0x2, 0x0218, 0x1, 0), MX7ULP_PAD_PTC9__LPSPI2_SOUT = IOMUX_PAD(0x0024, 0x0024, 0x3, 0x02B4, 0x1, 0), - MX7ULP_PAD_PTC9__LPUART6_RTS_b = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC9__LPUART6_RTS_B = IOMUX_PAD(0x0024, 0x0024, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTC9__LPI2C6_SDA = IOMUX_PAD(0x0024, 0x0024, 0x5, 0x0300, 0x1, 0), MX7ULP_PAD_PTC9__TPM5_CH0 = IOMUX_PAD(0x0024, 0x0024, 0x6, 0x02C4, 0x1, 0), MX7ULP_PAD_PTC9__FB_AD9 = IOMUX_PAD(0x0024, 0x0024, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC9__TRACE_D6 = IOMUX_PAD(0x0024, 0x0024, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC9__DEBUG_MUX9 = IOMUX_PAD(0x0024, 0x0024, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC10__PTC10 = IOMUX_PAD(0x0028, 0x0028, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC10__FXIO1_D6 = IOMUX_PAD(0x0028, 0x0028, 0x2, 0x021C, 0x1, 0), MX7ULP_PAD_PTC10__LPSPI2_SCK = IOMUX_PAD(0x0028, 0x0028, 0x3, 0x02AC, 0x1, 0), @@ -502,7 +497,6 @@ enum { MX7ULP_PAD_PTC10__TPM7_CH3 = IOMUX_PAD(0x0028, 0x0028, 0x6, 0x02E8, 0x1, 0), MX7ULP_PAD_PTC10__FB_AD10 = IOMUX_PAD(0x0028, 0x0028, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC10__TRACE_D5 = IOMUX_PAD(0x0028, 0x0028, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC10__DEBUG_MUX10 = IOMUX_PAD(0x0028, 0x0028, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC11__PTC11 = IOMUX_PAD(0x002C, 0x002C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC11__FXIO1_D7 = IOMUX_PAD(0x002C, 0x002C, 0x2, 0x0220, 0x1, 0), MX7ULP_PAD_PTC11__LPSPI2_PCS0 = IOMUX_PAD(0x002C, 0x002C, 0x3, 0x029C, 0x1, 0), @@ -510,25 +504,23 @@ enum { MX7ULP_PAD_PTC11__TPM7_CH4 = IOMUX_PAD(0x002C, 0x002C, 0x6, 0x02EC, 0x1, 0), MX7ULP_PAD_PTC11__FB_AD11 = IOMUX_PAD(0x002C, 0x002C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC11__TRACE_D4 = IOMUX_PAD(0x002C, 0x002C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC11__DEBUG_MUX11 = IOMUX_PAD(0x002C, 0x002C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC12__PTC12 = IOMUX_PAD(0x0030, 0x0030, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC12__FXIO1_D8 = IOMUX_PAD(0x0030, 0x0030, 0x2, 0x0224, 0x1, 0), MX7ULP_PAD_PTC12__LPSPI3_PCS1 = IOMUX_PAD(0x0030, 0x0030, 0x3, 0x0314, 0x1, 0), - MX7ULP_PAD_PTC12__LPUART7_CTS_b = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0), + MX7ULP_PAD_PTC12__LPUART7_CTS_B = IOMUX_PAD(0x0030, 0x0030, 0x4, 0x0268, 0x1, 0), MX7ULP_PAD_PTC12__LPI2C7_SCL = IOMUX_PAD(0x0030, 0x0030, 0x5, 0x0308, 0x1, 0), MX7ULP_PAD_PTC12__TPM7_CH5 = IOMUX_PAD(0x0030, 0x0030, 0x6, 0x02F0, 0x1, 0), MX7ULP_PAD_PTC12__FB_AD12 = IOMUX_PAD(0x0030, 0x0030, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC12__TRACE_D3 = IOMUX_PAD(0x0030, 0x0030, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC12__DEBUG_MUX12 = IOMUX_PAD(0x0030, 0x0030, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC13__PTC13 = IOMUX_PAD(0x0034, 0x0034, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC13__FXIO1_D9 = IOMUX_PAD(0x0034, 0x0034, 0x2, 0x0228, 0x1, 0), MX7ULP_PAD_PTC13__LPSPI3_PCS2 = IOMUX_PAD(0x0034, 0x0034, 0x3, 0x0318, 0x1, 0), - MX7ULP_PAD_PTC13__LPUART7_RTS_b = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__LPUART7_RTS_B = IOMUX_PAD(0x0034, 0x0034, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTC13__LPI2C7_SDA = IOMUX_PAD(0x0034, 0x0034, 0x5, 0x030C, 0x1, 0), MX7ULP_PAD_PTC13__TPM7_CLKIN = IOMUX_PAD(0x0034, 0x0034, 0x6, 0x02F4, 0x1, 0), MX7ULP_PAD_PTC13__FB_AD13 = IOMUX_PAD(0x0034, 0x0034, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC13__TRACE_D2 = IOMUX_PAD(0x0034, 0x0034, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC13__DEBUG_MUX13 = IOMUX_PAD(0x0034, 0x0034, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC13__USB0_ID = IOMUX_PAD(0x0034, 0x0034, 0xb, 0x0338, 0x1, 0), MX7ULP_PAD_PTC14__PTC14 = IOMUX_PAD(0x0038, 0x0038, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC14__FXIO1_D10 = IOMUX_PAD(0x0038, 0x0038, 0x2, 0x022C, 0x1, 0), MX7ULP_PAD_PTC14__LPSPI3_PCS3 = IOMUX_PAD(0x0038, 0x0038, 0x3, 0x031C, 0x1, 0), @@ -537,122 +529,107 @@ enum { MX7ULP_PAD_PTC14__TPM7_CH0 = IOMUX_PAD(0x0038, 0x0038, 0x6, 0x02DC, 0x1, 0), MX7ULP_PAD_PTC14__FB_AD14 = IOMUX_PAD(0x0038, 0x0038, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC14__TRACE_D1 = IOMUX_PAD(0x0038, 0x0038, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC14__DEBUG_MUX14 = IOMUX_PAD(0x0038, 0x0038, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC15__PTC15 = IOMUX_PAD(0x003C, 0x003C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC15__FXIO1_D11 = IOMUX_PAD(0x003C, 0x003C, 0x2, 0x0230, 0x1, 0), MX7ULP_PAD_PTC15__LPUART7_RX = IOMUX_PAD(0x003C, 0x003C, 0x4, 0x026C, 0x1, 0), MX7ULP_PAD_PTC15__TPM7_CH1 = IOMUX_PAD(0x003C, 0x003C, 0x6, 0x02E0, 0x1, 0), MX7ULP_PAD_PTC15__FB_AD15 = IOMUX_PAD(0x003C, 0x003C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC15__TRACE_D0 = IOMUX_PAD(0x003C, 0x003C, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC15__DEBUG_MUX15 = IOMUX_PAD(0x003C, 0x003C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTC16__PTC16 = IOMUX_PAD(0x0040, 0x0040, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC16__FXIO1_D12 = IOMUX_PAD(0x0040, 0x0040, 0x2, 0x0234, 0x1, 0), MX7ULP_PAD_PTC16__LPSPI3_SIN = IOMUX_PAD(0x0040, 0x0040, 0x3, 0x0324, 0x1, 0), MX7ULP_PAD_PTC16__TPM7_CH2 = IOMUX_PAD(0x0040, 0x0040, 0x6, 0x02E4, 0x1, 0), - MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_b_FB_TS_b = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC16__FB_ALE_FB_CS1_B_FB_TS_B = IOMUX_PAD(0x0040, 0x0040, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC16__TRACE_CLKOUT = IOMUX_PAD(0x0040, 0x0040, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC16__USB1_ULPI_OC2 = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0), + MX7ULP_PAD_PTC16__USB1_OC2 = IOMUX_PAD(0x0040, 0x0040, 0xb, 0x0334, 0x1, 0), MX7ULP_PAD_PTC17__PTC17 = IOMUX_PAD(0x0044, 0x0044, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC17__FXIO1_D13 = IOMUX_PAD(0x0044, 0x0044, 0x2, 0x0238, 0x1, 0), MX7ULP_PAD_PTC17__LPSPI3_SOUT = IOMUX_PAD(0x0044, 0x0044, 0x3, 0x0328, 0x1, 0), MX7ULP_PAD_PTC17__TPM6_CLKIN = IOMUX_PAD(0x0044, 0x0044, 0x6, 0x02D8, 0x1, 0), - MX7ULP_PAD_PTC17__FB_CS0_b = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC17__DEBUG_MUX16 = IOMUX_PAD(0x0044, 0x0044, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC17__FB_CS0_B = IOMUX_PAD(0x0044, 0x0044, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTC18__PTC18 = IOMUX_PAD(0x0048, 0x0048, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC18__FXIO1_D14 = IOMUX_PAD(0x0048, 0x0048, 0x2, 0x023C, 0x1, 0), MX7ULP_PAD_PTC18__LPSPI3_SCK = IOMUX_PAD(0x0048, 0x0048, 0x3, 0x0320, 0x1, 0), MX7ULP_PAD_PTC18__TPM6_CH0 = IOMUX_PAD(0x0048, 0x0048, 0x6, 0x02D0, 0x1, 0), - MX7ULP_PAD_PTC18__FB_OE_b = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC18__DEBUG_MUX17 = IOMUX_PAD(0x0048, 0x0048, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__FB_OE_B = IOMUX_PAD(0x0048, 0x0048, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC18__USB0_ID = IOMUX_PAD(0x0048, 0x0048, 0xb, 0x0338, 0x2, 0), + MX7ULP_PAD_PTC18__VIU_DE = IOMUX_PAD(0x0048, 0x0048, 0xc, 0x033c, 0x1, 0), MX7ULP_PAD_PTC19__PTC19 = IOMUX_PAD(0x004C, 0x004C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTC19__FXIO1_D15 = IOMUX_PAD(0x004C, 0x004C, 0x2, 0x0240, 0x1, 0), MX7ULP_PAD_PTC19__LPSPI3_PCS0 = IOMUX_PAD(0x004C, 0x004C, 0x3, 0x0310, 0x1, 0), MX7ULP_PAD_PTC19__TPM6_CH1 = IOMUX_PAD(0x004C, 0x004C, 0x6, 0x02D4, 0x1, 0), MX7ULP_PAD_PTC19__FB_A16 = IOMUX_PAD(0x004C, 0x004C, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTC19__USB1_ULPI_PWR2 = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__USB0_ID = IOMUX_PAD(0x004C, 0x004C, 0xa, 0x0338, 0x3, 0), + MX7ULP_PAD_PTC19__USB1_PWR2 = IOMUX_PAD(0x004C, 0x004C, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTC19__VIU_DE = IOMUX_PAD(0x004C, 0x004C, 0xc, 0x033c, 0x3, 0), MX7ULP_PAD_PTD0__PTD0 = IOMUX_PAD(0x0080, 0x0080, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD0__SDHC0_RESET_b = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD0__DEBUG_MUX18 = IOMUX_PAD(0x0080, 0x0080, 0xe, 0x0000, 0x0, 0), + MX7ULP_PAD_PTD0__SDHC0_RESET_B = IOMUX_PAD(0x0080, 0x0080, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTD1__PTD1 = IOMUX_PAD(0x0084, 0x0084, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD1__SDHC0_CMD = IOMUX_PAD(0x0084, 0x0084, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD1__DEBUG_MUX19 = IOMUX_PAD(0x0084, 0x0084, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD2__PTD2 = IOMUX_PAD(0x0088, 0x0088, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD2__SDHC0_CLK = IOMUX_PAD(0x0088, 0x0088, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD2__DEBUG_MUX20 = IOMUX_PAD(0x0088, 0x0088, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD3__PTD3 = IOMUX_PAD(0x008C, 0x008C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD3__SDHC0_D7 = IOMUX_PAD(0x008C, 0x008C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD3__DEBUG_MUX21 = IOMUX_PAD(0x008C, 0x008C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD4__PTD4 = IOMUX_PAD(0x0090, 0x0090, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD4__SDHC0_D6 = IOMUX_PAD(0x0090, 0x0090, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD4__DEBUG_MUX22 = IOMUX_PAD(0x0090, 0x0090, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD5__PTD5 = IOMUX_PAD(0x0094, 0x0094, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD5__SDHC0_D5 = IOMUX_PAD(0x0094, 0x0094, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD5__DEBUG_MUX23 = IOMUX_PAD(0x0094, 0x0094, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD6__PTD6 = IOMUX_PAD(0x0098, 0x0098, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD6__SDHC0_D4 = IOMUX_PAD(0x0098, 0x0098, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD6__DEBUG_MUX24 = IOMUX_PAD(0x0098, 0x0098, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD7__PTD7 = IOMUX_PAD(0x009C, 0x009C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD7__SDHC0_D3 = IOMUX_PAD(0x009C, 0x009C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD7__DEBUG_MUX25 = IOMUX_PAD(0x009C, 0x009C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD8__PTD8 = IOMUX_PAD(0x00A0, 0x00A0, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD8__TPM4_CLKIN = IOMUX_PAD(0x00A0, 0x00A0, 0x6, 0x0298, 0x2, 0), MX7ULP_PAD_PTD8__SDHC0_D2 = IOMUX_PAD(0x00A0, 0x00A0, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD8__DEBUG_MUX26 = IOMUX_PAD(0x00A0, 0x00A0, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD9__PTD9 = IOMUX_PAD(0x00A4, 0x00A4, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD9__TPM4_CH0 = IOMUX_PAD(0x00A4, 0x00A4, 0x6, 0x0280, 0x2, 0), MX7ULP_PAD_PTD9__SDHC0_D1 = IOMUX_PAD(0x00A4, 0x00A4, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD9__DEBUG_MUX27 = IOMUX_PAD(0x00A4, 0x00A4, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD10__PTD10 = IOMUX_PAD(0x00A8, 0x00A8, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD10__TPM4_CH1 = IOMUX_PAD(0x00A8, 0x00A8, 0x6, 0x0284, 0x2, 0), MX7ULP_PAD_PTD10__SDHC0_D0 = IOMUX_PAD(0x00A8, 0x00A8, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD10__DEBUG_MUX28 = IOMUX_PAD(0x00A8, 0x00A8, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTD11__PTD11 = IOMUX_PAD(0x00AC, 0x00AC, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTD11__TPM4_CH2 = IOMUX_PAD(0x00AC, 0x00AC, 0x6, 0x0288, 0x2, 0), MX7ULP_PAD_PTD11__SDHC0_DQS = IOMUX_PAD(0x00AC, 0x00AC, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTD11__DEBUG_MUX29 = IOMUX_PAD(0x00AC, 0x00AC, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE0__PTE0 = IOMUX_PAD(0x0100, 0x0100, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE0__FXIO1_D31 = IOMUX_PAD(0x0100, 0x0100, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE0__LPSPI2_PCS1 = IOMUX_PAD(0x0100, 0x0100, 0x3, 0x02A0, 0x2, 0), - MX7ULP_PAD_PTE0__LPUART4_CTS_b = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0), + MX7ULP_PAD_PTE0__LPUART4_CTS_B = IOMUX_PAD(0x0100, 0x0100, 0x4, 0x0244, 0x2, 0), MX7ULP_PAD_PTE0__LPI2C4_SCL = IOMUX_PAD(0x0100, 0x0100, 0x5, 0x0278, 0x2, 0), MX7ULP_PAD_PTE0__SDHC1_D1 = IOMUX_PAD(0x0100, 0x0100, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTE0__FB_A25 = IOMUX_PAD(0x0100, 0x0100, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE0__DEBUG_MUX30 = IOMUX_PAD(0x0100, 0x0100, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__PTE1 = IOMUX_PAD(0x0104, 0x0104, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__FXIO1_D30 = IOMUX_PAD(0x0104, 0x0104, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__LPSPI2_PCS2 = IOMUX_PAD(0x0104, 0x0104, 0x3, 0x02A4, 0x2, 0), - MX7ULP_PAD_PTE1__LPUART4_RTS_b = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE1__LPUART4_RTS_B = IOMUX_PAD(0x0104, 0x0104, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__LPI2C4_SDA = IOMUX_PAD(0x0104, 0x0104, 0x5, 0x027C, 0x2, 0), MX7ULP_PAD_PTE1__SDHC1_D0 = IOMUX_PAD(0x0104, 0x0104, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTE1__FB_A26 = IOMUX_PAD(0x0104, 0x0104, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE1__DEBUG_MUX31 = IOMUX_PAD(0x0104, 0x0104, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE2__PTE2 = IOMUX_PAD(0x0108, 0x0108, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE2__FXIO1_D29 = IOMUX_PAD(0x0108, 0x0108, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE2__LPSPI2_PCS3 = IOMUX_PAD(0x0108, 0x0108, 0x3, 0x02A8, 0x2, 0), MX7ULP_PAD_PTE2__LPUART4_TX = IOMUX_PAD(0x0108, 0x0108, 0x4, 0x024C, 0x2, 0), MX7ULP_PAD_PTE2__LPI2C4_HREQ = IOMUX_PAD(0x0108, 0x0108, 0x5, 0x0274, 0x2, 0), MX7ULP_PAD_PTE2__SDHC1_CLK = IOMUX_PAD(0x0108, 0x0108, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE2__DEBUG_MUX32 = IOMUX_PAD(0x0108, 0x0108, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE3__PTE3 = IOMUX_PAD(0x010C, 0x010C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE3__FXIO1_D28 = IOMUX_PAD(0x010C, 0x010C, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE3__LPUART4_RX = IOMUX_PAD(0x010C, 0x010C, 0x4, 0x0248, 0x2, 0), MX7ULP_PAD_PTE3__TPM5_CH1 = IOMUX_PAD(0x010C, 0x010C, 0x6, 0x02C8, 0x2, 0), MX7ULP_PAD_PTE3__SDHC1_CMD = IOMUX_PAD(0x010C, 0x010C, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE3__DEBUG_MUX33 = IOMUX_PAD(0x010C, 0x010C, 0xe, 0x0000, 0x0, 0), MX7ULP_PAD_PTE4__PTE4 = IOMUX_PAD(0x0110, 0x0110, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE4__FXIO1_D27 = IOMUX_PAD(0x0110, 0x0110, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE4__LPSPI2_SIN = IOMUX_PAD(0x0110, 0x0110, 0x3, 0x02B0, 0x2, 0), - MX7ULP_PAD_PTE4__LPUART5_CTS_b = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0), + MX7ULP_PAD_PTE4__LPUART5_CTS_B = IOMUX_PAD(0x0110, 0x0110, 0x4, 0x0250, 0x2, 0), MX7ULP_PAD_PTE4__LPI2C5_SCL = IOMUX_PAD(0x0110, 0x0110, 0x5, 0x02BC, 0x2, 0), MX7ULP_PAD_PTE4__TPM5_CLKIN = IOMUX_PAD(0x0110, 0x0110, 0x6, 0x02CC, 0x2, 0), MX7ULP_PAD_PTE4__SDHC1_D3 = IOMUX_PAD(0x0110, 0x0110, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTE5__PTE5 = IOMUX_PAD(0x0114, 0x0114, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE5__FXIO1_D26 = IOMUX_PAD(0x0114, 0x0114, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE5__LPSPI2_SOUT = IOMUX_PAD(0x0114, 0x0114, 0x3, 0x02B4, 0x2, 0), - MX7ULP_PAD_PTE5__LPUART5_RTS_b = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__LPUART5_RTS_B = IOMUX_PAD(0x0114, 0x0114, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTE5__LPI2C5_SDA = IOMUX_PAD(0x0114, 0x0114, 0x5, 0x02C0, 0x2, 0), MX7ULP_PAD_PTE5__TPM5_CH0 = IOMUX_PAD(0x0114, 0x0114, 0x6, 0x02C4, 0x2, 0), MX7ULP_PAD_PTE5__SDHC1_D2 = IOMUX_PAD(0x0114, 0x0114, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE5__VIU_DE = IOMUX_PAD(0x0114, 0x0114, 0xc, 0x033c, 0x2, 0), MX7ULP_PAD_PTE6__PTE6 = IOMUX_PAD(0x0118, 0x0118, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE6__FXIO1_D25 = IOMUX_PAD(0x0118, 0x0118, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE6__LPSPI2_SCK = IOMUX_PAD(0x0118, 0x0118, 0x3, 0x02AC, 0x2, 0), @@ -677,23 +654,23 @@ enum { MX7ULP_PAD_PTE8__VIU_D16 = IOMUX_PAD(0x0120, 0x0120, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTE8__FXIO1_D23 = IOMUX_PAD(0x0120, 0x0120, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE8__LPSPI3_PCS1 = IOMUX_PAD(0x0120, 0x0120, 0x3, 0x0314, 0x2, 0), - MX7ULP_PAD_PTE8__LPUART6_CTS_b = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0), + MX7ULP_PAD_PTE8__LPUART6_CTS_B = IOMUX_PAD(0x0120, 0x0120, 0x4, 0x025C, 0x2, 0), MX7ULP_PAD_PTE8__LPI2C6_SCL = IOMUX_PAD(0x0120, 0x0120, 0x5, 0x02FC, 0x2, 0), MX7ULP_PAD_PTE8__TPM7_CH5 = IOMUX_PAD(0x0120, 0x0120, 0x6, 0x02F0, 0x2, 0), MX7ULP_PAD_PTE8__SDHC1_WP = IOMUX_PAD(0x0120, 0x0120, 0x7, 0x0200, 0x1, 0), MX7ULP_PAD_PTE8__SDHC1_D6 = IOMUX_PAD(0x0120, 0x0120, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE8__FB_CS3_b_FB_BE7_0_BLS31_24_b = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE8__FB_CS3_B_FB_BE7_0_BLS31_24_B = IOMUX_PAD(0x0120, 0x0120, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__PTE9 = IOMUX_PAD(0x0124, 0x0124, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__TRACE_D5 = IOMUX_PAD(0x0124, 0x0124, 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__VIU_D17 = IOMUX_PAD(0x0124, 0x0124, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__FXIO1_D22 = IOMUX_PAD(0x0124, 0x0124, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__LPSPI3_PCS2 = IOMUX_PAD(0x0124, 0x0124, 0x3, 0x0318, 0x2, 0), - MX7ULP_PAD_PTE9__LPUART6_RTS_b = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__LPUART6_RTS_B = IOMUX_PAD(0x0124, 0x0124, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTE9__LPI2C6_SDA = IOMUX_PAD(0x0124, 0x0124, 0x5, 0x0300, 0x2, 0), MX7ULP_PAD_PTE9__TPM7_CLKIN = IOMUX_PAD(0x0124, 0x0124, 0x6, 0x02F4, 0x2, 0), MX7ULP_PAD_PTE9__SDHC1_CD = IOMUX_PAD(0x0124, 0x0124, 0x7, 0x032C, 0x1, 0), MX7ULP_PAD_PTE9__SDHC1_D7 = IOMUX_PAD(0x0124, 0x0124, 0x8, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE9__FB_TBST_b_FB_CS2_b_FB_BE15_8_BLS23_16_b = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE9__FB_TBST_B_FB_CS2_B_FB_BE15_8_BLS23_16_B = IOMUX_PAD(0x0124, 0x0124, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE10__PTE10 = IOMUX_PAD(0x0128, 0x0128, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE10__TRACE_D4 = IOMUX_PAD(0x0128, 0x0128, 0xa, 0x0000, 0x0, 0), MX7ULP_PAD_PTE10__VIU_D18 = IOMUX_PAD(0x0128, 0x0128, 0xc, 0x0000, 0x0, 0), @@ -711,29 +688,29 @@ enum { MX7ULP_PAD_PTE11__FXIO1_D20 = IOMUX_PAD(0x012C, 0x012C, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE11__LPUART6_RX = IOMUX_PAD(0x012C, 0x012C, 0x4, 0x0260, 0x2, 0), MX7ULP_PAD_PTE11__TPM7_CH1 = IOMUX_PAD(0x012C, 0x012C, 0x6, 0x02E0, 0x2, 0), - MX7ULP_PAD_PTE11__SDHC1_RESET_b = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE11__SDHC1_RESET_B = IOMUX_PAD(0x012C, 0x012C, 0x8, 0x0000, 0x0, 0), MX7ULP_PAD_PTE11__FB_A20 = IOMUX_PAD(0x012C, 0x012C, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE12__PTE12 = IOMUX_PAD(0x0130, 0x0130, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE12__FXIO1_D19 = IOMUX_PAD(0x0130, 0x0130, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE12__LPSPI3_SIN = IOMUX_PAD(0x0130, 0x0130, 0x3, 0x0324, 0x2, 0), - MX7ULP_PAD_PTE12__LPUART7_CTS_b = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0), + MX7ULP_PAD_PTE12__LPUART7_CTS_B = IOMUX_PAD(0x0130, 0x0130, 0x4, 0x0268, 0x2, 0), MX7ULP_PAD_PTE12__LPI2C7_SCL = IOMUX_PAD(0x0130, 0x0130, 0x5, 0x0308, 0x2, 0), MX7ULP_PAD_PTE12__TPM7_CH2 = IOMUX_PAD(0x0130, 0x0130, 0x6, 0x02E4, 0x2, 0), MX7ULP_PAD_PTE12__SDHC1_WP = IOMUX_PAD(0x0130, 0x0130, 0x8, 0x0200, 0x2, 0), MX7ULP_PAD_PTE12__FB_A21 = IOMUX_PAD(0x0130, 0x0130, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE12__TRACE_D2 = IOMUX_PAD(0x0130, 0x0130, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE12__USB1_ULPI_OC2 = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0), + MX7ULP_PAD_PTE12__USB1_OC2 = IOMUX_PAD(0x0130, 0x0130, 0xb, 0x0334, 0x2, 0), MX7ULP_PAD_PTE12__VIU_D20 = IOMUX_PAD(0x0130, 0x0130, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__PTE13 = IOMUX_PAD(0x0134, 0x0134, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__FXIO1_D18 = IOMUX_PAD(0x0134, 0x0134, 0x2, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__LPSPI3_SOUT = IOMUX_PAD(0x0134, 0x0134, 0x3, 0x0328, 0x2, 0), - MX7ULP_PAD_PTE13__LPUART7_RTS_b = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__LPUART7_RTS_B = IOMUX_PAD(0x0134, 0x0134, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__LPI2C7_SDA = IOMUX_PAD(0x0134, 0x0134, 0x5, 0x030C, 0x2, 0), MX7ULP_PAD_PTE13__TPM6_CLKIN = IOMUX_PAD(0x0134, 0x0134, 0x6, 0x02D8, 0x2, 0), MX7ULP_PAD_PTE13__SDHC1_CD = IOMUX_PAD(0x0134, 0x0134, 0x8, 0x032C, 0x2, 0), MX7ULP_PAD_PTE13__FB_A22 = IOMUX_PAD(0x0134, 0x0134, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__TRACE_D1 = IOMUX_PAD(0x0134, 0x0134, 0xa, 0x0000, 0x0, 0), - MX7ULP_PAD_PTE13__USB1_ULPI_PWR2 = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTE13__USB1_PWR2 = IOMUX_PAD(0x0134, 0x0134, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTE13__VIU_D21 = IOMUX_PAD(0x0134, 0x0134, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTE14__PTE14 = IOMUX_PAD(0x0138, 0x0138, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTE14__FXIO1_D17 = IOMUX_PAD(0x0138, 0x0138, 0x2, 0x0000, 0x0, 0), @@ -756,13 +733,13 @@ enum { MX7ULP_PAD_PTE15__USB0_PWR = IOMUX_PAD(0x013C, 0x013C, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTE15__VIU_D23 = IOMUX_PAD(0x013C, 0x013C, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF0__PTF0 = IOMUX_PAD(0x0180, 0x0180, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF0__LPUART4_CTS_b = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0), + MX7ULP_PAD_PTF0__LPUART4_CTS_B = IOMUX_PAD(0x0180, 0x0180, 0x4, 0x0244, 0x3, 0), MX7ULP_PAD_PTF0__LPI2C4_SCL = IOMUX_PAD(0x0180, 0x0180, 0x5, 0x0278, 0x3, 0), MX7ULP_PAD_PTF0__TPM4_CLKIN = IOMUX_PAD(0x0180, 0x0180, 0x6, 0x0298, 0x3, 0), - MX7ULP_PAD_PTF0__FB_RW_b = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF0__VIU_DE = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF0__FB_RW_B = IOMUX_PAD(0x0180, 0x0180, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF0__VIU_DE = IOMUX_PAD(0x0180, 0x0180, 0xc, 0x033C, 0x0, 0), MX7ULP_PAD_PTF1__PTF1 = IOMUX_PAD(0x0184, 0x0184, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF1__LPUART4_RTS_b = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF1__LPUART4_RTS_B = IOMUX_PAD(0x0184, 0x0184, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTF1__LPI2C4_SDA = IOMUX_PAD(0x0184, 0x0184, 0x5, 0x027C, 0x3, 0), MX7ULP_PAD_PTF1__TPM4_CH0 = IOMUX_PAD(0x0184, 0x0184, 0x6, 0x0280, 0x3, 0), MX7ULP_PAD_PTF1__CLKOUT = IOMUX_PAD(0x0184, 0x0184, 0x9, 0x0000, 0x0, 0), @@ -771,7 +748,7 @@ enum { MX7ULP_PAD_PTF2__LPUART4_TX = IOMUX_PAD(0x0188, 0x0188, 0x4, 0x024C, 0x3, 0), MX7ULP_PAD_PTF2__LPI2C4_HREQ = IOMUX_PAD(0x0188, 0x0188, 0x5, 0x0274, 0x3, 0), MX7ULP_PAD_PTF2__TPM4_CH1 = IOMUX_PAD(0x0188, 0x0188, 0x6, 0x0284, 0x3, 0), - MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_b_FB_BE23_16_BLS15_8_b = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF2__FB_TSIZ1_FB_CS5_B_FB_BE23_16_BLS15_8_B = IOMUX_PAD(0x0188, 0x0188, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTF2__VIU_VSYNC = IOMUX_PAD(0x0188, 0x0188, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF3__PTF3 = IOMUX_PAD(0x018C, 0x018C, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF3__LPUART4_RX = IOMUX_PAD(0x018C, 0x018C, 0x4, 0x0248, 0x3, 0), @@ -781,7 +758,7 @@ enum { MX7ULP_PAD_PTF4__PTF4 = IOMUX_PAD(0x0190, 0x0190, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF4__FXIO1_D0 = IOMUX_PAD(0x0190, 0x0190, 0x2, 0x0204, 0x2, 0), MX7ULP_PAD_PTF4__LPSPI2_PCS1 = IOMUX_PAD(0x0190, 0x0190, 0x3, 0x02A0, 0x3, 0), - MX7ULP_PAD_PTF4__LPUART5_CTS_b = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0), + MX7ULP_PAD_PTF4__LPUART5_CTS_B = IOMUX_PAD(0x0190, 0x0190, 0x4, 0x0250, 0x3, 0), MX7ULP_PAD_PTF4__LPI2C5_SCL = IOMUX_PAD(0x0190, 0x0190, 0x5, 0x02BC, 0x3, 0), MX7ULP_PAD_PTF4__TPM4_CH3 = IOMUX_PAD(0x0190, 0x0190, 0x6, 0x028C, 0x2, 0), MX7ULP_PAD_PTF4__FB_AD17 = IOMUX_PAD(0x0190, 0x0190, 0x9, 0x0000, 0x0, 0), @@ -789,7 +766,7 @@ enum { MX7ULP_PAD_PTF5__PTF5 = IOMUX_PAD(0x0194, 0x0194, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF5__FXIO1_D1 = IOMUX_PAD(0x0194, 0x0194, 0x2, 0x0208, 0x2, 0), MX7ULP_PAD_PTF5__LPSPI2_PCS2 = IOMUX_PAD(0x0194, 0x0194, 0x3, 0x02A4, 0x3, 0), - MX7ULP_PAD_PTF5__LPUART5_RTS_b = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF5__LPUART5_RTS_B = IOMUX_PAD(0x0194, 0x0194, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTF5__LPI2C5_SDA = IOMUX_PAD(0x0194, 0x0194, 0x5, 0x02C0, 0x3, 0), MX7ULP_PAD_PTF5__TPM4_CH4 = IOMUX_PAD(0x0194, 0x0194, 0x6, 0x0290, 0x2, 0), MX7ULP_PAD_PTF5__FB_AD18 = IOMUX_PAD(0x0194, 0x0194, 0x9, 0x0000, 0x0, 0), @@ -811,20 +788,20 @@ enum { MX7ULP_PAD_PTF8__PTF8 = IOMUX_PAD(0x01A0, 0x01A0, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF8__FXIO1_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0x2, 0x0214, 0x2, 0), MX7ULP_PAD_PTF8__LPSPI2_SIN = IOMUX_PAD(0x01A0, 0x01A0, 0x3, 0x02B0, 0x3, 0), - MX7ULP_PAD_PTF8__LPUART6_CTS_b = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0), + MX7ULP_PAD_PTF8__LPUART6_CTS_B = IOMUX_PAD(0x01A0, 0x01A0, 0x4, 0x025C, 0x3, 0), MX7ULP_PAD_PTF8__LPI2C6_SCL = IOMUX_PAD(0x01A0, 0x01A0, 0x5, 0x02FC, 0x3, 0), MX7ULP_PAD_PTF8__TPM5_CLKIN = IOMUX_PAD(0x01A0, 0x01A0, 0x6, 0x02CC, 0x3, 0), MX7ULP_PAD_PTF8__FB_AD21 = IOMUX_PAD(0x01A0, 0x01A0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF8__USB1_ULPI_CLK = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF8__USB1_CLK = IOMUX_PAD(0x01A0, 0x01A0, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF8__VIU_D4 = IOMUX_PAD(0x01A0, 0x01A0, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF9__PTF9 = IOMUX_PAD(0x01A4, 0x01A4, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF9__FXIO1_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0x2, 0x0218, 0x2, 0), MX7ULP_PAD_PTF9__LPSPI2_SOUT = IOMUX_PAD(0x01A4, 0x01A4, 0x3, 0x02B4, 0x3, 0), - MX7ULP_PAD_PTF9__LPUART6_RTS_b = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__LPUART6_RTS_B = IOMUX_PAD(0x01A4, 0x01A4, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTF9__LPI2C6_SDA = IOMUX_PAD(0x01A4, 0x01A4, 0x5, 0x0300, 0x3, 0), MX7ULP_PAD_PTF9__TPM5_CH0 = IOMUX_PAD(0x01A4, 0x01A4, 0x6, 0x02C4, 0x3, 0), MX7ULP_PAD_PTF9__FB_AD22 = IOMUX_PAD(0x01A4, 0x01A4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF9__USB1_ULPI_NXT = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF9__USB1_NXT = IOMUX_PAD(0x01A4, 0x01A4, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF9__VIU_D5 = IOMUX_PAD(0x01A4, 0x01A4, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF10__PTF10 = IOMUX_PAD(0x01A8, 0x01A8, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF10__FXIO1_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0x2, 0x021C, 0x2, 0), @@ -833,33 +810,33 @@ enum { MX7ULP_PAD_PTF10__LPI2C6_HREQ = IOMUX_PAD(0x01A8, 0x01A8, 0x5, 0x02F8, 0x3, 0), MX7ULP_PAD_PTF10__TPM7_CH3 = IOMUX_PAD(0x01A8, 0x01A8, 0x6, 0x02E8, 0x3, 0), MX7ULP_PAD_PTF10__FB_AD23 = IOMUX_PAD(0x01A8, 0x01A8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF10__USB1_ULPI_STP = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF10__USB1_STP = IOMUX_PAD(0x01A8, 0x01A8, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF10__VIU_D6 = IOMUX_PAD(0x01A8, 0x01A8, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF11__PTF11 = IOMUX_PAD(0x01AC, 0x01AC, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF11__FXIO1_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0x2, 0x0220, 0x2, 0), MX7ULP_PAD_PTF11__LPSPI2_PCS0 = IOMUX_PAD(0x01AC, 0x01AC, 0x3, 0x029C, 0x3, 0), MX7ULP_PAD_PTF11__LPUART6_RX = IOMUX_PAD(0x01AC, 0x01AC, 0x4, 0x0260, 0x3, 0), MX7ULP_PAD_PTF11__TPM7_CH4 = IOMUX_PAD(0x01AC, 0x01AC, 0x6, 0x02EC, 0x3, 0), - MX7ULP_PAD_PTF11__FB_CS4_b_FB_TSIZ0_FB_BE31_24_BLS7_0_b = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF11__USB1_ULPI_DIR = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__FB_CS4_B_FB_TSIZ0_FB_BE31_24_BLS7_0_B = IOMUX_PAD(0x01AC, 0x01AC, 0x9, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF11__USB1_DIR = IOMUX_PAD(0x01AC, 0x01AC, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF11__VIU_D7 = IOMUX_PAD(0x01AC, 0x01AC, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF12__PTF12 = IOMUX_PAD(0x01B0, 0x01B0, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF12__FXIO1_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0x2, 0x0224, 0x2, 0), MX7ULP_PAD_PTF12__LPSPI3_PCS1 = IOMUX_PAD(0x01B0, 0x01B0, 0x3, 0x0314, 0x3, 0), - MX7ULP_PAD_PTF12__LPUART7_CTS_b = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0), + MX7ULP_PAD_PTF12__LPUART7_CTS_B = IOMUX_PAD(0x01B0, 0x01B0, 0x4, 0x0268, 0x3, 0), MX7ULP_PAD_PTF12__LPI2C7_SCL = IOMUX_PAD(0x01B0, 0x01B0, 0x5, 0x0308, 0x3, 0), MX7ULP_PAD_PTF12__TPM7_CH5 = IOMUX_PAD(0x01B0, 0x01B0, 0x6, 0x02F0, 0x3, 0), MX7ULP_PAD_PTF12__FB_AD24 = IOMUX_PAD(0x01B0, 0x01B0, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF12__USB1_ULPI_DATA0 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF12__USB1_DATA0 = IOMUX_PAD(0x01B0, 0x01B0, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF12__VIU_D8 = IOMUX_PAD(0x01B0, 0x01B0, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF13__PTF13 = IOMUX_PAD(0x01B4, 0x01B4, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF13__FXIO1_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0x2, 0x0228, 0x2, 0), MX7ULP_PAD_PTF13__LPSPI3_PCS2 = IOMUX_PAD(0x01B4, 0x01B4, 0x3, 0x0318, 0x3, 0), - MX7ULP_PAD_PTF13__LPUART7_RTS_b = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__LPUART7_RTS_B = IOMUX_PAD(0x01B4, 0x01B4, 0x4, 0x0000, 0x0, 0), MX7ULP_PAD_PTF13__LPI2C7_SDA = IOMUX_PAD(0x01B4, 0x01B4, 0x5, 0x030C, 0x3, 0), MX7ULP_PAD_PTF13__TPM7_CLKIN = IOMUX_PAD(0x01B4, 0x01B4, 0x6, 0x02F4, 0x3, 0), MX7ULP_PAD_PTF13__FB_AD25 = IOMUX_PAD(0x01B4, 0x01B4, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF13__USB1_ULPI_DATA1 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF13__USB1_DATA1 = IOMUX_PAD(0x01B4, 0x01B4, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF13__VIU_D9 = IOMUX_PAD(0x01B4, 0x01B4, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF14__PTF14 = IOMUX_PAD(0x01B8, 0x01B8, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF14__FXIO1_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0x2, 0x022C, 0x2, 0), @@ -868,38 +845,38 @@ enum { MX7ULP_PAD_PTF14__LPI2C7_HREQ = IOMUX_PAD(0x01B8, 0x01B8, 0x5, 0x0304, 0x3, 0), MX7ULP_PAD_PTF14__TPM7_CH0 = IOMUX_PAD(0x01B8, 0x01B8, 0x6, 0x02DC, 0x3, 0), MX7ULP_PAD_PTF14__FB_AD26 = IOMUX_PAD(0x01B8, 0x01B8, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF14__USB1_ULPI_DATA2 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF14__USB1_DATA2 = IOMUX_PAD(0x01B8, 0x01B8, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF14__VIU_D10 = IOMUX_PAD(0x01B8, 0x01B8, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF15__PTF15 = IOMUX_PAD(0x01BC, 0x01BC, 0x1, 0x0000, 0x0, 0), MX7ULP_PAD_PTF15__FXIO1_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0x2, 0x0230, 0x2, 0), MX7ULP_PAD_PTF15__LPUART7_RX = IOMUX_PAD(0x01BC, 0x01BC, 0x4, 0x026C, 0x3, 0), MX7ULP_PAD_PTF15__TPM7_CH1 = IOMUX_PAD(0x01BC, 0x01BC, 0x6, 0x02E0, 0x3, 0), MX7ULP_PAD_PTF15__FB_AD27 = IOMUX_PAD(0x01BC, 0x01BC, 0x9, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF15__USB1_ULPI_DATA3 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF15__USB1_DATA3 = IOMUX_PAD(0x01BC, 0x01BC, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF15__VIU_D11 = IOMUX_PAD(0x01BC, 0x01BC, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF16__PTF16 = IOMUX_PAD(0x01C0, 0x01C0, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF16__USB1_ULPI_DATA4 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF16__USB1_DATA4 = IOMUX_PAD(0x01C0, 0x01C0, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF16__VIU_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF16__FXIO1_D12 = IOMUX_PAD(0x01C0, 0x01C0, 0x2, 0x0234, 0x2, 0), MX7ULP_PAD_PTF16__LPSPI3_SIN = IOMUX_PAD(0x01C0, 0x01C0, 0x3, 0x0324, 0x3, 0), MX7ULP_PAD_PTF16__TPM7_CH2 = IOMUX_PAD(0x01C0, 0x01C0, 0x6, 0x02E4, 0x3, 0), MX7ULP_PAD_PTF16__FB_AD28 = IOMUX_PAD(0x01C0, 0x01C0, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTF17__PTF17 = IOMUX_PAD(0x01C4, 0x01C4, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF17__USB1_ULPI_DATA5 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF17__USB1_DATA5 = IOMUX_PAD(0x01C4, 0x01C4, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF17__VIU_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF17__FXIO1_D13 = IOMUX_PAD(0x01C4, 0x01C4, 0x2, 0x0238, 0x2, 0), MX7ULP_PAD_PTF17__LPSPI3_SOUT = IOMUX_PAD(0x01C4, 0x01C4, 0x3, 0x0328, 0x3, 0), MX7ULP_PAD_PTF17__TPM6_CLKIN = IOMUX_PAD(0x01C4, 0x01C4, 0x6, 0x02D8, 0x3, 0), MX7ULP_PAD_PTF17__FB_AD29 = IOMUX_PAD(0x01C4, 0x01C4, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTF18__PTF18 = IOMUX_PAD(0x01C8, 0x01C8, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF18__USB1_ULPI_DATA6 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF18__USB1_DATA6 = IOMUX_PAD(0x01C8, 0x01C8, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF18__VIU_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF18__FXIO1_D14 = IOMUX_PAD(0x01C8, 0x01C8, 0x2, 0x023C, 0x2, 0), MX7ULP_PAD_PTF18__LPSPI3_SCK = IOMUX_PAD(0x01C8, 0x01C8, 0x3, 0x0320, 0x3, 0), MX7ULP_PAD_PTF18__TPM6_CH0 = IOMUX_PAD(0x01C8, 0x01C8, 0x6, 0x02D0, 0x3, 0), MX7ULP_PAD_PTF18__FB_AD30 = IOMUX_PAD(0x01C8, 0x01C8, 0x9, 0x0000, 0x0, 0), MX7ULP_PAD_PTF19__PTF19 = IOMUX_PAD(0x01CC, 0x01CC, 0x1, 0x0000, 0x0, 0), - MX7ULP_PAD_PTF19__USB1_ULPI_DATA7 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0), + MX7ULP_PAD_PTF19__USB1_DATA7 = IOMUX_PAD(0x01CC, 0x01CC, 0xb, 0x0000, 0x0, 0), MX7ULP_PAD_PTF19__VIU_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0xc, 0x0000, 0x0, 0), MX7ULP_PAD_PTF19__FXIO1_D15 = IOMUX_PAD(0x01CC, 0x01CC, 0x2, 0x0240, 0x2, 0), MX7ULP_PAD_PTF19__LPSPI3_PCS0 = IOMUX_PAD(0x01CC, 0x01CC, 0x3, 0x0310, 0x3, 0), diff --git a/arch/arm/include/asm/arch-mx7ulp/scg.h b/arch/arm/include/asm/arch-mx7ulp/scg.h index 3b5b7f6803c..59cb92473ab 100644 --- a/arch/arm/include/asm/arch-mx7ulp/scg.h +++ b/arch/arm/include/asm/arch-mx7ulp/scg.h @@ -323,6 +323,7 @@ typedef struct scg_regs { u32 scg_clk_get_rate(enum scg_clk clk); int scg_enable_pll_pfd(enum scg_clk clk, u32 frac); +int scg_disable_pll_pfd(enum scg_clk clk); int scg_enable_usb_pll(bool usb_control); u32 decode_pll(enum pll_clocks pll); diff --git a/arch/arm/include/asm/mach-imx/hab.h b/arch/arm/include/asm/mach-imx/hab.h index d8bd77075ae..2abf28ea45b 100644 --- a/arch/arm/include/asm/mach-imx/hab.h +++ b/arch/arm/include/asm/mach-imx/hab.h @@ -18,8 +18,6 @@ */ #define IVT_HEADER_MAGIC 0xD1 #define IVT_TOTAL_LENGTH 0x20 -#define IVT_HEADER_V1 0x40 -#define IVT_HEADER_V2 0x41 struct __packed ivt_header { uint8_t magic; @@ -44,6 +42,15 @@ struct __packed hab_hdr { u8 par; /* Parameters field */ }; +/* Default event structure */ +struct __packed evt_def { + struct hab_hdr hdr; /* Header */ + uint32_t sts; /* Status */ + uint32_t ctx; /* Default context */ + uint8_t *data; /* Default data location */ + size_t bytes; /* Size of default data */ +}; + /* -------- start of HAB API updates ------------*/ /* The following are taken from HAB4 SIS */ @@ -165,6 +172,22 @@ typedef void hapi_clock_init_t(void); #define HAB_ENG_RTL 0x77 /* RTL simulation engine */ #define HAB_ENG_SW 0xff /* Software engine */ +#ifdef CONFIG_ARM64 +#ifdef CONFIG_IMX8MQ +#define HAB_RVT_BASE 0x00000880 +#else +#define HAB_RVT_BASE 0x00000900 +#endif + +#define HAB_RVT_ENTRY (*(ulong *)(HAB_RVT_BASE + 0x08)) +#define HAB_RVT_EXIT (*(ulong *)(HAB_RVT_BASE + 0x10)) +#define HAB_RVT_CHECK_TARGET (*(ulong *)(HAB_RVT_BASE + 0x18)) +#define HAB_RVT_AUTHENTICATE_IMAGE (*(ulong *)(HAB_RVT_BASE + 0x20)) +#define HAB_RVT_REPORT_EVENT (*(ulong *)(HAB_RVT_BASE + 0x40)) +#define HAB_RVT_REPORT_STATUS (*(ulong *)(HAB_RVT_BASE + 0x48)) +#define HAB_RVT_FAILSAFE (*(ulong *)(HAB_RVT_BASE + 0x50)) +#else + #ifdef CONFIG_ROM_UNIFIED_SECTIONS #define HAB_RVT_BASE 0x00000100 #else @@ -172,7 +195,7 @@ typedef void hapi_clock_init_t(void); #define HAB_RVT_BASE_OLD 0x00000094 #define HAB_RVT_BASE ((is_mx6dqp()) ? \ HAB_RVT_BASE_NEW : \ - (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_3)) ? \ HAB_RVT_BASE_NEW : \ (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ HAB_RVT_BASE_NEW : HAB_RVT_BASE_OLD) @@ -186,6 +209,8 @@ typedef void hapi_clock_init_t(void); #define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24)) #define HAB_RVT_FAILSAFE (*(uint32_t *)(HAB_RVT_BASE + 0x28)) +#endif /*CONFIG_ARM64*/ + #define HAB_CID_ROM 0 /**< ROM Caller ID */ #define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ @@ -199,6 +224,12 @@ typedef void hapi_clock_init_t(void); #define IVT_SIZE 0x20 #define CSF_PAD_SIZE 0x2000 +#define HAB_TAG_EVT 0xDB +#define HAB_TAG_EVT_DEF 0x0C + +#define HAB_MAJ_VER 0x40 +#define HAB_MAJ_MASK 0xF0 + /* ----------- end of HAB API updates ------------*/ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, diff --git a/arch/arm/include/asm/mach-imx/imx_vservice.h b/arch/arm/include/asm/mach-imx/imx_vservice.h new file mode 100644 index 00000000000..9e083e98443 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/imx_vservice.h @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#ifndef __IMX_VSERVICE_H__ +#define __IMX_VSERVICE_H__ + +#include +#include + +struct imx_vservice_channel +{ + u32 msg_seq; + struct udevice *mu_dev; + struct list_head channel_head; +}; + +void * imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size); +int imx_vservice_blocking_request(struct imx_vservice_channel *node, u8 *buf, u32* size); +struct imx_vservice_channel * imx_vservice_setup(struct udevice *virt_dev); + +#endif diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h index 1de70933550..541c8ea8426 100644 --- a/arch/arm/include/asm/mach-imx/iomux-v3.h +++ b/arch/arm/include/asm/mach-imx/iomux-v3.h @@ -87,15 +87,6 @@ typedef u64 iomux_v3_cfg_t; #define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \ MUX_MODE_SHIFT) #ifdef CONFIG_IMX8M -#define PAD_CTL_DSE0 (0x0 << 0) -#define PAD_CTL_DSE1 (0x1 << 0) -#define PAD_CTL_DSE2 (0x2 << 0) -#define PAD_CTL_DSE3 (0x3 << 0) -#define PAD_CTL_DSE4 (0x4 << 0) -#define PAD_CTL_DSE5 (0x5 << 0) -#define PAD_CTL_DSE6 (0x6 << 0) -#define PAD_CTL_DSE7 (0x7 << 0) - #define PAD_CTL_FSEL0 (0x0 << 3) #define PAD_CTL_FSEL1 (0x1 << 3) #define PAD_CTL_FSEL2 (0x2 << 3) @@ -105,8 +96,20 @@ typedef u64 iomux_v3_cfg_t; #define PAD_CTL_PUE (0x1 << 6) #define PAD_CTL_HYS (0x1 << 7) #if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP) +#define PAD_CTL_DSE1 (0x0 << 1) +#define PAD_CTL_DSE2 (0x2 << 1) +#define PAD_CTL_DSE4 (0x1 << 1) +#define PAD_CTL_DSE6 (0x3 << 1) #define PAD_CTL_PE (0x1 << 8) #else +#define PAD_CTL_DSE0 (0x0 << 0) +#define PAD_CTL_DSE1 (0x1 << 0) +#define PAD_CTL_DSE2 (0x2 << 0) +#define PAD_CTL_DSE3 (0x3 << 0) +#define PAD_CTL_DSE4 (0x4 << 0) +#define PAD_CTL_DSE5 (0x5 << 0) +#define PAD_CTL_DSE6 (0x6 << 0) +#define PAD_CTL_DSE7 (0x7 << 0) #define PAD_CTL_LVTTL (0x1 << 8) #endif @@ -278,10 +281,10 @@ if (is_mx6dq() || is_mx6dqp()) { \ } #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2) -#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) -#define IOMUX_PADS(x) MX6Q_##x +#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6QP) +#define IOMUX_PADS(x) MX6_##x #define SETUP_IOMUX_PAD(def) \ - imx_iomux_v3_setup_pad(MX6Q_##def); + imx_iomux_v3_setup_pad(MX6_##def); #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) #elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) @@ -291,9 +294,9 @@ if (is_mx6dq() || is_mx6dqp()) { \ #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) #else -#define IOMUX_PADS(x) MX6DL_##x +#define IOMUX_PADS(x) MX6_##x #define SETUP_IOMUX_PAD(def) \ - imx_iomux_v3_setup_pad(MX6DL_##def); + imx_iomux_v3_setup_pad(MX6_##def); #define SETUP_IOMUX_PADS(x) \ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)) #endif diff --git a/arch/arm/include/asm/mach-imx/mxc_key_defs.h b/arch/arm/include/asm/mach-imx/mxc_key_defs.h new file mode 100644 index 00000000000..3c0f4ce4545 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/mxc_key_defs.h @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +#ifndef _MXC_KEYPAD_H_ +#define _MXC_KEYPAD_H_ + +#define KEY_1 2 +#define KEY_2 3 +#define KEY_3 4 +#define KEY_F1 59 +#define KEY_UP 103 +#define KEY_F2 60 + +#define KEY_4 5 +#define KEY_5 6 +#define KEY_6 7 +#define KEY_LEFT 105 +#define KEY_SELECT 0x161 +#define KEY_RIGHT 106 + +#define KEY_7 8 +#define KEY_8 9 +#define KEY_9 10 +#define KEY_F3 61 +#define KEY_DOWN 108 +#define KEY_F4 62 + +#define KEY_0 11 +#define KEY_OK 0x160 +#define KEY_ESC 1 +#define KEY_ENTER 28 +#define KEY_MENU 139 /* Menu (show menu) */ +#define KEY_BACK 158 /* AC Back */ + +#endif diff --git a/arch/arm/include/asm/mach-imx/optee.h b/arch/arm/include/asm/mach-imx/optee.h new file mode 100644 index 00000000000..f13c5a397f8 --- /dev/null +++ b/arch/arm/include/asm/mach-imx/optee.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ +#ifndef __IMX_OPTEE_H__ +#define __IMX_OPTEE_H__ + +#include + +#define OPTEE_SHM_SIZE 0x00400000 +int ft_add_optee_node(void *fdt, struct bd_info *bd); +#endif diff --git a/arch/arm/include/asm/mach-imx/regs-bch.h b/arch/arm/include/asm/mach-imx/regs-bch.h index 5a149002e2a..d2acb1194ab 100644 --- a/arch/arm/include/asm/mach-imx/regs-bch.h +++ b/arch/arm/include/asm/mach-imx/regs-bch.h @@ -36,6 +36,7 @@ struct mxs_bch_regs { mxs_reg_32(hw_bch_flash2layout1) mxs_reg_32(hw_bch_flash3layout0) mxs_reg_32(hw_bch_flash3layout1) + mxs_reg_32(hw_bch_debug0) mxs_reg_32(hw_bch_dbgkesread) mxs_reg_32(hw_bch_dbgcsferead) mxs_reg_32(hw_bch_dbgsyndegread) diff --git a/arch/arm/include/asm/mach-imx/regs-lcdif.h b/arch/arm/include/asm/mach-imx/regs-lcdif.h index 58746387966..a44ce354223 100644 --- a/arch/arm/include/asm/mach-imx/regs-lcdif.h +++ b/arch/arm/include/asm/mach-imx/regs-lcdif.h @@ -22,7 +22,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT) + defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMXRT) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ #endif mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ @@ -61,7 +61,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_IMX8M) || defined(CONFIG_IMXRT) + defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMXRT) mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ @@ -73,7 +73,7 @@ struct mxs_lcdif_regs { defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || \ defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ - defined(CONFIG_IMX8M) + defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) mxs_reg_32(hw_lcdif_thres) mxs_reg_32(hw_lcdif_as_ctrl) mxs_reg_32(hw_lcdif_as_buf) diff --git a/arch/arm/include/asm/mach-imx/regs-usbphy.h b/arch/arm/include/asm/mach-imx/regs-usbphy.h index 2b18ec20f3f..bd1bca54b61 100644 --- a/arch/arm/include/asm/mach-imx/regs-usbphy.h +++ b/arch/arm/include/asm/mach-imx/regs-usbphy.h @@ -22,4 +22,7 @@ #define USBPHY_CTRL_CLKGATE (1 << 30) #define USBPHY_CTRL_SFTRST (1 << 31) +#define USBNC_PHY_STATUS_OFFSET 0x23C +#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ + #endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 43eae6d796d..674ae08454b 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -2,6 +2,7 @@ /* * (C) Copyright 2009 * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * Copyright 2018-2020 NXP */ #ifndef _SYS_PROTO_H_ @@ -60,12 +61,16 @@ struct bd_info; #define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL)) #define is_imx8mn() (is_cpu_type(MXC_CPU_IMX8MN) || is_cpu_type(MXC_CPU_IMX8MND) || \ is_cpu_type(MXC_CPU_IMX8MNS) || is_cpu_type(MXC_CPU_IMX8MNL) || \ - is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL)) + is_cpu_type(MXC_CPU_IMX8MNDL) || is_cpu_type(MXC_CPU_IMX8MNSL) || \ + is_cpu_type(MXC_CPU_IMX8MNUD) || is_cpu_type(MXC_CPU_IMX8MNUS) || is_cpu_type(MXC_CPU_IMX8MNUQ)) #define is_imx8mnd() (is_cpu_type(MXC_CPU_IMX8MND)) #define is_imx8mns() (is_cpu_type(MXC_CPU_IMX8MNS)) #define is_imx8mnl() (is_cpu_type(MXC_CPU_IMX8MNL)) #define is_imx8mndl() (is_cpu_type(MXC_CPU_IMX8MNDL)) #define is_imx8mnsl() (is_cpu_type(MXC_CPU_IMX8MNSL)) +#define is_imx8mnuq() (is_cpu_type(MXC_CPU_IMX8MNUQ)) +#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD)) +#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS)) #define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \ is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6)) #define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD)) @@ -73,6 +78,10 @@ struct bd_info; #define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6)) #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) +#define is_imx8dxl() (is_cpu_type(MXC_CPU_IMX8DXL)) + + /* gd->flags reserves high 16 bits for arch-specific flags */ +#define GD_FLG_ARCH_IMX_USB_BOOT 0x80000000 /* Only used for MX6/7, If set, the u-boot is booting from USB serial download */ #ifdef CONFIG_MX6 #define IMX6_SRC_GPR10_BMODE BIT(28) @@ -188,6 +197,7 @@ void board_mem_get_layout(u64 *phys_sdram_1_start, u64 *phys_sdram_2_start, u64 *phys_sdram_2_size); +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data); int arch_auxiliary_core_check_up(u32 core_id); int board_mmc_get_env_dev(int devno); @@ -209,6 +219,14 @@ int mxs_reset_block(struct mxs_register_32 *reg); int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout); int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout); +void board_late_mmc_env_init(void); + +void vadc_power_up(void); +void vadc_power_down(void); + +void pcie_power_up(void); +void pcie_power_off(void); + unsigned long call_imx_sip(unsigned long id, unsigned long reg0, unsigned long reg1, unsigned long reg2, unsigned long reg3); @@ -217,4 +235,9 @@ unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0, unsigned long reg3); void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); + +int add_res_mem_dt_node(void *fdt, const char *name, phys_addr_t pa, + size_t size); +int add_dt_path_subnode(void *fdt, const char *path, const char *subnode); +void configure_tzc380(void); #endif diff --git a/arch/arm/include/asm/mach-imx/video.h b/arch/arm/include/asm/mach-imx/video.h index d1a14ad7d34..51f21f212a8 100644 --- a/arch/arm/include/asm/mach-imx/video.h +++ b/arch/arm/include/asm/mach-imx/video.h @@ -1,10 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + */ #ifndef __IMX_VIDEO_H_ #define __IMX_VIDEO_H_ #include +#if defined(CONFIG_VIDEO_IPUV3) #include +#elif defined(CONFIG_VIDEO_MXS) +#include +#endif struct display_info_t { int bus; diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 5fe83699f43..a7a3b1950a0 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -491,7 +491,11 @@ enum dcache_option { DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT, DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK, DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK, +#ifdef CONFIG_IMX_TRUSTY_OS + DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1) | TTB_SECT_S_MASK, +#else DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1), +#endif }; #else #define TTB_SECT_AP (3 << 10) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 11af9e2fb9c..b3988ae7e38 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -34,6 +34,7 @@ #include #include #include +#include #ifdef CONFIG_ARMV7_NONSEC #include @@ -111,6 +112,10 @@ static void announce_and_cleanup(int fake) udc_disconnect(); #endif +#if defined(CONFIG_VIDEO_LINK) + video_link_shut_down(); +#endif + board_quiesce_devices(); printf("\nStarting kernel ...%s\n\n", fake ? @@ -120,10 +125,12 @@ static void announce_and_cleanup(int fake) * This may be useful for last-stage operations, like cancelling * of DMA operation or releasing device internal buffers. */ +#ifndef CONFIG_POWER_DOMAIN dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL | DM_REMOVE_NON_VITAL); /* Remove all active vital devices next */ dm_remove_devices_flags(DM_REMOVE_ACTIVE_ALL); +#endif cleanup_before_linux(); } diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 24050e5bdd3..b6d966e3193 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -258,11 +258,14 @@ static void cache_disable(uint32_t cache_bit) reg = get_cr(); #ifdef CONFIG_SYS_ARM_MMU - if (cache_bit == (CR_C | CR_M)) + if (cache_bit == (CR_C | CR_M)) { #elif defined(CONFIG_SYS_ARM_MPU) - if (cache_bit == CR_C) + if (cache_bit == CR_C) { #endif flush_dcache_all(); + set_cr(reg & ~CR_C); + flush_dcache_all(); + } set_cr(reg & ~cache_bit); } #endif diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index f5a921b3d1b..2d3fdb600eb 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -3,6 +3,7 @@ * Copyright 2019 Broadcom. */ #include +#include #include #include #include @@ -108,6 +109,8 @@ int gic_lpi_tables_init(void) int i; u64 redist_lpi_base; u64 pend_base; + ulong pend_tab_total_sz; + void *pend_tab_va; if (gic_v3_its_get_gic_addr(&priv)) return -EINVAL; @@ -161,6 +164,12 @@ int gic_lpi_tables_init(void) } redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ; + pend_tab_total_sz = priv.num_redist * LPI_PENDBASE_SZ; + pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz, + MAP_NOCACHE); + memset(pend_tab_va, 0, pend_tab_total_sz); + flush_cache((ulong)pend_tab_va, pend_tab_total_sz); + unmap_physmem(pend_tab_va, MAP_NOCACHE); pend_base = priv.gicr_base + GICR_PENDBASER; for (i = 0; i < priv.num_redist; i++) { @@ -168,7 +177,8 @@ int gic_lpi_tables_init(void) val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) | GICR_PENDBASER_INNERSHAREABLE | - GICR_PENDBASER_RAWAWB); + GICR_PENDBASER_RAWAWB | + GICR_PENDBASER_PTZ); writeq(val, (uintptr_t)(pend_base + offset)); tmp = readq((uintptr_t)(pend_base + offset)); diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 8f64e231952..bf479995c99 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -4,6 +4,11 @@ config HAS_CAAM config IMX_CONFIG string +config IMX_OPTEE + bool "Support OP-TEE" + help + Enable support for OP-TEE + config ROM_UNIFIED_SECTIONS bool @@ -13,6 +18,9 @@ config SYSCOUNTER_TIMER config GPT_TIMER bool +config FSL_CAAM_KB + bool + config IMX_RDC bool "i.MX Resource domain controller driver" depends on ARCH_MX6 || ARCH_MX7 @@ -23,7 +31,7 @@ config IMX_RDC config IMX_BOOTAUX bool "Support boot auxiliary core" - depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8M + depends on ARCH_MX7 || ARCH_MX6 || ARCH_VF610 || ARCH_IMX8 || ARCH_IMX8M help bootaux [addr] to boot auxiliary core. @@ -34,6 +42,26 @@ config IMX_MODULE_FUSE i.MX module fuse to runtime disable some driver, including Linux OS device node. +config IMX_VSERVICE_SHARED_BUFFER + hex "Define the buffer address used for virtual service" + depends on IMX_VSERVICE + help + IMX virtual service will use this buffer for exchanging data with remote core. + +config IMX_VSERVICE_SHARED_BUFFER_SIZE + hex "Define the size of buffer address used for virtual service" + default 0x400000 + depends on IMX_VSERVICE + help + The buffer size for IMX virtual service needs enough large to fit all possible message. + +config IMX_VSERVICE + bool + select MISC + select IMX_M4_MU + help + This enables imx virtual service provides framework for imx virtual driver working. + config USE_IMXIMG_PLUGIN bool "Use imximage plugin code" depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX7ULP @@ -43,9 +71,9 @@ config USE_IMXIMG_PLUGIN config IMX_HAB bool "Support i.MX HAB features" - depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 + depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_MX7ULP || ARCH_IMX8M select FSL_CAAM if HAS_CAAM - imply CMD_DEKBLOB + imply CMD_DEKBLOB if HAS_CAAM help This option enables the support for secure boot (HAB). See doc/imx/habv4/* for more details. @@ -75,12 +103,43 @@ config CMD_BMODE config CMD_DEKBLOB bool "Support the 'dek_blob' command" + select IMX_CAAM_DEK_ENCAP if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP + select IMX_OPTEE_DEK_ENCAP if ARCH_IMX8M + select IMX_SECO_DEK_ENCAP if ARCH_IMX8 help This enables the 'dek_blob' command which is used with the Freescale secure boot mechanism. This command encapsulates and creates a blob of data. See also CMD_BLOB and doc/imx/habv4/* for more information. +config IMX_CAAM_DEK_ENCAP + bool "Support the DEK blob encapsulation with CAAM U-Boot driver" + help + This enables the DEK blob encapsulation with the U-Boot CAAM driver. + This option is only available on imx6, imx7 and imx7ulp. + +config IMX_OPTEE_DEK_ENCAP + select TEE + select OPTEE + bool "Support the DEK blob encapsulation with OP-TEE" + help + This enabled the DEK blob encapsulation with OP-TEE. The communication + with OP-TEE is done through a SMC call and OP-TEE shared memory. This + option is available on imx8mm. + +config IMX_SECO_DEK_ENCAP + bool "Support the DEK blob encapsulation with SECO" + help + This enabled the DEK blob encapsulation with the SECO API. This option + is only available on imx8. + +config CMD_PRIBLOB + bool "Support the set_priblob_bitfield command" + depends on HAS_CAAM && IMX_HAB + help + This option enables the priblob command which can be used + to set the priblob setting to 0x3. + config CMD_HDMIDETECT bool "Support the 'hdmidet' command" help @@ -91,7 +150,7 @@ config CMD_NANDBCB bool "i.MX6 NAND Boot Control Block(BCB) command" depends on MTD_RAW_NAND && CMD_MTDPARTS select BCH if MX6UL || MX6ULL - default y if ((ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M) && NAND_MXS) + default y if ((ARCH_MX6 || ARCH_MX7 || ARCH_IMX8M || ARCH_IMX8) && NAND_MXS) help Unlike normal 'nand write/erase' commands, this command update Boot Control Block(BCB) for i.MX6 platform NAND IP's. @@ -99,6 +158,45 @@ config CMD_NANDBCB This is similar to kobs-ng, which is used in Linux as separate rootfs package. +config CMD_QSPIHDR + bool "Q(F)SPI Boot Config Header command" + depends on DM_SPI_FLASH + default y + help + Boot from Q(F)SPI need a boot config header, this command can + help to check if header already exists or add one if not. + +config FSL_MFGPROT + bool "Support the 'mfgprot' command" + depends on IMX_HAB || AHAB_BOOT + select IMX_CAAM_MFG_PROT if (ARCH_MX7 || ARCH_IMX8M) + select IMX_SECO_MFG_PROT if ARCH_IMX8 + help + This option enables the manufacturing protection command + which can be used has a protection feature for Manufacturing + process. With this tool is possible to authenticate the + chip to the OEM's server. + +config IMX_CAAM_MFG_PROT + bool "Support the manufacturing protection with CAAM U-Boot driver" + help + This enables the manufacturing protection feature with the U-Boot + CAAM driver. This option is only available on iMX7D/S. + +config IMX_SECO_MFG_PROT + bool "Support the manufacturing protection with SECO API" + help + This enables the manufacturing protection feature with the SECO API. + This option is only available on iMX8/8x series. + +config DBG_MONITOR + bool "Enable the AXI debug monitor" + depends on ARCH_MX6 || ARCH_MX7 + help + This option enables the debug monitor which prints out last + failed AXI access info when system reboot is caused by AXI + access failure. + config NXP_BOARD_REVISION bool "Read NXP board revision from fuses" depends on ARCH_MX6 || ARCH_MX7 @@ -107,6 +205,12 @@ config NXP_BOARD_REVISION stored in the fuses. Select this option if you want to be able to retrieve the board revision information. +config FLASH_MCUFIRMWARE_SUPPORT + bool "Enable mcu firmware flash support" + depends on ARCH_MX7ULP || ARCH_IMX8M + help + This enables the mcu firmware flash support for some SOCs. + config DDRMC_VF610_CALIBRATION bool "Enable DDRMC (DDR3) on-chip calibration" depends on ARCH_VF610 @@ -132,3 +236,108 @@ config IMX_DCD_ADDR the ROM code to configure the device at early boot stage, is located. This information is shared with the user via mkimage -l just so the image can be signed. + +config ANDROID_SUPPORT + bool "Standard Android features support" + default n + select FSL_FASTBOOT + select FASTBOOT_LOCK + select BCB_SUPPORT + select ANDROID_RECOVERY + select SUPPORT_RAW_INITRD + select LIBAVB + select AVB_SUPPORT + +config ANDROID_AUTO_SUPPORT + bool "Android Automotive features support" + default n + select FSL_FASTBOOT + select FASTBOOT_LOCK + select BCB_SUPPORT + select ANDROID_RECOVERY + select SUPPORT_RAW_INITRD + select LIBAVB + select AVB_SUPPORT + +config ANDROID_THINGS_SUPPORT + bool "Android Things features support" + default n + select FSL_FASTBOOT + select FASTBOOT_LOCK + select BCB_SUPPORT + select ANDROID_RECOVERY + select SUPPORT_RAW_INITRD + select LIBAVB + select AVB_SUPPORT + +config AT_AUTHENTICATE_UNLOCK + bool "Enable authenticate unlock for Android Things devices" + depends on ANDROID_THINGS_SUPPORT + +config ANDROID_AB_SUPPORT + bool "Android A/B slots support" + depends on ANDROID_SUPPORT || ANDROID_AUTO_SUPPORT || ANDROID_THINGS_SUPPORT + default n + select SYSTEM_RAMDISK_SUPPORT + +config SYSTEM_RAMDISK_SUPPORT + bool "Support build ramdisk in system image" + default n + +menu "TRUSTY OS Support" + +config IMX_TRUSTY_OS + bool "Support Trusty OS related feature" + depends on ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M + select SYS_ARM_CACHE_WRITEALLOC + select CMD_MMC_RPMB + select SUPPORT_EMMC_RPMB + select SPL_SUPPORT_EMMC_RPMB + +config TRUSTY_UNLOCK_PERMISSION + bool "Support unlock permission protection in trusty" + default y + depends on IMX_TRUSTY_OS + +config LOAD_KEY_FROM_RPMB + bool "Support load AVB public key from RPMB storage" + default y + depends on IMX_TRUSTY_OS + +config ID_ATTESTATION + bool "Support device ID attestation" + default y + depends on IMX_TRUSTY_OS + +config ATTESTATION_ID_PRODUCT + string "Product name for ID attestation" + depends on IMX_TRUSTY_OS && ID_ATTESTATION + default SYS_CONFIG_NAME + +config SECURE_UNLOCK + bool "Enable secure unlock for Android devices, it can only be enabled on HAB closed board" + depends on IMX_TRUSTY_OS + +endmenu + +config APPEND_BOOTARGS + bool "Append bootargs support" + +config DUAL_BOOTLOADER + bool "Enable dual bootloader support" + select SPL_MMC_SUPPORT + select SPL_MMC_WRITE + help + Enable A/B bootloader select in SPL. + +config ANDROID_DYNAMIC_PARTITION + bool "Support to boot up Android with system image in logical partitions" + +config VIRTUAL_AB_SUPPORT + bool "Support virtual AB update" + select ANDROID_DYNAMIC_PARTITION + +config BOOTLOADER_MENU + bool "Enable bootloader menu for android device" + help + bootloader menu feature for android device. diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index e6b4654cd35..5994e181bc6 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -13,9 +13,11 @@ ifeq ($(SOC),$(filter $(SOC),imx8m)) ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif -obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o +obj-y += mmc_env.o obj-$(CONFIG_FEC_MXC) += mac.o +obj-$(CONFIG_DWC_ETH_QOS) += mac.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o +obj-$(CONFIG_IMX_HAB) += hab.o obj-y += cpu.o endif @@ -27,14 +29,23 @@ endif obj-$(CONFIG_GPT_TIMER) += timer.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o endif -ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt)) +ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs mx7ulp imx8m imx8 imxrt)) obj-y += misc.o +obj-$(CONFIG_CMD_PRIBLOB) += priblob.o obj-$(CONFIG_SPL_BUILD) += spl.o endif +ifeq ($(SOC),$(filter $(SOC),imx8m imx8)) +obj-y += dt_optee.o +endif ifeq ($(SOC),$(filter $(SOC),mx7)) obj-y += cpu.o obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o -obj-$(CONFIG_ENV_IS_IN_MMC) += mmc_env.o +obj-y += mmc_env.o +endif +ifneq ($(CONFIG_SPL_BUILD),y) +ifeq ($(SOC),$(filter $(SOC),mx7 imx8 imx8m)) +obj-$(CONFIG_FSL_MFGPROT) += cmd_mfgprot.o +endif endif ifeq ($(SOC),$(filter $(SOC),mx5 mx6 mx7)) obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o @@ -49,6 +60,7 @@ endif obj-$(CONFIG_SATA) += sata.o obj-$(CONFIG_IMX_HAB) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o +obj-$(CONFIG_IMX_TRUSTY_OS) += trusty.o endif ifeq ($(SOC),$(filter $(SOC),mx7ulp)) obj-y += cache.o mmdc_size.o @@ -58,11 +70,18 @@ ifeq ($(SOC),$(filter $(SOC),vf610)) obj-y += ddrmc-vf610.o obj-$(CONFIG_DDRMC_VF610_CALIBRATION) += ddrmc-vf610-calibration.o endif +ifeq ($(SOC),$(filter $(SOC),imx8)) +ifneq ($(CONFIG_SPL_BUILD),y) +obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o +endif +endif ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o obj-$(CONFIG_CMD_NANDBCB) += cmd_nandbcb.o +obj-$(CONFIG_CMD_QSPIHDR) += cmd_qspihdr.o +obj-$(CONFIG_IMX_VSERVICE) += imx_vservice.o endif PLUGIN = board/$(BOARDDIR)/plugin @@ -114,12 +133,41 @@ IMAGE_TYPE := imximage DEPFILE_EXISTS := 0 endif -MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ +MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $(PLUGIN).bin $(QSPI_HEADER) $< $(PHONY),$^) \ -T $(IMAGE_TYPE) -e $(CONFIG_SYS_TEXT_BASE) u-boot.imx: MKIMAGEOUTPUT = u-boot.imx.log -u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin FORCE +QSPI_HEADER_SOURCE = board/freescale/common/qspi_header +QSPI_HEADER = qspi_header +QSPI_HEADER_OFF = 1 +QSPI_UBOOT_OFF = 4 +ifeq ($(SOC),$(filter $(SOC),mx7)) +QSPI_HEADER_OFF = 0 +QSPI_UBOOT_OFF = 1 +endif + +ifeq ($(CONFIG_QSPI_BOOT),y) +$(QSPI_HEADER): $(QSPI_HEADER_SOURCE) FORCE + @cp $< $@ + +else +$(QSPI_HEADER): + +endif + +u-boot.imx: u-boot.bin u-boot.cfgout $(PLUGIN).bin $(QSPI_HEADER) FORCE $(call if_changed,mkimage) +ifeq ($(CONFIG_QSPI_BOOT),y) + @awk '{s="0000000"$$1;l=length(s);if(!((NR-1)%4))printf "%08x ",(NR-1)*4; \ + for(i=1;i<8;i+=2)printf " %s",substr(s,l-i,2);if(!(NR%4))printf "\n";}' \ + $(QSPI_HEADER) > qspi.tmp + @xxd -r qspi.tmp qspi.bin + @dd if=$@ of=u-boot.tmp bs=1k seek=$(QSPI_UBOOT_OFF) + @dd if=qspi.bin of=u-boot.tmp bs=1k seek=$(QSPI_HEADER_OFF) conv=notrunc + @mv u-boot.tmp $@ + @rm qspi.tmp qspi.bin + @echo "Packed QSPI header with $@" +endif ifeq ($(CONFIG_MULTI_DTB_FIT),y) MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ @@ -131,13 +179,24 @@ ifeq ($(DEPFILE_EXISTS),0) $(call if_changed,mkimage) endif else ifeq ($(CONFIG_OF_SEPARATE),y) -MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \ +MKIMAGEFLAGS_u-boot-dtb.imx = -n $(filter-out $(PLUGIN).bin $(QSPI_HEADER) $< $(PHONY),$^) \ -T $(IMAGE_TYPE) -e $(CONFIG_SYS_TEXT_BASE) u-boot-dtb.imx: MKIMAGEOUTPUT = u-boot-dtb.imx.log -u-boot-dtb.imx: u-boot-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin FORCE +u-boot-dtb.imx: u-boot-dtb.bin u-boot-dtb.cfgout $(PLUGIN).bin $(QSPI_HEADER) FORCE ifeq ($(DEPFILE_EXISTS),0) $(call if_changed,mkimage) +ifeq ($(CONFIG_QSPI_BOOT),y) + @awk '{s="0000000"$$1;l=length(s);if(!((NR-1)%4))printf "%08x ",(NR-1)*4; \ + for(i=1;i<8;i+=2)printf " %s",substr(s,l-i,2);if(!(NR%4))printf "\n";}' \ + $(QSPI_HEADER) > qspi.tmp + @xxd -r qspi.tmp qspi.bin + @dd if=$@ of=u-boot.tmp bs=1k seek=$(QSPI_UBOOT_OFF) + @dd if=qspi.bin of=u-boot.tmp bs=1k seek=$(QSPI_HEADER_OFF) conv=notrunc + @mv u-boot.tmp $@ + @rm qspi.tmp qspi.bin + @echo "Packed QSPI header with $@" +endif endif endif diff --git a/arch/arm/mach-imx/cache.c b/arch/arm/mach-imx/cache.c index 4e3b49a3fdf..9dc410b64f0 100644 --- a/arch/arm/mach-imx/cache.c +++ b/arch/arm/mach-imx/cache.c @@ -10,6 +10,9 @@ #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; static void enable_ca7_smp(void) { @@ -40,12 +43,16 @@ static void enable_ca7_smp(void) } #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) + +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0) + void enable_caches(void) { #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) - enum dcache_option option = DCACHE_WRITETHROUGH; + enum dcache_option option = DCACHE_WRITETHROUGH & ~TTB_SECT_XN_MASK; #else - enum dcache_option option = DCACHE_WRITEBACK; + enum dcache_option option = DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK; #endif /* Avoid random hang when download by usb */ invalidate_dcache_all(); @@ -64,6 +71,33 @@ void enable_caches(void) IRAM_SIZE, option); } + +void dram_bank_mmu_setup(int bank) +{ + struct bd_info *bd = gd->bd; + int i; + + debug("%s: bank: %d\n", __func__, bank); + for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; + i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) + + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION & ~TTB_SECT_XN_MASK); +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set domain to client to do access and XN check + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} + #else void enable_caches(void) { diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 49dd473af72..2b5dafdddb3 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -9,11 +9,18 @@ #include #include #include +#include #include #include #include #include #include +#include +#ifdef CONFIG_IMX_SECO_DEK_ENCAP +#include +#include +#endif +#include /** * blob_dek() - Encapsulate the DEK as a blob using CAM's Key @@ -23,16 +30,20 @@ * * Returns zero on success,and negative on error. */ -static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) +#ifdef CONFIG_IMX_CAAM_DEK_ENCAP +static int blob_encap_dek(uint32_t src_addr, uint32_t dst_addr, uint32_t len) { - int ret = 0; - u32 jr_size = 4; + uint8_t *src_ptr, *dst_ptr; + + src_ptr = map_sysmem(src_addr, len / 8); + dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len / 8)); - u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c); - if (out_jr_size != jr_size) { - hab_caam_clock_enable(1); + hab_caam_clock_enable(1); + + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + FSL_CAAM_ORSR_JRa_OFFSET); + if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) sec_init(); - } if (!((len == 128) | (len == 192) | (len == 256))) { debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); @@ -40,10 +51,239 @@ static int blob_encap_dek(const u8 *src, u8 *dst, u32 len) } len /= 8; - ret = blob_dek(src, dst, len); + return blob_dek(src_ptr, dst_ptr, len); +} +#endif /* CONFIG_IMX_CAAM_DEK_ENCAP */ + +#ifdef CONFIG_IMX_OPTEE_DEK_ENCAP + +#define PTA_DEK_BLOB_PTA_UUID {0xef477737, 0x0db1, 0x4a9d, \ + {0x84, 0x37, 0xf2, 0xf5, 0x35, 0xc0, 0xbd, 0x92} } + +#define OPTEE_BLOB_HDR_SIZE 8 + +static int blob_encap_dek(uint32_t src_addr, uint32_t dst_addr, uint32_t len) +{ + struct udevice *dev = NULL; + struct tee_shm *shm_input, *shm_output; + struct tee_open_session_arg arg = {0}; + struct tee_invoke_arg arg_func = {0}; + const struct tee_optee_ta_uuid uuid = PTA_DEK_BLOB_PTA_UUID; + struct tee_param param[4] = {0}; + int ret; + + /* Get tee device */ + dev = tee_find_device(NULL, NULL, NULL, NULL); + if (dev == NULL) { + printf("Cannot get OP-TEE device\n"); + return -1; + } + + /* Set TA UUID */ + tee_optee_ta_uuid_to_octets(arg.uuid, &uuid); + + /* Open TA session */ + ret = tee_open_session(dev, &arg, 0, NULL); + if (ret < 0) { + printf("Cannot open session with PTA Blob 0x%X\n", ret); + return -1; + } + + /* Allocate shared input and output buffers for TA */ + ret = tee_shm_register(dev, (void *)(ulong)src_addr, len / 8, 0x0, &shm_input); + if (ret < 0) { + printf("Cannot register input shared memory 0x%X\n", ret); + goto error; + } + + ret = tee_shm_register(dev, (void *)(ulong)dst_addr, + BLOB_SIZE(len / 8) + OPTEE_BLOB_HDR_SIZE, + 0x0, &shm_output); + if (ret < 0) { + printf("Cannot register output shared memory 0x%X\n", ret); + goto error; + } + + param[0].u.memref.shm = shm_input; + param[0].u.memref.size = shm_input->size; + param[0].attr = TEE_PARAM_ATTR_TYPE_MEMREF_INPUT; + param[1].u.memref.shm = shm_output; + param[1].u.memref.size = shm_output->size; + param[1].attr = TEE_PARAM_ATTR_TYPE_MEMREF_OUTPUT; + param[2].attr = TEE_PARAM_ATTR_TYPE_NONE; + param[3].attr = TEE_PARAM_ATTR_TYPE_NONE; + + arg_func.func = 0; + arg_func.session = arg.session; + + /* Generate DEK blob */ + arg_func.session = arg.session; + ret = tee_invoke_func(dev, &arg_func, 4, param); + if (ret < 0) + printf("Cannot generate Blob with PTA DEK Blob 0x%X\n", ret); + +error: + /* Free shared memory */ + tee_shm_free(shm_input); + tee_shm_free(shm_output); + + /* Close session */ + ret = tee_close_session(dev, arg.session); + if (ret < 0) + printf("Cannot close session with PTA DEK Blob 0x%X\n", ret); return ret; } +#endif /* CONFIG_IMX_OPTEE_DEK_ENCAP */ +#ifdef CONFIG_IMX_SECO_DEK_ENCAP + +#define DEK_BLOB_KEY_ID 0x0 + +#define AHAB_PRIVATE_KEY 0x81 +#define AHAB_VERSION 0x00 +#define AHAB_MODE_CBC 0x67 +#define AHAB_ALG_AES 0x55 +#define AHAB_128_AES_KEY 0x10 +#define AHAB_192_AES_KEY 0x18 +#define AHAB_256_AES_KEY 0x20 +#define AHAB_FLAG_KEK 0x80 +#define AHAB_DEK_BLOB 0x01 + +#define DEK_BLOB_HDR_SIZE 8 +#define SECO_PT 2U + +static int blob_encap_dek(uint32_t src_addr, uint32_t dst_addr, uint32_t len) +{ + sc_err_t err; + sc_rm_mr_t mr_input, mr_output; + struct generate_key_blob_hdr hdr; + uint8_t in_size, out_size; + uint8_t *src_ptr, *dst_ptr; + int ret = 0; + int i; + + /* Set sizes */ + in_size = sizeof(struct generate_key_blob_hdr) + len / 8; + out_size = BLOB_SIZE(len / 8) + DEK_BLOB_HDR_SIZE; + + /* Get src and dst virtual addresses */ + src_ptr = map_sysmem(src_addr, in_size); + dst_ptr = map_sysmem(dst_addr, out_size); + + /* Check addr input */ + if (!(src_ptr && dst_ptr)) { + debug("src_addr or dst_addr invalid\n"); + return -1; + } + + /* Build key header */ + hdr.version = AHAB_VERSION; + hdr.length_lsb = sizeof(struct generate_key_blob_hdr) + len / 8; + hdr.length_msb = 0x00; + hdr.tag = AHAB_PRIVATE_KEY; + hdr.flags = AHAB_DEK_BLOB; + hdr.algorithm = AHAB_ALG_AES; + hdr.mode = AHAB_MODE_CBC; + + switch (len) { + case 128: + hdr.size = AHAB_128_AES_KEY; + break; + case 192: + hdr.size = AHAB_192_AES_KEY; + break; + case 256: + hdr.size = AHAB_256_AES_KEY; + break; + default: + /* Not supported */ + debug("Invalid DEK size. Valid sizes are 128, 192 and 256b\n"); + return -1; + } + + /* Build input message */ + memmove((void *)(src_ptr + sizeof(struct generate_key_blob_hdr)), + (void *)src_ptr, len / 8); + memcpy((void *)src_ptr, (void *)&hdr, + sizeof(struct generate_key_blob_hdr)); + + /* Flush the cache before triggering the CAAM DMA */ + flush_dcache_range(src_addr, src_addr + in_size); + + /* Find input memory region */ + err = sc_rm_find_memreg( + (-1), &mr_input, src_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(src_addr + in_size, CONFIG_SYS_CACHELINE_SIZE)); + if (err) { + printf("Error: find memory region 0x%X\n", src_addr); + return -ENOMEM; + } + + /* Find output memory region */ + err = sc_rm_find_memreg( + (-1), &mr_output, dst_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1), + ALIGN(dst_addr + out_size, CONFIG_SYS_CACHELINE_SIZE)); + if (err) { + printf("Error: find memory region 0x%X\n", dst_addr); + return -ENOMEM; + } + + /* Set memory region permissions for SECO */ + err = sc_rm_set_memreg_permissions(-1, mr_input, SECO_PT, + SC_RM_PERM_FULL); + if (err) { + printf("Set permission failed for input memory region\n"); + ret = -EPERM; + goto error; + } + + err = sc_rm_set_memreg_permissions(-1, mr_output, SECO_PT, + SC_RM_PERM_FULL); + if (err) { + printf("Set permission failed for output memory region\n"); + ret = -EPERM; + goto error; + } + + /* Flush output data before SECO operation */ + flush_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + /* Generate DEK blob */ + err = sc_seco_gen_key_blob((-1), 0x0, src_addr, dst_addr, out_size); + if (err) { + ret = -EPERM; + goto error; + } + + /* Invalidate output buffer */ + invalidate_dcache_range((ulong)dst_ptr, (ulong)(dst_ptr + + roundup(out_size, ARCH_DMA_MINALIGN))); + + printf("DEK Blob\n"); + for (i = 0; i < DEK_BLOB_HDR_SIZE + BLOB_SIZE(len / 8); i++) + printf("%02X", dst_ptr[i]); + printf("\n"); + +error: + /* Remove memory region permission to SECO */ + err = sc_rm_set_memreg_permissions(-1, mr_input, SECO_PT, + SC_RM_PERM_NONE); + if (err) { + printf("Error: remove permission failed for input\n"); + ret = -EPERM; + } + + err = sc_rm_set_memreg_permissions(-1, mr_output, SECO_PT, + SC_RM_PERM_NONE); + if (err) { + printf("Error: remove permission failed for output\n"); + ret = -EPERM; + } + + return ret; +} +#endif /* CONFIG_IMX_SECO_DEK_ENCAP */ /** * do_dek_blob() - Handle the "dek_blob" command-line command @@ -59,8 +299,6 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { uint32_t src_addr, dst_addr, len; - uint8_t *src_ptr, *dst_ptr; - int ret = 0; if (argc != 4) return CMD_RET_USAGE; @@ -69,12 +307,7 @@ static int do_dek_blob(struct cmd_tbl *cmdtp, int flag, int argc, dst_addr = simple_strtoul(argv[2], NULL, 16); len = simple_strtoul(argv[3], NULL, 10); - src_ptr = map_sysmem(src_addr, len/8); - dst_ptr = map_sysmem(dst_addr, BLOB_SIZE(len/8)); - - ret = blob_encap_dek(src_ptr, dst_ptr, len); - - return ret; + return blob_encap_dek(src_addr, dst_addr, len); } /***************************************************/ diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c new file mode 100644 index 00000000000..b20cd942145 --- /dev/null +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * These commands enable the use of the CAAM MPPubK-generation and MPSign + * functions in supported i.MX devices. + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_IMX_CAAM_MFG_PROT +#include +#include +#endif +#ifdef CONFIG_IMX_SECO_MFG_PROT +#include +#include +#endif + +/** + * do_mfgprot() - Handle the "mfgprot" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Returns zero on success, CMD_RET_USAGE in case of misuse and negative + * on error. + */ +#ifdef CONFIG_IMX_CAAM_MFG_PROT + +static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u8 *m_ptr, *dgst_ptr, *c_ptr, *d_ptr, *dst_ptr; + char *pubk, *sign, *sel; + int m_size, i, ret; + u32 m_addr; + + pubk = "pubk"; + sign = "sign"; + sel = argv[1]; + + /* Enable HAB clock */ + hab_caam_clock_enable(1); + + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + FSL_CAAM_ORSR_JRa_OFFSET); + + if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) + sec_init(); + + if (strcmp(sel, pubk) == 0) { + dst_ptr = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES); + if (!dst_ptr) + return -ENOMEM; + + ret = gen_mppubk(dst_ptr); + if (ret) { + free(dst_ptr); + return ret; + } + + /* Output results */ + puts("Public key:\n"); + for (i = 0; i < FSL_CAAM_MP_PUBK_BYTES; i++) + printf("%02X", (dst_ptr)[i]); + puts("\n"); + free(dst_ptr); + + } else if (strcmp(sel, sign) == 0) { + if (argc != 4) + return CMD_RET_USAGE; + + m_addr = hextoul(argv[2], NULL); + m_size = dectoul(argv[3], NULL); + m_ptr = map_physmem(m_addr, m_size, MAP_NOCACHE); + if (!m_ptr) + return -ENOMEM; + + dgst_ptr = malloc_cache_aligned(FSL_CAAM_MP_MES_DGST_BYTES); + if (!dgst_ptr) { + ret = -ENOMEM; + goto free_m; + } + + c_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES); + if (!c_ptr) { + ret = -ENOMEM; + goto free_dgst; + } + + d_ptr = malloc_cache_aligned(FSL_CAAM_MP_PRVK_BYTES); + if (!d_ptr) { + ret = -ENOMEM; + goto free_c; + } + + ret = sign_mppubk(m_ptr, m_size, dgst_ptr, c_ptr, d_ptr); + if (ret) + goto free_d; + + /* Output results */ + puts("Message: "); + for (i = 0; i < m_size; i++) + printf("%02X ", (m_ptr)[i]); + puts("\n"); + + puts("Message Representative Digest(SHA-256):\n"); + for (i = 0; i < FSL_CAAM_MP_MES_DGST_BYTES; i++) + printf("%02X", (dgst_ptr)[i]); + puts("\n"); + + puts("Signature:\n"); + puts("C:\n"); + for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++) + printf("%02X", (c_ptr)[i]); + puts("\n"); + + puts("d:\n"); + for (i = 0; i < FSL_CAAM_MP_PRVK_BYTES; i++) + printf("%02X", (d_ptr)[i]); + puts("\n"); +free_d: + free(d_ptr); +free_c: + free(c_ptr); +free_dgst: + free(dgst_ptr); +free_m: + unmap_sysmem(m_ptr); + + } else { + return CMD_RET_USAGE; + } + return ret; +} +#endif /* CONFIG_IMX_CAAM_MFG_PROT */ + +#ifdef CONFIG_IMX_SECO_MFG_PROT + +#define FSL_CAAM_MP_PUBK_BYTES 96 +#define FSL_CAAM_MP_SIGN_BYTES 96 +#define SCU_SEC_SECURE_RAM_BASE (0x20800000UL) +#define SEC_SECURE_RAM_BASE (0x31800000UL) + +static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u8 *m_ptr, *sign_ptr, *dst_ptr; + char *pubk, *sign, *sel; + int m_size, i, ret; + u32 m_addr; + + pubk = "pubk"; + sign = "sign"; + sel = argv[1]; + + if (!sel) + return CMD_RET_USAGE; + + if (strcmp(sel, pubk) == 0) { + dst_ptr = malloc_cache_aligned(FSL_CAAM_MP_PUBK_BYTES); + if (!dst_ptr) + return -ENOMEM; + + puts("\nGenerating Manufacturing Protection Public Key\n"); + + ret = sc_seco_get_mp_key(-1, SCU_SEC_SECURE_RAM_BASE, + FSL_CAAM_MP_PUBK_BYTES); + if (ret) { + printf("SECO get MP key failed, return %d\n", ret); + ret = -EIO; + free(dst_ptr); + return ret; + } + + memcpy((void *)dst_ptr, (const void *)SEC_SECURE_RAM_BASE, + ALIGN(FSL_CAAM_MP_PUBK_BYTES, + CONFIG_SYS_CACHELINE_SIZE)); + + /* Output results */ + puts("\nPublic key:\n"); + for (i = 0; i < FSL_CAAM_MP_PUBK_BYTES; i++) + printf("%02X", (dst_ptr)[i]); + puts("\n"); + free(dst_ptr); + + } else if (strcmp(sel, sign) == 0) { + if (argc != 4) + return CMD_RET_USAGE; + + m_addr = simple_strtoul(argv[2], NULL, 16); + m_size = simple_strtoul(argv[3], NULL, 10); + m_ptr = map_physmem(m_addr, m_size, MAP_NOCACHE); + if (!m_ptr) + return -ENOMEM; + + sign_ptr = malloc_cache_aligned(FSL_CAAM_MP_SIGN_BYTES); + if (!sign_ptr) { + ret = -ENOMEM; + goto free_m; + } + + memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)m_ptr, + ALIGN(m_size, CONFIG_SYS_CACHELINE_SIZE)); + + puts("\nSigning message with SECO MP signature function\n"); + + ret = sc_seco_get_mp_sign(-1, SCU_SEC_SECURE_RAM_BASE, m_size, + SCU_SEC_SECURE_RAM_BASE + 0x1000, + FSL_CAAM_MP_SIGN_BYTES); + + if (ret) { + printf("SECO get MP signature failed, return %d\n", + ret); + ret = -EIO; + goto free_sign; + } + + memcpy((void *)sign_ptr, (const void *)SEC_SECURE_RAM_BASE + + 0x1000, ALIGN(FSL_CAAM_MP_SIGN_BYTES, + CONFIG_SYS_CACHELINE_SIZE)); + + /* Output results */ + puts("\nMessage: "); + for (i = 0; i < m_size; i++) + printf("%02X", (m_ptr)[i]); + puts("\n"); + + puts("\nSignature:\n"); + puts("c:\n"); + for (i = 0; i < FSL_CAAM_MP_SIGN_BYTES / 2; i++) + printf("%02X", (sign_ptr)[i]); + puts("\n"); + + puts("d:\n"); + for (i = FSL_CAAM_MP_SIGN_BYTES / 2; i < FSL_CAAM_MP_SIGN_BYTES; + i++) + printf("%02X", (sign_ptr)[i]); + puts("\n"); + +free_sign: + free(sign_ptr); +free_m: + unmap_sysmem(m_ptr); + + } else { + return CMD_RET_USAGE; + } + return ret; +} +#endif /* CONFIG_IMX_SECO_MFG_PROT */ + +/***************************************************/ +static char mfgprot_help_text[] = + "Usage:\n" + "Print the public key for Manufacturing Protection\n" + "\tmfgprot pubk\n" + "Generates a Manufacturing Protection signature\n" + "\tmfgprot sign "; + +U_BOOT_CMD( + mfgprot, 4, 1, do_mfgprot, + "Manufacturing Protection\n", + mfgprot_help_text +); diff --git a/arch/arm/mach-imx/cmd_nandbcb.c b/arch/arm/mach-imx/cmd_nandbcb.c index 7157c9e9799..d9639750748 100644 --- a/arch/arm/mach-imx/cmd_nandbcb.c +++ b/arch/arm/mach-imx/cmd_nandbcb.c @@ -1489,7 +1489,7 @@ static int do_nandbcb(struct cmd_tbl *cmdtp, int flag, int argc, plat_config = imx8mm_plat_config; } else if (is_imx8mn() || is_imx8mp()) { plat_config = imx8mn_plat_config; - } else if (is_imx8qm() || is_imx8qxp()) { + } else if (is_imx8qm() || is_imx8qxp() || is_imx8dxl()) { plat_config = imx8q_plat_config; } else { printf("ERROR: Unknown platform\n"); @@ -1497,7 +1497,7 @@ static int do_nandbcb(struct cmd_tbl *cmdtp, int flag, int argc, } if ((plat_config.misc_flags) & BT_SEARCH_CNT_FROM_FUSE) { - if (is_imx8qxp()) + if (is_imx8qxp() || is_imx8dxl()) g_boot_search_count = fuse_to_search_count(0, 720, 0xc0, 6); if (is_imx8mn() || is_imx8mp()) g_boot_search_count = fuse_to_search_count(2, 2, 0x6000, 13); diff --git a/arch/arm/mach-imx/cmd_qspihdr.c b/arch/arm/mach-imx/cmd_qspihdr.c new file mode 100644 index 00000000000..6e2758664f8 --- /dev/null +++ b/arch/arm/mach-imx/cmd_qspihdr.c @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static struct spi_flash *flash; + +#define QSPI_HDR_TAG 0xc0ffee01 /* c0ffee01 */ +#define QSPI_HDR_TAG_OFF 0x1fc +#define FSPI_HDR_TAG 0x42464346/* FCFB, bigendian */ +#define FSPI_HDR_TAG_OFF 0x0 + +#define HDR_LEN 0x200 + +#ifdef CONFIG_MX7 +#define QSPI_HDR_OFF 0x0 +#define QSPI_DATA_OFF 0x400 +#else +#define QSPI_HDR_OFF 0x400 +#define QSPI_DATA_OFF 0x1000 +#endif + +#ifdef CONFIG_IMX8MM +#define FSPI_HDR_OFF 0x0 +#define FSPI_DATA_OFF 0x1000 +#else +#define FSPI_HDR_OFF 0x400 +#define FSPI_DATA_OFF 0x1000 +#endif + +#define FLAG_VERBOSE 1 + +struct qspi_config_parameter { + u32 dqs_loopback; /* Sets DQS LoopBack Mode to enable Dummy Pad MCR[24] */ + u32 hold_delay; /* No needed on ULT1 */ + u32 hsphs; /* Half Speed Phase Shift */ + u32 hsdly; /* Half Speed Delay Selection */ + u32 device_quad_mode_en; /* Write Command to Device */ + u32 device_cmd; /* Cmd to xfer to device */ + u32 write_cmd_ipcr; /* IPCR value of Write Cmd */ + u32 write_enable_ipcr; /* IPCR value of Write enable */ + u32 cs_hold_time; /* CS hold time in terms of serial clock.(for example 1 serial clock cyle) */ + u32 cs_setup_time; /* CS setup time in terms of serial clock.(for example 1 serial clock cyle) */ + u32 sflash_A1_size; /* interms of Bytes */ + u32 sflash_A2_size; /* interms of Bytes */ + u32 sflash_B1_size; /* interms of Bytes */ + u32 sflash_B2_size; /* interms of Bytes */ + u32 sclk_freq; /* 0 - 18MHz, 1 - 49MHz, 2 - 55MHz, 3 - 60MHz, 4 - 66Mhz, 5 - 76MHz, 6 - 99MHz (only for SDR Mode) */ + u16 busy_bit_offset; /* Flash device busy bit offset in status register */ + u16 busy_bit_polarity; /* Polarity of busy bit, 0 means the busy bit is 1 while busy and vice versa. */ + u32 sflash_type; /* 1 - Single, 2 - Dual, 4 - Quad */ + u32 sflash_port; /* 0 - Only Port-A, 1 - Both PortA and PortB */ + u32 ddr_mode_enable; /* Enable DDR mode if set to TRUE */ + u32 dqs_enable; /* Enable DQS mode if set to TRUE. Bit 0 represents DQS_EN, bit 1 represents DQS_LAT_EN */ + u32 parallel_mode_enable; /* Enable Individual or parrallel mode. */ + u32 portA_cs1; /* Enable Port A CS1 */ + u32 portB_cs1; /* Enable Port B CS1 */ + u32 fsphs; /* Full Speed Phase Selection */ + u32 fsdly; /* Full Speed Phase Selection */ + u32 ddrsmp; /* Select the sampling point for incoming data when serial flash is in DDR mode. */ + u32 command_seq[64]; /* Set of seq to perform optimum read on SFLASH as as per vendor SFLASH */ + u32 read_status_ipcr; /* IPCR value of Read Status Reg */ + u32 enable_dqs_phase; /* Enable DQS phase */ + u32 config_cmds_en; /* Enable config commands */ + u32 config_cmds[4]; /* config commands, used to configure nor flash */ + u32 config_cmds_args[4]; /* config commands argu */ + u32 dqs_pad_setting_override; /* DQS pin pad setting override */ + u32 sclk_pad_setting_override; /* SCLK pin pad setting override */ + u32 data_pad_setting_override; /* DATA pins pad setting override */ + u32 cs_pad_setting_override; /* CS pins pad setting override */ + u32 dqs_loopback_internal; /* 0: dqs loopback from pad, 1: dqs loopback internally */ + u32 dqs_phase_sel; /* dqs phase sel */ + u32 dqs_fa_delay_chain_sel; /* dqs fa delay chain selection */ + u32 dqs_fb_delay_chain_sel; /* dqs fb delay chain selection */ + u32 sclk_fa_delay_chain_sel; /* sclk fa delay chain selection */ + u32 sclk_fb_delay_chain_sel; /* sclk fb delay chain selection */ + u32 misc_clock_enable; /* Misc clock enable, bit 0 means differential clock enable, bit 1 means CK2 clock enable. */ + u32 reserve[15]; /* Reserved area, the total size of configuration structure should be 512 bytes */ + u32 tag; /* QSPI configuration TAG, should be 0xc0ffee01 */ +}; + +struct fspi_config_parameter { + u32 tag; /* tag, 0x46434642 ascii 'FCFB' */ + u32 version; /* 0x00000156 ascii bugfix | minor | major | 'V' */ + u16 reserved; + u8 reserved0[2]; + u8 readSampleClkSrc; /* 0 - internal loopback, 1 - loopback from DQS pad, 2 - loopback from SCK pad, 3 - Flash provided DQS */ + u8 dataHoldTime; /* CS hold time */ + u8 dataSetupTime; /* CS setup time */ + u8 columnAddressWidth; /* 3 - for HyperFlash, 0 - other devices */ + u8 deviceModeCfgEnable; /* device mode configuration enable feature, 0 - disable, 1- enable */ + u8 reserved1[3]; + u32 deviceModeSeq; /* sequence parameter for device mode configuration */ + u32 deviceModeArg; /* device mode argument, effective only when deviceModeCfgEnable = 1 */ + u8 configCmdEnable; /* config command enable feature, 0 - disable, 1 - enable */ + u8 reserved2[3]; + u32 configCmdSeqs[4]; /* sequences for config command, allow 4 separate configuration command sequences */ + u32 configCmdArgs[4]; /* arguments for each separate configuration command sequence */ + u32 controllerMiscOption; + /* + * + * +--------+----------------------------------------------------------+ + * | offset | description | + * +--------+----------------------------------------------------------+ + * | | differential clock enable | + * | 0 | | + * | | 0 - differential clock is not supported | + * | | 1 - differential clock is supported | + * +--------+----------------------------------------------------------+ + * | | CK2 enable | + * | 1 | | + * | | must set 0 for this silicon | + * | | | + * +--------+----------------------------------------------------------+ + * | | parallel mode enable | + * | 2 | | + * | | must set 0 for this silicon | + * | | | + * +--------+----------------------------------------------------------+ + * | | word addressable enable | + * | 3 | | + * | | 0 - device is not word addressable | + * | | 1 - device is word addressable | + * +--------+----------------------------------------------------------+ + * | | safe configuration frequency enable | + * | 4 | | + * | | 0 - configure external device using specified frequency | + * | | 1 - configure external device using 30MHz | + * +--------+----------------------------------------------------------+ + * | 5 | reserved | + * +--------+----------------------------------------------------------+ + * | | ddr mode enable | + * | 6 | | + * | | 0 - external device works using SDR commands | + * | | 1 - external device works using DDR commands | + * +--------+----------------------------------------------------------+ + */ + u8 deviceType; /* 1 - serial NOR */ + u8 sflashPadType; /* 1 - single pad, 2 - dual pads, 4 - quad pads, 8 - octal pads */ + u8 serialClkFreq; /* 1 - 20MHz, 2 - 50MHz, 3 - 60MHz, 4 - 80MHz, 5 - 100MHz, 6 - 133MHz, 7 - 166MHz, other values - 20MHz*/ + u8 lutCustomSeqEnable; /* 0 - use pre-defined LUT sequence index and number, 1 - use LUT sequence parameters provided in this block */ + u32 reserved3[2]; + u32 sflashA1Size; /* For SPI NOR, need to fill with actual size, in terms of bytes */ + u32 sflashA2Size; /* same as above */ + u32 sflashB1Size; /* same as above */ + u32 sflashB2Size; /* same as above */ + u32 csPadSettingOverride; /* set to 0 if it is not supported */ + u32 sclkPadSettingOverride; /* set to 0 if it is not supported */ + u32 dataPadSettingOverride; /* set to 0 if it is not supported */ + u32 dqsPadSettingOverride; /* set to 0 if it is not supported */ + u32 timeoutInMs; /* maximum wait time during dread busy status, not used in ROM */ + u32 commandInterval; /* interval of CS deselected period, set to 0 */ + u16 dataValidTime[2]; /* time from clock edge to data valid edge */ + /* This field is used when the FlexSPI root clock is less than 100MHz and the read sample */ + /* clock source is device provided DQS signal without CK2 support. */ + /* [31:16] - data valid time for DLLB in terms of 0.1ns */ + /* [15:0] - data valid time for DLLA in terms of 0.1ns */ + u16 busyOffset; /* busy bit offset, valid range: 0 - 31 */ + u16 busyBitPolarity; /* 0 - busy bit is 1 if device is busy, 1 - busy bit is 0 if device is busy */ + u32 lookupTable[64]; /* lookup table */ + u32 lutCustomSeq[12]; /* customized LUT sequence */ + u32 reserved4[4]; + u32 pageSize; /* page size of serial NOR flash, not used in ROM */ + u32 sectorSize; /* sector size of serial NOR flash, not used in ROM */ + u32 reserved5[14]; +}; + +struct header_config { + union { + struct qspi_config_parameter qspi_hdr_config; + struct fspi_config_parameter fspi_hdr_config; + }; +}; + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) +static struct qspi_config_parameter qspi_safe_config = { + .cs_hold_time = 3, + .cs_setup_time = 3, + .sflash_A1_size = 0x4000000, + .sflash_B1_size = 0x4000000, + .sflash_type = 1, + .command_seq[0] = 0x08180403, + .command_seq[1] = 0x24001c00, + .tag = 0xc0ffee01, +}; + +static struct header_config *safe_config = (struct header_config *)&qspi_safe_config; +#else +static struct fspi_config_parameter fspi_safe_config = { + .tag = 0x42464346, + .version = 0x56010000, + .dataHoldTime = 0x3, + .dataSetupTime = 0x3, + .deviceType = 0x1, + .sflashPadType = 0x1, + .serialClkFreq = 0x2, + .sflashA1Size = 0x10000000, + .lookupTable[0] = 0x0818040b, + .lookupTable[1] = 0x24043008, +}; + +static struct header_config *safe_config = (struct header_config *)&fspi_safe_config; +#endif + +static int qspi_erase_update(struct spi_flash *flash, int off, int len, void *buf) +{ + int size; + int ret; + + size = ROUND(len, flash->sector_size); + ret = spi_flash_erase(flash, off, size); + printf("Erase %#x bytes @ %#x %s\n", + size, off, ret ? "ERROR" : "OK"); + if (ret) + return ret; + + ret = spi_flash_write(flash, off, len, buf); + printf("Write %#x bytes @ %#x %s\n", + len, off, ret ? "ERROR" : "OK"); + + return ret; +} + +static int do_qspihdr_check(int argc, char * const argv[], int flag) +{ + u32 buf; + unsigned long addr; + char *endp; + void *tmp; + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) + int off = QSPI_HDR_OFF + QSPI_HDR_TAG_OFF; + int tag = QSPI_HDR_TAG; +#else + int off = FSPI_HDR_OFF + FSPI_HDR_TAG_OFF; + int tag = FSPI_HDR_TAG; +#endif + + if (argc == 3) { + /* check data in memory */ + addr = simple_strtoul(argv[2], &endp, 16); + + tmp = map_physmem(addr + off, 4, MAP_WRBACK); + if (!tmp) { + printf("Failed to map physical memory\n"); + return 1; + } + + if (*(u32 *)tmp == tag) { + if (flag & FLAG_VERBOSE) + printf("Found boot config header in memory\n"); + unmap_physmem(tmp, 4); + return 0; + } else { + if (flag & FLAG_VERBOSE) + printf("NO boot config header in memory\n"); + unmap_physmem(tmp, 4); + return 1; + } + } else { + spi_flash_read(flash, off, 4, &buf); + + if (buf == tag) { + if (flag & FLAG_VERBOSE) + printf("Found boot config header in Q(F)SPI\n"); + return 0; + } else { + if (flag & FLAG_VERBOSE) + printf("NO boot config header in Q(F)SPI\n"); + return 1; + } + } +} + +static void hdr_dump(void *data) +{ +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) + struct qspi_config_parameter *hdr = + (struct qspi_config_parameter *)data; +#else + struct fspi_config_parameter *hdr = + (struct fspi_config_parameter *)data; +#endif + int i; + +#define PH(mem, cnt) ( \ +{ \ + if (cnt > 1) { \ + int len = strlen(#mem); \ + char *sub = strchr(#mem, '['); \ + if (sub) \ + *sub = '\0'; \ + for (i = 0; i < cnt; ++i) \ + printf(" %s[%02d%-*s = %08x\n", \ + #mem, i, 25 - len, "]", \ + (u32)*(&hdr->mem + i)); \ + } else { \ + printf(" %-25s = %0*x\n", \ + #mem, (int)sizeof(hdr->mem), hdr->mem); \ + } \ +} \ +) + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) + PH(dqs_loopback, 1); + PH(hold_delay, 1); + PH(hsphs, 1); + PH(hsdly, 1); + PH(device_quad_mode_en, 1); + PH(write_cmd_ipcr, 1); + PH(write_enable_ipcr, 1); + PH(cs_hold_time, 1); + PH(cs_setup_time, 1); + PH(sflash_A1_size, 1); + PH(sflash_A2_size, 1); + PH(sflash_B1_size, 1); + PH(sflash_B2_size, 1); + PH(sclk_freq, 1); + PH(busy_bit_offset, 1); + PH(busy_bit_polarity, 1); + PH(sflash_type, 1); + PH(sflash_port, 1); + PH(ddr_mode_enable, 1); + PH(dqs_enable, 1); + PH(parallel_mode_enable, 1); + PH(portA_cs1, 1); + PH(portB_cs1, 1); + PH(fsphs, 1); + PH(fsdly, 1); + PH(ddrsmp, 1); + PH(command_seq[0], 64); + PH(read_status_ipcr, 1); + PH(enable_dqs_phase, 1); + PH(config_cmds_en, 1); + PH(config_cmds[0], 4); + PH(config_cmds_args[0], 4); + PH(dqs_pad_setting_override, 1); + PH(sclk_pad_setting_override, 1); + PH(data_pad_setting_override, 1); + PH(cs_pad_setting_override, 1); + PH(dqs_loopback_internal, 1); + PH(dqs_phase_sel, 1); + PH(dqs_fa_delay_chain_sel, 1); + PH(dqs_fb_delay_chain_sel, 1); + PH(sclk_fa_delay_chain_sel, 1); + PH(sclk_fb_delay_chain_sel, 1); + PH(misc_clock_enable, 1); + PH(tag, 1); +#else + PH(tag, 1); + PH(version, 1); + PH(readSampleClkSrc, 1); + PH(dataHoldTime, 1); + PH(dataSetupTime, 1); + PH(columnAddressWidth, 1); + PH(deviceModeCfgEnable, 1); + PH(deviceModeSeq, 1); + PH(deviceModeArg, 1); + PH(configCmdEnable, 1); + PH(configCmdSeqs[0], 4); + PH(configCmdArgs[0], 4); + PH(controllerMiscOption, 1); + PH(deviceType, 1); + PH(sflashPadType, 1); + PH(serialClkFreq, 1); + PH(lutCustomSeqEnable, 1); + PH(sflashA1Size, 1); + PH(sflashA2Size, 1); + PH(sflashB1Size, 1); + PH(sflashB2Size, 1); + PH(csPadSettingOverride, 1); + PH(sclkPadSettingOverride, 1); + PH(dataPadSettingOverride, 1); + PH(dqsPadSettingOverride, 1); + PH(timeoutInMs, 1); + PH(commandInterval, 1); + PH(dataValidTime[0], 2); + PH(busyOffset, 1); + PH(busyBitPolarity, 1); + PH(lookupTable[0], 64); + PH(lutCustomSeq[0], 12); + PH(pageSize, 1); + PH(sectorSize, 1); +#endif +} + +static int do_qspihdr_dump(int argc, char * const argv[]) +{ + unsigned long addr; + char *endp; + void *tmp; + void *buf; + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) + int off = QSPI_HDR_OFF; +#else + int off = FSPI_HDR_OFF; +#endif + + if (argc == 3) { + /* check data in memory */ + if (do_qspihdr_check(3, argv, FLAG_VERBOSE)) { + /* return 0 in any cases */ + return 0; + } + + addr = simple_strtoul(argv[2], &endp, 16); + + tmp = map_physmem(addr + off, HDR_LEN, MAP_WRBACK); + if (!tmp) { + printf("Failed to map physical memory\n"); + return 1; + } + + hdr_dump(tmp); + unmap_physmem(tmp, HDR_LEN); + } else { + /* check data in Q(F)SPI */ + buf = malloc(HDR_LEN); + if (!buf) { + printf("Failed to alloc memory\n"); + /* return 0 in any cases */ + return 0; + } + + spi_flash_read(flash, off, HDR_LEN, buf); + + hdr_dump(buf); + free(buf); + } + + return 0; +} + +static int do_qspihdr_init(int argc, char * const argv[]) +{ + unsigned long addr, len; + char *endp; + int total_len; + void *tmp; + void *buf; + bool hdr_flag = false; + int ret; + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) + int hdr_off = QSPI_HDR_OFF; + int data_off = QSPI_DATA_OFF; +#else + int hdr_off = FSPI_HDR_OFF; + int data_off = FSPI_DATA_OFF; + + safe_config->fspi_hdr_config.pageSize = flash->page_size; + safe_config->fspi_hdr_config.sectorSize = flash->sector_size; +#endif + + addr = simple_strtoul(argv[2], &endp, 16); + len = simple_strtoul(argv[3], &endp, 16); + + total_len = data_off + len; + if (total_len > flash->size) { + printf("Error: length %lx over flash size (%#x)\n", + len, flash->size); + return 1; + } + + /* check if header exists in this memory area*/ + if (do_qspihdr_check(3, argv, 0) == 0) + hdr_flag = true; + + tmp = map_physmem(addr, len, MAP_WRBACK); + if (!tmp) { + printf("Failed to map physical memory\n"); + return 1; + } + + if (hdr_flag) + goto burn_image; + + buf = malloc(total_len); + if (!buf) { + printf("Failed to alloc memory\n"); + unmap_physmem(tmp, total_len); + return 1; + } + + memset(buf, 0xff, total_len); + memcpy(buf + hdr_off, safe_config, HDR_LEN); + memcpy(buf + data_off, tmp, len); + +burn_image: + if (hdr_flag) { + ret = qspi_erase_update(flash, 0, len, tmp); + } else { + ret = qspi_erase_update(flash, 0, total_len, buf); + free(buf); + } + + unmap_physmem(tmp, total_len); + return ret; +} + +static int do_qspihdr_update(int argc, char * const argv[]) +{ + int len; + int size; + void *buf; + int ret; + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_ARCH_MX7ULP) + int hdr_off = QSPI_HDR_OFF; +#else + int hdr_off = FSPI_HDR_OFF; +#endif + + len = hdr_off + HDR_LEN; + size = ROUND(len, flash->sector_size); + + buf = malloc(size); + if (!buf) { + printf("Failed to alloc memory\n"); + return 1; + } + + spi_flash_read(flash, 0, size, buf); + memcpy(buf + hdr_off, safe_config, HDR_LEN); + + ret = qspi_erase_update(flash, 0, size, buf); + free(buf); + + return ret; +} + +static int do_qspihdr(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd; + unsigned int bus = CONFIG_SF_DEFAULT_BUS; + unsigned int cs = CONFIG_SF_DEFAULT_CS; + unsigned int speed = CONFIG_SF_DEFAULT_SPEED; + unsigned int mode = CONFIG_SF_DEFAULT_MODE; + int flags = 0; + int ret; + + if (argc < 2) + goto usage; + +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new, *bus_dev; + + ret = spi_find_bus_and_cs(bus, cs, &bus_dev, &new); + if (!ret) + device_remove(new, DM_REMOVE_NORMAL); + flash = NULL; + ret = spi_flash_probe_bus_cs(bus, cs, speed, mode, &new); + if (ret) { + printf("Failed to initialize SPI flash at %u:%u (error %d)\n", + bus, cs, ret); + return 1; + } + flash = dev_get_uclass_priv(new); +#endif + + cmd = argv[1]; + + if (strcmp(cmd, "check") == 0) + return do_qspihdr_check(argc, argv, flags | FLAG_VERBOSE); + + if (strcmp(cmd, "dump") == 0) + return do_qspihdr_dump(argc, argv); + + if (strcmp(cmd, "init") == 0) { + if (argc < 5) + goto usage; + return do_qspihdr_init(argc, argv); + } + + if (strcmp(cmd, "update") == 0) { + if (argc < 3) + goto usage; + return do_qspihdr_update(argc, argv); + } + + return 0; +usage: + return CMD_RET_USAGE; +} + +static char qspihdr_help_text[] = + "check [addr] - check if boot config already exists, 0-yes, 1-no\n" + " with addr, it will check data in memory of this addr\n" + " without addr, it will check data in Q(F)SPI chip\n" + "qspihdr dump [addr] - dump the header information, if exists\n" + " with addr, it will check data in memory of this addr\n" + " without addr, it will check data in Q(F)SPI chip\n" + "qspihdr init addr len safe - burn data to Q(F)SPI with header\n" + " if data contains header, it will be used, otherwise,\n" + " safe: most common header, single line, sdr, low freq\n" + "qspihdr update safe - only update the header in Q(F)SPI\n"; + +U_BOOT_CMD(qspihdr, 5, 1, do_qspihdr, + "Q(F)SPI Boot Config sub-system", + qspihdr_help_text +); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 38b87ed5c39..a96b2c3d30c 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -27,6 +27,10 @@ #include #include +#ifdef CONFIG_VIDEO_GIS +#include +#endif + #ifdef CONFIG_FSL_ESDHC_IMX #include #endif @@ -40,7 +44,10 @@ u32 get_imx_reset_cause(void) if (reset_cause == -1) { reset_cause = readl(&src_regs->srsr); /* preserve the value for U-Boot proper */ -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ANDROID_BOOT_IMAGE) + /* We will read the ssrs states later for android so we don't + * clear the states here. + */ writel(reset_cause, &src_regs->srsr); #endif } @@ -91,6 +98,17 @@ static char *get_reset_cause(void) return "unknown reset"; } } + +#ifdef CONFIG_ANDROID_BOOT_IMAGE +void get_reboot_reason(char *ret) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + + strcpy(ret, (const char *)get_reset_cause()); + /* clear the srsr here, its state has been recorded in reset_cause */ + writel(reset_cause, &src_regs->srsr); +} +#endif #endif #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) @@ -117,7 +135,13 @@ const char *get_imx_type(u32 imxtype) case MXC_CPU_IMX8MNDL: return "8MNano DualLite"; /* Dual-core Lite version */ case MXC_CPU_IMX8MNSL: - return "8MNano SoloLite"; /* Single-core Lite version */ + return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */ + case MXC_CPU_IMX8MNUQ: + return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */ + case MXC_CPU_IMX8MNUD: + return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */ + case MXC_CPU_IMX8MNUS: + return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */ case MXC_CPU_IMX8MM: return "8MMQ"; /* Quad-core version of the imx8mm */ case MXC_CPU_IMX8MML: @@ -177,6 +201,10 @@ int print_cpuinfo(void) { u32 cpurev; __maybe_unused u32 max_freq; +#if defined(CONFIG_DBG_MONITOR) + struct dbg_monitor_regs *dbg = + (struct dbg_monitor_regs *)DEBUG_MONITOR_BASE_ADDR; +#endif cpurev = get_cpu_rev(); @@ -184,7 +212,7 @@ int print_cpuinfo(void) struct udevice *thermal_dev; int cpu_tmp, minc, maxc, ret; - printf("CPU: Freescale i.MX%s rev%d.%d", + printf("CPU: i.MX%s rev%d.%d", get_imx_type((cpurev & 0x1FF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0); @@ -196,13 +224,14 @@ int print_cpuinfo(void) mxc_get_clock(MXC_ARM_CLK) / 1000000); } #else - printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + printf("CPU: i.MX%s rev%d.%d at %d MHz\n", get_imx_type((cpurev & 0x1FF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); #endif +#ifdef ENABLE_TMU_MESSAGE #if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU) puts("CPU: "); switch (get_cpu_temp_grade(&minc, &maxc)) { @@ -233,6 +262,15 @@ int print_cpuinfo(void) } puts("\n"); #endif +#endif + +#if defined(CONFIG_DBG_MONITOR) + if (readl(&dbg->snvs_addr)) + printf("DBG snvs regs addr 0x%x, data 0x%x, info 0x%x\n", + readl(&dbg->snvs_addr), + readl(&dbg->snvs_data), + readl(&dbg->snvs_info)); +#endif printf("Reset cause: %s\n", get_reset_cause()); return 0; @@ -302,10 +340,17 @@ void arch_preboot_os(void) #endif } #endif +#if defined(CONFIG_LDO_BYPASS_CHECK) + ldo_mode_set(check_ldo_bypass()); +#endif #if defined(CONFIG_VIDEO_IPUV3) /* disable video before launching O/S */ ipuv3_fb_shutdown(); #endif +#ifdef CONFIG_VIDEO_GIS + /* Entry for GIS */ + mxc_disable_gis(); +#endif #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO) lcdif_power_down(); #endif @@ -430,8 +475,8 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) *minc = -20; *maxc = 105; } else { - *minc = 0; - *maxc = 95; + *minc = -40; + *maxc = 155; } } return val; diff --git a/arch/arm/mach-imx/dt_optee.c b/arch/arm/mach-imx/dt_optee.c new file mode 100644 index 00000000000..7c2fe79e386 --- /dev/null +++ b/arch/arm/mach-imx/dt_optee.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ +#include +#include +#include +#include +#include + +#ifdef CONFIG_OF_SYSTEM_SETUP +int ft_add_optee_node(void *fdt, struct bd_info *bd) +{ + const char *path, *subpath; + int ret = 0; + int offs; + phys_addr_t optee_start; + size_t optee_size; + + /* Not let uboot create the node */ + if (CONFIG_IS_ENABLED(XEN)) + return 0; + /* + * No TEE space allocated indicating no TEE running, so no + * need to add optee node in dts + */ + if (!rom_pointer[1]) + return 0; + +#ifdef CONFIG_OF_LIBFDT_OVERLAY + if (rom_pointer[2]) { + debug("OP-TEE: applying overlay on 0x%lx\n",rom_pointer[2]); + ret = fdt_check_header((void*)rom_pointer[2]); + if (ret == 0) { + /* Copy the fdt overlay to next 1M and use copied overlay */ + memcpy((void *)(rom_pointer[2] + SZ_1M), (void *)rom_pointer[2], + fdt_totalsize((void*)rom_pointer[2])); + ret = fdt_overlay_apply_verbose(fdt, (void*)(rom_pointer[2] + SZ_1M)); + if (ret == 0) { + debug("Overlay applied with success"); + fdt_pack(fdt); + return 0; + } + } + } + /* Fallback to previous implementation */ +#endif + + optee_start = (phys_addr_t)rom_pointer[0]; + optee_size = rom_pointer[1] - OPTEE_SHM_SIZE; + + offs = fdt_increase_size(fdt, 512); + if (offs) { + printf("No Space for dtb\n"); + return -1; + } + + path = "/firmware"; + offs = fdt_path_offset(fdt, path); + if (offs < 0) { + offs = add_dt_path_subnode(fdt, "/", "firmware"); + if (offs < 0) + return -1; + } + + subpath = "optee"; + offs = fdt_add_subnode(fdt, offs, subpath); + if (offs < 0) { + printf("Could not create %s node.\n", subpath); + return -1; + } + + fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz"); + fdt_setprop_string(fdt, offs, "method", "smc"); + + ret = add_res_mem_dt_node(fdt, "optee_core", optee_start, optee_size); + if (ret < 0) { + printf("Could not create optee_core node.\n"); + return -1; + } + + ret = add_res_mem_dt_node(fdt, "optee_shm", optee_start + optee_size, + OPTEE_SHM_SIZE); + if (ret < 0) { + printf("Could not create optee_shm node.\n"); + return -1; + } + return ret; +} +#endif diff --git a/arch/arm/mach-imx/hab.c b/arch/arm/mach-imx/hab.c index d0757d8b66a..2c502f8b96f 100644 --- a/arch/arm/mach-imx/hab.c +++ b/arch/arm/mach-imx/hab.c @@ -14,6 +14,11 @@ #include #include #include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; #define ALIGN_SIZE 0x1000 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8 @@ -21,8 +26,15 @@ #define MX6SL_PU_IROM_MMU_EN_VAR 0x00901c60 #define IS_HAB_ENABLED_BIT \ (is_soc_type(MXC_SOC_MX7ULP) ? 0x80000000 : \ - (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)) + ((is_soc_type(MXC_SOC_MX7) || is_soc_type(MXC_SOC_IMX8M))? 0x2000000 : 0x2)) + +#ifdef CONFIG_MX7ULP +#define HAB_M4_PERSISTENT_START ((soc_rev() >= CHIP_REV_2_0) ? 0x20008040 : \ + 0x20008180) +#define HAB_M4_PERSISTENT_BYTES 0xB80 +#endif +#define DEBUG 1 static int ivt_header_error(const char *err_str, struct ivt_header *ivt_hdr) { printf("%s magic=0x%x length=0x%02x version=0x%x\n", err_str, @@ -41,13 +53,200 @@ static int verify_ivt_header(struct ivt_header *ivt_hdr) if (be16_to_cpu(ivt_hdr->length) != IVT_TOTAL_LENGTH) result = ivt_header_error("bad length", ivt_hdr); - if (ivt_hdr->version != IVT_HEADER_V1 && - ivt_hdr->version != IVT_HEADER_V2) + if ((ivt_hdr->version & HAB_MAJ_MASK) != HAB_MAJ_VER) result = ivt_header_error("bad version", ivt_hdr); return result; } +#ifdef CONFIG_ARM64 +static volatile gd_t *gd_save; +#endif + +static inline void save_gd(void) +{ +#ifdef CONFIG_ARM64 + gd_save = gd; +#endif +} + +static inline void restore_gd(void) +{ +#ifdef CONFIG_ARM64 + /* + * Make will already error that reserving x18 is not supported at the + * time of writing, clang: error: unknown argument: '-ffixed-x18' + */ + __asm__ volatile("mov x18, %0\n" : : "r" (gd_save)); +#endif +} + +enum hab_status hab_rvt_report_event(enum hab_status status, uint32_t index, + uint8_t *event, size_t *bytes) +{ + enum hab_status ret; + hab_rvt_report_event_t *hab_rvt_report_event_func; + hab_rvt_report_event_func = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + struct arm_smccc_res res; + arm_smccc_smc(IMX_SIP_HAB, IMX_SIP_HAB_REPORT_EVENT, (unsigned long)index, + (unsigned long)event, (unsigned long)bytes, 0, 0, 0, &res); + ret = (enum hab_status)res.a0; + + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_report_event_func(status, index, event, bytes); + restore_gd(); + + return ret; + +} + +enum hab_status hab_rvt_report_status(enum hab_config *config, + enum hab_state *state) +{ + enum hab_status ret; + hab_rvt_report_status_t *hab_rvt_report_status_func; + hab_rvt_report_status_func = (hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + struct arm_smccc_res res; + arm_smccc_smc(IMX_SIP_HAB, IMX_SIP_HAB_REPORT_STATUS, + (unsigned long)config, (unsigned long)state, 0, 0, 0, 0, &res); + ret = (enum hab_status)res.a0; + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_report_status_func(config, state); + restore_gd(); + + return ret; +} + +enum hab_status hab_rvt_entry(void) +{ + enum hab_status ret; + hab_rvt_entry_t *hab_rvt_entry_func; + hab_rvt_entry_func = (hab_rvt_entry_t *)HAB_RVT_ENTRY; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + struct arm_smccc_res res; + arm_smccc_smc(IMX_SIP_HAB, IMX_SIP_HAB_ENTRY, 0, 0, 0, 0, 0, 0, &res); + ret = (enum hab_status)res.a0; + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_entry_func(); + restore_gd(); + + return ret; +} + +enum hab_status hab_rvt_exit(void) +{ + enum hab_status ret; + hab_rvt_exit_t *hab_rvt_exit_func; + hab_rvt_exit_func = (hab_rvt_exit_t *)HAB_RVT_EXIT; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + struct arm_smccc_res res; + arm_smccc_smc(IMX_SIP_HAB, IMX_SIP_HAB_EXIT, 0, 0, 0, 0, 0, 0, &res); + ret = (enum hab_status)res.a0; + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_exit_func(); + restore_gd(); + + return ret; +} + +void hab_rvt_failsafe(void) +{ + hab_rvt_failsafe_t *hab_rvt_failsafe_func; + hab_rvt_failsafe_func = (hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + arm_smccc_smc(IMX_SIP_HAB, IMX_SIP_HAB_FAILSAFE, 0, 0, 0, 0, 0, 0, NULL); + return; + } +#endif + + save_gd(); + hab_rvt_failsafe_func(); + restore_gd(); +} + +enum hab_status hab_rvt_check_target(enum hab_target type, const void *start, + size_t bytes) +{ + enum hab_status ret; + hab_rvt_check_target_t *hab_rvt_check_target_func; + hab_rvt_check_target_func = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + struct arm_smccc_res res; + arm_smccc_smc(IMX_SIP_HAB, IMX_SIP_HAB_CHECK_TARGET, (unsigned long)type, + (unsigned long)start, (unsigned long)bytes, 0, 0, 0, &res); + ret = (enum hab_status)res.a0; + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_check_target_func(type, start, bytes); + restore_gd(); + + return ret; +} + +void *hab_rvt_authenticate_image(uint8_t cid, ptrdiff_t ivt_offset, + void **start, size_t *bytes, hab_loader_callback_f_t loader) +{ + void *ret; + hab_rvt_authenticate_image_t *hab_rvt_authenticate_image_func; + hab_rvt_authenticate_image_func = (hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE; + +#if defined(CONFIG_ARM64) + if (current_el() != 3) { + /* call sip */ + struct arm_smccc_res res; + arm_smccc_smc(IMX_SIP_HAB, IMX_SIP_HAB_AUTHENTICATE, (unsigned long)ivt_offset, + (unsigned long)start, (unsigned long)bytes, 0, 0, 0, &res); + ret = (void *)res.a0; + return ret; + } +#endif + + save_gd(); + ret = hab_rvt_authenticate_image_func(cid, ivt_offset, start, bytes, loader); + restore_gd(); + + return ret; +} + #if !defined(CONFIG_SPL_BUILD) #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */ @@ -253,12 +452,6 @@ static int get_hab_status(void) size_t bytes = sizeof(event_data); /* Event size in bytes */ enum hab_config config = 0; enum hab_state state = 0; - hab_rvt_report_event_t *hab_rvt_report_event; - hab_rvt_report_status_t *hab_rvt_report_status; - - hab_rvt_report_event = (hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT; - hab_rvt_report_status = - (hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS; if (imx_hab_is_enabled()) puts("\nSecure boot enabled\n"); @@ -270,8 +463,8 @@ static int get_hab_status(void) printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", config, state); - /* Display HAB Error events */ - while (hab_rvt_report_event(HAB_FAILURE, index, event_data, + /* Display HAB events */ + while (hab_rvt_report_event(HAB_STS_ANY, index, event_data, &bytes) == HAB_SUCCESS) { puts("\n"); printf("--------- HAB Event %d -----------------\n", @@ -292,15 +485,99 @@ static int get_hab_status(void) return 0; } +#ifdef CONFIG_MX7ULP + +static int get_record_len(struct record *rec) +{ + return (size_t)((rec->len[0] << 8) + (rec->len[1])); +} + +static int get_hab_status_m4(void) +{ + unsigned int index = 0; + uint8_t event_data[128]; + size_t record_len, offset = 0; + enum hab_config config = 0; + enum hab_state state = 0; + + if (imx_hab_is_enabled()) + puts("\nSecure boot enabled\n"); + else + puts("\nSecure boot disabled\n"); + + /* + * HAB in both A7 and M4 gather the security state + * and configuration of the chip from + * shared SNVS module + */ + hab_rvt_report_status(&config, &state); + printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n", + config, state); + + struct record *rec = (struct record *)(HAB_M4_PERSISTENT_START); + + record_len = get_record_len(rec); + + /* Check if HAB persistent memory is valid */ + if (rec->tag != HAB_TAG_EVT_DEF || + record_len != sizeof(struct evt_def) || + (rec->par & HAB_MAJ_MASK) != HAB_MAJ_VER) { + puts("\nERROR: Invalid HAB persistent memory\n"); + return 1; + } + + /* Parse events in HAB M4 persistent memory region */ + while (offset < HAB_M4_PERSISTENT_BYTES) { + rec = (struct record *)(HAB_M4_PERSISTENT_START + offset); + + record_len = get_record_len(rec); + + if (rec->tag == HAB_TAG_EVT) { + memcpy(&event_data, rec, record_len); + puts("\n"); + printf("--------- HAB Event %d -----------------\n", + index + 1); + puts("event data:\n"); + display_event(event_data, record_len); + puts("\n"); + index++; + } + + offset += record_len; + + /* Ensure all records start on a word boundary */ + if ((offset % 4) != 0) + offset = offset + (4 - (offset % 4)); + } + + if (!index) + puts("No HAB Events Found!\n\n"); + + return 0; +} +#endif + static int do_hab_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { +#ifdef CONFIG_MX7ULP + if ((argc > 2)) { + cmd_usage(cmdtp); + return 1; + } + + if (strcmp("m4", argv[1]) == 0) + get_hab_status_m4(); + else + get_hab_status(); +#else if ((argc != 1)) { cmd_usage(cmdtp); return 1; } get_hab_status(); +#endif return 0; } @@ -353,14 +630,11 @@ static int do_authenticate_image(struct cmd_tbl *cmdtp, int flag, int argc, static int do_hab_failsafe(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - hab_rvt_failsafe_t *hab_rvt_failsafe; - if (argc != 1) { cmd_usage(cmdtp); return 1; } - hab_rvt_failsafe = (hab_rvt_failsafe_t *)HAB_RVT_FAILSAFE; hab_rvt_failsafe(); return 0; @@ -406,11 +680,20 @@ static int do_authenticate_image_or_failover(struct cmd_tbl *cmdtp, int flag, return ret; } +#ifdef CONFIG_MX7ULP +U_BOOT_CMD( + hab_status, CONFIG_SYS_MAXARGS, 2, do_hab_status, + "display HAB status and events", + "hab_status - A7 HAB event and status\n" + "hab_status m4 - M4 HAB event and status" + ); +#else U_BOOT_CMD( hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status, "display HAB status", "" ); +#endif U_BOOT_CMD( hab_auth_img, 4, 0, do_authenticate_image, @@ -493,7 +776,7 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes) return false; } - csf_hdr = (u8 *)ivt->csf; + csf_hdr = (u8 *)(ulong)ivt->csf; /* Verify if CSF Header exist */ if (*csf_hdr != HAB_CMD_HDR) { @@ -542,6 +825,48 @@ static bool csf_is_valid(struct ivt *ivt, ulong start_addr, size_t bytes) return true; } +/* + * Validate IVT structure of the image being authenticated + */ +static int validate_ivt(struct ivt *ivt_initial) +{ + struct ivt_header *ivt_hdr = &ivt_initial->hdr; + + if ((ulong)ivt_initial & 0x3) { + puts("Error: Image's start address is not 4 byte aligned\n"); + return 0; + } + + /* Check IVT fields before allowing authentication */ + if ((!verify_ivt_header(ivt_hdr)) && \ + (ivt_initial->entry != 0x0) && \ + (ivt_initial->reserved1 == 0x0) && \ + (ivt_initial->self == \ + (uint32_t)((ulong)ivt_initial & 0xffffffff)) && \ + (ivt_initial->csf != 0x0) && \ + (ivt_initial->reserved2 == 0x0)) { + /* Report boot failure if DCD pointer is found in IVT */ + if (ivt_initial->dcd != 0x0) + puts("Error: DCD pointer must be 0\n"); + else + return 1; + } + + puts("Error: Invalid IVT structure\n"); + puts("\nAllowed IVT structure:\n"); + puts("IVT HDR = 0x4X2000D1\n"); + puts("IVT ENTRY = 0xXXXXXXXX\n"); + puts("IVT RSV1 = 0x0\n"); + puts("IVT DCD = 0x0\n"); /* Recommended */ + puts("IVT BOOT_DATA = 0xXXXXXXXX\n"); /* Commonly 0x0 */ + puts("IVT SELF = 0xXXXXXXXX\n"); /* = ddr_start + ivt_offset */ + puts("IVT CSF = 0xXXXXXXXX\n"); + puts("IVT RSV2 = 0x0\n"); + + /* Invalid IVT structure */ + return 0; +} + bool imx_hab_is_enabled(void) { struct imx_sec_config_fuse_t *fuse = @@ -561,29 +886,16 @@ bool imx_hab_is_enabled(void) int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, uint32_t ivt_offset) { - uint32_t load_addr = 0; + ulong load_addr = 0; size_t bytes; - uint32_t ivt_addr = 0; + ulong ivt_addr = 0; int result = 1; ulong start; - hab_rvt_authenticate_image_t *hab_rvt_authenticate_image; - hab_rvt_entry_t *hab_rvt_entry; - hab_rvt_exit_t *hab_rvt_exit; - hab_rvt_check_target_t *hab_rvt_check_target; struct ivt *ivt; - struct ivt_header *ivt_hdr; enum hab_status status; - hab_rvt_authenticate_image = - (hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE; - hab_rvt_entry = (hab_rvt_entry_t *)HAB_RVT_ENTRY; - hab_rvt_exit = (hab_rvt_exit_t *)HAB_RVT_EXIT; - hab_rvt_check_target = (hab_rvt_check_target_t *)HAB_RVT_CHECK_TARGET; - - if (!imx_hab_is_enabled()) { + if (!imx_hab_is_enabled()) puts("hab fuse not enabled\n"); - return 0; - } printf("\nAuthenticate image from DDR location 0x%x...\n", ddr_start); @@ -591,26 +903,12 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, hab_caam_clock_enable(1); /* Calculate IVT address header */ - ivt_addr = ddr_start + ivt_offset; + ivt_addr = (ulong) (ddr_start + ivt_offset); ivt = (struct ivt *)ivt_addr; - ivt_hdr = &ivt->hdr; /* Verify IVT header bugging out on error */ - if (verify_ivt_header(ivt_hdr)) - goto hab_authentication_exit; - - /* Verify IVT body */ - if (ivt->self != ivt_addr) { - printf("ivt->self 0x%08x pointer is 0x%08x\n", - ivt->self, ivt_addr); + if (!validate_ivt(ivt)) goto hab_authentication_exit; - } - - /* Verify if IVT DCD pointer is NULL */ - if (ivt->dcd) { - puts("Error: DCD pointer must be NULL\n"); - goto hab_authentication_exit; - } start = ddr_start; bytes = image_size; @@ -624,14 +922,14 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, goto hab_exit_failure_print_status; } - status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)ddr_start, bytes); + status = hab_rvt_check_target(HAB_TGT_MEMORY, (void *)(ulong)ddr_start, bytes); if (status != HAB_SUCCESS) { - printf("HAB check target 0x%08x-0x%08x fail\n", - ddr_start, ddr_start + bytes); + printf("HAB check target 0x%08x-0x%08lx fail\n", + ddr_start, ddr_start + (ulong)bytes); goto hab_exit_failure_print_status; } #ifdef DEBUG - printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n", ivt_offset, ivt_addr); + printf("\nivt_offset = 0x%x, ivt addr = 0x%lx\n", ivt_offset, ivt_addr); printf("ivt entry = 0x%08x, dcd = 0x%08x, csf = 0x%08x\n", ivt->entry, ivt->dcd, ivt->csf); puts("Dumping IVT\n"); @@ -649,6 +947,8 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, printf("\tstart = 0x%08lx\n", start); printf("\tbytes = 0x%x\n", bytes); #endif + +#ifndef CONFIG_ARM64 /* * If the MMU is enabled, we have to notify the ROM * code, or it won't flush the caches when needed. @@ -676,8 +976,9 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, writel(1, MX6SL_PU_IROM_MMU_EN_VAR); } } +#endif - load_addr = (uint32_t)hab_rvt_authenticate_image( + load_addr = (ulong)hab_rvt_authenticate_image( HAB_CID_UBOOT, ivt_offset, (void **)&start, (size_t *)&bytes, NULL); @@ -693,8 +994,26 @@ int imx_hab_authenticate_image(uint32_t ddr_start, uint32_t image_size, hab_authentication_exit: - if (load_addr != 0) + if (load_addr != 0 || !imx_hab_is_enabled()) result = 0; return result; } + +int authenticate_image(uint32_t ddr_start, uint32_t raw_image_size) +{ + uint32_t ivt_offset; + size_t bytes; + + ivt_offset = (raw_image_size + ALIGN_SIZE - 1) & + ~(ALIGN_SIZE - 1); + bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE; + + return imx_hab_authenticate_image(ddr_start, bytes, ivt_offset); +} + +int authenticate_buffer(void *buffer, size_t size) +{ + u32 ivt_offset = (( size >> 12 ) << 12 ); + return imx_hab_authenticate_image( (uint32_t) buffer, size, ivt_offset ); +} diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c index d36347d8e82..9a8b033031d 100644 --- a/arch/arm/mach-imx/i2c-mxv7.c +++ b/arch/arm/mach-imx/i2c-mxv7.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2012 Boundary Devices Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #include #include @@ -33,13 +35,36 @@ int force_idle_bus(void *priv) printf("%s: sda=%d scl=%d sda.gp=0x%x scl.gp=0x%x\n", __func__, sda, scl, p->sda.gp, p->scl.gp); + gpio_direction_output(p->scl.gp, 1); + udelay(1000); /* Send high and low on the SCL line */ for (i = 0; i < 9; i++) { - gpio_direction_output(p->scl.gp, 0); + gpio_direction_output(p->scl.gp, 1); udelay(50); - gpio_direction_input(p->scl.gp); + gpio_direction_output(p->scl.gp, 0); udelay(50); } + + /* Simulate the NACK */ + gpio_direction_output(p->sda.gp, 1); + udelay(50); + gpio_direction_output(p->scl.gp, 1); + udelay(50); + gpio_direction_output(p->scl.gp, 0); + udelay(50); + + /* Simulate the STOP signal */ + gpio_direction_output(p->sda.gp, 0); + udelay(50); + gpio_direction_output(p->scl.gp, 1); + udelay(50); + gpio_direction_output(p->sda.gp, 1); + udelay(50); + + /* Get the bus status */ + gpio_direction_input(p->sda.gp); + gpio_direction_input(p->scl.gp); + start_time = get_timer(0); for (;;) { sda = gpio_get_value(p->sda.gp); diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 04b9729109e..2f31a4f9498 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -2,11 +2,25 @@ if ARCH_IMX8 config AHAB_BOOT bool "Support i.MX8 AHAB features" + imply CMD_DEKBLOB help This option enables the support for AHAB secure boot. +config IMX_LOAD_HDMI_FIMRWARE_RX + bool "Enable HDMI rx firmware loading" + depends on ARCH_IMX8 || VIDEO_IMX_HDP_LOAD + help + This enable the hdmi rx firmware loading. It depends on the "hdprx" command. + +config IMX_LOAD_HDMI_FIMRWARE_TX + bool "Enable HDMI tx firmware loading" + depends on ARCH_IMX8 || VIDEO_IMX_HDP_LOAD + help + This enable the hdmi tx firmware loading. It depends on the "hdp" command. + config IMX8 bool + select HAS_CAAM config MU_BASE_SPL hex "MU base address used in SPL" @@ -27,6 +41,12 @@ config IMX8QXP select SPL_RECOVER_DATA_SECTION bool +config IMX8DXL + select IMX8 + select SUPPORT_SPL + select RECOVER_SPL_DATA_SECTION + bool + config SYS_SOC default "imx8" @@ -51,6 +71,12 @@ config BOOTAUX_RESERVED_MEM_SIZE hex "i.MX auxiliary core dram memory size" default 0 +config PSCI_BOARD_REBOOT + bool "Enable psci board reboot command" + depends on ARM_PSCI_FW + help + This is a optional command used to trigger system board reboot on imx8. + choice prompt "i.MX8 board select" optional @@ -84,6 +110,20 @@ config TARGET_IMX8QM_MEK bool "Support i.MX8QM MEK board" select BOARD_LATE_INIT select IMX8QM + select FSL_CAAM + select FSL_BLOB + select ARCH_MISC_INIT + select SPL_CRYPTO_SUPPORT if SPL + +config TARGET_IMX8QM_LPDDR4_VAL + bool "Support i.MX8QM lpddr4 validation board" + select BOARD_LATE_INIT + select IMX8QM + +config TARGET_IMX8QM_DDR4_VAL + bool "Support i.MX8QM ddr4 validation board" + select BOARD_LATE_INIT + select IMX8QM config TARGET_IMX8QM_ROM7720_A1 bool "Support i.MX8QM ROM-7720-A1" @@ -95,11 +135,81 @@ config TARGET_IMX8QXP_MEK bool "Support i.MX8QXP MEK board" select BOARD_LATE_INIT select IMX8QXP + select FSL_CAAM + select FSL_BLOB + select ARCH_MISC_INIT + select SPL_CRYPTO_SUPPORT if SPL + +config TARGET_IMX8QM_MEK_A53_ONLY + bool "Support i.MX8QM MEK board, cluster A53 only" + select BOARD_LATE_INIT + select IMX8QM + +config TARGET_IMX8QM_MEK_A72_ONLY + bool "Support i.MX8QM MEK board, cluster A72 only" + select BOARD_LATE_INIT + select IMX8QM + +config TARGET_IMX8QXP_LPDDR4_VAL + bool "Support i.MX8QXP lpddr4 validation board" + select BOARD_LATE_INIT + select IMX8QXP + +config TARGET_IMX8QXP_DDR3_VAL + bool "Support i.MX8QXP ddr3 validation board" + select BOARD_LATE_INIT + select IMX8QXP + +config TARGET_IMX8X_17X17_VAL + bool "Support i.MX8QXP/DX 17x17 validation board" + select BOARD_LATE_INIT + select IMX8QXP + +config TARGET_IMX8DXL_PHANTOM_MEK + bool "Support i.MX8DXL PHANTOM MEK board" + select BOARD_LATE_INIT + select IMX8QXP + select FSL_CAAM + select FSL_BLOB + select ARCH_MISC_INIT + select SPL_CRYPTO_SUPPORT if SPL + +config TARGET_IMX8DX_MEK + bool "Support i.MX8DX MEK board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QXP + select FSL_CAAM + select FSL_BLOB + select ARCH_MISC_INIT + select SPL_CRYPTO_SUPPORT if SPL + +config TARGET_IMX8DXL_EVK + bool "Support i.MX8DXL EVK board" + select BOARD_LATE_INIT + select IMX8DXL + select FSL_CAAM + select FSL_BLOB + select ARCH_MISC_INIT + select SPL_CRYPTO_SUPPORT if SPL + +config TARGET_IMX8DXL_DDR3_EVK + bool "Support i.MX8DXL EVK board" + select BOARD_LATE_INIT + select IMX8DXL + select FSL_CAAM + select FSL_BLOB + select ARCH_MISC_INIT + select SPL_CRYPTO_SUPPORT if SPL endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" +source "board/freescale/imx8qm_val/Kconfig" +source "board/freescale/imx8qxp_val/Kconfig" +source "board/freescale/imx8dxl_phantom_mek/Kconfig" +source "board/freescale/imx8dxl_evk/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile index bbb41adbe43..628b08e655a 100644 --- a/arch/arm/mach-imx/imx8/Makefile +++ b/arch/arm/mach-imx/imx8/Makefile @@ -4,11 +4,13 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += cpu.o iomux.o misc.o lowlevel_init.o +obj-y += cpu.o iomux.o misc.o lowlevel_init.o lpcg.o clock.o obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o obj-$(CONFIG_AHAB_BOOT) += ahab.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_LOAD_IMX_CONTAINER) += image.o parse-container.o -endif +else +obj-y += partition.o obj-$(CONFIG_IMX_SNVS_SEC_SC) += snvs_security_sc.o +endif diff --git a/arch/arm/mach-imx/imx8/ahab.c b/arch/arm/mach-imx/imx8/ahab.c index 6392fe267a0..4e0c180e911 100644 --- a/arch/arm/mach-imx/imx8/ahab.c +++ b/arch/arm/mach-imx/imx8/ahab.c @@ -106,7 +106,7 @@ int authenticate_os_container(ulong addr) flush_dcache_range(s, e); /* Find the memreg and set permission for seco pt */ - err = sc_rm_find_memreg(-1, &mr, s, e); + err = sc_rm_find_memreg(-1, &mr, s, e - 1); if (err) { printf("Error: can't find memreg for image load address 0x%llx, error %d\n", img->dst, err); ret = -ENOMEM; diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 9941b57b4be..4eb22ce129d 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -1,18 +1,78 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018-2020 NXP */ #include #include #include #include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; +u32 get_lpuart_clk(void) +{ + return mxc_get_clock(MXC_UART_CLK); +} + u32 mxc_get_clock(enum mxc_clock clk) { + sc_err_t err; + sc_pm_clock_rate_t clkrate; + switch (clk) { + case MXC_UART_CLK: + err = sc_pm_get_clock_rate(-1, + SC_R_UART_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get UART clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ESDHC_CLK: + err = sc_pm_get_clock_rate(-1, + SC_R_SDHC_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get uSDHC1 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ESDHC2_CLK: + err = sc_pm_get_clock_rate(-1, + SC_R_SDHC_1, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get uSDHC2 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_ESDHC3_CLK: + err = sc_pm_get_clock_rate(-1, + SC_R_SDHC_2, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get uSDHC3 clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_FEC_CLK: + err = sc_pm_get_clock_rate(-1, + SC_R_ENET_0, 2, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get ENET clk failed! err=%d\n", err); + return 0; + } + return clkrate; + case MXC_DDR_CLK: + err = sc_pm_get_clock_rate(-1, + SC_R_DRC_0, 0, &clkrate); + if (err != SC_ERR_NONE) { + printf("sc get DRC0 clk failed! err=%d\n", err); + return 0; + } + return clkrate; default: printf("Unsupported mxc_clock %d\n", clk); break; @@ -20,3 +80,351 @@ u32 mxc_get_clock(enum mxc_clock clk) return 0; } + +u32 imx_get_fecclk(void) +{ + return mxc_get_clock(MXC_FEC_CLK); +} + +static struct imx_i2c_map *get_i2c_desc(unsigned i2c_num) +{ + int i; + for (i = 0; i < ARRAY_SIZE(imx_i2c_desc); i++) { + if (imx_i2c_desc[i].index == i2c_num) + return &imx_i2c_desc[i]; + } + return NULL; +} + +int enable_i2c_clk(unsigned char enable, unsigned i2c_num) +{ + sc_err_t err; + struct imx_i2c_map *desc; + int i; + + desc = get_i2c_desc(i2c_num); + if (!desc) + return -EINVAL; + + + if (enable) + err = sc_pm_clock_enable(-1, + desc->rsrc, 2, true, false); + else + err = sc_pm_clock_enable(-1, + desc->rsrc, 2, false, false); + + if (err != SC_ERR_NONE) { + printf("i2c clock error %d\n", err); + return -EPERM; + } + + for (i = 0; i < 4; i++) { + if (desc->lpcg[i] == 0) + break; + lpcg_all_clock_on(desc->lpcg[i]); + } + + return 0; +} + +u32 imx_get_i2cclk(unsigned i2c_num) +{ + sc_err_t err; + u32 clock_rate; + struct imx_i2c_map *desc; + + desc = get_i2c_desc(i2c_num); + if (!desc) + return -EINVAL; + + err = sc_pm_get_clock_rate(-1, desc->rsrc, 2, + &clock_rate); + if (err != SC_ERR_NONE) + return 0; + + return clock_rate; +} + +void init_clk_fspi(int index) +{ + sc_err_t sciErr = 0; + sc_pm_clock_rate_t rate; + + /* Set FSPI0 clock root to 29 MHz */ + rate = 29000000; + sciErr = sc_pm_set_clock_rate(-1, SC_R_FSPI_0, SC_PM_CLK_PER, &rate); + if (sciErr != SC_ERR_NONE) { + puts("FSPI0 setrate failed\n"); + return; + } + + /* Enable FSPI0 clock root */ + sciErr = sc_pm_clock_enable(-1, SC_R_FSPI_0, SC_PM_CLK_PER, true, false); + if (sciErr != SC_ERR_NONE) { + puts("FSPI0 enable clock failed\n"); + return; + } + + lpcg_all_clock_on(FSPI_0_LPCG); + + return; +} + +void init_clk_gpmi_nand(void) +{ + sc_err_t sciErr = 0; + sc_pm_clock_rate_t rate; + + /* Set NAND BCH clock root to 50 MHz */ + rate = 50000000; + sciErr = sc_pm_set_clock_rate(-1, SC_R_NAND, SC_PM_CLK_PER, &rate); + if (sciErr != SC_ERR_NONE) { + puts("NAND BCH set rate failed\n"); + return; + } + + /* Enable NAND BCH clock root */ + sciErr = sc_pm_clock_enable(-1, SC_R_NAND, SC_PM_CLK_PER, true, false); + if (sciErr != SC_ERR_NONE) { + puts("NAND BCH enable clock failed\n"); + return; + } + + /* Set NAND GPMI clock root to 50 MHz */ + rate = 50000000; + sciErr = sc_pm_set_clock_rate(-1, SC_R_NAND, SC_PM_CLK_MST_BUS, &rate); + if (sciErr != SC_ERR_NONE) { + puts("NAND GPMI set rate failed\n"); + return; + } + + /* Enable NAND GPMI clock root */ + sciErr = sc_pm_clock_enable(-1, SC_R_NAND, SC_PM_CLK_MST_BUS, true, false); + if (sciErr != SC_ERR_NONE) { + puts("NAND GPMI enable clock failed\n"); + return; + } + + lpcg_all_clock_on(NAND_LPCG); + lpcg_all_clock_on(NAND_LPCG + 0x4); + + return; +} + +void enable_usboh3_clk(unsigned char enable) +{ +#if !defined(CONFIG_IMX8DXL) + lpcg_all_clock_on(USB_2_LPCG); +#endif + return; +} + +void init_clk_usb3(int index) +{ + sc_err_t err; + sc_pm_clock_rate_t rate; + + err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MISC, false, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MST_BUS, false, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_PER, false, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + rate = 12000000; + err = sc_pm_set_clock_rate(-1, SC_R_USB_2, SC_PM_CLK_MISC, &rate); + if (err != SC_ERR_NONE) + printf("USB3 set MISC clock rate failed!, line=%d (error = %d)\n", + __LINE__, err); + + rate = 250000000; + err = sc_pm_set_clock_rate(-1, SC_R_USB_2, SC_PM_CLK_MST_BUS, &rate); + if (err != SC_ERR_NONE) + printf("USB3 set BUS clock rate failed!, line=%d (error = %d)\n", + __LINE__, err); + + rate = 125000000; + err = sc_pm_set_clock_rate(-1, SC_R_USB_2, SC_PM_CLK_PER, &rate); + if (err != SC_ERR_NONE) + printf("USB3 set PER clock rate failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MISC, true, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MST_BUS, true, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_PER, true, false); + if (err != SC_ERR_NONE) + printf("USB3 set clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + lpcg_all_clock_on(USB_3_LPCG); + return; +} + +int cdns3_enable_clks(int index) +{ + init_clk_usb3(index); + return 0; +} + +int cdns3_disable_clks(int index) +{ + sc_err_t err; + + lpcg_all_clock_off(USB_3_LPCG); + + err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MISC, false, false); + if (err != SC_ERR_NONE) + printf("USB3 disable clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_MST_BUS, false, false); + if (err != SC_ERR_NONE) + printf("USB3 disable clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + err = sc_pm_clock_enable(-1, SC_R_USB_2, SC_PM_CLK_PER, false, false); + if (err != SC_ERR_NONE) + printf("USB3 disable clock failed!, line=%d (error = %d)\n", + __LINE__, err); + + return 0; +} + +void init_clk_usdhc(u32 index) +{ +#ifdef CONFIG_IMX8QM + sc_rsrc_t usdhcs[] = {SC_R_SDHC_0, SC_R_SDHC_1, SC_R_SDHC_2}; + u32 instances = 3; +#else + sc_rsrc_t usdhcs[] = {SC_R_SDHC_0, SC_R_SDHC_1}; + u32 instances = 2; +#endif + + sc_err_t err; + sc_pm_clock_rate_t actual = 400000000; + + if (index >= instances) + return; + + /* Must disable the clock before set clock parent */ + err = sc_pm_clock_enable(-1, usdhcs[index], SC_PM_CLK_PER, false, false); + if (err != SC_ERR_NONE) { + printf("SDHC_%d per clk enable failed!\n", index); + return; + } + + /* + * IMX8QXP USDHC_CLK_ROOT default source from DPLL, but this DPLL + * do not stable, will cause usdhc data transfer crc error. So here + * is a workaround, let USDHC_CLK_ROOT source from AVPLL. Due to + * AVPLL is fixed to 1000MHz, so here config USDHC1_CLK_ROOT to 333MHz, + * USDHC2_CLK_ROOT to 200MHz, make eMMC HS400ES work at 166MHz, and SD + * SDR104 work at 200MHz. + */ + if (is_imx8qxp()) { + err = sc_pm_set_clock_parent(-1, usdhcs[index], 2, SC_PM_PARENT_PLL1); + if (err != SC_ERR_NONE) + printf("SDHC_%d set clock parent failed!(error = %d)\n", index, err); + + if (index == 1) + actual = 200000000; + } + + err = sc_pm_set_clock_rate(-1, usdhcs[index], 2, &actual); + if (err != SC_ERR_NONE) { + printf("SDHC_%d set clock failed! (error = %d)\n", index, err); + return; + } + + if (actual != 400000000) + debug("Actual rate for SDHC_%d is %d\n", index, actual); + + err = sc_pm_clock_enable(-1, usdhcs[index], SC_PM_CLK_PER, true, false); + if (err != SC_ERR_NONE) { + printf("SDHC_%d per clk enable failed!\n", index); + return; + } + + lpcg_all_clock_on(USDHC_0_LPCG + index * 0x10000); +} + +void init_clk_fec(int index) +{ + sc_err_t err; + sc_pm_clock_rate_t rate = 24000000; + sc_rsrc_t enet[2] = {SC_R_ENET_0, SC_R_ENET_1}; + + if (index > 1) + return; + + if (index == -1) + index = 0; + + /* Disable SC_R_ENET_0 clock root */ + err = sc_pm_clock_enable(-1, enet[index], 0, false, false); + err |= sc_pm_clock_enable(-1, enet[index], 2, false, false); + err |= sc_pm_clock_enable(-1, enet[index], 4, false, false); + if (err != SC_ERR_NONE) { + printf("\nSC_R_ENET_0 set clock disable failed! (error = %d)\n", err); + return; + } + + /* Set SC_R_ENET_0 clock root to 250 MHz, the clkdiv is set to div 2 + * so finally RGMII TX clk is 125Mhz + */ + rate = 250000000; + if (is_imx8dxl() && index == 1) /* eQos */ + rate = 125000000; + + /* div = 8 clk_source = PLL_1 ss_slice #7 in verfication codes */ + err = sc_pm_set_clock_rate(-1, enet[index], 2, &rate); + if (err != SC_ERR_NONE) { + printf("\nSC_R_ENET_0 set clock ref clock 125M failed! (error = %d)\n", err); + return; + } + + /* Enable SC_R_ENET_0 clock root */ + err = sc_pm_clock_enable(-1, enet[index], 0, true, true); + err |= sc_pm_clock_enable(-1, enet[index], 2, true, true); + err |= sc_pm_clock_enable(-1, enet[index], 4, true, true); + if (err != SC_ERR_NONE) { + printf("\nSC_R_ENET_0 set clock enable failed! (error = %d)\n", err); + return; + } + + /* Configure GPR regisers */ + if (!(is_imx8dxl() && index == 1)) { + if (sc_misc_set_control(-1, enet[index], SC_C_TXCLK, 0) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_TXCLK); + /* Enable divclk */ + if (sc_misc_set_control(-1, enet[index], SC_C_CLKDIV, 1) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_CLKDIV); + } + if (sc_misc_set_control(-1, enet[index], SC_C_DISABLE_50, 1) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_DISABLE_50); + if (sc_misc_set_control(-1, enet[index], SC_C_DISABLE_125, 1) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_DISABLE_125); + if (sc_misc_set_control(-1, enet[index], SC_C_SEL_125, 0) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_SEL_125); + if (sc_misc_set_control(-1, enet[index], SC_C_IPG_STOP, 0) != SC_ERR_NONE) + printf("\nConfigure GPR registers operation(%d) failed!\n", SC_C_IPG_STOP); + + lpcg_all_clock_on(ENET_0_LPCG + index * 0x10000); +} diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 02db322f51a..4697c6ea668 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2017-2020 NXP */ #include @@ -13,12 +13,15 @@ #include #include #include +#include #include #include #include -#include +#include #include #include +#include +#include #include #include #include @@ -26,6 +29,9 @@ #include #include #include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -48,10 +54,30 @@ int arch_cpu_init(void) spl_save_restore_data(); #endif -#ifdef CONFIG_SPL_BUILD + return 0; +} + +static void power_off_all_usb(void); + +int arch_cpu_init_dm(void) +{ + struct udevice *devp; + int node, ret; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu"); + + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); + if (ret) { + printf("could not get scu %d\n", ret); + return ret; + } + + if (IS_ENABLED(CONFIG_XEN)) + return 0; + struct pass_over_info_t *pass_over; - if (is_soc_rev(CHIP_REV_A)) { + if ((is_imx8qm() || is_imx8qxp()) && is_soc_rev(CHIP_REV_A)) { pass_over = get_pass_over_info(); if (pass_over && pass_over->g_ap_mu == 0) { /* @@ -61,33 +87,214 @@ int arch_cpu_init(void) sc_misc_boot_status(-1, SC_MISC_BOOT_STATUS_SUCCESS); } } + +#if !defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) && !defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) + if (is_imx8qm()) { + ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU, + SC_PM_PW_MODE_ON); + if (ret) + return ret; + } #endif + power_off_all_usb(); + return 0; } -int arch_cpu_init_dm(void) +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) { - struct udevice *devp; +#if !defined(CONFIG_ANDROID_SUPPORT) && !defined(CONFIG_ANDROID_AUTO_SUPPORT) + struct udevice *dev; int node, ret; - node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu"); + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,sec-v4.0"); - ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &dev); if (ret) { - printf("could not get scu %d\n", ret); + printf("could not get caam jr device %d\n", ret); return ret; } + device_probe(dev); +#endif - if (is_imx8qm()) { - ret = sc_pm_set_resource_power_mode(-1, SC_R_SMMU, - SC_PM_PW_MODE_ON); - if (ret) - return ret; + return 0; +} +#endif + +#ifdef CONFIG_IMX_BOOTAUX + +#ifdef CONFIG_IMX8QM +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +{ + sc_rsrc_t core_rsrc, mu_rsrc; + sc_faddr_t tcml_addr; + u32 tcm_size = SZ_256K; /* TCML + TCMU */ + ulong addr; + + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + tcml_addr = 0x34FE0000; + mu_rsrc = SC_R_M4_0_MU_1A; + break; + case 1: + core_rsrc = SC_R_M4_1_PID0; + tcml_addr = 0x38FE0000; + mu_rsrc = SC_R_M4_1_MU_1A; + break; + default: + printf("Not support this core boot up, ID:%u\n", core_id); + return -EINVAL; + } + + addr = (sc_faddr_t)boot_private_data; + + if (addr >= tcml_addr && addr <= tcml_addr + tcm_size) { + printf("Wrong image address 0x%lx, should not in TCML\n", + addr); + return -EINVAL; + } + + printf("Power on M4 and MU\n"); + + if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + printf("Copy M4 image from 0x%lx to TCML 0x%lx\n", addr, (ulong)tcml_addr); + + if (addr != tcml_addr) + memcpy((void *)tcml_addr, (void *)addr, tcm_size); + + printf("Start M4 %u\n", core_id); + if (sc_pm_cpu_start(-1, core_rsrc, true, tcml_addr) != SC_ERR_NONE) + return -EIO; + + printf("bootaux complete\n"); + return 0; +} +#endif + +#if defined(CONFIG_IMX8QXP) || defined(CONFIG_IMX8DXL) +int arch_auxiliary_core_up(u32 core_id, ulong boot_private_data) +{ + sc_rsrc_t core_rsrc, mu_rsrc = SC_R_NONE; + sc_faddr_t aux_core_ram; + u32 size; + ulong addr; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + aux_core_ram = 0x34FE0000; + mu_rsrc = SC_R_M4_0_MU_1A; + size = SZ_256K; + break; + case 1: + core_rsrc = SC_R_DSP; + aux_core_ram = 0x596f8000; + size = SZ_2K; + break; + default: + printf("Not support this core boot up, ID:%u\n", core_id); + return -EINVAL; + } + + addr = (sc_faddr_t)boot_private_data; + + if (addr >= aux_core_ram && addr <= aux_core_ram + size) { + printf("Wrong image address 0x%lx, should not in aux core ram\n", + addr); + return -EINVAL; + } + + printf("Power on aux core %d\n", core_id); + + if (sc_pm_set_resource_power_mode(-1, core_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + + if (mu_rsrc != SC_R_NONE) { + if (sc_pm_set_resource_power_mode(-1, mu_rsrc, SC_PM_PW_MODE_ON) != SC_ERR_NONE) + return -EIO; + } + + if (core_id == 1) { + struct power_domain pd; + + if (sc_pm_clock_enable(-1, core_rsrc, SC_PM_CLK_PER, true, false) != SC_ERR_NONE) { + printf("Error enable clock\n"); + return -EIO; + } + + if (!power_domain_lookup_name("audio_sai0", &pd)) { + if (power_domain_on(&pd)) { + printf("Error power on SAI0\n"); + return -EIO; + } + } + + if (!power_domain_lookup_name("audio_ocram", &pd)) { + if (power_domain_on(&pd)) { + printf("Error power on HIFI RAM\n"); + return -EIO; + } + } + } + + printf("Copy image from 0x%lx to 0x%lx\n", addr, (ulong)aux_core_ram); + if (core_id == 0) { + /* M4 use bin file */ + memcpy((void *)aux_core_ram, (void *)addr, size); + } else { + /* HIFI use elf file */ + if (!valid_elf_image(addr)) + return -1; + addr = load_elf_image_shdr(addr); + } + + printf("Start %s\n", core_id == 0 ? "M4" : "HIFI"); + + if (sc_pm_cpu_start(-1, core_rsrc, true, aux_core_ram) != SC_ERR_NONE) + return -EIO; + + printf("bootaux complete\n"); + return 0; +} +#endif + +int arch_auxiliary_core_check_up(u32 core_id) +{ + sc_rsrc_t core_rsrc; + sc_pm_power_mode_t power_mode; + + switch (core_id) { + case 0: + core_rsrc = SC_R_M4_0_PID0; + break; +#ifdef CONFIG_IMX8QM + case 1: + core_rsrc = SC_R_M4_1_PID0; + break; +#endif + default: + printf("Not support this core, ID:%u\n", core_id); + return 0; } + if (sc_pm_get_resource_power_mode(-1, core_rsrc, &power_mode) != SC_ERR_NONE) + return 0; + + if (power_mode != SC_PM_PW_MODE_OFF) + return 1; + return 0; } +#endif int print_bootinfo(void) { @@ -139,6 +346,15 @@ enum boot_device get_boot_device(void) sc_rsrc_t dev_rsrc; +#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) + return MMC1_BOOT; +#elif defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) + return SD2_BOOT; +#endif + /* Note we only support android in EMMC SDHC0 */ + if (IS_ENABLED(CONFIG_XEN)) + return MMC1_BOOT; + sc_misc_get_boot_dev(-1, &dev_rsrc); switch (dev_rsrc) { @@ -172,6 +388,11 @@ enum boot_device get_boot_device(void) return boot_dev; } +bool is_usb_boot(void) +{ + return get_boot_device() == USB_BOOT; +} + #ifdef CONFIG_SERIAL_TAG #define FUSE_UNIQUE_ID_WORD0 16 #define FUSE_UNIQUE_ID_WORD1 17 @@ -203,10 +424,9 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif /*CONFIG_SERIAL_TAG*/ -#ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return devno; } int mmc_get_env_dev(void) @@ -214,7 +434,11 @@ int mmc_get_env_dev(void) sc_rsrc_t dev_rsrc; int devno; +#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) + dev_rsrc = SC_R_SDHC_0; +#else sc_misc_get_boot_dev(-1, &dev_rsrc); +#endif switch (dev_rsrc) { case SC_R_SDHC_0: @@ -228,15 +452,35 @@ int mmc_get_env_dev(void) break; default: /* If not boot from sd/mmc, use default value */ - return CONFIG_SYS_MMC_ENV_DEV; + return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); } return board_mmc_get_env_dev(devno); } -#endif #define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */ +static sc_faddr_t reserve_optee_shm(sc_faddr_t addr_start) +{ + /* OPTEE has a share memory at its top address, + * ATF assigns the share memory to non-secure os partition for share with kernel + * We should not add this share memory to DDR bank, as this memory is dedicated for + * optee, optee driver will memremap it and can't be used by system malloc. + */ + + sc_faddr_t optee_start = rom_pointer[0]; + sc_faddr_t optee_size = rom_pointer[1]; + + if (optee_size && optee_start <= addr_start && + addr_start < optee_start + optee_size) { + debug("optee 0x%llx 0x%llx, addr_start 0x%llx\n", + optee_start, optee_size, addr_start); + return optee_start + optee_size; + } + + return addr_start; +} + static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, sc_faddr_t *addr_end) { @@ -252,7 +496,7 @@ static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start, return -EINVAL; } debug("0x%llx -- 0x%llx\n", start, end); - *addr_start = start; + *addr_start = reserve_optee_shm(start); *addr_end = end; return 0; @@ -285,6 +529,10 @@ phys_size_t get_effective_memsize(void) end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; + + if (IS_ENABLED(CONFIG_XEN)) + return PHYS_SDRAM_1_SIZE; + for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -323,6 +571,14 @@ int dram_init(void) end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; + + if (IS_ENABLED(CONFIG_XEN)) { + gd->ram_size = PHYS_SDRAM_1_SIZE; + gd->ram_size += PHYS_SDRAM_2_SIZE; + + return 0; + } + for (mr = 0; mr < 64; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -391,6 +647,16 @@ int dram_init_banksize(void) end1 = (sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size; end2 = (sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size; + + if (IS_ENABLED(CONFIG_XEN)) { + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + + return 0; + } + for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -449,7 +715,11 @@ static u64 get_block_attrs(sc_faddr_t addr_start) addr_start <= ((sc_faddr_t)phys_sdram_1_start + phys_sdram_1_size)) || (addr_start >= phys_sdram_2_start && addr_start <= ((sc_faddr_t)phys_sdram_2_start + phys_sdram_2_size))) +#ifdef CONFIG_IMX_TRUSTY_OS + return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); +#else return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE); +#endif return attr; } @@ -490,6 +760,40 @@ void enable_caches(void) sc_faddr_t start, end; int err, i; + if (IS_ENABLED(CONFIG_XEN)) { + imx8_mem_map[0].virt = 0x00000000UL; + imx8_mem_map[0].phys = 0x00000000UL; + imx8_mem_map[0].size = 0x39000000UL; + imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + imx8_mem_map[1].virt = 0x39000000UL; + imx8_mem_map[1].phys = 0x39000000UL; + imx8_mem_map[1].size = 0x01000000UL; + imx8_mem_map[1].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); + + imx8_mem_map[2].virt = 0x40000000UL; + imx8_mem_map[2].phys = 0x40000000UL; + imx8_mem_map[2].size = 0x40000000UL; + imx8_mem_map[2].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + imx8_mem_map[3].virt = 0x80000000UL; + imx8_mem_map[3].phys = 0x80000000UL; + imx8_mem_map[3].size = 0x80000000UL; + imx8_mem_map[3].attrs = (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE); + + imx8_mem_map[4].virt = 0x100000000UL; + imx8_mem_map[4].phys = 0x100000000UL; + imx8_mem_map[4].size = 0x100000000UL; + imx8_mem_map[4].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + + icache_enable(); + dcache_enable(); + + return; + } + /* Create map for registers access from 0x1c000000 to 0x80000000*/ imx8_mem_map[0].virt = 0x1c000000UL; imx8_mem_map[0].phys = 0x1c000000UL; @@ -498,6 +802,16 @@ void enable_caches(void) PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; i = 1; + +#ifdef CONFIG_IMX_VSERVICE_SHARED_BUFFER + imx8_mem_map[i].virt = CONFIG_IMX_VSERVICE_SHARED_BUFFER; + imx8_mem_map[i].phys = CONFIG_IMX_VSERVICE_SHARED_BUFFER; + imx8_mem_map[i].size = CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE; + imx8_mem_map[i].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN; + i++; +#endif + for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) { err = get_owned_memreg(mr, &start, &end); if (!err) { @@ -561,7 +875,7 @@ u64 get_page_table_size(void) #define FUSE_MAC0_WORD1 453 #define FUSE_MAC1_WORD0 454 #define FUSE_MAC1_WORD1 455 -#elif defined(CONFIG_IMX8QXP) +#elif defined(CONFIG_IMX8QXP) || defined (CONFIG_IMX8DXL) #define FUSE_MAC0_WORD0 708 #define FUSE_MAC0_WORD1 709 #define FUSE_MAC1_WORD0 710 @@ -613,6 +927,10 @@ u32 get_cpu_rev(void) rev = (id >> 5) & 0xf; id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ + /* 8DXL uses A1/A2, so generate dummy rev to differentiate with B/C */ + if (id == MXC_CPU_IMX8DXL && rev != 0) + rev = 0x10 + rev; + return (id << 12) | rev; } @@ -656,3 +974,240 @@ bool m4_parts_booted(void) return false; } + +void disconnect_from_pc(void) +{ + int ret; + struct power_domain pd; + + if (!power_domain_lookup_name("conn_usb0", &pd)) { + ret = power_domain_on(&pd); + if (ret) { + printf("conn_usb0 Power up failed! (error = %d)\n", ret); + return; + } + + writel(0x0, USB_BASE_ADDR + 0x140); + + ret = power_domain_off(&pd); + if (ret) { + printf("conn_usb0 Power off failed! (error = %d)\n", ret); + return; + } + } else { + printf("conn_usb0 finding failed!\n"); + return; + } +} + +bool check_owned_udevice(struct udevice *dev) +{ + int ret; + sc_rsrc_t resource_id; + struct ofnode_phandle_args args; + + /* Get the resource id from its power-domain */ + ret = dev_read_phandle_with_args(dev, "power-domains", + "#power-domain-cells", 0, 0, &args); + if (ret) { + printf("no power-domains found\n"); + return false; + } + + /* Get the owner partition for resource*/ + resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE); + if (resource_id == SC_R_NONE) { + printf("Can't find the resource id for udev %s\n", dev->name); + return false; + } + + debug("udev %s, resource id %d\n", dev->name, resource_id); + + return sc_rm_is_resource_owned(-1, resource_id); +} + +#ifdef CONFIG_IMX_VSERVICE +struct udevice * board_imx_vservice_find_mu(struct udevice *dev) +{ + int ret; + const char *m4_mu_name[2] = { + "mu@5d230000", + "mu@5d240000" + }; + struct udevice *m4_mu[2]; + sc_rm_pt_t m4_parts[2]; + int err; + struct ofnode_phandle_args args; + sc_rsrc_t resource_id; + sc_rm_pt_t resource_part; + + /* Get the resource id from its power-domain */ + ret = dev_read_phandle_with_args(dev, "power-domains", + "#power-domain-cells", 0, 0, &args); + if (ret) { + printf("Can't find the power-domains property for udev %s\n", dev->name); + return NULL; + } + + /* Get the owner partition for resource*/ + resource_id = (sc_rsrc_t)ofnode_read_u32_default(args.node, "reg", SC_R_NONE); + if (resource_id == SC_R_NONE) { + printf("Can't find the resource id for udev %s\n", dev->name); + return NULL; + } + + err = sc_rm_get_resource_owner(-1, resource_id, &resource_part); + if (err != SC_ERR_NONE) { + printf("%s get resource [%d] owner error: %d\n", __func__, resource_id, err); + return NULL; + } + + debug("udev %s, resource id %d, resource part %d\n", dev->name, resource_id, resource_part); + + /* MU8 for communication between M4_0 and u-boot, MU9 for M4_1 and u-boot */ + err = sc_rm_get_resource_owner(-1, SC_R_M4_0_PID0, &m4_parts[0]); + if (err != SC_ERR_NONE) { + printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_0_PID0, err); + return NULL; + } + + ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[0], &m4_mu[0]); + if (!ret) { + /* If the i2c is in m4_0 partition, return the mu8 */ + if (resource_part == m4_parts[0]) + return m4_mu[0]; + } + + if (is_imx8qm()) { + err = sc_rm_get_resource_owner(-1, SC_R_M4_1_PID0, &m4_parts[1]); + if (err != SC_ERR_NONE) { + printf("%s get resource [%d] owner error: %d\n", __func__, SC_R_M4_1_PID0, err); + return NULL; + } + + ret = uclass_find_device_by_name(UCLASS_MISC, m4_mu_name[1], &m4_mu[1]); + if (!ret) { + /* If the i2c is in m4_1 partition, return the mu9 */ + if (resource_part == m4_parts[1]) + return m4_mu[1]; + } + } + + return NULL; +} + +void * board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size) +{ + const char *m4_mu_name[2] = { + "mu@5d230000", + "mu@5d240000" + }; + + /* Each MU ownes 1M buffer */ + if (size <= 0x100000) { + if (!strcmp(node->mu_dev->name, m4_mu_name[0])) + return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER; + else if (!strcmp(node->mu_dev->name, m4_mu_name[1])) + return (void * )(CONFIG_IMX_VSERVICE_SHARED_BUFFER + 0x100000); + else + return NULL; + } + + return NULL; +} +#endif + +/* imx8qxp i2c1 has lots of devices may used by both M4 and A core +* If A core partition does not own the resource, we will start +* virtual i2c driver. Otherwise use local i2c driver. +*/ +int board_imx_virt_i2c_bind(struct udevice *dev) +{ + if (check_owned_udevice(dev)) + return -ENODEV; + + return 0; +} + +int board_imx_lpi2c_bind(struct udevice *dev) +{ + if (check_owned_udevice(dev)) + return 0; + + return -ENODEV; +} + +#ifdef CONFIG_USB_PORT_AUTO +static int usb_port_auto_check(void) +{ + int ret; + u32 usb2_data; + struct power_domain pd; + struct power_domain phy_pd; + + if (!power_domain_lookup_name("conn_usb0", &pd)) { + ret = power_domain_on(&pd); + if (ret) { + printf("conn_usb0 Power up failed!\n"); + return ret; + } + + if (!power_domain_lookup_name("conn_usb0_phy", &phy_pd)) { + ret = power_domain_on(&phy_pd); + if (ret) { + printf("conn_usb0_phy Power up failed!\n"); + return ret; + } + } else { + return -1; + } + + enable_usboh3_clk(1); + usb2_data = ci_udc_check_bus_active(USB_BASE_ADDR, USB_PHY0_BASE_ADDR, 0); + + ret = power_domain_off(&phy_pd); + if (ret) { + printf("conn_usb0_phy Power off failed!\n"); + return ret; + } + ret = power_domain_off(&pd); + if (ret) { + printf("conn_usb0 Power off failed!\n"); + return ret; + } + + if (!usb2_data) + return 1; + else + return 0; + } + return -1; +} + +int board_usb_gadget_port_auto(void) +{ + int usb_boot_index; + usb_boot_index = usb_port_auto_check(); + + if (usb_boot_index < 0) + usb_boot_index = 0; + + printf("auto usb %d\n", usb_boot_index); + + return usb_boot_index; +} +#endif + +static void power_off_all_usb(void) +{ + if (is_usb_boot()) { + /* Turn off all usb resource to let conn SS power down */ + sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_OFF); + sc_pm_set_resource_power_mode(-1, SC_R_USB_1_PHY, SC_PM_PW_MODE_OFF); + sc_pm_set_resource_power_mode(-1, SC_R_USB_2_PHY, SC_PM_PW_MODE_OFF); + + sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_OFF); + sc_pm_set_resource_power_mode(-1, SC_R_USB_1, SC_PM_PW_MODE_OFF); + sc_pm_set_resource_power_mode(-1, SC_R_USB_2, SC_PM_PW_MODE_OFF); + } +} diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index a132ce2e6a3..551e00fd9ee 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -8,12 +8,21 @@ #include #include #include +#include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; +struct edma_ch_map { + sc_rsrc_t ch_start_rsrc; + u32 ch_start_regs; + u32 ch_num; + const char* node_path; +}; + static bool check_owned_resource(sc_rsrc_t rsrc_id) { bool owned; @@ -43,7 +52,339 @@ static int disable_fdt_node(void *blob, int nodeoffset) return rc; } -static void update_fdt_with_owned_resources(void *blob) +static void fdt_edma_debug_int_array(u32 *array, int count, u32 stride) +{ +#ifdef DEBUG + int i; + for (i = 0; i < count; i++) { + printf("0x%x ", array[i]); + if (i % stride == stride - 1) + printf("\n"); + } + + printf("\n"); +#endif +} + +static void fdt_edma_debug_stringlist(const char *stringlist, int length) +{ +#ifdef DEBUG + int i = 0, len; + while (i < length) { + printf("%s\n", stringlist); + + len = strlen(stringlist) + 1; + i += len; + stringlist += len; + } + + printf("\n"); +#endif +} + +static void fdt_edma_swap_int_array(u32 *array, int count) +{ + int i; + for (i = 0; i < count; i++) { + array[i] = cpu_to_fdt32(array[i]); + } +} + +static int fdt_edma_update_int_array(u32 *array, int count, u32 *new_array, u32 stride, int *remove_array, int remove_count) +{ + int i = 0, j, curr = 0, new_cnt = 0; + + do { + if (remove_count && curr == remove_array[i]) { + i++; + remove_count--; + array += stride; + } else { + for (j = 0; j< stride; j++) { + *new_array = *array; + new_array++; + array++; + } + new_cnt+= j; + } + curr++; + } while ((curr * stride) < count); + + return new_cnt; +} + +static int fdt_edma_update_stringlist(const char *stringlist, int stringlist_count, char *newlist, int *remove_array, int remove_count) +{ + int i = 0, curr = 0, new_len = 0; + int length; + + debug("fdt_edma_update_stringlist, remove_cnt %d\n", remove_count); + + do { + if (remove_count && curr == remove_array[i]) { + debug("remove %s at %d\n", stringlist, remove_array[i]); + + length = strlen(stringlist) + 1; + stringlist += length; + i++; + remove_count--; + } else { + length = strlen(stringlist) + 1; + strcpy(newlist, stringlist); + + debug("copy %s, %s, curr %d, len %d\n", newlist, stringlist, curr, length); + + stringlist += length; + newlist += length; + new_len += length; + } + curr++; + } while (curr < stringlist_count); + + return new_len; +} + +static int fdt_edma_get_channel_id(u32 *regs, int index, struct edma_ch_map *edma) +{ + u32 ch_reg = regs[(index << 2) + 1]; + u32 ch_reg_size = regs[(index << 2) + 3]; + int ch_id = (ch_reg - edma->ch_start_regs) / ch_reg_size; + if (ch_id >= edma->ch_num) + return -1; + + return ch_id; +} + +static __maybe_unused void update_fdt_edma_nodes(void *blob) +{ + struct edma_ch_map edma_qm[] = { + { SC_R_DMA_0_CH0, 0x5a200000, 32, "/dma-controller@5a1f0000"}, + { SC_R_DMA_1_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"}, + { SC_R_DMA_2_CH0, 0x59200000, 5, "/dma-controller@591F0000"}, + { SC_R_DMA_2_CH5, 0x59250000, 27, "/dma-controller@591F0000"}, + { SC_R_DMA_3_CH0, 0x59a00000, 32, "/dma-controller@599F0000"}, + }; + + struct edma_ch_map edma_qxp[] = { + { SC_R_DMA_0_CH0, 0x59200000, 32, "/dma-controller@591F0000"}, + { SC_R_DMA_1_CH0, 0x59a00000, 32, "/dma-controller@599F0000"}, + { SC_R_DMA_2_CH0, 0x5a200000, 5, "/dma-controller@5a1f0000"}, + { SC_R_DMA_2_CH5, 0x5a250000, 27, "/dma-controller@5a1f0000"}, + { SC_R_DMA_3_CH0, 0x5aa00000, 32, "/dma-controller@5a9f0000"}, + }; + + u32 i, j, edma_size; + int nodeoff, ret; + struct edma_ch_map *edma_array; + + if (is_imx8qm()) { + edma_array = edma_qm; + edma_size = ARRAY_SIZE(edma_qm); + } else { + edma_array = edma_qxp; + edma_size = ARRAY_SIZE(edma_qxp); + } + + for (i = 0; i < edma_size; i++, edma_array++) { + u32 regs[128]; + u32 interrupts[96]; + u32 dma_channels; + int regs_count, interrupts_count, int_names_count; + + const char *list; + int list_len, newlist_len; + int remove[32]; + int remove_cnt = 0; + char * newlist; + + nodeoff = fdt_path_offset(blob, edma_array->node_path); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + printf("%s, %d\n", edma_array->node_path, nodeoff); + + regs_count = fdtdec_get_int_array_count(blob, nodeoff, "reg", regs, 128); + debug("regs_count %d\n", regs_count); + if (regs_count < 0) + continue; + + interrupts_count = fdtdec_get_int_array_count(blob, nodeoff, "interrupts", interrupts, 96); + debug("interrupts_count %d\n", interrupts_count); + if (interrupts_count < 0) + continue; + + dma_channels = fdtdec_get_uint(blob, nodeoff, "dma-channels", 0); + if (dma_channels == 0) + continue; + + list = fdt_getprop(blob, nodeoff, "interrupt-names", &list_len); + if (!list) + continue; + + int_names_count = fdt_stringlist_count(blob, nodeoff, "interrupt-names"); + + fdt_edma_debug_int_array(regs, regs_count, 4); + fdt_edma_debug_int_array(interrupts, interrupts_count, 3); + fdt_edma_debug_stringlist(list, list_len); + + for (j = 0; j < (regs_count >> 2); j++) { + int ch_id = fdt_edma_get_channel_id(regs, j, edma_array); + if (ch_id < 0) + continue; + + if (!check_owned_resource(edma_array->ch_start_rsrc + ch_id)) { + printf("remove edma items %d\n", j); + + dma_channels--; + + remove[remove_cnt] = j; + remove_cnt++; + } + } + + if (remove_cnt > 0) { + u32 new_regs[128]; + u32 new_interrupts[96]; + + regs_count = fdt_edma_update_int_array(regs, regs_count, new_regs, 4, remove, remove_cnt); + interrupts_count = fdt_edma_update_int_array(interrupts, interrupts_count, new_interrupts, 3, remove, remove_cnt); + + fdt_edma_debug_int_array(new_regs, regs_count, 4); + fdt_edma_debug_int_array(new_interrupts, interrupts_count, 3); + + fdt_edma_swap_int_array(new_regs, regs_count); + fdt_edma_swap_int_array(new_interrupts, interrupts_count); + + /* malloc a new string list */ + newlist = (char *)malloc(list_len); + if (!newlist) { + printf("malloc new string list failed, len=%d\n", list_len); + continue; + } + + newlist_len = fdt_edma_update_stringlist(list, int_names_count, newlist, remove, remove_cnt); + fdt_edma_debug_stringlist(newlist, newlist_len); + + ret = fdt_setprop(blob, nodeoff, "reg", new_regs, regs_count * sizeof(u32)); + if (ret) + printf("fdt_setprop regs error %d\n", ret); + + ret = fdt_setprop(blob, nodeoff, "interrupts", new_interrupts, interrupts_count * sizeof(u32)); + if (ret) + printf("fdt_setprop interrupts error %d\n", ret); + + ret = fdt_setprop_u32(blob, nodeoff, "dma-channels", dma_channels); + if (ret) + printf("fdt_setprop_u32 dma-channels error %d\n", ret); + + ret = fdt_setprop(blob, nodeoff, "interrupt-names", newlist, newlist_len); + if (ret) + printf("fdt_setprop interrupt-names error %d\n", ret); + + free(newlist); + } + } +} + +static bool check_owned_resources_in_pd_tree(void *blob, int nodeoff, + unsigned int *unowned_rsrc) +{ + unsigned int rsrc_id; + int phplen; + const fdt32_t *php; + + /* Search the ancestors nodes in current SS power-domain tree, + * if all ancestors' resources are owned, we can enable the node, + * otherwise any ancestor is not owned, we should disable the node. + */ + + do { + php = fdt_getprop(blob, nodeoff, "power-domains", &phplen); + if (!php) { + debug(" - ignoring no power-domains\n"); + break; + } + if (phplen != 4) { + printf("ignoring %s power-domains of unexpected length %d\n", + fdt_get_name(blob, nodeoff, NULL), phplen); + break; + } + nodeoff = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*php)); + + rsrc_id = fdtdec_get_uint(blob, nodeoff, "reg", 0); + if (rsrc_id == SC_R_NONE) { + debug("%s's power domain use SC_R_NONE\n", + fdt_get_name(blob, nodeoff, NULL)); + break; + } + + debug("power-domains node 0x%x, resource id %u\n", nodeoff, rsrc_id); + + if (!check_owned_resource(rsrc_id)) { + if (unowned_rsrc != NULL) + *unowned_rsrc = rsrc_id; + return false; + } + } while (fdt_node_check_compatible(blob, nodeoff, "nxp,imx8-pd")); + + return true; +} + +static void update_fdt_with_owned_resources_legacy(void *blob) +{ + /* Traverses the fdt nodes, + * check its power domain and use the resource id in the power domain + * for checking whether it is owned by current partition + */ + + int offset = 0, next_off; + int depth = 0, next_depth; + unsigned int rsrc_id; + int rc; + + for (offset = fdt_next_node(blob, offset, &depth); offset > 0; + offset = fdt_next_node(blob, offset, &depth)) { + + debug("Node name: %s, depth %d\n", fdt_get_name(blob, offset, NULL), depth); + + if (!fdtdec_get_is_enabled(blob, offset)) { + debug(" - ignoring disabled device\n"); + continue; + } + + if (!fdt_node_check_compatible(blob, offset, "nxp,imx8-pd")) { + /* Skip to next depth=1 node*/ + next_off = offset; + next_depth = depth; + do { + offset = next_off; + depth = next_depth; + next_off = fdt_next_node(blob, offset, &next_depth); + if (next_off < 0 || next_depth < 1) + break; + + debug("PD name: %s, offset %d, depth %d\n", + fdt_get_name(blob, next_off, NULL), next_off, next_depth); + } while (next_depth > 1); + + continue; + } + + if (!check_owned_resources_in_pd_tree(blob, offset, &rsrc_id)) { + /* If the resource is not owned, disable it in FDT */ + rc = disable_fdt_node(blob, offset); + if (!rc) + printf("Disable %s, resource id %u not owned\n", + fdt_get_name(blob, offset, NULL), rsrc_id); + else + printf("Unable to disable %s, err=%s\n", + fdt_get_name(blob, offset, NULL), fdt_strerror(rc)); + } + + } +} + +static __maybe_unused void update_fdt_with_owned_resources(void *blob) { /* * Traverses the fdt nodes, check its power domain and use @@ -53,7 +394,12 @@ static void update_fdt_with_owned_resources(void *blob) struct fdtdec_phandle_args args; int offset = 0, depth = 0; u32 rsrc_id; - int rc, i; + int rc, i, count; + + /* Check the new PD, if not find, continue with old PD tree */ + count = fdt_node_offset_by_compatible(blob, -1, "fsl,scu-pd"); + if (count < 0) + return update_fdt_with_owned_resources_legacy(blob); for (offset = fdt_next_node(blob, offset, &depth); offset > 0; offset = fdt_next_node(blob, offset, &depth)) { @@ -154,16 +500,16 @@ static int config_smmu_fdt_device_sid(void *blob, int device_offset, int sid) "#power-domain-cells", 0, i++, &args); if (ret == -ENOENT) { - break; + return 0; } else if (ret) { printf("Parse power-domains of node %s wrong: %d\n", fdt_get_name(blob, device_offset, NULL), ret); continue; } + rsrc = args.args[0]; debug("configure node %s sid 0x%x rsrc=%d\n", name, sid, rsrc); - rsrc = args.args[0]; ret = config_smmu_resource_sid(rsrc, sid); if (ret) @@ -229,56 +575,6 @@ static int config_smmu_fdt(void *blob) return 0; } -static int ft_add_optee_node(void *fdt, struct bd_info *bd) -{ - const char *path, *subpath; - int offs; - - /* - * No TEE space allocated indicating no TEE running, so no - * need to add optee node in dts - */ - if (!boot_pointer[1]) - return 0; - - offs = fdt_increase_size(fdt, 512); - if (offs) { - printf("No Space for dtb\n"); - return 1; - } - - path = "/firmware"; - offs = fdt_path_offset(fdt, path); - if (offs < 0) { - path = "/"; - offs = fdt_path_offset(fdt, path); - - if (offs < 0) { - printf("Could not find root node.\n"); - return offs; - } - - subpath = "firmware"; - offs = fdt_add_subnode(fdt, offs, subpath); - if (offs < 0) { - printf("Could not create %s node.\n", subpath); - return offs; - } - } - - subpath = "optee"; - offs = fdt_add_subnode(fdt, offs, subpath); - if (offs < 0) { - printf("Could not create %s node.\n", subpath); - return offs; - } - - fdt_setprop_string(fdt, offs, "compatible", "linaro,optee-tz"); - fdt_setprop_string(fdt, offs, "method", "smc"); - - return 0; -} - int ft_system_setup(void *blob, struct bd_info *bd) { int ret; @@ -292,8 +588,11 @@ int ft_system_setup(void *blob, struct bd_info *bd) fdt_strerror(off)); } +#ifndef CONFIG_SKIP_RESOURCE_CHECKING update_fdt_with_owned_resources(blob); +#endif + update_fdt_edma_nodes(blob); if (is_imx8qm()) { ret = config_smmu_fdt(blob); if (ret) diff --git a/arch/arm/mach-imx/imx8/image.c b/arch/arm/mach-imx/imx8/image.c index 5abc0d3a39f..b8903a620fd 100644 --- a/arch/arm/mach-imx/imx8/image.c +++ b/arch/arm/mach-imx/imx8/image.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2018-2020 NXP */ #include @@ -20,7 +20,25 @@ #define NAND_DEV 2 #define QSPI_NOR_DEV 3 -static int __get_container_size(ulong addr) +/* The unit of second image offset number which provision by the fuse bits */ +#define SND_IMG_OFF_UNIT (0x100000UL) + +/* + * If num = 0, off = (2 ^ 2) * 1MB + * else If num = 2, off = (2 ^ 0) * 1MB + * else off = (2 ^ num) * 1MB + */ +#define SND_IMG_NUM_TO_OFF(num) \ + ((1UL << ((0 == (num)) ? 2 : (2 == (num)) ? 0 : (num))) * SND_IMG_OFF_UNIT) + + +#if defined(CONFIG_IMX8QM) +#define FUSE_IMG_SET_OFF_WORD 464 +#elif defined(CONFIG_IMX8QXP) || defined (CONFIG_IMX8DXL) +#define FUSE_IMG_SET_OFF_WORD 720 +#endif + +static int __get_container_size(ulong addr, u16 *header_length) { struct container_hdr *phdr; struct boot_img_t *img_entry; @@ -34,7 +52,9 @@ static int __get_container_size(ulong addr) return -EFAULT; } - max_offset = sizeof(struct container_hdr); + max_offset = phdr->length_lsb + (phdr->length_msb << 8); + if (header_length) + *header_length = max_offset; img_entry = (struct boot_img_t *)(addr + sizeof(struct container_hdr)); for (i = 0; i < phdr->num_images; i++) { @@ -60,7 +80,7 @@ static int __get_container_size(ulong addr) return max_offset; } -static int get_container_size(void *dev, int dev_type, unsigned long offset) +static int get_container_size(void *dev, int dev_type, unsigned long offset, u16 *header_length) { u8 *buf = malloc(CONTAINER_HDR_ALIGNMENT); int ret = 0; @@ -115,22 +135,53 @@ static int get_container_size(void *dev, int dev_type, unsigned long offset) memcpy(buf, (const void *)offset, CONTAINER_HDR_ALIGNMENT); #endif - ret = __get_container_size((ulong)buf); + ret = __get_container_size((ulong)buf, header_length); free(buf); return ret; } +static bool check_secondary_cnt_set(unsigned long *set_off) +{ + int ret; + u8 set_id = 1; + u32 fuse_val = 0; + + if (!(is_imx8qxp() && is_soc_rev(CHIP_REV_B))) { + ret = sc_misc_get_boot_container(-1, &set_id); + if (!ret) { + /* Secondary boot */ + if (set_id == 2) { + ret = sc_misc_otp_fuse_read(-1, FUSE_IMG_SET_OFF_WORD, &fuse_val); + if (!ret) { + if (set_off) + *set_off = SND_IMG_NUM_TO_OFF(fuse_val); + return true; + } + } + } + } + + return false; +} + static unsigned long get_boot_device_offset(void *dev, int dev_type) { - unsigned long offset = 0; + unsigned long offset = 0, sec_set_off = 0; + bool sec_boot = false; + + sec_boot = check_secondary_cnt_set(&sec_set_off); + if (sec_boot) + printf("Secondary set selected\n"); + else + printf("Primary set selected\n"); if (dev_type == MMC_DEV) { struct mmc *mmc = (struct mmc *)dev; if (IS_SD(mmc) || mmc->part_config == MMCPART_NOAVAILABLE) { - offset = CONTAINER_HDR_MMCSD_OFFSET; + offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; } else { u8 part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); @@ -140,29 +191,31 @@ static unsigned long get_boot_device_offset(void *dev, int dev_type) else offset = CONTAINER_HDR_EMMC_OFFSET; } else { - offset = CONTAINER_HDR_MMCSD_OFFSET; + offset = sec_boot? sec_set_off : CONTAINER_HDR_MMCSD_OFFSET; } } } else if (dev_type == QSPI_DEV) { - offset = CONTAINER_HDR_QSPI_OFFSET; + offset = sec_boot? (sec_set_off + CONTAINER_HDR_QSPI_OFFSET) : CONTAINER_HDR_QSPI_OFFSET; } else if (dev_type == NAND_DEV) { - offset = CONTAINER_HDR_NAND_OFFSET; + offset = sec_boot? (sec_set_off + CONTAINER_HDR_NAND_OFFSET) : CONTAINER_HDR_NAND_OFFSET; } else if (dev_type == QSPI_NOR_DEV) { offset = CONTAINER_HDR_QSPI_OFFSET + 0x08000000; } + debug("container set offset 0x%lx\n", offset); + return offset; } static int get_imageset_end(void *dev, int dev_type) { - unsigned long offset1 = 0, offset2 = 0; - int value_container[2]; + unsigned long offset[3] = {}; + int value_container[3] = {}; + u16 hdr_length; - offset1 = get_boot_device_offset(dev, dev_type); - offset2 = CONTAINER_HDR_ALIGNMENT + offset1; + offset[0] = get_boot_device_offset(dev, dev_type); - value_container[0] = get_container_size(dev, dev_type, offset1); + value_container[0] = get_container_size(dev, dev_type, offset[0], &hdr_length); if (value_container[0] < 0) { printf("Parse seco container failed %d\n", value_container[0]); return value_container[0]; @@ -170,17 +223,35 @@ static int get_imageset_end(void *dev, int dev_type) debug("seco container size 0x%x\n", value_container[0]); - value_container[1] = get_container_size(dev, dev_type, offset2); - if (value_container[1] < 0) { - debug("Parse scu container failed %d, only seco container\n", - value_container[1]); - /* return seco container total size */ - return value_container[0] + offset1; + if (is_imx8dxl()) { + offset[1] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0]; + + value_container[1] = get_container_size(dev, dev_type, offset[1], &hdr_length); + if (value_container[1] < 0) { + printf("Parse v2x container failed %d\n", value_container[1]); + return value_container[0] + offset[0]; /* return seco container total size */ + } + + debug("v2x container size 0x%x\n", value_container[1]); + + offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[1]; + } else { + /* Skip offset[1] */ + offset[2] = ALIGN(hdr_length, CONTAINER_HDR_ALIGNMENT) + offset[0]; + } + + value_container[2] = get_container_size(dev, dev_type, offset[2], &hdr_length); + if (value_container[2] < 0) { + debug("Parse scu container image failed %d, only seco container\n", value_container[2]); + if (is_imx8dxl()) + return value_container[1] + offset[1]; /* return seco + v2x container total size */ + else + return value_container[0] + offset[0]; /* return seco container total size */ } - debug("scu container size 0x%x\n", value_container[1]); + debug("scu container size 0x%x\n", value_container[2]); - return value_container[1] + offset2; + return value_container[2] + offset[2]; } #ifdef CONFIG_SPL_SPI_LOAD @@ -210,6 +281,32 @@ unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, return end / mmc->read_bl_len; } + +int spl_mmc_emmc_boot_partition(struct mmc *mmc) +{ + int part = 0; + +#ifdef CONFIG_DUAL_BOOTLOADER + /* Bootloader is stored in eMMC user partition for + * dual bootloader. + */ + part = 0; +#else + part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + if (part == 1 || part == 2) { + unsigned long sec_set_off = 0; + bool sec_boot = false; + + sec_boot = check_secondary_cnt_set(&sec_set_off); + if (sec_boot) + part = (part == 1)? 2 : 1; + } else if (part == 7) { + part = 0; + } +#endif + + return part; +} #endif #ifdef CONFIG_SPL_NAND_SUPPORT diff --git a/arch/arm/mach-imx/imx8/lowlevel_init.S b/arch/arm/mach-imx/imx8/lowlevel_init.S index a66243c5e4f..84798eab6b0 100644 --- a/arch/arm/mach-imx/imx8/lowlevel_init.S +++ b/arch/arm/mach-imx/imx8/lowlevel_init.S @@ -6,8 +6,8 @@ #include .align 8 -.global boot_pointer -boot_pointer: +.global rom_pointer +rom_pointer: .space 32 /* @@ -17,7 +17,7 @@ boot_pointer: .global save_boot_params save_boot_params: /* The firmware provided ATAG/FDT address can be found in r2/x0 */ - adr x0, boot_pointer + adr x0, rom_pointer stp x1, x2, [x0], #16 stp x3, x4, [x0], #16 diff --git a/arch/arm/mach-imx/imx8/lpcg.c b/arch/arm/mach-imx/imx8/lpcg.c new file mode 100644 index 00000000000..bda2046b4ac --- /dev/null +++ b/arch/arm/mach-imx/imx8/lpcg.c @@ -0,0 +1,116 @@ +/* + * Copyright 2017-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define LPCG_CLOCK_MASK 0x3U +#define LPCG_CLOCK_OFF 0x0U +#define LPCG_CLOCK_ON 0x2U +#define LPCG_CLOCK_AUTO 0x3U +#define LPCG_CLOCK_STOP 0x8U + +#define LPCG_ALL_CLOCK_OFF 0x00000000U +#define LPCG_ALL_CLOCK_ON 0x22222222U +#define LPCG_ALL_CLOCK_AUTO 0x33333333U +#define LPCG_ALL_CLOCK_STOP 0x88888888U + +static inline void lpcg_write(u32 lpcgVal, ulong lpcg_addr) +{ + /* + * Write twice with 4x DSC clock cycles (40x IPS clock cycles) interval + * to work around LPCG issue + */ + writel(lpcgVal, lpcg_addr); + udelay(10); /* 10us is enough. Worst case is 40x IPS cycle (200Mhz) */ + writel(lpcgVal, lpcg_addr); + udelay(10); +} + +void lpcg_clock_off(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_OFF) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void lpcg_clock_on(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_ON) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +bool lpcg_is_clock_on(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + lpcgVal = (lpcgVal >> (clk * 4U)) & (u32)(LPCG_CLOCK_MASK); + + if (lpcgVal == LPCG_CLOCK_ON) + return true; + + return false; +} + +void lpcg_clock_autogate(u32 lpcg_addr, u8 clk) +{ + u32 lpcgVal; + + /* Read from LPCG */ + lpcgVal = readl((ulong)lpcg_addr); + + /* Modify */ + lpcgVal &= ~((u32)(LPCG_CLOCK_MASK) << (clk * 4U)); + lpcgVal |= ((u32)(LPCG_CLOCK_AUTO) << (clk * 4U)); + + /* Write to LPCG */ + lpcg_write(lpcgVal, (ulong)lpcg_addr); +} + +void lpcg_all_clock_off(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_OFF, (ulong)lpcg_addr); +} + +void lpcg_all_clock_on(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_ON, (ulong)lpcg_addr); + + /* Wait for clocks to start */ + while ((readl((ulong)lpcg_addr) & LPCG_ALL_CLOCK_STOP) != 0U) + { + } +} + +void lpcg_all_clock_autogate(u32 lpcg_addr) +{ + /* Write to LPCG */ + lpcg_write(LPCG_ALL_CLOCK_AUTO, (ulong)lpcg_addr); +} diff --git a/arch/arm/mach-imx/imx8/misc.c b/arch/arm/mach-imx/imx8/misc.c index de19955e2f7..0f695708c5b 100644 --- a/arch/arm/mach-imx/imx8/misc.c +++ b/arch/arm/mach-imx/imx8/misc.c @@ -3,14 +3,27 @@ #include #include #include +#include #include +#include #include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate) { sc_pm_clock_rate_t rate = clk_rate; int ret; + if (uart_rsrc < SC_R_UART_0 || uart_rsrc > SC_R_UART_4) + return -EINVAL; + /* Power up UARTn */ ret = sc_pm_set_resource_power_mode(-1, uart_rsrc, SC_PM_PW_MODE_ON); if (ret) @@ -26,15 +39,42 @@ int sc_pm_setup_uart(sc_rsrc_t uart_rsrc, sc_pm_clock_rate_t clk_rate) if (ret) return ret; + lpcg_all_clock_on(LPUART_0_LPCG + (uart_rsrc - SC_R_UART_0) * 0x10000); + return 0; } +extern uint32_t _end_ofs; + +#define V2X_PROD_VER(X) (((X) >> 16) & 0x7FFF) +#define V2X_MAJOR_VER(X) (((X) >> 4) & 0xFFF) +#define V2X_MINOR_VER(X) ((X) & 0xF) + +static void set_buildinfo_to_env(uint32_t scfw, uint32_t secofw, char *mkimage, char *atf) +{ + if (!mkimage || !atf) + return; + + env_set("commit_mkimage", mkimage); + env_set("commit_atf", atf); + env_set_hex("commit_scfw", (ulong)scfw); + env_set_hex("commit_secofw", (ulong)secofw); +} + +static void set_v2x_buildinfo_to_env(u32 v2x_build, u32 v2x_commit) +{ + env_set_hex("commit_v2x", (ulong)v2x_commit); + env_set_hex("version_v2x", (ulong)v2x_build); +} + void build_info(void) { struct arm_smccc_res res; u32 seco_build = 0, seco_commit = 0; u32 sc_build = 0, sc_commit = 0; + char *mkimage_commit, *temp; ulong atf_commit = 0; + u32 v2x_build = 0, v2x_commit = 0; /* Get SCFW build and commit id */ sc_misc_build_info(-1, &sc_build, &sc_commit); @@ -51,6 +91,30 @@ void build_info(void) seco_commit = 0; } + if (is_imx8dxl()) { + int ret; + ret = sc_seco_v2x_build_info(-1, &v2x_build, &v2x_commit); + if (ret) { + debug("Failed to get V2X FW build info\n"); + /* Display 0 when the build info is not supported */ + v2x_build = 0; + v2x_commit = 0; + } + } + + /* Get imx-mkimage commit id. + * The imx-mkimage puts the commit hash behind the end of u-boot.bin + */ + mkimage_commit = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + + _end_ofs + fdt_totalsize(gd->fdt_blob)); + temp = mkimage_commit + 8; + *temp = '\0'; + + if (strlen(mkimage_commit) == 0) { + debug("IMX-MKIMAGE does not support build info\n"); + mkimage_commit = "0"; /* Display 0 */ + } + /* Get ARM Trusted Firmware commit id */ arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH, 0, 0, 0, 0, 0, 0, &res); @@ -60,6 +124,38 @@ void build_info(void) atf_commit = 0x30; /* Display 0 */ } - printf("Build: SCFW %08x, SECO-FW %08x, ATF %s\n", - sc_commit, seco_commit, (char *)&atf_commit); + /* Set all to env */ + set_buildinfo_to_env(sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit); + + printf("\n BuildInfo: \n - SCFW %08x, SECO-FW %08x, IMX-MKIMAGE %s, ATF %s\n - %s \n", + sc_commit, seco_commit, mkimage_commit, (char *)&atf_commit, U_BOOT_VERSION); + + if (is_imx8dxl() && v2x_build != 0 && v2x_commit != 0) { + set_v2x_buildinfo_to_env(v2x_build, v2x_commit); + printf(" - V2X-FW %08x version %u.%u.%u\n", v2x_commit, + V2X_PROD_VER(v2x_build), V2X_MAJOR_VER(v2x_build), V2X_MINOR_VER(v2x_build)); + } + printf("\n"); +} + +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_PSCI_BOARD_REBOOT) + +#define PSCI_SYSTEM_RESET2_AARCH64 0xc4000012 +#define PSCI_RESET2_SYSTEM_BOARD_RESET 0x80000002 + +int do_board_reboot(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + + uclass_get_device_by_name(UCLASS_FIRMWARE, "psci", &dev); + invoke_psci_fn(PSCI_SYSTEM_RESET2_AARCH64, PSCI_RESET2_SYSTEM_BOARD_RESET, 0, 0); + + return 1; } + +U_BOOT_CMD( + reboot, 1, 1, do_board_reboot, + "reboot\n", + "system board reboot for i.MX 8 Quad devices \n" +); +#endif diff --git a/arch/arm/mach-imx/imx8/parse-container.c b/arch/arm/mach-imx/imx8/parse-container.c index 375098902f8..bc211e0151b 100644 --- a/arch/arm/mach-imx/imx8/parse-container.c +++ b/arch/arm/mach-imx/imx8/parse-container.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -132,21 +133,27 @@ static int read_auth_container(struct spl_image_info *spl_image, * It will not override the ATF code, so safe to use it here, * no need malloc */ - container = (struct container_hdr *)spl_get_load_buffer(-size, size); + container = malloc(size); + if (!container) + return -ENOMEM; debug("%s: container: %p sector: %lu sectors: %u\n", __func__, container, sector, sectors); - if (info->read(info, sector, sectors, container) != sectors) - return -EIO; + if (info->read(info, sector, sectors, container) != sectors) { + ret = -EIO; + goto end; + } if (container->tag != 0x87 && container->version != 0x0) { printf("Wrong container header"); - return -ENOENT; + ret = -ENOENT; + goto end; } if (!container->num_images) { printf("Wrong container, no image found"); - return -ENOENT; + ret = -ENOENT; + goto end; } length = container->length_lsb + (container->length_msb << 8); @@ -156,13 +163,18 @@ static int read_auth_container(struct spl_image_info *spl_image, size = roundup(length, info->bl_len); sectors = size / info->bl_len; - container = (struct container_hdr *)spl_get_load_buffer(-size, size); + free(container); + container = malloc(size); + if (!container) + return -ENOMEM; debug("%s: container: %p sector: %lu sectors: %u\n", __func__, container, sector, sectors); if (info->read(info, sector, sectors, container) != - sectors) - return -EIO; + sectors) { + ret = -EIO; + goto end; + } } #ifdef CONFIG_AHAB_BOOT @@ -173,7 +185,7 @@ static int read_auth_container(struct spl_image_info *spl_image, SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE); if (ret) { printf("authenticate container hdr failed, return %d\n", ret); - return ret; + goto end; } #endif @@ -193,11 +205,21 @@ static int read_auth_container(struct spl_image_info *spl_image, } } +#if defined(CONFIG_SPL_BUILD) && \ + defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_IMX_TRUSTY_OS) + /* Everything checks out, get the sw_version now. */ + spl_image->rbindex = (uint64_t)container->sw_version; +#endif + end_auth: #ifdef CONFIG_AHAB_BOOT if (sc_seco_authenticate(-1, SC_SECO_REL_CONTAINER, 0)) printf("Error: release container failed!\n"); #endif + +end: + free(container); + return ret; } diff --git a/arch/arm/mach-imx/imx8/partition.c b/arch/arm/mach-imx/imx8/partition.c new file mode 100644 index 00000000000..359936e495c --- /dev/null +++ b/arch/arm/mach-imx/imx8/partition.c @@ -0,0 +1,377 @@ +/* + * Copyright 2018 NXP. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SC_MAX_PARTS 32 + +struct scu_rm_part_data { + bool used; + bool isolated; + bool restricted; + bool grant; + sc_rm_did_t did; + sc_rm_pt_t self; + sc_rm_pt_t parent; + char *name; +}; + +static struct scu_rm_part_data rm_part_data[SC_MAX_PARTS]; + +static int partition_alloc(bool isolated, bool restricted, bool grant, sc_rm_pt_t *pt) +{ + sc_rm_pt_t parent_part, os_part; + int err; + int i; + + for (i = 0; i < SC_MAX_PARTS; i++) { + if (!rm_part_data[i].used) + break; + } + + if (i == SC_MAX_PARTS) { + puts("No empty slots\n"); + return -EINVAL; + } + + err = sc_rm_get_partition(-1, &parent_part); + if (err != SC_ERR_NONE) { + puts("sc_rm_get_partition failure\n"); + return -EINVAL; + } + + debug("isolated %d, restricted %d, grant %d\n", isolated, restricted, grant); + err = sc_rm_partition_alloc(-1, &os_part, false, isolated, + restricted, grant, false); + if (err != SC_ERR_NONE) { + printf("sc_rm_partition_alloc failure %d\n", err); + return -EINVAL; + } + + err = sc_rm_set_parent(-1, os_part, parent_part); + if (err != SC_ERR_NONE) { + sc_rm_partition_free(-1, os_part); + return -EINVAL; + } + + + rm_part_data[i].self = os_part; + rm_part_data[i].parent = parent_part; + rm_part_data[i].used = true; + rm_part_data[i].restricted = restricted; + rm_part_data[i].isolated = isolated; + rm_part_data[i].grant = grant; + + if (pt) + *pt = os_part; + + printf("%s: os_part, %d: parent_part, %d\n", __func__, os_part, + parent_part); + + return 0; +} + +static int do_part_alloc(int argc, char * const argv[]) +{ + bool restricted = false, isolated = false, grant = false; + int ret; + + if (argv[0]) + isolated = simple_strtoul(argv[0], NULL, 10); + if (argv[1]) + restricted = simple_strtoul(argv[1], NULL, 10); + if (argv[2]) + grant = simple_strtoul(argv[2], NULL, 10); + + ret = partition_alloc(isolated, restricted, grant, NULL); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static int do_part_dtb(int argc, char * const argv[]) +{ + int err; + sc_rm_pt_t pt; + char *pathp = "/domu"; + int nodeoffset, subnode; + int rsrc_size = 0, pad_size = 0; + int i, ret; + u32 *rsrc_data = NULL, *pad_data = NULL; + const struct fdt_property *prop; + bool init_ignore_domu_power = false; + char *tmp; + void *fdt; + + tmp = env_get("domu-init-ignore-poweroff"); + if (tmp && !strncmp(tmp, "yes", 3)) { + init_ignore_domu_power = true; + printf("ignore init power off domu power\n"); + } + + if (argc) + fdt = (void *)simple_strtoul(argv[0], NULL, 16); + else + fdt = working_fdt; + printf("fdt addr %p\n", fdt); + nodeoffset = fdt_path_offset(fdt, pathp); + debug("%s %s %p\n", __func__, fdt_get_name(fdt, nodeoffset, NULL), fdt); + fdt_for_each_subnode(subnode, fdt, nodeoffset) { + if (!fdtdec_get_is_enabled(fdt, subnode)) + continue; + if (!fdt_node_check_compatible(fdt, subnode, "xen,domu")) { + u32 temp; + prop = fdt_getprop(fdt, subnode, "rsrcs", &rsrc_size); + if (!prop) + debug("No rsrcs %s\n", fdt_get_name(fdt, subnode, NULL)); + if (rsrc_size > 0) { + rsrc_data = kmalloc(rsrc_size, __GFP_ZERO); + if (!rsrc_data) { + debug("No mem\n"); + return CMD_RET_FAILURE; + } + if (fdtdec_get_int_array(fdt, subnode, "rsrcs", + rsrc_data, rsrc_size >> 2)) { + debug("Error reading rsrcs\n"); + kfree(rsrc_data); + return CMD_RET_FAILURE; + } + } + + prop = fdt_getprop(fdt, subnode, "pads", &pad_size); + if (!prop) + debug("No pads %s %d\n", fdt_get_name(fdt, subnode, NULL), pad_size); + if (pad_size > 0) { + pad_data = kmalloc(pad_size, __GFP_ZERO); + if (!pad_data) { + debug("No mem\n"); + if (rsrc_data != NULL) + kfree(rsrc_data); + return CMD_RET_FAILURE; + } + if (fdtdec_get_int_array(fdt, subnode, "pads", + pad_data, pad_size >> 2)) { + debug("Error reading pad\n"); + kfree(pad_data); + kfree(rsrc_data); + return CMD_RET_FAILURE; + } + } + + if ((rsrc_size <= 0) && (pad_size <= 0)) + continue; + + ret = partition_alloc(false, false, true, &pt); + if (ret) + goto free_data; + + temp = cpu_to_fdt32(pt); + ret = fdt_setprop(fdt, subnode, "reg", &temp, + sizeof(u32)); + if (ret) { + printf("Could not set reg property %d\n", ret); + sc_rm_partition_free(-1, pt); + goto free_data; + } + + if (rsrc_size > 0) { + for (i = 0; i < rsrc_size >> 2; i++) { + switch (rsrc_data[i]) { + case SC_R_MU_2A: + case SC_R_MU_3A: + case SC_R_MU_4A: + err = sc_pm_set_resource_power_mode(-1, rsrc_data[i], SC_PM_PW_MODE_ON); + if (err) + debug("power on resource %d, err %d\n", rsrc_data[i], err); + break; + default: + if (init_ignore_domu_power) + break; + err = sc_pm_set_resource_power_mode(-1, rsrc_data[i], SC_PM_PW_MODE_OFF); + if (err) + debug("power off resource %d, err %d\n", rsrc_data[i], err); + break; + } + if (sc_rm_is_resource_owned(-1, rsrc_data[i])) { + err = sc_rm_assign_resource(-1, pt, rsrc_data[i]); + debug("pt %d, resource %d, err %d\n", pt, rsrc_data[i], err); + } + } + } + + if (pad_size > 0) { + for (i = 0; i < pad_size >> 2; i++) { + if (sc_rm_is_pad_owned(-1, pad_data[i])) { + err = sc_rm_assign_pad(-1, pt, pad_data[i]); + debug("pt %d, pad %d, err %d\n", pt, pad_data[i], err); + } + } + } + + free_data: + if (pad_size > 0) + kfree(pad_data); + if (rsrc_size > 0) { + kfree(rsrc_data); + rsrc_data = NULL; + } + } + + } + + return 0; +} + +static int do_part_free(int argc, char * const argv[]) +{ + sc_rm_pt_t os_part; + int err; + int i; + + if (argc == 0) + return CMD_RET_FAILURE; + + os_part = simple_strtoul(argv[0], NULL, 10); + + err = sc_rm_partition_free(-1, os_part); + if (err != SC_ERR_NONE) { + printf("free partiiton %d err %d\n", os_part, err); + return CMD_RET_FAILURE; + } + + for (i = 0; i < SC_MAX_PARTS; i++) { + if ((rm_part_data[i].self == os_part) && rm_part_data[i].used) { + rm_part_data[i].used = false; + break; + } + } + + return CMD_RET_SUCCESS; +} + +static int do_resource_assign(int argc, char * const argv[]) +{ + sc_rm_pt_t os_part; + int err; + sc_rsrc_t resource; + sc_pad_t pad; + int i, flag; + + + if (argc < 3) + return CMD_RET_FAILURE; + + os_part = simple_strtoul(argv[0], NULL, 10); + flag = simple_strtoul(argv[1], NULL, 10); + if (flag) + pad = simple_strtoul(argv[2], NULL, 10); + else + resource = simple_strtoul(argv[2], NULL, 10); + + for (i = 0; i < SC_MAX_PARTS; i++) { + if ((rm_part_data[i].self == os_part) && rm_part_data[i].used) + break; + } + + if (i == SC_MAX_PARTS) { + puts("Not valid partition\n"); + return CMD_RET_FAILURE; + } + + if (flag) + err = sc_rm_assign_pad(-1, os_part, pad); + else + err = sc_rm_assign_resource(-1, os_part, resource); + if (err != SC_ERR_NONE) { + printf("assign resource/pad error %d\n", err); + return CMD_RET_FAILURE; + } + + printf("%s: os_part, %d, %d\n", __func__, os_part, + flag ? pad : resource); + + return CMD_RET_SUCCESS; +} + +static int do_part_list(int argc, char * const argv[]) +{ + int i; + + for (i = 0; i < SC_MAX_PARTS; i++) { + if (rm_part_data[i].used) + printf("part id: %d %d\n", rm_part_data[i].self, + rm_part_data[i].parent); + } + + return CMD_RET_SUCCESS; +} + +static int do_part_test(int argc, char * const argv[]) +{ + sc_err_t err; + sc_rsrc_t resource; + + if (argc < 1) + return CMD_RET_FAILURE; + + resource = simple_strtoul(argv[0], NULL, 10); + + err = sc_pm_set_resource_power_mode(-1, resource, SC_PM_PW_MODE_ON); + if (err == SC_ERR_NOACCESS) + puts("NO ACCESS\n"); + + return CMD_RET_SUCCESS; +} + +static int do_scu_rm(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc < 2) + return CMD_RET_USAGE; + + if (!strcmp(argv[1], "alloc")) + return do_part_alloc(argc - 2, argv + 2); + else if (!strcmp(argv[1], "dtb")) + return do_part_dtb(argc - 2, argv + 2); + else if (!strcmp(argv[1], "free")) + return do_part_free(argc - 2, argv + 2); + else if (!strcmp(argv[1], "assign")) + return do_resource_assign(argc - 2, argv + 2); + else if (!strcmp(argv[1], "test")) + return do_part_test(argc - 2, argv + 2); + else if (!strcmp(argv[1], "print")) + return do_part_list(argc - 2, argv + 2); + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + scu_rm, CONFIG_SYS_MAXARGS, 1, do_scu_rm, + "scu partition function", + "\n" + "scu_rm alloc [isolated] [restricted] [grant]\n" + "scu_rm dtb [fdt]\n" + "scu_rm free pt\n" + "scu_rm assign pt 0 resource\n" + "scu_rm assign pt 1 pad\n" + "scu_rm test resource\n" + "scu_rm print\n" +); diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc.c b/arch/arm/mach-imx/imx8/snvs_security_sc.c index 6f9b1c99fcd..b2f45e91a80 100644 --- a/arch/arm/mach-imx/imx8/snvs_security_sc.c +++ b/arch/arm/mach-imx/imx8/snvs_security_sc.c @@ -9,19 +9,28 @@ * - passive mode expecting VCC on the line: "_passive_vcc_" * - passive mode expecting VCC on the line: "_passive_gnd_" * - active mode: "_active_" + * + * WARNING: + * The silicon revision B0 of the iMX8QM and iMX8QXP have a bug in the SECO ROM: + * If the SSM of the SNVS changes state, the next call to SECO will trigger an + * integrity check of the SECO firmware which will fail due to incorrect CAAM + * keys hence the SECO will not respond to the call. The system will hang in + * this state until a watchdog resets the board. */ #include #include #include #include +#include #include #include #include #include - -/* Access to gd */ -DECLARE_GLOBAL_DATA_PTR; +#include +#include "snvs_security_sc_conf_board.h" +#include +#include #define SC_WRITE_CONF 1 @@ -29,240 +38,17 @@ DECLARE_GLOBAL_DATA_PTR; #define SRTC_EN 0x1 #define DP_EN BIT(5) -struct snvs_security_sc_conf { - struct snvs_hp_conf { - u32 lock; /* HPLR - HP Lock */ - u32 __cmd; /* HPCOMR - HP Command */ - u32 __ctl; /* HPCR - HP Control */ - u32 secvio_intcfg; /* HPSICR - Security Violation Int - * Config - */ - u32 secvio_ctl; /* HPSVCR - Security Violation Control*/ - u32 status; /* HPSR - HP Status */ - u32 secvio_status; /* HPSVSR - Security Violation Status */ - u32 __ha_counteriv; /* High Assurance Counter IV */ - u32 __ha_counter; /* High Assurance Counter */ - u32 __rtc_msb; /* Real Time Clock/Counter MSB */ - u32 __rtc_lsb; /* Real Time Counter LSB */ - u32 __time_alarm_msb; /* Time Alarm MSB */ - u32 __time_alarm_lsb; /* Time Alarm LSB */ - } hp; - struct snvs_lp_conf { - u32 lock; - u32 __ctl; - u32 __mstr_key_ctl; /* Master Key Control */ - u32 secvio_ctl; /* Security Violation Control */ - u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration*/ - u32 tamper_det_cfg; /* Tamper Detectors Configuration */ - u32 status; - u32 __srtc_msb; /* Secure Real Time Clock/Counter MSB */ - u32 __srtc_lsb; /* Secure Real Time Clock/Counter LSB */ - u32 __time_alarm; /* Time Alarm */ - u32 __smc_msb; /* Secure Monotonic Counter MSB */ - u32 __smc_lsb; /* Secure Monotonic Counter LSB */ - u32 __pwr_glitch_det; /* Power Glitch Detector */ - u32 __gen_purpose; - u8 __zmk[32]; /* Zeroizable Master Key */ - u32 __rsvd0; - u32 __gen_purposes[4]; /* gp0_30 to gp0_33 */ - u32 tamper_det_cfg2; /* Tamper Detectors Configuration2 */ - u32 tamper_det_status; /* Tamper Detectors status */ - u32 tamper_filt1_cfg; /* Tamper Glitch Filter1 Configuration*/ - u32 tamper_filt2_cfg; /* Tamper Glitch Filter2 Configuration*/ - u32 __rsvd1[4]; - u32 act_tamper1_cfg; /* Active Tamper1 Configuration */ - u32 act_tamper2_cfg; /* Active Tamper2 Configuration */ - u32 act_tamper3_cfg; /* Active Tamper3 Configuration */ - u32 act_tamper4_cfg; /* Active Tamper4 Configuration */ - u32 act_tamper5_cfg; /* Active Tamper5 Configuration */ - u32 __rsvd2[3]; - u32 act_tamper_ctl; /* Active Tamper Control */ - u32 act_tamper_clk_ctl; /* Active Tamper Clock Control */ - u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */ - u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */ - } lp; -}; - -static struct snvs_security_sc_conf snvs_default_config = { - .hp = { - .lock = 0x1f0703ff, - .secvio_ctl = 0x3000007f, - }, - .lp = { - .lock = 0x1f0003ff, - .secvio_ctl = 0x36, - .tamper_filt_cfg = 0, - .tamper_det_cfg = 0x76, /* analogic tampers - * + rollover tampers - */ - .tamper_det_cfg2 = 0, - .tamper_filt1_cfg = 0, - .tamper_filt2_cfg = 0, - .act_tamper1_cfg = 0, - .act_tamper2_cfg = 0, - .act_tamper3_cfg = 0, - .act_tamper4_cfg = 0, - .act_tamper5_cfg = 0, - .act_tamper_ctl = 0, - .act_tamper_clk_ctl = 0, - .act_tamper_routing_ctl1 = 0, - .act_tamper_routing_ctl2 = 0, - } -}; - -static struct snvs_security_sc_conf snvs_passive_vcc_config = { - .hp = { - .lock = 0x1f0703ff, - .secvio_ctl = 0x3000007f, - }, - .lp = { - .lock = 0x1f0003ff, - .secvio_ctl = 0x36, - .tamper_filt_cfg = 0, - .tamper_det_cfg = 0x276, /* ET1 will trig on line at GND - * + analogic tampers - * + rollover tampers - */ - .tamper_det_cfg2 = 0, - .tamper_filt1_cfg = 0, - .tamper_filt2_cfg = 0, - .act_tamper1_cfg = 0, - .act_tamper2_cfg = 0, - .act_tamper3_cfg = 0, - .act_tamper4_cfg = 0, - .act_tamper5_cfg = 0, - .act_tamper_ctl = 0, - .act_tamper_clk_ctl = 0, - .act_tamper_routing_ctl1 = 0, - .act_tamper_routing_ctl2 = 0, - } -}; - -static struct snvs_security_sc_conf snvs_passive_gnd_config = { - .hp = { - .lock = 0x1f0703ff, - .secvio_ctl = 0x3000007f, - }, - .lp = { - .lock = 0x1f0003ff, - .secvio_ctl = 0x36, - .tamper_filt_cfg = 0, - .tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC - * + analogic tampers - * + rollover tampers - */ - .tamper_det_cfg2 = 0, - .tamper_filt1_cfg = 0, - .tamper_filt2_cfg = 0, - .act_tamper1_cfg = 0, - .act_tamper2_cfg = 0, - .act_tamper3_cfg = 0, - .act_tamper4_cfg = 0, - .act_tamper5_cfg = 0, - .act_tamper_ctl = 0, - .act_tamper_clk_ctl = 0, - .act_tamper_routing_ctl1 = 0, - .act_tamper_routing_ctl2 = 0, - } -}; - -static struct snvs_security_sc_conf snvs_active_config = { - .hp = { - .lock = 0x1f0703ff, - .secvio_ctl = 0x3000007f, - }, - .lp = { - .lock = 0x1f0003ff, - .secvio_ctl = 0x36, - .tamper_filt_cfg = 0x00800000, /* Enable filtering */ - .tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers - * + rollover tampers - */ - .tamper_det_cfg2 = 0, - .tamper_filt1_cfg = 0, - .tamper_filt2_cfg = 0, - .act_tamper1_cfg = 0x84001111, - .act_tamper2_cfg = 0, - .act_tamper3_cfg = 0, - .act_tamper4_cfg = 0, - .act_tamper5_cfg = 0, - .act_tamper_ctl = 0x00010001, - .act_tamper_clk_ctl = 0, - .act_tamper_routing_ctl1 = 0x1, - .act_tamper_routing_ctl2 = 0, - } -}; - +#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO static struct snvs_security_sc_conf *get_snvs_config(void) { return &snvs_default_config; } -struct snvs_dgo_conf { - u32 tamper_offset_ctl; - u32 tamper_pull_ctl; - u32 tamper_ana_test_ctl; - u32 tamper_sensor_trim_ctl; - u32 tamper_misc_ctl; - u32 tamper_core_volt_mon_ctl; -}; - -static struct snvs_dgo_conf snvs_dgo_default_config = { - .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ -}; - -static struct snvs_dgo_conf snvs_dgo_passive_vcc_config = { - .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ - .tamper_pull_ctl = 0x00000001, /* Pull down ET1 */ - .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ -}; - -static struct snvs_dgo_conf snvs_dgo_passive_gnd_config = { - .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ - .tamper_pull_ctl = 0x00000401, /* Pull up ET1 */ - .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ -}; - -static struct snvs_dgo_conf snvs_dgo_active_config = { - .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ - .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ -}; - static struct snvs_dgo_conf *get_snvs_dgo_config(void) { return &snvs_dgo_default_config; } - -struct tamper_pin_cfg { - u32 pad; - u32 mux_conf; -}; - -static struct tamper_pin_cfg tamper_pin_list_default_config[] = { - {SC_P_CSI_D00, 0}, /* Tamp_Out0 */ - {SC_P_CSI_D01, 0}, /* Tamp_Out1 */ - {SC_P_CSI_D02, 0}, /* Tamp_Out2 */ - {SC_P_CSI_D03, 0}, /* Tamp_Out3 */ - {SC_P_CSI_D04, 0}, /* Tamp_Out4 */ - {SC_P_CSI_D05, 0}, /* Tamp_In0 */ - {SC_P_CSI_D06, 0}, /* Tamp_In1 */ - {SC_P_CSI_D07, 0}, /* Tamp_In2 */ - {SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */ - {SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */ -}; - -static struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = { - {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */ -}; - -static struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = { - {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */ -}; - -static struct tamper_pin_cfg tamper_pin_list_active_config[] = { - {SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */ - {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */ -}; +#endif #define TAMPER_PIN_LIST_CHOSEN tamper_pin_list_default_config @@ -282,11 +68,11 @@ static u32 ptr_value(u32 *_p) return (_p) ? *_p : 0xdeadbeef; } -static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2, - u32 *_p3, u32 *_p4, u32 *_p5, - u32 _cnt) +static sc_err_t check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2, + u32 *_p3, u32 *_p4, u32 *_p5, + u32 _cnt) { - int scierr = 0; + sc_err_t scierr = 0; u32 d1 = ptr_value(_p1); u32 d2 = ptr_value(_p2); u32 d3 = ptr_value(_p3); @@ -323,12 +109,13 @@ static int check_write_secvio_config(u32 id, u32 *_p1, u32 *_p2, static int apply_snvs_config(struct snvs_security_sc_conf *cnf) { - int scierr = 0; + sc_err_t scierr = 0; debug("%s\n", __func__); debug("Applying config:\n" "\thp.lock = 0x%.8x\n" + "\thp.secvio_intcfg = 0x%.8x\n" "\thp.secvio_ctl = 0x%.8x\n" "\tlp.lock = 0x%.8x\n" "\tlp.secvio_ctl = 0x%.8x\n" @@ -347,6 +134,7 @@ static int apply_snvs_config(struct snvs_security_sc_conf *cnf) "\tlp.act_tamper_routing_ctl1 = 0x%.8x\n" "\tlp.act_tamper_routing_ctl2 = 0x%.8x\n", cnf->hp.lock, + cnf->hp.secvio_intcfg, cnf->hp.secvio_ctl, cnf->lp.lock, cnf->lp.secvio_ctl, @@ -377,9 +165,9 @@ static int apply_snvs_config(struct snvs_security_sc_conf *cnf) scierr = check_write_secvio_config(SC_CONF_OFFSET_OF(lp.act_tamper1_cfg), &cnf->lp.act_tamper1_cfg, &cnf->lp.act_tamper2_cfg, - &cnf->lp.act_tamper2_cfg, - &cnf->lp.act_tamper2_cfg, - &cnf->lp.act_tamper2_cfg, 5); + &cnf->lp.act_tamper3_cfg, + &cnf->lp.act_tamper4_cfg, + &cnf->lp.act_tamper5_cfg, 5); if (scierr != SC_ERR_NONE) goto exit; @@ -423,14 +211,23 @@ static int apply_snvs_config(struct snvs_security_sc_conf *cnf) if (scierr != SC_ERR_NONE) goto exit; - /* Lock access */ - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock); + scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.secvio_intcfg), + &cnf->hp.secvio_intcfg); if (scierr != SC_ERR_NONE) goto exit; - scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock); - if (scierr != SC_ERR_NONE) - goto exit; + /* Lock access */ + if (cnf->hp.lock) { + scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(hp.lock), &cnf->hp.lock); + if (scierr != SC_ERR_NONE) + goto exit; + } + + if (cnf->lp.lock) { + scierr = SC_CHECK_WRITE1(SC_CONF_OFFSET_OF(lp.lock), &cnf->lp.lock); + if (scierr != SC_ERR_NONE) + goto exit; + } exit: return (scierr == SC_ERR_NONE) ? 0 : -EIO; @@ -468,28 +265,28 @@ static int apply_snvs_dgo_config(struct snvs_dgo_conf *cnf) cnf->tamper_misc_ctl, cnf->tamper_core_volt_mon_ctl); - dgo_write(0x04, 1, &cnf->tamper_offset_ctl); + scierr = dgo_write(0x04, 1, &cnf->tamper_offset_ctl); if (scierr != SC_ERR_NONE) goto exit; - dgo_write(0x14, 1, &cnf->tamper_pull_ctl); + scierr = dgo_write(0x14, 1, &cnf->tamper_pull_ctl); if (scierr != SC_ERR_NONE) goto exit; - dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl); + scierr = dgo_write(0x24, 1, &cnf->tamper_ana_test_ctl); if (scierr != SC_ERR_NONE) goto exit; - dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl); + scierr = dgo_write(0x34, 1, &cnf->tamper_sensor_trim_ctl); if (scierr != SC_ERR_NONE) goto exit; - dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl); + scierr = dgo_write(0x54, 1, &cnf->tamper_core_volt_mon_ctl); if (scierr != SC_ERR_NONE) goto exit; /* Last as it could lock the writes */ - dgo_write(0x44, 1, &cnf->tamper_misc_ctl); + scierr = dgo_write(0x44, 1, &cnf->tamper_misc_ctl); if (scierr != SC_ERR_NONE) goto exit; @@ -509,6 +306,18 @@ static int pad_write(u32 _pad, u32 _value) return scierr; } +static int pad_read(u32 _pad, u32 *_value) +{ + int sciErr = sc_pad_get(-1, _pad, _value); + + if (sciErr != SC_ERR_NONE) { + printf("Failed to get pad configuration\n"); + printf("Failed to get conf pad %d", _pad); + } + + return sciErr; +} + static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size) { int scierr = 0; @@ -517,9 +326,12 @@ static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size) debug("%s\n", __func__); for (idx = 0; idx < size; idx++) { + if (confs[idx].pad == TAMPER_NOT_DEFINED) + continue; + debug("\t idx %d: pad %d: 0x%.8x\n", idx, confs[idx].pad, confs[idx].mux_conf); - pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf); + scierr = pad_write(confs[idx].pad, 3 << 30 | confs[idx].mux_conf); if (scierr != SC_ERR_NONE) goto exit; } @@ -528,41 +340,6 @@ static int apply_tamper_pin_list_config(struct tamper_pin_cfg *confs, u32 size) return (scierr == SC_ERR_NONE) ? 0 : -EIO; } -int examples(void) -{ - u32 size; - struct snvs_security_sc_conf *snvs_conf; - struct snvs_dgo_conf *snvs_dgo_conf; - struct tamper_pin_cfg *tamper_pin_conf; - - /* Caller */ - snvs_conf = get_snvs_config(); - snvs_dgo_conf = get_snvs_dgo_config(); - tamper_pin_conf = get_tamper_pin_cfg_list(&size); - - /* Default */ - snvs_conf = &snvs_default_config; - snvs_dgo_conf = &snvs_dgo_default_config; - tamper_pin_conf = tamper_pin_list_default_config; - - /* Passive tamper expecting VCC on the line */ - snvs_conf = &snvs_passive_vcc_config; - snvs_dgo_conf = &snvs_dgo_passive_vcc_config; - tamper_pin_conf = tamper_pin_list_passive_vcc_config; - - /* Passive tamper expecting GND on the line */ - snvs_conf = &snvs_passive_gnd_config; - snvs_dgo_conf = &snvs_dgo_passive_gnd_config; - tamper_pin_conf = tamper_pin_list_passive_gnd_config; - - /* Active tamper */ - snvs_conf = &snvs_active_config; - snvs_dgo_conf = &snvs_dgo_active_config; - tamper_pin_conf = tamper_pin_list_active_config; - - return !snvs_conf + !snvs_dgo_conf + !tamper_pin_conf; -} - #ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO int snvs_security_sc_init(void) { @@ -606,6 +383,7 @@ int snvs_security_sc_init(void) static char snvs_cfg_help_text[] = "snvs_cfg\n" "\thp.lock\n" + "\thp.secvio_intcfg\n" "\thp.secvio_ctl\n" "\tlp.lock\n" "\tlp.secvio_ctl\n" @@ -626,7 +404,7 @@ static char snvs_cfg_help_text[] = "\n" "ALL values should be in hexadecimal format"; -#define NB_REGISTERS 18 +#define NB_REGISTERS 19 static int do_snvs_cfg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -639,6 +417,7 @@ static int do_snvs_cfg(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_USAGE; conf.hp.lock = simple_strtoul(argv[++idx], NULL, 16); + conf.hp.secvio_intcfg = simple_strtoul(argv[++idx], NULL, 16); conf.hp.secvio_ctl = simple_strtoul(argv[++idx], NULL, 16); conf.lp.lock = simple_strtoul(argv[++idx], NULL, 16); conf.lp.secvio_ctl = simple_strtoul(argv[++idx], NULL, 16); @@ -742,8 +521,6 @@ U_BOOT_CMD(tamper_pin_cfg, static char snvs_clear_status_help_text[] = "snvs_clear_status\n" - "\tHPSR\n" - "\tHPSVSR\n" "\tLPSR\n" "\tLPTDSR\n" "\n" @@ -753,7 +530,7 @@ static char snvs_clear_status_help_text[] = static int do_snvs_clear_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { - int scierr = 0; + sc_err_t scierr = 0; u32 idx = 0; struct snvs_security_sc_conf conf = {0}; @@ -795,21 +572,9 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, { int scierr; u32 idx; - + u32 nb_pins; u32 data[5]; - - u32 pads[] = { - SC_P_CSI_D00, - SC_P_CSI_D01, - SC_P_CSI_D02, - SC_P_CSI_D03, - SC_P_CSI_D04, - SC_P_CSI_D05, - SC_P_CSI_D06, - SC_P_CSI_D07, - SC_P_CSI_HSYNC, - SC_P_CSI_VSYNC, - }; + struct tamper_pin_cfg *pin_cfg_list = get_tamper_pin_cfg_list(&nb_pins); u32 fuses[] = { 14, @@ -861,14 +626,17 @@ static int do_snvs_sec_status(struct cmd_tbl *cmdtp, int flag, int argc, /* Pins */ printf("Pins:\n"); - for (idx = 0; idx < ARRAY_SIZE(pads); idx++) { - u8 pad_id = pads[idx]; + for (idx = 0; idx < nb_pins; idx++) { + struct tamper_pin_cfg *cfg = &pin_cfg_list[idx]; - scierr = sc_pad_get(-1, pad_id, &data[0]); + if (cfg->pad == TAMPER_NOT_DEFINED) + continue; + + scierr = sc_pad_get(-1, cfg->pad, &data[0]); if (scierr == 0) - printf("\t- Pin %d: %.8x\n", pad_id, data[0]); + printf("\t- Pin %d: %.8x\n", cfg->pad, data[0]); else - printf("Failed to read Pin %d\n", pad_id); + printf("Failed to read Pin %d\n", cfg->pad); } /* Fuses */ @@ -923,3 +691,116 @@ U_BOOT_CMD(snvs_sec_status, "tamper pin configuration", snvs_sec_status_help_text ); + +static char gpio_conf_help_text[] = + "gpio_conf \n" + "Configure the GPIO of an IOMUX:\n" + " - pad:\n" + " - hexval:"; + +static int do_gpio_conf(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int err = -EIO; + int sciErr; + u32 pad, val, valcheck; + + pad = simple_strtoul(argv[1], NULL, 10); + val = simple_strtoul(argv[2], NULL, 16); + + printf("Configuring GPIO %d with %x\n", pad, val); + + sciErr = pad_write(pad, 3 << 30 | val); + if (sciErr != SC_ERR_NONE) { + printf("Error writing conf\n"); + goto exit; + } + + sciErr = pad_read(pad, &valcheck); + if (sciErr != SC_ERR_NONE) { + printf("Error reading conf\n"); + goto exit; + } + + if (valcheck != val) { + printf("Error: configured %x instead of %x\n", valcheck, val); + goto exit; + } + + err = 0; + +exit: + return err; +} + +U_BOOT_CMD(gpio_conf, + 3, 1, do_gpio_conf, + "gpio configuration", + gpio_conf_help_text +); + +static +int do_set_fips_mode(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u8 fips_mode = 0; + struct arm_smccc_res res; + + if (argc < 2) + return CMD_RET_USAGE; + + fips_mode = simple_strtoul(argv[1], NULL, 16); + + if (argc == 2) { + printf("Warning: Setting FIPS mode [%x] will burn a fuse and\n" + "is permanent\n" + "Really perform this fuse programming? \n", + fips_mode); + + /* If the user does not answer yes (1), we return */ + if (confirm_yesno() != 1) + return 0; + } + + if (argc == 3 && !(argv[2][0] == '-' && argv[2][1] == 'y')) + return CMD_RET_USAGE; + + arm_smccc_smc(IMX_SIP_FIPS_CONFIG, IMX_SIP_FIPS_CONFIG_SET, + fips_mode, 0, 0, 0, 0, 0, &res); + if (res.a0) { + printf("Failed to set fips mode %d. err: %ld\n", + fips_mode, res.a0); + } + + return (res.a0) ? CMD_RET_FAILURE : CMD_RET_SUCCESS; +} + +U_BOOT_CMD(set_fips_mode, + 3, 0, do_set_fips_mode, + "Set FIPS mode", + " [-y] \n" + " The SoC will be configured in FIPS (PERMANENT)\n" + " If \"-y\" is not passed, the function will ask for validation\n" + "ex: set_fips_mode 1\n" +); + +static +int do_check_fips_mode(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int err = -EIO; + u32 fuse_value = 0; + + /* The FIPS bit is the bit 3 in the word 0xA */ + err = sc_misc_otp_fuse_read(-1, 0xA, &fuse_value); + if (err) + return err; + + printf("FIPS mode: %x\n", fuse_value >> 3 & 0x1); + + return 0; +} + +U_BOOT_CMD(check_fips_mode, + 1, 0, do_check_fips_mode, + "Display the FIPS mode of the SoC by reading fuse 0xA, bit 3", + NULL +); diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf.h new file mode 100644 index 00000000000..79c5ed57c3a --- /dev/null +++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP. + */ + +#ifndef SNVS_SECURITY_SC_CONF_H_ +#define SNVS_SECURITY_SC_CONF_H_ + +/* + * File to list different example of tamper configuration: + * - default + * - passive to ground + * - passive to vcc + * - active + * + * for the different platform supported: + * - imx8qxp-mek + * - imx8qm-mek + * - imx8dxl-evk + */ + +#include + +/* Definition of the structures */ + +struct snvs_security_sc_conf { + struct snvs_hp_conf { + u32 lock; /* HPLR - HP Lock */ + u32 __cmd; /* HPCOMR - HP Command */ + u32 __ctl; /* HPCR - HP Control */ + u32 secvio_intcfg; /* HPSICR - Security Violation Int + * Config + */ + u32 secvio_ctl; /* HPSVCR - Security Violation Control*/ + u32 status; /* HPSR - HP Status */ + u32 secvio_status; /* HPSVSR - Security Violation Status */ + u32 __ha_counteriv; /* High Assurance Counter IV */ + u32 __ha_counter; /* High Assurance Counter */ + u32 __rtc_msb; /* Real Time Clock/Counter MSB */ + u32 __rtc_lsb; /* Real Time Counter LSB */ + u32 __time_alarm_msb; /* Time Alarm MSB */ + u32 __time_alarm_lsb; /* Time Alarm LSB */ + } hp; + struct snvs_lp_conf { + u32 lock; + u32 __ctl; + u32 __mstr_key_ctl; /* Master Key Control */ + u32 secvio_ctl; /* Security Violation Control */ + u32 tamper_filt_cfg; /* Tamper Glitch Filters Configuration*/ + u32 tamper_det_cfg; /* Tamper Detectors Configuration */ + u32 status; + u32 __srtc_msb; /* Secure Real Time Clock/Counter MSB */ + u32 __srtc_lsb; /* Secure Real Time Clock/Counter LSB */ + u32 __time_alarm; /* Time Alarm */ + u32 __smc_msb; /* Secure Monotonic Counter MSB */ + u32 __smc_lsb; /* Secure Monotonic Counter LSB */ + u32 __pwr_glitch_det; /* Power Glitch Detector */ + u32 __gen_purpose; + u8 __zmk[32]; /* Zeroizable Master Key */ + u32 __rsvd0; + u32 __gen_purposes[4]; /* gp0_30 to gp0_33 */ + u32 tamper_det_cfg2; /* Tamper Detectors Configuration2 */ + u32 tamper_det_status; /* Tamper Detectors status */ + u32 tamper_filt1_cfg; /* Tamper Glitch Filter1 Configuration*/ + u32 tamper_filt2_cfg; /* Tamper Glitch Filter2 Configuration*/ + u32 __rsvd1[4]; + u32 act_tamper1_cfg; /* Active Tamper1 Configuration */ + u32 act_tamper2_cfg; /* Active Tamper2 Configuration */ + u32 act_tamper3_cfg; /* Active Tamper3 Configuration */ + u32 act_tamper4_cfg; /* Active Tamper4 Configuration */ + u32 act_tamper5_cfg; /* Active Tamper5 Configuration */ + u32 __rsvd2[3]; + u32 act_tamper_ctl; /* Active Tamper Control */ + u32 act_tamper_clk_ctl; /* Active Tamper Clock Control */ + u32 act_tamper_routing_ctl1;/* Active Tamper Routing Control1 */ + u32 act_tamper_routing_ctl2;/* Active Tamper Routing Control2 */ + } lp; +}; + +struct snvs_dgo_conf { + u32 tamper_offset_ctl; + u32 tamper_pull_ctl; + u32 tamper_ana_test_ctl; + u32 tamper_sensor_trim_ctl; + u32 tamper_misc_ctl; + u32 tamper_core_volt_mon_ctl; +}; + +struct tamper_pin_cfg { + u32 pad; + u32 mux_conf; +}; + +#define TAMPER_NOT_DEFINED -1 +#define TAMPER_NO_IOMUX TAMPER_NOT_DEFINED + +/* There is 10 tampers and the list start at 1 */ +enum EXT_TAMPER { + EXT_TAMPER_ET1 = 0, + EXT_TAMPER_ET2 = 1, + EXT_TAMPER_ET3 = 2, + EXT_TAMPER_ET4 = 3, + EXT_TAMPER_ET5 = 4, + EXT_TAMPER_ET6 = 5, + EXT_TAMPER_ET7 = 6, + EXT_TAMPER_ET8 = 7, + EXT_TAMPER_ET9 = 8, + EXT_TAMPER_ET10 = 9, +}; + +enum ACT_TAMPER { + ACT_TAMPER_AT1 = EXT_TAMPER_ET6, + ACT_TAMPER_AT2 = EXT_TAMPER_ET7, + ACT_TAMPER_AT3 = EXT_TAMPER_ET8, + ACT_TAMPER_AT4 = EXT_TAMPER_ET9, + ACT_TAMPER_AT5 = EXT_TAMPER_ET10, +}; + +#endif /* SNVS_SECURITY_SC_CONF_H_ */ diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8dxl_evk.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8dxl_evk.h new file mode 100644 index 00000000000..2b4e6bc27f4 --- /dev/null +++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8dxl_evk.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP. + */ + +#ifndef SNVS_SECURITY_SC_CONF_8DXL_EVK_H_ +#define SNVS_SECURITY_SC_CONF_8DXL_EVK_H_ + +#include "snvs_security_sc_conf.h" + +static __maybe_unused struct snvs_security_sc_conf snvs_default_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x76, /* analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x076, /* analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0x11, /* ET3 + ET7 will trig on line at GND*/ + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x076, /* analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0x110011, /* ET3 + ET7 will trig on line at + * VCC + */ + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_active_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x076, /* analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0x10, /* Enable ET7 tamper */ + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0x80, /* Enable filtering */ + .act_tamper1_cfg = 0x84001111, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0x10001, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0x1000000, /* Route AT1 to ET 7 */ + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00000044, /* Pull down IN4 and OUT0 */ + .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00011044, /* Pull down IN4 and OUT0 */ + .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ +}; + +static struct tamper_pin_cfg tamper_pin_list_default_config[] = { + {SC_P_SNVS_TAMPER_IN0, 0}, /* Tamp_In0 */ + {SC_P_SNVS_TAMPER_IN1, 0}, /* Tamp_In1 */ + {SC_P_SNVS_TAMPER_IN2, 0}, /* Tamp_In2 */ + {SC_P_SNVS_TAMPER_IN3, 0}, /* Tamp_In3 */ + {TAMPER_NO_IOMUX, 0}, /* Tamp_In4 */ + {TAMPER_NO_IOMUX, 0}, /* Tamp_Out0 */ + {SC_P_SNVS_TAMPER_OUT1, 0}, /* Tamp_Out1 */ + {SC_P_SNVS_TAMPER_OUT2, 0}, /* Tamp_Out2 */ + {SC_P_SNVS_TAMPER_OUT3, 0}, /* Tamp_Out3 */ + {SC_P_SNVS_TAMPER_OUT4, 0}, /* Tamp_Out4 */ +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = { +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = { +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = { +}; + +#endif /* SNVS_SECURITY_SC_CONF_8DXL_EVK_H_ */ diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_mek.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_mek.h new file mode 100644 index 00000000000..20dad8b126b --- /dev/null +++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qm_mek.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP. + */ + +#ifndef SNVS_SECURITY_SC_CONF_8QM_MEK_H_ +#define SNVS_SECURITY_SC_CONF_8QM_MEK_H_ + +#include "snvs_security_sc_conf.h" + +/* Configuration */ + +static __maybe_unused struct snvs_security_sc_conf snvs_default_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x76, /* analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x276, /* ET1 will trig on line at GND + * + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC + * + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_active_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0x00800000, /* Enable filtering */ + .tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0x84001111, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0x00010001, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0x1, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00000001, /* Pull down ET1 */ +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00000401, /* Pull up ET1 */ +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ +}; + +static struct tamper_pin_cfg tamper_pin_list_default_config[] = { +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = { +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = { +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = { +}; + +#endif /* SNVS_SECURITY_SC_CONF_8QM_MEK_H_ */ diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qxp_mek.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qxp_mek.h new file mode 100644 index 00000000000..2cd3461008d --- /dev/null +++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_8qxp_mek.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP. + */ + +#ifndef SNVS_SECURITY_SC_CONF_8QXP_MEK_H_ +#define SNVS_SECURITY_SC_CONF_8QXP_MEK_H_ + +#include "snvs_security_sc_conf.h" + +static __maybe_unused struct snvs_security_sc_conf snvs_default_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x76, /* analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_passive_vcc_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x276, /* ET1 will trig on line at GND + * + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_passive_gnd_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0xa76, /* ET1 will trig on line at VCC + * + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_security_sc_conf snvs_active_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0x00800000, /* Enable filtering */ + .tamper_det_cfg = 0x276, /* ET1 enabled + analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0x84001111, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0x00010001, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0x1, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_vcc_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00000001, /* Pull down ET1 */ + .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_passive_gnd_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_pull_ctl = 0x00000401, /* Pull up ET1 */ + .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_active_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ + .tamper_ana_test_ctl = 0x20000000, /* Enable tamper */ +}; + +static struct tamper_pin_cfg tamper_pin_list_default_config[] = { + {SC_P_CSI_D05, 0}, /* Tamp_In0 */ + {SC_P_CSI_D06, 0}, /* Tamp_In1 */ + {SC_P_CSI_D07, 0}, /* Tamp_In2 */ + {SC_P_CSI_HSYNC, 0}, /* Tamp_In3 */ + {SC_P_CSI_VSYNC, 0}, /* Tamp_In4 */ + {SC_P_CSI_D00, 0}, /* Tamp_Out0 */ + {SC_P_CSI_D01, 0}, /* Tamp_Out1 */ + {SC_P_CSI_D02, 0}, /* Tamp_Out2 */ + {SC_P_CSI_D03, 0}, /* Tamp_Out3 */ + {SC_P_CSI_D04, 0}, /* Tamp_Out4 */ +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_vcc_config[] = { + {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */ +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_passive_gnd_config[] = { + {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */ +}; + +static __maybe_unused struct tamper_pin_cfg tamper_pin_list_active_config[] = { + {SC_P_CSI_D00, 0x1a000060}, /* Tamp_Out0 */ /* Sel tamper + OD */ + {SC_P_CSI_D05, 0x1c000060}, /* Tamp_In0 */ /* Sel tamper + OD input */ +}; + +#endif /* SNVS_SECURITY_SC_CONF_8QXP_MEK_H_ */ diff --git a/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h new file mode 100644 index 00000000000..250952b7df6 --- /dev/null +++ b/arch/arm/mach-imx/imx8/snvs_security_sc_conf_board.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP. + */ + +#ifndef SNVS_SECURITY_SC_CONF_BOARD_H_ +#define SNVS_SECURITY_SC_CONF_BOARD_H_ + +#ifdef CONFIG_TARGET_IMX8QM_MEK +#include "snvs_security_sc_conf_8qm_mek.h" +#elif CONFIG_TARGET_IMX8QXP_MEK +#include "snvs_security_sc_conf_8qxp_mek.h" +#elif CONFIG_TARGET_IMX8DXL_EVK +#include "snvs_security_sc_conf_8dxl_evk.h" +#else + +#include "snvs_security_sc_conf.h" + +/* Default configuration of the tamper for all boards */ +static __maybe_unused struct snvs_security_sc_conf snvs_default_config = { + .hp = { + .lock = 0x1f0703ff, + .secvio_intcfg = 0x8000002f, + .secvio_ctl = 0xC000007f, + }, + .lp = { + .lock = 0x1f0003ff, + .secvio_ctl = 0x36, + .tamper_filt_cfg = 0, + .tamper_det_cfg = 0x76, /* analogic tampers + * + rollover tampers + */ + .tamper_det_cfg2 = 0, + .tamper_filt1_cfg = 0, + .tamper_filt2_cfg = 0, + .act_tamper1_cfg = 0, + .act_tamper2_cfg = 0, + .act_tamper3_cfg = 0, + .act_tamper4_cfg = 0, + .act_tamper5_cfg = 0, + .act_tamper_ctl = 0, + .act_tamper_clk_ctl = 0, + .act_tamper_routing_ctl1 = 0, + .act_tamper_routing_ctl2 = 0, + } +}; + +static __maybe_unused struct snvs_dgo_conf snvs_dgo_default_config = { + .tamper_misc_ctl = 0x80000000, /* Lock the DGO */ +}; + +static struct tamper_pin_cfg tamper_pin_list_default_config[] = {0}; + +#endif + +#endif /* SNVS_SECURITY_SC_CONF_BOARD_H_ */ diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 12b8d0d8312..f9af50febdb 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -2,19 +2,23 @@ if ARCH_IMX8M config IMX8M bool + select HAS_CAAM select ROM_UNIFIED_SECTIONS config IMX8MQ bool select IMX8M + select ARMV8_SPL_EXCEPTION_VECTORS config IMX8MM bool select IMX8M + select ARMV8_SPL_EXCEPTION_VECTORS config IMX8MN bool select IMX8M + select ARMV8_SPL_EXCEPTION_VECTORS config IMX8MP bool @@ -23,6 +27,25 @@ config IMX8MP config SYS_SOC default "imx8m" +config SECONDARY_BOOT_SECTOR_OFFSET + hex "SD/MMC sector offset used for ROM secondary boot" + default 0x0 + depends on IMX8MQ || IMX8MM + help + Set the sector offset to non-zero value in SPL used for + secondary boot image. This value should be same as the + firstSectorNumber in secondary image table. + +config SECURE_STICKY_BITS_LOCKUP + bool "Enable workaround to fix sticky bits lock up issue" + depends on IMX8MQ && IMX_HAB + default y + +config IMX_UNIQUE_ID + hex "Enable workaround to fix sticky bits lock up issue" + depends on IMX8MQ && IMX_HAB && !SECURE_STICKY_BITS_LOCKUP + default 0x0 + choice prompt "NXP i.MX8M board select" optional @@ -31,17 +54,46 @@ config TARGET_IMX8MQ_EVK bool "imx8mq_evk" select IMX8MQ select IMX8M_LPDDR4 + select FSL_CAAM + select FSL_BLOB + select MISC + select SPL_CRYPTO_SUPPORT if SPL config TARGET_IMX8MQ_PHANBELL bool "imx8mq_phanbell" select IMX8MQ select IMX8M_LPDDR4 +config TARGET_IMX8MQ_DDR3L_VAL + bool "imx8mq_ddr3l_val" + select IMX8MQ + +config TARGET_IMX8MQ_DDR4_VAL + bool "imx8mq_ddr4_val" + select IMX8MQ + select IMX8M_DDR4 + +config TARGET_IMX8MM_DDR4_VAL + bool "imx8mm DDR4 validation board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR4 + +config TARGET_IMX8MM_DDR3L_VAL + bool "imx8mm DDR3L validation board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR3L + config TARGET_IMX8MM_EVK bool "imx8mm LPDDR4 EVK board" select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select FSL_BLOB + select MISC + select SPL_CRYPTO_SUPPORT if SPL config TARGET_IMX8MM_VENICE bool "Support Gateworks Venice iMX8M Mini module" @@ -49,23 +101,77 @@ config TARGET_IMX8MM_VENICE select SUPPORT_SPL select IMX8M_LPDDR4 +config TARGET_IMX8MM_EVK_QCA + bool "imx8mm LPDDR4 EVK Legacy QCA WIFI board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MM_DDR4_EVK + bool "imx8mm DDR4 EVK board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR4 + select FSL_CAAM + select FSL_BLOB + select MISC + select SPL_CRYPTO_SUPPORT if SPL + +config TARGET_IMX8MN_EVK + bool "imx8mn LPDDR4 EVK board" + select IMX8MN + select SUPPORT_SPL + select IMX8M_LPDDR4 + select FSL_CAAM + select FSL_BLOB + select MISC + select SPL_CRYPTO_SUPPORT if SPL + config TARGET_IMX8MN_DDR4_EVK bool "imx8mn DDR4 EVK board" select IMX8MN select SUPPORT_SPL select IMX8M_DDR4 + select FSL_CAAM + select FSL_BLOB + select MISC + select SPL_CRYPTO_SUPPORT if SPL + +config TARGET_IMX8MN_DDR3_EVK + bool "imx8mn 11x11 DDR3 EVK board" + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR3L + select FSL_CAAM + select FSL_BLOB + select MISC + select SPL_CRYPTO_SUPPORT if SPL config TARGET_IMX8MP_EVK bool "imx8mp LPDDR4 EVK board" select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + select FSL_CAAM + select FSL_BLOB + select MISC + select SPL_CRYPTO_SUPPORT if SPL config TARGET_PICO_IMX8MQ bool "Support Technexion Pico iMX8MQ" select IMX8MQ select IMX8M_LPDDR4 +config TARGET_IMX8MP_DDR4_EVK + bool "imx8mp DDR4 EVK board" + select IMX8MP + select SUPPORT_SPL + select IMX8M_DDR4 + select FSL_CAAM + select FSL_BLOB + select MISC + select SPL_CRYPTO_SUPPORT if SPL + config TARGET_VERDIN_IMX8MM bool "Support Toradex Verdin iMX8M Mini module" select IMX8MM @@ -95,10 +201,13 @@ config TARGET_PHYCORE_IMX8MP select IMX8MP select SUPPORT_SPL select IMX8M_LPDDR4 + endchoice source "board/freescale/imx8mq_evk/Kconfig" +source "board/freescale/imx8mq_val/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" +source "board/freescale/imx8mm_val/Kconfig" source "board/freescale/imx8mn_evk/Kconfig" source "board/freescale/imx8mp_evk/Kconfig" source "board/gateworks/venice/Kconfig" @@ -109,5 +218,6 @@ source "board/beacon/imx8mm/Kconfig" source "board/beacon/imx8mn/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" +source "board/compulab/plat/Kconfig" endif diff --git a/arch/arm/mach-imx/imx8m/Kconfig_plus b/arch/arm/mach-imx/imx8m/Kconfig_plus new file mode 100644 index 00000000000..d21b403be75 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/Kconfig_plus @@ -0,0 +1,204 @@ +if ARCH_IMX8M + +config IMX8M + bool + select HAS_CAAM + select ROM_UNIFIED_SECTIONS + +config IMX8MQ + bool + select IMX8M + select ARMV8_SPL_EXCEPTION_VECTORS + +config IMX8MM + bool + select IMX8M + select ARMV8_SPL_EXCEPTION_VECTORS + +config IMX8MN + bool + select IMX8M + select ARMV8_SPL_EXCEPTION_VECTORS + +config IMX8MP + bool + select IMX8M + +config SYS_SOC + default "imx8m" + +config SECONDARY_BOOT_SECTOR_OFFSET + hex "SD/MMC sector offset used for ROM secondary boot" + default 0x0 + depends on IMX8MQ || IMX8MM + help + Set the sector offset to non-zero value in SPL used for + secondary boot image. This value should be same as the + firstSectorNumber in secondary image table. + +config SECURE_STICKY_BITS_LOCKUP + bool "Enable workaround to fix sticky bits lock up issue" + depends on IMX8MQ && IMX_HAB + default y + +config IMX_UNIQUE_ID + hex "Enable workaround to fix sticky bits lock up issue" + depends on IMX8MQ && IMX_HAB && !SECURE_STICKY_BITS_LOCKUP + default 0x0 + +choice + prompt "NXP i.MX8M board select" + optional + +config TARGET_IMX8MQ_EVK + bool "imx8mq_evk" + select IMX8MQ + select IMX8M_LPDDR4 + +config TARGET_IMX8MQ_DDR3L_VAL + bool "imx8mq_ddr3l_val" + select IMX8MQ + +config TARGET_IMX8MQ_DDR4_VAL + bool "imx8mq_ddr4_val" + select IMX8MQ + select IMX8M_DDR4 + +config TARGET_IMX8MM_DDR4_VAL + bool "imx8mm DDR4 validation board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR4 + +config TARGET_IMX8MM_DDR3L_VAL + bool "imx8mm DDR3L validation board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR3L + +config TARGET_IMX8MM_EVK + bool "imx8mm LPDDR4 EVK board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MM_EVK_QCA + bool "imx8mm LPDDR4 EVK Legacy QCA WIFI board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MM_DDR4_EVK + bool "imx8mm DDR4 EVK board" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR4 + +config TARGET_IMX8MN_EVK + bool "imx8mn LPDDR4 EVK board" + select IMX8MN + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MN_DDR4_EVK + bool "imx8mn DDR4 EVK board" + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR4 + +config TARGET_IMX8MN_DDR3_EVK + bool "imx8mn 11x11 DDR3 EVK board" + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR3L + +config TARGET_IMX8MP_EVK + bool "imx8mp LPDDR4 EVK board" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MP_DDR4_EVK + bool "imx8mp DDR4 EVK board" + select IMX8MP + select SUPPORT_SPL + select IMX8M_DDR4 + +config TARGET_IMX8MM_AB2 + bool "imx8mm LPDDR4 Audio board 2.0" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MM_DDR4_AB2 + bool "imx8mm DDR4 Audio board 2.0" + select IMX8MM + select SUPPORT_SPL + select IMX8M_DDR4 + +config TARGET_IMX8MN_AB2 + bool "imx8mn LPDDR4 Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MN_DDR4_AB2 + bool "imx8mn DDR4 Audio board 2.0" + select IMX8MN + select SUPPORT_SPL + select IMX8M_DDR4 + +config TARGET_VERDIN_IMX8MM + bool "Support Toradex Verdin iMX8M Mini module" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_UCM_IMX8M_MINI + bool "CompuLab ucm-imx8m-mini" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_MCM_IMX8M_MINI + bool "CompuLab mcm-imx8m-mini" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IOT_GATE_IMX8 + bool "CompuLab iot-gate-imx8" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_UCM_IMX8M_PLUS + bool "CompuLab ucm-imx8m-plus" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IOT_GATE_IMX8PLUS + bool "CompuLab iot-gate-imx8plus" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + +endchoice + +source "board/freescale/imx8mq_evk/Kconfig" +source "board/freescale/imx8mq_val/Kconfig" +source "board/freescale/imx8mm_ab2/Kconfig" +source "board/freescale/imx8mm_evk/Kconfig" +source "board/freescale/imx8mm_val/Kconfig" +source "board/freescale/imx8mn_evk/Kconfig" +source "board/freescale/imx8mp_evk/Kconfig" +source "board/toradex/verdin-imx8mm/Kconfig" +source "board/compulab/ucm-imx8m-mini/Kconfig" +source "board/compulab/mcm-imx8m-mini/Kconfig" +source "board/compulab/iot-gate-imx8/Kconfig" +source "board/compulab/ucm-imx8m-plus/Kconfig" +#source "board/compulab/iot-gate-imx8plus/Kconfig" +source "board/compulab/plat/Kconfig" + +endif diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 4024dafca10..a97498c162f 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -15,12 +16,21 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; static u32 get_root_clk(enum clk_root_index clock_id); + +#ifdef CONFIG_IMX_HAB +void hab_caam_clock_enable(unsigned char enable) +{ + /* The CAAM clock is always on for iMX8M */ +} +#endif + void enable_ocotp_clk(unsigned char enable) { clock_enable(CCGR_OCOTP, !!enable); @@ -37,18 +47,17 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) return 0; } -#ifdef CONFIG_SPL_BUILD static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(1000000000U, 250, 3, 1, 0), - PLL_1443X_RATE(800000000U, 300, 9, 0, 0), - PLL_1443X_RATE(750000000U, 250, 8, 0, 0), + PLL_1443X_RATE(800000000U, 200, 3, 1, 0), + PLL_1443X_RATE(750000000U, 250, 2, 2, 0), PLL_1443X_RATE(650000000U, 325, 3, 2, 0), PLL_1443X_RATE(600000000U, 300, 3, 2, 0), PLL_1443X_RATE(594000000U, 99, 1, 2, 0), - PLL_1443X_RATE(400000000U, 300, 9, 1, 0), - PLL_1443X_RATE(266666667U, 400, 9, 2, 0), + PLL_1443X_RATE(400000000U, 400, 3, 3, 0), + PLL_1443X_RATE(266000000U, 266, 3, 3, 0), PLL_1443X_RATE(167000000U, 334, 3, 4, 0), - PLL_1443X_RATE(100000000U, 300, 9, 3, 0), + PLL_1443X_RATE(100000000U, 200, 3, 4, 0), }; static int fracpll_configure(enum pll_clocks pll, u32 freq) @@ -115,6 +124,7 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) return 0; } +#ifdef CONFIG_SPL_BUILD void dram_pll_init(ulong pll_val) { fracpll_configure(ANATOP_DRAM_PLL, pll_val); @@ -269,6 +279,95 @@ int intpll_configure(enum pll_clocks pll, ulong freq) return 0; } +#define VIDEO_PLL_RATE 594000000U + +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) +{ + uint32_t div, pre, post; + + div = VIDEO_PLL_RATE / 1000; + div = (div + freq - 1) / freq; + + if (div < 1) + div = 1; + + for (pre = 1; pre <= 8; pre++) { + for (post = 1; post <= 64; post++) { + if (pre * post == div) { + goto find; + } + } + } + + printf("Fail to set rate to %dkhz", freq); + return; + +find: + /* Select to video PLL */ + debug("mxs_set_lcdclk, pre = %d, post = %d\n", pre, post); + +#ifdef CONFIG_IMX8MP + clock_set_target_val(MEDIA_DISP1_PIX_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1)); +#elif defined(CONFIG_IMX8MN) + clock_set_target_val(DISPLAY_PIXEL_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1)); +#else + clock_set_target_val(LCDIF_PIXEL_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(pre - 1) | CLK_ROOT_POST_DIV(post - 1)); +#endif + +} + +#ifdef CONFIG_IMX8MP +void enable_display_clk(unsigned char enable) +{ + if (enable) { + clock_enable(CCGR_DISPMIX, false); + + /* Set Video PLL to 594Mhz, p = 1, m = 99, k = 0, s = 2 */ + fracpll_configure(ANATOP_VIDEO_PLL, VIDEO_PLL_RATE); + + /* 400Mhz */ + clock_set_target_val(MEDIA_AXI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2)); + + /* 200Mhz */ + clock_set_target_val(MEDIA_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + /* 27Mhz MIPI DPHY PLL ref from video PLL */ + clock_set_target_val(MEDIA_MIPI_PHY1_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22)); + clock_enable(CCGR_DISPMIX, true); + } else { + clock_enable(CCGR_DISPMIX, false); + } +} +#else +void enable_display_clk(unsigned char enable) +{ + if (enable) { + clock_enable(CCGR_DISPMIX, false); + + /* Set Video PLL to 594Mhz, p = 1, m = 99, k = 0, s = 2 */ + fracpll_configure(ANATOP_VIDEO_PLL, VIDEO_PLL_RATE); + + /* 500Mhz */ + clock_set_target_val(DISPLAY_AXI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2)); + + /* 200Mhz */ + clock_set_target_val(DISPLAY_APB_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + clock_set_target_val(MIPI_DSI_CORE_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + + /* 27Mhz MIPI DPHY PLL ref from video PLL */ +#ifdef CONFIG_IMX8MN + clock_set_target_val(DISPLAY_DSI_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22)); +#else + clock_set_target_val(MIPI_DSI_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22)); +#endif + clock_enable(CCGR_DISPMIX, true); + } else { + clock_enable(CCGR_DISPMIX, false); + } +} +#endif + void init_uart_clk(u32 index) { /* @@ -428,7 +527,6 @@ int clock_init(void) #ifdef CONFIG_IMX8MP /* 8MP ROM already set NOC to 800Mhz, only need to configure NOC_IO clk to 600Mhz */ - /* 8MP ROM already set GIC to 400Mhz, system_pll1_800m with div = 2 */ clock_set_target_val(NOC_IO_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2)); #else clock_set_target_val(NOC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(2)); @@ -456,13 +554,160 @@ int clock_init(void) clock_enable(CCGR_SEC_DEBUG, 1); + enable_display_clk(1); return 0; }; -u32 imx_get_uartclk(void) +void init_clk_fspi(int index) +{ + /* + * set qspi root + * sys pll1 100M + */ + clock_enable(CCGR_QSPI, 0); + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7)); + clock_enable(CCGR_QSPI, 1); +} + +#ifdef CONFIG_DWC_ETH_QOS +int set_clk_eqos(enum enet_freq type) +{ + u32 target; + u32 enet1_ref; + + switch (type) { + case ENET_125MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; + break; + case ENET_50MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; + break; + case ENET_25MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; + break; + default: + return -EINVAL; + } + + /* disable the clock first */ + clock_enable(CCGR_QOS_ETHENET, 0); + clock_enable(CCGR_SDMA2, 0); + + /* set enet axi clock 266Mhz */ + target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_AXI_CLK_ROOT, target); + + target = CLK_ROOT_ON | enet1_ref | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_QOS_CLK_ROOT, target); + + target = CLK_ROOT_ON | + ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target); + + /* enable clock */ + clock_enable(CCGR_QOS_ETHENET, 1); + clock_enable(CCGR_SDMA2, 1); + + return 0; +} + +int imx_eqos_txclk_set_rate(unsigned long rate) +{ + u32 val; + u32 eqos_post_div; + + /* disable the clock first */ + clock_enable(CCGR_QOS_ETHENET, 0); + clock_enable(CCGR_SDMA2, 0); + + switch (rate) { + case 125000000: + eqos_post_div = 1; + break; + case 25000000: + eqos_post_div = 125000000 / 25000000; + break; + case 2500000: + eqos_post_div = 125000000 / 2500000; + break; + default: + return -EINVAL; + } + + clock_get_target_val(ENET_QOS_CLK_ROOT, &val); + val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK); + val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(eqos_post_div - 1); + clock_set_target_val(ENET_QOS_CLK_ROOT, val); + + /* enable clock */ + clock_enable(CCGR_QOS_ETHENET, 1); + clock_enable(CCGR_SDMA2, 1); + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int set_clk_enet(enum enet_freq type) { - return 24000000U; + u32 target; + u32 enet1_ref; + + /* disable the clock first */ + clock_enable(CCGR_ENET1, 0); + clock_enable(CCGR_SIM_ENET, 0); + + switch (type) { + case ENET_125MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; + break; + case ENET_50MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; + break; + case ENET_25MHZ: + enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; + break; + default: + return -EINVAL; + } + + /* set enet axi clock 266Mhz */ + target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_AXI_CLK_ROOT, target); + + target = CLK_ROOT_ON | enet1_ref | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_REF_CLK_ROOT, target); + + target = CLK_ROOT_ON | ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); + clock_set_target_val(ENET_TIMER_CLK_ROOT, target); + +#ifdef CONFIG_FEC_MXC_25M_REF_CLK + target = CLK_ROOT_ON | + ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | + CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); + clock_set_target_val(ENET_PHY_REF_CLK_ROOT, target); +#endif + /* enable clock */ + clock_enable(CCGR_SIM_ENET, 1); + clock_enable(CCGR_ENET1, 1); + + return 0; } +#endif static u32 decode_intpll(enum clk_root_src intpll) { @@ -790,141 +1035,118 @@ u32 mxc_get_clock(enum mxc_clock clk) return 0; } -#ifdef CONFIG_DWC_ETH_QOS -int set_clk_eqos(enum enet_freq type) +u32 imx_get_uartclk(void) { - u32 target; - u32 enet1_ref; - - switch (type) { - case ENET_125MHZ: - enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; - break; - case ENET_50MHZ: - enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; - break; - case ENET_25MHZ: - enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; - break; - default: - return -EINVAL; - } - - /* disable the clock first */ - clock_enable(CCGR_QOS_ETHENET, 0); - clock_enable(CCGR_SDMA2, 0); - - /* set enet axi clock 266Mhz */ - target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); - clock_set_target_val(ENET_AXI_CLK_ROOT, target); - - target = CLK_ROOT_ON | enet1_ref | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); - clock_set_target_val(ENET_QOS_CLK_ROOT, target); - - target = CLK_ROOT_ON | - ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); - clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target); - - /* enable clock */ - clock_enable(CCGR_QOS_ETHENET, 1); - clock_enable(CCGR_SDMA2, 1); - - return 0; + return mxc_get_clock(MXC_UART_CLK); } -int imx_eqos_txclk_set_rate(u32 rate) +u32 imx_get_fecclk(void) { - u32 val; - u32 eqos_post_div; - - /* disable the clock first */ - clock_enable(CCGR_QOS_ETHENET, 0); - clock_enable(CCGR_SDMA2, 0); - - switch (rate) { - case 125000000: - eqos_post_div = 1; - break; - case 25000000: - eqos_post_div = 125000000 / 25000000; - break; - case 2500000: - eqos_post_div = 125000000 / 2500000; - break; - default: - return -EINVAL; - } - - clock_get_target_val(ENET_QOS_CLK_ROOT, &val); - val &= ~(CLK_ROOT_PRE_DIV_MASK | CLK_ROOT_POST_DIV_MASK); - val |= CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(eqos_post_div - 1); - clock_set_target_val(ENET_QOS_CLK_ROOT, val); - - /* enable clock */ - clock_enable(CCGR_QOS_ETHENET, 1); - clock_enable(CCGR_SDMA2, 1); - - return 0; + return get_root_clk(ENET_AXI_CLK_ROOT); } u32 imx_get_eqos_csr_clk(void) { return get_root_clk(ENET_AXI_CLK_ROOT); } -#endif -#ifdef CONFIG_FEC_MXC -int set_clk_enet(enum enet_freq type) +#if defined(CONFIG_IMX8MP) +void init_usb_clk(void) { - u32 target; - u32 enet1_ref; - - switch (type) { - case ENET_125MHZ: - enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK; - break; - case ENET_50MHZ: - enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK; - break; - case ENET_25MHZ: - enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK; - break; - default: - return -EINVAL; - } - - /* disable the clock first */ - clock_enable(CCGR_ENET1, 0); - clock_enable(CCGR_SIM_ENET, 0); + clock_enable(CCGR_USB_MSCALE_PL301, 0); + clock_enable(CCGR_USB_PHY_8MP, 0); - /* set enet axi clock 266Mhz */ - target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); - clock_set_target_val(ENET_AXI_CLK_ROOT, target); + /* HSIOMIX AXI BUS root already been set by ROM */ - target = CLK_ROOT_ON | enet1_ref | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1); - clock_set_target_val(ENET_REF_CLK_ROOT, target); + /* 100MHz */ + clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + /* 100MHz */ + clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); - target = CLK_ROOT_ON | - ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK | - CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4); - clock_set_target_val(ENET_TIMER_CLK_ROOT, target); + clock_enable(CCGR_USB_MSCALE_PL301, 1); + clock_enable(CCGR_USB_PHY_8MP, 1); +} +#else +void enable_usboh3_clk(unsigned char enable) +{ + if (enable) { + clock_enable(CCGR_USB_MSCALE_PL301, 0); + /* 500M */ + clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + /* 100M */ + clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + /* 100M */ + clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(1)); + clock_enable(CCGR_USB_MSCALE_PL301, 1); + } else { + clock_enable(CCGR_USB_MSCALE_PL301, 0); + } +} +#endif - /* enable clock */ - clock_enable(CCGR_SIM_ENET, 1); - clock_enable(CCGR_ENET1, 1); +/* + * Dump some clockes. + */ +#ifndef CONFIG_SPL_BUILD +int do_mscale_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + u32 freq; + + freq = decode_intpll(ARM_PLL_CLK); + printf("ARM_PLL %8d MHz\n", freq / 1000000); + freq = decode_fracpll(DRAM_PLL1_CLK); + printf("DRAM_PLL %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_800M_CLK); + printf("SYS_PLL1_800 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_400M_CLK); + printf("SYS_PLL1_400 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_266M_CLK); + printf("SYS_PLL1_266 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_160M_CLK); + printf("SYS_PLL1_160 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_133M_CLK); + printf("SYS_PLL1_133 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_100M_CLK); + printf("SYS_PLL1_100 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_80M_CLK); + printf("SYS_PLL1_80 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL1_40M_CLK); + printf("SYS_PLL1_40 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_1000M_CLK); + printf("SYS_PLL2_1000 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_500M_CLK); + printf("SYS_PLL2_500 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_333M_CLK); + printf("SYS_PLL2_333 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_250M_CLK); + printf("SYS_PLL2_250 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_200M_CLK); + printf("SYS_PLL2_200 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_166M_CLK); + printf("SYS_PLL2_166 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_125M_CLK); + printf("SYS_PLL2_125 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_100M_CLK); + printf("SYS_PLL2_100 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL2_50M_CLK); + printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000); + freq = decode_intpll(SYSTEM_PLL3_CLK); + printf("SYS_PLL3 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_UART_CLK); + printf("UART1 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_ESDHC_CLK); + printf("USDHC1 %8d MHz\n", freq / 1000000); + freq = mxc_get_clock(MXC_QSPI_CLK); + printf("QSPI %8d MHz\n", freq / 1000000); return 0; } + +U_BOOT_CMD( + clocks, CONFIG_SYS_MAXARGS, 1, do_mscale_showclocks, + "display clocks", + "" +); #endif diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index 759ec6d114e..43c4e89aaa2 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -310,6 +310,13 @@ static u32 get_root_clk(enum clk_root_index clock_id) return root_src_clk / (post_podf + 1) / (pre_podf + 1); } +#ifdef CONFIG_IMX_HAB +void hab_caam_clock_enable(unsigned char enable) +{ + /* The CAAM clock is always on for iMX8M */ +} +#endif + #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable) { @@ -352,18 +359,29 @@ unsigned int mxc_get_clock(enum mxc_clock clk) clock_get_target_val(IPG_CLK_ROOT, &val); val = val & 0x3; return get_root_clk(AHB_CLK_ROOT) / (val + 1); + case MXC_CSPI_CLK: + return get_root_clk(ECSPI1_CLK_ROOT); case MXC_ESDHC_CLK: return get_root_clk(USDHC1_CLK_ROOT); case MXC_ESDHC2_CLK: return get_root_clk(USDHC2_CLK_ROOT); + case MXC_I2C_CLK: + return get_root_clk(I2C1_CLK_ROOT); + case MXC_UART_CLK: + return get_root_clk(UART1_CLK_ROOT); + case MXC_QSPI_CLK: + return get_root_clk(QSPI_CLK_ROOT); default: - return get_root_clk(clk); + printf("Unsupported mxc_clock %d\n", clk); + break; } + + return 0; } u32 imx_get_uartclk(void) { - return mxc_get_clock(UART1_CLK_ROOT); + return mxc_get_clock(MXC_UART_CLK); } void mxs_set_lcdclk(u32 base_addr, u32 freq) @@ -393,6 +411,28 @@ void init_wdog_clk(void) clock_enable(CCGR_WDOG3, 1); } +void init_usb_clk(void) +{ + if (!is_usb_boot()) { + clock_enable(CCGR_USB_CTRL1, 0); + clock_enable(CCGR_USB_CTRL2, 0); + clock_enable(CCGR_USB_PHY1, 0); + clock_enable(CCGR_USB_PHY2, 0); + /* 500MHz */ + clock_set_target_val(USB_BUS_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + /* 100MHz */ + clock_set_target_val(USB_CORE_REF_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + /* 100MHz */ + clock_set_target_val(USB_PHY_REF_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(1)); + clock_enable(CCGR_USB_CTRL1, 1); + clock_enable(CCGR_USB_CTRL2, 1); + clock_enable(CCGR_USB_PHY1, 1); + clock_enable(CCGR_USB_PHY2, 1); + } +} void init_nand_clk(void) { @@ -697,6 +737,77 @@ static int frac_pll_init(u32 pll, enum frac_pll_out_val val) return 0; } +int sscg_pll_init(u32 pll) +{ + void __iomem *pll_cfg0, __iomem *pll_cfg1, __iomem *pll_cfg2; + u32 val_cfg0, val_cfg1, val_cfg2, val; + u32 bypass1_mask = 0x20, bypass2_mask = 0x10; + int ret; + + switch (pll) { + case ANATOP_SYSTEM_PLL1: + pll_cfg0 = &ana_pll->sys_pll1_cfg0; + pll_cfg1 = &ana_pll->sys_pll1_cfg1; + pll_cfg2 = &ana_pll->sys_pll1_cfg2; + /* 800MHz */ + val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | + SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); + val_cfg1 = 0; + val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | + SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | + SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | + SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | + SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | + SSCG_PLL_REFCLK_SEL_OSC_25M; + break; + case ANATOP_SYSTEM_PLL2: + pll_cfg0 = &ana_pll->sys_pll2_cfg0; + pll_cfg1 = &ana_pll->sys_pll2_cfg1; + pll_cfg2 = &ana_pll->sys_pll2_cfg2; + /* 1000MHz */ + val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | + SSCG_PLL_FEEDBACK_DIV_F2_VAL(4); + val_cfg1 = 0; + val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | + SSCG_PLL_DIV3_CLKE_MASK | SSCG_PLL_DIV4_CLKE_MASK | + SSCG_PLL_DIV5_CLKE_MASK | SSCG_PLL_DIV6_CLKE_MASK | + SSCG_PLL_DIV8_CLKE_MASK | SSCG_PLL_DIV10_CLKE_MASK | + SSCG_PLL_DIV20_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | + SSCG_PLL_REFCLK_SEL_OSC_25M; + break; + case ANATOP_SYSTEM_PLL3: + pll_cfg0 = &ana_pll->sys_pll3_cfg0; + pll_cfg1 = &ana_pll->sys_pll3_cfg1; + pll_cfg2 = &ana_pll->sys_pll3_cfg2; + /* 800MHz */ + val_cfg2 = SSCG_PLL_FEEDBACK_DIV_F1_VAL(3) | + SSCG_PLL_FEEDBACK_DIV_F2_VAL(3); + val_cfg1 = 0; + val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | + SSCG_PLL_REFCLK_SEL_OSC_25M; + break; + default: + return -EINVAL; + } + + /*bypass*/ + setbits_le32(pll_cfg0, bypass1_mask | bypass2_mask); + /* set value */ + writel(val_cfg2, pll_cfg2); + writel(val_cfg1, pll_cfg1); + /*unbypass1 and wait 70us */ + writel(val_cfg0 | bypass2_mask, pll_cfg1); + + __udelay(70); + + /* unbypass2 and wait lock */ + writel(val_cfg0, pll_cfg1); + ret = readl_poll_timeout(pll_cfg0, val, val & SSCG_PLL_LOCK_MASK, 1); + if (ret) + printf("%s timeout\n", __func__); + + return ret; +} int clock_init(void) { @@ -753,6 +864,20 @@ int clock_init(void) } #endif +int imx8m_dcss_clock_init(u32 pixclk) +{ + /* b_clk: bus_clk_root(4) sel 2nd input source and + pre_div to 0; output should be 800M */ + clock_set_target_val(DISPLAY_AXI_CLK_ROOT, CLK_ROOT_ON |CLK_ROOT_SOURCE_SEL(2)); + + /* rtr_clk: bus_clk_root(6) sel 1st input source + and pre_div to 1; output should be 400M */ + clock_set_target_val(DISPLAY_RTRM_CLK_ROOT, + CLK_ROOT_ON |CLK_ROOT_SOURCE_SEL(1) |CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV2)); + + return 0; +} + /* * Dump some clockes. */ @@ -804,11 +929,11 @@ static int do_imx8m_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, printf("SYS_PLL2_50 %8d MHz\n", freq / 1000000); freq = decode_sscg_pll(SYSTEM_PLL3_CLK); printf("SYS_PLL3 %8d MHz\n", freq / 1000000); - freq = mxc_get_clock(UART1_CLK_ROOT); + freq = mxc_get_clock(MXC_UART_CLK); printf("UART1 %8d MHz\n", freq / 1000000); - freq = mxc_get_clock(USDHC1_CLK_ROOT); + freq = mxc_get_clock(MXC_ESDHC_CLK); printf("USDHC1 %8d MHz\n", freq / 1000000); - freq = mxc_get_clock(QSPI_CLK_ROOT); + freq = mxc_get_clock(MXC_QSPI_CLK); printf("QSPI %8d MHz\n", freq / 1000000); return 0; } diff --git a/arch/arm/mach-imx/imx8m/imximage-8mm-ddr3l.cfg b/arch/arm/mach-imx/imx8m/imximage-8mm-ddr3l.cfg new file mode 100644 index 00000000000..022b565fd97 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage-8mm-ddr3l.cfg @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +FIT +BOOT_FROM sd +LOADER spl/u-boot-spl-ddr.bin 0x7E1000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW ddr3_imem_1d.bin +DDR_FW ddr3_dmem_1d.bin diff --git a/arch/arm/mach-imx/imx8m/imximage-8mm-ddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mm-ddr4.cfg new file mode 100644 index 00000000000..d4587c1bfb1 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage-8mm-ddr4.cfg @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +FIT +BOOT_FROM sd +LOADER spl/u-boot-spl-ddr.bin 0x7E1000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW ddr4_imem_1d.bin +DDR_FW ddr4_dmem_1d.bin +DDR_FW ddr4_imem_2d.bin +DDR_FW ddr4_dmem_2d.bin diff --git a/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4-fspi.cfg b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4-fspi.cfg new file mode 100644 index 00000000000..1644ffb0eef --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4-fspi.cfg @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +FIT +BOOT_FROM fspi +LOADER spl/u-boot-spl-ddr.bin 0x7E2000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW lpddr4_pmu_train_1d_imem.bin +DDR_FW lpddr4_pmu_train_1d_dmem.bin +DDR_FW lpddr4_pmu_train_2d_imem.bin +DDR_FW lpddr4_pmu_train_2d_dmem.bin diff --git a/arch/arm/mach-imx/imx8m/imximage-8mn-ddr3l.cfg b/arch/arm/mach-imx/imx8m/imximage-8mn-ddr3l.cfg new file mode 100644 index 00000000000..ab43bf5b011 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage-8mn-ddr3l.cfg @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +FIT +BOOT_FROM sd +LOADER spl/u-boot-spl-ddr.bin 0x912000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW ddr3_imem_1d.bin +DDR_FW ddr3_dmem_1d.bin diff --git a/arch/arm/mach-imx/imx8m/imximage-8mp-ddr4.cfg b/arch/arm/mach-imx/imx8m/imximage-8mp-ddr4.cfg new file mode 100644 index 00000000000..74bb66831e4 --- /dev/null +++ b/arch/arm/mach-imx/imx8m/imximage-8mp-ddr4.cfg @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +FIT +ROM_VERSION v2 +BOOT_FROM sd +LOADER spl/u-boot-spl-ddr.bin 0x920000 +SECOND_LOADER u-boot.itb 0x40200000 0x60000 + +DDR_FW ddr4_imem_1d.bin +DDR_FW ddr4_dmem_1d.bin +DDR_FW ddr4_imem_2d.bin +DDR_FW ddr4_dmem_2d.bin diff --git a/arch/arm/mach-imx/imx8m/imximage.cfg b/arch/arm/mach-imx/imx8m/imximage.cfg index 714b24273bf..60c38abce4f 100644 --- a/arch/arm/mach-imx/imx8m/imximage.cfg +++ b/arch/arm/mach-imx/imx8m/imximage.cfg @@ -7,7 +7,9 @@ FIT BOOT_FROM sd +#ifdef CONFIG_IMX8MQ SIGNED_HDMI signed_hdmi_imx8m.bin +#endif LOADER spl/u-boot-spl-ddr.bin 0x7E1000 SECOND_LOADER u-boot.itb 0x40200000 0x60000 diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5f37282ff10..9d58a9a7501 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -16,10 +16,14 @@ #include #include #include +#include #include #include #include #include +#include +#include +#include #include #include #include @@ -29,10 +33,12 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_IMX_HAB) +#if defined(CONFIG_IMX_HAB) || defined(CONFIG_AVB_ATX) || defined(CONFIG_IMX_TRUSTY_OS) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 1, .word = 3, @@ -133,7 +139,11 @@ static struct mm_region imx8m_mem_map[] = { .phys = 0x40000000UL, .size = PHYS_SDRAM_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#ifdef CONFIG_IMX_TRUSTY_OS + PTE_BLOCK_INNER_SHARE +#else PTE_BLOCK_OUTER_SHARE +#endif #ifdef PHYS_SDRAM_2_SIZE }, { /* DRAM2 */ @@ -141,7 +151,11 @@ static struct mm_region imx8m_mem_map[] = { .phys = 0x100000000UL, .size = PHYS_SDRAM_2_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | +#ifdef CONFIG_IMX_TRUSTY_OS + PTE_BLOCK_INNER_SHARE +#else PTE_BLOCK_OUTER_SHARE +#endif #endif }, { /* empty entrie to split table entry 5 if needed when TEEs are used */ @@ -233,8 +247,7 @@ int dram_init(void) return 0; } - -int dram_init_banksize(void) +__weak int dram_init_banksize(void) { int bank = 0; int ret; @@ -324,18 +337,30 @@ static u32 get_cpu_variant_type(u32 type) } else if (type == MXC_CPU_IMX8MN) { switch (value & 0x3) { case 2: - if (value & 0x1000000) - return MXC_CPU_IMX8MNDL; - else + if (value & 0x1000000) { + if (value & 0x10000000) /* MIPI DSI */ + return MXC_CPU_IMX8MNUD; + else + return MXC_CPU_IMX8MNDL; + } else { return MXC_CPU_IMX8MND; + } case 3: - if (value & 0x1000000) - return MXC_CPU_IMX8MNSL; - else + if (value & 0x1000000) { + if (value & 0x10000000) /* MIPI DSI */ + return MXC_CPU_IMX8MNUS; + else + return MXC_CPU_IMX8MNSL; + } else { return MXC_CPU_IMX8MNS; + } default: - if (value & 0x1000000) - return MXC_CPU_IMX8MNL; + if (value & 0x1000000) { + if (value & 0x10000000) /* MIPI DSI */ + return MXC_CPU_IMX8MNUQ; + else + return MXC_CPU_IMX8MNL; + } break; } } else if (type == MXC_CPU_IMX8MP) { @@ -398,7 +423,16 @@ u32 get_cpu_rev(void) * 0xff0055aa is magic number for B1. */ if (readl((void __iomem *)(OCOTP_BASE_ADDR + 0x40)) == 0xff0055aa) { - reg = CHIP_REV_2_1; + /* + * B2 uses same DIGPROG and OCOTP_READ_FUSE_DATA value with B1, + * so have to check ROM to distinguish them + */ + rom_version = readl((void __iomem *)ROM_VERSION_B0); + rom_version &= 0xff; + if (rom_version == CHIP_REV_2_2) + reg = CHIP_REV_2_2; + else + reg = CHIP_REV_2_1; } else { rom_version = readl((void __iomem *)ROM_VERSION_A0); @@ -447,6 +481,53 @@ int arch_cpu_init_dm(void) return 0; } +#if defined(CONFIG_IMX_HAB) && defined(CONFIG_IMX8MQ) +static bool is_hdmi_fused(void) { + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + + u32 value = readl(&fuse->tester4); + + if (is_imx8mq()) { + if (value & 0x02000000) + return true; + } + + return false; +} + +bool is_uid_matched(u64 uid) { + struct tag_serialnr nr; + get_board_serial(&nr); + + if (lower_32_bits(uid) == nr.low && + upper_32_bits(uid) == nr.high) + return true; + + return false; +} + +static void secure_lockup(void) +{ + if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1) && + imx_hab_is_enabled() && !is_hdmi_fused()) { +#ifdef CONFIG_SECURE_STICKY_BITS_LOCKUP + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + + clock_enable(CCGR_OCOTP, 1); + setbits_le32(&ocotp->sw_sticky, 0x6); /* Lock up field return and SRK revoke */ + writel(0x80000000, &ocotp->scs_set); /* Lock up SCS */ +#else + /* Check the Unique ID, if it is matched with UID config, then allow to leave sticky bits unlocked */ + if (!is_uid_matched(CONFIG_IMX_UNIQUE_ID)) + hang(); +#endif + } +} +#endif + int arch_cpu_init(void) { struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; @@ -466,9 +547,12 @@ int arch_cpu_init(void) clock_init(); imx_set_wdog_powerdown(false); +#if defined(CONFIG_IMX_HAB) && defined(CONFIG_IMX8MQ) + secure_lockup(); +#endif if (is_imx8md() || is_imx8mmd() || is_imx8mmdl() || is_imx8mms() || is_imx8mmsl() || is_imx8mnd() || is_imx8mndl() || is_imx8mns() || - is_imx8mnsl() || is_imx8mpd()) { + is_imx8mnsl() || is_imx8mpd() || is_imx8mnud() || is_imx8mnus()) { /* Power down cpu core 1, 2 and 3 for iMX8M Dual core or Single core */ struct pgc_reg *pgc_core1 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x840); struct pgc_reg *pgc_core2 = (struct pgc_reg *)(GPC_BASE_ADDR + 0x880); @@ -477,7 +561,7 @@ int arch_cpu_init(void) writel(0x1, &pgc_core2->pgcr); writel(0x1, &pgc_core3->pgcr); - if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl()) { + if (is_imx8mms() || is_imx8mmsl() || is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) { writel(0x1, &pgc_core1->pgcr); writel(0xE, &gpc->cpu_pgc_dn_trg); } else { @@ -486,6 +570,11 @@ int arch_cpu_init(void) } } +#if defined(CONFIG_ANDROID_SUPPORT) + /* Enable RTC */ + writel(0x21, 0x30370038); +#endif + if (is_imx8mq()) { clock_enable(CCGR_OCOTP, 1); if (readl(&ocotp->ctrl) & 0x200) @@ -547,6 +636,18 @@ bool is_usb_boot(void) { return get_boot_device() == USB_BOOT; } +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + serialnr->low = fuse->uid_low; + serialnr->high = fuse->uid_high; +} +#endif #ifdef CONFIG_OF_SYSTEM_SETUP bool check_fdt_new_path(void *blob) @@ -616,7 +717,8 @@ static int disable_mipi_dsi_nodes(void *blob) "/mipi_dsi_bridge@30A00000", "/dsi_phy@30A00300", "/soc@0/bus@30800000/mipi_dsi@30a00000", - "/soc@0/bus@30800000/dphy@30a00300" + "/soc@0/bus@30800000/dphy@30a00300", + "/soc@0/bus@30800000/mipi-dsi@30a00000", }; return disable_fdt_nodes(blob, nodes_path, ARRAY_SIZE(nodes_path)); @@ -644,7 +746,8 @@ static int check_mipi_dsi_nodes(void *blob) { static const char * const lcdif_path[] = { "/lcdif@30320000", - "/soc@0/bus@30000000/lcdif@30320000" + "/soc@0/bus@30000000/lcdif@30320000", + "/soc@0/bus@30000000/lcd-controller@30320000" }; static const char * const mipi_dsi_path[] = { "/mipi_dsi@30A00000", @@ -652,11 +755,13 @@ static int check_mipi_dsi_nodes(void *blob) }; static const char * const lcdif_ep_path[] = { "/lcdif@30320000/port@0/mipi-dsi-endpoint", - "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint" + "/soc@0/bus@30000000/lcdif@30320000/port@0/endpoint", + "/soc@0/bus@30000000/lcd-controller@30320000/port@0/endpoint" }; static const char * const mipi_dsi_ep_path[] = { "/mipi_dsi@30A00000/port@1/endpoint", - "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint" + "/soc@0/bus@30800000/mipi_dsi@30a00000/ports/port@0/endpoint", + "/soc@0/bus@30800000/mipi-dsi@30a00000/ports/port@0/endpoint@0" }; int lookup_node; @@ -697,6 +802,14 @@ static int check_mipi_dsi_nodes(void *blob) } #endif +void board_quiesce_devices(void) +{ +#ifdef CONFIG_USB_DWC3 + if (is_usb_boot()) + disconnect_from_pc(); +#endif +} + int disable_vpu_nodes(void *blob) { static const char * const nodes_path_8mq[] = { @@ -707,13 +820,19 @@ int disable_vpu_nodes(void *blob) static const char * const nodes_path_8mm[] = { "/vpu_g1@38300000", "/vpu_g2@38310000", - "/vpu_h1@38320000" + "/vpu_h1@38320000", + "/soc@0/blk-ctrl@38330000" }; static const char * const nodes_path_8mp[] = { "/vpu_g1@38300000", "/vpu_g2@38310000", - "/vpu_vc8000e@38320000" + "/vpu_vc8000e@38320000", + "/soc@0/blk-ctl@38330000", + "/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@19", + "/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@20", + "/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@21", + "/soc@0/bus@30000000/gpc@303a0000/pgc/power-domain@22" }; if (is_imx8mq()) @@ -726,10 +845,50 @@ int disable_vpu_nodes(void *blob) return -EPERM; } +#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +static int low_drive_gpu_freq(void *blob) +{ + const char *nodes_path_8mn[] = { + "/gpu@38000000", + "/soc@0/gpu@38000000" + }; + + int nodeoff, cnt, i, j; + u32 assignedclks[7]; + + for (i = 0; i < ARRAY_SIZE(nodes_path_8mn); i++) { + nodeoff = fdt_path_offset(blob, nodes_path_8mn[i]); + if (nodeoff < 0) + continue; + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "assigned-clock-rates", assignedclks, 7); + if (cnt < 0) + return cnt; + + if (cnt != 7) + printf("Warning: %s, assigned-clock-rates count %d\n", nodes_path_8mn[i], cnt); + + assignedclks[cnt - 1] = 200000000; + assignedclks[cnt - 2] = 200000000; + + for (j = 0; j < cnt; j++) { + debug("<%u>, ", assignedclks[j]); + assignedclks[j] = cpu_to_fdt32(assignedclks[j]); + } + debug("\n"); + + return fdt_setprop(blob, nodeoff, "assigned-clock-rates", &assignedclks, sizeof(assignedclks)); + } + + return -ENOENT; +} +#endif + int disable_gpu_nodes(void *blob) { static const char * const nodes_path_8mn[] = { - "/gpu@38000000" + "/gpu@38000000", + "/soc@/gpu@38000000" }; return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn)); @@ -763,6 +922,76 @@ int disable_dsp_nodes(void *blob) return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp)); } +static void disable_thermal_cpu_nodes(void *blob, u32 disabled_cores) +{ + const char *thermal_path[] = { + "/thermal-zones/cpu-thermal/cooling-maps/map0" + }; + + int nodeoff, cnt, i, ret, j; + u32 cooling_dev[12]; + + for (i = 0; i < ARRAY_SIZE(thermal_path); i++) { + nodeoff = fdt_path_offset(blob, thermal_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "cooling-device", cooling_dev, 12); + if (cnt < 0) + continue; + + if (cnt != 12) + printf("Warning: %s, cooling-device count %d\n", thermal_path[i], cnt); + + for (j = 0; j < cnt; j++) { + cooling_dev[j] = cpu_to_fdt32(cooling_dev[j]); + } + + ret= fdt_setprop(blob, nodeoff, "cooling-device", &cooling_dev, sizeof(u32) * (12 - disabled_cores * 3)); + if (ret < 0) { + printf("Warning: %s, cooling-device setprop failed %d\n", thermal_path[i], ret); + continue; + } + + printf("Update node %s, cooling-device prop\n", thermal_path[i]); + } +} + +static void disable_pmu_cpu_nodes(void *blob, u32 disabled_cores) +{ + const char *pmu_path[] = { + "/pmu" + }; + + int nodeoff, cnt, i, ret, j; + u32 irq_affinity[4]; + + for (i = 0; i < ARRAY_SIZE(pmu_path); i++) { + nodeoff = fdt_path_offset(blob, pmu_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + + cnt = fdtdec_get_int_array_count(blob, nodeoff, "interrupt-affinity", irq_affinity, 4); + if (cnt < 0) + continue; + + if (cnt != 4) + printf("Warning: %s, interrupt-affinity count %d\n", pmu_path[i], cnt); + + for (j = 0; j < cnt; j++) { + irq_affinity[j] = cpu_to_fdt32(irq_affinity[j]); + } + + ret= fdt_setprop(blob, nodeoff, "interrupt-affinity", &irq_affinity, sizeof(u32) * (4 - disabled_cores)); + if (ret < 0) { + printf("Warning: %s, interrupt-affinity setprop failed %d\n", pmu_path[i], ret); + continue; + } + + printf("Update node %s, interrupt-affinity prop\n", pmu_path[i]); + } +} + static int disable_cpu_nodes(void *blob, u32 disabled_cores) { static const char * const nodes_path[] = { @@ -795,9 +1024,43 @@ static int disable_cpu_nodes(void *blob, u32 disabled_cores) } } + disable_thermal_cpu_nodes(blob, disabled_cores); + disable_pmu_cpu_nodes(blob, disabled_cores); + return 0; } +#if defined(CONFIG_IMX8MM) +static int cleanup_nodes_for_efi(void *blob) +{ + static const char * const usbotg_path[] = { + "/soc@0/bus@32c00000/usb@32e40000", + "/soc@0/bus@32c00000/usb@32e50000" + }; + int nodeoff, i, rc; + + for (i = 0; i < ARRAY_SIZE(usbotg_path); i++) { + nodeoff = fdt_path_offset(blob, usbotg_path[i]); + if (nodeoff < 0) + continue; /* Not found, skip it */ + debug("Found %s node\n", usbotg_path[i]); + + rc = fdt_delprop(blob, nodeoff, "extcon"); + if (rc == -FDT_ERR_NOTFOUND) + continue; + if (rc) { + printf("Unable to update property %s:%s, err=%s\n", + usbotg_path[i], "extcon", fdt_strerror(rc)); + return rc; + } + + printf("Remove %s:%s\n", usbotg_path[i], "extcon"); + } + + return 0; +} +#endif + int ft_system_setup(void *blob, struct bd_info *bd) { #ifdef CONFIG_IMX8MQ @@ -892,13 +1155,24 @@ int ft_system_setup(void *blob, struct bd_info *bd) else if (is_imx8mms() || is_imx8mmsl()) disable_cpu_nodes(blob, 3); + cleanup_nodes_for_efi(blob); + #elif defined(CONFIG_IMX8MN) if (is_imx8mnl() || is_imx8mndl() || is_imx8mnsl()) disable_gpu_nodes(blob); +#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE + else { + int ldm_gpu = low_drive_gpu_freq(blob); + if (ldm_gpu < 0) + printf("Update GPU node assigned-clock-rates failed\n"); + else + printf("Update GPU node assigned-clock-rates ok\n"); + } +#endif - if (is_imx8mnd() || is_imx8mndl()) + if (is_imx8mnd() || is_imx8mndl() || is_imx8mnud()) disable_cpu_nodes(blob, 2); - else if (is_imx8mns() || is_imx8mnsl()) + else if (is_imx8mns() || is_imx8mnsl() || is_imx8mnus()) disable_cpu_nodes(blob, 3); #elif defined(CONFIG_IMX8MP) @@ -918,7 +1192,11 @@ int ft_system_setup(void *blob, struct bd_info *bd) disable_cpu_nodes(blob, 2); #endif +#if defined(CONFIG_ANDROID_SUPPORT) || defined(CONFIG_ANDROID_AUTO_SUPPORT) return 0; +#else + return ft_add_optee_node(blob, bd); +#endif } #endif @@ -958,12 +1236,76 @@ static void acquire_buildinfo(void) int arch_misc_init(void) { + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + acquire_buildinfo(); return 0; } #endif +#ifdef CONFIG_SPL_BUILD +static uint32_t gpc_pu_m_core_offset[11] = { + 0xc00, 0xc40, 0xc80, 0xcc0, + 0xdc0, 0xe00, 0xe40, 0xe80, + 0xec0, 0xf00, 0xf40, +}; + +#define PGC_PCR 0 + +void imx_gpc_set_m_core_pgc(unsigned int offset, bool pdn) +{ + uint32_t val; + uintptr_t reg = GPC_BASE_ADDR + offset; + + val = readl(reg); + val &= ~(0x1 << PGC_PCR); + + if(pdn) + val |= 0x1 << PGC_PCR; + writel(val, reg); +} + +void imx8m_usb_power_domain(uint32_t domain_id, bool on) +{ + uint32_t val; + uintptr_t reg; + + imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true); + + reg = GPC_BASE_ADDR + (on ? 0xf8 : 0x104); + val = 1 << (domain_id > 3 ? (domain_id + 3) : domain_id); + writel(val, reg); + while (readl(reg) & val) + ; + imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], false); +} +#endif + +int imx8m_usb_power(int usb_id, bool on) +{ + if (usb_id > 1) + return -EINVAL; + +#ifdef CONFIG_SPL_BUILD + imx8m_usb_power_domain(2 + usb_id, on); +#else + struct arm_smccc_res res; + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + 2 + usb_id, on, 0, 0, 0, 0, &res); + if (res.a0) + return -EPERM; +#endif + + return 0; +} + void imx_tmu_arch_init(void *reg_base) { if (is_imx8mm() || is_imx8mn()) { @@ -1129,3 +1471,16 @@ long long env_get_offset(long long defautl_offset) } #endif #endif + +#ifdef CONFIG_IMX8MQ +int imx8m_dcss_power_init(void) +{ + /* Enable the display CCGR before power on */ + clock_enable(CCGR_DISPLAY, 1); + + writel(0x0000ffff, 0x303A00EC); /*PGC_CPU_MAPPING */ + setbits_le32(0x303A00F8, 0x1 << 10); /*PU_PGC_SW_PUP_REQ : disp was 10 */ + + return 0; +} +#endif diff --git a/arch/arm/mach-imx/imx_bootaux.c b/arch/arm/mach-imx/imx_bootaux.c index e1fc4b3e19a..21a4629dce6 100644 --- a/arch/arm/mach-imx/imx_bootaux.c +++ b/arch/arm/mach-imx/imx_bootaux.c @@ -14,9 +14,10 @@ #include #include +#ifndef CONFIG_IMX8 int arch_auxiliary_core_up(u32 core_id, ulong addr) { - ulong stack, pc; + u32 stack, pc; if (!addr) return -EINVAL; @@ -45,18 +46,18 @@ int arch_auxiliary_core_up(u32 core_id, ulong addr) pc = *(u32 *)(addr + 4); } #endif - printf("## Starting auxiliary core stack = 0x%08lX, pc = 0x%08lX...\n", + printf("## Starting auxiliary core stack = 0x%08X, pc = 0x%08X...\n", stack, pc); - /* Set the stack and pc to M4 bootROM */ - writel(stack, M4_BOOTROM_BASE_ADDR); - writel(pc, M4_BOOTROM_BASE_ADDR + 4); + /* Set the stack and pc to MCU bootROM */ + writel(stack, MCU_BOOTROM_BASE_ADDR); + writel(pc, MCU_BOOTROM_BASE_ADDR + 4); flush_dcache_all(); - /* Enable M4 */ + /* Enable MCU */ #ifdef CONFIG_IMX8M - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_START, 0, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_START, 0, 0, 0, 0, 0, 0, NULL); #else clrsetbits_le32(SRC_BASE_ADDR + SRC_M4_REG_OFFSET, @@ -71,7 +72,7 @@ int arch_auxiliary_core_check_up(u32 core_id) #ifdef CONFIG_IMX8M struct arm_smccc_res res; - arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_M4_STARTED, 0, 0, + arm_smccc_smc(IMX_SIP_SRC, IMX_SIP_SRC_MCU_STARTED, 0, 0, 0, 0, 0, 0, &res); return res.a0; @@ -86,30 +87,34 @@ int arch_auxiliary_core_check_up(u32 core_id) return 1; #endif } - +#endif /* * To i.MX6SX and i.MX7D, the image supported by bootaux needs * the reset vector at the head for the image, with SP and PC * as the first two words. * - * Per the cortex-M reference manual, the reset vector of M4 needs - * to exist at 0x0 (TCMUL). The PC and SP are the first two addresses - * of that vector. So to boot M4, the A core must build the M4's reset + * Per the cortex-M reference manual, the reset vector of M4/M7 needs + * to exist at 0x0 (TCMUL/IDTCM). The PC and SP are the first two addresses + * of that vector. So to boot M4/M7, the A core must build the M4/M7's reset * vector with getting the PC and SP from image and filling them to - * TCMUL. When M4 is kicked, it will load the PC and SP by itself. - * The TCMUL is mapped to (M4_BOOTROM_BASE_ADDR) at A core side for - * accessing the M4 TCMUL. + * TCMUL/IDTCM. When M4/M7 is kicked, it will load the PC and SP by itself. + * The TCMUL/IDTCM is mapped to (MCU_BOOTROM_BASE_ADDR) at A core side for + * accessing the M4/M7 TCMUL/IDTCM. */ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { ulong addr; int ret, up; + u32 core = 0; if (argc < 2) return CMD_RET_USAGE; - up = arch_auxiliary_core_check_up(0); + if (argc > 2) + core = simple_strtoul(argv[2], NULL, 10); + + up = arch_auxiliary_core_check_up(core); if (up) { printf("## Auxiliary core is already up\n"); return CMD_RET_SUCCESS; @@ -120,7 +125,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, if (!addr) return CMD_RET_FAILURE; - ret = arch_auxiliary_core_up(0, addr); + ret = arch_auxiliary_core_up(core, addr); if (ret) return CMD_RET_FAILURE; @@ -130,5 +135,7 @@ static int do_bootaux(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD( bootaux, CONFIG_SYS_MAXARGS, 1, do_bootaux, "Start auxiliary core", - "" + "
[]\n" + " - start auxiliary core [] (default 0),\n" + " at address
\n" ); diff --git a/arch/arm/mach-imx/imx_vservice.c b/arch/arm/mach-imx/imx_vservice.c new file mode 100644 index 00000000000..1669e24819a --- /dev/null +++ b/arch/arm/mach-imx/imx_vservice.c @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static LIST_HEAD(vservice_channels); + +void * __weak board_imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size) +{ + if (size <= CONFIG_IMX_VSERVICE_SHARED_BUFFER_SIZE) + return (void * )CONFIG_IMX_VSERVICE_SHARED_BUFFER; + + return NULL; +} + +void * imx_vservice_get_buffer(struct imx_vservice_channel *node, u32 size) +{ + return board_imx_vservice_get_buffer(node, size); +} + +int imx_vservice_blocking_request(struct imx_vservice_channel *node, u8 *buf, u32* size) +{ + int ret = 0; + union imx_m4_msg msg; + + msg.format.seq = node->msg_seq; + msg.format.type = MU_MSG_REQ; + msg.format.buffer = (u32)(ulong)buf; + msg.format.size = *size; + + ret = misc_call(node->mu_dev, 1000000, &msg, 4, &msg, 4); + if (ret) { + printf("%s: Send request MU message failed, ret %d\n", __func__, ret); + goto MU_ERR; + } + + if (msg.format.type != MU_MSG_RESP|| msg.format.seq != node->msg_seq) { + printf("%s: wrong msg response: type %d, seq %d, expect seq %d\n", + __func__, msg.format.type, msg.format.seq, node->msg_seq); + ret = -EIO; + goto MU_ERR; + } + + *size = msg.format.size; + +MU_ERR: + node->msg_seq++; + + return ret; +} + +static int imx_vservice_connect(struct imx_vservice_channel *node) +{ + int ret = 0; + union imx_m4_msg msg; + + unsigned long timeout = timer_get_us() + 2000000; /* 2s timeout */ + + for (;;) { + msg.format.seq = 0; + msg.format.type = MU_MSG_READY_A; + msg.format.buffer = 0; + msg.format.size = 0; + + ret = misc_call(node->mu_dev, 100000, &msg, 4, &msg, 4); + if (!ret && msg.format.type == MU_MSG_READY_B) + return 0; + + if (time_after(timer_get_us(), timeout)) { + printf("%s: Timeout to connect peer, %d\n", __func__, ret); + return -ETIMEDOUT; + } + } + + return -EIO; +} + +struct udevice * __weak board_imx_vservice_find_mu(struct udevice *virt_dev) +{ + int ret; + struct ofnode_phandle_args args; + struct udevice *mu_dev; + + /* Default get mu from "fsl,vservice-mu" property*/ + ret = dev_read_phandle_with_args(virt_dev, "fsl,vservice-mu", + NULL, 0, 0, &args); + if (ret) { + printf("Can't find \"fsl,vservice-mu\" property\n"); + return NULL; + } + + ret = uclass_find_device_by_ofnode(UCLASS_MISC, args.node, &mu_dev); + if (ret) { + printf("Can't find MU device, err %d\n", ret); + return NULL; + } + + return mu_dev; +} + +static struct udevice * imx_vservice_find_mu(struct udevice *virt_dev) +{ + return board_imx_vservice_find_mu(virt_dev); +} + +struct imx_vservice_channel * imx_vservice_setup(struct udevice *virt_dev) +{ + int ret; + struct udevice *mu_dev; + struct imx_vservice_channel *channel; + + mu_dev = imx_vservice_find_mu(virt_dev); + if (mu_dev == NULL) { + printf("No MU device for virtual service %s connection\n", virt_dev->name); + return NULL; + } + + ret = device_probe(mu_dev); + if (ret) { + printf("Probe MU device failed\n"); + return NULL; + } + + list_for_each_entry(channel, &vservice_channels, channel_head) { + if (channel->mu_dev == mu_dev) + return channel; + } + + channel = malloc(sizeof(struct imx_vservice_channel)); + if (!channel) { + printf("Malloc vservice channel is failed\n"); + return NULL; + } + + channel->msg_seq = 0; + channel->mu_dev = mu_dev; + INIT_LIST_HEAD(&channel->channel_head); + + ret = imx_vservice_connect(channel); + if (ret) { + printf("VService: Connection is failed, ret %d\n", ret); + free(channel); + return NULL; + } + + list_add_tail(&channel->channel_head, &vservice_channels); + + printf("VService: Connection is ok on MU %s\n", mu_dev->name); + + return channel; +} diff --git a/arch/arm/mach-imx/lowlevel.S b/arch/arm/mach-imx/lowlevel.S index 158fdb7d87b..2cb2d056a95 100644 --- a/arch/arm/mach-imx/lowlevel.S +++ b/arch/arm/mach-imx/lowlevel.S @@ -6,6 +6,16 @@ #include ENTRY(lowlevel_init) +#ifdef CONFIG_SPL_BUILD + mrs x0, CurrentEL + cmp x0, #12 + b.eq 1f + ret +1: + msr daifclr, #4 + isb + ret +#else mrs x0, CurrentEL cmp x0, #8 b.eq 1f @@ -19,4 +29,5 @@ ENTRY(lowlevel_init) msr hcr_el2, x0 isb ret +#endif ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-imx/mac.c b/arch/arm/mach-imx/mac.c index 3b1496b2038..02de001f307 100644 --- a/arch/arm/mach-imx/mac.c +++ b/arch/arm/mach-imx/mac.c @@ -23,7 +23,7 @@ struct imx_mac_fuse { #define MAC_FUSE_MX6_OFFSET 0x620 #define MAC_FUSE_MX7_OFFSET 0x640 -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +__weak void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { struct imx_mac_fuse *fuse; u32 offset; @@ -31,7 +31,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) offset = is_mx6() ? MAC_FUSE_MX6_OFFSET : MAC_FUSE_MX7_OFFSET; fuse = (struct imx_mac_fuse *)(ulong)(OCOTP_BASE_ADDR + offset); - has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull(); + has_second_mac = is_mx7() || is_mx6sx() || is_mx6ul() || is_mx6ull() || is_imx8mp(); if (has_second_mac && dev_id == 1) { u32 value = readl(&fuse->mac_addr2); diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index d82efa7f8f0..9f53cc21684 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013 Stefan Roese + * Copyright 2018 NXP */ #include @@ -12,6 +13,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -107,3 +109,107 @@ void board_lmb_reserve(struct lmb *lmb) break; } } + +void configure_tzc380(void) +{ +#if defined (IP2APB_TZASC1_BASE_ADDR) + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + if (iomux->gpr[9] & 0x1) + writel(0xf0000000, IP2APB_TZASC1_BASE_ADDR + 0x108); +#endif +#if defined (IP2APB_TZASC2_BASE_ADDR) + if (iomux->gpr[9] & 0x2) + writel(0xf0000000, IP2APB_TZASC2_BASE_ADDR + 0x108); +#endif +} + +static void set_dt_val(void *data, uint32_t cell_size, uint64_t val) +{ + if (cell_size == 1) { + fdt32_t v = cpu_to_fdt32((uint32_t)val); + + memcpy(data, &v, sizeof(v)); + } else { + fdt64_t v = cpu_to_fdt64(val); + + memcpy(data, &v, sizeof(v)); + } +} + +int add_dt_path_subnode(void *fdt, const char *path, const char *subnode) +{ + int offs; + + offs = fdt_path_offset(fdt, path); + if (offs < 0) + return -1; + + offs = fdt_add_subnode(fdt, offs, subnode); + if (offs < 0) + return -1; + return offs; +} + +int add_res_mem_dt_node(void *fdt, const char *name, phys_addr_t pa, + size_t size) +{ + int offs = 0; + int ret = 0; + int addr_size = -1; + int len_size = -1; + bool found = true; + char subnode_name[80] = { 0 }; + + offs = fdt_path_offset(fdt, "/reserved-memory"); + + if (offs < 0) { + found = false; + offs = 0; + } + + len_size = fdt_size_cells(fdt, offs); + if (len_size < 0) + return -1; + addr_size = fdt_address_cells(fdt, offs); + if (addr_size < 0) + return -1; + + if (!found) { + offs = add_dt_path_subnode(fdt, "/", "reserved-memory"); + if (offs < 0) + return -1; + + ret = fdt_setprop_cell(fdt, offs, "#address-cells", addr_size); + if (ret < 0) + return -1; + ret = fdt_setprop_cell(fdt, offs, "#size-cells", len_size); + if (ret < 0) + return -1; + ret = fdt_setprop(fdt, offs, "ranges", NULL, 0); + if (ret < 0) + return -1; + } + +#ifdef CONFIG_PHYS_64BIT + snprintf(subnode_name, sizeof(subnode_name), "%s@0x%llx", name, pa); +#else + snprintf(subnode_name, sizeof(subnode_name), "%s@0x%lx", name, pa); +#endif + offs = fdt_add_subnode(fdt, offs, subnode_name); + if (offs >= 0) { + u32 data[FDT_MAX_NCELLS * 2]; + + set_dt_val(data, addr_size, pa); + set_dt_val(data + addr_size, len_size, size); + ret = fdt_setprop(fdt, offs, "reg", data, + sizeof(uint32_t) * (addr_size + len_size)); + if (ret < 0) + return -1; + ret = fdt_setprop(fdt, offs, "no-map", NULL, 0); + if (ret < 0) + return -1; + } else { + return -1; + } + return 0; +} diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index 9c822f721c6..7012ae9d7bd 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -8,10 +8,11 @@ #include #include #include +#include __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return devno; } int mmc_get_env_dev(void) @@ -23,7 +24,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) - return CONFIG_SYS_MMC_ENV_DEV; + return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); return board_mmc_get_env_dev(devno); } diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 92fb4c4f23e..6442fbb4aa8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -33,6 +33,11 @@ config MX6Q select HAS_CAAM select MX6_SMP +config MX6QP + bool "i.MX 6QuadPlus SoC support" + select HAS_CAAM + select MX6_SMP + config MX6QDL bool "i.MX 6Dual and 6Quad SoC support" select HAS_CAAM @@ -107,6 +112,48 @@ config MX6_DDRCAL Say "Y" if your board uses dynamic (per-boot) DDR calibration. If unsure, say N. +config LDO_BYPASS_CHECK + bool "Enable the LDO bypass checking and setting" + default y if !MX6SLL + help + This feature searches the gpc node in loaded DTB and checking the + "fsl,ldo-bypass" property. When the property is set, board relevant + PMIC settings are called to adjust for LDO bypass. + +config CMD_BEE + bool "Enable commands for Bus Encryption Engine(BEE)" + depends on MX6UL + help + Set "Y" to enable the bee commands + +config TARGET_MX6SABREAUTO_COMMON + bool + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select IMX_THERMAL + select BOARD_EARLY_INIT_F + select NXP_BOARD_REVISION + imply CMD_DM + +config TARGET_MX6SABRESD_COMMON + bool + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select IMX_THERMAL + select BOARD_EARLY_INIT_F + select NXP_BOARD_REVISION + imply CMD_DM + +config TARGET_MX6QDLARM2 + bool + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + imply CMD_DM + choice prompt "MX6 board select" optional @@ -304,6 +351,13 @@ config TARGET_MX6MEMCAL config TARGET_MX6QARM2 bool "mx6qarm2" + depends on MX6Q + select TARGET_MX6QDLARM2 + +config TARGET_MX6DLARM2 + bool "mx6dlarm2" + depends on MX6DL + select TARGET_MX6QDLARM2 config TARGET_MX6DL_MAMOJ bool "Support BTicino Mamoj" @@ -376,6 +430,78 @@ config TARGET_MX6SABRESD select SUPPORT_SPL imply CMD_DM +config TARGET_MX6QSABREAUTO + bool "mx6qsabreauto" + select TARGET_MX6SABREAUTO_COMMON + depends on MX6Q + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT + +config TARGET_MX6QPSABREAUTO + bool "mx6qpsabreauto" + select TARGET_MX6SABREAUTO_COMMON + depends on MX6QP + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT + +config TARGET_MX6DLSABREAUTO + bool "mx6dlsabreauto" + select TARGET_MX6SABREAUTO_COMMON + depends on MX6DL + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT + +config TARGET_MX6SOLOSABREAUTO + bool "mx6solosabreauto" + select TARGET_MX6SABREAUTO_COMMON + depends on MX6S + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT + +config TARGET_MX6QSABRESD + bool "mx6qsabresd" + select TARGET_MX6SABRESD_COMMON + depends on MX6Q + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT + +config TARGET_MX6QPSABRESD + bool "mx6qpsabresd" + select TARGET_MX6SABRESD_COMMON + depends on MX6QP + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT + +config TARGET_MX6DLSABRESD + bool "mx6dlsabresd" + select TARGET_MX6SABRESD_COMMON + depends on MX6DL + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT + +config TARGET_MX6SOLOSABRESD + bool "mx6solosabresd" + select TARGET_MX6SABRESD_COMMON + depends on MX6S + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT + config TARGET_MX6SLEVK bool "mx6slevk" depends on MX6SL @@ -389,6 +515,14 @@ config TARGET_MX6SLLEVK select DM_THERMAL imply CMD_DM +config TARGET_MX6SLL_VAL + bool "mx6sll val" + depends on MX6SLL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + imply CMD_DM + config TARGET_MX6SXSABRESD bool "mx6sxsabresd" depends on MX6SX @@ -397,6 +531,10 @@ config TARGET_MX6SXSABRESD select DM select DM_THERMAL select SUPPORT_SPL + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT config TARGET_MX6SXSABREAUTO bool "mx6sxsabreauto" @@ -407,6 +545,33 @@ config TARGET_MX6SXSABREAUTO select DM_THERMAL imply CMD_DM +config TARGET_MX6SX_14X14_VAL + bool "mx6sx_14x14_val" + depends on MX6SX + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply CMD_DM + +config TARGET_MX6SX_17X17_VAL + bool "mx6sx_17x17_val" + depends on MX6SX + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply CMD_DM + +config TARGET_MX6SX_19X19_VAL + bool "mx6sx_19x19_val" + depends on MX6SX + select DM + select DM_THERMAL + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply CMD_DM + config TARGET_MX6UL_9X9_EVK bool "mx6ul_9x9_evk" depends on MX6UL @@ -414,6 +579,8 @@ config TARGET_MX6UL_9X9_EVK select DM select DM_THERMAL select SUPPORT_SPL + select IMX_MODULE_FUSE + select OF_SYSTEM_SETUP imply CMD_DM config TARGET_MX6UL_14X14_EVK @@ -423,6 +590,32 @@ config TARGET_MX6UL_14X14_EVK select DM select DM_THERMAL select SUPPORT_SPL + select IMX_MODULE_FUSE + select OF_SYSTEM_SETUP + imply CMD_DM + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT + +config TARGET_MX6UL_14X14_DDR3_VAL + bool "mx6ul_14x14_ddr3_val" + depends on MX6UL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select IMX_MODULE_FUSE + select OF_SYSTEM_SETUP + imply CMD_DM + +config TARGET_MX6UL_14X14_LPDDR2_VAL + bool "mx6ul_14x14_lpddr2_val" + depends on MX6UL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select IMX_MODULE_FUSE + select OF_SYSTEM_SETUP imply CMD_DM config TARGET_MX6UL_ENGICAM @@ -443,12 +636,34 @@ config TARGET_MX6UL_ENGICAM select SUPPORT_SPL imply CMD_DM +config TARGET_MX6ULL_DDR3_VAL + bool "Support mx6ull_ddr3_val" + depends on MX6ULL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select IMX_MODULE_FUSE + select OF_SYSTEM_SETUP + imply CMD_DM + +config TARGET_MX6ULL_9X9_EVK + bool "Support mx6ull_9x9_evk" + depends on MX6ULL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select IMX_MODULE_FUSE + select OF_SYSTEM_SETUP + imply CMD_DM + config TARGET_MX6ULL_14X14_EVK bool "Support mx6ull_14x14_evk" depends on MX6ULL select BOARD_LATE_INIT select DM select DM_THERMAL + select IMX_MODULE_FUSE + select OF_SYSTEM_SETUP imply CMD_DM config TARGET_MYS_6ULX @@ -716,11 +931,17 @@ source "board/freescale/mx6memcal/Kconfig" source "board/freescale/mx6sabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" source "board/freescale/mx6slevk/Kconfig" +source "board/freescale/mx6sll_val/Kconfig" source "board/freescale/mx6sllevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" +source "board/freescale/mx6sx_17x17_val/Kconfig" +source "board/freescale/mx6sx_19x19_val/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" +source "board/freescale/mx6ul_14x14_ddr3_val/Kconfig" +source "board/freescale/mx6ul_14x14_lpddr2_val/Kconfig" source "board/freescale/mx6ullevk/Kconfig" +source "board/freescale/mx6ull_ddr3_val/Kconfig" source "board/grinn/liteboard/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/phytec/pfla02/Kconfig" diff --git a/arch/arm/mach-imx/mx6/Makefile b/arch/arm/mach-imx/mx6/Makefile index 7ea8f91e4f0..a6e45391db2 100644 --- a/arch/arm/mach-imx/mx6/Makefile +++ b/arch/arm/mach-imx/mx6/Makefile @@ -4,6 +4,8 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # (C) Copyright 2011 Freescale Semiconductor, Inc. +# Copyright 2018 NXP +# obj-y := soc.o clock.o obj-$(CONFIG_IMX_MODULE_FUSE) += module_fuse.o @@ -11,3 +13,6 @@ obj-$(CONFIG_SPL_BUILD) += ddr.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_MX6UL_LITESOM) += litesom.o obj-$(CONFIG_MX6UL_OPOS6UL) += opos6ul.o +ifdef CONFIG_MX6UL +obj-$(CONFIG_CMD_BEE) += bee.o +endif diff --git a/arch/arm/mach-imx/mx6/bee.c b/arch/arm/mach-imx/mx6/bee.c new file mode 100644 index 00000000000..a852c5f3a29 --- /dev/null +++ b/arch/arm/mach-imx/mx6/bee.c @@ -0,0 +1,466 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if (defined(CONFIG_SYS_DCACHE_OFF) || defined(CONFIG_SYS_ICACHE_OFF)) +#error "Bee needs Cache Open" +#endif + +struct bee_parameters { + int key_method; + int mode; + u32 start1; + u32 size1; + u32 start2; + u32 size2; +}; + +#define SOFT_KEY 0 +#define SNVS_KEY 1 + +#define ECB_MODE 0 +#define CTR_MODE 1 + +#define AES_REGION0_ADDR 0x10000000 +#define AES_REGION1_ADDR 0x30000000 + +static struct bee_parameters para; +static int bee_inited; + +union key_soft { + u8 s_key[16]; + u32 b_key[4]; +}; + +union key_soft key_bad; + +/* software version */ +u8 hw_get_random_byte(void) +{ + static u32 lcg_state; + static u32 nb_soft = 9876543; +#define MAX_SOFT_RNG 1024 + static const u32 a = 1664525; + static const u32 c = 1013904223; + nb_soft = (nb_soft + 1) % MAX_SOFT_RNG; + lcg_state = (a * lcg_state + c); + return (u8) (lcg_state >> 24); +} + +/* + * Lock bee GPR0 bits + * Only reset can release these bits. + */ +static int bee_lock(void) +{ + int val; + + val = readl(BEE_BASE_ADDR + GPR0); + val |= (GPR0_CTRL_CLK_EN_LOCK | GPR0_CTRL_SFTRST_N_LOCK | + GPR0_CTRL_AES_MODE_LOCK | GPR0_SEC_LEVEL_LOCK | + GPR0_AES_KEY_SEL_LOCK | GPR0_BEE_ENABLE_LOCK); + writel(val, BEE_BASE_ADDR + GPR0); + + return 0; +} + +/* Only check bee enable lock is enough */ +static int bee_locked(void) +{ + int val; + + val = readl(BEE_BASE_ADDR + GPR0); + + return val & GPR0_BEE_ENABLE_LOCK ? 1 : 0; +} + +int bee_init(struct bee_parameters *p) +{ + int i; + union key_soft *key = &key_bad; + u32 value; + + if (bee_locked()) { + printf("BEE already enabled and locked.\n"); + return CMD_RET_FAILURE; + } + + /* CLKGATE, SFTRST */ + writel(GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N, BEE_BASE_ADDR + GPR0); + /* OFFSET_ADDR0 */ + writel(p->start1 >> 16, BEE_BASE_ADDR + GPR1); + /* + * OFFSET_ADDR1 + * Default protect IRAM region, if what you want to protect + * bigger that 512M which is the max size that one AES region + * can protect, we need AES region 1 to cover. + */ + writel(p->start2 >> 16, BEE_BASE_ADDR + GPR2); + + if (p->key_method == SOFT_KEY) { + for (i = 0; i < 16; i++) + key->s_key[i] = hw_get_random_byte(); + /* AES 128 key from software */ + /* aes0_key0_w0 */ + writel(key->b_key[0], BEE_BASE_ADDR + GPR3); + /* aes0_key0_w1 */ + writel(key->b_key[1], BEE_BASE_ADDR + GPR4); + /* aes0_key0_w2 */ + writel(key->b_key[2], BEE_BASE_ADDR + GPR5); + /* aes0_key0_w3 */ + writel(key->b_key[3], BEE_BASE_ADDR + GPR6); + } + + if (p->mode == ECB_MODE) { + value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | + GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS | + GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB; + if (p->key_method == SOFT_KEY) + value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | + GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT | + GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_ECB; + writel(value, BEE_BASE_ADDR + GPR0); + } else { + for (i = 0; i < 16; i++) + key->s_key[i] = hw_get_random_byte(); + /* aes_key1_w0 */ + writel(key->b_key[0], BEE_BASE_ADDR + GPR8); + /* aes_key1_w1 */ + writel(key->b_key[1], BEE_BASE_ADDR + GPR9); + /* aes_key1_w2 */ + writel(key->b_key[2], BEE_BASE_ADDR + GPR10); + /* aes_key1_w3 */ + writel(key->b_key[3], BEE_BASE_ADDR + GPR11); + + value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | + GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SNVS | + GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR; + if (p->key_method == SOFT_KEY) + value = GPR0_CTRL_CLK_EN | GPR0_CTRL_SFTRST_N | + GPR0_SEC_LEVEL_3 | GPR0_AES_KEY_SEL_SOFT | + GPR0_BEE_ENABLE | GPR0_CTRL_AES_MODE_CTR; + writel(value, BEE_BASE_ADDR + GPR0); + } + + bee_lock(); + + printf("BEE is settings as: %s mode, %s %d key\n", + (p->mode == ECB_MODE) ? "ECB" : "CTR", + (p->key_method == SOFT_KEY) ? "SOFT" : "SNVS HW", + (p->mode == ECB_MODE) ? 128 : 256); + + return CMD_RET_SUCCESS; +} + +int bee_test(struct bee_parameters *p, int region) +{ + u32 result = 0, range, address; + int i, val; + /* + * Test instruction running in AES Region: + * int test(void) + * { + * return 0x55aa55aa; + * } + * Assemble: + * 0xe59f0000: ldr r0, [pc] + * 0xe12fff1e: bx lr + * 0x55aa55aa: 0x55aa55aa + */ + u32 inst[3] = {0xe59f0000, 0xe12fff1e, 0x55aa55aa}; + + /* Cache enabled? */ + if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) { + printf("Enable dcache and icache first!\n"); + return CMD_RET_FAILURE; + } + + printf("Test Region %d\nBegin Data test: Writing... ", region); + + range = (region == 0) ? p->size1 : p->size2; + address = (region == 0) ? AES_REGION0_ADDR : AES_REGION1_ADDR; + for (i = 0; i < range; i = i + 4) + writel(i, address + i); + + printf("Finshed Write!\n"); + + flush_dcache_range(address, address + range); + + printf("Reading... "); + for (i = 0; i < range; i = i + 4) { + val = readl(address + i); + if (val != i) + result++; + } + printf("Finshed Read!\n"); + + if (result > 0) + printf("BEE Data Test check Failed!\n"); + else + printf("BEE Data Test Check Passed!\n"); + + for (i = 0; i < ARRAY_SIZE(inst); i++) + writel(inst[i], address + (i * 4)); + + flush_dcache_range(address, address + sizeof(inst)); + + val = ((int (*)(void))address)(); + + printf("\nBee Instruction test, Program:\n" + "int test(void)\n" + "{\n" + " return 0x55aa55aa;\n" + "}\n" + "Assemble:\n" + "0xe59f0000: ldr r0, [pc]\n" + "0xe12fff1e: bx lr\n" + "0x55aa55aa: 0x55aa55aa\n" + "Runnint at 0x%x\n", address); + if (val == 0x55aa55aa) + printf("Bee Instruction Test Passed!\n"); + else + printf("Bee Instruction Test Failed!\n"); + + return CMD_RET_SUCCESS; +} + +static int region_valid(u32 start, u32 size) +{ + if ((start < PHYS_SDRAM) || (start >= (start + size - 1)) || + (start >= (PHYS_SDRAM + PHYS_SDRAM_SIZE - 1))) { + printf("Invalid start 0x%x, size 0x%x\n", start, size); + return -EINVAL; + } + + if (size > SZ_512M) { + printf("The region size exceeds SZ_512M\n"); + return -EINVAL; + } + + if ((start & 0xFFFF) && (size & 0xFFFF)) { + printf("start or size not 64KB aligned!\n"); + return -EINVAL; + } + + /* 128K for U-Boot Stack */ + if ((start + size - 1) >= (gd->start_addr_sp - SZ_128K)) { + printf("Overlap with uboot execution environment!\n" + "Decrease size or start\n"); + return -EINVAL; + } + + return 0; +} + +static int do_bee_init(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 start, size; + int ret; + struct bee_parameters *p = ¶ + +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + enum dcache_option option = DCACHE_WRITETHROUGH & ~TTB_SECT_XN_MASK; +#else + enum dcache_option option = DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK; +#endif + + if (argc > 5) + return CMD_RET_USAGE; + + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_BEE)) { + printf("BEE is fused, disable it!\n"); + return CMD_RET_FAILURE; + } + } + + /* Cache enabled? */ + if ((get_cr() & (CR_I | CR_C)) != (CR_I | CR_C)) { + /* + * Here we need icache and dcache both enabled, because + * we may take the protected region for instruction and + * data usage. And icache and dcache both enabled are + * better for performance. + */ + printf("Please enable dcache and icache first!\n"); + return CMD_RET_FAILURE; + } + + p->key_method = SOFT_KEY; + p->mode = ECB_MODE; + p->start1 = PHYS_SDRAM; + p->size1 = SZ_512M; + p->start2 = IRAM_BASE_ADDR; + p->size2 = IRAM_SIZE; + + if (argc == 2) { + p->key_method = (int)simple_strtoul(argv[1], NULL, 16); + p->mode = ECB_MODE; + p->start1 = PHYS_SDRAM; + p->size1 = SZ_512M; + } else if (argc == 3) { + p->key_method = (int)simple_strtoul(argv[1], NULL, 16); + p->mode = (int)simple_strtoul(argv[2], NULL, 10); + p->start1 = PHYS_SDRAM; + p->size1 = SZ_512M; + } else if ((argc == 4) || (argc == 5)) { + p->key_method = (int)simple_strtoul(argv[1], NULL, 16); + p->mode = (int)simple_strtoul(argv[2], NULL, 10); + start = (u32)simple_strtoul(argv[3], NULL, 16); + /* Default size that AES Region0 can protected */ + size = SZ_512M; + if (argc == 5) + size = (u32)simple_strtoul(argv[4], NULL, 16); + p->start1 = start; + p->size1 = size; + } + + if ((p->key_method != SOFT_KEY) && (p->key_method != SNVS_KEY)) + return CMD_RET_USAGE; + + if ((p->mode != ECB_MODE) && (p->mode != CTR_MODE)) + return CMD_RET_USAGE; + + /* + * No need to check region valid for IRAM, since it is fixed. + * Only check DRAM region here. + */ + if (region_valid(p->start1, p->size1)) + return CMD_RET_FAILURE; + + ret = bee_init(p); + if (ret) + return CMD_RET_FAILURE; + + /* + * Set DCACHE OFF to AES REGION0 and AES REGION1 first + * to avoid possible unexcepted cache settings. + */ + mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, SZ_1G, DCACHE_OFF); + + mmu_set_region_dcache_behaviour(AES_REGION0_ADDR, p->size1, option); + + mmu_set_region_dcache_behaviour(AES_REGION1_ADDR, p->size2, option); + + printf("Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n" + "Do not directly access 0x%x - 0x%x\n" + "Access Region 0x%x - 0x%x to protect 0x%x - 0x%x\n" + "Do not directly access 0x%x - 0x%x\n", + AES_REGION0_ADDR, AES_REGION0_ADDR + p->size1 - 1, + p->start1, p->start1 + p->size1 - 1, + p->start1, p->start1 + p->size1 - 1, + AES_REGION1_ADDR, AES_REGION1_ADDR + p->size2 - 1, + p->start2, p->start2 + p->size2 - 1, + p->start2, p->start2 + p->size2 - 1); + + bee_inited = 1; + + return CMD_RET_SUCCESS; +} + +static int do_bee_test(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + int ret; + int region; + + if (bee_inited == 0) { + printf("Bee not initialized, run bee init first!\n"); + return CMD_RET_FAILURE; + } + if (argc > 2) + return CMD_RET_USAGE; + + region = 0; + if (argc == 2) + region = (int)simple_strtoul(argv[1], NULL, 16); + /* Only two regions are supported, 0 and 1 */ + if (region >= 2) + return CMD_RET_USAGE; + + ret = bee_test(¶, region); + if (ret) + return CMD_RET_FAILURE; + + return CMD_RET_SUCCESS; +} + +static struct cmd_tbl cmd_bmp_sub[] = { + U_BOOT_CMD_MKENT(init, 5, 0, do_bee_init, "", ""), + U_BOOT_CMD_MKENT(test, 2, 0, do_bee_test, "", ""), +}; + +static int do_bee_ops(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct cmd_tbl *c; + + c = find_cmd_tbl(argv[1], &cmd_bmp_sub[0], ARRAY_SIZE(cmd_bmp_sub)); + + /* Drop off the 'bee' command argument */ + argc--; + argv++; + + if (c) + return c->cmd(cmdtp, flag, argc, argv); + else + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + bee, CONFIG_SYS_MAXARGS, 1, do_bee_ops, + "BEE function test", + "init [key] [mode] [start] [size] - BEE block initial\n" + " key: 0 | 1, 0 means software key, 1 means SNVS random key\n" + " mode: 0 | 1, 0 means ECB mode, 1 means CTR mode\n" + " start: start address that you want to protect\n" + " size: The size of the area that you want to protect\n" + " start and end(start + size) addr both should be 64KB aligned.\n" + "\n" + " After initialization, the mapping:\n" + " 1. [0x10000000 - (0x10000000 + size - 1)] <--->\n" + " [start - (start + size - 1)]\n" + " Here [start - (start + size -1)] is fixed mapping to\n" + " [0x10000000 - (0x10000000 + size - 1)], whatever start is.\n" + " 2. [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] <--->\n" + " [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)]\n" + "\n" + " Note: Here we only use AES region 0 to protect the DRAM\n" + " area that you specified, max size SZ_512M.\n" + " AES region 1 is used to protect IRAM area.\n" + " Example:\n" + " 1. bee init 1 1 0xa0000000 0x10000\n" + " Access 0x10000000 - 0x10010000 to protect 0xa0000000 - 0xa0010000\n" + " 2. bee init 1 1 0x80000000 0x20000\n" + " Access 0x10000000 - 0x10020000 to protect 0x80000000 - 0x80020000\n" + "\n" + " Default configuration if only `bee init` without any args:\n" + " 1. software key\n" + " 2. ECB mode\n" + " 3. Address protected:\n" + " Remapped Region0: PHYS_SDRAM - PHYS_SDRAM + SZ_512M\n" + " Remapped Region1: IRAM_BASE_ADDR - IRAM_BASE_ADDR + IRAM_SIZE\n" + " 4. Default Mapping for 6UL:\n" + " [0x10000000 - 0x2FFFFFFF] <-> [0x80000000 - 0x9FFFFFFF]\n" + " [0x30000000 - 0x3001FFFF] <-> [0x00900000 - 0x0091FFFF]\n" + "\n" + "bee test [region] - BEE function test\n" + " region: 0 | 1, 0 means region0, 1 means regions1\n" +); + diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index cb9d629be40..7a9007b82a4 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #include @@ -60,6 +61,12 @@ void setup_gpmi_io_clk(u32 cfg) cfg); setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); +#elif defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) + clrsetbits_le32(&imx_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + cfg); #else clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); @@ -851,6 +858,65 @@ int enable_lcdif_clock(u32 base_addr, bool enable) return 0; } + +int enable_lvds_bridge(u32 lcd_base_addr) +{ + u32 reg = 0; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + if (is_cpu_type(MXC_CPU_MX6SX)) { + if ((lcd_base_addr != LCDIF1_BASE_ADDR) && + (lcd_base_addr != LCDIF2_BASE_ADDR)) { + puts("Wrong LCD interface!\n"); + return -EINVAL; + } + } else { + debug("This chip not support lvds bridge!\n"); + return 0; + } + + /* Turn on LDB DI0 clocks */ + reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_LDB_DI0_MASK; + writel(reg, &imx_ccm->CCGR3); + + /* set LDB DI0 clk select to 011 PLL2 PFD3 200M*/ + reg = readl(&imx_ccm->cs2cdr); + reg &= ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK; + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET); + writel(reg, &imx_ccm->cs2cdr); + + reg = readl(&imx_ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &imx_ccm->cscmr2); + + /* set LDB DI0 clock for LCDIF PIX clock */ + reg = readl(&imx_ccm->cscdr2); + if (lcd_base_addr == LCDIF1_BASE_ADDR) { + reg &= ~MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK; + reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET); + } else { + reg &= ~MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK; + reg |= (0x3 << MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET); + } + writel(reg, &imx_ccm->cscdr2); + + reg = IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[6]); + + reg = readl(&iomux->gpr[5]); + if (lcd_base_addr == LCDIF1_BASE_ADDR) + reg &= ~0x8; /* MUX LVDS to LCDIF1 */ + else + reg |= 0x8; /* MUX LVDS to LCDIF2 */ + writel(reg, &iomux->gpr[5]); + + return 0; +} + #endif #ifdef CONFIG_FSL_QSPI @@ -903,6 +969,18 @@ void enable_qspi_clk(int qspi_num) } #endif +#if defined(CONFIG_VIDEO_GIS) +void mxs_set_vadcclk() +{ + u32 reg = 0; + + reg = readl(&imx_ccm->cscmr2); + reg &= ~MXC_CCM_CSCMR2_VID_CLK_SEL_MASK; + reg |= 0x19 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET; + writel(reg, &imx_ccm->cscmr2); +} +#endif + #ifdef CONFIG_FEC_MXC int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) { @@ -1043,7 +1121,7 @@ u32 imx_get_fecclk(void) return mxc_get_clock(MXC_IPG_CLK); } -#if defined(CONFIG_SATA) || defined(CONFIG_PCIE_IMX) +#if defined(CONFIG_SATA) || defined(CONFIG_IMX_AHCI) || defined(CONFIG_PCIE_IMX) static int enable_enet_pll(uint32_t en) { struct mxc_ccm_reg *const imx_ccm @@ -1070,7 +1148,7 @@ static int enable_enet_pll(uint32_t en) } #endif -#ifdef CONFIG_SATA +#if defined(CONFIG_SATA) || defined(CONFIG_IMX_AHCI) static void ungate_sata_clock(void) { struct mxc_ccm_reg *const imx_ccm = @@ -1096,6 +1174,15 @@ void disable_sata_clock(void) #endif #ifdef CONFIG_PCIE_IMX +static void ungate_disp_axi_clock(void) +{ + struct mxc_ccm_reg *const imx_ccm = + (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Enable display axi clock. */ + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_DISP_AXI_MASK); +} + static void ungate_pcie_clock(void) { struct mxc_ccm_reg *const imx_ccm = @@ -1143,14 +1230,22 @@ int enable_pcie_clock(void) /* PCIe reference clock sourced from AXI. */ clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); + if (!is_mx6sx()) { /* Party time! Ungate the clock to the PCIe. */ -#ifdef CONFIG_SATA - ungate_sata_clock(); +#if defined(CONFIG_SATA) || defined(CONFIG_IMX_AHCI) + ungate_sata_clock(); #endif - ungate_pcie_clock(); + ungate_pcie_clock(); + + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | + BM_ANADIG_PLL_ENET_ENABLE_PCIE); + } else { + /* Party time! Ungate the clock to the PCIe. */ + ungate_disp_axi_clock(); + ungate_pcie_clock(); - return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA | - BM_ANADIG_PLL_ENET_ENABLE_PCIE); + return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_PCIE); + } } #endif @@ -1341,7 +1436,7 @@ int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, } #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6DL) || \ - defined(CONFIG_MX6S) || defined(CONFIG_MX6QDL) + defined(CONFIG_MX6S) || defined(CONFIG_MX6QDL) || defined(CONFIG_MX6QP) static void disable_ldb_di_clock_sources(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -1490,6 +1585,38 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk) } #endif + +#if defined(CONFIG_MXC_EPDC) +#if defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) +void enable_epdc_clock(void) +{ + u32 reg = 0; + + /* disable the clock gate first */ + clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK); + + /* PLL3_PFD2 */ + reg = readl(&imx_ccm->chsccdr); + reg &= ~MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK; + reg |= 5 << MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET; + writel(reg, &imx_ccm->chsccdr); + + reg = readl(&imx_ccm->chsccdr); + reg &= ~MXC_CCM_CHSCCDR_EPDC_PODF_MASK; + reg |= 7 << MXC_CCM_CHSCCDR_EPDC_PODF_OFFSET; + writel(reg, &imx_ccm->chsccdr); + + reg = readl(&imx_ccm->chsccdr); + reg &= ~MXC_CCM_CHSCCDR_EPDC_CLK_SEL_MASK; + reg |= 0 <chsccdr); + + /* enable the clock gate */ + setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_EPDC_CLK_ENABLE_MASK); +} +#endif +#endif + /***************************************************/ U_BOOT_CMD( diff --git a/arch/arm/mach-imx/mx6/ddr.c b/arch/arm/mach-imx/mx6/ddr.c index f872bfdab31..704869cbdd9 100644 --- a/arch/arm/mach-imx/mx6/ddr.c +++ b/arch/arm/mach-imx/mx6/ddr.c @@ -780,7 +780,7 @@ void mx6sl_dram_iocfg(unsigned width, } #endif -#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) +#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D) || defined(CONFIG_MX6QP) /* Configure MX6DQ mmdc iomux */ void mx6dq_dram_iocfg(unsigned width, const struct mx6dq_iomux_ddr_regs *ddr, diff --git a/arch/arm/mach-imx/mx6/module_fuse.c b/arch/arm/mach-imx/mx6/module_fuse.c index 0f4565e3117..c24d8279eda 100644 --- a/arch/arm/mach-imx/mx6/module_fuse.c +++ b/arch/arm/mach-imx/mx6/module_fuse.c @@ -13,6 +13,45 @@ static struct fuse_entry_desc mx6_fuse_descs[] = { #if defined(CONFIG_MX6ULL) + {MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22}, + {MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23}, + {MODULE_EPDC, "/soc/bus@2200000/epdc@228c000", 0x430, 24}, + {MODULE_ESAI, "/soc/bus@2000000/spba-bus@2000000/esai@2024000", 0x430, 25}, + {MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26}, + {MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27}, + {MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2}, + {MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3}, + {MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4}, + {MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5}, + {MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6}, + {MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7}, + {MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8}, + {MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9}, + {MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10}, + {MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11}, + {MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12}, + {MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13}, + {MODULE_DCP, "/soc/bus@2200000/dcp@2280000", 0x440, 14}, + {MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15}, + {MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24}, + {MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24}, + {MODULE_DCP_CRYPTO, "/soc/bus@2200000/dcp@2280000", 0x440, 25}, + {MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26}, + {MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26}, + {MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26}, + {MODULE_UART8, "/soc/bus@2200000/serial@2288000", 0x440, 26}, + {MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27}, + {MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27}, + {MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27}, + {MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28}, + {MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29}, + {MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29}, + {MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30}, + {MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31}, + {MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22}, {MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23}, {MODULE_EPDC, "/soc/aips-bus@2200000/epdc@228c000", 0x430, 24}, @@ -91,6 +130,45 @@ static struct fuse_entry_desc mx6_fuse_descs[] = { {MODULE_GPT2, "/soc/aips-bus@02000000/gpt@020e8000", 0x440, 30}, {MODULE_EPIT2, "/soc/aips-bus@02000000/epit@020d4000", 0x440, 31}, #elif defined(CONFIG_MX6UL) + {MODULE_TSC, "/soc/bus@2000000/tsc@2040000", 0x430, 22}, + {MODULE_ADC2, "/soc/bus@2100000/adc@219c000", 0x430, 23}, + {MODULE_SIM1, "/soc/bus@2100000/sim@218c000", 0x430, 24}, + {MODULE_SIM2, "/soc/bus@2100000/sim@21b4000", 0x430, 25}, + {MODULE_FLEXCAN1, "/soc/bus@2000000/can@2090000", 0x430, 26}, + {MODULE_FLEXCAN2, "/soc/bus@2000000/can@2094000", 0x430, 27}, + {MODULE_SPDIF, "/soc/bus@2000000/spba-bus@2000000/spdif@2004000", 0x440, 2}, + {MODULE_EIM, "/soc/bus@2100000/weim@21b8000", 0x440, 3}, + {MODULE_SD1, "/soc/bus@2100000/usdhc@2190000", 0x440, 4}, + {MODULE_SD2, "/soc/bus@2100000/usdhc@2194000", 0x440, 5}, + {MODULE_QSPI1, "/soc/bus@2100000/qspi@21e0000", 0x440, 6}, + {MODULE_GPMI, "/soc/nand-controller@1806000", 0x440, 7}, + {MODULE_APBHDMA, "/soc/dma-apbh@1804000", 0x440, 7}, + {MODULE_LCDIF, "/soc/bus@2100000/lcdif@21c8000", 0x440, 8}, + {MODULE_PXP, "/soc/bus@2100000/pxp@21cc000", 0x440, 9}, + {MODULE_CSI, "/soc/bus@2100000/csi@21c4000", 0x440, 10}, + {MODULE_ADC1, "/soc/bus@2100000/adc@2198000", 0x440, 11}, + {MODULE_ENET1, "/soc/bus@2100000/ethernet@2188000", 0x440, 12}, + {MODULE_ENET2, "/soc/bus@2000000/ethernet@20b4000", 0x440, 13}, + {MODULE_CAAM, "/soc/bus@2100000/caam@2140000", 0x440, 14}, + {MODULE_USB_OTG2, "/soc/bus@2100000/usb@2184200", 0x440, 15}, + {MODULE_SAI2, "/soc/bus@2000000/spba-bus@2000000/sai@202c000", 0x440, 24}, + {MODULE_SAI3, "/soc/bus@2000000/spba-bus@2000000/sai@2030000", 0x440, 24}, + {MODULE_BEE, "/soc/bus@2000000/bee@2044000", 0x440, 25}, + {MODULE_UART5, "/soc/bus@2100000/serial@21f4000", 0x440, 26}, + {MODULE_UART6, "/soc/bus@2100000/serial@21fc000", 0x440, 26}, + {MODULE_UART7, "/soc/bus@2000000/spba-bus@2000000/serial@2018000", 0x440, 26}, + {MODULE_UART8, "/soc/bus@2000000/spba-bus@2000000/serial@2024000", 0x440, 26}, + {MODULE_PWM5, "/soc/bus@2000000/pwm@20f0000", 0x440, 27}, + {MODULE_PWM6, "/soc/bus@2000000/pwm@20f4000", 0x440, 27}, + {MODULE_PWM7, "/soc/bus@2000000/pwm@20f8000", 0x440, 27}, + {MODULE_PWM8, "/soc/bus@2000000/pwm@20fc000", 0x440, 27}, + {MODULE_ECSPI3, "/soc/bus@2000000/spba-bus@2000000/ecspi@2010000", 0x440, 28}, + {MODULE_ECSPI4, "/soc/bus@2000000/spba-bus@2000000/ecspi@2014000", 0x440, 28}, + {MODULE_I2C3, "/soc/bus@2100000/i2c@21a8000", 0x440, 29}, + {MODULE_I2C4, "/soc/bus@2100000/i2c@21f8000", 0x440, 29}, + {MODULE_GPT2, "/soc/bus@2000000/gpt@20e8000", 0x440, 30}, + {MODULE_EPIT2, "/soc/bus@2000000/epit@20d4000", 0x440, 31}, + {MODULE_TSC, "/soc/aips-bus@2000000/tsc@2040000", 0x430, 22}, {MODULE_ADC2, "/soc/aips-bus@2100000/adc@219c000", 0x430, 23}, {MODULE_SIM1, "/soc/aips-bus@2100000/sim@218c000", 0x430, 24}, @@ -129,6 +207,7 @@ static struct fuse_entry_desc mx6_fuse_descs[] = { {MODULE_I2C4, "/soc/aips-bus@2100000/i2c@21f8000", 0x440, 29}, {MODULE_GPT2, "/soc/aips-bus@2000000/gpt@20e8000", 0x440, 30}, {MODULE_EPIT2, "/soc/aips-bus@2000000/epit@20d4000", 0x440, 31}, + /* Paths for older imx tree: */ {MODULE_TSC, "/soc/aips-bus@02000000/tsc@02040000", 0x430, 22}, {MODULE_ADC2, "/soc/aips-bus@02100000/adc@0219c000", 0x430, 23}, @@ -206,7 +285,7 @@ int ft_system_setup(void *blob, struct bd_info *bd) if (off < 0) continue; /* Not found, skip it */ add_status: - rc = fdt_setprop(blob, nodeoff, "status", status, + rc = fdt_setprop(blob, off, "status", status, strlen(status) + 1); if (rc) { if (rc == -FDT_ERR_NOSPACE) { diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index aacfc854a2f..fa785cbbdeb 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -4,6 +4,7 @@ * Sascha Hauer, Pengutronix * * (C) Copyright 2009 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #include @@ -23,9 +24,16 @@ #include #include #include -#include +#include +#include #include #include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; #define has_err007805() \ (is_mx6sl() || is_mx6dl() || is_mx6solo() || is_mx6ull()) @@ -234,6 +242,35 @@ u32 __weak get_board_rev(void) } #endif +#ifdef CONFIG_IMX_TRUSTY_OS +#ifdef CONFIG_MX6UL +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + return; +} + +void smp_waitloop(unsigned previous_address) +{ + return; +} +#endif +#endif + +static void init_csu(void) +{ +#ifdef CONFIG_ARMV7_NONSEC + int i; + u32 csu = CSU_BASE_ADDR; + /* + * This is to allow device can be accessed in non-secure world. + * All imx6 chips CSU have 40 Config security level registers. + */ + for (i = 0; i < 40; i ++) { + *((u32 *)csu + i) = 0xffffffff; + } +#endif +} + static void clear_ldo_ramp(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; @@ -375,7 +412,7 @@ static void init_bandgap(void) } } -#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) || defined(CONFIG_MX6QP) static void noc_setup(void) { enable_ipu_clock(); @@ -406,12 +443,144 @@ static void noc_setup(void) } #endif +#ifdef CONFIG_MX6SX +void vadc_power_up(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + u32 val; + + /* csi0 */ + val = readl(&iomux->gpr[5]); + val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, + val |= IMX6SX_GPR5_CSI1_MUX_CTRL_CVD; + writel(val, &iomux->gpr[5]); + + /* Power on vadc analog + * Power down vadc ext power */ + val = readl(GPC_BASE_ADDR + 0); + val &= ~0x60000; + writel(val, GPC_BASE_ADDR + 0); + + /* software reset afe */ + val = readl(&iomux->gpr[1]); + writel(val | 0x80000, &iomux->gpr[1]); + + udelay(10*1000); + + /* Release reset bit */ + writel(val & ~0x80000, &iomux->gpr[1]); + + /* Power on vadc ext power */ + val = readl(GPC_BASE_ADDR + 0); + val |= 0x40000; + writel(val, GPC_BASE_ADDR + 0); +} + +void vadc_power_down(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + u32 val; + + /* Power down vadc ext power + * Power off vadc analog */ + val = readl(GPC_BASE_ADDR + 0); + val &= ~0x40000; + val |= 0x20000; + writel(val, GPC_BASE_ADDR + 0); + + /* clean csi0 connect to vadc */ + val = readl(&iomux->gpr[5]); + val &= ~IMX6SX_GPR5_CSI1_MUX_CTRL_MASK, + writel(val, &iomux->gpr[5]); +} + +void pcie_power_up(void) +{ + set_ldo_voltage(LDO_PU, 1100); /* Set VDDPU to 1.1V */ +} + +void pcie_power_off(void) +{ + set_ldo_voltage(LDO_PU, 0); /* Set VDDPU to 1.1V */ +} +#endif + +static void imx_set_vddpu_power_down(void) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + u32 val; + + /* need to power down xPU in GPC before turn off PU LDO */ + val = readl(GPC_BASE_ADDR + 0x260); + writel(val | 0x1, GPC_BASE_ADDR + 0x260); + + val = readl(GPC_BASE_ADDR + 0x0); + writel(val | 0x1, GPC_BASE_ADDR + 0x0); + while (readl(GPC_BASE_ADDR + 0x0) & 0x1) + ; + + /* disable VDDPU */ + val = 0x3e00; + writel(val, &anatop->reg_core_clr); +} + +static void imx_set_pcie_phy_power_down(void) +{ + u32 val; + + if (!is_cpu_type(MXC_CPU_MX6SX)) { + val = readl(IOMUXC_BASE_ADDR + 0x4); + val |= 0x1 << 18; + writel(val, IOMUXC_BASE_ADDR + 0x4); + } else { + val = readl(IOMUXC_GPR_BASE_ADDR + 0x30); + val |= 0x1 << 30; + writel(val, IOMUXC_GPR_BASE_ADDR + 0x30); + } +} + +bool is_usb_boot(void) +{ + if (gd->flags & GD_FLG_ARCH_IMX_USB_BOOT) + return true; + + return false; +} + int arch_cpu_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + if (is_usbphy_power_on()) + gd->flags |= GD_FLG_ARCH_IMX_USB_BOOT; + + if (!is_mx6sl() && !is_mx6sx() + && !is_mx6ul() && !is_mx6ull() + && !is_mx6sll()) { + /* + * imx6sl doesn't have pcie at all. + * this bit is not used by imx6sx anymore + */ + u32 val; + + /* + * There are about 0.02% percentage, random pcie link down + * when warm-reset is used. + * clear the ref_ssp_en bit16 of gpr1 to workaround it. + * then warm-reset imx6q/dl/solo again. + */ + val = readl(IOMUXC_BASE_ADDR + 0x4); + if (val & (0x1 << 16)) { + val &= ~(0x1 << 16); + writel(val, IOMUXC_BASE_ADDR + 0x4); + reset_cpu(0); + } + } + init_aips(); + init_csu(); + /* Need to clear MMDC_CHx_MASK to make warm reset work. */ clear_mmdc_ch_mask(); @@ -481,19 +650,32 @@ int arch_cpu_init(void) if (is_mx6sx()) setbits_le32(&ccm->cscdr1, MXC_CCM_CSCDR1_UART_CLK_SEL); + if (!is_mx6sl() && !is_mx6ul() && + !is_mx6ull() && !is_mx6sll()) + imx_set_pcie_phy_power_down(); + + if (!is_mx6dqp() && !is_mx6ul() && + !is_mx6ull() && !is_mx6sll()) + imx_set_vddpu_power_down(); + init_src(); -#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL) || defined(CONFIG_MX6QP) if (is_mx6dqp()) noc_setup(); #endif + configure_tzc380(); + return 0; } -#ifdef CONFIG_ENV_IS_IN_MMC +#ifndef CONFIG_SYS_MMC_ENV_DEV +#define CONFIG_SYS_MMC_ENV_DEV -1 +#endif + __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return devno; } static int mmc_get_boot_dev(void) @@ -512,7 +694,7 @@ static int mmc_get_boot_dev(void) bootsel = (soc_sbmr & 0x000000FF) >> 6; /* No boot from sd/mmc */ - if (bootsel != 1) + if (is_usb_boot() || bootsel != 1) return -1; /* BOOT_CFG2[3] and BOOT_CFG2[4] */ @@ -527,7 +709,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (devno < 0) - return CONFIG_SYS_MMC_ENV_DEV; + return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); return board_mmc_get_env_dev(devno); } @@ -549,7 +731,6 @@ uint mmc_get_env_part(struct mmc *mmc) return board_mmc_get_env_part(devno); } #endif -#endif int board_postclk_init(void) { @@ -562,6 +743,19 @@ int board_postclk_init(void) return 0; } +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse = + (struct fuse_bank0_regs *)bank->fuse_regs; + + serialnr->low = fuse->uid_low; + serialnr->high = fuse->uid_high; +} +#endif + #ifndef CONFIG_SPL_BUILD /* * cfg_val will be used for @@ -575,7 +769,7 @@ const struct boot_mode soc_boot_modes[] = { #if defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) {"usb", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, #else - {"usb", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)}, #endif {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)}, {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)}, @@ -591,6 +785,71 @@ const struct boot_mode soc_boot_modes[] = { }; #endif +enum boot_device get_boot_device(void) +{ + enum boot_device boot_dev = UNKNOWN_BOOT; + uint soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + uint bt_mem_ctl = (soc_sbmr & 0x000000FF) >> 4 ; + uint bt_mem_type = (soc_sbmr & 0x00000008) >> 3; + uint bt_dev_port = (soc_sbmr & 0x00001800) >> 11; + + switch (bt_mem_ctl) { + case 0x0: + if (bt_mem_type) + boot_dev = ONE_NAND_BOOT; + else + boot_dev = WEIM_NOR_BOOT; + break; + case 0x2: + boot_dev = SATA_BOOT; + break; + case 0x3: + if (bt_mem_type) + boot_dev = I2C_BOOT; + else + boot_dev = SPI_NOR_BOOT; + break; + case 0x4: + case 0x5: + boot_dev = bt_dev_port + SD1_BOOT; + break; + case 0x6: + case 0x7: + boot_dev = bt_dev_port + MMC1_BOOT; + break; + case 0x8 ... 0xf: + boot_dev = NAND_BOOT; + break; + default: + boot_dev = UNKNOWN_BOOT; + break; + } + + return boot_dev; +} + +void set_wdog_reset(struct wdog_regs *wdog) +{ + u32 reg = readw(&wdog->wcr); + /* + * use WDOG_B mode to reset external pmic because it's risky for the + * following watchdog reboot in case of cpu freq at lowest 400Mhz with + * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So + * in ldo-bypass mode watchdog reset will only triger POR reset, not + * WDOG reset. But below code depends on hardware design, if HW didn't + * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip + * these code since it assumed boot from 400Mhz always. + */ + reg = readw(&wdog->wcr); + reg |= 1 << 3; + /* + * WDZST bit is write-once only bit. Align this bit in kernel, + * otherwise kernel code will have no chance to set this bit. + */ + reg |= 1 << 0; + writew(reg, &wdog->wcr); +} + void reset_misc(void) { #ifndef CONFIG_SPL_BUILD @@ -608,6 +867,10 @@ void s_init(void) u32 mask528; u32 reg, periph1, periph2; +#if defined(CONFIG_ANDROID_SUPPORT) + /* Enable RTC */ + writel(0x21, 0x020cc038); +#endif if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sll()) return; @@ -734,9 +997,14 @@ static void setup_serial_number(void) int arch_misc_init(void) { -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + setup_serial_number(); return 0; } @@ -770,3 +1038,122 @@ void gpr_init(void) writel(0x007F007F, &iomux->gpr[7]); } } + +#ifdef CONFIG_LDO_BYPASS_CHECK +DECLARE_GLOBAL_DATA_PTR; +static int ldo_bypass; + +int check_ldo_bypass(void) +{ + const int *ldo_mode; + int node; + + /* get the right fdt_blob from the global working_fdt */ + gd->fdt_blob = working_fdt; + /* Get the node from FDT for anatop ldo-bypass */ + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, + "fsl,imx6q-gpc"); + if (node < 0) { + printf("No gpc device node %d, force to ldo-enable.\n", node); + return 0; + } + ldo_mode = fdt_getprop(gd->fdt_blob, node, "fsl,ldo-bypass", NULL); + /* + * return 1 if "fsl,ldo-bypass = <1>", else return 0 if + * "fsl,ldo-bypass = <0>" or no "fsl,ldo-bypass" property + */ + ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0; + + return ldo_bypass; +} + +int check_1_2G(void) +{ + u32 reg; + int result = 0; + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[0]; + struct fuse_bank0_regs *fuse_bank0 = + (struct fuse_bank0_regs *)bank->fuse_regs; + + reg = readl(&fuse_bank0->cfg3); + if (((reg >> 16) & 0x3) == 0x3) { + if (ldo_bypass) { + printf("Wrong dtb file used! i.MX6Q@1.2Ghz only " + "works with ldo-enable mode!\n"); + /* + * Currently, only imx6q-sabresd board might be here, + * since only i.MX6Q support 1.2G and only Sabresd board + * support ldo-bypass mode. So hardcode here. + * You can also modify your board(i.MX6Q) dtb name if it + * supports both ldo-bypass and ldo-enable mode. + */ + printf("Please use imx6q-sabresd-ldo.dtb!\n"); + hang(); + } + result = 1; + } + + return result; +} + +static int arm_orig_podf; +void set_arm_freq_400M(bool is_400M) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + if (is_400M) + writel(0x1, &mxc_ccm->cacrr); + else + writel(arm_orig_podf, &mxc_ccm->cacrr); +} + +void prep_anatop_bypass(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + arm_orig_podf = readl(&mxc_ccm->cacrr); + /* + * Downgrade ARM speed to 400Mhz as half of boot 800Mhz before ldo + * bypassed, also downgrade internal vddarm ldo to 0.975V. + * VDDARM_IN 0.975V + 125mV = 1.1V < Max(1.3V) + * otherwise at 800Mhz(i.mx6dl): + * VDDARM_IN 1.175V + 125mV = 1.3V = Max(1.3V) + * We need provide enough gap in this case. + * skip if boot from 400M. + */ + if (!arm_orig_podf) + set_arm_freq_400M(true); + + if (!is_mx6dl() && !is_mx6sx()) + set_ldo_voltage(LDO_ARM, 975); + else + set_ldo_voltage(LDO_ARM, 1150); +} + +int set_anatop_bypass(int wdog_reset_pin) +{ + struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; + struct wdog_regs *wdog; + u32 reg = readl(&anatop->reg_core); + + /* bypass VDDARM/VDDSOC */ + reg = reg | (0x1F << 18) | 0x1F; + writel(reg, &anatop->reg_core); + + if (wdog_reset_pin == 2) + wdog = (struct wdog_regs *) WDOG2_BASE_ADDR; + else if (wdog_reset_pin == 1) + wdog = (struct wdog_regs *) WDOG1_BASE_ADDR; + else + return arm_orig_podf; + set_wdog_reset(wdog); + return arm_orig_podf; +} + +void finish_anatop_bypass(void) +{ + if (!arm_orig_podf) + set_arm_freq_400M(false); +} +#endif diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index c8146c3509d..c2d510ba076 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -23,6 +23,11 @@ config SPL_TEXT_BASE depends on SPL default 0x00912000 +config IMX_TAMPER + bool "Enable commands for SNVS tamper pin configuration and test" + help + Set "Y" to enable the tamper commands + choice prompt "MX7 board select" optional @@ -51,6 +56,49 @@ config TARGET_MX7DSABRESD select DM_THERMAL select MX7D imply CMD_DM + select FSL_CAAM + select FSL_BLOB + select MISC + +config TARGET_MX7D_12X12_LPDDR3_VAL + bool "Support mx7d_12x12_lpddr3_val" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + imply CMD_DM + +config TARGET_MX7D_12X12_DDR3_VAL + bool "Support mx7d_12x12_ddr3_val" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + imply CMD_DM + +config TARGET_MX7D_19X19_DDR3_VAL + bool "Support mx7d_19x19_ddr3_val" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + imply CMD_DM + +config TARGET_MX7D_19X19_LPDDR3_VAL + bool "Support mx7d_19x19_lpddr3_val" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + imply CMD_DM + +config TARGET_MX7D_19X19_LPDDR2_VAL + bool "Support mx7d_19x19_lpddr2_val" + select BOARD_LATE_INIT + select MX7D + select DM + select DM_THERMAL + imply CMD_DM config TARGET_PICO_IMX7D bool "pico-imx7d" @@ -83,6 +131,10 @@ config SYS_SOC source "board/compulab/cl-som-imx7/Kconfig" source "board/freescale/mx7dsabresd/Kconfig" +source "board/freescale/mx7d_12x12_lpddr3_val/Kconfig" +source "board/freescale/mx7d_12x12_ddr3_val/Kconfig" +source "board/freescale/mx7d_19x19_ddr3_val/Kconfig" +source "board/freescale/mx7d_19x19_lpddr3_val/Kconfig" source "board/novtech/meerkat96/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" diff --git a/arch/arm/mach-imx/mx7/Makefile b/arch/arm/mach-imx/mx7/Makefile index f1436e2d0d7..255503790d3 100644 --- a/arch/arm/mach-imx/mx7/Makefile +++ b/arch/arm/mach-imx/mx7/Makefile @@ -4,4 +4,5 @@ # obj-y := soc.o clock.o clock_slice.o ddr.o snvs.o +obj-$(CONFIG_IMX_TAMPER) += tamper.o obj-$(CONFIG_ARMV7_PSCI) += psci-mx7.o psci-suspend.o diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index fda25ba66a3..1d979bafc86 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP */ #include @@ -16,11 +17,13 @@ #include #include #include +#include +#include #include #include -#include #include #include +#include #define IOMUXC_GPR1 0x4 #define BM_IOMUXC_GPR1_IRQ 0x1000 @@ -125,7 +128,7 @@ static void isolate_resource(void) } #endif -#if defined(CONFIG_IMX_HAB) +#if defined(CONFIG_IMX_HAB) || defined(CONFIG_AVB_ATX) struct imx_sec_config_fuse_t const imx_sec_config_fuse = { .bank = 1, .word = 3, @@ -304,8 +307,43 @@ static void imx_gpcv2_init(void) udelay(65); } +static void set_epdc_qos(void) +{ + writel(0, REGS_QOS_BASE); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_BASE + 0x60); /* Enable all masters */ + writel(0, REGS_QOS_EPDC); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_PXP0); /* Disable clkgate & soft_reset */ + writel(0, REGS_QOS_PXP1); /* Disable clkgate & soft_reset */ + + writel(0x0f020722, REGS_QOS_EPDC + 0xd0); /* WR, init = 7 with red flag */ + writel(0x0f020722, REGS_QOS_EPDC + 0xe0); /* RD, init = 7 with red flag */ + + writel(1, REGS_QOS_PXP0); /* OT_CTRL_EN =1 */ + writel(1, REGS_QOS_PXP1); /* OT_CTRL_EN =1 */ + + writel(0x0f020222, REGS_QOS_PXP0 + 0x50); /* WR, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP1 + 0x50); /* WR, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP0 + 0x60); /* rD, init = 2 with red flag */ + writel(0x0f020222, REGS_QOS_PXP1 + 0x60); /* rD, init = 2 with red flag */ + writel(0x0f020422, REGS_QOS_PXP0 + 0x70); /* tOTAL, init = 4 with red flag */ + writel(0x0f020422, REGS_QOS_PXP1 + 0x70); /* TOTAL, init = 4 with red flag */ + + writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034); /* EPDC AW/AR CACHE ENABLE */ +} + +bool is_usb_boot(void) +{ + if (gd->flags & GD_FLG_ARCH_IMX_USB_BOOT) + return true; + + return false; +} + int arch_cpu_init(void) { + if (is_usbotg_boot_enabled()) + gd->flags |= GD_FLG_ARCH_IMX_USB_BOOT; + init_aips(); init_csu(); @@ -314,6 +352,8 @@ int arch_cpu_init(void) init_cpu_basic(); + set_epdc_qos(); + #if CONFIG_IS_ENABLED(IMX_RDC) isolate_resource(); #endif @@ -322,6 +362,8 @@ int arch_cpu_init(void) imx_gpcv2_init(); + configure_tzc380(); + return 0; } #else @@ -336,16 +378,19 @@ int arch_cpu_init(void) #ifdef CONFIG_ARCH_MISC_INIT int arch_misc_init(void) { + struct udevice *dev; + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG if (is_mx7d()) env_set("soc", "imx7d"); else env_set("soc", "imx7s"); #endif - -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif + uclass_find_first_device(UCLASS_MISC, &dev); + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } return 0; } @@ -408,6 +453,10 @@ void s_init(void) /* clock configuration. */ clock_init(); +#if defined(CONFIG_ANDROID_SUPPORT) + /* Enable RTC */ + writel(0x21, 0x30370038); +#endif return; } @@ -436,3 +485,30 @@ void reset_misc(void) #endif } +#ifdef CONFIG_IMX_TRUSTY_OS +#ifdef CONFIG_MX7D +void smp_set_core_boot_addr(unsigned long addr, int corenr) +{ + return; +} + +void smp_waitloop(unsigned previous_address) +{ + return; +} +#endif +#endif + +void reset_cpu(ulong addr) +{ + struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; + + /* Clear WDA to trigger WDOG_B immediately */ + writew((WCR_WDE | WCR_SRS), &wdog->wcr); + + while (1) { + /* + * spin for .5 seconds before reset + */ + } +} diff --git a/arch/arm/mach-imx/mx7/tamper.c b/arch/arm/mach-imx/mx7/tamper.c new file mode 100644 index 00000000000..5cec69040eb --- /dev/null +++ b/arch/arm/mach-imx/mx7/tamper.c @@ -0,0 +1,384 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void enable_active_tamper(unsigned int tx, unsigned int rx) +{ + int val; + + printf("start active tamper test on %d -> %d\n", tx, rx); + + /**************************** + * Configuring CAAM and SNVS * + ****************************/ + + /* Initialize power glitch detector register */ + val = 0x41736166; + writel(val, SNVS_LPPGDR); + + /* W1C PGD */ + val = readl(SNVS_LPSR) & 0x00000008; + writel(val, SNVS_LPSR); + + /* Programming ZMK via SW */ + writel(0x11110000, SNVS_LPZMKR0); + writel(0x22220000, SNVS_LPZMKR1); + writel(0x33330000, SNVS_LPZMKR2); + writel(0x44440000, SNVS_LPZMKR3); + writel(0x55550000, SNVS_LPZMKR4); + writel(0x66660000, SNVS_LPZMKR5); + writel(0x77770000, SNVS_LPZMKR6); + writel(0x88880000, SNVS_LPZMKR7); + + val = readl(SNVS_LPMKCR) | 0xa; + writel(val, SNVS_LPMKCR); + val = readl(SNVS_HPCOMR) | 0x1000; + writel(val, SNVS_HPCOMR); + + val = readl(SNVS_LPMKCR) | 0x10; + writel(val, SNVS_LPMKCR); + + val = readl(SNVS_HPSVSR); + + /* LP Security Violation is a non-fatal Violation */ + val = 0x40000000; + writel(val, SNVS_HPSVCR); + + /* Enable SRTC invalidation in case of security violation */ + val = readl(SNVS_LPCR); + val |= 0x11; + writel(val, SNVS_LPCR); + + /********************************* + * Configuring active tamper tx output * + *********************************/ + + /* Configure LFSR polynomial and seed for active tamper tx */ + val = AT5_POLYSEED; + writel(val, SNVS_LPAT1CR + (tx - 5) * 4); + + /* Enable active tamper tx external pad */ + val = readl(SNVS_LPATCTLR) | (1 << (tx - 5 + 16)); + writel(val, SNVS_LPATCTLR); + + /* Enable active tamper tx clk 16hz */ + val = readl(SNVS_LPATCLKR); + val &= ~(3 << (tx - 5) * 4); + writel(val, SNVS_LPATCLKR); + + /* Enable active tamper tx LFSR */ + val = readl(SNVS_LPATCTLR) | (1 << (tx - 5)); + writel(val, SNVS_LPATCTLR); + + /* Enable glitch filter for external tamper rx */ + if (rx < 2) { + val = readl(SNVS_LPTGFCR); + if (rx == 0) + val |= 0x800000; + else if (rx == 1) + val |= 0x80000000; + writel(val, SNVS_LPTGFCR); + } else if (rx < 6) { + val = readl(SNVS_LPTGF1CR); + val |= 1 << ((rx - 1) * 8 - 1); + writel(val, SNVS_LPTGF1CR); + } else { + val = readl(SNVS_LPTGF2CR); + val |= 1 << ((rx - 5) * 8 - 1); + writel(val, SNVS_LPTGF2CR); + } + + /* Route active tamper tx to external tamper rx */ + if (rx < 8) { + val = readl(SNVS_LPATRC1R); + val &= ~(0xf << (rx * 4)); + val |= ((tx - 4) << (rx * 4)); + writel(val, SNVS_LPATRC1R); + } else { + val = readl(SNVS_LPATRC2R); + val &= ~(0xf << ((rx - 8) * 4)); + val |= ((tx - 4) << ((rx - 8) * 4)); + writel(val, SNVS_LPATRC2R); + } + + /* Enable external tamper rx */ + if (rx < 2) { + val = readl(SNVS_LPTDCR); + if (rx == 0) + val |= 0x200; + else if (rx == 1) + val |= 0x400; + writel(val, SNVS_LPTDCR); + } else { + val = readl(SNVS_LPTDC2R); + val |= 1 << (rx - 2); + writel(val, SNVS_LPTDC2R); + } +} + +void enable_passive_tamper(unsigned int rx, unsigned int high) +{ + int val; + + printf("start passive tamper test on pin %d\n", rx); + + /**************************** + * Configuring CAAM and SNVS * + ****************************/ + + /* Initialize power glitch detector register */ + val = 0x41736166; + writel(val, SNVS_LPPGDR); + + /* W1C PGD */ + val = readl(SNVS_LPSR) & 0x00000008; + writel(val, SNVS_LPSR); + + /* Programming ZMK via SW */ + writel(0x11111111, SNVS_LPZMKR0); + writel(0x22222222, SNVS_LPZMKR1); + writel(0x33333333, SNVS_LPZMKR2); + writel(0x44444444, SNVS_LPZMKR3); + writel(0x55555555, SNVS_LPZMKR4); + writel(0x66666666, SNVS_LPZMKR5); + writel(0x77777777, SNVS_LPZMKR6); + writel(0x88888888, SNVS_LPZMKR7); + + val = readl(SNVS_LPMKCR) | 0xa; + writel(val, SNVS_LPMKCR); + val = readl(SNVS_HPCOMR) | 0x1000; + writel(val, SNVS_HPCOMR); + + val = readl(SNVS_LPMKCR) | 0x10; + writel(val, SNVS_LPMKCR); + + /* LP Security Violation is a non-fatal Violation */ + val = 0x40000000; + writel(val, SNVS_HPSVCR); + + /* Enable SRTC invalidation in case of security violation */ + val = readl(SNVS_LPCR); + val |= 0x11; + writel(val, SNVS_LPCR); + + /********************************* + * Configuring passive tamper rx * + *********************************/ + + /* Enable glitch filter for external tamper rx */ + if (rx < 2) { + val = readl(SNVS_LPTGFCR); + if (rx == 0) + val |= 0x800000; + else if (rx == 1) + val |= 0x80000000; + writel(val, SNVS_LPTGFCR); + } else if (rx < 6) { + val = readl(SNVS_LPTGF1CR); + val |= 1 << ((rx - 1) * 8 - 1); + writel(val, SNVS_LPTGF1CR); + } else { + val = readl(SNVS_LPTGF2CR); + val |= 1 << ((rx - 5) * 8 - 1); + writel(val, SNVS_LPTGF2CR); + } + + if (high == 1) { + /* Set external tampering rx polarity to high and enable tamper */ + if (rx < 2) { + val = readl(SNVS_LPTDCR); + if (rx == 0) + val |= 0x800; + else if (rx == 1) + val |= 0x1000; + writel(val, SNVS_LPTDCR); + } else { + val = readl(SNVS_LPTDC2R); + val |= 1 << (rx - 2 + 16); + writel(val, SNVS_LPTDC2R); + } + } + /* Enable external tamper rx */ + if (rx < 2) { + val = readl(SNVS_LPTDCR); + if (rx == 0) + val |= 0x200; + else if (rx == 1) + val |= 0x400; + writel(val, SNVS_LPTDCR); + } else { + val = readl(SNVS_LPTDC2R); + val |= 1 << (rx - 2); + writel(val, SNVS_LPTDC2R); + } +} + +void stop_tamper(int rx) +{ + int val; + + /* stop tamper */ + if (rx < 2) { + val = readl(SNVS_LPTDCR); + if (rx == 0) + val &= ~0x200; + else if (rx == 1) + val &= ~0x400; + writel(val, SNVS_LPTDCR); + } else { + val = readl(SNVS_LPTDC2R); + val &= ~(1 << (rx - 2)); + writel(val, SNVS_LPTDC2R); + } + + /* clear tamper status */ + if (rx < 2) { + val = readl(SNVS_LPSR); + val |= 1 << (rx + 9); + writel(val, SNVS_LPSR); + } else if (rx < 10) { + val = readl(SNVS_LPTDSR); + val |= 1 << (rx - 2); + writel(val, SNVS_LPTDSR); + } +} + +static void get_tamper_status(void) +{ + unsigned int lpsr, lptdsr, hpsr, ssm; + + lpsr = readl(SNVS_LPSR); + lptdsr = readl(SNVS_LPTDSR); + hpsr = readl(SNVS_HPSR); + ssm = (hpsr & 0xf00) >> 8; + + if (lpsr & (1 << 9)) + printf("External Tampering 0 Detected\n"); + if (lpsr & (1 << 10)) + printf("External Tampering 1 Detected\n"); + if (lptdsr & (1 << 0)) + printf("External Tampering 2 Detected\n"); + if (lptdsr & (1 << 1)) + printf("External Tampering 3 Detected\n"); + if (lptdsr & (1 << 2)) + printf("External Tampering 4 Detected\n"); + if (lptdsr & (1 << 3)) + printf("External Tampering 5 Detected\n"); + if (lptdsr & (1 << 4)) + printf("External Tampering 6 Detected\n"); + if (lptdsr & (1 << 5)) + printf("External Tampering 7 Detected\n"); + if (lptdsr & (1 << 6)) + printf("External Tampering 8 Detected\n"); + if (lptdsr & (1 << 7)) + printf("External Tampering 9 Detected\n"); + if (!(lpsr & (3 << 9)) && !(lptdsr & 0xff)) + printf("No External Tampering Detected\n"); + + if (hpsr & 0x80000000) + printf("Zeroizable Master Key is clear\n"); + else + printf("Zeroizable Master Key is not zero\n"); + + if (ssm == 0) + printf("System Security Monitor State: Init\n"); + else if (ssm == 0x8) + printf("System Security Monitor State: Init Intermediate\n"); + else if (ssm == 0x9) + printf("System Security Monitor State: Check\n"); + else if (ssm == 0xb) + printf("System Security Monitor State: Non-Secure\n"); + else if (ssm == 0xd) + printf("System Security Monitor State: Trusted\n"); + else if (ssm == 0xf) + printf("System Security Monitor State: Secure\n"); + else if (ssm == 0x3) + printf("System Security Monitor State: Soft Fail\n"); + else if (ssm == 0x1) + printf("System Security Monitor State: Hard Fail\n"); + else + printf("System Security Monitor State: 0x%x\n", ssm); +} + +static void clear_tamper_warning(void) +{ + unsigned int lpsr, lptdsr; + + lpsr = readl(SNVS_LPSR); + lptdsr = readl(SNVS_LPTDSR); + + writel(lpsr, SNVS_LPSR); + writel(lptdsr, SNVS_LPTDSR); +} + +static int do_tamper(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + const char *op = argc >= 2 ? argv[1] : NULL; + unsigned int tx, rx, high; + + if (argc < 2) + return CMD_RET_USAGE; + + if (!strcmp(op, "active")) { + if (argc < 4) + return CMD_RET_USAGE; + + tx = simple_strtoul(argv[2], NULL, 16); + rx = simple_strtoul(argv[3], NULL, 16); + if ((tx > 9) || (tx < 5)) + return CMD_RET_USAGE; + if ((rx > 9) || (rx == tx)) + return CMD_RET_USAGE; + + enable_active_tamper(tx, rx); + + } else if (!strcmp(op, "passive")) { + if (argc < 4) + return CMD_RET_USAGE; + + rx = simple_strtoul(argv[2], NULL, 16); + if (rx > 9) + return CMD_RET_USAGE; + + high = simple_strtoul(argv[3], NULL, 16); + if (high != 0) + high = 1; + enable_passive_tamper(rx, high); + + } else if (!strcmp(op, "status")) { + get_tamper_status(); + } else if (!strcmp(op, "clear")) { + clear_tamper_warning(); + } else if (!strcmp(op, "stop")) { + if (argc < 3) + return CMD_RET_USAGE; + + rx = simple_strtoul(argv[2], NULL, 16); + if (rx > 9) + return CMD_RET_USAGE; + stop_tamper(rx); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + imx_tamper, CONFIG_SYS_MAXARGS, 0, do_tamper, + "imx tamper command for setting for test", + "active - tx is active tamper pin from 9 ~ 5, \n" + " rx pin is from 9 ~ 0 and should not equal to tx pin\n" + "passive - rx is passive tamper pin from 9 ~ 0, \n" + " high: 1 - high assert, 0 - low assert\n" + "status - Get tamper status\n" + "clear - clear tamper warning\n" + "stop rx - rx is tamper pin to stop\n" + ); diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig index 6680f856c5b..45ccffa903d 100644 --- a/arch/arm/mach-imx/mx7ulp/Kconfig +++ b/arch/arm/mach-imx/mx7ulp/Kconfig @@ -9,8 +9,15 @@ config LDO_ENABLED_MODE Select this option to enable the PMC1 LDO. config MX7ULP + select HAS_CAAM bool +config IMX_M4_BIND + bool "Bind ULP M4 image to final u-boot" + help + Select this to bind a ULP M4 image to final u-boot image + User needs put the M4 image ulp_m4.bin under u-boot directory + choice prompt "MX7ULP board select" optional @@ -19,15 +26,29 @@ config TARGET_MX7ULP_COM bool "Support MX7ULP COM board" select MX7ULP select SYS_ARCH_TIMER +config TARGET_MX7ULP_10X10_VAL + bool "Support mx7ulp 10x10 validation board" + select SYS_ARCH_TIMER + select MX7ULP + +config TARGET_MX7ULP_14X14_VAL + bool "Support mx7ulp 14x14 validation board" + select SYS_ARCH_TIMER + select MX7ULP config TARGET_MX7ULP_EVK bool "Support mx7ulp EVK board" select MX7ULP select SYS_ARCH_TIMER + select FSL_CAAM + select FSL_BLOB + select MISC + select ARCH_MISC_INIT endchoice source "board/ea/mx7ulp_com/Kconfig" +source "board/freescale/mx7ulp_val/Kconfig" source "board/freescale/mx7ulp_evk/Kconfig" endif diff --git a/arch/arm/mach-imx/mx7ulp/Makefile b/arch/arm/mach-imx/mx7ulp/Makefile index adb8d7aecb0..1b131dd28e0 100644 --- a/arch/arm/mach-imx/mx7ulp/Makefile +++ b/arch/arm/mach-imx/mx7ulp/Makefile @@ -4,3 +4,4 @@ # obj-y := soc.o clock.o iomux.o pcc.o scg.o +obj-$(CONFIG_IMX_M4_BIND) += piggy_m4.o diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 6191153917f..e50d84bff8b 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP */ #include @@ -115,6 +116,42 @@ u32 imx_get_i2cclk(unsigned i2c_num) } #endif +#ifdef CONFIG_FSL_LPSPI +int enable_lpspi_clk(unsigned char enable, unsigned spi_num) +{ + /* Set parent to FIRC DIV2 clock */ + const enum pcc_clk lpspi_pcc_clks[] = { + PER_CLK_LPSPI2, + PER_CLK_LPSPI3, + }; + + if (spi_num < 2 || spi_num > 3) + return -EINVAL; + + if (enable) { + pcc_clock_enable(lpspi_pcc_clks[spi_num - 2], false); + pcc_clock_sel(lpspi_pcc_clks[spi_num - 2], SCG_FIRC_DIV2_CLK); + pcc_clock_enable(lpspi_pcc_clks[spi_num - 2], true); + } else { + pcc_clock_enable(lpspi_pcc_clks[spi_num - 2], false); + } + return 0; +} + +u32 imx_get_spiclk(unsigned spi_num) +{ + const enum pcc_clk lpspi_pcc_clks[] = { + PER_CLK_LPSPI2, + PER_CLK_LPSPI3, + }; + + if (spi_num < 2 || spi_num > 3) + return 0; + + return pcc_clock_get_rate(lpspi_pcc_clks[spi_num - 2]); +} +#endif + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -128,6 +165,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_ipg_clk(); case MXC_I2C_CLK: return pcc_clock_get_rate(PER_CLK_LPI2C4); + case MXC_LPSPI_CLK: + return pcc_clock_get_rate(PER_CLK_LPSPI3); case MXC_UART_CLK: return get_lpuart_clk(); case MXC_ESDHC_CLK: @@ -151,8 +190,8 @@ void init_clk_usdhc(u32 index) /*Disable the clock before configure it */ pcc_clock_enable(PER_CLK_USDHC0, false); - /* 158MHz / 1 = 158MHz */ - pcc_clock_sel(PER_CLK_USDHC0, SCG_NIC1_CLK); + /* 352.8MHz / 1 = 352.8MHz */ + pcc_clock_sel(PER_CLK_USDHC0, SCG_APLL_PFD1_CLK); pcc_clock_div_config(PER_CLK_USDHC0, false, 1); pcc_clock_enable(PER_CLK_USDHC0, true); break; @@ -160,9 +199,9 @@ void init_clk_usdhc(u32 index) /*Disable the clock before configure it */ pcc_clock_enable(PER_CLK_USDHC1, false); - /* 158MHz / 1 = 158MHz */ - pcc_clock_sel(PER_CLK_USDHC1, SCG_NIC1_CLK); - pcc_clock_div_config(PER_CLK_USDHC1, false, 1); + /* 352.8MHz / 2 = 176.4MHz */ + pcc_clock_sel(PER_CLK_USDHC1, SCG_APLL_PFD1_CLK); + pcc_clock_div_config(PER_CLK_USDHC1, false, 2); pcc_clock_enable(PER_CLK_USDHC1, true); break; default: @@ -305,8 +344,8 @@ void clock_init(void) scg_a7_init_core_clk(); - /* APLL PFD1 = 270Mhz, PFD2=345.6Mhz, PFD3=800Mhz */ - scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 35); + /* APLL PFD1 = 352.8Mhz, PFD2=340.2Mhz, PFD3=793.8Mhz */ + scg_enable_pll_pfd(SCG_APLL_PFD1_CLK, 27); scg_enable_pll_pfd(SCG_APLL_PFD2_CLK, 28); scg_enable_pll_pfd(SCG_APLL_PFD3_CLK, 12); @@ -327,6 +366,88 @@ void hab_caam_clock_enable(unsigned char enable) } #endif +void enable_mipi_dsi_clk(unsigned char enable) +{ + if (enable) { + pcc_clock_enable(PER_CLK_DSI, false); + + /* mipi dsi escape clock range is 40-80Mhz, we expect to set it to about 60 Mhz + * To avoid PCD issue, we select parent clock with lowest frequency + * NIC1_CLK = 1584000khz, frac = 1, div = 5, output = 63.360Mhz + */ + pcc_clock_sel(PER_CLK_DSI, SCG_NIC1_CLK); + pcc_clock_div_config(PER_CLK_DSI, 1, 5); + + pcc_clock_enable(PER_CLK_DSI, true); + } else { + pcc_clock_enable(PER_CLK_DSI, false); + } +} + +void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq_in_khz) +{ + /* Scan the parent clock to find best fit clock, whose generate actual frequence <= freq + * Otherwise, the higher actual freq may introduce some problem + * 1. The real frequency exceeds max framerate that screen supports + * 2. The DSI PHY clock depends on the lcdif clock, so the higher lcdif clock may violate + * DSI PHY clock requirement + */ + u8 pcd, best_pcd = 0; + u32 parent, frac, rate, parent_rate; + u32 best_parent = 0, best_frac = 0, best = 0; + + static enum scg_clk clksrc_plat[] = { + SCG_NIC1_BUS_CLK, + SCG_NIC1_CLK, + SCG_DDR_CLK, + SCG_APLL_PFD2_CLK, + SCG_APLL_PFD1_CLK, + SCG_APLL_PFD0_CLK, + USB_PLL_OUT, + }; + + pcc_clock_enable(PER_CLK_LCDIF, false); + + for (parent = 0; parent < ARRAY_SIZE(clksrc_plat); parent++) { + parent_rate = scg_clk_get_rate(clksrc_plat[parent]); + if (!parent_rate) + continue; + + parent_rate = parent_rate / 1000; /* Change to khz*/ + + for (pcd = 0; pcd < 8; pcd++) { + for (frac = 0; frac < 2; frac++) { + if (pcd == 0 && frac == 1) + continue; + + rate = parent_rate * (frac + 1) / (pcd + 1); + if (rate > freq_in_khz) + continue; + + if (best == 0 || rate > best) { + best = rate; + best_parent = parent; + best_frac = frac; + best_pcd = pcd; + } + } + } + } + + if (best == 0) { + printf("Can't find parent clock for LCDIF, target freq: %u\n", freq_in_khz); + return; + } + + debug("LCD target rate %ukhz, best rate %ukhz, frac %u, pcd %u, best_parent %u\n", + freq_in_khz, best, best_frac, best_pcd, best_parent); + + pcc_clock_sel(PER_CLK_LCDIF, clksrc_plat[best_parent]); + pcc_clock_div_config(PER_CLK_LCDIF, best_frac, best_pcd + 1); + pcc_clock_enable(PER_CLK_LCDIF, true); +} + + #ifndef CONFIG_SPL_BUILD /* * Dump some core clockes. diff --git a/arch/arm/mach-imx/mx7ulp/piggy_m4.S b/arch/arm/mach-imx/mx7ulp/piggy_m4.S new file mode 100644 index 00000000000..b33e8422ea6 --- /dev/null +++ b/arch/arm/mach-imx/mx7ulp/piggy_m4.S @@ -0,0 +1,2 @@ + .section .firmware_image,#alloc + .incbin "ulp_m4.bin" diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c index 4c066557c1c..275311d51ff 100644 --- a/arch/arm/mach-imx/mx7ulp/scg.c +++ b/arch/arm/mach-imx/mx7ulp/scg.c @@ -715,6 +715,61 @@ int scg_enable_pll_pfd(enum scg_clk clk, u32 frac) return 0; } +int scg_disable_pll_pfd(enum scg_clk clk) +{ + u32 reg; + u32 gate; + u32 addr; + + switch (clk) { + case SCG_SPLL_PFD0_CLK: + case SCG_APLL_PFD0_CLK: + gate = SCG_PLL_PFD0_GATE_MASK; + + if (clk == SCG_SPLL_PFD0_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD1_CLK: + case SCG_APLL_PFD1_CLK: + gate = SCG_PLL_PFD1_GATE_MASK; + + if (clk == SCG_SPLL_PFD1_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD2_CLK: + case SCG_APLL_PFD2_CLK: + gate = SCG_PLL_PFD2_GATE_MASK; + + if (clk == SCG_SPLL_PFD2_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + case SCG_SPLL_PFD3_CLK: + case SCG_APLL_PFD3_CLK: + gate = SCG_PLL_PFD3_GATE_MASK; + + if (clk == SCG_SPLL_PFD3_CLK) + addr = (u32)(&scg1_regs->spllpfd); + else + addr = (u32)(&scg1_regs->apllpfd); + break; + default: + return -EINVAL; + } + + /* Gate the PFD */ + reg = readl(addr); + reg |= gate; + writel(reg, addr); + + return 0; +} + #define SIM_MISC_CTRL0_USB_PLL_EN_MASK (0x1 << 2) int scg_enable_usb_pll(bool usb_control) { diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 8dd6b4d40e7..e9bb048121e 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP */ #include @@ -10,10 +11,15 @@ #include #include #include +#include #include #include #include #include +#include +#include +#include +#include #define PMC0_BASE_ADDR 0x410a1000 #define PMC0_CTRL 0x28 @@ -46,7 +52,22 @@ u32 get_cpu_rev(void) /* Check the ROM version for cpu revision */ u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR); - return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF); + rom_version &= 0xFF; + if (rom_version == CHIP_REV_1_0) { + return (MXC_CPU_MX7ULP << 12) | (rom_version); + } else { + /* Check the "Mirror of JTAG ID" SIM register since RevB */ + uint32_t id; + id = readl(SIM0_RBASE + 0x8c); + id = (id >> 28) & 0xFF; + + /* Revision Number ULP1 Version + * 0000 A0 + * 0001 B0 + * 0010 B1 + */ + return (MXC_CPU_MX7ULP << 12) | (CHIP_REV_2_0 + (id - 1)); + } } #ifdef CONFIG_REVISION_TAG @@ -74,10 +95,62 @@ enum bt_mode get_boot_mode(void) return LOW_POWER_BOOT; } +#ifdef CONFIG_IMX_M4_BIND +char __firmware_image_start[0] __attribute__((section(".__firmware_image_start"))); +char __firmware_image_end[0] __attribute__((section(".__firmware_image_end"))); + +int mcore_early_load_and_boot(void) +{ + u32 *src_addr = (u32 *)&__firmware_image_start; + u32 *dest_addr = (u32 *)TCML_BASE; /*TCML*/ + u32 image_size = SZ_128K + SZ_64K; /* 192 KB*/ + u32 pc = 0, tag = 0; + + memcpy(dest_addr, src_addr, image_size); + + /* Set GP register to tell the M4 rom the image entry */ + /* We assume the M4 image has IVT head and padding which + * should be same as the one programmed into QSPI flash + */ + tag = *(dest_addr + 1024); + if (tag != 0x402000d1 && tag !=0x412000d1) + return -1; + + pc = *(dest_addr + 1025); + + writel(pc, SIM0_RBASE + 0x70); /*GP7*/ + + return 0; +} +#endif + int arch_cpu_init(void) { +#ifdef CONFIG_IMX_M4_BIND + int ret; + if (get_boot_mode() == SINGLE_BOOT) { + ret = mcore_early_load_and_boot(); + if (ret) + puts("Invalid M4 image, boot failed\n"); + } +#endif + + return 0; +} + +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } return 0; } +#endif #ifdef CONFIG_BOARD_POSTCLK_INIT int board_postclk_init(void) @@ -93,14 +166,29 @@ int board_postclk_init(void) static void disable_wdog(u32 wdog_base) { - writel(UNLOCK_WORD0, (wdog_base + 0x04)); - writel(UNLOCK_WORD1, (wdog_base + 0x04)); + u32 val_cs = readl(wdog_base + 0x00); + + if (!(val_cs & 0x80)) + return; + + dmb(); + __raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ + __raw_writel(REFRESH_WORD1, (wdog_base + 0x04)); + dmb(); + + if (!(val_cs & 800)) { + dmb(); + __raw_writel(UNLOCK_WORD0, (wdog_base + 0x04)); + __raw_writel(UNLOCK_WORD1, (wdog_base + 0x04)); + dmb(); + + while (!(readl(wdog_base + 0x00) & 0x800)); + } writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */ writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */ writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */ - writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */ - writel(REFRESH_WORD1, (wdog_base + 0x04)); + while (!(readl(wdog_base + 0x00) & 0x400)); } void init_wdog(void) @@ -187,6 +275,11 @@ void s_init(void) if (soc_rev() < CHIP_REV_2_0) { /* enable dumb pmic */ writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR); + +#if defined(CONFIG_ANDROID_SUPPORT) + /* Enable RTC */ + writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_SRTC_ENV), SNVS_LP_LPCR); +#endif } #if defined(CONFIG_LDO_ENABLED_MODE) @@ -218,7 +311,7 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + printf("CPU: i.MX%s rev%d.%d at %d MHz\n", get_imx_type((cpurev & 0xFF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); @@ -236,6 +329,10 @@ int print_cpuinfo(void) case SINGLE_BOOT: default: printf("Single boot\n"); +#ifdef CONFIG_IMX_M4_BIND + if (readl(SIM0_RBASE + 0x70)) + printf("M4 start at 0x%x\n", readl(SIM0_RBASE + 0x70)); +#endif break; } @@ -276,7 +373,12 @@ static char *get_reset_cause(char *ret) srs = readl(reg_srs); cause1 = readl(reg_ssrs); +#ifndef CONFIG_ANDROID_BOOT_IMAGE + /* We will read the ssrs states later for android so we don't + * clear the states here. + */ writel(cause1, reg_ssrs); +#endif reset_cause = cause1; @@ -316,10 +418,28 @@ static char *get_reset_cause(char *ret) return ret; } +#ifdef CONFIG_ANDROID_BOOT_IMAGE +void get_reboot_reason(char *ret) +{ + u32 *reg_ssrs = (u32 *)(SRC_BASE_ADDR + 0x28); + + get_reset_cause(ret); + /* clear the ssrs here, its state has been recorded in reset_cause */ + writel(reset_cause, reg_ssrs); +} +#endif + +void arch_preboot_os(void) +{ + scg_disable_pll_pfd(SCG_APLL_PFD1_CLK); + scg_disable_pll_pfd(SCG_APLL_PFD2_CLK); + scg_disable_pll_pfd(SCG_APLL_PFD3_CLK); +} + #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return devno; } int mmc_get_env_dev(void) @@ -363,3 +483,23 @@ enum boot_device get_boot_device(void) return boot_dev; } + +bool is_usb_boot(void) +{ + return get_boot_device() == USB_BOOT; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[1]; + struct fuse_bank1_regs *fuse = + (struct fuse_bank1_regs *)bank->fuse_regs; + serialnr->low = (fuse->cfg0 & 0xFFFF) + ((fuse->cfg1 & 0xFFFF) << 16); + serialnr->high = (fuse->cfg2 & 0xFFFF) + ((fuse->cfg3 & 0xFFFF) << 16); +} +#endif /*CONFIG_SERIAL_TAG*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/arch/arm/mach-imx/priblob.c b/arch/arm/mach-imx/priblob.c new file mode 100644 index 00000000000..7e2deb739df --- /dev/null +++ b/arch/arm/mach-imx/priblob.c @@ -0,0 +1,32 @@ +/* + * Copyright 2018 NXP + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Boot command to get and set the PRIBLOB bitfield form the SCFGR register + * of the CAAM IP. It is recommended to set this bitfield to 3 once your + * encrypted boot image is ready, to prevent the generation of blobs usable + * to decrypt an encrypted boot image. + */ +#include +#include +#include +#include "../drivers/crypto/fsl_caam_internal.h" + +int do_priblob_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + writel((readl(CAAM_SCFGR) & 0xFFFFFFFC) | 3, CAAM_SCFGR); + printf("New priblob setting = 0x%x\n", readl(CAAM_SCFGR) & 0x3); + + return 0; +} + +U_BOOT_CMD( + set_priblob_bitfield, 1, 0, do_priblob_write, + "Set the PRIBLOB bitfield to 3", + "\n" + " - Write 3 in PRIBLOB bitfield of SCFGR regiter of CAAM IP.\n" + " Prevent the generation of blobs usable to decrypt an\n" + " encrypted boot image." +); diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 36033d611c9..9ca152a943e 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -20,12 +20,49 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; __weak int spl_board_boot_device(enum boot_device boot_dev_spl) { - return 0; + switch (boot_dev_spl) { +#if defined(CONFIG_MX7) + case SD1_BOOT: + case MMC1_BOOT: + case SD2_BOOT: + case MMC2_BOOT: + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC1; +#elif defined(CONFIG_IMX8) + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + return BOOT_DEVICE_MMC2_2; + case SD3_BOOT: + return BOOT_DEVICE_MMC1; + case FLEXSPI_BOOT: + return BOOT_DEVICE_SPI; +#elif defined(CONFIG_IMX8M) + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; +#endif + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case SPI_NOR_BOOT: + return BOOT_DEVICE_SPI; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } } #if defined(CONFIG_MX6) @@ -140,47 +177,7 @@ u32 spl_boot_device(void) enum boot_device boot_device_spl = get_boot_device(); - if (IS_ENABLED(CONFIG_IMX8MM) || IS_ENABLED(CONFIG_IMX8MN) || - IS_ENABLED(CONFIG_IMX8MP)) - return spl_board_boot_device(boot_device_spl); - - switch (boot_device_spl) { -#if defined(CONFIG_MX7) - case SD1_BOOT: - case MMC1_BOOT: - case SD2_BOOT: - case MMC2_BOOT: - case SD3_BOOT: - case MMC3_BOOT: - return BOOT_DEVICE_MMC1; -#elif defined(CONFIG_IMX8) - case MMC1_BOOT: - return BOOT_DEVICE_MMC1; - case SD2_BOOT: - return BOOT_DEVICE_MMC2_2; - case SD3_BOOT: - return BOOT_DEVICE_MMC1; - case FLEXSPI_BOOT: - return BOOT_DEVICE_SPI; -#elif defined(CONFIG_IMX8M) - case SD1_BOOT: - case MMC1_BOOT: - return BOOT_DEVICE_MMC1; - case SD2_BOOT: - case MMC2_BOOT: - return BOOT_DEVICE_MMC2; -#endif - case NAND_BOOT: - return BOOT_DEVICE_NAND; - case SPI_NOR_BOOT: - return BOOT_DEVICE_SPI; - case QSPI_BOOT: - return BOOT_DEVICE_NOR; - case USB_BOOT: - return BOOT_DEVICE_USB; - default: - return BOOT_DEVICE_NONE; - } + return spl_board_boot_device(boot_device_spl); } #endif /* CONFIG_MX7 || CONFIG_IMX8M || CONFIG_IMX8 */ @@ -334,6 +331,20 @@ void board_spl_fit_post_load(const void *fit) } #endif +void* board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + int align_len = ARCH_DMA_MINALIGN - 1; + + /* Some devices like SDP, NOR, NAND, SPI are using bl_len =1, so their fit address + * is different with SD/MMC, this cause mismatch with signed address. Thus, adjust + * the bl_len to align with SD/MMC. + */ + if (bl_len < 512) + bl_len = 512; + + return (void *)((CONFIG_SYS_TEXT_BASE - fit_size - bl_len - + align_len) & ~align_len); +} #endif #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) @@ -345,3 +356,13 @@ int dram_init_banksize(void) return 0; } #endif + +#ifdef CONFIG_IMX_TRUSTY_OS +int check_rpmb_blob(struct mmc *mmc); + +int mmc_image_load_late(struct mmc *mmc) +{ + /* Check the rpmb key blob for trusty enabled platfrom. */ + return check_rpmb_blob(mmc); +} +#endif diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 9f4d95982e5..fd25df31b60 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -148,6 +148,10 @@ static ulong get_fit_image_size(void *fit) spl_load_info.read = spl_ram_load_read; spl_load_info.priv = &last; + /* We call load_simple_fit is just to get total size, the image is not downloaded, + * so should bypass authentication + */ + spl_image.flags = SPL_FIT_BYPASS_POST_LOAD; spl_load_simple_fit(&spl_image, &spl_load_info, (uintptr_t)fit, fit); diff --git a/arch/arm/mach-imx/timer.c b/arch/arm/mach-imx/timer.c index fcd45f09f18..990fa163fc1 100644 --- a/arch/arm/mach-imx/timer.c +++ b/arch/arm/mach-imx/timer.c @@ -3,7 +3,8 @@ * (C) Copyright 2007 * Sascha Hauer, Pengutronix * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * (C) Copyright 2009-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #include diff --git a/arch/arm/mach-imx/trusty.S b/arch/arm/mach-imx/trusty.S new file mode 100644 index 00000000000..2ca9b3c83ad --- /dev/null +++ b/arch/arm/mach-imx/trusty.S @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2009-2016 Freescale Semiconductor, Inc. + * + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +_regs_save: + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + +#ifdef CONFIG_IMX_TRUSTY_OS +ENTRY(trusty_os_init) + isb + + /* Save current registers */ + mov ip, r0 + adr r0, _regs_save + str ip, [r0] + add r0, r0, #4 @ Get _regs_save from instruction offset + + str sp, [r0] + add r0, r0, #4 + + stmia r0!, {r1-r12} @ Save r1 - r12 + + str lr, [r0] + adr lr, end_init_tee @ save return address to lr + + dsb + + ldr r1, =TRUSTY_OS_ENTRY + ldr r0, =TRUSTY_OS_RAM_SIZE + movs pc, r1 @ Go to TEE codes +end_init_tee: + /* Restore saved registers */ + adr lr, _regs_save + ldr r0, [lr] + add lr, lr, #4 + + ldr sp, [lr] + add lr, lr, #4 + + ldmfd lr!, {r1-r12} + ldr lr, [lr] + + dsb + + bx lr +ENDPROC(trusty_os_init) +#endif diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c index 1bc9b7cc7e1..177f1713497 100644 --- a/arch/arm/mach-imx/video.c +++ b/arch/arm/mach-imx/video.c @@ -1,4 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + */ #include #include @@ -44,8 +48,14 @@ int board_video_skip(void) } if (i < display_count) { +#if defined(CONFIG_VIDEO_IPUV3) ret = ipuv3_fb_init(&displays[i].mode, displays[i].di ? 1 : 0, displays[i].pixfmt); +#elif defined(CONFIG_VIDEO_MXS) + ret = mxs_lcd_panel_setup(displays[i].mode, + displays[i].pixfmt, + displays[i].bus); +#endif if (!ret) { if (displays[i].enable) displays[i].enable(displays + i); diff --git a/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi b/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi index 889c8d450e0..65bb8a4b0b6 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi @@ -30,7 +30,7 @@ fman@500000 { pcsphy-handle = <&pcsphy14>; }; - mdio@f1000 { + mdio@5f1000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi index 2e456983372..eb39d29b39f 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi @@ -30,7 +30,7 @@ fman@500000 { pcsphy-handle = <&pcsphy15>; }; - mdio@f3000 { + mdio@5f3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi index b4ff19bf495..2f2209dbc9b 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy8>; }; - mdio@e1000 { + mdio@5e1000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi index 239c56ad1f6..11653c58b5f 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy9>; }; - mdio@e3000 { + mdio@5e3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi index 6e2bb009d9a..ae27c7bc6df 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy10>; }; - mdio@e5000 { + mdio@5e5000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi index 29dd94ba749..55ae5499176 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy11>; }; - mdio@e7000 { + mdio@5e7000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi index a5b49358270..833cf3e23d8 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy12>; }; - mdio@e9000 { + mdio@5e9000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi index 486c84bf981..81da55dfbe2 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy13>; }; - mdio@eb000 { + mdio@5eb000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1.dtsi index d8609c3ecfd..9efcf26c4ab 100644 --- a/arch/powerpc/dts/qoriq-fman3-1.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1.dtsi @@ -61,14 +61,14 @@ fman1: fman@500000 { reg = <0x87000 0x1000>; }; - mdio1: mdio@fc000 { + mdio1: mdio@5fc000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; reg = <0xfc000 0x1000>; }; - mdio@fd000 { + mdio@5fd000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts index 3584c06aa8d..5e9fab7a105 100644 --- a/arch/powerpc/dts/t1042d4rdb.dts +++ b/arch/powerpc/dts/t1042d4rdb.dts @@ -3,7 +3,7 @@ * T1042D4RDB Device Tree Source * * Copyright 2013 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ /include/ "t104x.dtsi" @@ -20,6 +20,57 @@ }; }; +&soc { + fman0: fman@400000 { + ethernet@e0000 { + phy-handle = <&phy_sgmii_0>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&phy_sgmii_1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&phy_sgmii_2>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&phy_rgmii_0>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&phy_rgmii_1>; + phy-connection-type = "rgmii"; + }; + + mdio0: mdio@fc000 { + phy_sgmii_0: ethernet-phy@2 { + reg = <0x02>; + }; + + phy_sgmii_1: ethernet-phy@3 { + reg = <0x03>; + }; + + phy_sgmii_2: ethernet-phy@1 { + reg = <0x01>; + }; + + phy_rgmii_0: ethernet-phy@4 { + reg = <0x04>; + }; + + phy_rgmii_1: ethernet-phy@5 { + reg = <0x05>; + }; + }; + }; +}; + &espi0 { status = "okay"; flash@0 { @@ -30,3 +81,5 @@ spi-max-frequency = <10000000>; /* input clock */ }; }; + +/include/ "t1042si-post.dtsi" diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi new file mode 100644 index 00000000000..5c60944e607 --- /dev/null +++ b/arch/powerpc/dts/t1042si-post.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * T1042 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 - 2014 Freescale Semiconductor Inc. + * Copyright 2021 NXP + * + */ +&soc { +/include/ "qoriq-clockgen2.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" + +/include/ "qoriq-fman3l-0.dtsi" +/include/ "qoriq-fman3-0-1g-0.dtsi" +/include/ "qoriq-fman3-0-1g-1.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-1g-4.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + mdio@fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@fd000 { + status = "disabled"; + }; + }; +}; diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts index 74bbb20e2a1..25f8c978c6d 100644 --- a/arch/powerpc/dts/t2080rdb.dts +++ b/arch/powerpc/dts/t2080rdb.dts @@ -3,7 +3,7 @@ * T2080RDB Device Tree Source * * Copyright 2013 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ /include/ "t2080.dtsi" @@ -20,6 +20,71 @@ }; }; +&soc { + fman@400000 { + ethernet@e0000 { + phy-handle = <&xg_aq1202_phy3>; + phy-connection-type = "xgmii"; + }; + + ethernet@e2000 { + phy-handle = <&xg_aq1202_phy4>; + phy-connection-type = "xgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + }; + + ethernet@f0000 { + phy-handle = <&xg_cs4315_phy2>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { + phy-handle = <&xg_cs4315_phy1>; + phy-connection-type = "xgmii"; + }; + + mdio@fc000 { + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + mdio@fd000 { + xg_cs4315_phy1: ethernet-phy@c { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0xc>; + }; + + xg_cs4315_phy2: ethernet-phy@d { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0xd>; + }; + + xg_aq1202_phy3: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + xg_aq1202_phy4: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + }; + }; +}; + &espi0 { status = "okay"; flash@0 { @@ -38,3 +103,5 @@ reg = <0x68>; }; }; + +/include/ "t2080si-post.dtsi" diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi new file mode 100644 index 00000000000..d8ef579cb7c --- /dev/null +++ b/arch/powerpc/dts/t2080si-post.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * T2080 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2021 NXP + * + */ +&soc { + +/include/ "qoriq-clockgen2.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" + +/include/ "qoriq-fman3-0.dtsi" +/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi" +/include/ "qoriq-fman3-0-10g-1-best-effort.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-10g-0.dtsi" +/include/ "qoriq-fman3-0-10g-1.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet6: ethernet@f0000 { + }; + + enet7: ethernet@f2000 { + }; + + mdio@fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@fd000 { + interrupts = <101 1 0 0>; + }; + }; +}; diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts index 635065a0368..b3251e330de 100644 --- a/arch/powerpc/dts/t4240rdb.dts +++ b/arch/powerpc/dts/t4240rdb.dts @@ -3,7 +3,7 @@ * T4240RDB Device Tree Source * * Copyright 2013 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ /include/ "t4240.dtsi" @@ -20,6 +20,144 @@ }; }; +&soc { + fman@400000 { + ethernet@e0000 { + phy-handle = <&sgmiiphy21>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmiiphy22>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&sgmiiphy23>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&sgmiiphy24>; + phy-connection-type = "sgmii"; + }; + + ethernet@e8000 { + status = "disabled"; + }; + + ethernet@ea000 { + status = "disabled"; + }; + + ethernet@f0000 { + phy-handle = <&xfiphy1>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { + phy-handle = <&xfiphy2>; + phy-connection-type = "xgmii"; + }; + }; + + fman@500000 { + ethernet@e0000 { + phy-handle = <&sgmiiphy41>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmiiphy42>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&sgmiiphy43>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&sgmiiphy44>; + phy-connection-type = "sgmii"; + }; + + ethernet@e8000 { + status = "disabled"; + }; + + ethernet@ea000 { + status = "disabled"; + }; + + ethernet@f0000 { + phy-handle = <&xfiphy3>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { + phy-handle = <&xfiphy4>; + phy-connection-type = "xgmii"; + }; + + mdio@5fc000 { + sgmiiphy21: ethernet-phy@0 { + reg = <0x0>; + }; + + sgmiiphy22: ethernet-phy@1 { + reg = <0x1>; + }; + + sgmiiphy23: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmiiphy24: ethernet-phy@3 { + reg = <0x3>; + }; + + sgmiiphy41: ethernet-phy@4 { + reg = <0x4>; + }; + + sgmiiphy42: ethernet-phy@5 { + reg = <0x5>; + }; + + sgmiiphy43: ethernet-phy@6 { + reg = <0x6>; + }; + + sgmiiphy44: ethernet-phy@7 { + reg = <0x7>; + }; + }; + + mdio@5fd000 { + xfiphy1: ethernet-phy@10 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x10>; + }; + + xfiphy2: ethernet-phy@11 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x11>; + }; + + xfiphy3: ethernet-phy@13 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x13>; + }; + + xfiphy4: ethernet-phy@12 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x12>; + }; + }; + }; +}; + &espi0 { status = "okay"; flash@0 { @@ -30,3 +168,5 @@ spi-max-frequency = <10000000>; /* input clock */ }; }; + +/include/ "t4240si-post.dtsi" diff --git a/arch/powerpc/dts/t4240si-post.dtsi b/arch/powerpc/dts/t4240si-post.dtsi new file mode 100644 index 00000000000..a596f48b54f --- /dev/null +++ b/arch/powerpc/dts/t4240si-post.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * T4240 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2021 NXP + * + */ +&soc { +/include/ "qoriq-clockgen2.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" + +/include/ "qoriq-fman3-0.dtsi" +/include/ "qoriq-fman3-0-1g-0.dtsi" +/include/ "qoriq-fman3-0-1g-1.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-1g-4.dtsi" +/include/ "qoriq-fman3-0-1g-5.dtsi" +/include/ "qoriq-fman3-0-10g-0.dtsi" +/include/ "qoriq-fman3-0-10g-1.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + enet5: ethernet@ea000 { + }; + + enet6: ethernet@f0000 { + }; + + enet7: ethernet@f2000 { + }; + + mdio@fc000 { + status = "disabled"; + }; + + mdio@fd000 { + status = "disabled"; + }; + }; + +/include/ "qoriq-fman3-1.dtsi" +/include/ "qoriq-fman3-1-1g-0.dtsi" +/include/ "qoriq-fman3-1-1g-1.dtsi" +/include/ "qoriq-fman3-1-1g-2.dtsi" +/include/ "qoriq-fman3-1-1g-3.dtsi" +/include/ "qoriq-fman3-1-1g-4.dtsi" +/include/ "qoriq-fman3-1-1g-5.dtsi" +/include/ "qoriq-fman3-1-10g-0.dtsi" +/include/ "qoriq-fman3-1-10g-1.dtsi" + fman@500000 { + enet8: ethernet@e0000 { + }; + + enet9: ethernet@e2000 { + }; + + enet10: ethernet@e4000 { + }; + + enet11: ethernet@e6000 { + }; + + enet12: ethernet@e8000 { + }; + + enet13: ethernet@ea000 { + }; + + enet14: ethernet@f0000 { + }; + + enet15: ethernet@f2000 { + }; + + mdio@5fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@5fd000 { + interrupts = <101 1 0 0>; + }; + }; +}; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 26003602249..7ad16635ad3 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -15,7 +15,9 @@ aliases { console = &uart0; eth0 = "/eth@10002000"; + eth2 = &swp_0; eth3 = ð_3; + eth4 = &dsa_eth0; eth5 = ð_5; gpio1 = &gpio_a; gpio2 = &gpio_b; @@ -478,6 +480,48 @@ fake-host-hwaddr = [00 00 66 44 22 22]; }; + dsa_eth0: dsa-test-eth { + compatible = "sandbox,eth"; + reg = <0x10006000 0x1000>; + fake-host-hwaddr = [00 00 66 44 22 66]; + }; + + dsa-test { + compatible = "sandbox,dsa"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + swp_0: port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "rgmii-rxid"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + swp_1: port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "rgmii-txid"; + fixed-link = <0 1 100 0 0>; + }; + + port@2 { + reg = <2>; + ethernet = <&dsa_eth0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + firmware { sandbox_firmware: sandbox-firmware { compatible = "sandbox,firmware"; diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index 7ba92f5db03..b57f589ec2d 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -1,10 +1,17 @@ -# SPDX-License-Identifier: GPL-2.0+ # # (C) Copyright 2011 - 2013 CompuLab, Ltd. # # Author: Igor Grinberg +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += fdt.o obj-y += common.o -obj-$(CONFIG_SYS_I2C) += eeprom.o +obj-y += mmc.o +obj-y += ../../freescale/common/mmc.o +ifneq "$(or $(CONFIG_SYS_I2C),$(CONFIG_DM_I2C))" "" +obj-y += eeprom.o +endif # (CONFIG_SYS_I2C || CONFIG_DM_I2C2) obj-$(CONFIG_LCD) += omap3_display.o obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c index 528c97df19a..a425778fdee 100644 --- a/board/compulab/common/common.c +++ b/board/compulab/common/common.c @@ -1,8 +1,9 @@ -// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2014 CompuLab, Ltd. * * Authors: Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ */ #include @@ -10,7 +11,6 @@ #include #include #include -#include #include "common.h" #include "eeprom.h" diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h index 17cfbb6f27a..759ec31317f 100644 --- a/board/compulab/common/common.h +++ b/board/compulab/common/common.h @@ -1,8 +1,9 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2014 CompuLab, Ltd. * * Authors: Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CL_COMMON_ diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index 5206cf5c0ad..cc171555947 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -1,18 +1,22 @@ -// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2011 CompuLab, Ltd. * * Authors: Nikita Kiryanov * Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ */ +#include #include -#include +#include #include +#include #include #include -#include #include +#include +#include #include "eeprom.h" #ifndef CONFIG_SYS_I2C_EEPROM_ADDR @@ -20,45 +24,95 @@ # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #endif +#ifndef CONFIG_SYS_I2C_EEPROM_ADDR_SB +# define CONFIG_SYS_I2C_EEPROM_ADDR_SB 0x54 +#endif + #ifndef CONFIG_SYS_I2C_EEPROM_BUS -#define CONFIG_SYS_I2C_EEPROM_BUS 0 +# define CONFIG_SYS_I2C_EEPROM_BUS 1 #endif -#define EEPROM_LAYOUT_VER_OFFSET 44 -#define BOARD_SERIAL_OFFSET 20 -#define BOARD_SERIAL_OFFSET_LEGACY 8 -#define BOARD_REV_OFFSET 0 -#define BOARD_REV_OFFSET_LEGACY 6 -#define BOARD_REV_SIZE 2 -#define PRODUCT_NAME_OFFSET 128 -#define PRODUCT_NAME_SIZE 16 -#define MAC_ADDR_OFFSET 4 -#define MAC_ADDR_OFFSET_LEGACY 0 +#ifndef CONFIG_SYS_I2C_EEPROM_BUS_SB +# define CONFIG_SYS_I2C_EEPROM_BUS_SB 0 +#endif #define LAYOUT_INVALID 0 #define LAYOUT_LEGACY 0xff -static int cl_eeprom_bus; static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */ +struct eeprom_path { + int bus; + uint8_t chip; +}; + +static const struct eeprom_path eeprom_som = { + CONFIG_SYS_I2C_EEPROM_BUS, + CONFIG_SYS_I2C_EEPROM_ADDR +}; +static const struct eeprom_path eeprom_sb = { + CONFIG_SYS_I2C_EEPROM_BUS_SB, + CONFIG_SYS_I2C_EEPROM_ADDR_SB +}; + +static const struct eeprom_path *working_eeprom; + +static struct udevice *g_dev = NULL; + +static int cpl_eeprom_init(void) { + + struct udevice *bus, *dev; + int ret; + + if (!g_dev) { + + ret = uclass_get_device_by_seq(UCLASS_I2C, working_eeprom->bus, &bus); + if (ret) { + printf("%s: No bus %d\n", __func__, working_eeprom->bus); + return ret; + } + + ret = dm_i2c_probe(bus, working_eeprom->chip, 0, &dev); + if (ret) { + printf("%s: Can't find device id=0x%x, on bus %d\n", + __func__, working_eeprom->chip, working_eeprom->bus); + return ret; + } + + /* Init */ + g_dev = dev; + } + + return 0; +} + static int cl_eeprom_read(uint offset, uchar *buf, int len) { int res; - unsigned int current_i2c_bus = i2c_get_bus_num(); - res = i2c_set_bus_num(cl_eeprom_bus); + res = cpl_eeprom_init(); if (res < 0) return res; - res = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, - CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); + res = dm_i2c_read(g_dev, offset, buf, len); + + return res; +} + +static int cl_eeprom_write(uint offset, uchar *buf, int len) +{ + int res; + + res = cpl_eeprom_init(); + if (res < 0) + return res; - i2c_set_bus_num(current_i2c_bus); + res = dm_i2c_write(g_dev, offset, buf, len); return res; } -static int cl_eeprom_setup(uint eeprom_bus) +static int cl_eeprom_setup(const struct eeprom_path *eeprom) { int res; @@ -66,10 +120,11 @@ static int cl_eeprom_setup(uint eeprom_bus) * We know the setup was already done when the layout is set to a valid * value and we're using the same bus as before. */ - if (cl_eeprom_layout != LAYOUT_INVALID && eeprom_bus == cl_eeprom_bus) + if (cl_eeprom_layout != LAYOUT_INVALID && eeprom == working_eeprom) return 0; - cl_eeprom_bus = eeprom_bus; + working_eeprom = eeprom; + g_dev = NULL; res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, (uchar *)&cl_eeprom_layout, 1); if (res) { @@ -83,14 +138,14 @@ static int cl_eeprom_setup(uint eeprom_bus) return 0; } -void get_board_serial(struct tag_serialnr *serialnr) +static void cpl_get_board_serial(struct tag_serialnr *serialnr, const struct eeprom_path *eeprom) { u32 serial[2]; uint offset; memset(serialnr, 0, sizeof(*serialnr)); - if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS)) + if (cl_eeprom_setup(eeprom)) return; offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? @@ -104,17 +159,25 @@ void get_board_serial(struct tag_serialnr *serialnr) serialnr->high = serial[1]; } } +inline void cpl_get_som_serial(struct tag_serialnr *serialnr) +{ + return cpl_get_board_serial(serialnr, &eeprom_som); +} +inline void cpl_get_sb_serial(struct tag_serialnr *serialnr) +{ + return cpl_get_board_serial(serialnr, &eeprom_sb); +} /* * Routine: cl_eeprom_read_mac_addr * Description: read mac address and store it in buf. */ -int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus) +int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus __attribute__((unused))) { uint offset; int err; - err = cl_eeprom_setup(eeprom_bus); + err = cl_eeprom_setup(&eeprom_som); if (err) return err; @@ -124,13 +187,39 @@ int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus) return cl_eeprom_read(offset, buf, 6); } +/* + * Routine: cl_eeprom_read_n_mac_addr + * Description: read iface_number mac address and store it in buf. + */ +int cl_eeprom_read_n_mac_addr(uchar *buf, uint iface_number, uint eeprom_bus __attribute__((unused))) +{ + uint offset; + int err; + + err = cl_eeprom_setup(&eeprom_som); + if (err) + return err; + + offset = (iface_number == 0) ? MAC_ADDR_OFFSET : MAC1_ADDR_OFFSET; + + err = cl_eeprom_read(offset, buf, 6); + { /* generate a random address if the som eeprom is empty */ + u32 mac0, mac2; + mac0 = (u32) buf[0]; + mac2 = (u32) buf[2]; + if ( mac0 == mac2 ) + net_random_ethaddr(buf); + } + return err; +} + static u32 board_rev; /* * Routine: cl_eeprom_get_board_rev * Description: read system revision from eeprom */ -u32 cl_eeprom_get_board_rev(uint eeprom_bus) +u32 cl_eeprom_get_board_rev(uint eeprom_bus __attribute__((unused))) { char str[5]; /* Legacy representation can contain at most 4 digits */ uint offset = BOARD_REV_OFFSET_LEGACY; @@ -138,7 +227,7 @@ u32 cl_eeprom_get_board_rev(uint eeprom_bus) if (board_rev) return board_rev; - if (cl_eeprom_setup(eeprom_bus)) + if (cl_eeprom_setup(&eeprom_som)) return 0; if (cl_eeprom_layout != LAYOUT_LEGACY) @@ -157,7 +246,29 @@ u32 cl_eeprom_get_board_rev(uint eeprom_bus) } return board_rev; -}; +} + +static u32 cl_eeprom_get_revision(const struct eeprom_path *eeprom) +{ + u32 revision; + + if (cl_eeprom_setup(eeprom)) + return 0; + + if (cl_eeprom_read(BOARD_REV_OFFSET, (uchar *)&revision, BOARD_REV_SIZE)) + return 0; + + return revision; +} +u32 cl_eeprom_get_som_revision(void) +{ + return cl_eeprom_get_revision(&eeprom_som); +} +u32 cl_eeprom_get_sb_revision(void) +{ + return cl_eeprom_get_revision(&eeprom_sb); +} + /* * Routine: cl_eeprom_get_board_rev @@ -168,14 +279,14 @@ u32 cl_eeprom_get_board_rev(uint eeprom_bus) * * @return: 0 on success, < 0 on failure */ -int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus) +int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus __attribute__((unused))) { int err; if (buf == NULL) return -EINVAL; - err = cl_eeprom_setup(eeprom_bus); + err = cl_eeprom_setup(&eeprom_som); if (err) return err; @@ -186,6 +297,71 @@ int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus) return err; } +static int cl_eeprom_read_options(char *buf, const struct eeprom_path *eeprom) +{ + int len = 0; + int err; + uchar tmp[PRODUCT_OPTION_SIZE]; + + err = cl_eeprom_setup(eeprom); + if (err) { + printf("%s: Error accesing i2c %x@%x\n", __func__, eeprom->bus, eeprom->chip); + return snprintf(buf, PRODUCT_NAME_SIZE, "unknown"); + } + + for(int i = 0; i < PRODUCT_OPTION_NUM; ++i) { + err = cl_eeprom_read(PRODUCT_OPTION_OFFSET + PRODUCT_OPTION_SIZE * i, tmp, PRODUCT_OPTION_SIZE); + if (!err && tmp[0] != 0xff) // Check if the flash isn't written + len += snprintf(buf + len, PRODUCT_OPTION_SIZE, (char*)tmp); + } + return len; +} +int cl_eeprom_read_som_options(char *buf) +{ + return cl_eeprom_read_options(buf, &eeprom_som); +} +int cl_eeprom_read_sb_options(char *buf) +{ + return cl_eeprom_read_options(buf, &eeprom_sb); +} + +static int cl_eeprom_read_product_name(char *buf, const struct eeprom_path *eeprom) +{ + int len; + int err; + uchar tmp[PRODUCT_NAME_SIZE]; + + err = cl_eeprom_setup(eeprom); + if (err) + printf("%s: Error accesing i2c %x@%x\n", __func__, eeprom->bus, eeprom->chip); + else + err = cl_eeprom_read(PRODUCT_NAME_OFFSET, tmp, PRODUCT_NAME_SIZE); + + if (!err && tmp[0] != 0xff) // Check if the flash isn't written + len = snprintf(buf, PRODUCT_NAME_SIZE, (char*)tmp); + else + len = snprintf(buf, PRODUCT_NAME_SIZE, "unknown"); + + return len; +} + +int cl_eeprom_read_sb_name(char *buf) +{ + return cl_eeprom_read_product_name(buf, &eeprom_sb); +} + +int cl_eeprom_read_som_name(char *buf) +{ + return cl_eeprom_read_product_name(buf, &eeprom_som); +} + +void cl_eeprom_get_suite(char *buf) +{ + buf += cl_eeprom_read_product_name(buf, &eeprom_som); + buf += sprintf(buf, " on "); + buf += cl_eeprom_read_product_name(buf, &eeprom_sb); +} + #ifdef CONFIG_CMD_EEPROM_LAYOUT /** * eeprom_field_print_bin_ver() - print a "version field" which contains binary @@ -199,17 +375,18 @@ int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus) * Field Name 123.45 * * @field: an initialized field to print + * @fbuf: field buffer */ -void eeprom_field_print_bin_ver(const struct eeprom_field *field) +void eeprom_field_print_bin_ver(const struct eeprom_field *field, uchar *fbuf) { - if ((field->buf[0] == 0xff) && (field->buf[1] == 0xff)) { - field->buf[0] = 0; - field->buf[1] = 0; + if ((fbuf[0] == 0xff) && (fbuf[1] == 0xff)) { + fbuf[0] = 0; + fbuf[1] = 0; } printf(PRINT_FIELD_SEGMENT, field->name); - int major = (field->buf[1] << 8 | field->buf[0]) / 100; - int minor = (field->buf[1] << 8 | field->buf[0]) - major * 100; + int major = (fbuf[1] << 8 | fbuf[0]) / 100; + int minor = (fbuf[1] << 8 | fbuf[0]) - major * 100; printf("%d.%02d\n", major, minor); } @@ -225,11 +402,13 @@ void eeprom_field_print_bin_ver(const struct eeprom_field *field) * field if there's any deviation from it. It also protects from overflow. * * @field: an initialized field + * @fbuf: field buffer * @value: a version string * * Returns 0 on success, -1 on failure. */ -int eeprom_field_update_bin_ver(struct eeprom_field *field, char *value) +int eeprom_field_update_bin_ver(struct eeprom_field *field, uchar *fbuf, + char *value) { char *endptr; char *tok = strtok(value, "."); @@ -252,8 +431,8 @@ int eeprom_field_update_bin_ver(struct eeprom_field *field, char *value) if (num >> 16) return -1; - field->buf[0] = (unsigned char)num; - field->buf[1] = num >> 8; + fbuf[0] = (unsigned char)num; + fbuf[1] = num >> 8; return 0; } @@ -270,17 +449,18 @@ char *months[12] = {"Jan", "Feb", "Mar", "Apr", "May", "Jun", * Field Name 56/BAD/9999 * * @field: an initialized field to print + * @fbuf: field buffer */ -void eeprom_field_print_date(const struct eeprom_field *field) +void eeprom_field_print_date(const struct eeprom_field *field, uchar *fbuf) { printf(PRINT_FIELD_SEGMENT, field->name); - printf("%02d/", field->buf[0]); - if (field->buf[1] >= 1 && field->buf[1] <= 12) - printf("%s", months[field->buf[1] - 1]); + printf("%02d/", fbuf[0]); + if (fbuf[1] >= 1 && fbuf[1] <= 12) + printf("%s", months[fbuf[1] - 1]); else printf("BAD"); - printf("/%d\n", field->buf[3] << 8 | field->buf[2]); + printf("/%d\n", fbuf[3] << 8 | fbuf[2]); } static int validate_date(unsigned char day, unsigned char month, @@ -338,11 +518,13 @@ static int validate_date(unsigned char day, unsigned char month, * year value, and checks the validity of the date. * * @field: an initialized field + * @fbuf: field buffer * @value: a date string * * Returns 0 on success, -1 on failure. */ -int eeprom_field_update_date(struct eeprom_field *field, char *value) +int eeprom_field_update_date(struct eeprom_field *field, uchar *fbuf, + char *value) { char *endptr; char *tok1 = strtok(value, "/"); @@ -381,10 +563,10 @@ int eeprom_field_update_date(struct eeprom_field *field, char *value) return -1; } - field->buf[0] = day; - field->buf[1] = month; - field->buf[2] = (unsigned char)year; - field->buf[3] = (unsigned char)(year >> 8); + fbuf[0] = day; + fbuf[1] = month; + fbuf[2] = (unsigned char)year; + fbuf[3] = (unsigned char)(year >> 8); return 0; } @@ -393,81 +575,111 @@ int eeprom_field_update_date(struct eeprom_field *field, char *value) #define LAYOUT_VERSION_VER1 2 #define LAYOUT_VERSION_VER2 3 #define LAYOUT_VERSION_VER3 4 +#define LAYOUT_VERSION_VER4 5 extern struct eeprom_field layout_unknown[1]; -#define DEFINE_PRINT_UPDATE(x) eeprom_field_print_##x, eeprom_field_update_##x +#define DEFINE_FIELD_FUNC(x) eeprom_field_print_##x, eeprom_field_update_##x, \ + eeprom_field_read_bin + +#define FIELD_FUNC_RES_LAST eeprom_field_print_reserved, \ + eeprom_field_update_ascii, \ + eeprom_field_read_bin + +#define FIELD_FUNC_SERIAL eeprom_field_print_bin_rev, \ + eeprom_field_update_bin_rev, \ + eeprom_field_read_rev #ifdef CONFIG_CM_T3X struct eeprom_field layout_legacy[5] = { - { "MAC address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "Board Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin) }, - { "Serial Number", 8, NULL, DEFINE_PRINT_UPDATE(bin) }, - { "Board Configuration", 64, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { RESERVED_FIELDS, 176, NULL, eeprom_field_print_reserved, - eeprom_field_update_ascii }, + { "MAC address", 6, DEFINE_FIELD_FUNC(mac) }, + { "Board Revision", 2, DEFINE_FIELD_FUNC(bin) }, + { "Serial Number", 8, DEFINE_FIELD_FUNC(bin) }, + { "Board Configuration", 64, DEFINE_FIELD_FUNC(ascii) }, + { RESERVED_FIELDS, 176, FIELD_FUNC_RES_LAST } }; #else #define layout_legacy layout_unknown #endif -#if defined(CONFIG_CM_T3X) +#if defined(CONFIG_CM_T3X) || defined(CONFIG_CM_T3517) struct eeprom_field layout_v1[12] = { - { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, - { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, - { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) }, - { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) }, - { RESERVED_FIELDS, 96, NULL, DEFINE_PRINT_UPDATE(reserved) }, - { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved, - eeprom_field_update_ascii }, + { "Major Revision", 2, DEFINE_FIELD_FUNC(bin_ver) }, + { "Minor Revision", 2, DEFINE_FIELD_FUNC(bin_ver) }, + { "1st MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { "2nd MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { "Production Date", 4, DEFINE_FIELD_FUNC(date) }, + { "Serial Number", 12, FIELD_FUNC_SERIAL }, + { RESERVED_FIELDS, 96, DEFINE_FIELD_FUNC(reserved) }, + { "Product Name", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #1", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #2", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #3", 16, DEFINE_FIELD_FUNC(ascii) }, + { RESERVED_FIELDS, 64, FIELD_FUNC_RES_LAST } }; #else #define layout_v1 layout_unknown #endif struct eeprom_field layout_v2[15] = { - { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, - { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, - { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) }, - { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) }, - { "3rd MAC Address (WIFI)", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "Layout Version", 1, NULL, DEFINE_PRINT_UPDATE(bin) }, - { RESERVED_FIELDS, 83, NULL, DEFINE_PRINT_UPDATE(reserved) }, - { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved, - eeprom_field_update_ascii }, + { "Major Revision", 2, DEFINE_FIELD_FUNC(bin_ver) }, + { "Minor Revision", 2, DEFINE_FIELD_FUNC(bin_ver) }, + { "1st MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { "2nd MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { "Production Date", 4, DEFINE_FIELD_FUNC(date) }, + { "Serial Number", 12, FIELD_FUNC_SERIAL }, + { "3rd MAC Address (WIFI)", 6, DEFINE_FIELD_FUNC(mac) }, + { "4th MAC Address (Bluetooth)", 6, DEFINE_FIELD_FUNC(mac) }, + { "Layout Version", 1, DEFINE_FIELD_FUNC(bin) }, + { RESERVED_FIELDS, 83, DEFINE_FIELD_FUNC(reserved) }, + { "Product Name", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #1", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #2", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #3", 16, DEFINE_FIELD_FUNC(ascii) }, + { RESERVED_FIELDS, 64, FIELD_FUNC_RES_LAST }, }; struct eeprom_field layout_v3[16] = { - { "Major Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, - { "Minor Revision", 2, NULL, DEFINE_PRINT_UPDATE(bin_ver) }, - { "1st MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "2nd MAC Address", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "Production Date", 4, NULL, DEFINE_PRINT_UPDATE(date) }, - { "Serial Number", 12, NULL, DEFINE_PRINT_UPDATE(bin_rev) }, - { "3rd MAC Address (WIFI)", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "4th MAC Address (Bluetooth)", 6, NULL, DEFINE_PRINT_UPDATE(mac) }, - { "Layout Version", 1, NULL, DEFINE_PRINT_UPDATE(bin) }, - { "CompuLab EEPROM ID", 3, NULL, DEFINE_PRINT_UPDATE(bin) }, - { RESERVED_FIELDS, 80, NULL, DEFINE_PRINT_UPDATE(reserved) }, - { "Product Name", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #1", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #2", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { "Product Options #3", 16, NULL, DEFINE_PRINT_UPDATE(ascii) }, - { RESERVED_FIELDS, 64, NULL, eeprom_field_print_reserved, - eeprom_field_update_ascii }, + { "Major Revision", 2, DEFINE_FIELD_FUNC(bin_ver) }, + { "Minor Revision", 2, DEFINE_FIELD_FUNC(bin_ver) }, + { "1st MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { "2nd MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { "Production Date", 4, DEFINE_FIELD_FUNC(date) }, + { "Serial Number", 12, FIELD_FUNC_SERIAL }, + { "3rd MAC Address (WIFI)", 6, DEFINE_FIELD_FUNC(mac) }, + { "4th MAC Address (Bluetooth)", 6, DEFINE_FIELD_FUNC(mac) }, + { "Layout Version", 1, DEFINE_FIELD_FUNC(bin) }, + { "CompuLab EEPROM ID", 3, DEFINE_FIELD_FUNC(bin) }, + { RESERVED_FIELDS, 80, DEFINE_FIELD_FUNC(reserved) }, + { "Product Name", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #1", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #2", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #3", 16, DEFINE_FIELD_FUNC(ascii) }, + { RESERVED_FIELDS, 64, FIELD_FUNC_RES_LAST }, +}; + +struct eeprom_field layout_v4[21] = { + { "Major Revision", 2, DEFINE_FIELD_FUNC(bin_ver) }, + { "Minor Revision", 2, DEFINE_FIELD_FUNC(bin_ver) }, + { "1st MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { "2nd MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { "Production Date", 4, DEFINE_FIELD_FUNC(date) }, + { "Serial Number", 12, FIELD_FUNC_SERIAL }, + { "3rd MAC Address (WIFI)", 6, DEFINE_FIELD_FUNC(mac) }, + { "4th MAC Address (Bluetooth)", 6, DEFINE_FIELD_FUNC(mac) }, + { "Layout Version", 1, DEFINE_FIELD_FUNC(bin) }, + { "CompuLab EEPROM ID", 3, DEFINE_FIELD_FUNC(bin) }, + { "5th MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { "6th MAC Address", 6, DEFINE_FIELD_FUNC(mac) }, + { RESERVED_FIELDS, 4, DEFINE_FIELD_FUNC(reserved) }, + { RESERVED_FIELDS, 64, DEFINE_FIELD_FUNC(reserved) }, + { "Product Name", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #1", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #2", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #3", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #4", 16, DEFINE_FIELD_FUNC(ascii) }, + { "Product Options #5", 16, DEFINE_FIELD_FUNC(ascii) }, + { RESERVED_FIELDS, 32, DEFINE_FIELD_FUNC(reserved) }, }; void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version) @@ -489,6 +701,10 @@ void eeprom_layout_assign(struct eeprom_layout *layout, int layout_version) layout->fields = layout_v3; layout->num_of_fields = ARRAY_SIZE(layout_v3); break; + case LAYOUT_VERSION_VER4: + layout->fields = layout_v4; + layout->num_of_fields = ARRAY_SIZE(layout_v4); + break; default: __eeprom_layout_assign(layout, layout_version); } @@ -504,6 +720,8 @@ int eeprom_parse_layout_version(char *str) return LAYOUT_VERSION_VER2; else if (!strcmp(str, "v3")) return LAYOUT_VERSION_VER3; + else if (!strcmp(str, "v4")) + return LAYOUT_VERSION_VER4; else return LAYOUT_VERSION_UNRECOGNIZED; } @@ -518,6 +736,8 @@ int eeprom_layout_detect(unsigned char *data) return LAYOUT_VERSION_VER2; case 3: return LAYOUT_VERSION_VER3; + case 4 ... 0x1f: + return LAYOUT_VERSION_VER4; } if (data[EEPROM_LAYOUT_VER_OFFSET] >= 0x20) @@ -526,3 +746,93 @@ int eeprom_layout_detect(unsigned char *data) return LAYOUT_VERSION_UNRECOGNIZED; } #endif + +#define BOARD_LDO4_OFFSET 0x60 +#define BOARD_LDO4_SIZE 1 +static const struct eeprom_path eeprom_51 = { + /*CONFIG_SYS_I2C_EEPROM_BUS*/ 0x1, + /*CONFIG_SYS_I2C_EEPROM_ADDR_P1*/ 0x51, +}; + +static u8 board_ldo4 = 0xff; +u8 cl_eeprom_get_ldo4(void) +{ + g_dev = NULL; + working_eeprom = &eeprom_51; + if (cl_eeprom_read(BOARD_LDO4_OFFSET, (uchar *)&board_ldo4, BOARD_LDO4_SIZE)) + return 0xff; + + return board_ldo4; +}; + +u8 cl_eeprom_set_ldo4(u8 ldo4) +{ + g_dev = NULL; + working_eeprom = &eeprom_51; + if (cl_eeprom_write(BOARD_LDO4_OFFSET, (uchar *)&ldo4, BOARD_LDO4_SIZE)) + return 0xff; + board_ldo4 = ldo4; + + return board_ldo4; +}; + +#ifndef CONFIG_SPL_BUILD +#define BOARD_DDRINFO_OFFSET 0x40 +#define BOARD_DDRINFO_SIZE 4 +static u32 board_ddrinfo = 0xdeadbeef; + +u32 cl_eeprom_get_ddrinfo(void) +{ + g_dev = NULL; + working_eeprom = &eeprom_51; + if (cl_eeprom_read(BOARD_DDRINFO_OFFSET, (uchar *)&board_ddrinfo, BOARD_DDRINFO_SIZE)) + return 0; + return board_ddrinfo; +}; + +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo) +{ + g_dev = NULL; + working_eeprom = &eeprom_51; + if (cl_eeprom_write(BOARD_DDRINFO_OFFSET, (uchar *)&ddrinfo, BOARD_DDRINFO_SIZE)) + return 0; + + board_ddrinfo = ddrinfo; + + return board_ddrinfo; +}; + +void cl_eeprom_clr_ddrinfo(void) +{ + u32 ddrinfo[2] = { 0xFFFFFFFF , 0xFFFFFFFF }; + g_dev = NULL; + working_eeprom = &eeprom_51; + cl_eeprom_write(BOARD_DDRINFO_OFFSET, (uchar *)ddrinfo, (BOARD_DDRINFO_SIZE<<1)); + return; +}; + +#define BOARD_DDRSUBIND_OFFSET 0x44 +#define BOARD_DDRSUBIND_SIZE 1 +static u8 board_ddrsubind = 0xff; +u8 cl_eeprom_get_subind(void) +{ + g_dev = NULL; + working_eeprom = &eeprom_51; + if (cl_eeprom_read(BOARD_DDRSUBIND_OFFSET, (uchar *)&board_ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + + return board_ddrsubind; +}; + +u8 cl_eeprom_set_subind(u8 ddrsubind) +{ + g_dev = NULL; + working_eeprom = &eeprom_51; + if (cl_eeprom_write(BOARD_DDRSUBIND_OFFSET, (uchar *)&ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + + board_ddrsubind = ddrsubind; + + return board_ddrsubind; +}; +#endif diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h index a9c0203b81a..d4b70febcb2 100644 --- a/board/compulab/common/eeprom.h +++ b/board/compulab/common/eeprom.h @@ -1,27 +1,53 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2011 CompuLab, Ltd. * * Authors: Nikita Kiryanov * Igor Grinberg + * + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _EEPROM_ #define _EEPROM_ #include +#include + +#define EEPROM_LAYOUT_VER_OFFSET 44 +#define BOARD_SERIAL_OFFSET 20 +#define BOARD_SERIAL_OFFSET_LEGACY 8 +#define BOARD_REV_OFFSET 0 +#define BOARD_REV_OFFSET_LEGACY 6 +#define BOARD_REV_SIZE 2 +#define PRODUCT_NAME_OFFSET 128 +#define PRODUCT_NAME_SIZE 16 +#define PRODUCT_OPTION_OFFSET 144 +#define PRODUCT_OPTION_SIZE 16 +#define PRODUCT_OPTION_NUM 5 +#define MAC_ADDR_OFFSET 4 +#define MAC1_ADDR_OFFSET 10 +#define MAC_ADDR_OFFSET_LEGACY 0 -#ifdef CONFIG_SYS_I2C +#if (defined(CONFIG_SYS_I2C) || defined(CONFIG_DM_I2C)) int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus); -u32 cl_eeprom_get_board_rev(uint eeprom_bus); +int cl_eeprom_read_n_mac_addr(uchar *buf, uint iface_number, uint eeprom_bus); +u32 cl_eeprom_get_som_revision(void); +u32 cl_eeprom_get_sb_revision(void); int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus); +int cl_eeprom_read_sb_name(char *buf); +int cl_eeprom_read_som_name(char *buf); +int cl_eeprom_read_som_options(char *buf); +int cl_eeprom_read_sb_options(char *buf); +void cl_eeprom_get_suite(char* buf); +void cpl_get_som_serial(struct tag_serialnr *serialnr); +void cpl_get_sb_serial(struct tag_serialnr *serialnr); #else static inline int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus) { return 1; } -static inline u32 cl_eeprom_get_board_rev(uint eeprom_bus) +static int cl_eeprom_read_n_mac_addr(uchar *buf, uint iface_number, uint eeprom_bus) { - return 0; + return 1; } static inline int cl_eeprom_get_product_name(uchar *buf, uint eeprom_bus) { diff --git a/board/compulab/common/fdt.c b/board/compulab/common/fdt.c new file mode 100644 index 00000000000..bec94ad8097 --- /dev/null +++ b/board/compulab/common/fdt.c @@ -0,0 +1,72 @@ +#include +#include +#include +#include +#include +#include +#include +#include "mmc.h" +#include "eeprom.h" + +void fdt_set_sn(void *blob) +{ + u32 rev; + char buf[100]; + int len; + union { + struct tag_serialnr s; + u64 u; + } serialnr; + + len = cl_eeprom_read_som_name(buf); + fdt_setprop(blob, 0, "product-name", buf, len); + + len = cl_eeprom_read_sb_name(buf); + fdt_setprop(blob, 0, "baseboard-name", buf, len); + + cpl_get_som_serial(&serialnr.s); + fdt_setprop(blob, 0, "product-sn", buf, sprintf(buf, "%llx", serialnr.u) + 1); + + cpl_get_sb_serial(&serialnr.s); + fdt_setprop(blob, 0, "baseboard-sn", buf, sprintf(buf, "%llx", serialnr.u) + 1); + + rev = cl_eeprom_get_som_revision(); + fdt_setprop(blob, 0, "product-revision", buf, + sprintf(buf, "%u.%02u", rev/100 , rev%100 ) + 1); + + rev = cl_eeprom_get_sb_revision(); + fdt_setprop(blob, 0, "baseboard-revision", buf, + sprintf(buf, "%u.%02u", rev/100 , rev%100 ) + 1); + + len = cl_eeprom_read_som_options(buf); + fdt_setprop(blob, 0, "product-options", buf, len); + + len = cl_eeprom_read_sb_options(buf); + fdt_setprop(blob, 0, "baseboard-options", buf, len); + + return; +} + +int fdt_set_env_addr(void *blob) +{ + char tmp[32]; + int nodeoff = fdt_add_subnode(blob, 0, "fw_env"); + int env_dev = get_env_dev(); + int env_part = get_env_part(); + if(0 > nodeoff) + return nodeoff; + + fdt_setprop(blob, nodeoff, "env_off", tmp, sprintf(tmp, "0x%x", CONFIG_ENV_OFFSET)); + fdt_setprop(blob, nodeoff, "env_size", tmp, sprintf(tmp, "0x%x", CONFIG_ENV_SIZE)); + if(0 < env_dev) { + switch(env_part) { + case 1 ... 2: + fdt_setprop(blob, nodeoff, "env_dev", tmp, sprintf(tmp, "/dev/mmcblk%iboot%i", env_dev, env_part - 1)); + break; + default: + fdt_setprop(blob, nodeoff, "env_dev", tmp, sprintf(tmp, "/dev/mmcblk%i", env_dev)); + break; + } + } + return 0; +} diff --git a/board/compulab/common/fdt.h b/board/compulab/common/fdt.h new file mode 100644 index 00000000000..ba9f0515d21 --- /dev/null +++ b/board/compulab/common/fdt.h @@ -0,0 +1,7 @@ +#ifndef _COMMON_FDT_H__ +#define _COMMON_FDT_H__ + +void fdt_set_sn(void *blob); +int fdt_set_env_addr(void *blob); + +#endif /* _FDT_H__ */ diff --git a/board/compulab/common/mmc.c b/board/compulab/common/mmc.c new file mode 100644 index 00000000000..ce21add72d8 --- /dev/null +++ b/board/compulab/common/mmc.c @@ -0,0 +1,50 @@ +#include +#include +#include +#include +#include +#include +#include +#include "mmc.h" + +static int env_dev = -1; +static int env_part= -1; + +int get_env_dev() { + return env_dev; +} + +int get_env_part() { + return env_dev; +} + +int board_mmc_get_env_dev(int devno) +{ + const ulong user_env_devno = env_get_hex("env_dev", ULONG_MAX); + if (user_env_devno != ULONG_MAX) { + printf("User Environment dev# is (%lu)\n", user_env_devno); + return (int)user_env_devno; + } + return devno; +} + +static int _mmc_get_env_part(struct mmc *mmc) +{ + const ulong user_env_part = env_get_hex("env_part", ULONG_MAX); + if (user_env_part != ULONG_MAX) { + printf("User Environment part# is (%lu)\n", user_env_part); + return (int)user_env_part; + } + + return EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); +} + +uint mmc_get_env_part(struct mmc *mmc) +{ + if (mmc->part_support && mmc->part_config != MMCPART_NOAVAILABLE) { + uint partno = _mmc_get_env_part(mmc); + env_part = partno; + return partno; + } + return 0; +} diff --git a/board/compulab/common/mmc.h b/board/compulab/common/mmc.h new file mode 100644 index 00000000000..11e5c7a65df --- /dev/null +++ b/board/compulab/common/mmc.h @@ -0,0 +1,8 @@ +#ifndef _COMMON_MMC_H__ +#define _COMMON_MMC_H__ + +int get_env_dev(void); +int get_env_part(void); + +#endif /* _COMMON_MMC_H__ */ + diff --git a/board/compulab/common/pfuze.c b/board/compulab/common/pfuze.c new file mode 100644 index 00000000000..f194d0b79d0 --- /dev/null +++ b/board/compulab/common/pfuze.c @@ -0,0 +1,174 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifndef CONFIG_DM_PMIC_PFUZE100 +int pfuze_mode_init(struct pmic *p, u32 mode) +{ + unsigned char offset, i, switch_num; + u32 id; + int ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = id & 0xf; + + if (id == 0) { + switch_num = 6; + offset = PFUZE100_SW1CMODE; + } else if (id == 1) { + switch_num = 4; + offset = PFUZE100_SW2MODE; + } else { + printf("Not supported, id=%d\n", id); + return -EINVAL; + } + + ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + if (ret < 0) { + printf("Set SW1AB mode error!\n"); + return ret; + } + + for (i = 0; i < switch_num - 1; i++) { + ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + if (ret < 0) { + printf("Set switch 0x%x mode error!\n", + offset + i * SWITCH_SIZE); + return ret; + } + } + + return ret; +} + +struct pmic *pfuze_common_init(unsigned char i2cbus) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(i2cbus); + if (ret) + return NULL; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return NULL; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set SW1AB stanby volage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + + return p; +} +#else +int pfuze_mode_init(struct udevice *dev, u32 mode) +{ + unsigned char offset, i, switch_num; + u32 id; + int ret; + + id = pmic_reg_read(dev, PFUZE100_DEVICEID); + id = id & 0xf; + + if (id == 0) { + switch_num = 6; + offset = PFUZE100_SW1CMODE; + } else if (id == 1) { + switch_num = 4; + offset = PFUZE100_SW2MODE; + } else { + printf("Not supported, id=%d\n", id); + return -EINVAL; + } + + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); + if (ret < 0) { + printf("Set SW1AB mode error!\n"); + return ret; + } + + for (i = 0; i < switch_num - 1; i++) { + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); + if (ret < 0) { + printf("Set switch 0x%x mode error!\n", + offset + i * SWITCH_SIZE); + return ret; + } + } + + return ret; +} + +struct udevice *pfuze_common_init(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return NULL; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* Set SW1AB stanby volage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + return dev; +} +#endif diff --git a/board/compulab/common/pfuze.h b/board/compulab/common/pfuze.h new file mode 100644 index 00000000000..b7994170709 --- /dev/null +++ b/board/compulab/common/pfuze.h @@ -0,0 +1,19 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PFUZE_BOARD_HELPER__ +#define __PFUZE_BOARD_HELPER__ + +#ifdef CONFIG_DM_PMIC_PFUZE100 +struct udevice *pfuze_common_init(void); +int pfuze_mode_init(struct udevice *dev, u32 mode); +#else +struct pmic *pfuze_common_init(unsigned char i2cbus); +int pfuze_mode_init(struct pmic *p, u32 mode); +#endif + +#endif diff --git a/board/compulab/common/pfuze_dm.c b/board/compulab/common/pfuze_dm.c new file mode 100644 index 00000000000..c6af6278276 --- /dev/null +++ b/board/compulab/common/pfuze_dm.c @@ -0,0 +1,89 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int pfuze_mode_init(struct udevice *dev, u32 mode) +{ + unsigned char offset, i, switch_num; + u32 id; + int ret; + + id = pmic_reg_read(dev, PFUZE100_DEVICEID); + id = id & 0xf; + + if (id == 0) { + switch_num = 6; + offset = PFUZE100_SW1CMODE; + } else if (id == 1) { + switch_num = 4; + offset = PFUZE100_SW2MODE; + } else { + printf("Not supported, id=%d\n", id); + return -EINVAL; + } + + ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode); + if (ret < 0) { + printf("Set SW1AB mode error!\n"); + return ret; + } + + for (i = 0; i < switch_num - 1; i++) { + ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode); + if (ret < 0) { + printf("Set switch 0x%x mode error!\n", + offset + i * SWITCH_SIZE); + return ret; + } + } + + return ret; +} + +struct udevice *pfuze_common_init(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) + return NULL; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* Set SW1AB stanby volage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + return dev; +} diff --git a/board/compulab/common/rtc.h b/board/compulab/common/rtc.h new file mode 100644 index 00000000000..b5927a86f44 --- /dev/null +++ b/board/compulab/common/rtc.h @@ -0,0 +1,20 @@ +#ifndef _RTC_H_ +#define _RTC_H_ + + +#ifndef CONFIG_SYS_I2C_RTC_BUS +#define CONFIG_SYS_I2C_RTC_BUS 1 +#endif + +#ifndef CONFIG_SYS_I2C_RTC_ADDR +#define CONFIG_SYS_I2C_RTC_ADDR 0x69 +#endif + +#define ABX8XX_REG_CFG_KEY 0x1f +#define ABX8XX_CFG_KEY_MISC 0x9d + +#define ABX8XX_REG_BATMODE 0x27 +#define ABX8XX_BATMODE_IOBM_NOT 0 + +#endif //_RTC_H_ + diff --git a/board/compulab/common/tcpc.h b/board/compulab/common/tcpc.h new file mode 100644 index 00000000000..e1193c3f84f --- /dev/null +++ b/board/compulab/common/tcpc.h @@ -0,0 +1,454 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TCPCI_H +#define __TCPCI_H + +#include + +#define TCPC_VENDOR_ID 0x0 +#define TCPC_PRODUCT_ID 0x2 + +#define TCPC_ALERT 0x10 +#define TCPC_ALERT_VBUS_DISCNCT BIT(11) +#define TCPC_ALERT_RX_BUF_OVF BIT(10) +#define TCPC_ALERT_FAULT BIT(9) +#define TCPC_ALERT_V_ALARM_LO BIT(8) +#define TCPC_ALERT_V_ALARM_HI BIT(7) +#define TCPC_ALERT_TX_SUCCESS BIT(6) +#define TCPC_ALERT_TX_DISCARDED BIT(5) +#define TCPC_ALERT_TX_FAILED BIT(4) +#define TCPC_ALERT_RX_HARD_RST BIT(3) +#define TCPC_ALERT_RX_STATUS BIT(2) +#define TCPC_ALERT_POWER_STATUS BIT(1) +#define TCPC_ALERT_CC_STATUS BIT(0) + +#define TCPC_TCPC_CTRL 0x19 +#define TCPC_TCPC_CTRL_BIST_MODE BIT(1) +#define TCPC_TCPC_CTRL_ORIENTATION BIT(0) + +#define TCPC_ROLE_CTRL 0x1a +#define TCPC_ROLE_CTRL_DRP BIT(6) +#define TCPC_ROLE_CTRL_RP_VAL_SHIFT 4 +#define TCPC_ROLE_CTRL_RP_VAL_MASK 0x3 +#define TCPC_ROLE_CTRL_RP_VAL_DEF 0x0 +#define TCPC_ROLE_CTRL_RP_VAL_1_5 0x1 +#define TCPC_ROLE_CTRL_RP_VAL_3_0 0x2 +#define TCPC_ROLE_CTRL_CC2_SHIFT 2 +#define TCPC_ROLE_CTRL_CC2_MASK 0x3 +#define TCPC_ROLE_CTRL_CC1_SHIFT 0 +#define TCPC_ROLE_CTRL_CC1_MASK 0x3 +#define TCPC_ROLE_CTRL_CC_RA 0x0 +#define TCPC_ROLE_CTRL_CC_RP 0x1 +#define TCPC_ROLE_CTRL_CC_RD 0x2 +#define TCPC_ROLE_CTRL_CC_OPEN 0x3 + +#define TCPC_POWER_CTRL 0x1c +#define TCPC_POWER_CTRL_EN_VCONN BIT(0) +#define TCPC_POWER_CTRL_VCONN_POWER BIT(1) +#define TCPC_POWER_CTRL_FORCE_DISCH BIT(2) +#define TCPC_POWER_CTRL_EN_BLEED_CH BIT(3) +#define TCPC_POWER_CTRL_AUTO_DISCH_DISCO BIT(4) +#define TCPC_POWER_CTRL_DIS_V_ALARMS BIT(5) +#define TCPC_POWER_CTRL_VBUS_V_MONITOR BIT(6) + +#define TCPC_CC_STATUS 0x1d +#define TCPC_CC_STATUS_LOOK4CONN BIT(5) +#define TCPC_CC_STATUS_TERM BIT(4) +#define TCPC_CC_STATUS_CC2_SHIFT 2 +#define TCPC_CC_STATUS_CC2_MASK 0x3 +#define TCPC_CC_STATUS_CC1_SHIFT 0 +#define TCPC_CC_STATUS_CC1_MASK 0x3 + +#define TCPC_POWER_STATUS 0x1e +#define TCPC_POWER_STATUS_UNINIT BIT(6) +#define TCPC_POWER_STATUS_VBUS_DET BIT(3) +#define TCPC_POWER_STATUS_VBUS_PRES BIT(2) +#define TCPC_POWER_STATUS_SINKING_VBUS BIT(0) + +#define TCPC_FAULT_STATUS 0x1f + +#define TCPC_COMMAND 0x23 +#define TCPC_CMD_WAKE_I2C 0x11 +#define TCPC_CMD_DISABLE_VBUS_DETECT 0x22 +#define TCPC_CMD_ENABLE_VBUS_DETECT 0x33 +#define TCPC_CMD_DISABLE_SINK_VBUS 0x44 +#define TCPC_CMD_SINK_VBUS 0x55 +#define TCPC_CMD_DISABLE_SRC_VBUS 0x66 +#define TCPC_CMD_SRC_VBUS_DEFAULT 0x77 +#define TCPC_CMD_SRC_VBUS_HIGH 0x88 +#define TCPC_CMD_LOOK4CONNECTION 0x99 +#define TCPC_CMD_RXONEMORE 0xAA +#define TCPC_CMD_I2C_IDLE 0xFF + +#define TCPC_DEV_CAP_1 0x24 +#define TCPC_DEV_CAP_2 0x26 +#define TCPC_STD_INPUT_CAP 0x28 +#define TCPC_STD_OUTPUT_CAP 0x29 + +#define TCPC_MSG_HDR_INFO 0x2e +#define TCPC_MSG_HDR_INFO_DATA_ROLE BIT(3) +#define TCPC_MSG_HDR_INFO_PWR_ROLE BIT(0) +#define TCPC_MSG_HDR_INFO_REV_SHIFT 1 +#define TCPC_MSG_HDR_INFO_REV_MASK 0x3 + +#define TCPC_RX_DETECT 0x2f +#define TCPC_RX_DETECT_HARD_RESET BIT(5) +#define TCPC_RX_DETECT_SOP BIT(0) + +#define TCPC_RX_BYTE_CNT 0x30 +#define TCPC_RX_BUF_FRAME_TYPE 0x31 +#define TCPC_RX_HDR 0x32 +#define TCPC_RX_DATA 0x34 /* through 0x4f */ + +#define TCPC_TRANSMIT 0x50 +#define TCPC_TRANSMIT_RETRY_SHIFT 4 +#define TCPC_TRANSMIT_RETRY_MASK 0x3 +#define TCPC_TRANSMIT_TYPE_SHIFT 0 +#define TCPC_TRANSMIT_TYPE_MASK 0x7 + +#define TCPC_TX_BYTE_CNT 0x51 +#define TCPC_TX_HDR 0x52 +#define TCPC_TX_DATA 0x54 /* through 0x6f */ + +#define TCPC_VBUS_VOLTAGE 0x70 +#define TCPC_VBUS_VOL_MASK 0x3ff +#define TCPC_VBUS_VOL_SCALE_FACTOR_MASK 0xc00 +#define TCPC_VBUS_VOL_SCALE_FACTOR_SHIFT 10 +#define TCPC_VBUS_VOL_MV_UNIT 25 + +#define TCPC_VBUS_SINK_DISCONNECT_THRESH 0x72 +#define TCPC_VBUS_STOP_DISCHARGE_THRESH 0x74 +#define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 +#define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 + +enum typec_role { + TYPEC_SINK, + TYPEC_SOURCE, + TYPEC_ROLE_UNKNOWN, +}; + +enum typec_data_role { + TYPEC_DEVICE, + TYPEC_HOST, +}; + +enum typec_cc_polarity { + TYPEC_POLARITY_CC1, + TYPEC_POLARITY_CC2, +}; + +enum typec_cc_state { + TYPEC_STATE_OPEN, + TYPEC_STATE_SRC_BOTH_RA, + TYPEC_STATE_SRC_RD_RA, + TYPEC_STATE_SRC_RD, + TYPEC_STATE_SRC_RESERVED, + TYPEC_STATE_SNK_DEFAULT, + TYPEC_STATE_SNK_POWER15, + TYPEC_STATE_SNK_POWER30, +}; + + +/* USB PD Messages */ +enum pd_ctrl_msg_type { + /* 0 Reserved */ + PD_CTRL_GOOD_CRC = 1, + PD_CTRL_GOTO_MIN = 2, + PD_CTRL_ACCEPT = 3, + PD_CTRL_REJECT = 4, + PD_CTRL_PING = 5, + PD_CTRL_PS_RDY = 6, + PD_CTRL_GET_SOURCE_CAP = 7, + PD_CTRL_GET_SINK_CAP = 8, + PD_CTRL_DR_SWAP = 9, + PD_CTRL_PR_SWAP = 10, + PD_CTRL_VCONN_SWAP = 11, + PD_CTRL_WAIT = 12, + PD_CTRL_SOFT_RESET = 13, + /* 14-15 Reserved */ +}; + +enum pd_data_msg_type { + /* 0 Reserved */ + PD_DATA_SOURCE_CAP = 1, + PD_DATA_REQUEST = 2, + PD_DATA_BIST = 3, + PD_DATA_SINK_CAP = 4, + /* 5-14 Reserved */ + PD_DATA_VENDOR_DEF = 15, +}; + +enum tcpc_transmit_type { + TCPC_TX_SOP = 0, + TCPC_TX_SOP_PRIME = 1, + TCPC_TX_SOP_PRIME_PRIME = 2, + TCPC_TX_SOP_DEBUG_PRIME = 3, + TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4, + TCPC_TX_HARD_RESET = 5, + TCPC_TX_CABLE_RESET = 6, + TCPC_TX_BIST_MODE_2 = 7 +}; + +enum pd_sink_state{ + UNATTACH = 0, + ATTACHED, + WAIT_SOURCE_CAP, + WAIT_SOURCE_ACCEPT, + WAIT_SOURCE_READY, + SINK_READY, +}; + + +#define PD_REV10 0x0 +#define PD_REV20 0x1 + +#define PD_HEADER_CNT_SHIFT 12 +#define PD_HEADER_CNT_MASK 0x7 +#define PD_HEADER_ID_SHIFT 9 +#define PD_HEADER_ID_MASK 0x7 +#define PD_HEADER_PWR_ROLE BIT(8) +#define PD_HEADER_REV_SHIFT 6 +#define PD_HEADER_REV_MASK 0x3 +#define PD_HEADER_DATA_ROLE BIT(5) +#define PD_HEADER_TYPE_SHIFT 0 +#define PD_HEADER_TYPE_MASK 0xf + +#define PD_HEADER(type, pwr, data, id, cnt) \ + ((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) | \ + ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) | \ + ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) | \ + (PD_REV20 << PD_HEADER_REV_SHIFT) | \ + (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) | \ + (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT)) + + +static inline unsigned int pd_header_cnt(uint16_t header) +{ + return (header >> PD_HEADER_CNT_SHIFT) & PD_HEADER_CNT_MASK; +} + +static inline unsigned int pd_header_cnt_le(__le16 header) +{ + return pd_header_cnt(le16_to_cpu(header)); +} + +static inline unsigned int pd_header_type(uint16_t header) +{ + return (header >> PD_HEADER_TYPE_SHIFT) & PD_HEADER_TYPE_MASK; +} + +static inline unsigned int pd_header_type_le(__le16 header) +{ + return pd_header_type(le16_to_cpu(header)); +} + +#define PD_MAX_PAYLOAD 7 + +struct pd_message { + uint8_t frametype; + uint16_t header; + uint32_t payload[PD_MAX_PAYLOAD]; +} __packed; + +enum pd_pdo_type { + PDO_TYPE_FIXED = 0, + PDO_TYPE_BATT = 1, + PDO_TYPE_VAR = 2, +}; + + +#define PDO_TYPE_SHIFT 30 +#define PDO_TYPE_MASK 0x3 + +#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) + +#define PDO_VOLT_MASK 0x3ff +#define PDO_CURR_MASK 0x3ff +#define PDO_PWR_MASK 0x3ff + +#define PDO_FIXED_DUAL_ROLE BIT(29) /* Power role swap supported */ +#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported (Source) */ +#define PDO_FIXED_HIGHER_CAP BIT(28) /* Requires more than vSafe5V (Sink) */ +#define PDO_FIXED_EXTPOWER BIT(27) /* Externally powered */ +#define PDO_FIXED_USB_COMM BIT(26) /* USB communications capable */ +#define PDO_FIXED_DATA_SWAP BIT(25) /* Data role swap supported */ +#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) +#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) + +#define PDO_FIXED(mv, ma, flags) \ + (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ + PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) + +#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) +#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) +#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) + +#define PDO_BATT(min_mv, max_mv, max_mw) \ + (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ + PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) + +#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) +#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) +#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) + +#define PDO_VAR(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ + PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) + +static inline enum pd_pdo_type pdo_type(uint32_t pdo) +{ + return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK; +} + +static inline unsigned int pdo_fixed_voltage(uint32_t pdo) +{ + return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50; +} + +static inline unsigned int pdo_min_voltage(uint32_t pdo) +{ + return ((pdo >> PDO_VAR_MIN_VOLT_SHIFT) & PDO_VOLT_MASK) * 50; +} + +static inline unsigned int pdo_max_voltage(uint32_t pdo) +{ + return ((pdo >> PDO_VAR_MAX_VOLT_SHIFT) & PDO_VOLT_MASK) * 50; +} + +static inline unsigned int pdo_max_current(uint32_t pdo) +{ + return ((pdo >> PDO_VAR_MAX_CURR_SHIFT) & PDO_CURR_MASK) * 10; +} + +static inline unsigned int pdo_max_power(uint32_t pdo) +{ + return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250; +} + +/* RDO: Request Data Object */ +#define RDO_OBJ_POS_SHIFT 28 +#define RDO_OBJ_POS_MASK 0x7 +#define RDO_GIVE_BACK BIT(27) /* Supports reduced operating current */ +#define RDO_CAP_MISMATCH BIT(26) /* Not satisfied by source caps */ +#define RDO_USB_COMM BIT(25) /* USB communications capable */ +#define RDO_NO_SUSPEND BIT(24) /* USB Suspend not supported */ + +#define RDO_PWR_MASK 0x3ff +#define RDO_CURR_MASK 0x3ff + +#define RDO_FIXED_OP_CURR_SHIFT 10 +#define RDO_FIXED_MAX_CURR_SHIFT 0 + +#define RDO_OBJ(idx) (((idx) & RDO_OBJ_POS_MASK) << RDO_OBJ_POS_SHIFT) + +#define PDO_FIXED_OP_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_OP_CURR_SHIFT) +#define PDO_FIXED_MAX_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_MAX_CURR_SHIFT) + +#define RDO_FIXED(idx, op_ma, max_ma, flags) \ + (RDO_OBJ(idx) | (flags) | \ + PDO_FIXED_OP_CURR(op_ma) | PDO_FIXED_MAX_CURR(max_ma)) + +#define RDO_BATT_OP_PWR_SHIFT 10 /* 250mW units */ +#define RDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT) +#define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT) + +#define RDO_BATT(idx, op_mw, max_mw, flags) \ + (RDO_OBJ(idx) | (flags) | \ + RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw)) + +static inline unsigned int rdo_index(u32 rdo) +{ + return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK; +} + +static inline unsigned int rdo_op_current(u32 rdo) +{ + return ((rdo >> RDO_FIXED_OP_CURR_SHIFT) & RDO_CURR_MASK) * 10; +} + +static inline unsigned int rdo_max_current(u32 rdo) +{ + return ((rdo >> RDO_FIXED_MAX_CURR_SHIFT) & + RDO_CURR_MASK) * 10; +} + +static inline unsigned int rdo_op_power(u32 rdo) +{ + return ((rdo >> RDO_BATT_OP_PWR_SHIFT) & RDO_PWR_MASK) * 250; +} + +static inline unsigned int rdo_max_power(u32 rdo) +{ + return ((rdo >> RDO_BATT_MAX_PWR_SHIFT) & RDO_PWR_MASK) * 250; +} + +#define TCPC_LOG_BUFFER_SIZE 1024 + +struct tcpc_port; + +typedef void (*ss_mux_sel)(enum typec_cc_polarity pol); +typedef int (*ext_pd_switch_setup)(struct tcpc_port *port_p); + +enum tcpc_port_type { + TYPEC_PORT_DFP, + TYPEC_PORT_UFP, + TYPEC_PORT_DRP, +}; + +struct tcpc_port_config { + uint8_t i2c_bus; + uint8_t addr; + enum tcpc_port_type port_type; + uint32_t max_snk_mv; + uint32_t max_snk_ma; + uint32_t max_snk_mw; + uint32_t op_snk_mv; + bool disable_pd; + ext_pd_switch_setup switch_setup_func; +}; + +struct tcpc_port { + struct tcpc_port_config cfg; + struct udevice *i2c_dev; + ss_mux_sel ss_sel_func; + enum pd_sink_state pd_state; + uint32_t tx_msg_id; + uint32_t log_size; + char logbuffer[TCPC_LOG_BUFFER_SIZE]; + char *log_p; + char *log_print; +}; + +int tcpc_set_cc_to_source(struct tcpc_port *port); +int tcpc_set_cc_to_sink(struct tcpc_port *port); +int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity polarity); +int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, enum typec_cc_state *state); +int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask); +int tcpc_send_command(struct tcpc_port *port, uint8_t command); +int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg, + uint8_t reg_width, uint16_t mask, uint16_t value, ulong timeout_ms); +int tcpc_setup_dfp_mode(struct tcpc_port *port); +int tcpc_setup_ufp_mode(struct tcpc_port *port); +int tcpc_disable_src_vbus(struct tcpc_port *port); +int tcpc_init(struct tcpc_port *port, struct tcpc_port_config config, ss_mux_sel ss_sel_func); +bool tcpc_pd_sink_check_charging(struct tcpc_port *port); +void tcpc_print_log(struct tcpc_port *port); + +#endif /* __TCPCI_H */ diff --git a/board/compulab/iot-gate-imx8/Kconfig b/board/compulab/iot-gate-imx8/Kconfig new file mode 100644 index 00000000000..0f6a7f39542 --- /dev/null +++ b/board/compulab/iot-gate-imx8/Kconfig @@ -0,0 +1,17 @@ +if TARGET_IOT_GATE_IMX8 + +config SYS_BOARD + default "iot-gate-imx8" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "iot-gate-imx8" + +config DEFAULT_FDT + string + depends on TARGET_IOT_GATE_IMX8 + default "sb-iotgimx8-can.dtb" + +endif diff --git a/board/compulab/iot-gate-imx8/Makefile b/board/compulab/iot-gate-imx8/Makefile new file mode 100644 index 00000000000..fa228294ef0 --- /dev/null +++ b/board/compulab/iot-gate-imx8/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2018 CompuLab +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mm/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += iot-gate-imx8.o +endif + +obj-y += ../plat/imx8mm/ +obj-y += ../plat/imx8/ diff --git a/board/compulab/iot-gate-imx8/iot-gate-imx8.c b/board/compulab/iot-gate-imx8/iot-gate-imx8.c new file mode 100644 index 00000000000..6cafc259e9e --- /dev/null +++ b/board/compulab/iot-gate-imx8/iot-gate-imx8.c @@ -0,0 +1,30 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; diff --git a/board/compulab/iot-gate-imx8/spl.c b/board/compulab/iot-gate-imx8/spl.c new file mode 100644 index 00000000000..d6ece8ef3ee --- /dev/null +++ b/board/compulab/iot-gate-imx8/spl.c @@ -0,0 +1,9 @@ +#include +#include +#include +#include +#include + +int spl_board_private_init(void) { + return 0; +} diff --git a/board/compulab/iot-gate-imx8plus/Kconfig b/board/compulab/iot-gate-imx8plus/Kconfig new file mode 100644 index 00000000000..223608a9dff --- /dev/null +++ b/board/compulab/iot-gate-imx8plus/Kconfig @@ -0,0 +1,38 @@ +if TARGET_IOT_GATE_IMX8PLUS + +config SYS_BOARD + default "iot-gate-imx8plus" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "iot-gate-imx8plus" + +config DEFAULT_DTB + string + default "iot-gate-imx8plus.dtb" + +config DEFAULT_FDT_FILE + default "iot-gate-imx8plus.dtb" + +config DEFAULT_DEVICE_TREE + default "iot-gate-imx8plus" + +config SYS_I2C_EEPROM_BUS + int + default 1 + +config SYS_I2C_EEPROM_ADDR + hex + default 0x50 + +config SYS_I2C_EEPROM_BUS_SB + hex + default 0x1 + +config SYS_I2C_EEPROM_ADDR_SB + hex + default 0x54 + +endif diff --git a/board/compulab/iot-gate-imx8plus/Makefile b/board/compulab/iot-gate-imx8plus/Makefile new file mode 100644 index 00000000000..21e316cb46f --- /dev/null +++ b/board/compulab/iot-gate-imx8plus/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2018 CompuLab +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mp/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += iot-gate-imx8plus.o +endif + +obj-y += ../plat/imx8mp/ +obj-y += ../plat/imx8/ diff --git a/board/compulab/iot-gate-imx8plus/iot-gate-imx8plus.c b/board/compulab/iot-gate-imx8plus/iot-gate-imx8plus.c new file mode 100644 index 00000000000..06ee6b54091 --- /dev/null +++ b/board/compulab/iot-gate-imx8plus/iot-gate-imx8plus.c @@ -0,0 +1,168 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS) +#include "../common/eeprom.h" +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + cl_eeprom_read_n_mac_addr(mac, dev_id, CONFIG_SYS_I2C_EEPROM_BUS); + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +} +#endif + +/* IOT-GATE-IMX8PLUS M.2 extension boards ID */ +typedef enum { + IOTG_IMX8PLUS_ADDON_FIRST, + IOTG_IMX8PLUS_ADDON_M2EMMC = IOTG_IMX8PLUS_ADDON_FIRST, /* eMMC+TPM module */ + IOTG_IMX8PLUS_ADDON_M2M2, /* M.2 slot+IMC+TPM module */ + IOTG_IMX8PLUS_ADDON_M2ADC, /* ADC+TPM module */ + IOTG_IMX8PLUS_ADDON_M2TPM, /* TPM module */ + IOTG_IMX8PLUS_ADDON_EMPTY, + IOTG_IMX8PLUS_ADDON_LAST = IOTG_IMX8PLUS_ADDON_EMPTY, + IOTG_IMX8PLUS_ADDON_NUM, +} iotg_imx8plus_addon_type; + +static char *iotg_imx8plus_addon_type_name[IOTG_IMX8PLUS_ADDON_NUM] = { + [IOTG_IMX8PLUS_ADDON_M2EMMC] = "M2EMMC", + [IOTG_IMX8PLUS_ADDON_M2M2] = "M2M2", + [IOTG_IMX8PLUS_ADDON_M2ADC] = "M2ADC", + [IOTG_IMX8PLUS_ADDON_M2TPM] = "M2TPM", + [IOTG_IMX8PLUS_ADDON_EMPTY] = "none", +}; + +/* Device tree names array */ +static char *iotg_imx8plus_dtb[IOTG_IMX8PLUS_ADDON_NUM] = { + [IOTG_IMX8PLUS_ADDON_M2EMMC] = "iot-gate-imx8plus-m2emmc.dtb", + [IOTG_IMX8PLUS_ADDON_M2M2] = "iot-gate-imx8plus-m2m2.dtb", + [IOTG_IMX8PLUS_ADDON_M2ADC] = "iot-gate-imx8plus-m2adc.dtb", + [IOTG_IMX8PLUS_ADDON_M2TPM] = "iot-gate-imx8plus-m2tpm.dtb", + [IOTG_IMX8PLUS_ADDON_EMPTY] = "iot-gate-imx8plus.dtb", +}; + +/* I2C bus numbers array */ +static int iotg_imx8plus_addon_i2c_bus[IOTG_IMX8PLUS_ADDON_LAST] = { + [IOTG_IMX8PLUS_ADDON_M2EMMC] = 4, + [IOTG_IMX8PLUS_ADDON_M2M2] = 4, + [IOTG_IMX8PLUS_ADDON_M2ADC] = 4, + [IOTG_IMX8PLUS_ADDON_M2TPM] = 4, +}; + +/* I2C device addresses array */ +static uint iotg_imx8plus_addon_i2c_addr[IOTG_IMX8PLUS_ADDON_LAST] = { + [IOTG_IMX8PLUS_ADDON_M2EMMC] = 0x20, + [IOTG_IMX8PLUS_ADDON_M2M2] = 0x21, + [IOTG_IMX8PLUS_ADDON_M2ADC] = 0x48, + [IOTG_IMX8PLUS_ADDON_M2TPM] = 0x54, +}; + +/* Extension board type detected */ +static int iotg_imx8plus_addon_id = IOTG_IMX8PLUS_ADDON_EMPTY; + +#define IOTG_IMX8PLUS_ENV_FDT_FILE "fdtfile" +#define IOTG_IMX8PLUS_ENV_ADDON_SETUP "addon_smart_setup" +#define IOTG_IMX8PLUS_ENV_ADDON_BOARD "addon_board" + +#define EMMC_SIZE(_detval) ((_detval & 0xf) << 4) + +/* + * iotg_imx8plus_detect_addon() - extended add-on board detection + * The detection is done according to the detected I2C devices. + */ +static void iotg_imx8plus_detect_addon(void) +{ + int ret; + struct udevice *i2c_bus, *i2c_dev; + int type; + + for (type = IOTG_IMX8PLUS_ADDON_FIRST; type < IOTG_IMX8PLUS_ADDON_LAST; type++) { + debug("%s: type_idx = %d, probing I2C bus %d\n", __func__, type, iotg_imx8plus_addon_i2c_bus[type]); + ret = uclass_get_device_by_seq(UCLASS_I2C, iotg_imx8plus_addon_i2c_bus[type], &i2c_bus); + if (ret) { + debug("%s: Failed probing I2C bus %d\n", __func__, iotg_imx8plus_addon_i2c_bus[type]); + continue; + } + + debug("%s: type_idx = %d, probing I2C addr = %d\n", __func__, type, iotg_imx8plus_addon_i2c_addr[type]); + ret = dm_i2c_probe(i2c_bus, iotg_imx8plus_addon_i2c_addr[type], 0, &i2c_dev); + if (!ret) { + iotg_imx8plus_addon_id = type; + debug("%s: detected module type_idx = %d, type_name = %s\n", __func__, type, + iotg_imx8plus_addon_type_name[type]); + printf("Add-on Board: %s", iotg_imx8plus_addon_type_name[type]); + if (type == IOTG_IMX8PLUS_ADDON_M2EMMC) { + /* Detect eMMC size: read offset 0 (Input port 0 reg) and inspect 4 lower bits */ + ret = dm_i2c_reg_read(i2c_dev, 0); + printf("(%dG)", EMMC_SIZE(ret)); + } + printf("\n"); + env_set(IOTG_IMX8PLUS_ENV_ADDON_BOARD, iotg_imx8plus_addon_type_name[type]); + + return; + } + } + + env_set(IOTG_IMX8PLUS_ENV_ADDON_BOARD, iotg_imx8plus_addon_type_name[IOTG_IMX8PLUS_ADDON_EMPTY]); +} + +/* + * iot_gate_imx8plus_select_dtb() - select the kernel device tree blob + * The device tree blob is selected according to the detected add-on board. + */ +static void iotg_imx8plus_select_dtb(void) +{ + if (!env_get_yesno(IOTG_IMX8PLUS_ENV_ADDON_SETUP)) + return; + + debug("%s: set %s = %s\n", __func__, IOTG_IMX8PLUS_ENV_FDT_FILE, + iotg_imx8plus_dtb[iotg_imx8plus_addon_id]); + env_set(IOTG_IMX8PLUS_ENV_FDT_FILE, + iotg_imx8plus_dtb[iotg_imx8plus_addon_id]); +} + +void board_vendor_late_init(void) { +#ifdef CONFIG_ADDON_SMART_SETUP + /* Check feature strategy and set to default if not defined explicitly */ + if (env_get_yesno(IOTG_IMX8PLUS_ENV_ADDON_SETUP) == -1) { + #ifdef CONFIG_ADDON_SMART_SETUP_DEFAULT_ON + env_set(IOTG_IMX8PLUS_ENV_ADDON_SETUP, "yes"); + #else + env_set(IOTG_IMX8PLUS_ENV_ADDON_SETUP, "no"); + #endif + } + + /* Detect extension module in M.2 expantion connector */ + iotg_imx8plus_detect_addon(); + /* Apply an appropriate dtb */ + iotg_imx8plus_select_dtb(); +#endif +} diff --git a/board/compulab/iot-gate-imx8plus/spl.c b/board/compulab/iot-gate-imx8plus/spl.c new file mode 100644 index 00000000000..b2fe004bdc1 --- /dev/null +++ b/board/compulab/iot-gate-imx8plus/spl.c @@ -0,0 +1,9 @@ +#include +#include +#include +#include +#include + +int spl_board_private_init(void) { + return 0; +} diff --git a/board/compulab/iotdin-imx8p/Kconfig b/board/compulab/iotdin-imx8p/Kconfig new file mode 100644 index 00000000000..3eea90d0c28 --- /dev/null +++ b/board/compulab/iotdin-imx8p/Kconfig @@ -0,0 +1,38 @@ +if TARGET_IOTDIN_IMX8P + +config SYS_BOARD + default "iotdin-imx8p" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "iotdin-imx8p" + +config DEFAULT_DTB + string + default "iotdin-imx8p.dtb" + +config DEFAULT_FDT_FILE + default "iotdin-imx8p.dtb" + +config DEFAULT_DEVICE_TREE + default "iotdin-imx8p" + +config SYS_I2C_EEPROM_BUS + int + default 1 + +config SYS_I2C_EEPROM_ADDR + hex + default 0x50 + +config SYS_I2C_EEPROM_BUS_SB + hex + default 0x2 + +config SYS_I2C_EEPROM_ADDR_SB + hex + default 0x50 + +endif diff --git a/board/compulab/iotdin-imx8p/Makefile b/board/compulab/iotdin-imx8p/Makefile new file mode 100644 index 00000000000..0c0a1f1b0a5 --- /dev/null +++ b/board/compulab/iotdin-imx8p/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2024 CompuLab +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mp/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += iotdin-imx8p.o +endif + +obj-y += ../plat/imx8mp/ +obj-y += ../plat/imx8/ diff --git a/board/compulab/iotdin-imx8p/iotdin-imx8p.c b/board/compulab/iotdin-imx8p/iotdin-imx8p.c new file mode 100644 index 00000000000..3a7a83ffa71 --- /dev/null +++ b/board/compulab/iotdin-imx8p/iotdin-imx8p.c @@ -0,0 +1,42 @@ +/* + * Copyright 2024 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS) +#include "../common/eeprom.h" +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + cl_eeprom_read_n_mac_addr(mac, dev_id, CONFIG_SYS_I2C_EEPROM_BUS); + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +} +#endif + diff --git a/board/compulab/iotdin-imx8p/spl.c b/board/compulab/iotdin-imx8p/spl.c new file mode 100644 index 00000000000..b2fe004bdc1 --- /dev/null +++ b/board/compulab/iotdin-imx8p/spl.c @@ -0,0 +1,9 @@ +#include +#include +#include +#include +#include + +int spl_board_private_init(void) { + return 0; +} diff --git a/board/compulab/mcm-imx8m-mini/Kconfig b/board/compulab/mcm-imx8m-mini/Kconfig new file mode 100644 index 00000000000..d11480b5570 --- /dev/null +++ b/board/compulab/mcm-imx8m-mini/Kconfig @@ -0,0 +1,16 @@ +if TARGET_MCM_IMX8M_MINI + +config SYS_BOARD + default "mcm-imx8m-mini" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "mcm-imx8m-mini" + +config DEFAULT_DTB + depends on TARGET_MCM_IMX8M_MINI + default "sbc-mcm-imx8m-mini.dtb" + +endif diff --git a/board/compulab/mcm-imx8m-mini/Makefile b/board/compulab/mcm-imx8m-mini/Makefile new file mode 100644 index 00000000000..906eff02bd4 --- /dev/null +++ b/board/compulab/mcm-imx8m-mini/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2018 CompuLab +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mm/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += mcm-imx8m-mini.o +endif + +obj-y += ../plat/imx8mm/ +obj-y += ../plat/imx8/ diff --git a/board/compulab/mcm-imx8m-mini/mcm-imx8m-mini.c b/board/compulab/mcm-imx8m-mini/mcm-imx8m-mini.c new file mode 100644 index 00000000000..bd863f154f2 --- /dev/null +++ b/board/compulab/mcm-imx8m-mini/mcm-imx8m-mini.c @@ -0,0 +1,34 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int uboot_board_private_init(void) { + return 0; +} diff --git a/board/compulab/mcm-imx8m-mini/spl.c b/board/compulab/mcm-imx8m-mini/spl.c new file mode 100644 index 00000000000..1a208e09a41 --- /dev/null +++ b/board/compulab/mcm-imx8m-mini/spl.c @@ -0,0 +1,19 @@ +#include +#include +#include +#include +#include + +int spl_board_private_init(void) { + return 0; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/board/compulab/mcm-imx8m-plus/Kconfig b/board/compulab/mcm-imx8m-plus/Kconfig new file mode 100644 index 00000000000..982c9bcabaf --- /dev/null +++ b/board/compulab/mcm-imx8m-plus/Kconfig @@ -0,0 +1,45 @@ +if TARGET_MCM_IMX8M_PLUS + +config SYS_BOARD + default "mcm-imx8m-plus" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "mcm-imx8m-plus" + +config DEFAULT_DTB + string + default "mcm-imx8m-plus.dtb" + + +config DEFAULT_FDT_FILE + string + default "mcm-imx8m-plus.dtb" + +config DEFAULT_DEVICE_TREE + string + default "mcm-imx8m-plus" + +config SYS_I2C_EEPROM_BUS + int + default 1 + +config SYS_I2C_EEPROM_ADDR + hex + default 0x50 + +config SYS_I2C_EEPROM_BUS_SB + hex + default 0x1 + +config SYS_I2C_EEPROM_ADDR_SB + hex + default 0x54 + +config COMPULAB_DEBUG_UART1 + bool "System Debug UART1" + default false + +endif diff --git a/board/compulab/mcm-imx8m-plus/Makefile b/board/compulab/mcm-imx8m-plus/Makefile new file mode 100644 index 00000000000..6a25e77474f --- /dev/null +++ b/board/compulab/mcm-imx8m-plus/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2018 CompuLab +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mp/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += mcm-imx8m-plus.o +endif + +obj-y += ../plat/imx8mp/ +obj-y += ../plat/imx8/ diff --git a/board/compulab/mcm-imx8m-plus/mcm-imx8m-plus.c b/board/compulab/mcm-imx8m-plus/mcm-imx8m-plus.c new file mode 100644 index 00000000000..3b3ec6a9120 --- /dev/null +++ b/board/compulab/mcm-imx8m-plus/mcm-imx8m-plus.c @@ -0,0 +1,41 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS) +#include "../common/eeprom.h" +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + cl_eeprom_read_n_mac_addr(mac, /*dev_id*/ 0, CONFIG_SYS_I2C_EEPROM_BUS); + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +} +#endif diff --git a/board/compulab/mcm-imx8m-plus/spl.c b/board/compulab/mcm-imx8m-plus/spl.c new file mode 100644 index 00000000000..a2e83cb8836 --- /dev/null +++ b/board/compulab/mcm-imx8m-plus/spl.c @@ -0,0 +1,10 @@ +#include +#include +#include +#include +#include + +int spl_board_private_init(void) +{ + return 0; +} diff --git a/board/compulab/plat/Kconfig b/board/compulab/plat/Kconfig new file mode 100644 index 00000000000..5db1d9bafec --- /dev/null +++ b/board/compulab/plat/Kconfig @@ -0,0 +1,140 @@ +choice + prompt "CompuLab i.MX8M select" + +config TARGET_UCM_IMX8M_MINI + bool "CompuLab ucm-imx8m-mini" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_MCM_IMX8M_MINI + bool "CompuLab mcm-imx8m-mini" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IOT_GATE_IMX8 + bool "CompuLab iot-gate-imx8" + select IMX8MM + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_UCM_IMX8M_PLUS + bool "CompuLab ucm-imx8m-plus" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_MCM_IMX8M_PLUS + bool "CompuLab mcm-imx8m-plus" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_SOM_IMX8M_PLUS + bool "CompuLab som-imx8m-plus" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IOT_GATE_IMX8PLUS + bool "CompuLab iot-gate-imx8plus" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IOTDIN_IMX8P + bool "CompuLab iotdin-imx8p" + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 +endchoice + +if TARGET_IOT_GATE_IMX8PLUS || TARGET_SOM_IMX8M_PLUS || TARGET_UCM_IMX8M_PLUS || TARGET_MCM_IMX8M_PLUS || TARGET_IOTDIN_IMX8P + +config IMX_FLASH_BIN + bool + default y + select USE_SPL_FIT_GENERATOR + +config SPL_FIT_GENERATOR + string + default "arch/arm/mach-imx/mkimage_fit_atf.sh" + +endif + +menu "Compulab i.MX8MM platform features" + depends on TARGET_UCM_IMX8M_MINI || TARGET_MCM_IMX8M_MINI || TARGET_IOT_GATE_IMX8 + +config SPL_REPORT_FAKE_MEMSIZE + bool "SPL passes a fake DRAM size to U-Boot" + default n + help + SPL passes to the U-Boot a value from EEPROM instead of a real memory + size. For debug purposes ONLY!!! + +endmenu + +menu "Compulab i.MX8MP platform features" + depends on TARGET_SOM_IMX8M_PLUS || TARGET_UCM_IMX8M_PLUS || TARGET_IOT_GATE_IMX8PLUS || TARGET_MCM_IMX8M_PLUS || TARGET_IOTDIN_IMX8P + +config DRAM_D2D4 + bool "Enable D2D4 or D1D8 dram support" + default y + help + If 'Y' then support for D2 and D4 configuration is enabled + else support for D1 and D8 configuration is enabled + +menu "Compulab IOT-GATE-IMX8PLUS features" + depends on TARGET_IOT_GATE_IMX8PLUS + +config ADDON_SMART_SETUP + bool "CompuLab i.MX8M-Plus Add-on Board Smart Setup" + default y + help + CompuLab i.MX8M-Plus Add-on Board Smart Setup feature allows detecting an extension board + and enabling it in Linux kernel by choosing a proper device tree + +choice + prompt "Select Add-on Board Smart Setup default strategy" + + depends on ADDON_SMART_SETUP + help + Choose a default strategy for CompuLab i.MX8M-Plus Add-on Board Smart Setup: either Enabled or Disabled. + The default strategy can be overriden by "addon_smart_setup" environment variable + +config ADDON_SMART_SETUP_DEFAULT_OFF + bool "Disabled" + help + Do not enable add-on boards in Linux kernel by default. + Can be overriden by setting "addon_smart_setup" environment variable + to the true value (1/Y/y/T/t) + +config ADDON_SMART_SETUP_DEFAULT_ON + bool "Enabled" + help + Detect an add-on board type and enaible it in Linux kernel by default. + Can be overriden by setting "addon_smart_setup" environment variable + to the false value (neither one of following: 1/Y/y/T/t) + +endchoice +endmenu + +config ATF_LOAD_ADDR + hex + default 0x00970000 + +config TEE_LOAD_ADDR + hex + default 0x56000000 + +endmenu + +source "board/compulab/ucm-imx8m-mini/Kconfig" +source "board/compulab/mcm-imx8m-mini/Kconfig" +source "board/compulab/iot-gate-imx8/Kconfig" +source "board/compulab/ucm-imx8m-plus/Kconfig" +source "board/compulab/mcm-imx8m-plus/Kconfig" +source "board/compulab/som-imx8m-plus/Kconfig" +source "board/compulab/iot-gate-imx8plus/Kconfig" +source "board/compulab/iotdin-imx8p/Kconfig" diff --git a/board/compulab/plat/imx8/Makefile b/board/compulab/plat/imx8/Makefile new file mode 100644 index 00000000000..9d3044cb9e9 --- /dev/null +++ b/board/compulab/plat/imx8/Makefile @@ -0,0 +1 @@ +obj-y += eeprom/ diff --git a/board/compulab/plat/imx8/eeprom/Makefile b/board/compulab/plat/imx8/eeprom/Makefile new file mode 100644 index 00000000000..62ee6de6fa2 --- /dev/null +++ b/board/compulab/plat/imx8/eeprom/Makefile @@ -0,0 +1 @@ +obj-y += eeprom_spl.o diff --git a/board/compulab/plat/imx8/eeprom/eeprom_spl.c b/board/compulab/plat/imx8/eeprom/eeprom_spl.c new file mode 100644 index 00000000000..0e030475c16 --- /dev/null +++ b/board/compulab/plat/imx8/eeprom/eeprom_spl.c @@ -0,0 +1,225 @@ +/* + * (C) Copyright 2019 CompuLab, Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SPL_BUILD + +#define CONFIG_SYS_I2C_EEPROM_ADDR_P1 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +#ifndef CONFIG_SYS_I2C_EEPROM_BUS +#define CONFIG_SYS_I2C_EEPROM_BUS 1 +#endif + +static iomux_v3_cfg_t const eeprom_pads[] = { + IMX8MQ_PAD_GPIO1_IO13__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define EEPROM_WP_GPIO IMX_GPIO_NR(1, 13) + +static void cl_eeprom_we(int enable) +{ + static int done = 0; + + if (done) { + gpio_direction_output(EEPROM_WP_GPIO, enable); + return; + } + + imx_iomux_v3_setup_multiple_pads( + eeprom_pads, ARRAY_SIZE(eeprom_pads)); + gpio_request(EEPROM_WP_GPIO, "eeprom_wp"); + gpio_direction_output(EEPROM_WP_GPIO, enable); + done = 1; +} + +struct eeprom_path { + int bus; + uint8_t chip; +}; + +static const struct eeprom_path eeprom_som = { + CONFIG_SYS_I2C_EEPROM_BUS, + CONFIG_SYS_I2C_EEPROM_ADDR_P1, +}; + +static const struct eeprom_path *working_eeprom; + +static struct udevice *g_dev = NULL; + +static int cpl_eeprom_init(void) { + + struct udevice *bus, *dev; + int ret; + + if (!g_dev) { + + working_eeprom = &eeprom_som; + ret = uclass_get_device_by_seq(UCLASS_I2C, working_eeprom->bus, &bus); + if (ret) { + printf("%s: No bus %d\n", __func__, working_eeprom->bus); + return ret; + } + + ret = dm_i2c_probe(bus, working_eeprom->chip, 0, &dev); + if (ret) { + printf("%s: Can't find device id=0x%x, on bus %d\n", + __func__, working_eeprom->chip, working_eeprom->bus); + return ret; + } + + /* Init */ + g_dev = dev; + } + + return 0; +} + +static int cl_eeprom_read(uint offset, uchar *buf, int len) +{ + int res; + + res = cpl_eeprom_init(); + if (res < 0) + return res; + + res = dm_i2c_read(g_dev, offset, buf, len); + + return res; +} + +static int cl_eeprom_write(uint offset, uchar *buf, int len) +{ + int res; + + res = cpl_eeprom_init(); + if (res < 0) + return res; + + cl_eeprom_we(1); + + res = dm_i2c_write(g_dev, offset, buf, len); + + return res; +} + +/* Reserved for fututre use area */ +#define BOARD_DDRINFO_OFFSET 0x40 +#define BOARD_DDRINFO_SIZE 4 +static u32 board_ddrinfo = 0xdeadbeef; + +#define BOARD_DDRSUBIND_OFFSET 0x44 +#define BOARD_DDRSUBIND_SIZE 1 +static u8 board_ddrsubind = 0xff; + +#define BOARD_DRATE_OFFSET 0x50 +#define BOARD_DRATE_SIZE 4 +static u32 board_drate = 0xdeadbeef; + +#ifdef CONFIG_SPL_REPORT_FAKE_MEMSIZE +#define BOARD_OSIZE_OFFSET 0x80 +#define BOARD_OSIZE_SIZE 4 +static u32 board_osize = 0xdeadbeef; +#endif + +#define BOARD_DDRINFO_VALID(A) (A != 0xdeadbeef) + +u32 cl_eeprom_get_ddrinfo(void) +{ + if (!BOARD_DDRINFO_VALID(board_ddrinfo)) { + if (cl_eeprom_read(BOARD_DDRINFO_OFFSET, (uchar *)&board_ddrinfo, BOARD_DDRINFO_SIZE)) + return 0; + } + return board_ddrinfo; +}; + +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo) +{ + if (cl_eeprom_write(BOARD_DDRINFO_OFFSET, (uchar *)&ddrinfo, BOARD_DDRINFO_SIZE)) + return 0; + + board_ddrinfo = ddrinfo; + + return board_ddrinfo; +}; + +#define DRATE_OFFSET(R,C) (BOARD_DRATE_OFFSET + ( 0x10 * (R) ) + ( (C) << 2 )) +u32 cl_eeprom_get_drate(unsigned int r, unsigned int c) +{ + if (cl_eeprom_read(DRATE_OFFSET(r,c) , (uchar *)&board_drate, BOARD_DRATE_SIZE)) + return 0; + + return board_drate; +}; + +u32 cl_eeprom_set_drate(u32 drate, unsigned int r, unsigned int c) +{ + if (cl_eeprom_write(DRATE_OFFSET(r,c), (uchar *)&drate, BOARD_DRATE_SIZE)) + return 0; + + board_drate = drate; + + udelay(5000); + + return board_drate; +}; + +u8 cl_eeprom_get_subind(void) +{ + if (cl_eeprom_read(BOARD_DDRSUBIND_OFFSET, (uchar *)&board_ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + + return board_ddrsubind; +}; + +u8 cl_eeprom_set_subind(u8 ddrsubind) +{ + if (cl_eeprom_write(BOARD_DDRSUBIND_OFFSET, (uchar *)&ddrsubind, BOARD_DDRSUBIND_SIZE)) + return 0xff; + board_ddrsubind = ddrsubind; + + return board_ddrsubind; +}; + +#ifdef CONFIG_SPL_REPORT_FAKE_MEMSIZE +/* override-size ifaces */ +u32 cl_eeprom_get_osize(void) +{ + if (cl_eeprom_read(BOARD_OSIZE_OFFSET, (uchar *)&board_osize, BOARD_OSIZE_SIZE)) + return 0; + + return board_osize; +}; + +u32 cl_eeprom_set_osize(u32 osize) +{ + if (cl_eeprom_write(BOARD_OSIZE_OFFSET, (uchar *)&osize, BOARD_OSIZE_SIZE)) + return 0; + + board_osize = osize; + + return board_osize; +}; +#endif //CONFIG_SPL_REPORT_FAKE_MEMSIZE + +int cl_eeprom_buffer_write(uint offset, uchar *buf, int len) { + return cl_eeprom_write(offset, buf, len); +} + +int cl_eeprom_buffer_read(uint offset, uchar *buf, int len) { + return cl_eeprom_read(offset, buf, len); +} + +#endif diff --git a/board/compulab/plat/imx8mm/Makefile b/board/compulab/plat/imx8mm/Makefile new file mode 100644 index 00000000000..15ce6673575 --- /dev/null +++ b/board/compulab/plat/imx8mm/Makefile @@ -0,0 +1,3 @@ +obj-y += ddr/ +obj-y += spl/ +obj-y += board/ diff --git a/board/compulab/plat/imx8mm/board/Makefile b/board/compulab/plat/imx8mm/board/Makefile new file mode 100644 index 00000000000..8c507270526 --- /dev/null +++ b/board/compulab/plat/imx8mm/board/Makefile @@ -0,0 +1,4 @@ +ccflags-y += -I$(srctree)/board/compulab/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mm/ + +obj-y += board.o diff --git a/board/compulab/plat/imx8mm/board/board.c b/board/compulab/plat/imx8mm/board/board.c new file mode 100644 index 00000000000..13bb161e515 --- /dev/null +++ b/board/compulab/plat/imx8mm/board/board.c @@ -0,0 +1,398 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr/ddr.h" +#include "common/eeprom.h" +#include "common/rtc.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int env_dev = -1; +static int env_part= -1; + +#ifdef CONFIG_BOARD_POSTCLK_INIT +int board_postclk_init(void) +{ + /* TODO */ + return 0; +} +#endif +int board_phys_sdram_size(phys_size_t *size) +{ + struct lpddr4_tcm_desc *lpddr4_tcm_desc = (struct lpddr4_tcm_desc *) TCM_DATA_CFG; + + switch (lpddr4_tcm_desc->size) { + case 4096: + case 2048: + case 1024: + *size = (1L << 20) * lpddr4_tcm_desc->size; + break; + default: + printf("%s: DRAM size %uM is not supported \n", __func__, + lpddr4_tcm_desc->size); + while ( 1 ) {}; + break; + }; + return 0; +} + /* Get the top of usable RAM */ +ulong board_get_usable_ram_top(ulong total_size) +{ + + if(gd->ram_top > 0x100000000) + gd->ram_top = 0x100000000; + + return gd->ram_top; +} + +int dram_init(void) +{ + phys_size_t sdram_size; + int ret; + ret = board_phys_sdram_size(&sdram_size); + if (ret) + return ret; + + /* rom_pointer[1] contains the size of TEE occupies */ + gd->ram_size = sdram_size - rom_pointer[1]; + + return 0; +} + +#ifdef CONFIG_OF_BOARD_SETUP +static void fdt_set_sn(void *blob) +{ + u32 rev; + char buf[100]; + int len; + union { + struct tag_serialnr s; + u64 u; + } serialnr; + + len = cl_eeprom_read_som_name(buf); + fdt_setprop(blob, 0, "product-name", buf, len); + + len = cl_eeprom_read_sb_name(buf); + fdt_setprop(blob, 0, "baseboard-name", buf, len); + + cpl_get_som_serial(&serialnr.s); + fdt_setprop(blob, 0, "product-sn", buf, sprintf(buf, "%llx", serialnr.u) + 1); + + cpl_get_sb_serial(&serialnr.s); + fdt_setprop(blob, 0, "baseboard-sn", buf, sprintf(buf, "%llx", serialnr.u) + 1); + + rev = cl_eeprom_get_som_revision(); + fdt_setprop(blob, 0, "product-revision", buf, + sprintf(buf, "%u.%02u", rev/100 , rev%100 ) + 1); + + rev = cl_eeprom_get_sb_revision(); + fdt_setprop(blob, 0, "baseboard-revision", buf, + sprintf(buf, "%u.%02u", rev/100 , rev%100 ) + 1); + + len = cl_eeprom_read_som_options(buf); + fdt_setprop(blob, 0, "product-options", buf, len); + + len = cl_eeprom_read_sb_options(buf); + fdt_setprop(blob, 0, "baseboard-options", buf, len); + + return; +} + +static int fdt_set_env_addr(void *blob) +{ + char tmp[32]; + int nodeoff = fdt_add_subnode(blob, 0, "fw_env"); + if(0 > nodeoff) + return nodeoff; + + fdt_setprop(blob, nodeoff, "env_off", tmp, sprintf(tmp, "0x%x", CONFIG_ENV_OFFSET)); + fdt_setprop(blob, nodeoff, "env_size", tmp, sprintf(tmp, "0x%x", CONFIG_ENV_SIZE)); + if(0 < env_dev) { + switch(env_part) { + case 1 ... 2: + fdt_setprop(blob, nodeoff, "env_dev", tmp, sprintf(tmp, "/dev/mmcblk%iboot%i", env_dev, env_part - 1)); + break; + default: + fdt_setprop(blob, nodeoff, "env_dev", tmp, sprintf(tmp, "/dev/mmcblk%i", env_dev)); + break; + } + } + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + fdt_set_env_addr(blob); + fdt_set_sn(blob); + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +#define FEC_RST_PAD IMX_GPIO_NR(1, 10) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(FEC_RST_PAD, "fec1_rst"); + gpio_direction_output(FEC_RST_PAD, 0); + udelay(500); + gpio_direction_output(FEC_RST_PAD, 1); +} + +/* + * setup_mac_address() - set Ethernet MAC address environment. + * + * @return: 0 on success, -1 on failure + */ +static int setup_mac_address(void) +{ + int ret; + unsigned char enetaddr[6]; + + ret = eth_env_get_enetaddr("ethaddr", enetaddr); + if (ret) + return 0; + + ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); + if (ret) + return ret; + + ret = is_valid_ethaddr(enetaddr); + if (!ret) + return -1; + + ret = eth_env_set_enetaddr("ethaddr", enetaddr); + if (ret) + return -1; + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); + return set_clk_enet(ENET_125MHZ); +} + +int board_phy_config(struct phy_device *phydev) +{ + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_usb_init(int index, enum usb_init_type init) +{ + debug("board_usb_init %d, type %d\n", index, init); + + imx8m_usb_power(index, true); + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + debug("board_usb_cleanup %d, type %d\n", index, init); + + imx8m_usb_power(index, false); + + return 0; +} + +__weak int uboot_board_private_init(void) { + return 0; +} + +static void show_suite_info(void) +{ + char *buf = malloc(200); //More than necessary + + if(!buf) { + printf("%s: Not enough memory\n", __func__); + return; + } + + cl_eeprom_get_suite(buf); + printf("Suite:\t%s\n", buf); + + free(buf); + return; +} + +static void disable_rtc_bus_on_battery(void) +{ + struct udevice *bus, *dev; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, CONFIG_SYS_I2C_RTC_BUS, &bus); + if (ret) { + printf("%s: No bus %d\n", __func__, CONFIG_SYS_I2C_RTC_BUS); + return; + } + + ret = dm_i2c_probe(bus, CONFIG_SYS_I2C_RTC_ADDR, 0, &dev); + if (ret) { + printf("%s: Can't find device id=0x%x, on bus %d\n", + __func__, CONFIG_SYS_I2C_RTC_BUS, CONFIG_SYS_I2C_RTC_ADDR); + return; + } + + if((ret = dm_i2c_reg_write(dev, ABX8XX_REG_CFG_KEY, ABX8XX_CFG_KEY_MISC)) || + (ret = dm_i2c_reg_write(dev, ABX8XX_REG_BATMODE, ABX8XX_BATMODE_IOBM_NOT))) + printf("%s: i2c write error %d\n", __func__, ret); + + return; +} + +int board_init(void) +{ + + disable_rtc_bus_on_battery(); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + if (uboot_board_private_init()) { + printf("uboot_board_private_init() failed\n"); + hang(); + } + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + + show_suite_info(); + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + const ulong user_env_devno = env_get_hex("env_dev", ULONG_MAX); + if (user_env_devno != ULONG_MAX) { + printf("User Environment dev# is (%lu)\n", user_env_devno); + return (int)user_env_devno; + } + return devno; +} + +static int _mmc_get_env_part(struct mmc *mmc) +{ + const ulong user_env_part = env_get_hex("env_part", ULONG_MAX); + if (user_env_part != ULONG_MAX) { + printf("User Environment part# is (%lu)\n", user_env_part); + return (int)user_env_part; + } + + return EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); +} + +uint mmc_get_env_part(struct mmc *mmc) +{ + if (mmc->part_support && mmc->part_config != MMCPART_NOAVAILABLE) { + uint partno = _mmc_get_env_part(mmc); + env_part = partno; + return partno; + } + return 0; +} + +static void board_bootdev_init(void) +{ + u32 bootdev = get_boot_device(); + struct mmc *mmc; + + switch (bootdev) { + case MMC3_BOOT: + bootdev = 2; + break; + case SD2_BOOT: + bootdev = 1; + break; + default: + env_set("bootdev", NULL); + return; + } + + env_dev = bootdev; + + mmc = find_mmc_device(bootdev); + if (mmc && mmc->part_support && mmc->part_config != MMCPART_NOAVAILABLE) + env_part = EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config); + + env_set_ulong("bootdev", bootdev); +} + +int board_late_init(void) +{ + int ret; + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); + board_bootdev_init(); +#endif + + ret = setup_mac_address(); + if (ret < 0) + printf("%s: Can't set MAC address\n", __func__); + + return 0; +} + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ diff --git a/board/compulab/plat/imx8mm/ddr/Makefile b/board/compulab/plat/imx8mm/ddr/Makefile new file mode 100644 index 00000000000..be4a6abd7a1 --- /dev/null +++ b/board/compulab/plat/imx8mm/ddr/Makefile @@ -0,0 +1,8 @@ +obj-y += ddr.o +obj-y += lpddr4_timing_ff020008.o +obj-y += lpddr4_timing_ff000110.o +obj-y += lpddr4_timing_01061010.o +obj-y += lpddr4_timing_01050008.o +ifndef CONFIG_TARGET_MCM_IMX8M_MINI +obj-y += lpddr4_timing_05000010.o +endif diff --git a/board/compulab/plat/imx8mm/ddr/ddr.c b/board/compulab/plat/imx8mm/ddr/ddr.c new file mode 100644 index 00000000000..31307b82575 --- /dev/null +++ b/board/compulab/plat/imx8mm/ddr/ddr.c @@ -0,0 +1,218 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +/* Forward declarations */ +u32 cl_eeprom_get_ddrinfo(void); +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo); +u32 cl_eeprom_get_subind(void); +u32 cl_eeprom_set_subind(u32 subind); + +#ifdef CONFIG_SPL_REPORT_FAKE_MEMSIZE +u32 cl_eeprom_get_osize(void); +#endif +static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) +{ + unsigned int tmp; + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); + } while ((tmp & 0x8) == 0); + tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + while(tmp) { //try to find a significant byte in the word + if(tmp & 0xff) { + tmp &= 0xff; + break; + } + tmp >>= 8; + } + return tmp; +} + +struct lpddr4_desc { + char name[16]; + unsigned int id; + unsigned int size; + unsigned int count; + /* an optional field + * use it if default is not the + * 1-st array entry */ + unsigned int _default; + /* An optional field to distiguish DRAM chips that + * have different geometry, though return the same MRR. + * Default value 0xff + */ + u8 subind; + struct dram_timing_info *timing; + char *desc[4]; +}; + +#define DEFAULT (('D' << 24) + ('E' << 16 ) + ( 'F' << 8 ) + 'A') +static const struct lpddr4_desc lpddr4_array[] = { +#ifdef CONFIG_TARGET_MCM_IMX8M_MINI + { .name = "Nanya", .id = 0x05000010, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, +#else + { .name = "Nanya", .id = 0x05000010, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_05000010}, +#endif + { .name = "Samsung", .id = 0x01061010, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, + { .name = "Samsung", .id = 0x01050008, .subind = 0xff, .size = 1024, .count = 1, .timing = &ucm_dram_timing_01050008}, + { .name = "Kingston", .id = 0xff000010, .subind = 0x04, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, + { .name = "Kingston", .id = 0xff000010, .subind = 0x02, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010}, + { .name = "Micron", .id = 0xff020008, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008}, + { .name = "Micron", .id = 0xff000110, .subind = 0xff, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110}, +}; + +static unsigned int lpddr4_get_mr(void) +{ + int i = 0, attempts = 5; + unsigned int ddr_info = 0; + unsigned int regs[] = { 5, 6, 7, 8 }; + + do { + for ( i = 0 ; i < ARRAY_SIZE(regs) ; i++ ) { + unsigned int data = 0; + data = lpddr4_mr_read(0xF, regs[i]); + ddr_info <<= 8; + ddr_info += (data & 0xFF); + } + if ((ddr_info != 0xFFFFFFFF) && (ddr_info != 0)) + break; // The attempt was successfull + } while ( --attempts ); + return ddr_info; +} + +static void spl_tcm_init(struct lpddr4_tcm_desc *lpddr4_tcm_desc) { + if (lpddr4_tcm_desc->sign == DEFAULT) + return; + + lpddr4_tcm_desc->sign = DEFAULT; + lpddr4_tcm_desc->index = 0; +} + +static void spl_tcm_fini(struct lpddr4_tcm_desc *lpddr4_tcm_desc) { + if (lpddr4_tcm_desc->sign != DEFAULT) + return; + + lpddr4_tcm_desc->sign = ~DEFAULT; + lpddr4_tcm_desc->index = 0; +} + +#define SPL_TCM_DATA 0x7e0000 +#define SPL_TCM_INIT spl_tcm_init(lpddr4_tcm_desc) +#define SPL_TCM_FINI spl_tcm_fini(lpddr4_tcm_desc) + +void spl_dram_init(void) +{ + unsigned int ddr_info = 0xdeadbeef; + unsigned int ddr_info_mrr = 0xdeadbeef; + unsigned int ddr_found = 0; + int i = 0; + + struct lpddr4_tcm_desc *lpddr4_tcm_desc = (struct lpddr4_tcm_desc *) SPL_TCM_DATA; + + if (lpddr4_tcm_desc->sign != DEFAULT) { + /* get ddr type from the eeprom if not in tcm scan mode */ + ddr_info = cl_eeprom_get_ddrinfo(); + for ( i = 0; i < ARRAY_SIZE(lpddr4_array); i++ ) { + if (lpddr4_array[i].id == ddr_info && + lpddr4_array[i].subind == cl_eeprom_get_subind()) { + ddr_found = 1; + break; + } + } + } + + /* Walk trought all available ddr ids and apply + * one by one. Save the index at the tcm memory that + * persists after the reset. + */ + if (ddr_found == 0) { + + SPL_TCM_INIT; + + if (lpddr4_tcm_desc->index < ARRAY_SIZE(lpddr4_array)) { + printf("DDRINFO: Cfg attempt: [ %d/%lu ]\n", lpddr4_tcm_desc->index+1, ARRAY_SIZE(lpddr4_array)); + i = lpddr4_tcm_desc->index; + lpddr4_tcm_desc->index += 1; + } else { + /* Ran out all available ddr setings */ + printf("DDRINFO: Ran out all [ %lu ] cfg attempts. A non supported configuration.\n", ARRAY_SIZE(lpddr4_array)); + while ( 1 ) {}; + } + ddr_info = lpddr4_array[i].id; + } else + + printf("DDRINFO(%s): %s %dG @ %d MHz\n", (ddr_found ? "D" : "?" ), lpddr4_array[i].name, + lpddr4_array[i].size, lpddr4_array[i].timing->fsp_table[0]); + + if (ddr_init(lpddr4_array[i].timing)) { + SPL_TCM_INIT; + do_reset(NULL,0,0,NULL); + } + + ddr_info_mrr = lpddr4_get_mr(); + if (ddr_info_mrr == 0xFFFFFFFF ) { + printf("DDRINFO(M): mr5-8 [ 0x%x ] is invalid; reset\n", ddr_info_mrr); + SPL_TCM_INIT; + do_reset(NULL,0,0,NULL); + } + + printf("DDRINFO(M): mr5-8 [ 0x%x ]\n", ddr_info_mrr); + printf("DDRINFO(%s): mr5-8 [ 0x%x ]\n", (ddr_found ? "E" : "T" ), ddr_info); + + if (ddr_info_mrr != ddr_info) { + SPL_TCM_INIT; + do_reset(NULL,0,0,NULL); + } + + SPL_TCM_FINI; + + if (ddr_found == 0) { + /* Update eeprom */ + cl_eeprom_set_ddrinfo(ddr_info_mrr); + mdelay(10); + ddr_info = cl_eeprom_get_ddrinfo(); + mdelay(10); + cl_eeprom_set_subind(lpddr4_array[i].subind); + /* make sure that the ddr_info has reached the eeprom */ + printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n", ddr_info); + if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind() != lpddr4_array[i].subind) { + printf("DDRINFO(EEPROM): make sure that the eeprom is accessible\n"); + printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x51 0x40 0x50\n"); + } + } +#ifdef CONFIG_SPL_REPORT_FAKE_MEMSIZE + /* Pass the dram size to th U-Boot through the tcm memory */ + { /* To figure out what to store into the TCM buffer */ + /* For debug purpouse only. To override the real memsize */ + unsigned int ddr_tcm_size = cl_eeprom_get_osize(); + if ((ddr_tcm_size == 0) || (ddr_tcm_size == -1)) + ddr_tcm_size = lpddr4_array[i].size; + + lpddr4_tcm_desc->size = ddr_tcm_size; + } +#else + lpddr4_tcm_desc->size = lpddr4_array[i].size; +#endif + +} diff --git a/board/compulab/plat/imx8mm/ddr/ddr.h b/board/compulab/plat/imx8mm/ddr/ddr.h new file mode 100644 index 00000000000..4901e826a8d --- /dev/null +++ b/board/compulab/plat/imx8mm/ddr/ddr.h @@ -0,0 +1,27 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +extern struct dram_timing_info ucm_dram_timing_ff020008; +extern struct dram_timing_info ucm_dram_timing_ff000110; +extern struct dram_timing_info ucm_dram_timing_01061010; +extern struct dram_timing_info ucm_dram_timing_01050008; +extern struct dram_timing_info ucm_dram_timing_05000010; + +void spl_dram_init(void); + +#define TCM_DATA_CFG 0x7e0000 + +struct lpddr4_tcm_desc { + unsigned int size; + unsigned int sign; + unsigned int index; + unsigned int count; +}; + +#endif diff --git a/board/compulab/plat/imx8mm/ddr/lpddr4_timing_01050008.c b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_01050008.c new file mode 100644 index 00000000000..54c3922de5d --- /dev/null +++ b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_01050008.c @@ -0,0 +1,1849 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa1080020}, + {0x3d400020,0x223}, + {0x3d400024,0x3a980}, + {0x3d400064,0x5b0087}, + {0x3d4000d0,0xc00305ba}, + {0x3d4000d4,0x940000}, + {0x3d4000dc,0xd4002d}, + {0x3d4000e0,0x310000}, + {0x3d4000e8,0x66004d}, + {0x3d4000ec,0x16004d}, + {0x3d400100,0x191e1920}, + {0x3d400104,0x60630}, + {0x3d40010c,0xb0b000}, + {0x3d400110,0xe04080e}, + {0x3d400114,0x2040c0c}, + {0x3d400118,0x1010007}, + {0x3d40011c,0x401}, + {0x3d400130,0x20600}, + {0x3d400134,0xc100002}, + {0x3d400138,0x8d}, + {0x3d400144,0x96004b}, + {0x3d400180,0x2ee0017}, + {0x3d400184,0x2605b8e}, + {0x3d400188,0x0}, + {0x3d400190,0x497820a}, + {0x3d400194,0x80303}, + {0x3d4001b4,0x170a}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x0}, + {0x3d4000f4,0xc99}, + {0x3d400108,0x70e1617}, + {0x3d400200,0x1f}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0xf070707}, + {0x3d400250,0x29001701}, + {0x3d400254,0x2c}, + {0x3d40025c,0x4000030}, + {0x3d400264,0x900093e7}, + {0x3d40026c,0x2005574}, + {0x3d400400,0x111}, + {0x3d400408,0x72ff}, + {0x3d400494,0x2100e07}, + {0x3d400498,0x620096}, + {0x3d40049c,0x1100e07}, + {0x3d4004a0,0xc8012c}, + {0x3d402020,0x21}, + {0x3d402024,0x7d00}, + {0x3d402050,0x20d040}, + {0x3d402064,0xc0012}, + {0x3d4020dc,0x840000}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004d}, + {0x3d4020ec,0x16004d}, + {0x3d402100,0xa040305}, + {0x3d402104,0x30407}, + {0x3d402108,0x203060b}, + {0x3d40210c,0x505000}, + {0x3d402110,0x2040202}, + {0x3d402114,0x2030202}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x13}, + {0x3d402144,0x14000a}, + {0x3d402180,0x640004}, + {0x3d402190,0x3818200}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x100}, + {0x3d403020,0x21}, + {0x3d403024,0x1f40}, + {0x3d403050,0x20d040}, + {0x3d403064,0x30005}, + {0x3d4030dc,0x840000}, + {0x3d4030e0,0x310000}, + {0x3d4030e8,0x66004d}, + {0x3d4030ec,0x16004d}, + {0x3d403100,0xa010102}, + {0x3d403104,0x30404}, + {0x3d403108,0x203060b}, + {0x3d40310c,0x505000}, + {0x3d403110,0x2040202}, + {0x3d403114,0x2030202}, + {0x3d403118,0x1010004}, + {0x3d40311c,0x301}, + {0x3d403130,0x20300}, + {0x3d403134,0xa100002}, + {0x3d403138,0x5}, + {0x3d403144,0x50003}, + {0x3d403180,0x190004}, + {0x3d403190,0x3818200}, + {0x3d403194,0x80303}, + {0x3d4031b4,0x100}, + {0x3d400028,0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x0}, + {0x110a1,0x1}, + {0x110a2,0x3}, + {0x110a3,0x4}, + {0x110a4,0x5}, + {0x110a5,0x2}, + {0x110a6,0x7}, + {0x110a7,0x6}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x3}, + {0x120a3,0x2}, + {0x120a4,0x5}, + {0x120a5,0x4}, + {0x120a6,0x7}, + {0x120a7,0x6}, + {0x130a0,0x0}, + {0x130a1,0x1}, + {0x130a2,0x2}, + {0x130a3,0x3}, + {0x130a4,0x4}, + {0x130a5,0x5}, + {0x130a6,0x6}, + {0x130a7,0x7}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x21005f,0x1ff}, + {0x21015f,0x1ff}, + {0x21105f,0x1ff}, + {0x21115f,0x1ff}, + {0x21205f,0x1ff}, + {0x21215f,0x1ff}, + {0x21305f,0x1ff}, + {0x21315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0x19}, + {0x1200c5,0x7}, + {0x2200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x2}, + {0x22002e,0x2}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x290204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x220024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x3}, + {0x120056,0xa}, + {0x220056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x21004d,0xe00}, + {0x21014d,0xe00}, + {0x21104d,0xe00}, + {0x21114d,0xe00}, + {0x21204d,0xe00}, + {0x21214d,0xe00}, + {0x21304d,0xe00}, + {0x21314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x210049,0xeba}, + {0x210149,0xeba}, + {0x211049,0xeba}, + {0x211149,0xeba}, + {0x212049,0xeba}, + {0x212149,0xeba}, + {0x213049,0xeba}, + {0x213149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x2ee}, + {0x120008,0x64}, + {0x220008,0x19}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x2200b2,0xdc}, + {0x210043,0x5a1}, + {0x210143,0x5a1}, + {0x211043,0x5a1}, + {0x211143,0x5a1}, + {0x212043,0x5a1}, + {0x212143,0x5a1}, + {0x213043,0x5a1}, + {0x213143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x2200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x220019,0x1}, + {0x200f0,0x660}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5665}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x22002d,0x0}, + {0x200c7,0x21}, + {0x1200c7,0x21}, + {0x2200c7,0x21}, + {0x200ca,0x24}, + {0x1200ca,0x24}, + {0x2200ca,0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x101}, + {0x54003,0x190}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x102}, + {0x54003,0x64}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x110}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x5d}, + {0x2000c,0xbb}, + {0x2000d,0x753}, + {0x2000e,0x2c}, + {0x12000b,0xc}, + {0x12000c,0x19}, + {0x12000d,0xfa}, + {0x12000e,0x10}, + {0x22000b,0x3}, + {0x22000c,0x6}, + {0x22000d,0x3e}, + {0x22000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x220010,0x5a}, + {0x220011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x240080,0xe0}, + {0x240081,0x12}, + {0x240082,0xe0}, + {0x240083,0x12}, + {0x240084,0xe0}, + {0x240085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_01050008 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; + diff --git a/board/compulab/plat/imx8mm/ddr/lpddr4_timing_01061010.c b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_01061010.c new file mode 100644 index 00000000000..ef7085d9099 --- /dev/null +++ b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_01061010.c @@ -0,0 +1,1849 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa1080020}, + {0x3d400020,0x223}, + {0x3d400024,0x3a980}, + {0x3d400064,0x5b00d2}, + {0x3d4000d0,0xc00305ba}, + {0x3d4000d4,0x940000}, + {0x3d4000dc,0xd4002d}, + {0x3d4000e0,0x310000}, + {0x3d4000e8,0x66004d}, + {0x3d4000ec,0x16004d}, + {0x3d400100,0x191e1920}, + {0x3d400104,0x60630}, + {0x3d40010c,0xb0b000}, + {0x3d400110,0xe04080e}, + {0x3d400114,0x2040c0c}, + {0x3d400118,0x1010007}, + {0x3d40011c,0x401}, + {0x3d400130,0x20600}, + {0x3d400134,0xc100002}, + {0x3d400138,0xd8}, + {0x3d400144,0x96004b}, + {0x3d400180,0x2ee0017}, + {0x3d400184,0x2605b8e}, + {0x3d400188,0x0}, + {0x3d400190,0x497820a}, + {0x3d400194,0x80303}, + {0x3d4001b4,0x170a}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x0}, + {0x3d4000f4,0xc99}, + {0x3d400108,0x70e1617}, + {0x3d400200,0x1f}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0x7070707}, + {0x3d400250,0x29001701}, + {0x3d400254,0x2c}, + {0x3d40025c,0x4000030}, + {0x3d400264,0x900093e7}, + {0x3d40026c,0x2005574}, + {0x3d400400,0x111}, + {0x3d400408,0x72ff}, + {0x3d400494,0x2100e07}, + {0x3d400498,0x620096}, + {0x3d40049c,0x1100e07}, + {0x3d4004a0,0xc8012c}, + {0x3d402020,0x21}, + {0x3d402024,0x7d00}, + {0x3d402050,0x20d040}, + {0x3d402064,0xc001c}, + {0x3d4020dc,0x840000}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004d}, + {0x3d4020ec,0x16004d}, + {0x3d402100,0xa040305}, + {0x3d402104,0x30407}, + {0x3d402108,0x203060b}, + {0x3d40210c,0x505000}, + {0x3d402110,0x2040202}, + {0x3d402114,0x2030202}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x1d}, + {0x3d402144,0x14000a}, + {0x3d402180,0x640004}, + {0x3d402190,0x3818200}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x100}, + {0x3d403020,0x21}, + {0x3d403024,0x1f40}, + {0x3d403050,0x20d040}, + {0x3d403064,0x30007}, + {0x3d4030dc,0x840000}, + {0x3d4030e0,0x310000}, + {0x3d4030e8,0x66004d}, + {0x3d4030ec,0x16004d}, + {0x3d403100,0xa010102}, + {0x3d403104,0x30404}, + {0x3d403108,0x203060b}, + {0x3d40310c,0x505000}, + {0x3d403110,0x2040202}, + {0x3d403114,0x2030202}, + {0x3d403118,0x1010004}, + {0x3d40311c,0x301}, + {0x3d403130,0x20300}, + {0x3d403134,0xa100002}, + {0x3d403138,0x8}, + {0x3d403144,0x50003}, + {0x3d403180,0x190004}, + {0x3d403190,0x3818200}, + {0x3d403194,0x80303}, + {0x3d4031b4,0x100}, + {0x3d400028,0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x0}, + {0x110a1,0x1}, + {0x110a2,0x3}, + {0x110a3,0x4}, + {0x110a4,0x5}, + {0x110a5,0x2}, + {0x110a6,0x7}, + {0x110a7,0x6}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x3}, + {0x120a3,0x2}, + {0x120a4,0x5}, + {0x120a5,0x4}, + {0x120a6,0x7}, + {0x120a7,0x6}, + {0x130a0,0x0}, + {0x130a1,0x1}, + {0x130a2,0x2}, + {0x130a3,0x3}, + {0x130a4,0x4}, + {0x130a5,0x5}, + {0x130a6,0x6}, + {0x130a7,0x7}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x21005f,0x1ff}, + {0x21015f,0x1ff}, + {0x21105f,0x1ff}, + {0x21115f,0x1ff}, + {0x21205f,0x1ff}, + {0x21215f,0x1ff}, + {0x21305f,0x1ff}, + {0x21315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0x19}, + {0x1200c5,0x7}, + {0x2200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x2}, + {0x22002e,0x2}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x290204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x220024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x3}, + {0x120056,0xa}, + {0x220056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x21004d,0xe00}, + {0x21014d,0xe00}, + {0x21104d,0xe00}, + {0x21114d,0xe00}, + {0x21204d,0xe00}, + {0x21214d,0xe00}, + {0x21304d,0xe00}, + {0x21314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x210049,0xeba}, + {0x210149,0xeba}, + {0x211049,0xeba}, + {0x211149,0xeba}, + {0x212049,0xeba}, + {0x212149,0xeba}, + {0x213049,0xeba}, + {0x213149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x2ee}, + {0x120008,0x64}, + {0x220008,0x19}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x2200b2,0xdc}, + {0x210043,0x5a1}, + {0x210143,0x5a1}, + {0x211043,0x5a1}, + {0x211143,0x5a1}, + {0x212043,0x5a1}, + {0x212143,0x5a1}, + {0x213043,0x5a1}, + {0x213143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x2200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x220019,0x1}, + {0x200f0,0x660}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5665}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x22002d,0x0}, + {0x200c7,0x21}, + {0x1200c7,0x21}, + {0x2200c7,0x21}, + {0x200ca,0x24}, + {0x1200ca,0x24}, + {0x2200ca,0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x101}, + {0x54003,0x190}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x102}, + {0x54003,0x64}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x110}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x5d}, + {0x2000c,0xbb}, + {0x2000d,0x753}, + {0x2000e,0x2c}, + {0x12000b,0xc}, + {0x12000c,0x19}, + {0x12000d,0xfa}, + {0x12000e,0x10}, + {0x22000b,0x3}, + {0x22000c,0x6}, + {0x22000d,0x3e}, + {0x22000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x220010,0x5a}, + {0x220011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x240080,0xe0}, + {0x240081,0x12}, + {0x240082,0xe0}, + {0x240083,0x12}, + {0x240084,0xe0}, + {0x240085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_01061010 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; + diff --git a/board/compulab/plat/imx8mm/ddr/lpddr4_timing_05000010.c b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_05000010.c new file mode 100644 index 00000000000..5b091de47b4 --- /dev/null +++ b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_05000010.c @@ -0,0 +1,1849 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa1080020}, + {0x3d400020,0x223}, + {0x3d400024,0x2ee00}, + {0x3d400064,0x4900a8}, + {0x3d4000d0,0xc0030495}, + {0x3d4000d4,0x770000}, + {0x3d4000dc,0xc40024}, + {0x3d4000e0,0x310000}, + {0x3d4000e8,0x66004d}, + {0x3d4000ec,0x16004d}, + {0x3d400100,0x1618141a}, + {0x3d400104,0x504a6}, + {0x3d40010c,0x909000}, + {0x3d400110,0xb04060b}, + {0x3d400114,0x2030909}, + {0x3d400118,0x1010006}, + {0x3d40011c,0x301}, + {0x3d400130,0x20500}, + {0x3d400134,0xb100002}, + {0x3d400138,0xad}, + {0x3d400144,0x78003c}, + {0x3d400180,0x2580012}, + {0x3d400184,0x1e0493e}, + {0x3d400188,0x0}, + {0x3d400190,0x4938208}, + {0x3d400194,0x80303}, + {0x3d4001b4,0x1308}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x0}, + {0x3d4000f4,0xc99}, + {0x3d400108,0x60c1514}, + {0x3d400200,0x1f}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0x7070707}, + {0x3d400250,0x29001701}, + {0x3d400254,0x2c}, + {0x3d40025c,0x4000030}, + {0x3d400264,0x900093e7}, + {0x3d40026c,0x2005574}, + {0x3d400400,0x111}, + {0x3d400408,0x72ff}, + {0x3d400494,0x2100e07}, + {0x3d400498,0x620096}, + {0x3d40049c,0x1100e07}, + {0x3d4004a0,0xc8012c}, + {0x3d402020,0x21}, + {0x3d402024,0x7d00}, + {0x3d402050,0x20d040}, + {0x3d402064,0xc001c}, + {0x3d4020dc,0x840000}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004d}, + {0x3d4020ec,0x16004d}, + {0x3d402100,0xa040305}, + {0x3d402104,0x30407}, + {0x3d402108,0x203060b}, + {0x3d40210c,0x505000}, + {0x3d402110,0x2040202}, + {0x3d402114,0x2030202}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x1d}, + {0x3d402144,0x14000a}, + {0x3d402180,0x640004}, + {0x3d402190,0x3818200}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x100}, + {0x3d403020,0x21}, + {0x3d403024,0x1f40}, + {0x3d403050,0x20d040}, + {0x3d403064,0x30007}, + {0x3d4030dc,0x840000}, + {0x3d4030e0,0x310000}, + {0x3d4030e8,0x66004d}, + {0x3d4030ec,0x16004d}, + {0x3d403100,0xa010102}, + {0x3d403104,0x30404}, + {0x3d403108,0x203060b}, + {0x3d40310c,0x505000}, + {0x3d403110,0x2040202}, + {0x3d403114,0x2030202}, + {0x3d403118,0x1010004}, + {0x3d40311c,0x301}, + {0x3d403130,0x20300}, + {0x3d403134,0xa100002}, + {0x3d403138,0x8}, + {0x3d403144,0x50003}, + {0x3d403180,0x190004}, + {0x3d403190,0x3818200}, + {0x3d403194,0x80303}, + {0x3d4031b4,0x100}, + {0x3d400028,0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x0}, + {0x110a1,0x1}, + {0x110a2,0x3}, + {0x110a3,0x4}, + {0x110a4,0x5}, + {0x110a5,0x2}, + {0x110a6,0x7}, + {0x110a7,0x6}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x3}, + {0x120a3,0x2}, + {0x120a4,0x5}, + {0x120a5,0x4}, + {0x120a6,0x7}, + {0x120a7,0x6}, + {0x130a0,0x0}, + {0x130a1,0x1}, + {0x130a2,0x2}, + {0x130a3,0x3}, + {0x130a4,0x4}, + {0x130a5,0x5}, + {0x130a6,0x6}, + {0x130a7,0x7}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x21005f,0x1ff}, + {0x21015f,0x1ff}, + {0x21105f,0x1ff}, + {0x21115f,0x1ff}, + {0x21205f,0x1ff}, + {0x21215f,0x1ff}, + {0x21305f,0x1ff}, + {0x21315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0xa}, + {0x1200c5,0x7}, + {0x2200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x2}, + {0x22002e,0x2}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x290204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x220024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x2}, + {0x120056,0xa}, + {0x220056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x21004d,0xe00}, + {0x21014d,0xe00}, + {0x21104d,0xe00}, + {0x21114d,0xe00}, + {0x21204d,0xe00}, + {0x21214d,0xe00}, + {0x21304d,0xe00}, + {0x21314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x210049,0xeba}, + {0x210149,0xeba}, + {0x211049,0xeba}, + {0x211149,0xeba}, + {0x212049,0xeba}, + {0x212149,0xeba}, + {0x213049,0xeba}, + {0x213149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x258}, + {0x120008,0x64}, + {0x220008,0x19}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x2200b2,0xdc}, + {0x210043,0x5a1}, + {0x210143,0x5a1}, + {0x211043,0x5a1}, + {0x211143,0x5a1}, + {0x212043,0x5a1}, + {0x212143,0x5a1}, + {0x213043,0x5a1}, + {0x213143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x2200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x220019,0x1}, + {0x200f0,0x660}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5665}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x22002d,0x0}, + {0x200c7,0x21}, + {0x1200c7,0x21}, + {0x2200c7,0x21}, + {0x200ca,0x24}, + {0x1200ca,0x24}, + {0x2200ca,0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0x960}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x24c4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x24c4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xc400}, + {0x54033,0x3124}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xc400}, + {0x54039,0x3124}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x101}, + {0x54003,0x190}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x102}, + {0x54003,0x64}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x110}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0x960}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x110}, + {0x54019,0x24c4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x24c4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x1}, + {0x54032,0xc400}, + {0x54033,0x3124}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xc400}, + {0x54039,0x3124}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x4b}, + {0x2000c,0x96}, + {0x2000d,0x5dc}, + {0x2000e,0x2c}, + {0x12000b,0xc}, + {0x12000c,0x19}, + {0x12000d,0xfa}, + {0x12000e,0x10}, + {0x22000b,0x3}, + {0x22000c,0x6}, + {0x22000d,0x3e}, + {0x22000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x220010,0x5a}, + {0x220011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x240080,0xe0}, + {0x240081,0x12}, + {0x240082,0xe0}, + {0x240083,0x12}, + {0x240084,0xe0}, + {0x240085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_05000010 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 400, 100, }, +}; + diff --git a/board/compulab/plat/imx8mm/ddr/lpddr4_timing_ff000110.c b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_ff000110.c new file mode 100644 index 00000000000..4401282800b --- /dev/null +++ b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_ff000110.c @@ -0,0 +1,1848 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa3080020}, + {0x3d400020,0x223}, + {0x3d400024,0x3a980}, + {0x3d400064,0x5b00d2}, + {0x3d4000d0,0xc00305ba}, + {0x3d4000d4,0x940000}, + {0x3d4000dc,0xd4002d}, + {0x3d4000e0,0x310000}, + {0x3d4000e8,0x66004d}, + {0x3d4000ec,0x16004d}, + {0x3d400100,0x191e1920}, + {0x3d400104,0x60630}, + {0x3d40010c,0xb0b000}, + {0x3d400110,0xe04080e}, + {0x3d400114,0x2040c0c}, + {0x3d400118,0x1010007}, + {0x3d40011c,0x401}, + {0x3d400130,0x20600}, + {0x3d400134,0xc100002}, + {0x3d400138,0xd8}, + {0x3d400144,0x96004b}, + {0x3d400180,0x2ee0017}, + {0x3d400184,0x2605b8e}, + {0x3d400188,0x0}, + {0x3d400190,0x497820a}, + {0x3d400194,0x80303}, + {0x3d4001b4,0x170a}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x0}, + {0x3d4000f4,0xc99}, + {0x3d400108,0x70e1617}, + {0x3d400200,0x17}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0x7070707}, + {0x3d400250,0x29001701}, + {0x3d400254,0x2c}, + {0x3d40025c,0x4000030}, + {0x3d400264,0x900093e7}, + {0x3d40026c,0x2005574}, + {0x3d400400,0x111}, + {0x3d400408,0x72ff}, + {0x3d400494,0x2100e07}, + {0x3d400498,0x620096}, + {0x3d40049c,0x1100e07}, + {0x3d4004a0,0xc8012c}, + {0x3d402020,0x21}, + {0x3d402024,0x7d00}, + {0x3d402050,0x20d040}, + {0x3d402064,0xc001c}, + {0x3d4020dc,0x840000}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004d}, + {0x3d4020ec,0x16004d}, + {0x3d402100,0xa040305}, + {0x3d402104,0x30407}, + {0x3d402108,0x203060b}, + {0x3d40210c,0x505000}, + {0x3d402110,0x2040202}, + {0x3d402114,0x2030202}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x1d}, + {0x3d402144,0x14000a}, + {0x3d402180,0x640004}, + {0x3d402190,0x3818200}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x100}, + {0x3d403020,0x21}, + {0x3d403024,0x1f40}, + {0x3d403050,0x20d040}, + {0x3d403064,0x30007}, + {0x3d4030dc,0x840000}, + {0x3d4030e0,0x310000}, + {0x3d4030e8,0x66004d}, + {0x3d4030ec,0x16004d}, + {0x3d403100,0xa010102}, + {0x3d403104,0x30404}, + {0x3d403108,0x203060b}, + {0x3d40310c,0x505000}, + {0x3d403110,0x2040202}, + {0x3d403114,0x2030202}, + {0x3d403118,0x1010004}, + {0x3d40311c,0x301}, + {0x3d403130,0x20300}, + {0x3d403134,0xa100002}, + {0x3d403138,0x8}, + {0x3d403144,0x50003}, + {0x3d403180,0x190004}, + {0x3d403190,0x3818200}, + {0x3d403194,0x80303}, + {0x3d4031b4,0x100}, + {0x3d400028,0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x0}, + {0x110a1,0x1}, + {0x110a2,0x3}, + {0x110a3,0x4}, + {0x110a4,0x5}, + {0x110a5,0x2}, + {0x110a6,0x7}, + {0x110a7,0x6}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x3}, + {0x120a3,0x2}, + {0x120a4,0x5}, + {0x120a5,0x4}, + {0x120a6,0x7}, + {0x120a7,0x6}, + {0x130a0,0x0}, + {0x130a1,0x1}, + {0x130a2,0x2}, + {0x130a3,0x3}, + {0x130a4,0x4}, + {0x130a5,0x5}, + {0x130a6,0x6}, + {0x130a7,0x7}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x21005f,0x1ff}, + {0x21015f,0x1ff}, + {0x21105f,0x1ff}, + {0x21115f,0x1ff}, + {0x21205f,0x1ff}, + {0x21215f,0x1ff}, + {0x21305f,0x1ff}, + {0x21315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0x19}, + {0x1200c5,0x7}, + {0x2200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x2}, + {0x22002e,0x2}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x290204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x220024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x3}, + {0x120056,0xa}, + {0x220056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x21004d,0xe00}, + {0x21014d,0xe00}, + {0x21104d,0xe00}, + {0x21114d,0xe00}, + {0x21204d,0xe00}, + {0x21214d,0xe00}, + {0x21304d,0xe00}, + {0x21314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x210049,0xeba}, + {0x210149,0xeba}, + {0x211049,0xeba}, + {0x211149,0xeba}, + {0x212049,0xeba}, + {0x212149,0xeba}, + {0x213049,0xeba}, + {0x213149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x2ee}, + {0x120008,0x64}, + {0x220008,0x19}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x2200b2,0xdc}, + {0x210043,0x5a1}, + {0x210143,0x5a1}, + {0x211043,0x5a1}, + {0x211143,0x5a1}, + {0x212043,0x5a1}, + {0x212143,0x5a1}, + {0x213043,0x5a1}, + {0x213143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x2200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x220019,0x1}, + {0x200f0,0x660}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5665}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x22002d,0x0}, + {0x200c7,0x21}, + {0x1200c7,0x21}, + {0x2200c7,0x21}, + {0x200ca,0x24}, + {0x1200ca,0x24}, + {0x2200ca,0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x101}, + {0x54003,0x190}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x102}, + {0x54003,0x64}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x5d}, + {0x2000c,0xbb}, + {0x2000d,0x753}, + {0x2000e,0x2c}, + {0x12000b,0xc}, + {0x12000c,0x19}, + {0x12000d,0xfa}, + {0x12000e,0x10}, + {0x22000b,0x3}, + {0x22000c,0x6}, + {0x22000d,0x3e}, + {0x22000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x220010,0x5a}, + {0x220011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x240080,0xe0}, + {0x240081,0x12}, + {0x240082,0xe0}, + {0x240083,0x12}, + {0x240084,0xe0}, + {0x240085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_ff000110 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/compulab/plat/imx8mm/ddr/lpddr4_timing_ff020008.c b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_ff020008.c new file mode 100644 index 00000000000..7473c96e8d6 --- /dev/null +++ b/board/compulab/plat/imx8mm/ddr/lpddr4_timing_ff020008.c @@ -0,0 +1,1848 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa3080020}, + {0x3d400020,0x223}, + {0x3d400024,0x3a980}, + {0x3d400064,0x5b00d2}, + {0x3d4000d0,0xc00305ba}, + {0x3d4000d4,0x940000}, + {0x3d4000dc,0xd4002d}, + {0x3d4000e0,0x310000}, + {0x3d4000e8,0x66004d}, + {0x3d4000ec,0x16004d}, + {0x3d400100,0x191e1920}, + {0x3d400104,0x60630}, + {0x3d40010c,0xb0b000}, + {0x3d400110,0xe04080e}, + {0x3d400114,0x2040c0c}, + {0x3d400118,0x1010007}, + {0x3d40011c,0x401}, + {0x3d400130,0x20600}, + {0x3d400134,0xc100002}, + {0x3d400138,0xd8}, + {0x3d400144,0x96004b}, + {0x3d400180,0x2ee0017}, + {0x3d400184,0x2605b8e}, + {0x3d400188,0x0}, + {0x3d400190,0x497820a}, + {0x3d400194,0x80303}, + {0x3d4001b4,0x170a}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x0}, + {0x3d4000f4,0xc99}, + {0x3d400108,0x70e1617}, + {0x3d400200,0x16}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0xf070707}, + {0x3d400250,0x29001701}, + {0x3d400254,0x2c}, + {0x3d40025c,0x4000030}, + {0x3d400264,0x900093e7}, + {0x3d40026c,0x2005574}, + {0x3d400400,0x111}, + {0x3d400408,0x72ff}, + {0x3d400494,0x2100e07}, + {0x3d400498,0x620096}, + {0x3d40049c,0x1100e07}, + {0x3d4004a0,0xc8012c}, + {0x3d402020,0x21}, + {0x3d402024,0x7d00}, + {0x3d402050,0x20d040}, + {0x3d402064,0xc001c}, + {0x3d4020dc,0x840000}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004d}, + {0x3d4020ec,0x16004d}, + {0x3d402100,0xa040305}, + {0x3d402104,0x30407}, + {0x3d402108,0x203060b}, + {0x3d40210c,0x505000}, + {0x3d402110,0x2040202}, + {0x3d402114,0x2030202}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x1d}, + {0x3d402144,0x14000a}, + {0x3d402180,0x640004}, + {0x3d402190,0x3818200}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x100}, + {0x3d403020,0x21}, + {0x3d403024,0x1f40}, + {0x3d403050,0x20d040}, + {0x3d403064,0x30007}, + {0x3d4030dc,0x840000}, + {0x3d4030e0,0x310000}, + {0x3d4030e8,0x66004d}, + {0x3d4030ec,0x16004d}, + {0x3d403100,0xa010102}, + {0x3d403104,0x30404}, + {0x3d403108,0x203060b}, + {0x3d40310c,0x505000}, + {0x3d403110,0x2040202}, + {0x3d403114,0x2030202}, + {0x3d403118,0x1010004}, + {0x3d40311c,0x301}, + {0x3d403130,0x20300}, + {0x3d403134,0xa100002}, + {0x3d403138,0x8}, + {0x3d403144,0x50003}, + {0x3d403180,0x190004}, + {0x3d403190,0x3818200}, + {0x3d403194,0x80303}, + {0x3d4031b4,0x100}, + {0x3d400028,0x0}, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x0}, + {0x110a1,0x1}, + {0x110a2,0x3}, + {0x110a3,0x4}, + {0x110a4,0x5}, + {0x110a5,0x2}, + {0x110a6,0x7}, + {0x110a7,0x6}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x3}, + {0x120a3,0x2}, + {0x120a4,0x5}, + {0x120a5,0x4}, + {0x120a6,0x7}, + {0x120a7,0x6}, + {0x130a0,0x0}, + {0x130a1,0x1}, + {0x130a2,0x2}, + {0x130a3,0x3}, + {0x130a4,0x4}, + {0x130a5,0x5}, + {0x130a6,0x6}, + {0x130a7,0x7}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x21005f,0x1ff}, + {0x21015f,0x1ff}, + {0x21105f,0x1ff}, + {0x21115f,0x1ff}, + {0x21205f,0x1ff}, + {0x21215f,0x1ff}, + {0x21305f,0x1ff}, + {0x21315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0x19}, + {0x1200c5,0x7}, + {0x2200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x2}, + {0x22002e,0x2}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x290204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x220024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x3}, + {0x120056,0xa}, + {0x220056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x21004d,0xe00}, + {0x21014d,0xe00}, + {0x21104d,0xe00}, + {0x21114d,0xe00}, + {0x21204d,0xe00}, + {0x21214d,0xe00}, + {0x21304d,0xe00}, + {0x21314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x210049,0xeba}, + {0x210149,0xeba}, + {0x211049,0xeba}, + {0x211149,0xeba}, + {0x212049,0xeba}, + {0x212149,0xeba}, + {0x213049,0xeba}, + {0x213149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x2ee}, + {0x120008,0x64}, + {0x220008,0x19}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x2200b2,0xdc}, + {0x210043,0x5a1}, + {0x210143,0x5a1}, + {0x211043,0x5a1}, + {0x211143,0x5a1}, + {0x212043,0x5a1}, + {0x212143,0x5a1}, + {0x213043,0x5a1}, + {0x213143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x2200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x220019,0x1}, + {0x200f0,0x660}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5665}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x22002d,0x0}, + {0x200c7,0x21}, + {0x1200c7,0x21}, + {0x2200c7,0x21}, + {0x200ca,0x24}, + {0x1200ca,0x24}, + {0x2200ca,0x24}, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x101}, + {0x54003,0x190}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x102}, + {0x54003,0x64}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400d,0x100}, + {0x54012,0x310}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54005,0x2228}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x5d}, + {0x2000c,0xbb}, + {0x2000d,0x753}, + {0x2000e,0x2c}, + {0x12000b,0xc}, + {0x12000c,0x19}, + {0x12000d,0xfa}, + {0x12000e,0x10}, + {0x22000b,0x3}, + {0x22000c,0x6}, + {0x22000d,0x3e}, + {0x22000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x220010,0x5a}, + {0x220011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x240080,0xe0}, + {0x240081,0x12}, + {0x240082,0xe0}, + {0x240083,0x12}, + {0x240084,0xe0}, + {0x240085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_ff020008 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/compulab/plat/imx8mm/spl/Makefile b/board/compulab/plat/imx8mm/spl/Makefile new file mode 100644 index 00000000000..a3a9acaa6e7 --- /dev/null +++ b/board/compulab/plat/imx8mm/spl/Makefile @@ -0,0 +1,7 @@ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mm/ + +obj-y += common.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/compulab/plat/imx8mm/spl/common.c b/board/compulab/plat/imx8mm/spl/common.c new file mode 100644 index 00000000000..5f1d1e5b972 --- /dev/null +++ b/board/compulab/plat/imx8mm/spl/common.c @@ -0,0 +1,33 @@ +#include +#include +#include +#include +#include + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(2); + + return 0; +} + diff --git a/board/compulab/plat/imx8mm/spl/spl.c b/board/compulab/plat/imx8mm/spl/spl.c new file mode 100644 index 00000000000..325d6b6a5f6 --- /dev/null +++ b/board/compulab/plat/imx8mm/spl/spl.c @@ -0,0 +1,251 @@ +/* + * Copyright 2020 CompuLab Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include "ddr/ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + default: + return BOOT_DEVICE_NONE; + } +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MM_PAD_I2C2_SCL_I2C2_SCL | PC, + .gpio_mode = IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 | PC, + .gp = IMX_GPIO_NR(5, 16), + }, + .sda = { + .i2c_mode = IMX8MM_PAD_I2C2_SDA_I2C2_SDA | PC, + .gpio_mode = IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 | PC, + .gp = IMX_GPIO_NR(5, 17), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 8}, +}; + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(2); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + ret = gpio_get_value(USDHC2_CD_GPIO); + /* CD is active low */ + return !ret; + } + + return 1; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 1 +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_bd71837_init(I2C_PMIC); + if (ret) + printf("power init failed"); + + p = pmic_get("BD71837"); + pmic_probe(p); + + + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(p, BD71837_PWRONCONFIG1, 0x0); + + /* unlock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x1); + + /* decrease VDD_ARM to 0.85V for 1.2GHz operation */ + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); + + /* increase VDD_DRAM to 0.975V (9v5 required but not supported)*/ + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83); + + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(p, BD71837_BUCK8_VOLT, 0x28); + + /* lock the PMIC regs */ + pmic_reg_write(p, BD71837_REGLOCK, 0x11); + + return 0; +} +#else +int power_init_board(void) { return 0; } +#endif + +__weak int spl_board_private_init(void) { + return 0; +} + +void spl_board_init(void) +{ +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + if (spl_board_private_init()) { + debug("spl_board_private_init() failed\n"); + hang(); + } + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +__weak int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/compulab/plat/imx8mp/Makefile b/board/compulab/plat/imx8mp/Makefile new file mode 100644 index 00000000000..15ce6673575 --- /dev/null +++ b/board/compulab/plat/imx8mp/Makefile @@ -0,0 +1,3 @@ +obj-y += ddr/ +obj-y += spl/ +obj-y += board/ diff --git a/board/compulab/plat/imx8mp/board/Makefile b/board/compulab/plat/imx8mp/board/Makefile new file mode 100644 index 00000000000..951cd799dbb --- /dev/null +++ b/board/compulab/plat/imx8mp/board/Makefile @@ -0,0 +1,8 @@ +ccflags-y += -I$(srctree)/board/compulab/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mp/ +ccflags-y += -I$(srctree)/board/freescale/ + +obj-y += board.o +ifndef CONFIG_SPL_BUILD +obj-y += cmd.o +endif diff --git a/board/compulab/plat/imx8mp/board/board.c b/board/compulab/plat/imx8mp/board/board.c new file mode 100644 index 00000000000..bb73ee7e26c --- /dev/null +++ b/board/compulab/plat/imx8mp/board/board.c @@ -0,0 +1,635 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common/tcpc.h" +#include "common/fdt.h" +#include +#include +#include +#include +#include "ddr/ddr.h" +#include "common/eeprom.h" +#include "cmd.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_NAND_MXS + +static void setup_gpmi_nand(void) +{ + init_nand_clk(); +} +#endif + +int board_phys_sdram_size(phys_size_t *size) +{ + size_t dramsize; + if (!size) + return -EINVAL; + + dramsize = lppdr4_get_ramsize(); + + *size = ((1L << 20) * dramsize ); + + return 0; +} + + +#ifdef CONFIG_OF_BOARD_SETUP +__weak int fdt_board_vendor_setup(void *blob) { + return 0; +} + +__weak void board_save_phyaddr(int phy_addr) { + return; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + int rc; + phys_addr_t ecc0_start = 0xb0000000; + phys_addr_t ecc1_start = 0x130000000; + phys_addr_t ecc2_start = 0x1b0000000; + size_t ecc_size = 0x10000000; + + rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc0 reserved-memory node.\n"); + return rc; + } + + rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc1 reserved-memory node.\n"); + return rc; + } + + rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc2 reserved-memory node.\n"); + return rc; + } +#endif + + fdt_set_env_addr(blob); + fdt_set_sn(blob); + fdt_board_vendor_setup(blob); + return 0; +} +#endif + +#ifdef CONFIG_DWC_ETH_QOS +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* set INTF as RGMII, enable RGMII TXC clock */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16)); + setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21)); + + return set_clk_eqos(ENET_125MHZ); +} +#endif + +#if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS) +static int mx8_rgmii_rework(struct phy_device *phydev); +int board_phy_config(struct phy_device *phydev) +{ + mx8_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(1, 0x72); + } else + return -EINVAL; +} + +/* Port2 is the power supply, port 1 does not support power */ +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 45000, + .op_snk_mv = 15000, + .switch_setup_func = &pd_switch_snk_enable, + .disable_pd = true, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 2, /*i2c3*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 45000, + .op_snk_mv = 15000, +}; + +#define USB_TYPEC_SEL IMX_GPIO_NR(4, 20) +#define USB_TYPEC_EN IMX_GPIO_NR(2, 20) + +static iomux_v3_cfg_t ss_mux_gpio[] = { + MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void ss_mux_select(enum typec_cc_polarity pol) +{ + if (pol == TYPEC_POLARITY_CC1) + gpio_direction_output(USB_TYPEC_SEL, 0); + else + gpio_direction_output(USB_TYPEC_SEL, 1); +} + +static int setup_typec(void) +{ + int ret; + struct gpio_desc per_12v_desc; + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } else if (tcpc_pd_sink_check_charging(&port2)) { + printf("Power supply on USB2\n"); + + /* Enable PER 12V, any check before it? */ + ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc); + if (ret) { + printf("%s lookup gpio@20_1 failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + ret = dm_gpio_request(&per_12v_desc, "per_12v_en"); + if (ret) { + printf("%s request per_12v failed ret = %d\n", __func__, ret); + return -EIO; + } + + /* Enable PER 12V regulator */ + dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + } + + debug("tcpc_init port 1\n"); + imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + gpio_request(USB_TYPEC_SEL, "typec_sel"); + gpio_request(USB_TYPEC_EN, "typec_en"); + gpio_direction_output(USB_TYPEC_EN, 0); + + ret = tcpc_init(&port1, port1_config, &ss_mux_select); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } else { + return ret; + } + + return ret; +} +#endif + +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +#define USB_PHY_CTRL6 0xF0058 + +#define HSIO_GPR_BASE (0x32F10000U) +#define HSIO_GPR_REG_0 (HSIO_GPR_BASE) +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1) +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT) + + +static struct dwc3_device dwc3_device_data = { +#ifdef CONFIG_SPL_BUILD + .maximum_speed = USB_SPEED_HIGH, +#else + .maximum_speed = USB_SPEED_SUPER, +#endif + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(int index) +{ + dwc3_uboot_handle_interrupt(index); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + /* enable usb clock via hsio gpr */ + RegData = readl(HSIO_GPR_REG_0); + RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN; + writel(RegData, HSIO_GPR_REG_0); + + /* USB3.0 PHY signal fsel for 100M ref */ + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData = (RegData & 0xfffff81f) | (0x2a<<5); + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL6); + RegData &=~0x1; + writel(RegData, dwc3->base + USB_PHY_CTRL6); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) +#define USB2_PWR_EN IMX_GPIO_NR(1, 14) +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + imx8m_usb_power(index, true); + + if (index == 0 && init == USB_INIT_DEVICE) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port1); + if (ret) + return ret; +#endif + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port1); +#endif + return ret; + } else if (index == 1 && init == USB_INIT_HOST) { + /* Enable GPIO1_IO14 for 5V VBUS */ + gpio_request(USB2_PWR_EN, "usb2_pwr"); + gpio_direction_output(USB2_PWR_EN, 1); + } + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port1); +#endif + } else if (index == 1 && init == USB_INIT_HOST) { + /* Disable GPIO1_IO14 for 5V VBUS */ + gpio_direction_output(USB2_PWR_EN, 0); + } + + imx8m_usb_power(index, false); + + return ret; +} + +#ifdef CONFIG_USB_TCPC +/* Not used so far */ +int board_typec_get_mode(int index) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + + if (index == 0) { + tcpc_setup_ufp_mode(&port1); + + ret = tcpc_get_cc_status(&port1, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; + } else { + return USB_INIT_HOST; + } +} +#endif +#endif + +#define FSL_SIP_GPC 0xC2000000 +#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x3 +#define DISPMIX 13 +#define MIPI 15 + +__weak void board_vendor_init(void) { + return; +} + +__weak void board_vendor_late_init(void) { + return; +} + +int board_init(void) +{ + struct arm_smccc_res res; + + board_vendor_init(); + +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + +#ifdef CONFIG_DWC_ETH_QOS + /* clock, pin, gpr */ + setup_eqos(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) + init_usb_clk(); +#endif + + /* enable the dispmix & mipi phy power domain */ + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + DISPMIX, true, 0, 0, 0, 0, &res); + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + MIPI, true, 0, 0, 0, 0, &res); + + if (IS_ENABLED(CONFIG_LED)) + led_default_state(); + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", CONFIG_SYS_BOARD); + env_set("board_rev", "iMX8MP"); +#endif + +#ifdef CONFIG_DRAM_D2D4 + env_set("dram_subset", "d2d4"); +#else + env_set("dram_subset", "d1d8"); +#endif + board_vendor_late_init(); + + do_pbb_restore(); + return 0; +} + +#ifdef CONFIG_IMX_BOOTAUX +ulong board_get_usable_ram_top(ulong total_size) +{ + /* Set U-boot upper limit to 2^32 */ + if(gd->ram_top > 0x100000000) + gd->ram_top = 0x100000000; + + /* Reserve 16M memory used by M core vring/buffer, which begins at 16MB before optee */ + if (rom_pointer[1]) + return gd->ram_top - SZ_16M; + + return gd->ram_top; +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /*TODO*/ +} +#endif /*CONFIG_ANDROID_RECOVERY*/ +#endif /*CONFIG_FSL_FASTBOOT*/ + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); +} +#endif + +#ifdef CONFIG_SPL_MMC_SUPPORT + +#define UBOOT_RAW_SECTOR_OFFSET 0x40 +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) +{ + u32 boot_dev = spl_boot_device(); + switch (boot_dev) { + case BOOT_DEVICE_MMC2: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET; + default: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; + } +} +#endif + +#define PHY_VENDOR_ID_MASK (( 1<<5 ) - 1 ) +#define PHY_ATEROS_ID 0x7 +#define PHY_REALTEK_ID 0x11 + +int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) +{ + int phy_reg; + + /* + * Grab the bits from PHYIR1, and put them + * in the upper half + */ + phy_reg = bus->read(bus, addr, devad, MII_PHYSID1); + + if (phy_reg < 0) + return -EIO; + + *phy_id = (phy_reg & 0xffff) << 16; + + /* Grab the bits from PHYIR2, and put them in the lower half */ + phy_reg = bus->read(bus, addr, devad, MII_PHYSID2); + + if (phy_reg < 0) + return -EIO; + + *phy_id |= (phy_reg & 0xffff); + +#ifdef CONFIG_TARGET_SOM_IMX8M_PLUS + /* Specical case for REALTEK */ + phy_reg = (( phy_reg >> 4 ) & PHY_VENDOR_ID_MASK); + if ((addr == 0) && (phy_reg == PHY_REALTEK_ID)) { + return -ENODEV; + } +#endif + return 0; +} + +static int mx8_rgmii_rework_realtek(struct phy_device *phydev) +{ +#define TXDLY_MASK ((1 << 13) | (1 << 12)) +#define RXDLY_MASK ((1 << 13) | (1 << 11)) + + unsigned short val; + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c); + val |= TXDLY_MASK; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val); + + /* introduce rx clock delay */ + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c); + val |= RXDLY_MASK; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0); + + /*LEDs:*/ + /* set to extension page */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007); + /* extension Page44 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010); + /* To disable EEE LED mode (blinking .4s/2s) */ + /* extension Page5 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005); + phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82); + phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00); + return 0; +} + +static int mx8_rgmii_rework(struct phy_device *phydev) +{ + unsigned short val = phy_read(phydev, MDIO_DEVAD_NONE, 0x3); + + val = (( val >> 4 ) & PHY_VENDOR_ID_MASK); + + switch (val) { + case PHY_ATEROS_ID: + break; + case PHY_REALTEK_ID: + mx8_rgmii_rework_realtek(phydev); + break; + default: + break; + } + + board_save_phyaddr(phydev->addr); + return 0; +} diff --git a/board/compulab/plat/imx8mp/board/cmd.c b/board/compulab/plat/imx8mp/board/cmd.c new file mode 100644 index 00000000000..ac269fcf950 --- /dev/null +++ b/board/compulab/plat/imx8mp/board/cmd.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common/tcpc.h" +#include "common/fdt.h" +#include +#include +#include +#include +#include "ddr/ddr.h" +#include "common/eeprom.h" + +#include +#include + +static char ldo4_help_text[] = + "value[8-33] - set 0x24 register value; voltage range: [0.80-3.30]\n" + "ldo4 value[0] - disable ldo4\n"; + +/* Forward declaration */ +u8 cl_eeprom_get_ldo4(void); +u8 cl_eeprom_set_ldo4(u8 ldo4); + +static void do_pmic_ldo4(u8 ldo4) { + const char *name = "pca9450@25"; + static struct udevice *currdev = NULL; + int ret; + if (currdev == NULL) { + ret = pmic_get(name, &currdev); + if (ret) { + printf("Can't get PMIC: %s!\n", name); + return; + } + } + ret = pmic_reg_write(currdev, 0x24, ldo4); + if (ret) { + printf("Can't set PMIC: %s; register 0x%x\n", name, 0x24); + return; + } +} + +int do_ldo4(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + u8 ldo4 = 0xDA; + if (argc == 2) { + ldo4 = (u8) simple_strtoul(argv[1], NULL, 10); + if (( ldo4 >= 0x8 ) && ( ldo4 <= 0x21 )) { + ldo4 -= 0x8; ldo4 |= 0x80; + } else if ( ldo4 == 0 ) + ldo4 = 0; + else + return CMD_RET_USAGE; + ldo4 = cl_eeprom_set_ldo4(ldo4); + do_pmic_ldo4(ldo4); + return 0; + } + + ldo4 = cl_eeprom_get_ldo4(); + if (( ldo4 >= 0x80 ) && ( ldo4 <= 0x9F )) { + ldo4 &= ~0x80; ldo4 += 8; + ldo4 = (( ldo4 > 33 ) ? 33 : ldo4); + printf("pca9450@25 [ldo4] = %dv%d\n", (ldo4/10) , (ldo4%10)); + } else + printf("pca9450@25 [ldo4] = 0x%x\n", ldo4); + + return 0; +} + +U_BOOT_CMD( + ldo4, 2, 1, do_ldo4, + "get/set ldo4 value", + ldo4_help_text +); + +static char ddr_help_text[] = + "rdmr -- read mr[5-8] registers\n" + "ddr read -- read eeprom values [ mrs, subid, size ]\n" + "ddr clear -- clean up eeprom\n"; + +unsigned int lpddr4_get_mr(void); +void do_ddr_rdmr(void) { + unsigned int data = lpddr4_get_mr(); + printf("mr[5-8]: [0x%x]\n", data); +} + +u32 cl_eeprom_get_ddrinfo(void); +u8 cl_eeprom_get_subind(void); +void do_ddr_read(void) { + u32 ddrinfo = cl_eeprom_get_ddrinfo(); + u8 subind = cl_eeprom_get_subind(); + printf("eeprom: [0x%x][0x%x]\n", ddrinfo, subind); +} + +void cl_eeprom_clr_ddrinfo(void); +void do_ddr_clear(void) { + cl_eeprom_clr_ddrinfo(); +} + +int do_ddr(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc != 2) { + return CMD_RET_USAGE; + } + + if (strcmp(argv[1], "rdmr") == 0) { + do_ddr_rdmr(); + } else if (strcmp(argv[1], "read") == 0 ) { + do_ddr_read(); + } else if (strcmp(argv[1], "clear") == 0 ) { + do_ddr_clear(); + } else + return CMD_RET_USAGE; + + return 0; +} + +#ifdef CONFIG_DRAM_D2D4 +#define SUPPORTED_CONF "D2,D4" +#else +#define SUPPORTED_CONF "D1,D8" +#endif + +U_BOOT_CMD( + ddr, 2, 1, do_ddr, + "rdmr/read/clear\nSupported configurations : [ "SUPPORTED_CONF" ]" , + ddr_help_text +); + +#define SNVS_LP 0x30370038 + +static char pbb_help_text[] = + "help -- show this help\n" + "pbb get -- get SVNS_LP resgister value\n" + "pbb set -- set SVNS_LP resgister value\n" + "pbb on_time -- set power button on_time value\n" + "\t0: 500msec off->on transition time (default)\n" + "\t1: 50msec off->on transition time\n" + "\t2: 100msec off->on transition time\n" + "\t3: 0msec off->on transition time\n" + "pbb btn_press_time -- set power button btn_press_time value\n" + "\t0: 5sec on->off long press time (default)\n" + "\t1: 10sec on->off long press time\n" + "\t2: 15sec on->off long press time\n" + "\t3: on->off long press disabled\n"; + +static void do_pbb_get(void) { + unsigned int value; + char *cvalue = NULL; + value = readl(SNVS_LP); + printf("%s = 0x%x\n","SNVS_LP Control Register LPCR",value); + cvalue = env_get("on_time"); + if (cvalue) { + printf("env: on_time=%s\n",cvalue); + } + cvalue = env_get("btn_press_time"); + if (cvalue) { + printf("env: btn_press_time=%s\n",cvalue); + } + return; +} + +static void do_pbb_set(const char *cvalue) { + unsigned int value; + value = simple_strtoul(cvalue, NULL, 16); + writel(value, SNVS_LP); + return; +} + +static void do_pbb_function(char *name, const char *cvalue, unsigned int offset, int flag) { + unsigned int value; + unsigned int _value; + if (cvalue == NULL) { + value = readl(SNVS_LP); + value &= (3 << offset); + value = (value >> offset); + if (flag) + printf("%s[%d] = 0x%x\n","SNVS_LP Control Register LPCR",offset,value); + } else { + value = simple_strtoul(cvalue, NULL, 10); + _value = readl(SNVS_LP); + _value &= ~(3 << offset); + _value |= (value << offset); + writel(_value, SNVS_LP); + if (flag) + env_set(name, cvalue); + } +} + +int do_pbb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) { + return CMD_RET_USAGE; + } + + if (strcmp(argv[1], "on_time") == 0) { + do_pbb_function(argv[1], argv[2], 20, 1); + } else if (strcmp(argv[1], "btn_press_time") == 0 ) { + do_pbb_function(argv[1], argv[2], 16, 1); + } else if (strcmp(argv[1], "get") == 0 ) { + do_pbb_get(); + } else if ((strcmp(argv[1], "set") == 0) && (argv[2])) { + do_pbb_set(argv[2]); + } else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + pbb, 3, 1, do_pbb, + "get/set power button settings", + pbb_help_text +); + +void do_pbb_restore(void) { + char *cvalue = NULL; + cvalue = env_get("on_time"); + do_pbb_function("on_time", cvalue, 20, 0); + cvalue = env_get("btn_press_time"); + do_pbb_function("btn_press_time", cvalue, 16, 0); +} diff --git a/board/compulab/plat/imx8mp/board/cmd.h b/board/compulab/plat/imx8mp/board/cmd.h new file mode 100644 index 00000000000..afd1037bccd --- /dev/null +++ b/board/compulab/plat/imx8mp/board/cmd.h @@ -0,0 +1,6 @@ +#ifndef __CMD_H__ +#define __CMD_H__ + +void do_pbb_restore(void); + +#endif /* __CMD_H__ */ diff --git a/board/compulab/plat/imx8mp/ddr/Makefile b/board/compulab/plat/imx8mp/ddr/Makefile new file mode 100644 index 00000000000..78574f89a73 --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/Makefile @@ -0,0 +1,11 @@ +ifeq ($(CONFIG_DRAM_D2D4),y) +obj-$(CONFIG_SPL_BUILD) += lpddr4_timing_ff000010.o +obj-$(CONFIG_SPL_BUILD) += lpddr4_timing_01061010_4G.o +obj-$(CONFIG_SPL_BUILD) += lpddr4_timing_01061010_2G.o +else +obj-$(CONFIG_SPL_BUILD) += lpddr4_timing_ff060018.o +obj-$(CONFIG_SPL_BUILD) += lpddr4_timing_01061010_1G.o +obj-$(CONFIG_SPL_BUILD) += lpddr4_timing_01061010_1G_4000.o +endif +obj-$(CONFIG_SPL_BUILD) += ddr.o +obj-y += ddr_common.o diff --git a/board/compulab/plat/imx8mp/ddr/ddr.c b/board/compulab/plat/imx8mp/ddr/ddr.c new file mode 100644 index 00000000000..82b9d974a22 --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/ddr.c @@ -0,0 +1,214 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +/* Forward declarations */ +u32 cl_eeprom_get_ddrinfo(void); +u32 cl_eeprom_set_ddrinfo(u32 ddrinfo); +u32 cl_eeprom_get_subind(void); +u32 cl_eeprom_set_subind(u32 subind); +void reset_misc(void); + +static void do_reset_spl(void) { reset_misc(); } + +#define DEFAULT (('D' << 24) + ('E' << 16 ) + ( 'F' << 8 ) + 'A') +#define VALID 0xCAFECAFE +#define DDR_INIT_IN 0xCACACACA +#define DDR_INIT_OUT 0x0C0C0C0C + +int cl_eeprom_buffer_write(uint offset, uchar *buf, int len); +int cl_eeprom_buffer_read(uint offset, uchar *buf, int len); + +static inline void lpddr4_data_get(struct lpddr4_tcm_desc *lpddr4_tcm_desc) { + cl_eeprom_buffer_read(0, (uchar *)lpddr4_tcm_desc, sizeof(struct lpddr4_tcm_desc)); +} + +static inline void lpddr4_data_set(struct lpddr4_tcm_desc *lpddr4_tcm_desc) { + cl_eeprom_buffer_write(0, (uchar *)lpddr4_tcm_desc, sizeof(struct lpddr4_tcm_desc)); +} + +static void spl_tcm_init(struct lpddr4_tcm_desc *lpddr4_tcm_desc) { + if (lpddr4_tcm_desc->sign == DEFAULT) + return; + + memset((char *)lpddr4_tcm_desc, 0x0, sizeof(struct lpddr4_tcm_desc)); + lpddr4_tcm_desc->sign = DEFAULT; +} + +static void spl_tcm_fini(struct lpddr4_tcm_desc *lpddr4_tcm_desc) { + if (lpddr4_tcm_desc->sign == VALID) + return; + + memset((char *)lpddr4_tcm_desc, 0x0, sizeof(struct lpddr4_tcm_desc)); + lpddr4_tcm_desc->sign = VALID; +} + +static void spl_tcm_clr(struct lpddr4_tcm_desc *lpddr4_tcm_desc) { + memset((char *)lpddr4_tcm_desc, 0xFF, sizeof(struct lpddr4_tcm_desc)); +} + +static struct lpddr4_tcm_desc spl_tcm_data; +#define SPL_TCM_DATA &spl_tcm_data +#define SPL_TCM_CLR spl_tcm_clr(lpddr4_tcm_desc) +#define SPL_TCM_INIT spl_tcm_init(lpddr4_tcm_desc) +#define SPL_TCM_FINI spl_tcm_fini(lpddr4_tcm_desc) + +static int _spl_dram_init(void) +{ + unsigned int ddr_info = 0xdeadbeef; + unsigned char subind = 0xfF; + unsigned int ddr_info_mrr = 0xdeadbeef; + unsigned int ddr_found = 0; + int i = 0; + + struct lpddr4_tcm_desc *lpddr4_tcm_desc = SPL_TCM_DATA; + + if (lpddr4_tcm_desc->sign == VALID) { + /* get ddr type from the eeprom if not in tcm scan mode */ + ddr_info = cl_eeprom_get_ddrinfo(); + subind = cl_eeprom_get_subind(); + + printf("DDRINFO: EEPROM VALID DATA [ [ %x ] = %x %x \n", + lpddr4_tcm_desc->sign, ddr_info, subind); + + for ( i = 0; i < ARRAY_SIZE(lpddr4_array); i++ ) { + if (lpddr4_array[i].id == ddr_info && + lpddr4_array[i].subind == subind) { + ddr_found = 1; + break; + } + } + } + + /* Walk trought all available ddr ids and apply + * one by one. Save the index at the tcm memory that + * persists after the reset. + */ + if (ddr_found == 0) { + + SPL_TCM_INIT; + + /* Let's check the latest training status */ + if (lpddr4_tcm_desc->ddr_init_status == DDR_INIT_IN) { + printf("%s Bad attempt %d skip\n",__func__,(lpddr4_tcm_desc->index+1)); + lpddr4_tcm_desc->index += 1; + } + + if (lpddr4_tcm_desc->index < ARRAY_SIZE(lpddr4_array)) { + printf("DDRINFO: Cfg attempt: [ %d/%lu ]\n", lpddr4_tcm_desc->index+1, ARRAY_SIZE(lpddr4_array)); + i = lpddr4_tcm_desc->index; + lpddr4_tcm_desc->index += 1; + } else { + /* Ran out all available ddr setings */ + SPL_TCM_CLR; + printf("DDRINFO: Ran out all [ %lu ] cfg attempts. A non supported configuration.\n", ARRAY_SIZE(lpddr4_array)); + return -1; + } + + ddr_info = lpddr4_array[i].id; + } + + printf("DDRINFO(%s): %s %dMB @ %d MHz\n", (ddr_found ? "D" : "?" ), lpddr4_array[i].name, + lpddr4_array[i].size, lpddr4_array[i].timing->fsp_table[0]); + + + if (ddr_found == 0) { + /* This is a discovery case, save in ddr_init_status 'cause it can stack */ + lpddr4_tcm_desc->ddr_init_status = DDR_INIT_IN; + /* Save the data before training */ + lpddr4_data_set(SPL_TCM_DATA); + } + + if (ddr_init(lpddr4_array[i].timing)) { + SPL_TCM_INIT; + return 1; + } + + if (ddr_found == 0) { + /* This is a discovery case, save out ddr_init_status */ + lpddr4_tcm_desc->ddr_init_status = DDR_INIT_OUT; + /* Save the data after training */ + lpddr4_data_set(SPL_TCM_DATA); + } + + ddr_info_mrr = lpddr4_get_mr(); + if (ddr_info_mrr == 0xFFFFFFFF ) { + printf("DDRINFO(M): mr5-8 [ 0x%x ] is invalid; reset\n", ddr_info_mrr); + SPL_TCM_INIT; + return 1; + } + + printf("DDRINFO(M): mr5-8 [ 0x%x ]\n", ddr_info_mrr); + printf("DDRINFO(%s): mr5-8 [ 0x%x ]\n", (ddr_found ? "E" : "T" ), ddr_info); + + if (ddr_info_mrr != ddr_info) { + SPL_TCM_INIT; + return 1; + } + + lpddr4_tcm_desc->size = lpddr4_array[i].size; + + if (ddr_found == 0) { + /* Update eeprom */ + cl_eeprom_set_ddrinfo(ddr_info_mrr); + mdelay(10); + ddr_info = cl_eeprom_get_ddrinfo(); + mdelay(10); + cl_eeprom_set_subind(lpddr4_array[i].subind); + /* make sure that the ddr_info has reached the eeprom */ + printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n", ddr_info); + if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind() != lpddr4_array[i].subind) { + printf("DDRINFO(EEPROM): make sure that the eeprom is accessible\n"); + printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x51 0x40 0x50\n"); + } + /* Set the data valid */ + SPL_TCM_FINI; + /* Return with 1 in ordert to make the caller save the ddr discovery status */ + return 1; + } + + return 0; +} + +static inline void spl_dram_share_info(void) { +#ifdef SHARED_DDR_INFO + struct lpddr4_tcm_desc *lpddr4_tcm_desc = (void *) SHARED_DDR_INFO; + memcpy(lpddr4_tcm_desc, SPL_TCM_DATA, sizeof(struct lpddr4_tcm_desc)); +#endif +} + +void spl_dram_init(void) +{ + int rc=0; + + lpddr4_data_get(SPL_TCM_DATA); + + rc=_spl_dram_init(); + + if (rc==0) { + spl_dram_share_info(); + return; + } + + lpddr4_data_set(SPL_TCM_DATA); + + if (rc==1) { + printf("%s Reset ... \n",__func__); + do_reset_spl(); + } + + while ( 1 ) { }; +} diff --git a/board/compulab/plat/imx8mp/ddr/ddr.h b/board/compulab/plat/imx8mp/ddr/ddr.h new file mode 100644 index 00000000000..0e94c26268d --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/ddr.h @@ -0,0 +1,117 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_DRAM_D2D4 +extern struct dram_timing_info ucm_dram_timing_01061010_2G; +extern struct dram_timing_info ucm_dram_timing_ff000010; +extern struct dram_timing_info ucm_dram_timing_01061010_4G; +#endif +extern struct dram_timing_info ucm_dram_timing_01061010_1G; +extern struct dram_timing_info ucm_dram_timing_01061010_1G_4000; +extern struct dram_timing_info ucm_dram_timing_ff060018; +#endif + +void spl_dram_init(void); + +struct lpddr4_tcm_desc { + unsigned int size; + unsigned int sign; + unsigned int index; + unsigned int ddr_init_status; +}; + +struct lpddr4_desc { + char name[16]; + unsigned int id; + unsigned int size; + unsigned int count; + /* an optional field + * use it if default is not the + * 1-st array entry */ + unsigned int _default; + /* An optional field to distiguish DRAM chips that + * have different geometry, though return the same MRR. + * Default value 0xff + */ + u8 subind; + struct dram_timing_info *timing; + char *desc[4]; +}; + +static const struct lpddr4_desc lpddr4_array[] = { +#ifdef CONFIG_DRAM_D2D4 + { .name = "deadbeaf", .id = 0xdeadbeef, .subind = 0x2, .size = 2048, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_01061010_2G +#endif + }, + { .name = "Samsung", .id = 0x01061010, .subind = 0x4, .size = 4096, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_01061010_4G +#endif + }, + { .name = "Micron", .id = 0xff000010, .subind = 0x4, .size = 4096, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_ff000010 +#endif + }, + { .name = "Micron", .id = 0xff000110, .subind = 0x4, .size = 4096, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_ff000010 +#endif + }, + { .name = "Nanya", .id = 0x05000010, .subind = 0x2, .size = 2048, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_01061010_2G +#endif + }, + { .name = "Samsung", .id = 0x01061010, .subind = 0x2, .size = 2048, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_01061010_2G +#endif + }, + { .name = "Samsung", .id = 0x01080010, .subind = 0x2, .size = 2048, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_01061010_2G +#endif + }, +#else + { .name = "deadbeaf", .id = 0xdeadbeaf, .subind = 0x1, .size = 1024, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_01061010_1G +#endif + }, + { .name = "Samsung", .id = 0x01050008, .subind = 0x1, .size = 1024, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_01061010_1G +#endif + }, + { .name = "Samsung", .id = 0x01060008, .subind = 0x1, .size = 1024, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_01061010_1G_4000 +#endif + }, + { .name = "Micron", .id = 0xff060018, .subind = 0x8, .size = 8192, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_ff060018 +#endif + }, + { .name = "Micron", .id = 0xff070018, .subind = 0x8, .size = 8192, .count = 1, +#ifdef CONFIG_SPL_BUILD + .timing = &ucm_dram_timing_ff060018 +#endif + }, +#endif +}; + +unsigned int lpddr4_get_mr(void); +const struct lpddr4_desc *lpddr4_get_desc_by_id(unsigned int id); +size_t lppdr4_get_ramsize(void); +#endif diff --git a/board/compulab/plat/imx8mp/ddr/ddr_common.c b/board/compulab/plat/imx8mp/ddr/ddr_common.c new file mode 100644 index 00000000000..85c9b4fba6d --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/ddr_common.c @@ -0,0 +1,77 @@ +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr) +{ + unsigned int tmp; + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1); + do { + tmp = reg32_read(DDRC_MRSTAT(0)); + } while (tmp & 0x1); + + reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1); + reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8)); + reg32setbit(DDRC_MRCTRL0(0), 31); + do { + tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0)); + } while ((tmp & 0x8) == 0); + tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0)); + reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4); + while(tmp) { //try to find a significant byte in the word + if(tmp & 0xff) { + tmp &= 0xff; + break; + } + tmp >>= 8; + } + return tmp; +} + +unsigned int lpddr4_get_mr(void) +{ + int i = 0, attempts = 5; + unsigned int ddr_info = 0; + unsigned int regs[] = { 5, 6, 7, 8 }; + + do { + for ( i = 0 ; i < ARRAY_SIZE(regs) ; i++ ) { + unsigned int data = 0; + data = lpddr4_mr_read(0xF, regs[i]); + ddr_info <<= 8; + ddr_info += (data & 0xFF); + } + if ((ddr_info != 0xFFFFFFFF) && (ddr_info != 0)) + break; // The attempt was successfull + } while ( --attempts ); + return ddr_info; +} + +const struct lpddr4_desc *lpddr4_get_desc_by_id(unsigned int id) { + int i = 0; + for ( i = 0; i < ARRAY_SIZE(lpddr4_array); i++ ) { + if (lpddr4_array[i].id == id) + return &lpddr4_array[i]; + } + return NULL; +} + +#ifdef SHARED_DDR_INFO +size_t lppdr4_get_ramsize() { + struct lpddr4_tcm_desc *lpddr4_tcm_desc = (void *) SHARED_DDR_INFO; + return lpddr4_tcm_desc->size; +} +#else +size_t lppdr4_get_ramsize() { + size_t ramsize = 0; + unsigned int id = lpddr4_get_mr(); + const struct lpddr4_desc *desc = lpddr4_get_desc_by_id(id); + if (desc) + ramsize = desc->size; + return ramsize; +} +#endif diff --git a/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_1G.c b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_1G.c new file mode 100644 index 00000000000..e06eb0a09e1 --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_1G.c @@ -0,0 +1,1852 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b0087 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0x8d }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0xf070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0012 }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x13 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30005 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x5 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x34b }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_01061010_1G = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_1G_4000.c b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_1G_4000.c new file mode 100644 index 00000000000..01d77c5dd11 --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_1G_4000.c @@ -0,0 +1,1852 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a00b4 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x8083f }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0xbc }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0xf070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0012 }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x13 }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30005 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x5 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x465 }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_01061010_1G_4000 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; diff --git a/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_2G.c b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_2G.c new file mode 100644 index 00000000000..74938906276 --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_2G.c @@ -0,0 +1,1853 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x110 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x110 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x1 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_01061010_2G = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; diff --git a/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_4G.c b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_4G.c new file mode 100644 index 00000000000..11f9e808fdb --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_01061010_4G.c @@ -0,0 +1,1854 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x186a000 }, + { 0x3d400064, 0x6100e0 }, + { 0x3d400070, 0x7027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc003061c }, + { 0x3d4000d4, 0x9e0000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x1a201b22 }, + { 0x3d400104, 0x60633 }, + { 0x3d40010c, 0xc0c000 }, + { 0x3d400110, 0xf04080f }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x402 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xe6 }, + { 0x3d400144, 0xa00050 }, + { 0x3d400180, 0x3200018 }, + { 0x3d400184, 0x28061a8 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0x699 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x17 }, + { 0x3d400208, 0x0 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x302 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0x599 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x302 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0x599 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x384 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x70 }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x1c }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_01061010_4G = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; + diff --git a/board/compulab/plat/imx8mp/ddr/lpddr4_timing_ff000010.c b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_ff000010.c new file mode 100644 index 00000000000..e2dea08b3d4 --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_ff000010.c @@ -0,0 +1,1853 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x332d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x332d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_ff000010 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; + diff --git a/board/compulab/plat/imx8mp/ddr/lpddr4_timing_ff060018.c b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_ff060018.c new file mode 100644 index 00000000000..a816cf6485c --- /dev/null +++ b/board/compulab/plat/imx8mp/ddr/lpddr4_timing_ff060018.c @@ -0,0 +1,1854 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include + */ + +#include +#include + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x1323 }, + { 0x3d400024, 0x1e84800 }, + { 0x3d400064, 0x7a0118 }, + { 0x3d400070, 0x61027f10 }, + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc00307a3 }, + { 0x3d4000d4, 0xc50000 }, + { 0x3d4000dc, 0xf4003f }, + { 0x3d4000e0, 0x330000 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, + { 0x3d400100, 0x2028222a }, + { 0x3d400104, 0x807bf }, + { 0x3d40010c, 0xe0e000 }, + { 0x3d400110, 0x12040a12 }, + { 0x3d400114, 0x2050f0f }, + { 0x3d400118, 0x1010009 }, + { 0x3d40011c, 0x501 }, + { 0x3d400130, 0x20800 }, + { 0x3d400134, 0xe100002 }, + { 0x3d400138, 0x120 }, + { 0x3d400144, 0xc80064 }, + { 0x3d400180, 0x3e8001e }, + { 0x3d400184, 0x3207a12 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x49f820e }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1f0e }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x9121c1c }, + { 0x3d400200, 0x18 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400250, 0x1705 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x18 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1e3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x3e8 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x104 }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0x104 }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0x104 }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3300 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3300 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x3ff4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x3ff4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xf400 }, + { 0x54033, 0x333f }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xf400 }, + { 0x54039, 0x333f }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x48 }, + { 0x5403c, 0x48 }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x1 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, + { 0x90169, 0x109 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, + { 0x90172, 0x109 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, + { 0x90179, 0x0 }, + { 0x9017a, 0x478 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x68 }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x200be, 0x3 }, + { 0x2000b, 0x7d }, + { 0x2000c, 0xfa }, + { 0x2000d, 0x9c4 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 4000mts 1D */ + .drate = 4000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 4000mts 2D */ + .drate = 4000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info ucm_dram_timing_ff060018 = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 4000, 400, 100, }, +}; + diff --git a/board/compulab/plat/imx8mp/firmware/Makefile b/board/compulab/plat/imx8mp/firmware/Makefile new file mode 100644 index 00000000000..f50b346fdd3 --- /dev/null +++ b/board/compulab/plat/imx8mp/firmware/Makefile @@ -0,0 +1,10 @@ +files=bl31.bin lpddr4_pmu_train_1d_dmem.bin lpddr4_pmu_train_1d_imem.bin lpddr4_pmu_train_2d_dmem.bin lpddr4_pmu_train_2d_imem.bin tee.bin +fw_src=$(srctree)/board/compulab/plat/imx8mp/firmware + +all: $(files) + +$(files): + uudecode --output-file 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+M`"A\!P`P?`<`0'P'`$A\!P!0?`<`6'P'`&!\!P!H?`<`<'P'`(!\!P"(?`<` +MD'P'`)A\!P"@?`<`J'P'`+!\!P#`?`<`R'P'`-!\!P#8?`<`X'P'`.A\!P#P +M?`<``'T'``A]!P`0?0<`&'T'`"!]!P`H?0<`,'T'`$!]!P!(?0<`4'T'`%A] +M!P!@?0<`:'T'`'!]!P"`?0<`B'T'`)!]!P"8?0<`H'T'`*A]!P"P?0<`P'T' +1``A^!P`@?@<`*'X'```````` +` +end diff --git a/board/compulab/plat/imx8mp/spl/Makefile b/board/compulab/plat/imx8mp/spl/Makefile new file mode 100644 index 00000000000..ed4cf945e42 --- /dev/null +++ b/board/compulab/plat/imx8mp/spl/Makefile @@ -0,0 +1,7 @@ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mp/ + +obj-y += common.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/compulab/plat/imx8mp/spl/common.c b/board/compulab/plat/imx8mp/spl/common.c new file mode 100644 index 00000000000..67ae0ccf9d6 --- /dev/null +++ b/board/compulab/plat/imx8mp/spl/common.c @@ -0,0 +1,42 @@ +#include +#include +#include +#include +#include +#include + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +#ifdef CONFIG_COMPULAB_DEBUG_UART1 +static iomux_v3_cfg_t const uart_pads[] = { + MX8MP_PAD_SD1_CMD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_SAI2_RXFS__UART1_DCE_TX| MUX_PAD_CTRL(UART_PAD_CTRL), +}; +#define UART_CLK_INDEX 0 +#else +static iomux_v3_cfg_t const uart_pads[] = { + MX8MP_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX8MP_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; +#define UART_CLK_INDEX 1 +#endif + +static iomux_v3_cfg_t const wdog_pads[] = { + MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(UART_CLK_INDEX); + + return 0; +} diff --git a/board/compulab/plat/imx8mp/spl/spl.c b/board/compulab/plat/imx8mp/spl/spl.c new file mode 100644 index 00000000000..dd05af40eb6 --- /dev/null +++ b/board/compulab/plat/imx8mp/spl/spl.c @@ -0,0 +1,284 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ddr/ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ +#ifdef CONFIG_SPL_BOOTROM_SUPPORT + return BOOT_DEVICE_BOOTROM; +#else + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +#endif +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) +#define USDHC_CD_PAD_CTRL (PAD_CTL_PE |PAD_CTL_PUE |PAD_CTL_HYS | PAD_CTL_DSE4) + + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX8MP_PAD_NAND_WE_B__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_WP_B__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA04__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA05__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA06__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_DATA07__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_RE_B__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE2_B__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CE3_B__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_NAND_CLE__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX8MP_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX8MP_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + MX8MP_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 8}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + break; + case 1: + init_clk_usdhc(2); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +/* Forward declarations */ +u8 cl_eeprom_get_ldo4(void); +static void power_init_ldo4(struct udevice *dev) { + u8 ldo4 = cl_eeprom_get_ldo4(); + int mode = 0; + + if ( ldo4 == 0 ) { + pmic_reg_write(dev, PCA9450_LDO4CTRL, ldo4); + printf("pca9450@25 [ldo4] is off\n"); + return; + }; + + if (( ldo4 >= 0x80 ) && ( ldo4 <= 0x9F )) { + /* user mode; eeprom value */ + mode = 1; + } else { + /* default 1v8 mode */ + ldo4 = 0x8A; + } + + pmic_reg_write(dev, PCA9450_LDO4CTRL, ldo4); + ldo4 &= ~0x80; ldo4 += 8; + ldo4 = (( ldo4 > 33 ) ? 33 : ldo4); + printf("pca9450@25 [ldo4][%s] = %dv%d\n", ( mode ? "u" : "d" ), (ldo4/10) , (ldo4%10)); +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pca9450@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + power_init_ldo4(dev); + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* + * increase VDD_SOC to typical value 0.95V before first + * DRAM access, set DVS1 to 0.85v for suspend. + * Enable DVS control through PMIC_STBY_REQ and + * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) + */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); + + return 0; +} +#endif + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} + +void reset_misc(void) { + puts("resetting ...\n"); + reset_cpu(WDOG1_BASE_ADDR); +} diff --git a/board/compulab/som-imx8m-plus/Kconfig b/board/compulab/som-imx8m-plus/Kconfig new file mode 100644 index 00000000000..903c326cb29 --- /dev/null +++ b/board/compulab/som-imx8m-plus/Kconfig @@ -0,0 +1,38 @@ +if TARGET_SOM_IMX8M_PLUS + +config SYS_BOARD + default "som-imx8m-plus" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "som-imx8m-plus" + +config DEFAULT_DTB + string + default "sbc-som-imx8m-plus.dtb" + +config DEFAULT_FDT_FILE + default "som-imx8m-plus.dtb" + +config DEFAULT_DEVICE_TREE + default "som-imx8m-plus" + +config SYS_I2C_EEPROM_BUS + int + default 1 + +config SYS_I2C_EEPROM_ADDR + hex + default 0x50 + +config SYS_I2C_EEPROM_BUS_SB + hex + default 0x2 + +config SYS_I2C_EEPROM_ADDR_SB + hex + default 0x54 + +endif diff --git a/board/compulab/som-imx8m-plus/Makefile b/board/compulab/som-imx8m-plus/Makefile new file mode 100644 index 00000000000..6e6e5068dca --- /dev/null +++ b/board/compulab/som-imx8m-plus/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2018 CompuLab +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mp/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += som-imx8m-plus.o +endif + +obj-y += ../plat/imx8mp/ +obj-y += ../plat/imx8/ diff --git a/board/compulab/som-imx8m-plus/som-imx8m-plus.c b/board/compulab/som-imx8m-plus/som-imx8m-plus.c new file mode 100644 index 00000000000..b42b2dc6dd0 --- /dev/null +++ b/board/compulab/som-imx8m-plus/som-imx8m-plus.c @@ -0,0 +1,146 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define EXP_3V3_PAD IMX_GPIO_NR(2, 11) +static iomux_v3_cfg_t const exp_3v3_pads[] = { + MX8MP_PAD_SD1_STROBE__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_3v3_exp(void) +{ + imx_iomux_v3_setup_multiple_pads(exp_3v3_pads, + ARRAY_SIZE(exp_3v3_pads)); + + gpio_request(EXP_3V3_PAD, "3v3_exp"); + gpio_direction_output(EXP_3V3_PAD, 0); + mdelay(50); + gpio_direction_output(EXP_3V3_PAD, 1); + mdelay(50); +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22) | BIT(13)); + + return set_clk_enet(ENET_125MHZ); +} +#endif + +#if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS) +#include "../common/eeprom.h" +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + cl_eeprom_read_n_mac_addr(mac, dev_id, CONFIG_SYS_I2C_EEPROM_BUS); + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +} +#endif + +#define WIFI_PD IMX_GPIO_NR(1, 0) +static iomux_v3_cfg_t const wifi_pd_pads[] = { + MX8MP_PAD_GPIO1_IO00__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_wifi_pd(void) +{ + imx_iomux_v3_setup_multiple_pads(wifi_pd_pads, + ARRAY_SIZE(wifi_pd_pads)); + + gpio_request(WIFI_PD, "wifi_pd"); + gpio_direction_output(WIFI_PD, 0); +} + +void board_vendor_init(void) { + setup_3v3_exp(); + + setup_wifi_pd(); +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + return; +} + +#define ETHPHY0 "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0" +#define ETHPHY1 "/soc@0/bus@30800000/ethernet@30bf0000/mdio/ethernet-phy@1" + +struct phy_node { + char *node; + unsigned int addr; +}; + +static struct phy_node phy_nodes[] = { + { .node = ETHPHY0, .addr = -1 }, + { .node = ETHPHY1, .addr = -1 }, +}; + +void board_save_phyaddr(int phy_addr) { + debug("[*] %s:%d addr [ %d ]\n",__func__,__LINE__,phy_addr); + if ((phy_addr == 4) || (phy_addr == 5)) { + /* rev1.1 */ + phy_nodes[0].addr = 5; + phy_nodes[1].addr = 4; + } else { + phy_nodes[0].addr = 1; + phy_nodes[1].addr = 0; + } + return; +} + +static int fdt_update_phy_address(void *blob, const char *node, unsigned int phy_address) { + debug("[*] %s:%d [ %s = %d ]\n",__func__,__LINE__,node,phy_address); + int offs = fdt_path_offset(blob, node); + if (offs < 0) { + printf("Node %s not found.\n", node); + return -EINVAL; + } + fdt_delprop(blob, offs, "reg"); + phy_address = cpu_to_fdt32(phy_address); + return fdt_setprop(blob, offs , "reg", &phy_address, sizeof(u32)); +} + +int fdt_board_vendor_setup(void *blob) { + int rc, i; + for ( i = 0; i < ARRAY_SIZE(phy_nodes); i++ ) { + rc = fdt_update_phy_address(blob, phy_nodes[i].node, phy_nodes[i].addr); + if (rc) { + printf("Node %s update failed rc %d\n", phy_nodes[i].node, rc); + return rc; + } + } + return 0; +} diff --git a/board/compulab/som-imx8m-plus/spl.c b/board/compulab/som-imx8m-plus/spl.c new file mode 100644 index 00000000000..b2fe004bdc1 --- /dev/null +++ b/board/compulab/som-imx8m-plus/spl.c @@ -0,0 +1,9 @@ +#include +#include +#include +#include +#include + +int spl_board_private_init(void) { + return 0; +} diff --git a/board/compulab/ucm-imx8m-mini/Kconfig b/board/compulab/ucm-imx8m-mini/Kconfig new file mode 100644 index 00000000000..2c638cb15f8 --- /dev/null +++ b/board/compulab/ucm-imx8m-mini/Kconfig @@ -0,0 +1,17 @@ +if TARGET_UCM_IMX8M_MINI + +config SYS_BOARD + default "ucm-imx8m-mini" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "ucm-imx8m-mini" + +config DEFAULT_FDT + string + depends on TARGET_UCM_IMX8M_MINI + default "ucm-imx8m-mini.dtb" + +endif diff --git a/board/compulab/ucm-imx8m-mini/Makefile b/board/compulab/ucm-imx8m-mini/Makefile new file mode 100644 index 00000000000..50618b9b6db --- /dev/null +++ b/board/compulab/ucm-imx8m-mini/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2018 CompuLab +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mm/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += ucm-imx8m-mini.o +endif + +obj-y += ../plat/imx8mm/ +obj-y += ../plat/imx8/ diff --git a/board/compulab/ucm-imx8m-mini/spl.c b/board/compulab/ucm-imx8m-mini/spl.c new file mode 100644 index 00000000000..d6ece8ef3ee --- /dev/null +++ b/board/compulab/ucm-imx8m-mini/spl.c @@ -0,0 +1,9 @@ +#include +#include +#include +#include +#include + +int spl_board_private_init(void) { + return 0; +} diff --git a/board/compulab/ucm-imx8m-mini/ucm-imx8m-mini.c b/board/compulab/ucm-imx8m-mini/ucm-imx8m-mini.c new file mode 100644 index 00000000000..6cafc259e9e --- /dev/null +++ b/board/compulab/ucm-imx8m-mini/ucm-imx8m-mini.c @@ -0,0 +1,30 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; diff --git a/board/compulab/ucm-imx8m-plus/Kconfig b/board/compulab/ucm-imx8m-plus/Kconfig new file mode 100644 index 00000000000..b85924612cd --- /dev/null +++ b/board/compulab/ucm-imx8m-plus/Kconfig @@ -0,0 +1,45 @@ +if TARGET_UCM_IMX8M_PLUS + +config SYS_BOARD + default "ucm-imx8m-plus" + +config SYS_VENDOR + default "compulab" + +config SYS_CONFIG_NAME + default "ucm-imx8m-plus" + +config DEFAULT_DTB + string + default "ucm-imx8m-plus.dtb" + + +config DEFAULT_FDT_FILE + string + default "ucm-imx8m-plus.dtb" + +config DEFAULT_DEVICE_TREE + string + default "ucm-imx8m-plus" + +config SYS_I2C_EEPROM_BUS + int + default 1 + +config SYS_I2C_EEPROM_ADDR + hex + default 0x50 + +config SYS_I2C_EEPROM_BUS_SB + hex + default 0x1 + +config SYS_I2C_EEPROM_ADDR_SB + hex + default 0x54 + +config COMPULAB_DEBUG_UART1 + bool "System Debug UART1" + default false + +endif diff --git a/board/compulab/ucm-imx8m-plus/Makefile b/board/compulab/ucm-imx8m-plus/Makefile new file mode 100644 index 00000000000..ec35c20c0be --- /dev/null +++ b/board/compulab/ucm-imx8m-plus/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2018 CompuLab +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I$(srctree)/board/compulab/plat/imx8mp/ +ccflags-y += -I$(srctree)/board/compulab/plat/imx8/ + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else +obj-y += ucm-imx8m-plus.o +endif + +obj-y += ../plat/imx8mp/ +obj-y += ../plat/imx8/ diff --git a/board/compulab/ucm-imx8m-plus/spl.c b/board/compulab/ucm-imx8m-plus/spl.c new file mode 100644 index 00000000000..b2fe004bdc1 --- /dev/null +++ b/board/compulab/ucm-imx8m-plus/spl.c @@ -0,0 +1,9 @@ +#include +#include +#include +#include +#include + +int spl_board_private_init(void) { + return 0; +} diff --git a/board/compulab/ucm-imx8m-plus/ucm-imx8m-plus.c b/board/compulab/ucm-imx8m-plus/ucm-imx8m-plus.c new file mode 100644 index 00000000000..3b3ec6a9120 --- /dev/null +++ b/board/compulab/ucm-imx8m-plus/ucm-imx8m-plus.c @@ -0,0 +1,41 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_FEC_MXC) || defined(CONFIG_DWC_ETH_QOS) +#include "../common/eeprom.h" +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + cl_eeprom_read_n_mac_addr(mac, /*dev_id*/ 0, CONFIG_SYS_I2C_EEPROM_BUS); + debug("%s: MAC%d: %02x.%02x.%02x.%02x.%02x.%02x\n", + __func__, dev_id, mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + return; +} +#endif diff --git a/board/emulation/qemu-ppce500/Kconfig b/board/emulation/qemu-ppce500/Kconfig index 4312d986d83..1c5aa18aa90 100644 --- a/board/emulation/qemu-ppce500/Kconfig +++ b/board/emulation/qemu-ppce500/Kconfig @@ -9,4 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "qemu-ppce500" +config PLATFORM_BUS_MAP_ADDR + hex + default 0xf0000000 + help + The QEMU platform bus base mapped address in the virtual memory space. + endif diff --git a/board/emulation/qemu-ppce500/qemu-ppce500.c b/board/emulation/qemu-ppce500/qemu-ppce500.c index daa103c5646..924cc02c4be 100644 --- a/board/emulation/qemu-ppce500/qemu-ppce500.c +++ b/board/emulation/qemu-ppce500/qemu-ppce500.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include #include #include @@ -109,6 +111,17 @@ static int pci_map_region(phys_addr_t paddr, phys_size_t size, ulong *pmap_addr) return 0; } +static void platform_bus_map_region(ulong map_addr, phys_addr_t paddr, + phys_size_t size) +{ + /* Align map_addr */ + map_addr += size - 1; + map_addr &= ~(size - 1); + + /* Map virtual memory for range */ + assert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO)); +} + int misc_init_r(void) { struct udevice *dev; @@ -148,6 +161,22 @@ int misc_init_r(void) */ disable_tlb(find_tlb_idx((void *)CONFIG_SYS_TMPVIRT, 1)); + /* + * Detect the presence of the platform bus node, and + * create a virtual memory mapping for it. + */ + for (ret = uclass_find_first_device(UCLASS_SIMPLE_BUS, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + if (device_is_compatible(dev, "qemu,platform")) { + struct simple_bus_plat *plat = dev_get_uclass_plat(dev); + + platform_bus_map_region(CONFIG_PLATFORM_BUS_MAP_ADDR, + plat->target, plat->size); + break; + } + } + return 0; } diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig index 17db755951e..9ed58cd4ba8 100644 --- a/board/freescale/common/Kconfig +++ b/board/freescale/common/Kconfig @@ -55,3 +55,9 @@ config VOL_MONITOR_ISL68233_SET help This option enables ISL68233 voltage monitor set functionality. It is used by the common VID driver. + +config USB_TCPC + bool "USB Typec port controller simple driver" + default n + help + Enable USB type-c port controller (TCPC) driver diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 114b7ba8f9f..abc3a6660bb 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -59,10 +59,18 @@ obj-$(CONFIG_ZM7300) += zm7300.o obj-$(CONFIG_POWER_PFUZE100) += pfuze.o obj-$(CONFIG_DM_PMIC_PFUZE100) += pfuze.o obj-$(CONFIG_POWER_MC34VR500) += mc34vr500.o +obj-$(CONFIG_MXC_EPDC) += epdc_setup.o +ifneq (,$(filter $(SOC), mx25 mx31 mx35 mx5 mx6 mx7 mx7ulp imx8 imx8m vf610)) +obj-y += mmc.o +endif +ifdef CONFIG_FSL_FASTBOOT +obj-${CONFIG_ANDROID_RECOVERY} += recovery_keypad.o +endif obj-$(CONFIG_LS102XA_STREAM_ID) += ls102xa_stream_id.o obj-$(CONFIG_EMC2305) += emc2305.o +obj-$(CONFIG_QSFP_EEPROM) += qsfp_eeprom.o # deal with common files for P-series corenet based devices obj-$(CONFIG_TARGET_P2041RDB) += p_corenet/ @@ -78,4 +86,8 @@ obj-$(CONFIG_CMD_ESBC_VALIDATE) += fsl_validate.o cmd_esbc_validate.o endif obj-$(CONFIG_CHAIN_OF_TRUST) += fsl_chain_of_trust.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_USB_TCPC) += tcpc.o +endif + endif diff --git a/board/freescale/common/epdc_setup.c b/board/freescale/common/epdc_setup.c new file mode 100644 index 00000000000..78935c6ff71 --- /dev/null +++ b/board/freescale/common/epdc_setup.c @@ -0,0 +1,226 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Peng Fan + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define is_digit(c) ((c) >= '0' && (c) <= '9') +__weak int mmc_get_env_devno(void) +{ + return 0; +} +__weak int check_mmc_autodetect(void) +{ + return 0; +} + +int board_setup_waveform_file(ulong waveform_buf) +{ + char *fs_argv[5]; + char addr[17]; + ulong file_len, mmc_dev; + + if (!check_mmc_autodetect()) + mmc_dev = env_get_ulong("mmcdev", 10, 0); + else + mmc_dev = mmc_get_env_devno(); + + sprintf(addr, "%lx", (ulong)CONFIG_SYS_LOAD_ADDR); + + fs_argv[0] = "fatload"; + fs_argv[1] = "mmc"; + fs_argv[2] = simple_itoa(mmc_dev); + fs_argv[3] = addr; + fs_argv[4] = env_get("epdc_waveform"); + + if (!fs_argv[4]) + fs_argv[4] = "epdc_splash.bin"; + + if (do_fat_fsload(NULL, 0, 5, fs_argv)) { + printf("File %s not found on MMC Device %lu!\n", fs_argv[4], mmc_dev); + return -1; + } + + file_len = env_get_hex("filesize", 0); + if (!file_len) + return -1; + + memcpy((void *)waveform_buf, (const void *)CONFIG_SYS_LOAD_ADDR, file_len); + + flush_cache(waveform_buf, roundup(file_len, ARCH_DMA_MINALIGN)); + + return 0; +} + +int board_setup_logo_file(void *display_buf) +{ + int logo_width, logo_height; + char *fs_argv[5]; + char addr[17]; + int array[3]; + ulong file_len, mmc_dev; + char *buf, *s; + int arg = 0, val = 0, pos = 0; + int i, j, max_check_length; + int row, col, row_end, col_end; + + if (!display_buf) + return -EINVAL; + + /* Assume PGM header not exceeds 128 bytes */ + max_check_length = 128; + + if (!check_mmc_autodetect()) + mmc_dev = env_get_ulong("mmcdev", 10, 0); + else + mmc_dev = mmc_get_env_devno(); + + memset(display_buf, 0xFF, panel_info.vl_col * panel_info.vl_row); + + fs_argv[0] = "fatsize"; + fs_argv[1] = "mmc"; + fs_argv[2] = simple_itoa(mmc_dev); + fs_argv[3] = env_get("epdc_logo"); + if (!fs_argv[3]) + fs_argv[3] = "epdc_logo.pgm"; + if (do_fat_size(NULL, 0, 4, fs_argv)) { + debug("File %s not found on MMC Device %lu, use black border\n", fs_argv[3], mmc_dev); + /* Draw black border around framebuffer*/ + memset(display_buf, 0x0, 24 * panel_info.vl_col); + for (i = 24; i < (panel_info.vl_row - 24); i++) { + memset((u8 *)display_buf + i * panel_info.vl_col, + 0x00, 24); + memset((u8 *)display_buf + i * panel_info.vl_col + + panel_info.vl_col - 24, 0x00, 24); + } + memset((u8 *)display_buf + + panel_info.vl_col * (panel_info.vl_row - 24), + 0x00, 24 * panel_info.vl_col); + return 0; + } + + file_len = env_get_hex("filesize", 0); + if (!file_len) + return -EINVAL; + + buf = memalign(ARCH_DMA_MINALIGN, file_len); + if (!buf) + return -ENOMEM; + + sprintf(addr, "%lx", (ulong)CONFIG_SYS_LOAD_ADDR); + + fs_argv[0] = "fatload"; + fs_argv[1] = "mmc"; + fs_argv[2] = simple_itoa(mmc_dev); + fs_argv[3] = addr; + fs_argv[4] = env_get("epdc_logo"); + + if (!fs_argv[4]) + fs_argv[4] = "epdc_logo.pgm"; + + if (do_fat_fsload(NULL, 0, 5, fs_argv)) { + printf("File %s not found on MMC Device %lu!\n", fs_argv[4], mmc_dev); + free(buf); + return -1; + } + + memcpy((void *)buf, (const void *)CONFIG_SYS_LOAD_ADDR, file_len); + + if (strncmp(buf, "P5", 2)) { + printf("Wrong format for epdc logo, use PGM-P5 format.\n"); + free(buf); + return -EINVAL; + } + /* Skip P5\n */ + pos += 3; + arg = 0; + for (i = 3; i < max_check_length; ) { + /* skip \n \t and space */ + if ((buf[i] == '\n') || (buf[i] == '\t') || (buf[i] == ' ')) { + i++; + continue; + } + /* skip comment */ + if (buf[i] == '#') { + while (buf[i++] != '\n') + ; + continue; + } + + /* HEIGTH, WIDTH, MAX PIXEL VLAUE total 3 args */ + if (arg > 2) + break; + val = 0; + while (is_digit(buf[i])) { + val = val * 10 + buf[i] - '0'; + i++; + } + array[arg++] = val; + + i++; + } + + /* Point to data area */ + pos = i; + + logo_width = array[0]; + logo_height = array[1]; + + if ((logo_width > panel_info.vl_col) || + (logo_height > panel_info.vl_row)) { + printf("Picture: too big\n"); + free(buf); + return -EINVAL; + } + + /* m,m means center of screen */ + row = 0; + col = 0; + s = env_get("splashpos"); + if (s) { + if (s[0] == 'm') + col = (panel_info.vl_col - logo_width) >> 1; + else + col = simple_strtol(s, NULL, 0); + s = strchr(s + 1, ','); + if (s != NULL) { + if (s[1] == 'm') + row = (panel_info.vl_row - logo_height) >> 1; + else + row = simple_strtol(s + 1, NULL, 0); + } + } + if ((col + logo_width > panel_info.vl_col) || + (row + logo_height > panel_info.vl_row)) { + printf("Incorrect pos, use (0, 0)\n"); + row = 0; + col = 0; + } + + /* Draw picture at the center of screen */ + row_end = row + logo_height; + col_end = col + logo_width; + for (i = row; i < row_end; i++) { + for (j = col; j < col_end; j++) { + *((u8 *)display_buf + i * (panel_info.vl_col) + j) = + buf[pos++]; + } + } + + free(buf); + + flush_cache((ulong)display_buf, file_len - pos - 1); + + return 0; +} diff --git a/board/freescale/common/mmc.c b/board/freescale/common/mmc.c new file mode 100644 index 00000000000..ab1652d6972 --- /dev/null +++ b/board/freescale/common/mmc.c @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include + +static int check_mmc_autodetect(void) +{ + char *autodetect_str = env_get("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +/* This should be defined for each board */ +__weak int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_dev(); + + if (!check_mmc_autodetect()) + return; + + env_set_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + env_set("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} diff --git a/board/freescale/common/qsfp_eeprom.c b/board/freescale/common/qsfp_eeprom.c new file mode 100644 index 00000000000..4e0f52c4e6d --- /dev/null +++ b/board/freescale/common/qsfp_eeprom.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP + */ +#include +#include +#include +#include + +#define DEV_ID_QSFP 0x0c +#define DEV_ID_QSFP_PLUS 0x0d + +static struct __attribute__ ((__packed__)) qsfp_eeprom_map { + struct __attribute__ ((__packed__)) qsfp_low_mem { + /* field byte address */ + u8 identifier; /* 0 */ + u16 status; /* 1-2 */ + u8 reserved[124]; /* 3-126 */ + u8 page_select; /* 127 */ + } base; + + struct __attribute__ ((__packed__)) qsfp_page00_mem { + /* field byte address */ + u8 identifier; /* 128 */ + u8 ext_identifier; /* 129 */ + u8 connector; /* 130 */ + u8 compat[8]; /* 131-138 */ + u8 reserved[3]; /* 139-142 */ + u8 length_fiber[4]; + u8 length_copper; /* 146 */ + u8 tech; /* 147 */ + u8 vendor_name[16]; /* 148-163 */ + u8 reserved2; /* 164 */ + u8 oui[3]; /* 165-167 */ + u8 pn[16]; /* 168-183 */ + u8 rev[2]; /* 184-185 */ + u8 reserved3[10]; /* 186-195 */ + u8 serial[16]; /* 196-211 */ + u8 date[8]; /* 212-219 */ + u8 reserved4[35]; /* 220-255 */ + } page0; +} qsfp; + +unsigned char get_qsfp_compat0(void) +{ + int ret; + char vendor[20] = {0}; + char serial[20] = {0}; + char pname[20] = {0}; + char mfgdt[20] = {0}; +#ifdef CONFIG_DM_I2C + struct udevice *dev; +#endif + + memset(&qsfp, 0, sizeof(qsfp)); +#ifndef CONFIG_DM_I2C + ret = i2c_read(I2C_SFP_EEPROM_ADDR, + 0, + I2C_SFP_EEPROM_ADDR_LEN, + (void *)&qsfp, + sizeof(qsfp)); +#else + ret = i2c_get_chip_for_busnum(0, I2C_SFP_EEPROM_ADDR, 1, &dev); + if (!ret) + ret = dm_i2c_read(dev, 0, (void *)&qsfp, sizeof(qsfp)); +#endif + + if (ret != 0) { + debug("\nQSFP: no module detected\n"); + return 0; + } + /* check if QSFP type */ + if (qsfp.base.identifier != DEV_ID_QSFP_PLUS) { + debug("\nQSFP: unrecognized module\n"); + return 0; + } + + /* copy fields and trim the whitespaces and dump on screen */ + snprintf(vendor, sizeof(vendor), "%.16s", qsfp.page0.vendor_name); + snprintf(serial, sizeof(serial), "%.16s", qsfp.page0.serial); + snprintf(pname, sizeof(pname), "%.16s", qsfp.page0.pn); + snprintf(mfgdt, sizeof(mfgdt), "%.2s/%.2s/%.2s", + &qsfp.page0.date[0], &qsfp.page0.date[2], &qsfp.page0.date[4]); + + printf("QSFP: detected %s %s s/n: %s mfgdt: %s\n", + strim(vendor), strim(pname), strim(serial), strim(mfgdt)); + + /* return ethernet compatibility code*/ + return qsfp.page0.compat[0]; +} diff --git a/board/freescale/common/qsfp_eeprom.h b/board/freescale/common/qsfp_eeprom.h new file mode 100644 index 00000000000..4cbbcb3a7b1 --- /dev/null +++ b/board/freescale/common/qsfp_eeprom.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019-2021 NXP + */ + +#ifndef __QSFP_EEPROM_H_ +#define __QSFP_EEPROM_H_ +/* + * QSFP eeprom reader external API interface. + */ + +/* return the ethernet compatibility field 0 */ +unsigned char get_qsfp_compat0(void); +#endif /* __QSFP_EEPROM_H_ */ diff --git a/board/freescale/common/qspi_header b/board/freescale/common/qspi_header new file mode 100644 index 00000000000..d4f3c12d418 --- /dev/null +++ b/board/freescale/common/qspi_header @@ -0,0 +1,128 @@ +0 /*dqs_loopback=0 or 1*/ +0 /*hold_delay=0 to 3*/ +0 /*hsphs=0 (Half Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/ +0 /*hsdly=0 (Half Speed Delay one clk delay) or 1 (two clk cycle delay)*/ +0 /*device_quad_mode_en=1 to enable sending command to SPI device*/ +0 /*device_cmd=command to device for enableing Quad I/O mode*/ +0 /*write_cmd_ipcr=hex value to be written to IPCR register for write cmd of device*/ +2000000 /*write_enable_ipcr=hex value to be written to IPCR register for write enable of device*/ +3 /*cs_hold_time=0 to 0xF*/ +3 /*cs_setup_time=0 to 0xF*/ +8000000 /*sflash_A1_size=size in byte(hex)*/ +0 /*sflash_A2_size=size in byte(hex)*/ +8000000 /*sflash_B1_size=size in byte(hex)*/ +0 /*sflash_B2_size=size in byte(hex)*/ +0 /*sclk_freq=0 to 6*/ +0 /*busy_bit_offset=bit position of device BUSY in device status register*/ +1 /*sflash_type=1 (Single), 2 (Dual), 4 (Quad mode of operation)*/ +0 /*sflash_port=0 or 1 (Port B used)*/ +0 /*ddr_mode_enable=0 or 1*/ +0 /*dqs_enable=0 or 1*/ +0 /*parallel_mode_enable=0 or 1*/ +0 /*portA_cs1=0 or 1*/ +0 /*portB_cs1=0 or 1*/ +0 /*fsphs=0 (Full Speed Phase sampling at non-inverted clock) or 1 (sampling at inverted clock)*/ +0 /*fsdly=0 (Full Speed Delay One clk delay) or 1 (two clk cycle delay)*/ +0 /*ddrsmp=0 to 7 (sampling point for incoming data in DDR mode)*/ +08180403 /*lut[0] command sequence*/ +24001c00 /*lut[1] command sequence*/ +0 /*lut[2] command sequence*/ +0 /*lut[3] command sequence*/ +0 /*lut[4] command sequence*/ +0 /*lut[5] command sequence*/ +0 /*lut[6] command sequence*/ +0 /*lut[7] command sequence*/ +0 /*lut[8] command sequence*/ +0 /*lut[9] command sequence*/ +0 /*lut[10] command sequence*/ +0 /*lut[11] command sequence*/ +0 /*lut[12] command sequence*/ +0 /*lut[13] command sequence*/ +0 /*lut[14] command sequence*/ +0 /*lut[15] command sequence*/ +0 /*lut[16] command sequence*/ +0 /*lut[17] command sequence*/ +0 /*lut[18] command sequence*/ +0 /*lut[19] command sequence*/ +0 /*lut[20] command sequence*/ +0 /*lut[21] command sequence*/ +0 /*lut[22] command sequence*/ +0 /*lut[23] command sequence*/ +0 /*lut[24] command sequence*/ +0 /*lut[25] command sequence*/ +0 /*lut[26] command sequence*/ +0 /*lut[27] command sequence*/ +0 /*lut[28] command sequence*/ +0 /*lut[29] command sequence*/ +0 /*lut[30] command sequence*/ +0 /*lut[31] command sequence*/ +0 /*lut[32] command sequence*/ +0 /*lut[33] command sequence*/ +0 /*lut[34] command sequence*/ +0 /*lut[35] command sequence*/ +0 /*lut[36] command sequence*/ +0 /*lut[37] command sequence*/ +0 /*lut[38] command sequence*/ +0 /*lut[39] command sequence*/ +0 /*lut[40] command sequence*/ +0 /*lut[41] command sequence*/ +0 /*lut[42] command sequence*/ +0 /*lut[43] command sequence*/ +0 /*lut[44] command sequence*/ +0 /*lut[45] command sequence*/ +0 /*lut[46] command sequence*/ +0 /*lut[47] command sequence*/ +0 /*lut[48] command sequence*/ +0 /*lut[49] command sequence*/ +0 /*lut[50] command sequence*/ +0 /*lut[51] command sequence*/ +0 /*lut[52] command sequence*/ +0 /*lut[53] command sequence*/ +0 /*lut[54] command sequence*/ +0 /*lut[55] command sequence*/ +0 /*lut[56] command sequence*/ +0 /*lut[57] command sequence*/ +0 /*lut[58] command sequence*/ +0 /*lut[59] command sequence*/ +0 /*lut[60] command sequence*/ +0 /*lut[61] command sequence*/ +0 /*lut[62] command sequence*/ +0 /*lut[63] command sequence*/ +1000001 /*read_status_ipcr=hex value to be written to IPCR register for reading status reg of device*/ +0 /*enable_dqs_phase=0 or 1*/ +0 /*config_cmds_en, enable config command*/ +0 /*config_cmds[0]*/ +0 /*config_cmds[1]*/ +0 /*config_cmds[2]*/ +0 /*config_cmds[3]*/ +0 /*config_cmds_args[0]*/ +0 /*config_cmds_args[1]*/ +0 /*config_cmds_args[2]*/ +0 /*config_cmds_args[3]*/ +0 /*io_pad_override_setting QSPI pins override setting*/ +0 /*reserve[0], 25 byte reserved area*/ +0 /*reserve[1], 25 byte reserved area*/ +0 /*reserve[2], 25 byte reserved area*/ +0 /*reserve[3], 25 byte reserved area*/ +0 /*reserve[4], 25 byte reserved area*/ +0 /*reserve[5], 25 byte reserved area*/ +0 /*reserve[6], 25 byte reserved area*/ +0 /*reserve[7], 25 byte reserved area*/ +0 /*reserve[8], 25 byte reserved area*/ +0 /*reserve[9], 25 byte reserved area*/ +0 /*reserve[10], 25 byte reserved area*/ +0 /*reserve[11], 25 byte reserved area*/ +0 /*reserve[12], 25 byte reserved area*/ +0 /*reserve[13], 25 byte reserved area*/ +0 /*reserve[14], 25 byte reserved area*/ +0 /*reserve[15], 25 byte reserved area*/ +0 /*reserve[16], 25 byte reserved area*/ +0 /*reserve[17], 25 byte reserved area*/ +0 /*reserve[18], 25 byte reserved area*/ +0 /*reserve[19], 25 byte reserved area*/ +0 /*reserve[20], 25 byte reserved area*/ +0 /*reserve[21], 25 byte reserved area*/ +0 /*reserve[22], 25 byte reserved area*/ +0 /*reserve[23], 25 byte reserved area*/ +0 /*reserve[24], 25 byte reserved area*/ +c0ffee01 /*tag, QSPI configuration tag, should be 0xc0ffee01*/ diff --git a/board/freescale/common/recovery_keypad.c b/board/freescale/common/recovery_keypad.c new file mode 100644 index 00000000000..2f5a58a92d8 --- /dev/null +++ b/board/freescale/common/recovery_keypad.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + */ +#include +#include +#include +#ifdef CONFIG_MXC_KPD +#include +#endif +#include + +#ifdef CONFIG_MXC_KPD +#define PRESSED_VOL_DOWN 0x01 +#define PRESSED_POWER 0x02 +#define RECOVERY_KEY_MASK (PRESSED_VOL_DOWN | PRESSED_POWER) + +inline int test_key(int value, struct kpp_key_info *ki) +{ + return (ki->val == value) && (ki->evt == KDepress); +} + +int is_recovery_keypad_pressing(void) +{ + struct kpp_key_info *key_info = NULL; + int state = 0, keys, i; + + int ret = 0; + + mxc_kpp_init(); + /* due to glitch suppression circuit, + wait sometime to let all keys scanned. */ + udelay(1000); + keys = mxc_kpp_getc(&key_info); + + printf("Detecting VOL_DOWN+POWER key for recovery(%d:%d) ...\n", + keys, keys ? key_info->val : 0); + if (keys > 1) { + for (i = 0; i < keys; i++) { + if (test_key(CONFIG_POWER_KEY, &key_info[i])) + state |= PRESSED_POWER; + else if (test_key(CONFIG_VOL_DOWN_KEY, &key_info[i])) + state |= PRESSED_VOL_DOWN; + } + } + if ((state & RECOVERY_KEY_MASK) == RECOVERY_KEY_MASK) + ret = 1; + if (key_info) + free(key_info); + return ret; +} +#else +/* If not using mxc keypad, currently we will detect power key on board */ +int is_recovery_keypad_pressing(void) +{ + return 0; +} +#endif diff --git a/board/freescale/common/recovery_keypad.h b/board/freescale/common/recovery_keypad.h new file mode 100644 index 00000000000..9adf2243e88 --- /dev/null +++ b/board/freescale/common/recovery_keypad.h @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + */ + +#ifndef __RECOVERY_KEYPAD_H_ +#define __RECOVERY_KEYPAD_H_ + +int is_recovery_keypad_pressing(void); + +#endif diff --git a/board/freescale/common/tcpc.c b/board/freescale/common/tcpc.c new file mode 100644 index 00000000000..f7d6ea66d3b --- /dev/null +++ b/board/freescale/common/tcpc.c @@ -0,0 +1,1036 @@ +/* + * Copyright 2017,2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include "tcpc.h" + +#ifdef DEBUG +#define tcpc_debug_log(port, fmt, args...) tcpc_log(port, fmt, ##args) +#else +#define tcpc_debug_log(port, fmt, args...) +#endif + +static int tcpc_log(struct tcpc_port *port, const char *fmt, ...) +{ + va_list args; + int i; + + va_start(args, fmt); + i = vscnprintf(port->log_p, port->log_size, fmt, args); + va_end(args); + + port->log_size -= i; + port->log_p += i; + + return i; +} + +int tcpc_set_cc_to_source(struct tcpc_port *port) +{ + uint8_t valb; + int err; + + if (port == NULL) + return -EINVAL; + + valb = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) | + (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) | + (TCPC_ROLE_CTRL_RP_VAL_DEF << + TCPC_ROLE_CTRL_RP_VAL_SHIFT) | TCPC_ROLE_CTRL_DRP; + + err = dm_i2c_write(port->i2c_dev, TCPC_ROLE_CTRL, &valb, 1); + if (err) + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return err; +} + +int tcpc_set_cc_to_sink(struct tcpc_port *port) +{ + uint8_t valb; + int err; + + if (port == NULL) + return -EINVAL; + + valb = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) | + (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT) | TCPC_ROLE_CTRL_DRP; + + err = dm_i2c_write(port->i2c_dev, TCPC_ROLE_CTRL, &valb, 1); + if (err) + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return err; +} + + +int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity polarity) +{ + uint8_t valb; + int err; + + if (port == NULL) + return -EINVAL; + + err = dm_i2c_read(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + if (polarity == TYPEC_POLARITY_CC2) + valb |= TCPC_TCPC_CTRL_ORIENTATION; + else + valb &= ~TCPC_TCPC_CTRL_ORIENTATION; + + err = dm_i2c_write(port->i2c_dev, TCPC_TCPC_CTRL, &valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return -EIO; + } + + return 0; +} + +int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, enum typec_cc_state *state) +{ + + uint8_t valb_cc, cc2, cc1; + int err; + + if (port == NULL || polarity == NULL || state == NULL) + return -EINVAL; + + err = dm_i2c_read(port->i2c_dev, TCPC_CC_STATUS, (uint8_t *)&valb_cc, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + tcpc_debug_log(port, "cc status 0x%x\n", valb_cc); + + cc2 = (valb_cc >> TCPC_CC_STATUS_CC2_SHIFT) & TCPC_CC_STATUS_CC2_MASK; + cc1 = (valb_cc >> TCPC_CC_STATUS_CC1_SHIFT) & TCPC_CC_STATUS_CC1_MASK; + + if (valb_cc & TCPC_CC_STATUS_LOOK4CONN) + return -EFAULT; + + *state = TYPEC_STATE_OPEN; + + if (valb_cc & TCPC_CC_STATUS_TERM) { + if (cc2) { + *polarity = TYPEC_POLARITY_CC2; + + switch (cc2) { + case 0x1: + *state = TYPEC_STATE_SNK_DEFAULT; + tcpc_log(port, "SNK.Default on CC2\n"); + break; + case 0x2: + *state = TYPEC_STATE_SNK_POWER15; + tcpc_log(port, "SNK.Power1.5 on CC2\n"); + break; + case 0x3: + *state = TYPEC_STATE_SNK_POWER30; + tcpc_log(port, "SNK.Power3.0 on CC2\n"); + break; + } + } else if (cc1) { + *polarity = TYPEC_POLARITY_CC1; + + switch (cc1) { + case 0x1: + *state = TYPEC_STATE_SNK_DEFAULT; + tcpc_log(port, "SNK.Default on CC1\n"); + break; + case 0x2: + *state = TYPEC_STATE_SNK_POWER15; + tcpc_log(port, "SNK.Power1.5 on CC1\n"); + break; + case 0x3: + *state = TYPEC_STATE_SNK_POWER30; + tcpc_log(port, "SNK.Power3.0 on CC1\n"); + break; + } + } else { + *state = TYPEC_STATE_OPEN; + return -EPERM; + } + + } else { + if (cc2) { + *polarity = TYPEC_POLARITY_CC2; + + switch (cc2) { + case 0x1: + if (cc1 == 0x1) { + *state = TYPEC_STATE_SRC_BOTH_RA; + tcpc_log(port, "SRC.Ra on both CC1 and CC2\n"); + } else if (cc1 == 0x2) { + *state = TYPEC_STATE_SRC_RD_RA; + tcpc_log(port, "SRC.Ra on CC2, SRC.Rd on CC1\n"); + } else if (cc1 == 0x0) { + tcpc_log(port, "SRC.Ra only on CC2\n"); + return -EFAULT; + } else + return -EFAULT; + break; + case 0x2: + if (cc1 == 0x1) { + *state = TYPEC_STATE_SRC_RD_RA; + tcpc_log(port, "SRC.Ra on CC1, SRC.Rd on CC2\n"); + } else if (cc1 == 0x0) { + *state = TYPEC_STATE_SRC_RD; + tcpc_log(port, "SRC.Rd on CC2\n"); + } else + return -EFAULT; + break; + case 0x3: + *state = TYPEC_STATE_SRC_RESERVED; + return -EFAULT; + } + } else if (cc1) { + *polarity = TYPEC_POLARITY_CC1; + + switch (cc1) { + case 0x1: + tcpc_log(port, "SRC.Ra only on CC1\n"); + return -EFAULT; + case 0x2: + *state = TYPEC_STATE_SRC_RD; + tcpc_log(port, "SRC.Rd on CC1\n"); + break; + case 0x3: + *state = TYPEC_STATE_SRC_RESERVED; + return -EFAULT; + } + } else { + *state = TYPEC_STATE_OPEN; + return -EPERM; + } + } + + return 0; +} + +int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask) +{ + int err; + + if (port == NULL) + return -EINVAL; + + err = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&clear_mask, 2); + if (err) { + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return -EIO; + } + + return 0; +} + +int tcpc_send_command(struct tcpc_port *port, uint8_t command) +{ + int err; + + if (port == NULL) + return -EINVAL; + + err = dm_i2c_write(port->i2c_dev, TCPC_COMMAND, (const uint8_t *)&command, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return -EIO; + } + + return 0; +} + +int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg, + uint8_t reg_width, uint16_t mask, uint16_t value, ulong timeout_ms) +{ + uint16_t val = 0; + int err; + ulong start; + + if (port == NULL) + return -EINVAL; + + tcpc_debug_log(port, "%s reg 0x%x, mask 0x%x, value 0x%x\n", __func__, reg, mask, value); + + /* TCPC registers is 8 bits or 16 bits */ + if (reg_width != 1 && reg_width != 2) + return -EINVAL; + + start = get_timer(0); /* Get current timestamp */ + do { + err = dm_i2c_read(port->i2c_dev, reg, (uint8_t *)&val, reg_width); + if (err) + return -EIO; + + if ((val & mask) == value) + return 0; + } while (get_timer(0) < (start + timeout_ms)); + + return -ETIME; +} + +void tcpc_print_log(struct tcpc_port *port) +{ + if (port == NULL) + return; + + if (port->log_print == port->log_p) /*nothing to output*/ + return; + + printf("%s", port->log_print); + + port->log_print = port->log_p; +} + +int tcpc_setup_dfp_mode(struct tcpc_port *port) +{ + enum typec_cc_polarity pol; + enum typec_cc_state state; + int ret; + + if ((port == NULL) || (port->i2c_dev == NULL)) + return -EINVAL; + + if (tcpc_pd_sink_check_charging(port)) { + tcpc_log(port, "%s: Can't apply DFP mode when PD is charging\n", + __func__); + return -EPERM; + } + + tcpc_set_cc_to_source(port); + + ret = tcpc_send_command(port, TCPC_CMD_LOOK4CONNECTION); + if (ret) + return ret; + + /* At least wait tCcStatusDelay + tTCPCFilter + tCcTCPCSampleRate (max) = 200us + 500us + ?ms + * PTN5110 datasheet does not contain the sample rate value, according other productions, + * the sample rate is at ms level, about 2 ms -10ms. So wait 100ms should be enough. + */ + mdelay(100); + + ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_CC_STATUS, TCPC_ALERT_CC_STATUS, 100); + if (ret) { + tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_CC_STATUS bit failed, ret = %d\n", + __func__, ret); + return ret; + } + + ret = tcpc_get_cc_status(port, &pol, &state); + tcpc_clear_alert(port, TCPC_ALERT_CC_STATUS); + + if (!ret) { + /* If presenting as Rd/audio mode/open, return */ + if (state != TYPEC_STATE_SRC_RD_RA && state != TYPEC_STATE_SRC_RD) + return -EPERM; + + if (pol == TYPEC_POLARITY_CC1) + tcpc_debug_log(port, "polarity cc1\n"); + else + tcpc_debug_log(port, "polarity cc2\n"); + + if (port->ss_sel_func) + port->ss_sel_func(pol); + + ret = tcpc_set_plug_orientation(port, pol); + if (ret) + return ret; + + /* Enable source vbus default voltage */ + ret = tcpc_send_command(port, TCPC_CMD_SRC_VBUS_DEFAULT); + if (ret) + return ret; + + /* The max vbus on time is 200ms, we add margin 100ms */ + mdelay(300); + + } + + return 0; +} + +int tcpc_setup_ufp_mode(struct tcpc_port *port) +{ + enum typec_cc_polarity pol; + enum typec_cc_state state; + int ret; + + if ((port == NULL) || (port->i2c_dev == NULL)) + return -EINVAL; + + /* Check if the PD charge is working. If not, need to configure CC role for UFP */ + if (!tcpc_pd_sink_check_charging(port)) { + + /* Disable the source vbus once it is enabled by DFP mode */ + tcpc_disable_src_vbus(port); + + tcpc_set_cc_to_sink(port); + + ret = tcpc_send_command(port, TCPC_CMD_LOOK4CONNECTION); + if (ret) + return ret; + + /* At least wait tCcStatusDelay + tTCPCFilter + tCcTCPCSampleRate (max) = 200us + 500us + ?ms + * PTN5110 datasheet does not contain the sample rate value, according other productions, + * the sample rate is at ms level, about 2 ms -10ms. So wait 100ms should be enough. + */ + mdelay(100); + + ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_CC_STATUS, TCPC_ALERT_CC_STATUS, 100); + if (ret) { + tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_CC_STATUS bit failed, ret = %d\n", + __func__, ret); + return ret; + } + + ret = tcpc_get_cc_status(port, &pol, &state); + tcpc_clear_alert(port, TCPC_ALERT_CC_STATUS); + + } else { + ret = tcpc_get_cc_status(port, &pol, &state); + } + + if (!ret) { + /* If presenting not as sink, then return */ + if (state != TYPEC_STATE_SNK_DEFAULT && state != TYPEC_STATE_SNK_POWER15 && + state != TYPEC_STATE_SNK_POWER30) + return -EPERM; + + if (pol == TYPEC_POLARITY_CC1) + tcpc_debug_log(port, "polarity cc1\n"); + else + tcpc_debug_log(port, "polarity cc2\n"); + + if (port->ss_sel_func) + port->ss_sel_func(pol); + + ret = tcpc_set_plug_orientation(port, pol); + if (ret) + return ret; + } + + return 0; +} + +int tcpc_disable_src_vbus(struct tcpc_port *port) +{ + int ret; + + if (port == NULL) + return -EINVAL; + + /* Disable VBUS*/ + ret = tcpc_send_command(port, TCPC_CMD_DISABLE_SRC_VBUS); + if (ret) + return ret; + + /* The max vbus off time is 0.5ms, we add margin 0.5 ms */ + mdelay(1); + + return 0; +} + +int tcpc_disable_sink_vbus(struct tcpc_port *port) +{ + int ret; + + if (port == NULL) + return -EINVAL; + + /* Disable SINK VBUS*/ + ret = tcpc_send_command(port, TCPC_CMD_DISABLE_SINK_VBUS); + if (ret) + return ret; + + /* The max vbus off time is 0.5ms, we add margin 0.5 ms */ + mdelay(1); + + return 0; +} + + +static int tcpc_pd_receive_message(struct tcpc_port *port, struct pd_message *msg) +{ + int ret; + uint8_t cnt; + uint16_t val; + + if (port == NULL) + return -EINVAL; + + /* Generally the max tSenderResponse is 30ms, max tTypeCSendSourceCap is 200ms, we set the timeout to 500ms */ + ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_RX_STATUS, TCPC_ALERT_RX_STATUS, 500); + if (ret) { + tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_RX_STATUS bit failed, ret = %d\n", + __func__, ret); + return ret; + } + + cnt = 0; + ret = dm_i2c_read(port->i2c_dev, TCPC_RX_BYTE_CNT, (uint8_t *)&cnt, 1); + if (ret) + return -EIO; + + if (cnt > 0) { + ret = dm_i2c_read(port->i2c_dev, TCPC_RX_BUF_FRAME_TYPE, (uint8_t *)msg, cnt); + if (ret) + return -EIO; + + /* Clear RX status alert bit */ + val = TCPC_ALERT_RX_STATUS; + ret = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&val, 2); + if (ret) + return -EIO; + } + + return cnt; +} + +static int tcpc_pd_transmit_message(struct tcpc_port *port, struct pd_message *msg_p, uint8_t bytes) +{ + int ret; + uint8_t valb; + uint16_t val = 0; + + if (port == NULL) + return -EINVAL; + + if (msg_p == NULL || bytes <= 0) + return -EINVAL; + + ret = dm_i2c_write(port->i2c_dev, TCPC_TX_BYTE_CNT, (const uint8_t *)&bytes, 1); + if (ret) + return -EIO; + + ret = dm_i2c_write(port->i2c_dev, TCPC_TX_HDR, (const uint8_t *)&(msg_p->header), bytes); + if (ret) + return -EIO; + + valb = (3 << TCPC_TRANSMIT_RETRY_SHIFT) | (TCPC_TX_SOP << TCPC_TRANSMIT_TYPE_SHIFT); + ret = dm_i2c_write(port->i2c_dev, TCPC_TRANSMIT, (const uint8_t *)&valb, 1); + if (ret) + return -EIO; + + /* Max tReceive is 1.1ms, we set to 5ms timeout */ + ret = tcpc_polling_reg(port, TCPC_ALERT, 2, TCPC_ALERT_TX_SUCCESS, TCPC_ALERT_TX_SUCCESS, 5); + if (ret) { + if (ret == -ETIME) { + ret = dm_i2c_read(port->i2c_dev, TCPC_ALERT, (uint8_t *)&val, 2); + if (ret) + return -EIO; + + if (val & TCPC_ALERT_TX_FAILED) + tcpc_log(port, "%s: PD TX FAILED, ALERT = 0x%x\n", __func__, val); + + if (val & TCPC_ALERT_TX_DISCARDED) + tcpc_log(port, "%s: PD TX DISCARDED, ALERT = 0x%x\n", __func__, val); + + } else { + tcpc_log(port, "%s: Polling ALERT register, TCPC_ALERT_TX_SUCCESS bit failed, ret = %d\n", + __func__, ret); + } + } else { + port->tx_msg_id = (port->tx_msg_id + 1) & PD_HEADER_ID_MASK; + } + + /* Clear ALERT status */ + val &= (TCPC_ALERT_TX_FAILED | TCPC_ALERT_TX_DISCARDED | TCPC_ALERT_TX_SUCCESS); + ret = dm_i2c_write(port->i2c_dev, TCPC_ALERT, (const uint8_t *)&val, 2); + if (ret) + return -EIO; + + return ret; +} + +static void tcpc_log_source_caps(struct tcpc_port *port, struct pd_message *msg, unsigned int capcount) +{ + int i; + + for (i = 0; i < capcount; i++) { + u32 pdo = msg->payload[i]; + enum pd_pdo_type type = pdo_type(pdo); + + tcpc_log(port, "PDO %d: type %d, ", + i, type); + + switch (type) { + case PDO_TYPE_FIXED: + tcpc_log(port, "%u mV, %u mA [%s%s%s%s%s%s]\n", + pdo_fixed_voltage(pdo), + pdo_max_current(pdo), + (pdo & PDO_FIXED_DUAL_ROLE) ? + "R" : "", + (pdo & PDO_FIXED_SUSPEND) ? + "S" : "", + (pdo & PDO_FIXED_HIGHER_CAP) ? + "H" : "", + (pdo & PDO_FIXED_USB_COMM) ? + "U" : "", + (pdo & PDO_FIXED_DATA_SWAP) ? + "D" : "", + (pdo & PDO_FIXED_EXTPOWER) ? + "E" : ""); + break; + case PDO_TYPE_VAR: + tcpc_log(port, "%u-%u mV, %u mA\n", + pdo_min_voltage(pdo), + pdo_max_voltage(pdo), + pdo_max_current(pdo)); + break; + case PDO_TYPE_BATT: + tcpc_log(port, "%u-%u mV, %u mW\n", + pdo_min_voltage(pdo), + pdo_max_voltage(pdo), + pdo_max_power(pdo)); + break; + default: + tcpc_log(port, "undefined\n"); + break; + } + } +} + +static int tcpc_pd_select_pdo(struct pd_message *msg, uint32_t capcount, uint32_t max_snk_mv, uint32_t max_snk_ma) +{ + unsigned int i, max_mw = 0, max_mv = 0; + int ret = -EINVAL; + + /* + * Select the source PDO providing the most power while staying within + * the board's voltage limits. Prefer PDO providing exp + */ + for (i = 0; i < capcount; i++) { + u32 pdo = msg->payload[i]; + enum pd_pdo_type type = pdo_type(pdo); + unsigned int mv, ma, mw; + + if (type == PDO_TYPE_FIXED) + mv = pdo_fixed_voltage(pdo); + else + mv = pdo_min_voltage(pdo); + + if (type == PDO_TYPE_BATT) { + mw = pdo_max_power(pdo); + } else { + ma = min(pdo_max_current(pdo), + max_snk_ma); + mw = ma * mv / 1000; + } + + /* Perfer higher voltages if available */ + if ((mw > max_mw || (mw == max_mw && mv > max_mv)) && + mv <= max_snk_mv) { + ret = i; + max_mw = mw; + max_mv = mv; + } + } + + return ret; +} + +static int tcpc_pd_build_request(struct tcpc_port *port, + struct pd_message *msg, + uint32_t capcount, + uint32_t max_snk_mv, + uint32_t max_snk_ma, + uint32_t max_snk_mw, + uint32_t operating_snk_mw, + uint32_t *rdo) +{ + unsigned int mv, ma, mw, flags; + unsigned int max_ma, max_mw; + enum pd_pdo_type type; + int index; + u32 pdo; + + index = tcpc_pd_select_pdo(msg, capcount, max_snk_mv, max_snk_ma); + if (index < 0) + return -EINVAL; + + pdo = msg->payload[index]; + type = pdo_type(pdo); + + if (type == PDO_TYPE_FIXED) + mv = pdo_fixed_voltage(pdo); + else + mv = pdo_min_voltage(pdo); + + /* Select maximum available current within the board's power limit */ + if (type == PDO_TYPE_BATT) { + mw = pdo_max_power(pdo); + ma = 1000 * min(mw, max_snk_mw) / mv; + } else { + ma = min(pdo_max_current(pdo), + 1000 * max_snk_mw / mv); + } + ma = min(ma, max_snk_ma); + + /* XXX: Any other flags need to be set? */ + flags = 0; + + /* Set mismatch bit if offered power is less than operating power */ + mw = ma * mv / 1000; + max_ma = ma; + max_mw = mw; + if (mw < operating_snk_mw) { + flags |= RDO_CAP_MISMATCH; + max_mw = operating_snk_mw; + max_ma = max_mw * 1000 / mv; + } + + if (type == PDO_TYPE_BATT) { + *rdo = RDO_BATT(index + 1, mw, max_mw, flags); + + tcpc_log(port, "Requesting PDO %d: %u mV, %u mW%s\n", + index, mv, mw, + flags & RDO_CAP_MISMATCH ? " [mismatch]" : ""); + } else { + *rdo = RDO_FIXED(index + 1, ma, max_ma, flags); + + tcpc_log(port, "Requesting PDO %d: %u mV, %u mA%s\n", + index, mv, ma, + flags & RDO_CAP_MISMATCH ? " [mismatch]" : ""); + } + + return 0; +} + +static void tcpc_pd_sink_process(struct tcpc_port *port) +{ + int ret; + uint8_t msgtype; + uint32_t objcnt; + struct pd_message msg; + enum pd_sink_state pd_state = WAIT_SOURCE_CAP; + + while (tcpc_pd_receive_message(port, &msg) > 0) { + + msgtype = pd_header_type(msg.header); + objcnt = pd_header_cnt_le(msg.header); + + tcpc_debug_log(port, "get msg, type %d, cnt %d\n", msgtype, objcnt); + + switch (pd_state) { + case WAIT_SOURCE_CAP: + case SINK_READY: + if (msgtype != PD_DATA_SOURCE_CAP) + continue; + + uint32_t rdo = 0; + + tcpc_log_source_caps(port, &msg, objcnt); + + tcpc_pd_build_request(port, &msg, objcnt, + port->cfg.max_snk_mv, port->cfg.max_snk_ma, + port->cfg.max_snk_mw, port->cfg.op_snk_mv, + &rdo); + + memset(&msg, 0, sizeof(msg)); + msg.header = PD_HEADER(PD_DATA_REQUEST, 0, 0, port->tx_msg_id, 1); /* power sink, data device, id 0, len 1 */ + msg.payload[0] = rdo; + + ret = tcpc_pd_transmit_message(port, &msg, 6); + if (ret) + tcpc_log(port, "send request failed\n"); + else + pd_state = WAIT_SOURCE_ACCEPT; + + break; + case WAIT_SOURCE_ACCEPT: + if (objcnt > 0) /* Should be ctrl message */ + continue; + + if (msgtype == PD_CTRL_ACCEPT) { + pd_state = WAIT_SOURCE_READY; + tcpc_log(port, "Source accept request\n"); + } else if (msgtype == PD_CTRL_REJECT) { + tcpc_log(port, "Source reject request\n"); + return; + } + + break; + case WAIT_SOURCE_READY: + if (objcnt > 0) /* Should be ctrl message */ + continue; + + if (msgtype == PD_CTRL_PS_RDY) { + tcpc_log(port, "PD source ready!\n"); + pd_state = SINK_READY; + } + + break; + default: + tcpc_log(port, "unexpect status: %u\n", pd_state); + break; + } + } +} + +bool tcpc_pd_sink_check_charging(struct tcpc_port *port) +{ + uint8_t valb; + int err; + enum typec_cc_polarity pol; + enum typec_cc_state state; + + if (port == NULL) + return false; + + /* Check the CC status, must be sink */ + err = tcpc_get_cc_status(port, &pol, &state); + if (err || (state != TYPEC_STATE_SNK_POWER15 + && state != TYPEC_STATE_SNK_POWER30 + && state != TYPEC_STATE_SNK_DEFAULT)) { + tcpc_debug_log(port, "TCPC wrong state for PD charging, err = %d, CC = 0x%x\n", + err, state); + return false; + } + + /* Check the VBUS PRES and SINK VBUS for dead battery */ + err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1); + if (err) { + tcpc_debug_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return false; + } + + if (!(valb & TCPC_POWER_STATUS_VBUS_PRES)) { + tcpc_debug_log(port, "VBUS NOT PRES \n"); + return false; + } + + if (!(valb & TCPC_POWER_STATUS_SINKING_VBUS)) { + tcpc_debug_log(port, "SINK VBUS is not enabled for dead battery\n"); + return false; + } + + return true; +} + +static int tcpc_pd_sink_disable(struct tcpc_port *port) +{ + uint8_t valb; + int err; + + if (port == NULL) + return -EINVAL; + + port->pd_state = UNATTACH; + + /* Check the VBUS PRES and SINK VBUS for dead battery */ + err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + if ((valb & TCPC_POWER_STATUS_VBUS_PRES) && (valb & TCPC_POWER_STATUS_SINKING_VBUS)) { + err = dm_i2c_read(port->i2c_dev, TCPC_POWER_CTRL, (uint8_t *)&valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + valb &= ~TCPC_POWER_CTRL_AUTO_DISCH_DISCO; /* disable AutoDischargeDisconnect */ + err = dm_i2c_write(port->i2c_dev, TCPC_POWER_CTRL, (const uint8_t *)&valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return -EIO; + } + + tcpc_disable_sink_vbus(port); + } + + if (port->cfg.switch_setup_func) + port->cfg.switch_setup_func(port); + + return 0; +} + +static int tcpc_pd_sink_init(struct tcpc_port *port) +{ + uint8_t valb; + uint16_t val; + int err; + enum typec_cc_polarity pol; + enum typec_cc_state state; + + if (port == NULL) + return -EINVAL; + + port->pd_state = UNATTACH; + + /* Check the VBUS PRES and SINK VBUS for dead battery */ + err = dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + if (!(valb & TCPC_POWER_STATUS_VBUS_PRES)) { + tcpc_debug_log(port, "VBUS NOT PRES \n"); + return -EPERM; + } + + if (!(valb & TCPC_POWER_STATUS_SINKING_VBUS)) { + tcpc_debug_log(port, "SINK VBUS is not enabled for dead battery\n"); + return -EPERM; + } + + err = dm_i2c_read(port->i2c_dev, TCPC_ALERT, (uint8_t *)&val, 2); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + if (!(val & TCPC_ALERT_CC_STATUS)) { + tcpc_debug_log(port, "CC STATUS not detected for dead battery\n"); + return -EPERM; + } + + err = tcpc_get_cc_status(port, &pol, &state); + if (err || (state != TYPEC_STATE_SNK_POWER15 + && state != TYPEC_STATE_SNK_POWER30 + && state != TYPEC_STATE_SNK_DEFAULT)) { + tcpc_log(port, "TCPC wrong state for dead battery, err = %d, CC = 0x%x\n", + err, state); + return -EPERM; + } else { + err = tcpc_set_plug_orientation(port, pol); + if (err) { + tcpc_log(port, "TCPC set plug orientation failed, err = %d\n", err); + return err; + } + port->pd_state = ATTACHED; + } + + err = dm_i2c_read(port->i2c_dev, TCPC_POWER_CTRL, (uint8_t *)&valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + valb &= ~TCPC_POWER_CTRL_AUTO_DISCH_DISCO; /* disable AutoDischargeDisconnect */ + err = dm_i2c_write(port->i2c_dev, TCPC_POWER_CTRL, (const uint8_t *)&valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_write failed, err %d\n", __func__, err); + return -EIO; + } + + if (port->cfg.switch_setup_func) + port->cfg.switch_setup_func(port); + + /* As sink role */ + valb = 0x00; + err = dm_i2c_write(port->i2c_dev, TCPC_MSG_HDR_INFO, (const uint8_t *)&valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + /* Enable rx */ + valb = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET; + err = dm_i2c_write(port->i2c_dev, TCPC_RX_DETECT, (const uint8_t *)&valb, 1); + if (err) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, err); + return -EIO; + } + + tcpc_pd_sink_process(port); + + return 0; +} + +int tcpc_init(struct tcpc_port *port, struct tcpc_port_config config, ss_mux_sel ss_sel_func) +{ + int ret; + uint8_t valb; + uint16_t vid, pid; + struct udevice *bus; + struct udevice *i2c_dev = NULL; + + memset(port, 0, sizeof(struct tcpc_port)); + + if (port == NULL) + return -EINVAL; + + port->cfg = config; + port->tx_msg_id = 0; + port->ss_sel_func = ss_sel_func; + port->log_p = (char *)&(port->logbuffer); + port->log_size = TCPC_LOG_BUFFER_SIZE; + port->log_print = port->log_p; + memset(&(port->logbuffer), 0, TCPC_LOG_BUFFER_SIZE); + + ret = uclass_get_device_by_seq(UCLASS_I2C, port->cfg.i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, port->cfg.addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, config.addr); + return -ENODEV; + } + + port->i2c_dev = i2c_dev; + + /* Check the Initialization Status bit in 1s */ + ret = tcpc_polling_reg(port, TCPC_POWER_STATUS, 1, TCPC_POWER_STATUS_UNINIT, 0, 1000); + if (ret) { + tcpc_log(port, "%s: Polling TCPC POWER STATUS Initialization Status bit failed, ret = %d\n", + __func__, ret); + return ret; + } + + dm_i2c_read(port->i2c_dev, TCPC_POWER_STATUS, &valb, 1); + tcpc_debug_log(port, "POWER STATUS: 0x%x\n", valb); + + /* Clear AllRegistersResetToDefault */ + valb = 0x80; + ret = dm_i2c_write(port->i2c_dev, TCPC_FAULT_STATUS, (const uint8_t *)&valb, 1); + if (ret) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Read Vendor ID and Product ID */ + ret = dm_i2c_read(port->i2c_dev, TCPC_VENDOR_ID, (uint8_t *)&vid, 2); + if (ret) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + + ret = dm_i2c_read(port->i2c_dev, TCPC_PRODUCT_ID, (uint8_t *)&pid, 2); + if (ret) { + tcpc_log(port, "%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + + tcpc_log(port, "TCPC: Vendor ID [0x%x], Product ID [0x%x], Addr [I2C%u 0x%x]\n", + vid, pid, port->cfg.i2c_bus, port->cfg.addr); + + if (!port->cfg.disable_pd) { + if (port->cfg.port_type == TYPEC_PORT_UFP + || port->cfg.port_type == TYPEC_PORT_DRP) + tcpc_pd_sink_init(port); + } else { + tcpc_pd_sink_disable(port); + } + + tcpc_clear_alert(port, 0xffff); + + tcpc_print_log(port); + + return 0; +} diff --git a/board/freescale/common/tcpc.h b/board/freescale/common/tcpc.h new file mode 100644 index 00000000000..ff749518a8b --- /dev/null +++ b/board/freescale/common/tcpc.h @@ -0,0 +1,469 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TCPCI_H +#define __TCPCI_H + +#include + +#define TCPC_VENDOR_ID 0x0 +#define TCPC_PRODUCT_ID 0x2 + +#define TCPC_ALERT 0x10 +#define TCPC_ALERT_VBUS_DISCNCT BIT(11) +#define TCPC_ALERT_RX_BUF_OVF BIT(10) +#define TCPC_ALERT_FAULT BIT(9) +#define TCPC_ALERT_V_ALARM_LO BIT(8) +#define TCPC_ALERT_V_ALARM_HI BIT(7) +#define TCPC_ALERT_TX_SUCCESS BIT(6) +#define TCPC_ALERT_TX_DISCARDED BIT(5) +#define TCPC_ALERT_TX_FAILED BIT(4) +#define TCPC_ALERT_RX_HARD_RST BIT(3) +#define TCPC_ALERT_RX_STATUS BIT(2) +#define TCPC_ALERT_POWER_STATUS BIT(1) +#define TCPC_ALERT_CC_STATUS BIT(0) + +#define TCPC_TCPC_CTRL 0x19 +#define TCPC_TCPC_CTRL_BIST_MODE BIT(1) +#define TCPC_TCPC_CTRL_ORIENTATION BIT(0) + +#define TCPC_ROLE_CTRL 0x1a +#define TCPC_ROLE_CTRL_DRP BIT(6) +#define TCPC_ROLE_CTRL_RP_VAL_SHIFT 4 +#define TCPC_ROLE_CTRL_RP_VAL_MASK 0x3 +#define TCPC_ROLE_CTRL_RP_VAL_DEF 0x0 +#define TCPC_ROLE_CTRL_RP_VAL_1_5 0x1 +#define TCPC_ROLE_CTRL_RP_VAL_3_0 0x2 +#define TCPC_ROLE_CTRL_CC2_SHIFT 2 +#define TCPC_ROLE_CTRL_CC2_MASK 0x3 +#define TCPC_ROLE_CTRL_CC1_SHIFT 0 +#define TCPC_ROLE_CTRL_CC1_MASK 0x3 +#define TCPC_ROLE_CTRL_CC_RA 0x0 +#define TCPC_ROLE_CTRL_CC_RP 0x1 +#define TCPC_ROLE_CTRL_CC_RD 0x2 +#define TCPC_ROLE_CTRL_CC_OPEN 0x3 + +#define TCPC_POWER_CTRL 0x1c +#define TCPC_POWER_CTRL_EN_VCONN BIT(0) +#define TCPC_POWER_CTRL_VCONN_POWER BIT(1) +#define TCPC_POWER_CTRL_FORCE_DISCH BIT(2) +#define TCPC_POWER_CTRL_EN_BLEED_CH BIT(3) +#define TCPC_POWER_CTRL_AUTO_DISCH_DISCO BIT(4) +#define TCPC_POWER_CTRL_DIS_V_ALARMS BIT(5) +#define TCPC_POWER_CTRL_VBUS_V_MONITOR BIT(6) + +#define TCPC_CC_STATUS 0x1d +#define TCPC_CC_STATUS_LOOK4CONN BIT(5) +#define TCPC_CC_STATUS_TERM BIT(4) +#define TCPC_CC_STATUS_CC2_SHIFT 2 +#define TCPC_CC_STATUS_CC2_MASK 0x3 +#define TCPC_CC_STATUS_CC1_SHIFT 0 +#define TCPC_CC_STATUS_CC1_MASK 0x3 + +#define TCPC_POWER_STATUS 0x1e +#define TCPC_POWER_STATUS_UNINIT BIT(6) +#define TCPC_POWER_STATUS_VBUS_DET BIT(3) +#define TCPC_POWER_STATUS_VBUS_PRES BIT(2) +#define TCPC_POWER_STATUS_SINKING_VBUS BIT(0) + +#define TCPC_FAULT_STATUS 0x1f + +#define TCPC_COMMAND 0x23 +#define TCPC_CMD_WAKE_I2C 0x11 +#define TCPC_CMD_DISABLE_VBUS_DETECT 0x22 +#define TCPC_CMD_ENABLE_VBUS_DETECT 0x33 +#define TCPC_CMD_DISABLE_SINK_VBUS 0x44 +#define TCPC_CMD_SINK_VBUS 0x55 +#define TCPC_CMD_DISABLE_SRC_VBUS 0x66 +#define TCPC_CMD_SRC_VBUS_DEFAULT 0x77 +#define TCPC_CMD_SRC_VBUS_HIGH 0x88 +#define TCPC_CMD_LOOK4CONNECTION 0x99 +#define TCPC_CMD_RXONEMORE 0xAA +#define TCPC_CMD_I2C_IDLE 0xFF + +#define TCPC_DEV_CAP_1 0x24 +#define TCPC_DEV_CAP_2 0x26 +#define TCPC_STD_INPUT_CAP 0x28 +#define TCPC_STD_OUTPUT_CAP 0x29 + +#define TCPC_MSG_HDR_INFO 0x2e +#define TCPC_MSG_HDR_INFO_DATA_ROLE BIT(3) +#define TCPC_MSG_HDR_INFO_PWR_ROLE BIT(0) +#define TCPC_MSG_HDR_INFO_REV_SHIFT 1 +#define TCPC_MSG_HDR_INFO_REV_MASK 0x3 + +#define TCPC_RX_DETECT 0x2f +#define TCPC_RX_DETECT_HARD_RESET BIT(5) +#define TCPC_RX_DETECT_SOP BIT(0) + +#define TCPC_RX_BYTE_CNT 0x30 +#define TCPC_RX_BUF_FRAME_TYPE 0x31 +#define TCPC_RX_HDR 0x32 +#define TCPC_RX_DATA 0x34 /* through 0x4f */ + +#define TCPC_TRANSMIT 0x50 +#define TCPC_TRANSMIT_RETRY_SHIFT 4 +#define TCPC_TRANSMIT_RETRY_MASK 0x3 +#define TCPC_TRANSMIT_TYPE_SHIFT 0 +#define TCPC_TRANSMIT_TYPE_MASK 0x7 + +#define TCPC_TX_BYTE_CNT 0x51 +#define TCPC_TX_HDR 0x52 +#define TCPC_TX_DATA 0x54 /* through 0x6f */ + +#define TCPC_VBUS_VOLTAGE 0x70 +#define TCPC_VBUS_VOL_MASK 0x3ff +#define TCPC_VBUS_VOL_SCALE_FACTOR_MASK 0xc00 +#define TCPC_VBUS_VOL_SCALE_FACTOR_SHIFT 10 +#define TCPC_VBUS_VOL_MV_UNIT 25 + +#define TCPC_VBUS_SINK_DISCONNECT_THRESH 0x72 +#define TCPC_VBUS_STOP_DISCHARGE_THRESH 0x74 +#define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG 0x76 +#define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG 0x78 + +enum typec_role { + TYPEC_SINK, + TYPEC_SOURCE, + TYPEC_ROLE_UNKNOWN, +}; + +enum typec_data_role { + TYPEC_DEVICE, + TYPEC_HOST, +}; + +enum typec_cc_polarity { + TYPEC_POLARITY_CC1, + TYPEC_POLARITY_CC2, +}; + +enum typec_cc_state { + TYPEC_STATE_OPEN, + TYPEC_STATE_SRC_BOTH_RA, + TYPEC_STATE_SRC_RD_RA, + TYPEC_STATE_SRC_RD, + TYPEC_STATE_SRC_RESERVED, + TYPEC_STATE_SNK_DEFAULT, + TYPEC_STATE_SNK_POWER15, + TYPEC_STATE_SNK_POWER30, +}; + + +/* USB PD Messages */ +enum pd_ctrl_msg_type { + /* 0 Reserved */ + PD_CTRL_GOOD_CRC = 1, + PD_CTRL_GOTO_MIN = 2, + PD_CTRL_ACCEPT = 3, + PD_CTRL_REJECT = 4, + PD_CTRL_PING = 5, + PD_CTRL_PS_RDY = 6, + PD_CTRL_GET_SOURCE_CAP = 7, + PD_CTRL_GET_SINK_CAP = 8, + PD_CTRL_DR_SWAP = 9, + PD_CTRL_PR_SWAP = 10, + PD_CTRL_VCONN_SWAP = 11, + PD_CTRL_WAIT = 12, + PD_CTRL_SOFT_RESET = 13, + /* 14-15 Reserved */ +}; + +enum pd_data_msg_type { + /* 0 Reserved */ + PD_DATA_SOURCE_CAP = 1, + PD_DATA_REQUEST = 2, + PD_DATA_BIST = 3, + PD_DATA_SINK_CAP = 4, + /* 5-14 Reserved */ + PD_DATA_VENDOR_DEF = 15, +}; + +enum tcpc_transmit_type { + TCPC_TX_SOP = 0, + TCPC_TX_SOP_PRIME = 1, + TCPC_TX_SOP_PRIME_PRIME = 2, + TCPC_TX_SOP_DEBUG_PRIME = 3, + TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4, + TCPC_TX_HARD_RESET = 5, + TCPC_TX_CABLE_RESET = 6, + TCPC_TX_BIST_MODE_2 = 7 +}; + +enum pd_sink_state{ + UNATTACH = 0, + ATTACHED, + WAIT_SOURCE_CAP, + WAIT_SOURCE_ACCEPT, + WAIT_SOURCE_READY, + SINK_READY, +}; + + +#define PD_REV10 0x0 +#define PD_REV20 0x1 + +#define PD_HEADER_CNT_SHIFT 12 +#define PD_HEADER_CNT_MASK 0x7 +#define PD_HEADER_ID_SHIFT 9 +#define PD_HEADER_ID_MASK 0x7 +#define PD_HEADER_PWR_ROLE BIT(8) +#define PD_HEADER_REV_SHIFT 6 +#define PD_HEADER_REV_MASK 0x3 +#define PD_HEADER_DATA_ROLE BIT(5) +#define PD_HEADER_TYPE_SHIFT 0 +#define PD_HEADER_TYPE_MASK 0xf + +#define PD_HEADER(type, pwr, data, id, cnt) \ + ((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) | \ + ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) | \ + ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) | \ + (PD_REV20 << PD_HEADER_REV_SHIFT) | \ + (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) | \ + (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT)) + + +static inline unsigned int pd_header_cnt(uint16_t header) +{ + return (header >> PD_HEADER_CNT_SHIFT) & PD_HEADER_CNT_MASK; +} + +static inline unsigned int pd_header_cnt_le(__le16 header) +{ + return pd_header_cnt(le16_to_cpu(header)); +} + +static inline unsigned int pd_header_type(uint16_t header) +{ + return (header >> PD_HEADER_TYPE_SHIFT) & PD_HEADER_TYPE_MASK; +} + +static inline unsigned int pd_header_type_le(__le16 header) +{ + return pd_header_type(le16_to_cpu(header)); +} + +#define PD_MAX_PAYLOAD 7 + +struct pd_message { + uint8_t frametype; + uint16_t header; + uint32_t payload[PD_MAX_PAYLOAD]; +} __packed; + +enum pd_pdo_type { + PDO_TYPE_FIXED = 0, + PDO_TYPE_BATT = 1, + PDO_TYPE_VAR = 2, +}; + + +#define PDO_TYPE_SHIFT 30 +#define PDO_TYPE_MASK 0x3 + +#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) + +#define PDO_VOLT_MASK 0x3ff +#define PDO_CURR_MASK 0x3ff +#define PDO_PWR_MASK 0x3ff + +#define PDO_FIXED_DUAL_ROLE BIT(29) /* Power role swap supported */ +#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported (Source) */ +#define PDO_FIXED_HIGHER_CAP BIT(28) /* Requires more than vSafe5V (Sink) */ +#define PDO_FIXED_EXTPOWER BIT(27) /* Externally powered */ +#define PDO_FIXED_USB_COMM BIT(26) /* USB communications capable */ +#define PDO_FIXED_DATA_SWAP BIT(25) /* Data role swap supported */ +#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) +#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) + +#define PDO_FIXED(mv, ma, flags) \ + (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ + PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) + +#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) +#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) +#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) + +#define PDO_BATT(min_mv, max_mv, max_mw) \ + (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ + PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) + +#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) +#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) +#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) + +#define PDO_VAR(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ + PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) + +static inline enum pd_pdo_type pdo_type(uint32_t pdo) +{ + return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK; +} + +static inline unsigned int pdo_fixed_voltage(uint32_t pdo) +{ + return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50; +} + +static inline unsigned int pdo_min_voltage(uint32_t pdo) +{ + return ((pdo >> PDO_VAR_MIN_VOLT_SHIFT) & PDO_VOLT_MASK) * 50; +} + +static inline unsigned int pdo_max_voltage(uint32_t pdo) +{ + return ((pdo >> PDO_VAR_MAX_VOLT_SHIFT) & PDO_VOLT_MASK) * 50; +} + +static inline unsigned int pdo_max_current(uint32_t pdo) +{ + return ((pdo >> PDO_VAR_MAX_CURR_SHIFT) & PDO_CURR_MASK) * 10; +} + +static inline unsigned int pdo_max_power(uint32_t pdo) +{ + return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250; +} + +/* RDO: Request Data Object */ +#define RDO_OBJ_POS_SHIFT 28 +#define RDO_OBJ_POS_MASK 0x7 +#define RDO_GIVE_BACK BIT(27) /* Supports reduced operating current */ +#define RDO_CAP_MISMATCH BIT(26) /* Not satisfied by source caps */ +#define RDO_USB_COMM BIT(25) /* USB communications capable */ +#define RDO_NO_SUSPEND BIT(24) /* USB Suspend not supported */ + +#define RDO_PWR_MASK 0x3ff +#define RDO_CURR_MASK 0x3ff + +#define RDO_FIXED_OP_CURR_SHIFT 10 +#define RDO_FIXED_MAX_CURR_SHIFT 0 + +#define RDO_OBJ(idx) (((idx) & RDO_OBJ_POS_MASK) << RDO_OBJ_POS_SHIFT) + +#define PDO_FIXED_OP_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_OP_CURR_SHIFT) +#define PDO_FIXED_MAX_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_MAX_CURR_SHIFT) + +#define RDO_FIXED(idx, op_ma, max_ma, flags) \ + (RDO_OBJ(idx) | (flags) | \ + PDO_FIXED_OP_CURR(op_ma) | PDO_FIXED_MAX_CURR(max_ma)) + +#define RDO_BATT_OP_PWR_SHIFT 10 /* 250mW units */ +#define RDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT) +#define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT) + +#define RDO_BATT(idx, op_mw, max_mw, flags) \ + (RDO_OBJ(idx) | (flags) | \ + RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw)) + +static inline unsigned int rdo_index(u32 rdo) +{ + return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK; +} + +static inline unsigned int rdo_op_current(u32 rdo) +{ + return ((rdo >> RDO_FIXED_OP_CURR_SHIFT) & RDO_CURR_MASK) * 10; +} + +static inline unsigned int rdo_max_current(u32 rdo) +{ + return ((rdo >> RDO_FIXED_MAX_CURR_SHIFT) & + RDO_CURR_MASK) * 10; +} + +static inline unsigned int rdo_op_power(u32 rdo) +{ + return ((rdo >> RDO_BATT_OP_PWR_SHIFT) & RDO_PWR_MASK) * 250; +} + +static inline unsigned int rdo_max_power(u32 rdo) +{ + return ((rdo >> RDO_BATT_MAX_PWR_SHIFT) & RDO_PWR_MASK) * 250; +} + +#define TCPC_LOG_BUFFER_SIZE 1024 + +struct tcpc_port; + +typedef void (*ss_mux_sel)(enum typec_cc_polarity pol); +typedef int (*ext_pd_switch_setup)(struct tcpc_port *port_p); + +enum tcpc_port_type { + TYPEC_PORT_DFP, + TYPEC_PORT_UFP, + TYPEC_PORT_DRP, +}; + +struct tcpc_port_config { + uint8_t i2c_bus; + uint8_t addr; + enum tcpc_port_type port_type; + uint32_t max_snk_mv; + uint32_t max_snk_ma; + uint32_t max_snk_mw; + uint32_t op_snk_mv; + bool disable_pd; + ext_pd_switch_setup switch_setup_func; +}; + +struct tcpc_port { + struct tcpc_port_config cfg; + struct udevice *i2c_dev; + ss_mux_sel ss_sel_func; + enum pd_sink_state pd_state; + uint32_t tx_msg_id; + uint32_t log_size; + char logbuffer[TCPC_LOG_BUFFER_SIZE]; + char *log_p; + char *log_print; +}; + +int tcpc_set_cc_to_source(struct tcpc_port *port); +int tcpc_set_cc_to_sink(struct tcpc_port *port); +int tcpc_set_plug_orientation(struct tcpc_port *port, enum typec_cc_polarity polarity); +int tcpc_get_cc_status(struct tcpc_port *port, enum typec_cc_polarity *polarity, enum typec_cc_state *state); +int tcpc_clear_alert(struct tcpc_port *port, uint16_t clear_mask); +int tcpc_send_command(struct tcpc_port *port, uint8_t command); +int tcpc_polling_reg(struct tcpc_port *port, uint8_t reg, + uint8_t reg_width, uint16_t mask, uint16_t value, ulong timeout_ms); +int tcpc_setup_dfp_mode(struct tcpc_port *port); +int tcpc_setup_ufp_mode(struct tcpc_port *port); +int tcpc_disable_src_vbus(struct tcpc_port *port); +int tcpc_init(struct tcpc_port *port, struct tcpc_port_config config, ss_mux_sel ss_sel_func); +bool tcpc_pd_sink_check_charging(struct tcpc_port *port); +void tcpc_print_log(struct tcpc_port *port); + +#ifdef CONFIG_SPL_BUILD +int tcpc_setup_ufp_mode(struct tcpc_port *port) +{ + return 0; +} +int tcpc_setup_dfp_mode(struct tcpc_port *port) +{ + return 0; +} + +int tcpc_disable_src_vbus(struct tcpc_port *port) +{ + return 0; +} +#endif +#endif /* __TCPCI_H */ diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 6e8296293b8..13ef101e7fb 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-21 NXP * Copyright 2020 Stephen Carlson */ @@ -793,13 +793,16 @@ static int do_vdd_override(struct cmd_tbl *cmdtp, char *const argv[]) { ulong override; + int ret = 0; if (argc < 2) return CMD_RET_USAGE; - if (!strict_strtoul(argv[1], 10, &override)) - adjust_vdd(override); /* the value is checked by callee */ - else + if (!strict_strtoul(argv[1], 10, &override)) { + ret = adjust_vdd(override); + if (ret < 0) + return CMD_RET_FAILURE; + } else return CMD_RET_USAGE; return 0; } diff --git a/board/freescale/imx8dxl_evk/Kconfig b/board/freescale/imx8dxl_evk/Kconfig new file mode 100644 index 00000000000..6655e849ac1 --- /dev/null +++ b/board/freescale/imx8dxl_evk/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8DXL_EVK || TARGET_IMX8DXL_DDR3_EVK + +config SYS_BOARD + default "imx8dxl_evk" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8dxl_evk" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8dxl_evk/Makefile b/board/freescale/imx8dxl_evk/Makefile new file mode 100644 index 00000000000..f031c5fb500 --- /dev/null +++ b/board/freescale/imx8dxl_evk/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2020 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8dxl_evk.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8dxl_evk/imx8dxl_evk.c b/board/freescale/imx8dxl_evk/imx8dxl_evk.c new file mode 100644 index 00000000000..6601b493410 --- /dev/null +++ b/board/freescale/imx8dxl_evk/imx8dxl_evk.c @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPMI_NAND_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \ + | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_NAND_MXS +static iomux_cfg_t gpmi_nand_pads[] = { + SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + + SC_P_USDHC1_RESET_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_WP | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + +}; + +static void setup_iomux_gpmi_nand(void) +{ + imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads)); +} + +static void imx8dxl_gpmi_nand_initialize(void) +{ + int ret; + + ret = sc_pm_set_resource_power_mode(-1, SC_R_NAND, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return; + + init_clk_gpmi_nand(); + setup_iomux_gpmi_nand(); +} +#endif +#endif + + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_NAND_MXS + imx8dxl_gpmi_nand_initialize(); +#endif +#endif + return 0; +} + +#if CONFIG_IS_ENABLED(DM_GPIO) +static void board_gpio_init(void) +{ +#if defined(CONFIG_DM_VIDEO) + int ret; + struct gpio_desc desc; + + /* M40_DEBUG_UART_SEL */ + ret = dm_gpio_lookup_name("gpio@20_3", &desc); + if (ret) { + printf("%s lookup gpio@20_3 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "M40_DEBUG_UART_SEL"); + if (ret) { + printf("%s request M40_DEBUG_UART_SEL failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); + + /* SPI0_SEL */ + ret = dm_gpio_lookup_name("gpio@20_8", &desc); + if (ret) { + printf("%s lookup gpio@20_8 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "SPI0_SEL"); + if (ret) { + printf("%s request SPI0_SEL failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); + + /* UART1_SEL */ + ret = dm_gpio_lookup_name("gpio@20_6", &desc); + if (ret) { + printf("%s lookup gpio@20_6 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "UART1_SEL"); + if (ret) { + printf("%s request UART1_SEL failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); + + /* MUX3_EN */ + ret = dm_gpio_lookup_name("gpio@21_8", &desc); + if (ret) { + printf("%s lookup gpio@21_8 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "MUX3_EN"); + if (ret) { + printf("%s request MUX3_EN failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); + + /* SPI3_CS0_SEL */ + ret = dm_gpio_lookup_name("gpio@20_4", &desc); + if (ret) { + printf("%s lookup gpio@20_4 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "SPI3_CS0_SEL"); + if (ret) { + printf("%s request SPI3_CS0_SEL failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); + + /* SPI3_SEL */ + ret = dm_gpio_lookup_name("gpio@20_7", &desc); + if (ret) { + printf("%s lookup gpio@20_7 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "SPI3_SEL"); + if (ret) { + printf("%s request SPI3_SEL failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); + + /* BL_CTR */ + ret = dm_gpio_lookup_name("gpio@20_5", &desc); + if (ret) { + printf("%s lookup gpio@20_5 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "BL_CTR"); + if (ret) { + printf("%s request BL_CTR failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +#endif +} +#else +static inline void board_gpio_init(void) {} +#endif + +int checkboard(void) +{ + puts("Board: iMX8DXL EVK\n"); + + print_bootinfo(); + + return 0; +} + +#ifdef CONFIG_DWC_ETH_QOS +static int setup_eqos(void) +{ + sc_err_t err; + + /* set GPR14:12 to b'001: RGMII mode */ + err = sc_misc_set_control(-1, SC_R_ENET_1, SC_C_INTF_SEL, 0x1); + if (err != SC_ERR_NONE) + printf("SC_R_ENET_1 INTF_SEL failed! (error = %d)\n", err); + + /* enable GPR11: CLK_GEN_EN */ + err = sc_misc_set_control(-1, SC_R_ENET_1, SC_C_CLK_GEN_EN, 1); + if (err != SC_ERR_NONE) + printf("SC_R_ENET_1 CLK_GEN_EN failed! (error = %d)\n", err); + + return 0; +} +#endif + +int board_init(void) +{ + board_gpio_init(); +#ifdef CONFIG_DWC_ETH_QOS + /* clock, phy interface mode */ + setup_eqos(); +#endif + +#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO + { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + const char *power_on_devices[] = { + "dma_lpuart0", + }; + + imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_late_init(void) +{ + char *fdt_file; + bool __maybe_unused m4_booted; + + build_info(); + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "EVK"); + env_set("board_rev", "iMX8DXL"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + fdt_file = env_get("fdt_file"); + m4_booted = m4_parts_booted(); + + if (fdt_file && !strcmp(fdt_file, "undefined")) { +#if defined(CONFIG_TARGET_IMX8DXL_DDR3_EVK) + env_set("fdt_file", "imx8dxl-ddr3-evk.dtb"); +#else + if (m4_booted) + env_set("fdt_file", "imx8dxl-evk-rpmsg.dtb"); + else + env_set("fdt_file", "imx8dxl-evk.dtb"); +#endif + } + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} diff --git a/board/freescale/imx8dxl_evk/imximage.cfg b/board/freescale/imx8dxl_evk/imximage.cfg new file mode 100644 index 00000000000..e5f2a9e817f --- /dev/null +++ b/board/freescale/imx8dxl_evk/imximage.cfg @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8DXL */ +SOC_TYPE IMX8DXL +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8dxl-evk-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8dxl_evk/spl.c b/board/freescale/imx8dxl_evk/spl.c new file mode 100644 index 00000000000..812d4a13ddf --- /dev/null +++ b/board/freescale/imx8dxl_evk/spl.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: +#ifdef CONFIG_TARGET_IMX8DXL_DDR3_VAL + return BOOT_DEVICE_MMC1; +#else + return BOOT_DEVICE_MMC2_2; +#endif + case FLEXSPI_BOOT: + return BOOT_DEVICE_SPI; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ + board_quiesce_devices(); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8dxl_evk/uboot-container.cfg b/board/freescale/imx8dxl_evk/uboot-container.cfg new file mode 100644 index 00000000000..9ef26331c13 --- /dev/null +++ b/board/freescale/imx8dxl_evk/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8DXL +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/board/freescale/imx8dxl_phantom_mek/Kconfig b/board/freescale/imx8dxl_phantom_mek/Kconfig new file mode 100644 index 00000000000..33ff367bc5a --- /dev/null +++ b/board/freescale/imx8dxl_phantom_mek/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8DXL_PHANTOM_MEK + +config SYS_BOARD + default "imx8dxl_phantom_mek" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8dxl_phantom_mek" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8dxl_phantom_mek/Makefile b/board/freescale/imx8dxl_phantom_mek/Makefile new file mode 100644 index 00000000000..a2684eb555c --- /dev/null +++ b/board/freescale/imx8dxl_phantom_mek/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2019 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8dxl_phantom_mek.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8dxl_phantom_mek/imx8dxl_phantom_mek.c b/board/freescale/imx8dxl_phantom_mek/imx8dxl_phantom_mek.c new file mode 100644 index 00000000000..341cf44eadd --- /dev/null +++ b/board/freescale/imx8dxl_phantom_mek/imx8dxl_phantom_mek.c @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + return 0; +} + +#if CONFIG_IS_ENABLED(DM_GPIO) +static void board_gpio_init(void) +{ +} +#else +static inline void board_gpio_init(void) {} +#endif + +int checkboard(void) +{ + puts("Board: iMX8DXL Phantom MEK\n"); + + print_bootinfo(); + + return 0; +} + +#ifdef CONFIG_USB + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 0) { + if (init == USB_INIT_DEVICE) { +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB) + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + printf("conn_usb0 Power up failed! (error = %d)\n", ret); + + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + printf("conn_usb0_phy Power up failed! (error = %d)\n", ret); +#endif + } + } + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 0) { + if (init == USB_INIT_DEVICE) { +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB) + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_OFF); + if (ret != SC_ERR_NONE) + printf("conn_usb0 Power down failed! (error = %d)\n", ret); + + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_OFF); + if (ret != SC_ERR_NONE) + printf("conn_usb0_phy Power down failed! (error = %d)\n", ret); +#endif + } + } + return ret; +} +#endif + +int board_init(void) +{ + board_gpio_init(); + +#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO + { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + const char *power_on_devices[] = { + "dma_lpuart0", + + /* HIFI DSP boot */ + "audio_sai0", + "audio_ocram", + }; + + imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_late_init(void) +{ + char *fdt_file; + bool m4_booted; + + build_info(); + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "MEK"); + env_set("board_rev", "iMX8DXL Phantom"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + fdt_file = env_get("fdt_file"); + m4_booted = m4_parts_booted(); + + if (fdt_file && !strcmp(fdt_file, "undefined")) { + if (m4_booted) + env_set("fdt_file", "imx8dxl-phantom-mek-rpmsg.dtb"); + else + env_set("fdt_file", "imx8dxl-phantom-mek.dtb"); + } + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} diff --git a/board/freescale/imx8dxl_phantom_mek/imximage.cfg b/board/freescale/imx8dxl_phantom_mek/imximage.cfg new file mode 100644 index 00000000000..c203eace229 --- /dev/null +++ b/board/freescale/imx8dxl_phantom_mek/imximage.cfg @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8dxl_phantom_mek/spl.c b/board/freescale/imx8dxl_phantom_mek/spl.c new file mode 100644 index 00000000000..7b78452c09b --- /dev/null +++ b/board/freescale/imx8dxl_phantom_mek/spl.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + int node, ret; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu"); + + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &dev); + if (ret) { + return; + } + device_probe(dev); + + uclass_find_first_device(UCLASS_MISC, &dev); + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ + board_quiesce_devices(); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8dxl_phantom_mek/uboot-container.cfg b/board/freescale/imx8dxl_phantom_mek/uboot-container.cfg new file mode 100644 index 00000000000..81658118185 --- /dev/null +++ b/board/freescale/imx8dxl_phantom_mek/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QX +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig index 299691a6194..ae097ee6c5b 100644 --- a/board/freescale/imx8mm_evk/Kconfig +++ b/board/freescale/imx8mm_evk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8MM_EVK +if TARGET_IMX8MM_EVK || TARGET_IMX8MM_DDR4_EVK || TARGET_IMX8MM_EVK_QCA config SYS_BOARD default "imx8mm_evk" @@ -9,4 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mm_evk" +config IMX8M_1G_MEMORY + bool "imx8m 1GB memory size" + +source "board/freescale/common/Kconfig" + endif diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile index 1db7b62cafc..b3f1c185a3f 100644 --- a/board/freescale/imx8mm_evk/Makefile +++ b/board/freescale/imx8mm_evk/Makefile @@ -8,5 +8,10 @@ obj-y += imx8mm_evk.o ifdef CONFIG_SPL_BUILD obj-y += spl.o +ifdef CONFIG_IMX8M_4G_LPDDR4 +obj-y += lpddr4_timing_4g.o +else obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o +endif endif diff --git a/board/freescale/imx8mm_evk/ddr4_timing.c b/board/freescale/imx8mm_evk/ddr4_timing.c new file mode 100644 index 00000000000..2f80b9832b2 --- /dev/null +++ b/board/freescale/imx8mm_evk/ddr4_timing.c @@ -0,0 +1,1265 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0xaa }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x9200d2 }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340105 }, + { 0x3d4000e0, 0x180200 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x814 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x5050d08 }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1409010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x40005e }, + { 0x3d4020dc, 0x40105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x14 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x4030205 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x3030d04 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1005010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3858204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x504 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x1205f, 0x2fd }, + { 0x1215f, 0x2fd }, + { 0x1305f, 0x2fd }, + { 0x1315f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x11205f, 0x2fd }, + { 0x11215f, 0x2fd }, + { 0x11305f, 0x2fd }, + { 0x11315f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xa }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x1204d, 0x1a }, + { 0x1214d, 0x1a }, + { 0x1304d, 0x1a }, + { 0x1314d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x11204d, 0x1a }, + { 0x11214d, 0x1a }, + { 0x11304d, 0x1a }, + { 0x11314d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x12049, 0xe38 }, + { 0x12149, 0xe38 }, + { 0x13049, 0xe38 }, + { 0x13149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x112049, 0xe38 }, + { 0x112149, 0xe38 }, + { 0x113049, 0xe38 }, + { 0x113149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x5 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x12043, 0x5b1 }, + { 0x12143, 0x5b1 }, + { 0x13043, 0x5b1 }, + { 0x13143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x112043, 0x5b1 }, + { 0x112143, 0x5b1 }, + { 0x113043, 0x5b1 }, + { 0x113143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x814 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x4 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x14 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x814 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xf }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x630 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x630 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x630 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x630 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x630 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x630 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x630 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x630 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x630 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xa }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x2 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x7 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x10 }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x8140 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x10 }, + { 0x900a8, 0x8138 }, + { 0x900a9, 0x10c }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7c8 }, + { 0x900ac, 0x101 }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x0 }, + { 0x900af, 0x8 }, + { 0x900b0, 0x8 }, + { 0x900b1, 0x448 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0xf }, + { 0x900b4, 0x7c0 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x47 }, + { 0x900b7, 0x630 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x8 }, + { 0x900ba, 0x618 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0xe0 }, + { 0x900be, 0x109 }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x7c8 }, + { 0x900c1, 0x109 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x8140 }, + { 0x900c4, 0x10c }, + { 0x900c5, 0x0 }, + { 0x900c6, 0x1 }, + { 0x900c7, 0x8 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x8 }, + { 0x900cb, 0x8 }, + { 0x900cc, 0x7c8 }, + { 0x900cd, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2c }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1066, }, +}; diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c index ab55135a972..eaa2c6b7f14 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.c +++ b/board/freescale/imx8mm_evk/imx8mm_evk.c @@ -2,20 +2,93 @@ /* * Copyright 2018 NXP */ - #include #include #include #include #include #include - +#include +#include +#include #include #include +#include +#include +#include #include +#include "../common/tcpc.h" +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_NAND_MXS +#ifdef CONFIG_SPL_BUILD +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; +#endif + +static void setup_gpmi_nand(void) +{ +#ifdef CONFIG_SPL_BUILD + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); +#endif + + init_nand_clk(); +} +#endif + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(1); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + + return 0; +} + #if IS_ENABLED(CONFIG_FEC_MXC) static int setup_fec(void) { @@ -30,6 +103,10 @@ static int setup_fec(void) int board_phy_config(struct phy_device *phydev) { + if (phydev->drv->config) + phydev->drv->config(phydev); + +#ifndef CONFIG_DM_ETH /* enable rgmii rxc skew and phy mode select to RGMII copper */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); @@ -38,31 +115,232 @@ int board_phy_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif - if (phydev->drv->config) - phydev->drv->config(phydev); return 0; } #endif -int board_init(void) +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) { - if (IS_ENABLED(CONFIG_FEC_MXC)) - setup_fec(); + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } return 0; } -int board_mmc_get_env_dev(int devno) +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(1, 0x72); + } else if (port == &port2) { + debug("Setup pd switch on port 2\n"); + return setup_pd_switch(1, 0x73); + } else + return -EINVAL; +} + +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x52, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 9000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +static int setup_typec(void) +{ + int ret; + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } else if (tcpc_pd_sink_check_charging(&port2)) { + /* Disable PD for USB1, since USB2 has priority */ + port1_config.disable_pd = true; + printf("Power supply on USB2\n"); + } + + debug("tcpc_init port 1\n"); + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } else { + if (!port1_config.disable_pd) + printf("Power supply on USB1\n"); + return ret; + } + + return ret; +} + +int board_usb_init(int index, enum usb_init_type init) { - return devno; + int ret = 0; + struct tcpc_port *port_ptr; + + debug("board_usb_init %d, type %d\n", index, init); + + if (index == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + imx8m_usb_power(index, true); + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(port_ptr); + else + tcpc_setup_ufp_mode(port_ptr); + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + debug("board_usb_cleanup %d, type %d\n", index, init); + + if (init == USB_INIT_HOST) { + if (index == 0) + ret = tcpc_disable_src_vbus(&port1); + else + ret = tcpc_disable_src_vbus(&port2); + } + + imx8m_usb_power(index, false); + return ret; +} + +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + struct tcpc_port *port_ptr; + + if (dev_seq(dev) == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + tcpc_setup_ufp_mode(port_ptr); + + ret = tcpc_get_cc_status(port_ptr, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} + +#endif + +#define DISPMIX 9 +#define MIPI 10 + +int board_init(void) +{ + struct arm_smccc_res res; + +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + DISPMIX, true, 0, 0, 0, 0, &res); + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + MIPI, true, 0, 0, 0, 0, &res); + + return 0; } int board_late_init(void) { +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "EVK"); env_set("board_rev", "iMX8MM"); #endif return 0; } + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /* TODO */ +} +#endif /* CONFIG_ANDROID_RECOVERY */ +#endif /* CONFIG_FSL_FASTBOOT */ diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c index 8e48b9d81b7..3495b9c931e 100644 --- a/board/freescale/imx8mm_evk/lpddr4_timing.c +++ b/board/freescale/imx8mm_evk/lpddr4_timing.c @@ -1,129 +1,163 @@ -// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool */ #include -#include #include -#include -struct dram_cfg_param lpddr4_ddrc_cfg[] = { - /* Start to config, default 3200mbps */ - { DDRC_DBG1(0), 0x00000001 }, - { DDRC_PWRCTL(0), 0x00000001 }, - { DDRC_MSTR(0), 0xa1080020 }, - { DDRC_RFSHTMG(0), 0x005b00d2 }, - { DDRC_INIT0(0), 0xC003061B }, - { DDRC_INIT1(0), 0x009D0000 }, - { DDRC_INIT3(0), 0x00D4002D }, - { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, - { DDRC_INIT6(0), 0x0066004a }, - { DDRC_INIT7(0), 0x0006004a }, - - { DDRC_DRAMTMG0(0), 0x1A201B22 }, - { DDRC_DRAMTMG1(0), 0x00060633 }, - { DDRC_DRAMTMG3(0), 0x00C0C000 }, - { DDRC_DRAMTMG4(0), 0x0F04080F }, - { DDRC_DRAMTMG5(0), 0x02040C0C }, - { DDRC_DRAMTMG6(0), 0x01010007 }, - { DDRC_DRAMTMG7(0), 0x00000401 }, - { DDRC_DRAMTMG12(0), 0x00020600 }, - { DDRC_DRAMTMG13(0), 0x0C100002 }, - { DDRC_DRAMTMG14(0), 0x000000E6 }, - { DDRC_DRAMTMG17(0), 0x00A00050 }, - - { DDRC_ZQCTL0(0), 0x03200018 }, - { DDRC_ZQCTL1(0), 0x028061A8 }, - { DDRC_ZQCTL2(0), 0x00000000 }, - - { DDRC_DFITMG0(0), 0x0497820A }, - { DDRC_DFITMG2(0), 0x0000170A }, - { DDRC_DRAMTMG2(0), 0x070E171a }, - { DDRC_DBICTL(0), 0x00000001 }, - - { DDRC_DFITMG1(0), 0x00080303 }, - { DDRC_DFIUPD0(0), 0xE0400018 }, - { DDRC_DFIUPD1(0), 0x00DF00E4 }, - { DDRC_DFIUPD2(0), 0x80000000 }, - { DDRC_DFIMISC(0), 0x00000011 }, - - { DDRC_DFIPHYMSTR(0), 0x00000000 }, - { DDRC_RANKCTL(0), 0x00000c99 }, - - /* address mapping */ - { DDRC_ADDRMAP0(0), 0x0000001f }, - { DDRC_ADDRMAP1(0), 0x00080808 }, - { DDRC_ADDRMAP2(0), 0x00000000 }, - { DDRC_ADDRMAP3(0), 0x00000000 }, - { DDRC_ADDRMAP4(0), 0x00001f1f }, - { DDRC_ADDRMAP5(0), 0x07070707 }, - { DDRC_ADDRMAP6(0), 0x07070707 }, - { DDRC_ADDRMAP7(0), 0x00000f0f }, +struct dram_cfg_param ddr_ddrc_cfg[] = { + /* Initialize DDRC registers */ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa1080020 }, + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x16e3600 }, + { 0x3d400064, 0x5b00d2 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x1f }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, /* performance setting */ - { DDRC_SCHED(0), 0x29001701 }, - { DDRC_SCHED1(0), 0x0000002c }, - { DDRC_PERFHPR1(0), 0x04000030 }, - { DDRC_PERFLPR1(0), 0x900093e7 }, - { DDRC_PERFWR1(0), 0x20005574 }, - { DDRC_PCCFG(0), 0x00000111 }, - { DDRC_PCFGW_0(0), 0x000072ff }, - { DDRC_PCFGQOS0_0(0), 0x02100e07 }, - { DDRC_PCFGQOS1_0(0), 0x00620096 }, - { DDRC_PCFGWQOS0_0(0), 0x01100e07 }, - { DDRC_PCFGWQOS1_0(0), 0x00c8012c }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, - /* frequency P1&P2 */ - /* Frequency 1: 400mbps */ - { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, - { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, - { DDRC_FREQ1_DRAMTMG2(0), 0x0203090c }, - { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, - { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, - { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, - { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, - { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, - { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, - { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, - { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, - { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, - { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, - { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, - { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, - { DDRC_FREQ1_INIT3(0), 0x00840000 }, - { DDRC_FREQ1_INIT4(0), 0x00310000 }, - { DDRC_FREQ1_INIT6(0), 0x0066004a }, - { DDRC_FREQ1_INIT7(0), 0x0006004a }, + /* P1: 400mts */ + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, - /* Frequency 2: 100mbps */ - { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, - { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, - { DDRC_FREQ2_DRAMTMG2(0), 0x0203090c }, - { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, - { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, - { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, - { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, - { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, - { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, - { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, - { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, - { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, - { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, - { DDRC_FREQ2_RFSHTMG(0), 0x0003800c }, - { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, - { DDRC_FREQ2_INIT3(0), 0x00840000 }, - { DDRC_FREQ2_INIT4(0), 0x00310008 }, - { DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, - { DDRC_FREQ2_INIT6(0), 0x0066004a }, - { DDRC_FREQ2_INIT7(0), 0x0006004a }, + /* p2: 100mts */ + { 0x3d403020, 0x21 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, - /* boot start point */ - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 + /* default boot point */ + { 0x3d400028, 0x0 }, }; /* PHY Initialize Configuration */ -struct dram_cfg_param lpddr4_ddrphy_cfg[] = { +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -132,7 +166,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x1215f, 0x1ff }, { 0x1305f, 0x1ff }, { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, { 0x11015f, 0x1ff }, { 0x11105f, 0x1ff }, @@ -141,7 +174,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x11215f, 0x1ff }, { 0x11305f, 0x1ff }, { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, { 0x21015f, 0x1ff }, { 0x21105f, 0x1ff }, @@ -150,7 +182,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x21215f, 0x1ff }, { 0x21305f, 0x1ff }, { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, { 0x1055, 0x1ff }, { 0x2055, 0x1ff }, @@ -161,32 +192,24 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, { 0x12002e, 0x2 }, { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - - { 0x20024, 0xab }, + { 0x20024, 0x1ab }, { 0x2003a, 0x0 }, - - { 0x120024, 0xab }, + { 0x120024, 0x1ab }, { 0x2003a, 0x0 }, - - { 0x220024, 0xab }, + { 0x220024, 0x1ab }, { 0x2003a, 0x0 }, - { 0x20056, 0x3 }, { 0x120056, 0xa }, { 0x220056, 0xa }, - { 0x1004d, 0xe00 }, { 0x1014d, 0xe00 }, { 0x1104d, 0xe00 }, @@ -195,7 +218,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x1214d, 0xe00 }, { 0x1304d, 0xe00 }, { 0x1314d, 0xe00 }, - { 0x11004d, 0xe00 }, { 0x11014d, 0xe00 }, { 0x11104d, 0xe00 }, @@ -204,7 +226,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x11214d, 0xe00 }, { 0x11304d, 0xe00 }, { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, { 0x21014d, 0xe00 }, { 0x21104d, 0xe00 }, @@ -213,34 +234,30 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x21214d, 0xe00 }, { 0x21304d, 0xe00 }, { 0x21314d, 0xe00 }, - - { 0x10049, 0xfbe }, - { 0x10149, 0xfbe }, - { 0x11049, 0xfbe }, - { 0x11149, 0xfbe }, - { 0x12049, 0xfbe }, - { 0x12149, 0xfbe }, - { 0x13049, 0xfbe }, - { 0x13149, 0xfbe }, - - { 0x110049, 0xfbe }, - { 0x110149, 0xfbe }, - { 0x111049, 0xfbe }, - { 0x111149, 0xfbe }, - { 0x112049, 0xfbe }, - { 0x112149, 0xfbe }, - { 0x113049, 0xfbe }, - { 0x113149, 0xfbe }, - - { 0x210049, 0xfbe }, - { 0x210149, 0xfbe }, - { 0x211049, 0xfbe }, - { 0x211149, 0xfbe }, - { 0x212049, 0xfbe }, - { 0x212149, 0xfbe }, - { 0x213049, 0xfbe }, - { 0x213149, 0xfbe }, - + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, { 0x43, 0x63 }, { 0x1043, 0x63 }, { 0x2043, 0x63 }, @@ -251,7 +268,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x7043, 0x63 }, { 0x8043, 0x63 }, { 0x9043, 0x63 }, - { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, @@ -259,8 +275,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, - - { 0x200b2, 0x1d4 }, + { 0x200b2, 0xdc }, { 0x10043, 0x5a1 }, { 0x10143, 0x5a1 }, { 0x11043, 0x5a1 }, @@ -269,7 +284,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x12143, 0x5a1 }, { 0x13043, 0x5a1 }, { 0x13143, 0x5a1 }, - { 0x1200b2, 0xdc }, { 0x110043, 0x5a1 }, { 0x110143, 0x5a1 }, @@ -279,7 +293,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x112143, 0x5a1 }, { 0x113043, 0x5a1 }, { 0x113143, 0x5a1 }, - { 0x2200b2, 0xdc }, { 0x210043, 0x5a1 }, { 0x210143, 0x5a1 }, @@ -289,15 +302,12 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x212143, 0x5a1 }, { 0x213043, 0x5a1 }, { 0x213143, 0x5a1 }, - { 0x200fa, 0x1 }, { 0x1200fa, 0x1 }, { 0x2200fa, 0x1 }, - { 0x20019, 0x1 }, { 0x120019, 0x1 }, { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, { 0x200f1, 0x0 }, { 0x200f2, 0x4444 }, @@ -306,21 +316,20 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x200f5, 0x0 }, { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, - { 0x20025, 0x0 }, - { 0x2002d, LPDDR4_PHY_DMIPinPresent }, - { 0x12002d, LPDDR4_PHY_DMIPinPresent }, - { 0x22002d, LPDDR4_PHY_DMIPinPresent }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, { 0x200c7, 0x21 }, - { 0x200ca, 0x24 }, { 0x1200c7, 0x21 }, - { 0x1200ca, 0x24 }, { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, { 0x2200ca, 0x24 }, }; /* ddr phy trained csr */ -struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { { 0x200b2, 0x0 }, { 0x1200b2, 0x0 }, { 0x2200b2, 0x0 }, @@ -1041,309 +1050,167 @@ struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = { { 0x13730, 0x0 }, { 0x13830, 0x0 }, }; - /* P0 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp0_cfg[] = { +struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x131f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, + { 0x54012, 0x110 }, { 0x54019, 0x2dd4 }, - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d08 }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, - { 0x54022, 0x4d08 }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, - { 0x5402c, LPDDR4_CS }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, + { 0x5402c, 0x1 }, { 0x54032, 0xd400 }, - { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54033, 0x312d }, { 0x54034, 0x6600 }, - { 0x54035, 0x84d }, + { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, - { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54039, 0x312d }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x84d }, + { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; + /* P1 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp1_cfg[] = { +struct dram_cfg_param ddr_fsp1_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x101 }, { 0x54003, 0x190 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },/* PHY Ron/Rtt */ - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, + { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d08 }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, - { 0x54022, 0x4d08 }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, - { 0x5402c, LPDDR4_CS }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, + { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54033, 0x3100 }, { 0x54034, 0x6600 }, - { 0x54035, 0x84d }, + { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54039, 0x3100 }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x84d }, + { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; -/* P1 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp2_cfg[] = { + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x102 }, { 0x54003, 0x64 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, + { 0x54012, 0x110 }, { 0x54019, 0x84 }, - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d08 }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, - { 0x54022, 0x4d08 }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, - { 0x5402c, LPDDR4_CS }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, + { 0x5402c, 0x1 }, { 0x54032, 0x8400 }, - { 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54033, 0x3100 }, { 0x54034, 0x6600 }, - { 0x54035, 0x84d }, + { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) }, + { 0x54039, 0x3100 }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x84d }, + { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; + /* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, - { 0x54011, 0x0 }, - { 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, + { 0x54012, 0x110 }, { 0x54019, 0x2dd4 }, - { 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x5401a, 0x31 }, { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d08 }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, - { 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 }, + { 0x54020, 0x31 }, { 0x54021, 0x4d66 }, - { 0x54022, 0x4d08 }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1/*0x16*/ }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, - { 0x5402c, LPDDR4_CS }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, + { 0x5402c, 0x1 }, { 0x54032, 0xd400 }, - { 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54033, 0x312d }, { 0x54034, 0x6600 }, - { 0x54035, 0x84d }, + { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ }, + { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, - { 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) }, + { 0x54039, 0x312d }, { 0x5403a, 0x6600 }, - { 0x5403b, 0x84d }, + { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* DRAM PHY init engine image */ -struct dram_cfg_param lpddr4_phy_pie[] = { +struct dram_cfg_param ddr_phy_pie[] = { { 0xd0000, 0x0 }, { 0x90000, 0x10 }, { 0x90001, 0x400 }, @@ -1854,6 +1721,10 @@ struct dram_cfg_param lpddr4_phy_pie[] = { { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, @@ -1931,50 +1802,51 @@ struct dram_cfg_param lpddr4_phy_pie[] = { { 0x138b4, 0x1 }, { 0x2003a, 0x2 }, { 0xc0080, 0x2 }, - { 0xd0000, 0x1 }, + { 0xd0000, 0x1 } }; -struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { +struct dram_fsp_msg ddr_dram_fsp_msg[] = { { /* P0 3000mts 1D */ .drate = 3000, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), - }, - { - /* P0 3000mts 2D */ - .drate = 3000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), }, { /* P1 400mts 1D */ .drate = 400, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), }, { - /* P1 100mts 1D */ + /* P2 100mts 1D */ .drate = 100, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), }, }; -/* lpddr4 timing config params on EVK board */ +/* ddr timing config params */ struct dram_timing_info dram_timing = { - .ddrc_cfg = lpddr4_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), - .ddrphy_cfg = lpddr4_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), - .fsp_msg = lpddr4_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), - .ddrphy_trained_csr = lpddr4_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr), - .ddrphy_pie = lpddr4_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, }; diff --git a/board/freescale/imx8mm_evk/lpddr4_timing_4g.c b/board/freescale/imx8mm_evk/lpddr4_timing_4g.c new file mode 100755 index 00000000000..d32ecbf905b --- /dev/null +++ b/board/freescale/imx8mm_evk/lpddr4_timing_4g.c @@ -0,0 +1,1842 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + {0x3d400304,0x1}, + {0x3d400030,0x1}, + {0x3d400000,0xa3080020}, + {0x3d400020,0x223}, + {0x3d400024,0x16e3600}, + {0x3d400064,0x5b00d2}, + {0x3d4000d0,0xc00305ba}, + {0x3d4000d4,0x940000}, + {0x3d4000dc,0xd4002d}, + {0x3d4000e0,0x310000}, + {0x3d4000e8,0x66004d}, + {0x3d4000ec,0x16004d}, + {0x3d400100,0x191e1920}, + {0x3d400104,0x60630}, + {0x3d40010c,0xb0b000}, + {0x3d400110,0xe04080e}, + {0x3d400114,0x2040c0c}, + {0x3d400118,0x1010007}, + {0x3d40011c,0x401}, + {0x3d400130,0x20600}, + {0x3d400134,0xc100002}, + {0x3d400138,0xd8}, + {0x3d400144,0x96004b}, + {0x3d400180,0x2ee0017}, + {0x3d400184,0x2605b8e}, + {0x3d400188,0x0}, + {0x3d400190,0x497820a}, + {0x3d400194,0x80303}, + {0x3d4001b4,0x170a}, + {0x3d4001a0,0xe0400018}, + {0x3d4001a4,0xdf00e4}, + {0x3d4001a8,0x80000000}, + {0x3d4001b0,0x11}, + {0x3d4001c0,0x1}, + {0x3d4001c4,0x0}, + {0x3d4000f4,0xc99}, + {0x3d400108,0x70e1617}, + {0x3d400200,0x17}, + {0x3d40020c,0x0}, + {0x3d400210,0x1f1f}, + {0x3d400204,0x80808}, + {0x3d400214,0x7070707}, + {0x3d400218,0x7070707}, + {0x3d400250,0x29001701}, + {0x3d400254,0x2c}, + {0x3d40025c,0x4000030}, + {0x3d400264,0x900093e7}, + {0x3d40026c,0x2005574}, + {0x3d400400,0x111}, + {0x3d400408,0x72ff}, + {0x3d400494,0x2100e07}, + {0x3d400498,0x620096}, + {0x3d40049c,0x1100e07}, + {0x3d4004a0,0xc8012c}, + {0x3d402020,0x21}, + {0x3d402024,0x30d400}, + {0x3d402050,0x20d040}, + {0x3d402064,0xc001c}, + {0x3d4020dc,0x840000}, + {0x3d4020e0,0x310000}, + {0x3d4020e8,0x66004d}, + {0x3d4020ec,0x16004d}, + {0x3d402100,0xa040305}, + {0x3d402104,0x30407}, + {0x3d402108,0x203060b}, + {0x3d40210c,0x505000}, + {0x3d402110,0x2040202}, + {0x3d402114,0x2030202}, + {0x3d402118,0x1010004}, + {0x3d40211c,0x301}, + {0x3d402130,0x20300}, + {0x3d402134,0xa100002}, + {0x3d402138,0x1d}, + {0x3d402144,0x14000a}, + {0x3d402180,0x640004}, + {0x3d402190,0x3818200}, + {0x3d402194,0x80303}, + {0x3d4021b4,0x100}, + {0x3d403020,0x21}, + {0x3d403024,0xc3500}, + {0x3d403050,0x20d040}, + {0x3d403064,0x30007}, + {0x3d4030dc,0x840000}, + {0x3d4030e0,0x310000}, + {0x3d4030e8,0x66004d}, + {0x3d4030ec,0x16004d}, + {0x3d403100,0xa010102}, + {0x3d403104,0x30404}, + {0x3d403108,0x203060b}, + {0x3d40310c,0x505000}, + {0x3d403110,0x2040202}, + {0x3d403114,0x2030202}, + {0x3d403118,0x1010004}, + {0x3d40311c,0x301}, + {0x3d403130,0x20300}, + {0x3d403134,0xa100002}, + {0x3d403138,0x8}, + {0x3d403144,0x50003}, + {0x3d403180,0x190004}, + {0x3d403190,0x3818200}, + {0x3d403194,0x80303}, + {0x3d4031b4,0x100}, + {0x3d400028,0x0}, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0,0x0}, + {0x100a1,0x1}, + {0x100a2,0x2}, + {0x100a3,0x3}, + {0x100a4,0x4}, + {0x100a5,0x5}, + {0x100a6,0x6}, + {0x100a7,0x7}, + {0x110a0,0x0}, + {0x110a1,0x1}, + {0x110a2,0x3}, + {0x110a3,0x4}, + {0x110a4,0x5}, + {0x110a5,0x2}, + {0x110a6,0x7}, + {0x110a7,0x6}, + {0x120a0,0x0}, + {0x120a1,0x1}, + {0x120a2,0x3}, + {0x120a3,0x2}, + {0x120a4,0x5}, + {0x120a5,0x4}, + {0x120a6,0x7}, + {0x120a7,0x6}, + {0x130a0,0x0}, + {0x130a1,0x1}, + {0x130a2,0x2}, + {0x130a3,0x3}, + {0x130a4,0x4}, + {0x130a5,0x5}, + {0x130a6,0x6}, + {0x130a7,0x7}, + {0x1005f,0x1ff}, + {0x1015f,0x1ff}, + {0x1105f,0x1ff}, + {0x1115f,0x1ff}, + {0x1205f,0x1ff}, + {0x1215f,0x1ff}, + {0x1305f,0x1ff}, + {0x1315f,0x1ff}, + {0x11005f,0x1ff}, + {0x11015f,0x1ff}, + {0x11105f,0x1ff}, + {0x11115f,0x1ff}, + {0x11205f,0x1ff}, + {0x11215f,0x1ff}, + {0x11305f,0x1ff}, + {0x11315f,0x1ff}, + {0x21005f,0x1ff}, + {0x21015f,0x1ff}, + {0x21105f,0x1ff}, + {0x21115f,0x1ff}, + {0x21205f,0x1ff}, + {0x21215f,0x1ff}, + {0x21305f,0x1ff}, + {0x21315f,0x1ff}, + {0x55,0x1ff}, + {0x1055,0x1ff}, + {0x2055,0x1ff}, + {0x3055,0x1ff}, + {0x4055,0x1ff}, + {0x5055,0x1ff}, + {0x6055,0x1ff}, + {0x7055,0x1ff}, + {0x8055,0x1ff}, + {0x9055,0x1ff}, + {0x200c5,0x19}, + {0x1200c5,0x7}, + {0x2200c5,0x7}, + {0x2002e,0x2}, + {0x12002e,0x2}, + {0x22002e,0x2}, + {0x90204,0x0}, + {0x190204,0x0}, + {0x290204,0x0}, + {0x20024,0x1ab}, + {0x2003a,0x0}, + {0x120024,0x1ab}, + {0x2003a,0x0}, + {0x220024,0x1ab}, + {0x2003a,0x0}, + {0x20056,0x3}, + {0x120056,0xa}, + {0x220056,0xa}, + {0x1004d,0xe00}, + {0x1014d,0xe00}, + {0x1104d,0xe00}, + {0x1114d,0xe00}, + {0x1204d,0xe00}, + {0x1214d,0xe00}, + {0x1304d,0xe00}, + {0x1314d,0xe00}, + {0x11004d,0xe00}, + {0x11014d,0xe00}, + {0x11104d,0xe00}, + {0x11114d,0xe00}, + {0x11204d,0xe00}, + {0x11214d,0xe00}, + {0x11304d,0xe00}, + {0x11314d,0xe00}, + {0x21004d,0xe00}, + {0x21014d,0xe00}, + {0x21104d,0xe00}, + {0x21114d,0xe00}, + {0x21204d,0xe00}, + {0x21214d,0xe00}, + {0x21304d,0xe00}, + {0x21314d,0xe00}, + {0x10049,0xeba}, + {0x10149,0xeba}, + {0x11049,0xeba}, + {0x11149,0xeba}, + {0x12049,0xeba}, + {0x12149,0xeba}, + {0x13049,0xeba}, + {0x13149,0xeba}, + {0x110049,0xeba}, + {0x110149,0xeba}, + {0x111049,0xeba}, + {0x111149,0xeba}, + {0x112049,0xeba}, + {0x112149,0xeba}, + {0x113049,0xeba}, + {0x113149,0xeba}, + {0x210049,0xeba}, + {0x210149,0xeba}, + {0x211049,0xeba}, + {0x211149,0xeba}, + {0x212049,0xeba}, + {0x212149,0xeba}, + {0x213049,0xeba}, + {0x213149,0xeba}, + {0x43,0x63}, + {0x1043,0x63}, + {0x2043,0x63}, + {0x3043,0x63}, + {0x4043,0x63}, + {0x5043,0x63}, + {0x6043,0x63}, + {0x7043,0x63}, + {0x8043,0x63}, + {0x9043,0x63}, + {0x20018,0x3}, + {0x20075,0x4}, + {0x20050,0x0}, + {0x20008,0x2ee}, + {0x120008,0x64}, + {0x220008,0x19}, + {0x20088,0x9}, + {0x200b2,0xdc}, + {0x10043,0x5a1}, + {0x10143,0x5a1}, + {0x11043,0x5a1}, + {0x11143,0x5a1}, + {0x12043,0x5a1}, + {0x12143,0x5a1}, + {0x13043,0x5a1}, + {0x13143,0x5a1}, + {0x1200b2,0xdc}, + {0x110043,0x5a1}, + {0x110143,0x5a1}, + {0x111043,0x5a1}, + {0x111143,0x5a1}, + {0x112043,0x5a1}, + {0x112143,0x5a1}, + {0x113043,0x5a1}, + {0x113143,0x5a1}, + {0x2200b2,0xdc}, + {0x210043,0x5a1}, + {0x210143,0x5a1}, + {0x211043,0x5a1}, + {0x211143,0x5a1}, + {0x212043,0x5a1}, + {0x212143,0x5a1}, + {0x213043,0x5a1}, + {0x213143,0x5a1}, + {0x200fa,0x1}, + {0x1200fa,0x1}, + {0x2200fa,0x1}, + {0x20019,0x1}, + {0x120019,0x1}, + {0x220019,0x1}, + {0x200f0,0x660}, + {0x200f1,0x0}, + {0x200f2,0x4444}, + {0x200f3,0x8888}, + {0x200f4,0x5665}, + {0x200f5,0x0}, + {0x200f6,0x0}, + {0x200f7,0xf000}, + {0x20025,0x0}, + {0x2002d,0x0}, + {0x12002d,0x0}, + {0x22002d,0x0}, + {0x200c7,0x21}, + {0x1200c7,0x21}, + {0x2200c7,0x21}, + {0x200ca,0x24}, + {0x1200ca,0x24}, + {0x2200ca,0x24}, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54006,0x11}, + {0x54008,0x131f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x101}, + {0x54003,0x190}, + {0x54004,0x2}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x54012,0x310}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002,0x102}, + {0x54003,0x64}, + {0x54004,0x2}, + {0x54006,0x11}, + {0x54008,0x121f}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x54012,0x310}, + {0x54019,0x84}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x84}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0x8400}, + {0x54033,0x3100}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0x8400}, + {0x54039,0x3100}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + {0xd0000, 0x1}, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003,0xbb8}, + {0x54004,0x2}, + {0x54006,0x11}, + {0x54008,0x61}, + {0x54009,0xc8}, + {0x5400b,0x2}, + {0x5400f,0x100}, + {0x54010,0x1f7f}, + {0x54012,0x310}, + {0x54019,0x2dd4}, + {0x5401a,0x31}, + {0x5401b,0x4d66}, + {0x5401c,0x4d00}, + {0x5401e,0x16}, + {0x5401f,0x2dd4}, + {0x54020,0x31}, + {0x54021,0x4d66}, + {0x54022,0x4d00}, + {0x54024,0x16}, + {0x5402b,0x1000}, + {0x5402c,0x3}, + {0x54032,0xd400}, + {0x54033,0x312d}, + {0x54034,0x6600}, + {0x54035,0x4d}, + {0x54036,0x4d}, + {0x54037,0x1600}, + {0x54038,0xd400}, + {0x54039,0x312d}, + {0x5403a,0x6600}, + {0x5403b,0x4d}, + {0x5403c,0x4d}, + {0x5403d,0x1600}, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000,0x10}, + {0x90001,0x400}, + {0x90002,0x10e}, + {0x90003,0x0}, + {0x90004,0x0}, + {0x90005,0x8}, + {0x90029,0xb}, + {0x9002a,0x480}, + {0x9002b,0x109}, + {0x9002c,0x8}, + {0x9002d,0x448}, + {0x9002e,0x139}, + {0x9002f,0x8}, + {0x90030,0x478}, + {0x90031,0x109}, + {0x90032,0x0}, + {0x90033,0xe8}, + {0x90034,0x109}, + {0x90035,0x2}, + {0x90036,0x10}, + {0x90037,0x139}, + {0x90038,0xf}, + {0x90039,0x7c0}, + {0x9003a,0x139}, + {0x9003b,0x44}, + {0x9003c,0x630}, + {0x9003d,0x159}, + {0x9003e,0x14f}, + {0x9003f,0x630}, + {0x90040,0x159}, + {0x90041,0x47}, + {0x90042,0x630}, + {0x90043,0x149}, + {0x90044,0x4f}, + {0x90045,0x630}, + {0x90046,0x179}, + {0x90047,0x8}, + {0x90048,0xe0}, + {0x90049,0x109}, + {0x9004a,0x0}, + {0x9004b,0x7c8}, + {0x9004c,0x109}, + {0x9004d,0x0}, + {0x9004e,0x1}, + {0x9004f,0x8}, + {0x90050,0x0}, + {0x90051,0x45a}, + {0x90052,0x9}, + {0x90053,0x0}, + {0x90054,0x448}, + {0x90055,0x109}, + {0x90056,0x40}, + {0x90057,0x630}, + {0x90058,0x179}, + {0x90059,0x1}, + {0x9005a,0x618}, + {0x9005b,0x109}, + {0x9005c,0x40c0}, + {0x9005d,0x630}, + {0x9005e,0x149}, + {0x9005f,0x8}, + {0x90060,0x4}, + {0x90061,0x48}, + {0x90062,0x4040}, + {0x90063,0x630}, + {0x90064,0x149}, + {0x90065,0x0}, + {0x90066,0x4}, + {0x90067,0x48}, + {0x90068,0x40}, + {0x90069,0x630}, + {0x9006a,0x149}, + {0x9006b,0x10}, + {0x9006c,0x4}, + {0x9006d,0x18}, + {0x9006e,0x0}, + {0x9006f,0x4}, + {0x90070,0x78}, + {0x90071,0x549}, + {0x90072,0x630}, + {0x90073,0x159}, + {0x90074,0xd49}, + {0x90075,0x630}, + {0x90076,0x159}, + {0x90077,0x94a}, + {0x90078,0x630}, + {0x90079,0x159}, + {0x9007a,0x441}, + {0x9007b,0x630}, + {0x9007c,0x149}, + {0x9007d,0x42}, + {0x9007e,0x630}, + {0x9007f,0x149}, + {0x90080,0x1}, + {0x90081,0x630}, + {0x90082,0x149}, + {0x90083,0x0}, + {0x90084,0xe0}, + {0x90085,0x109}, + {0x90086,0xa}, + {0x90087,0x10}, + {0x90088,0x109}, + {0x90089,0x9}, + {0x9008a,0x3c0}, + {0x9008b,0x149}, + {0x9008c,0x9}, + {0x9008d,0x3c0}, + {0x9008e,0x159}, + {0x9008f,0x18}, + {0x90090,0x10}, + {0x90091,0x109}, + {0x90092,0x0}, + {0x90093,0x3c0}, + {0x90094,0x109}, + {0x90095,0x18}, + {0x90096,0x4}, + {0x90097,0x48}, + {0x90098,0x18}, + {0x90099,0x4}, + {0x9009a,0x58}, + {0x9009b,0xa}, + {0x9009c,0x10}, + {0x9009d,0x109}, + {0x9009e,0x2}, + {0x9009f,0x10}, + {0x900a0,0x109}, + {0x900a1,0x5}, + {0x900a2,0x7c0}, + {0x900a3,0x109}, + {0x900a4,0x10}, + {0x900a5,0x10}, + {0x900a6,0x109}, + {0x40000,0x811}, + {0x40020,0x880}, + {0x40040,0x0}, + {0x40060,0x0}, + {0x40001,0x4008}, + {0x40021,0x83}, + {0x40041,0x4f}, + {0x40061,0x0}, + {0x40002,0x4040}, + {0x40022,0x83}, + {0x40042,0x51}, + {0x40062,0x0}, + {0x40003,0x811}, + {0x40023,0x880}, + {0x40043,0x0}, + {0x40063,0x0}, + {0x40004,0x720}, + {0x40024,0xf}, + {0x40044,0x1740}, + {0x40064,0x0}, + {0x40005,0x16}, + {0x40025,0x83}, + {0x40045,0x4b}, + {0x40065,0x0}, + {0x40006,0x716}, + {0x40026,0xf}, + {0x40046,0x2001}, + {0x40066,0x0}, + {0x40007,0x716}, + {0x40027,0xf}, + {0x40047,0x2800}, + {0x40067,0x0}, + {0x40008,0x716}, + {0x40028,0xf}, + {0x40048,0xf00}, + {0x40068,0x0}, + {0x40009,0x720}, + {0x40029,0xf}, + {0x40049,0x1400}, + {0x40069,0x0}, + {0x4000a,0xe08}, + {0x4002a,0xc15}, + {0x4004a,0x0}, + {0x4006a,0x0}, + {0x4000b,0x623}, + {0x4002b,0x15}, + {0x4004b,0x0}, + {0x4006b,0x0}, + {0x4000c,0x4028}, + {0x4002c,0x80}, + {0x4004c,0x0}, + {0x4006c,0x0}, + {0x4000d,0xe08}, + {0x4002d,0xc1a}, + {0x4004d,0x0}, + {0x4006d,0x0}, + {0x4000e,0x623}, + {0x4002e,0x1a}, + {0x4004e,0x0}, + {0x4006e,0x0}, + {0x4000f,0x4040}, + {0x4002f,0x80}, + {0x4004f,0x0}, + {0x4006f,0x0}, + {0x40010,0x2604}, + {0x40030,0x15}, + {0x40050,0x0}, + {0x40070,0x0}, + {0x40011,0x708}, + {0x40031,0x5}, + {0x40051,0x0}, + {0x40071,0x2002}, + {0x40012,0x8}, + {0x40032,0x80}, + {0x40052,0x0}, + {0x40072,0x0}, + {0x40013,0x2604}, + {0x40033,0x1a}, + {0x40053,0x0}, + {0x40073,0x0}, + {0x40014,0x708}, + {0x40034,0xa}, + {0x40054,0x0}, + {0x40074,0x2002}, + {0x40015,0x4040}, + {0x40035,0x80}, + {0x40055,0x0}, + {0x40075,0x0}, + {0x40016,0x60a}, + {0x40036,0x15}, + {0x40056,0x1200}, + {0x40076,0x0}, + {0x40017,0x61a}, + {0x40037,0x15}, + {0x40057,0x1300}, + {0x40077,0x0}, + {0x40018,0x60a}, + {0x40038,0x1a}, + {0x40058,0x1200}, + {0x40078,0x0}, + {0x40019,0x642}, + {0x40039,0x1a}, + {0x40059,0x1300}, + {0x40079,0x0}, + {0x4001a,0x4808}, + {0x4003a,0x880}, + {0x4005a,0x0}, + {0x4007a,0x0}, + {0x900a7,0x0}, + {0x900a8,0x790}, + {0x900a9,0x11a}, + {0x900aa,0x8}, + {0x900ab,0x7aa}, + {0x900ac,0x2a}, + {0x900ad,0x10}, + {0x900ae,0x7b2}, + {0x900af,0x2a}, + {0x900b0,0x0}, + {0x900b1,0x7c8}, + {0x900b2,0x109}, + {0x900b3,0x10}, + {0x900b4,0x2a8}, + {0x900b5,0x129}, + {0x900b6,0x8}, + {0x900b7,0x370}, + {0x900b8,0x129}, + {0x900b9,0xa}, + {0x900ba,0x3c8}, + {0x900bb,0x1a9}, + {0x900bc,0xc}, + {0x900bd,0x408}, + {0x900be,0x199}, + {0x900bf,0x14}, + {0x900c0,0x790}, + {0x900c1,0x11a}, + {0x900c2,0x8}, + {0x900c3,0x4}, + {0x900c4,0x18}, + {0x900c5,0xe}, + {0x900c6,0x408}, + {0x900c7,0x199}, + {0x900c8,0x8}, + {0x900c9,0x8568}, + {0x900ca,0x108}, + {0x900cb,0x18}, + {0x900cc,0x790}, + {0x900cd,0x16a}, + {0x900ce,0x8}, + {0x900cf,0x1d8}, + {0x900d0,0x169}, + {0x900d1,0x10}, + {0x900d2,0x8558}, + {0x900d3,0x168}, + {0x900d4,0x70}, + {0x900d5,0x788}, + {0x900d6,0x16a}, + {0x900d7,0x1ff8}, + {0x900d8,0x85a8}, + {0x900d9,0x1e8}, + {0x900da,0x50}, + {0x900db,0x798}, + {0x900dc,0x16a}, + {0x900dd,0x60}, + {0x900de,0x7a0}, + {0x900df,0x16a}, + {0x900e0,0x8}, + {0x900e1,0x8310}, + {0x900e2,0x168}, + {0x900e3,0x8}, + {0x900e4,0xa310}, + {0x900e5,0x168}, + {0x900e6,0xa}, + {0x900e7,0x408}, + {0x900e8,0x169}, + {0x900e9,0x6e}, + {0x900ea,0x0}, + {0x900eb,0x68}, + {0x900ec,0x0}, + {0x900ed,0x408}, + {0x900ee,0x169}, + {0x900ef,0x0}, + {0x900f0,0x8310}, + {0x900f1,0x168}, + {0x900f2,0x0}, + {0x900f3,0xa310}, + {0x900f4,0x168}, + {0x900f5,0x1ff8}, + {0x900f6,0x85a8}, + {0x900f7,0x1e8}, + {0x900f8,0x68}, + {0x900f9,0x798}, + {0x900fa,0x16a}, + {0x900fb,0x78}, + {0x900fc,0x7a0}, + {0x900fd,0x16a}, + {0x900fe,0x68}, + {0x900ff,0x790}, + {0x90100,0x16a}, + {0x90101,0x8}, + {0x90102,0x8b10}, + {0x90103,0x168}, + {0x90104,0x8}, + {0x90105,0xab10}, + {0x90106,0x168}, + {0x90107,0xa}, + {0x90108,0x408}, + {0x90109,0x169}, + {0x9010a,0x58}, + {0x9010b,0x0}, + {0x9010c,0x68}, + {0x9010d,0x0}, + {0x9010e,0x408}, + {0x9010f,0x169}, + {0x90110,0x0}, + {0x90111,0x8b10}, + {0x90112,0x168}, + {0x90113,0x0}, + {0x90114,0xab10}, + {0x90115,0x168}, + {0x90116,0x0}, + {0x90117,0x1d8}, + {0x90118,0x169}, + {0x90119,0x80}, + {0x9011a,0x790}, + {0x9011b,0x16a}, + {0x9011c,0x18}, + {0x9011d,0x7aa}, + {0x9011e,0x6a}, + {0x9011f,0xa}, + {0x90120,0x0}, + {0x90121,0x1e9}, + {0x90122,0x8}, + {0x90123,0x8080}, + {0x90124,0x108}, + {0x90125,0xf}, + {0x90126,0x408}, + {0x90127,0x169}, + {0x90128,0xc}, + {0x90129,0x0}, + {0x9012a,0x68}, + {0x9012b,0x9}, + {0x9012c,0x0}, + {0x9012d,0x1a9}, + {0x9012e,0x0}, + {0x9012f,0x408}, + {0x90130,0x169}, + {0x90131,0x0}, + {0x90132,0x8080}, + {0x90133,0x108}, + {0x90134,0x8}, + {0x90135,0x7aa}, + {0x90136,0x6a}, + {0x90137,0x0}, + {0x90138,0x8568}, + {0x90139,0x108}, + {0x9013a,0xb7}, + {0x9013b,0x790}, + {0x9013c,0x16a}, + {0x9013d,0x1f}, + {0x9013e,0x0}, + {0x9013f,0x68}, + {0x90140,0x8}, + {0x90141,0x8558}, + {0x90142,0x168}, + {0x90143,0xf}, + {0x90144,0x408}, + {0x90145,0x169}, + {0x90146,0xc}, + {0x90147,0x0}, + {0x90148,0x68}, + {0x90149,0x0}, + {0x9014a,0x408}, + {0x9014b,0x169}, + {0x9014c,0x0}, + {0x9014d,0x8558}, + {0x9014e,0x168}, + {0x9014f,0x8}, + {0x90150,0x3c8}, + {0x90151,0x1a9}, + {0x90152,0x3}, + {0x90153,0x370}, + {0x90154,0x129}, + {0x90155,0x20}, + {0x90156,0x2aa}, + {0x90157,0x9}, + {0x90158,0x0}, + {0x90159,0x400}, + {0x9015a,0x10e}, + {0x9015b,0x8}, + {0x9015c,0xe8}, + {0x9015d,0x109}, + {0x9015e,0x0}, + {0x9015f,0x8140}, + {0x90160,0x10c}, + {0x90161,0x10}, + {0x90162,0x8138}, + {0x90163,0x10c}, + {0x90164,0x8}, + {0x90165,0x7c8}, + {0x90166,0x101}, + {0x90167,0x8}, + {0x90168,0x0}, + {0x90169,0x8}, + {0x9016a,0x8}, + {0x9016b,0x448}, + {0x9016c,0x109}, + {0x9016d,0xf}, + {0x9016e,0x7c0}, + {0x9016f,0x109}, + {0x90170,0x0}, + {0x90171,0xe8}, + {0x90172,0x109}, + {0x90173,0x47}, + {0x90174,0x630}, + {0x90175,0x109}, + {0x90176,0x8}, + {0x90177,0x618}, + {0x90178,0x109}, + {0x90179,0x8}, + {0x9017a,0xe0}, + {0x9017b,0x109}, + {0x9017c,0x0}, + {0x9017d,0x7c8}, + {0x9017e,0x109}, + {0x9017f,0x8}, + {0x90180,0x8140}, + {0x90181,0x10c}, + {0x90182,0x0}, + {0x90183,0x1}, + {0x90184,0x8}, + {0x90185,0x8}, + {0x90186,0x4}, + {0x90187,0x8}, + {0x90188,0x8}, + {0x90189,0x7c8}, + {0x9018a,0x101}, + {0x90006,0x0}, + {0x90007,0x0}, + {0x90008,0x8}, + {0x90009,0x0}, + {0x9000a,0x0}, + {0x9000b,0x0}, + {0xd00e7,0x400}, + {0x90017,0x0}, + {0x9001f,0x2a}, + {0x90026,0x6a}, + {0x400d0,0x0}, + {0x400d1,0x101}, + {0x400d2,0x105}, + {0x400d3,0x107}, + {0x400d4,0x10f}, + {0x400d5,0x202}, + {0x400d6,0x20a}, + {0x400d7,0x20b}, + {0x2003a,0x2}, + {0x2000b,0x5d}, + {0x2000c,0xbb}, + {0x2000d,0x753}, + {0x2000e,0x2c}, + {0x12000b,0xc}, + {0x12000c,0x19}, + {0x12000d,0xfa}, + {0x12000e,0x10}, + {0x22000b,0x3}, + {0x22000c,0x6}, + {0x22000d,0x3e}, + {0x22000e,0x10}, + {0x9000c,0x0}, + {0x9000d,0x173}, + {0x9000e,0x60}, + {0x9000f,0x6110}, + {0x90010,0x2152}, + {0x90011,0xdfbd}, + {0x90012,0x60}, + {0x90013,0x6152}, + {0x20010,0x5a}, + {0x20011,0x3}, + {0x120010,0x5a}, + {0x120011,0x3}, + {0x220010,0x5a}, + {0x220011,0x3}, + {0x40080,0xe0}, + {0x40081,0x12}, + {0x40082,0xe0}, + {0x40083,0x12}, + {0x40084,0xe0}, + {0x40085,0x12}, + {0x140080,0xe0}, + {0x140081,0x12}, + {0x140082,0xe0}, + {0x140083,0x12}, + {0x140084,0xe0}, + {0x140085,0x12}, + {0x240080,0xe0}, + {0x240081,0x12}, + {0x240082,0xe0}, + {0x240083,0x12}, + {0x240084,0xe0}, + {0x240085,0x12}, + {0x400fd,0xf}, + {0x10011,0x1}, + {0x10012,0x1}, + {0x10013,0x180}, + {0x10018,0x1}, + {0x10002,0x6209}, + {0x100b2,0x1}, + {0x101b4,0x1}, + {0x102b4,0x1}, + {0x103b4,0x1}, + {0x104b4,0x1}, + {0x105b4,0x1}, + {0x106b4,0x1}, + {0x107b4,0x1}, + {0x108b4,0x1}, + {0x11011,0x1}, + {0x11012,0x1}, + {0x11013,0x180}, + {0x11018,0x1}, + {0x11002,0x6209}, + {0x110b2,0x1}, + {0x111b4,0x1}, + {0x112b4,0x1}, + {0x113b4,0x1}, + {0x114b4,0x1}, + {0x115b4,0x1}, + {0x116b4,0x1}, + {0x117b4,0x1}, + {0x118b4,0x1}, + {0x12011,0x1}, + {0x12012,0x1}, + {0x12013,0x180}, + {0x12018,0x1}, + {0x12002,0x6209}, + {0x120b2,0x1}, + {0x121b4,0x1}, + {0x122b4,0x1}, + {0x123b4,0x1}, + {0x124b4,0x1}, + {0x125b4,0x1}, + {0x126b4,0x1}, + {0x127b4,0x1}, + {0x128b4,0x1}, + {0x13011,0x1}, + {0x13012,0x1}, + {0x13013,0x180}, + {0x13018,0x1}, + {0x13002,0x6209}, + {0x130b2,0x1}, + {0x131b4,0x1}, + {0x132b4,0x1}, + {0x133b4,0x1}, + {0x134b4,0x1}, + {0x135b4,0x1}, + {0x136b4,0x1}, + {0x137b4,0x1}, + {0x138b4,0x1}, + {0x2003a,0x2}, + {0xc0080,0x2}, + {0xd0000, 0x1} +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3000mts 1D */ + .drate = 3000, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3000, 400, 100, }, +}; + diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 64bc60651d3..4ca63ff1ba0 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -20,13 +20,18 @@ #include #include -#include -#include -#include -#include - #include +#ifdef CONFIG_POWER_PCA9450 +#include +#else #include +#endif +#include +#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -39,100 +44,263 @@ int spl_board_boot_device(enum boot_device boot_dev_spl) case SD3_BOOT: case MMC3_BOOT: return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + return BOOT_DEVICE_BOARD; default: return BOOT_DEVICE_NONE; } } -static void spl_dram_init(void) +void spl_dram_init(void) { ddr_init(&dram_timing); } -void spl_board_init(void) +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +/* + * The evk board uses DAT3 to detect CD card plugin, + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. + */ +static iomux_v3_cfg_t const usdhc2_cd_pad = + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); + +static iomux_v3_cfg_t const usdhc2_dat3_pad = + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | + MUX_PAD_CTRL(USDHC_PAD_CTRL); + + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 8}, +}; + +int board_mmc_init(struct bd_info *bis) { - puts("Normal Boot\n"); + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(2); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; } -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) +int board_mmc_getcd(struct mmc *mmc) { - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + imx_iomux_v3_setup_pad(usdhc2_cd_pad); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + + /* + * Since it is the DAT3 pin, this pin is pulled to + * low voltage if no card + */ + ret = gpio_get_value(USDHC2_CD_GPIO); + + imx_iomux_v3_setup_pad(usdhc2_dat3_pad); + return ret; + } - return 0; + return 1; } -#endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +#ifdef CONFIG_POWER_PCA9450 +int power_init_board(void) +{ + struct pmic *p; + int ret; -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; + ret = power_pca9450_init(I2C_PMIC); + if (ret) + printf("power init failed"); + p = pmic_get("PCA9450"); + pmic_probe(p); -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + /* Buck 1 DVS control through PMIC_STBY_REQ */ + pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); + + /* Set DVS1 to 0.8v for suspend */ + pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x10); - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + /* increase VDD_DRAM to 0.95v for 3Ghz DDR */ + pmic_reg_write(p, PCA9450_BUCK3OUT_DVS0, 0x1C); - set_wdog_reset(wdog); + /* VDD_DRAM needs off in suspend, set B1_ENMODE=10 (ON by PMIC_ON_REQ = H && PMIC_STBY_REQ = L) */ + pmic_reg_write(p, PCA9450_BUCK3CTRL, 0x4a); - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(p, PCA9450_LDO2CTRL, 0xC0); + + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); return 0; } - -static int power_init_board(void) +#else +int power_init_board(void) { - struct udevice *dev; + struct pmic *p; int ret; - ret = pmic_get("pmic@4b", &dev); - if (ret == -ENODEV) { - puts("No pmic\n"); - return 0; - } - if (ret != 0) - return ret; + ret = power_bd71837_init(I2C_PMIC); + if (ret) + printf("power init failed"); + + p = pmic_get("BD71837"); + pmic_probe(p); + /* decrease RESET key long push time from the default 10s to 10ms */ - pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); + pmic_reg_write(p, BD718XX_PWRONCONFIG1, 0x0); /* unlock the PMIC regs */ - pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); + pmic_reg_write(p, BD718XX_REGLOCK, 0x1); /* increase VDD_SOC to typical value 0.85v before first DRAM access */ - pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f); + pmic_reg_write(p, BD718XX_BUCK1_VOLT_RUN, 0x0f); /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ - pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); + pmic_reg_write(p, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83); #ifndef CONFIG_IMX8M_LPDDR4 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ - pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); + pmic_reg_write(p, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); #endif /* lock the PMIC regs */ - pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); + pmic_reg_write(p, BD718XX_REGLOCK, 0x11); + + return 0; +} +#endif +#endif + +void spl_board_init(void) +{ +#ifdef CONFIG_FSL_CAAM + if (sec_init()) { + printf("\nsec_init failed!\n"); + } +#endif +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); return 0; } +#endif void board_init_f(ulong dummy) { - struct udevice *dev; int ret; - arch_cpu_init(); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); - init_uart_clk(1); + arch_cpu_init(); board_early_init_f(); @@ -140,25 +308,17 @@ void board_init_f(ulong dummy) preloader_console_init(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_early_init(); + ret = spl_init(); if (ret) { - debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - ret = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@30380000", - &dev); - if (ret < 0) { - printf("Failed to find clock node. Check device tree\n"); + debug("spl_init() failed: %d\n", ret); hang(); } enable_tzc380(); + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + power_init_board(); /* DDR initialization */ diff --git a/board/freescale/imx8mm_val/Kconfig b/board/freescale/imx8mm_val/Kconfig new file mode 100644 index 00000000000..2364cc431ad --- /dev/null +++ b/board/freescale/imx8mm_val/Kconfig @@ -0,0 +1,14 @@ + if TARGET_IMX8MM_DDR4_VAL || TARGET_IMX8MM_DDR3L_VAL + +config SYS_BOARD + default "imx8mm_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mm_val" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/imx8mm_val/Makefile b/board/freescale/imx8mm_val/Makefile new file mode 100644 index 00000000000..1871b53a3d5 --- /dev/null +++ b/board/freescale/imx8mm_val/Makefile @@ -0,0 +1,13 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mm_val.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o +obj-$(CONFIG_IMX8M_DDR3L) += ddr3l_timing.o +endif diff --git a/board/freescale/imx8mm_val/ddr3l_timing.c b/board/freescale/imx8mm_val/ddr3l_timing.c new file mode 100644 index 00000000000..467476d788c --- /dev/null +++ b/board/freescale/imx8mm_val/ddr3l_timing.c @@ -0,0 +1,1384 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct dram_cfg_param ddr3l_ddrc_cfg[] = { + { DDRC_MSTR(0), 0xa3040001 }, + { DDRC_PWRCTL(0), 0x000000a8 }, + { DDRC_PWRTMG(0), 0x00532203 }, + { DDRC_RFSHCTL0(0), 0x00203020 }, + { DDRC_RFSHCTL1(0), 0x0001000d }, + { DDRC_RFSHCTL3(0), 0x00000000 }, + { DDRC_RFSHTMG(0), 0x0061008c }, + { DDRC_CRCPARCTL0(0), 0x00000000 }, + { DDRC_CRCPARCTL1(0), 0x00000000 }, + { DDRC_INIT0(0), 0xc0030002 }, + { DDRC_INIT1(0), 0x0001000b }, + { DDRC_INIT2(0), 0x00006303 }, + { DDRC_INIT3(0), 0x0d700004 },/* MR1, MR0 */ + { DDRC_INIT4(0), 0x00180000 },/* MR2 */ + { DDRC_INIT5(0), 0x00090071 }, + { DDRC_INIT6(0), 0x00000000 }, + { DDRC_INIT7(0), 0x00000000 }, + { DDRC_DIMMCTL(0), 0x00000032 }, /* [1] dimm_addr_mirr_en, it will effect the MRS if use umctl2 to initi dram. */ + { DDRC_RANKCTL(0), 0x00000ee5 }, + { DDRC_DRAMTMG0(0), 0x0c101a0e }, + { DDRC_DRAMTMG1(0), 0x000a0314 }, + { DDRC_DRAMTMG2(0), 0x04060509 }, + { DDRC_DRAMTMG3(0), 0x00002006 }, + { DDRC_DRAMTMG4(0), 0x06020306 }, + { DDRC_DRAMTMG5(0), 0x0b060202 }, + { DDRC_DRAMTMG6(0), 0x060a0009 }, + { DDRC_DRAMTMG7(0), 0x0000060b }, + { DDRC_DRAMTMG8(0), 0x01017c0a }, + { DDRC_DRAMTMG9(0), 0x4000000e }, + { DDRC_DRAMTMG10(0), 0x00070803 }, + { DDRC_DRAMTMG11(0), 0x0101000b }, + { DDRC_DRAMTMG12(0), 0x00000000 }, + { DDRC_DRAMTMG13(0), 0x5d000000 }, + { DDRC_DRAMTMG14(0), 0x00000b39 }, + { DDRC_DRAMTMG15(0), 0x80000000 }, + { DDRC_DRAMTMG17(0), 0x00f1006a }, + { DDRC_ZQCTL0(0), 0x50800020 }, + { DDRC_ZQCTL1(0), 0x00000070 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + { DDRC_DFITMG0(0), 0x03868203 }, + { DDRC_DFITMG1(0), 0x00020103 }, + { DDRC_DFILPCFG0(0), 0x07713021 }, + { DDRC_DFILPCFG1(0), 0x00000010 }, + { DDRC_DFIUPD0(0), 0xe0400018 }, + { DDRC_DFIUPD1(0), 0x0005003c }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000001 }, + { DDRC_DFITMG2(0), 0x00000603 }, + { DDRC_DFITMG3(0), 0x00000001 }, + { DDRC_DBICTL(0), 0x00000001 }, + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + + { DDRC_ADDRMAP0(0), 0x00000016 }, /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */ + { DDRC_ADDRMAP2(0), 0x00000000 }, /* [3:0] col-b2: 2; [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */ + { DDRC_ADDRMAP3(0), 0x00000000 }, /* [3:0] col-b6: 6; [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */ + { DDRC_ADDRMAP4(0), 0x00001f1f }, /* col-b10, col-b11 not used */ + { DDRC_ADDRMAP5(0), 0x07070707 }, /* [3:0] row-b0: 6; [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */ + { DDRC_ADDRMAP6(0), 0x0f070707 }, /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */ + { DDRC_ADDRMAP7(0), 0x00000f0f }, + { DDRC_ADDRMAP8(0), 0x00000000 }, /* [5:0] bg-b0; [13:8]bg-b1 */ + { DDRC_ADDRMAP9(0), 0x0a020b06 }, /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + { DDRC_ADDRMAP10(0), 0x0a0a0a0a },/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + { DDRC_ADDRMAP11(0), 0x00000000 }, + + { DDRC_ODTCFG(0), 0x041d0f5c }, + { DDRC_ODTMAP(0), 0x00000201 }, + { DDRC_SCHED(0), 0x7ab50b07 }, + { DDRC_SCHED1(0), 0x00000022 }, + { DDRC_PERFHPR1(0), 0x7b00665e }, + { DDRC_PERFLPR1(0), 0x2b00c4e1 }, + { DDRC_PERFWR1(0), 0xb700c9fe }, + { DDRC_DBG0(0), 0x00000017 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00010000 }, + { DDRC_PCCFG(0), 0x00000100 }, + { DDRC_PCFGR_0(0), 0x00003051 }, + { DDRC_PCFGW_0(0), 0x000061d2 }, + { DDRC_PCTRL_0(0), 0x00000001 }, + { DDRC_PCFGQOS0_0(0), 0x02100b04 }, + { DDRC_PCFGQOS1_0(0), 0x003f0353 }, + { DDRC_PCFGWQOS0_0(0), 0x00000002 }, + { DDRC_PCFGWQOS1_0(0), 0x000005fd }, + + { DDRC_FREQ1_RFSHCTL0(0), 0x00d19034 }, + { DDRC_FREQ1_RFSHTMG(0), 0x0040805e }, + { DDRC_FREQ1_INIT3(0), 0x09300004 }, + { DDRC_FREQ1_INIT4(0), 0x00080000 }, + { DDRC_FREQ1_INIT6(0), 0x00000000 }, + { DDRC_FREQ1_INIT7(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG0(0), 0x090e110a }, + { DDRC_FREQ1_DRAMTMG1(0), 0x0007020e }, + { DDRC_FREQ1_DRAMTMG2(0), 0x03040407 }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00002006 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x04020304 }, /* tRP=6 --> 7 */ + { DDRC_FREQ1_DRAMTMG5(0), 0x09030202 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0c020000 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x00000309 }, + { DDRC_FREQ1_DRAMTMG8(0), 0x01010a06 }, + { DDRC_FREQ1_DRAMTMG9(0), 0x00000003 }, + { DDRC_FREQ1_DRAMTMG10(0), 0x00090906 }, + { DDRC_FREQ1_DRAMTMG11(0), 0x01010011 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG13(0), 0x40000000 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x000000f3 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x80000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x001a0046 }, + { DDRC_FREQ1_ZQCTL0(0), 0x50800020 }, + { DDRC_FREQ1_DFITMG0(0), 0x03828201 }, + { DDRC_FREQ1_DFITMG1(0), 0x00020103 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000201 }, + { DDRC_FREQ1_DFITMG3(0), 0x00000001 }, + { DDRC_FREQ1_ODTCFG(0), 0x0a1a0768 }, + + { DDRC_FREQ2_RFSHCTL0(0), 0x00208014 }, + { DDRC_FREQ2_RFSHTMG(0), 0x00308046 }, + { DDRC_FREQ2_INIT3(0), 0x05200004 }, + { DDRC_FREQ2_INIT4(0), 0x00000000 }, + { DDRC_FREQ2_INIT6(0), 0x00000000 }, + { DDRC_FREQ2_INIT7(0), 0x00000000 }, + { DDRC_FREQ2_DRAMTMG0(0), 0x070a0c07 }, + { DDRC_FREQ2_DRAMTMG1(0), 0x0005020b }, + { DDRC_FREQ2_DRAMTMG2(0), 0x03030407 }, + { DDRC_FREQ2_DRAMTMG3(0), 0x00002006 }, + { DDRC_FREQ2_DRAMTMG4(0), 0x03020204 }, + { DDRC_FREQ2_DRAMTMG5(0), 0x04070302 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x07080000 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x00000704 }, + { DDRC_FREQ2_DRAMTMG8(0), 0x02026804 }, + { DDRC_FREQ2_DRAMTMG9(0), 0x40000006 }, + { DDRC_FREQ2_DRAMTMG10(0), 0x000c0b08 }, + { DDRC_FREQ2_DRAMTMG11(0), 0x01010015 }, + { DDRC_FREQ2_DRAMTMG12(0), 0x00000000 }, + { DDRC_FREQ2_DRAMTMG13(0), 0x51000000 }, + { DDRC_FREQ2_DRAMTMG14(0), 0x000002a0 }, + { DDRC_FREQ2_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x008c0039 }, + { DDRC_FREQ2_ZQCTL0(0), 0x50800020 }, + { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, + { DDRC_FREQ2_DFITMG1(0), 0x00020103 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000100 }, + { DDRC_FREQ2_DFITMG3(0), 0x00000001 }, + { DDRC_FREQ2_ODTCFG(0), 0x04050800 }, + + /* default start freq point */ + { DDRC_MSTR2(0), 0x2}, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr3l_ddrphy_cfg[] = { + { 0x1005f, 0x3cf }, + { 0x1015f, 0x3cf }, + { 0x1105f, 0x3cf }, + { 0x1115f, 0x3cf }, + { 0x1205f, 0x3cf }, + { 0x1215f, 0x3cf }, + { 0x1305f, 0x3cf }, + { 0x1315f, 0x3cf }, + + { 0x11005f, 0x3cf }, + { 0x11015f, 0x3cf }, + { 0x11105f, 0x3cf }, + { 0x11115f, 0x3cf }, + { 0x11205f, 0x3cf }, + { 0x11215f, 0x3cf }, + { 0x11305f, 0x3cf }, + { 0x11315f, 0x3cf }, + + { 0x21005f, 0x3cf }, + { 0x21015f, 0x3cf }, + { 0x21105f, 0x3cf }, + { 0x21115f, 0x3cf }, + { 0x21205f, 0x3cf }, + { 0x21215f, 0x3cf }, + { 0x21305f, 0x3cf }, + { 0x21315f, 0x3cf }, + + { 0x55, 0x365 }, + { 0x1055, 0x365 }, + { 0x2055, 0x365 }, + { 0x3055, 0x365 }, + { 0x4055, 0x65 }, + { 0x5055, 0x65 }, + { 0x6055, 0x365 }, + { 0x7055, 0x365 }, + { 0x8055, 0x365 }, + { 0x9055, 0x365 }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x1 }, + { 0x22002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x0 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x0 }, + { 0x220024, 0x8 }, + { 0x2003a, 0x0 }, + { 0x20056, 0xa }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0x618 }, + { 0x1014d, 0x618 }, + { 0x1104d, 0x618 }, + { 0x1114d, 0x618 }, + { 0x1204d, 0x618 }, + { 0x1214d, 0x618 }, + { 0x1304d, 0x618 }, + { 0x1314d, 0x618 }, + { 0x11004d, 0x618 }, + { 0x11014d, 0x618 }, + { 0x11104d, 0x618 }, + { 0x11114d, 0x618 }, + { 0x11204d, 0x618 }, + { 0x11214d, 0x618 }, + { 0x11304d, 0x618 }, + { 0x11314d, 0x618 }, + { 0x21004d, 0x618 }, + { 0x21014d, 0x618 }, + { 0x21104d, 0x618 }, + { 0x21114d, 0x618 }, + { 0x21204d, 0x618 }, + { 0x21214d, 0x618 }, + { 0x21304d, 0x618 }, + { 0x21314d, 0x618 }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x12049, 0xe38 }, + { 0x12149, 0xe38 }, + { 0x13049, 0xe38 }, + { 0x13149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x112049, 0xe38 }, + { 0x112149, 0xe38 }, + { 0x113049, 0xe38 }, + { 0x113149, 0xe38 }, + { 0x210049, 0xe38 }, + { 0x210149, 0xe38 }, + { 0x211049, 0xe38 }, + { 0x211149, 0xe38 }, + { 0x212049, 0xe38 }, + { 0x212149, 0xe38 }, + { 0x213049, 0xe38 }, + { 0x213149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x5 }, + { 0x20075, 0x0 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0x85 }, + { 0x220008, 0x53 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xf8 }, + { 0x10043, 0x581 }, + { 0x10143, 0x581 }, + { 0x11043, 0x581 }, + { 0x11143, 0x581 }, + { 0x12043, 0x581 }, + { 0x12143, 0x581 }, + { 0x13043, 0x581 }, + { 0x13143, 0x581 }, + { 0x1200b2, 0xf8 }, + { 0x110043, 0x581 }, + { 0x110143, 0x581 }, + { 0x111043, 0x581 }, + { 0x111143, 0x581 }, + { 0x112043, 0x581 }, + { 0x112143, 0x581 }, + { 0x113043, 0x581 }, + { 0x113143, 0x581 }, + { 0x2200b2, 0xf8 }, + { 0x210043, 0x581 }, + { 0x210143, 0x581 }, + { 0x211043, 0x581 }, + { 0x211143, 0x581 }, + { 0x212043, 0x581 }, + { 0x212143, 0x581 }, + { 0x213043, 0x581 }, + { 0x213143, 0x581 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x220019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, +}; + +/* ddr phy trained CSR */ +struct dram_cfg_param ddr3l_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr3l_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x140 }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0xd70 }, + { 0x54030, 0x4 }, + { 0x54031, 0x18 }, + { 0x5403a, 0x1221 }, + { 0x5403b, 0x4884 }, + { 0xd0000, 0x1 }, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr3l_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x214 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x140 }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x930 }, + { 0x54030, 0x4 }, + { 0x54031, 0x8 }, + { 0x5403a, 0x1221 }, + { 0x5403b, 0x4884 }, + { 0xd0000, 0x1 }, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr3l_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x2 }, + { 0x54003, 0x14c }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x140 }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x520 }, + { 0x54030, 0x4 }, + { 0x54031, 0x0 }, + { 0x5403a, 0x1221 }, + { 0x5403b, 0x4884 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr3l_phy_pie[] = { + { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + { 0x90000, 0x10 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + { 0x90001, 0x400 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + { 0x90002, 0x10e }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + { 0x90003, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + { 0x90004, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + { 0x90005, 0x8 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + { 0x90029, 0xb }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + { 0x9002a, 0x480 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + { 0x9002b, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + { 0x9002c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + { 0x9002d, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + { 0x9002e, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + { 0x9002f, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + { 0x90030, 0x478 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + { 0x90031, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + { 0x90032, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + { 0x90033, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + { 0x90034, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + { 0x90035, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + { 0x90036, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + { 0x90037, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + { 0x90038, 0x44 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + { 0x90039, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + { 0x9003a, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + { 0x9003b, 0x14f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + { 0x9003c, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + { 0x9003d, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + { 0x9003e, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + { 0x9003f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + { 0x90040, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + { 0x90041, 0x4f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + { 0x90042, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + { 0x90043, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + { 0x90044, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + { 0x90045, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + { 0x90046, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + { 0x90047, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + { 0x90048, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + { 0x90049, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + { 0x9004a, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + { 0x9004b, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + { 0x9004c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + { 0x9004d, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + { 0x9004e, 0x45a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + { 0x9004f, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + { 0x90050, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + { 0x90051, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + { 0x90052, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + { 0x90053, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + { 0x90054, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + { 0x90055, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + { 0x90056, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + { 0x90057, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + { 0x90058, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + { 0x90059, 0x40c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + { 0x9005a, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + { 0x9005b, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + { 0x9005c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + { 0x9005d, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + { 0x9005e, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + { 0x9005f, 0x4040 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + { 0x90060, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + { 0x90061, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + { 0x90062, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + { 0x90063, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + { 0x90064, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + { 0x90065, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + { 0x90066, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + { 0x90067, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + { 0x90068, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + { 0x90069, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + { 0x9006a, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + { 0x9006b, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + { 0x9006c, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + { 0x9006d, 0x78 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + { 0x9006e, 0x549 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + { 0x9006f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + { 0x90070, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + { 0x90071, 0xd49 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + { 0x90072, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + { 0x90073, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + { 0x90074, 0x94a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + { 0x90075, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + { 0x90076, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + { 0x90077, 0x441 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + { 0x90078, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + { 0x90079, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + { 0x9007a, 0x42 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + { 0x9007b, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + { 0x9007c, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + { 0x9007d, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + { 0x9007e, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + { 0x9007f, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + { 0x90080, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + { 0x90081, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + { 0x90082, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + { 0x90083, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + { 0x90084, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + { 0x90085, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + { 0x90086, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + { 0x90087, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + { 0x90088, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + { 0x90089, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + { 0x9008a, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + { 0x9008b, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + { 0x9008c, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + { 0x9008d, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + { 0x9008e, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + { 0x9008f, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + { 0x90090, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + { 0x90091, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + { 0x90092, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + { 0x90093, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + { 0x90094, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + { 0x90095, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + { 0x90096, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + { 0x90097, 0x58 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + { 0x90098, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + { 0x90099, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + { 0x9009a, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + { 0x9009b, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + { 0x9009c, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + { 0x9009d, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + { 0x9009e, 0x7 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + { 0x9009f, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + { 0x900a0, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + { 0x900a1, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + { 0x900a2, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + { 0x900a3, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + { 0x900a4, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + { 0x900a5, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + { 0x900a6, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + { 0x900a7, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + { 0x900a8, 0x8138 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + { 0x900a9, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + { 0x900aa, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + { 0x900ab, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + { 0x900ac, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + { 0x900ad, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + { 0x900ae, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + { 0x900af, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + { 0x900b0, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + { 0x900b1, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + { 0x900b2, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + { 0x900b3, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + { 0x900b4, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + { 0x900b5, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + { 0x900b6, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + { 0x900b7, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + { 0x900b8, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + { 0x900b9, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + { 0x900ba, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + { 0x900bb, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + { 0x900bc, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + { 0x900bd, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + { 0x900be, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + { 0x900bf, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + { 0x900c0, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + { 0x900c1, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + { 0x900c2, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + { 0x900c3, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + { 0x900c4, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + { 0x900c5, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + { 0x900c6, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + { 0x900c7, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + { 0x900c8, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + { 0x900c9, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + { 0x900ca, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + { 0x900cb, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + { 0x900cc, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + { 0x900cd, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + { 0x90006, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + { 0x90007, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + { 0x90008, 0x8 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + { 0x90009, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + { 0x9000a, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + { 0x9000b, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + { 0xd00e7, 0x400 }, /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + { 0x90017, 0x0 }, /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + { 0x90026, 0x2c }, /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + { 0x2000b, 0x32 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + { 0x2000c, 0x64 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + { 0x2000d, 0x3e8 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + { 0x2000e, 0x2c }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + { 0x12000b, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */ + { 0x12000c, 0x21 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */ + { 0x12000d, 0x14c }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */ + { 0x12000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */ + { 0x22000b, 0xa }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */ + { 0x22000c, 0x14 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */ + { 0x22000d, 0xcf }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */ + { 0x22000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */ + { 0x9000c, 0x0 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + { 0x9000d, 0x173 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + { 0x9000e, 0x60 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + { 0x9000f, 0x6110 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + { 0x90010, 0x2152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + { 0x90011, 0xdfbd }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + { 0x90012, 0xffff }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + { 0x90013, 0x6152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + { 0xc0080, 0x0 }, /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +}; + +struct dram_fsp_msg ddr3l_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr3l_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp0_cfg), + }, +#if 1 + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr3l_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp1_cfg), + }, + { + /* P2 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr3l_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr3l_fsp2_cfg), + }, +#endif +}; + +/* ddr3l timing config params on VAL board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr3l_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr3l_ddrc_cfg), + .ddrphy_cfg = ddr3l_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr3l_ddrphy_cfg), + .fsp_msg = ddr3l_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr3l_dram_fsp_msg), + .ddrphy_trained_csr = ddr3l_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr3l_ddrphy_trained_csr), + .ddrphy_pie = ddr3l_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr3l_phy_pie), + .fsp_table = { 1600, 1066, 667 }, +}; diff --git a/board/freescale/imx8mm_val/ddr4_timing.c b/board/freescale/imx8mm_val/ddr4_timing.c new file mode 100644 index 00000000000..c4c800f7dda --- /dev/null +++ b/board/freescale/imx8mm_val/ddr4_timing.c @@ -0,0 +1,1496 @@ +/* + * Copyright 2018-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct dram_cfg_param ddr4_ddrc_cfg[] = { + { DDRC_MSTR(0), 0x83040010 }, + { DDRC_PWRCTL(0), 0x000000aa }, + { DDRC_PWRTMG(0), 0x00221306 }, + { DDRC_RFSHCTL0(0), 0x00c0a070 }, + { DDRC_RFSHCTL1(0), 0x00010008 }, + { DDRC_RFSHCTL3(0), 0x00000010 }, + { DDRC_RFSHTMG(0), 0x004980f4 }, + { DDRC_CRCPARCTL0(0), 0x00000000 }, + { DDRC_CRCPARCTL1(0), 0x00001010 }, + { DDRC_INIT0(0), 0xc0030002 }, + { DDRC_INIT1(0), 0x00020009 }, + { DDRC_INIT2(0), 0x0000350f }, +// { DDRC_INIT3(0), (mr_value[0][0]<<16) | (mr_value[0][1]) }, + { DDRC_INIT3(0), (0xa34 << 16) | 0x105 }, +// { DDRC_INIT4(0), (mr_value[0][2]<<16) | (mr_value[0][3]) }, + { DDRC_INIT4(0), (0x1028 << 16) | 0x240 }, + { DDRC_INIT5(0), 0x001103cb }, +// { DDRC_INIT6(0), (mr_value[0][4]<<16) | (mr_value[0][5]) }, + { DDRC_INIT6(0), (0x200 << 16) | 0x200 }, +// { DDRC_INIT7(0), mr_value[0][6] }, + { DDRC_INIT7(0), 0x814 }, + { DDRC_DIMMCTL(0), 0x00000032 }, + { DDRC_RANKCTL(0), 0x00000fc7 }, + { DDRC_DRAMTMG0(0), 0x14132813 }, + { DDRC_DRAMTMG1(0), 0x0004051b }, + { DDRC_DRAMTMG2(0), 0x0808030f }, + { DDRC_DRAMTMG3(0), 0x0000400c }, + { DDRC_DRAMTMG4(0), 0x08030409 }, + { DDRC_DRAMTMG5(0), 0x0e090504 }, + { DDRC_DRAMTMG6(0), 0x05030000 }, + { DDRC_DRAMTMG7(0), 0x0000090e }, + { DDRC_DRAMTMG8(0), 0x0606700c }, + { DDRC_DRAMTMG9(0), 0x0002040c }, + { DDRC_DRAMTMG10(0), 0x000f0c07 }, + { DDRC_DRAMTMG11(0), 0x1809011d }, + { DDRC_DRAMTMG12(0), 0x0000000d }, + { DDRC_DRAMTMG13(0), 0x2b000000 }, + { DDRC_DRAMTMG14(0), 0x000000a4 }, + { DDRC_DRAMTMG15(0), 0x00000000 }, + { DDRC_DRAMTMG17(0), 0x00250078 }, + { DDRC_ZQCTL0(0), 0x51000040 }, + { DDRC_ZQCTL1(0), 0x00000070 }, + { DDRC_ZQCTL2(0), 0x00000000 }, + { DDRC_DFITMG0(0), 0x038b820b }, + { DDRC_DFITMG1(0), 0x02020103 }, + { DDRC_DFILPCFG0(0), 0x07f04011 }, /* [8]dfi_lp_en_sr = 0 */ + { DDRC_DFILPCFG1(0), 0x000000b0 }, + { DDRC_DFIUPD0(0), 0xe0400018 }, + { DDRC_DFIUPD1(0), 0x0048005a }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000001 }, + { DDRC_DFITMG2(0), 0x00000b0b }, + { DDRC_DFITMG3(0), 0x00000001 }, + { DDRC_DBICTL(0), 0x00000000 }, + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + + { DDRC_ADDRMAP0(0), 0x00000017 }, /* [4:0]cs0: 6+23 */ + { DDRC_ADDRMAP1(0), 0x003F0909 }, /* [5:0] bank b0: 2+9; [13:8] b1: P3+9 ; [21:16] b2: 4+, unused */ + { DDRC_ADDRMAP2(0), 0x01010100 }, /* [3:0] col-b2: 2; [11:8] col-b3: 3+1; [19:16] col-b4: 4+1 ; [27:24] col-b5: 5+1 */ + { DDRC_ADDRMAP3(0), 0x01010101 }, /* [3:0] col-b6: 6+1; [11:8] col-b7: 7+1; [19:16] col-b8: 8+1 ; [27:24] col-b9: 9+1 */ + { DDRC_ADDRMAP4(0), 0x00001f1f }, /* col-b10, col-b11 not used */ + { DDRC_ADDRMAP5(0), 0x07070707 }, /* [3:0] row-b0: 6+7; [11:8] row-b1: 7+7; [19:16] row-b2_b10: 8~16+7; [27:24] row-b11: 17+7 */ + { DDRC_ADDRMAP6(0), 0x07070707 }, /* [3:0] row-b12:18+7; [11:8] row-b13: 19+7; [19:16] row-b14:20+7; [27:24] row-b15: 21+7 */ + { DDRC_ADDRMAP7(0), 0x00000f0f }, /* col-b10, col-b11 not used */ + { DDRC_ADDRMAP8(0), 0x00003F01 }, /* [5:0] bg-b0: 2+1; [13:8]bg-b1:3+, unused */ + { DDRC_ADDRMAP9(0), 0x0a020b06 }, /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + { DDRC_ADDRMAP10(0), 0x0a0a0a0a },/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + { DDRC_ADDRMAP11(0), 0x00000000 }, + + /* FREQ0: BL8, CL=16, CWL=16, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1, so wr_odt_hold=5+1+1=7 */ + /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */ + { DDRC_ODTCFG(0), 0x07000600 }, + { DDRC_ODTMAP(0), 0x0201 },/* disable ODT0x00001120 , */ + { DDRC_SCHED(0), 0x317d1a07 }, + { DDRC_SCHED1(0), 0x0000000f }, + { DDRC_PERFHPR1(0), 0x2a001b76 }, + { DDRC_PERFLPR1(0), 0x7300b473 }, + { DDRC_PERFWR1(0), 0x30000e06 }, + { DDRC_DBG0(0), 0x00000014 }, + { DDRC_DBG1(0), 0x00000000 }, + { DDRC_DBGCMD(0), 0x00000000 }, + { DDRC_SWCTL(0), 0x00000001 }, + { DDRC_POISONCFG(0), 0x00000010 }, + { DDRC_PCCFG(0), 0x00000100 },/* bl_exp_mode=1 */ + { DDRC_PCFGR_0(0), 0x00013193 }, + { DDRC_PCFGW_0(0), 0x00006096 }, + { DDRC_PCTRL_0(0), 0x00000001 }, + { DDRC_PCFGQOS0_0(0), 0x02000c00 }, + { DDRC_PCFGQOS1_0(0), 0x003c00db }, + { DDRC_PCFGWQOS0_0(0), 0x00100009 }, + { DDRC_PCFGWQOS1_0(0), 0x00000002 }, + + { DDRC_FREQ1_RFSHCTL0(0), 0x0021a0c0 }, + { DDRC_FREQ1_RFSHTMG(0), 0x0018001a },/* tREFI=7.8us */ +// { DDRC_FREQ1_INIT3(0), (mr_value[1][0]<<16) | (mr_value[1][1]) }, +// { DDRC_FREQ1_INIT4(0), (mr_value[1][2]<<16) | (mr_value[1][3]) }, +// { DDRC_FREQ1_INIT6(0), (mr_value[1][4]<<16) | (mr_value[1][5]) }, +// { DDRC_FREQ1_INIT7(0), mr_value[1][6] }, + { DDRC_FREQ1_INIT3(0), (0x204 << 16) | 0x104 }, + { DDRC_FREQ1_INIT4(0), (0x1000 << 16) | 0x040 }, + { DDRC_FREQ1_INIT6(0), (0x200 << 16) | 0x200 }, + { DDRC_FREQ1_INIT7(0), 0x014 }, + { DDRC_FREQ1_DRAMTMG0(0), 0x0c0e0604 },/* t_ras_max=9*7.8us, t_ras_min=35ns */ + { DDRC_FREQ1_DRAMTMG1(0), 0x00030314 }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0505040a }, + { DDRC_FREQ1_DRAMTMG3(0), 0x0000400c }, + { DDRC_FREQ1_DRAMTMG4(0), 0x06040307 }, /* tRP=6 --> 7 */ + { DDRC_FREQ1_DRAMTMG5(0), 0x090d0202 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a070008 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x00000d09 }, + { DDRC_FREQ1_DRAMTMG8(0), 0x08084b09 }, + { DDRC_FREQ1_DRAMTMG9(0), 0x00020308 }, + { DDRC_FREQ1_DRAMTMG10(0), 0x000f0d06 }, + { DDRC_FREQ1_DRAMTMG11(0), 0x12060111 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x00000008 }, + { DDRC_FREQ1_DRAMTMG13(0), 0x21000000 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x00c6007d }, + { DDRC_FREQ1_ZQCTL0(0), 0x51000040 }, + { DDRC_FREQ1_DFITMG0(0), 0x03858204 }, + { DDRC_FREQ1_DFITMG1(0), 0x00020103 }, + { DDRC_FREQ1_DFITMG2(0), 0x00000504 }, + { DDRC_FREQ1_DFITMG3(0), 0x00000001 }, + /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */ + /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */ + { DDRC_FREQ1_ODTCFG(0), 0x07000601 }, + + { DDRC_FREQ2_RFSHCTL0(0), 0x0021a0c0 }, + { DDRC_FREQ2_RFSHTMG(0), 0x0006000e },/* tREFI=7.8us */ +// { DDRC_FREQ2_INIT3(0), (mr_value[2][0]<<16) | (mr_value[2][1]) }, +// { DDRC_FREQ2_INIT4(0), (mr_value[2][2]<<16) | (mr_value[2][3]) }, +// { DDRC_FREQ2_INIT6(0), (mr_value[2][4]<<16) | (mr_value[2][5]) }, +// { DDRC_FREQ2_INIT7(0), mr_value[2][6] }, + { DDRC_FREQ2_INIT3(0), (0x204 << 16) | 0x104 }, + { DDRC_FREQ2_INIT4(0), (0x1000 << 16) | 0x40 }, + { DDRC_FREQ2_INIT6(0), (0x200 << 16) | 0x200 }, + { DDRC_FREQ2_INIT7(0), 0x14 }, + { DDRC_FREQ2_DRAMTMG0(0), 0x0c0e0101 },/* t_ras_max=9*7.8us, t_ras_min=35ns */ + { DDRC_FREQ2_DRAMTMG1(0), 0x00030314 }, + { DDRC_FREQ2_DRAMTMG2(0), 0x0505040a }, + { DDRC_FREQ2_DRAMTMG3(0), 0x0000400c }, + { DDRC_FREQ2_DRAMTMG4(0), 0x06040307 }, /* tRP=6 --> 7 */ + { DDRC_FREQ2_DRAMTMG5(0), 0x090d0202 }, + { DDRC_FREQ2_DRAMTMG6(0), 0x0a070008 }, + { DDRC_FREQ2_DRAMTMG7(0), 0x00000d09 }, + { DDRC_FREQ2_DRAMTMG8(0), 0x08084b09 }, + { DDRC_FREQ2_DRAMTMG9(0), 0x00020308 }, + { DDRC_FREQ2_DRAMTMG10(0), 0x000f0d06 }, + { DDRC_FREQ2_DRAMTMG11(0), 0x12060111 }, + { DDRC_FREQ2_DRAMTMG12(0), 0x00000008 }, + { DDRC_FREQ2_DRAMTMG13(0), 0x21000000 }, + { DDRC_FREQ2_DRAMTMG14(0), 0x00000000 }, + { DDRC_FREQ2_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ2_DRAMTMG17(0), 0x00c6007d }, + { DDRC_FREQ2_ZQCTL0(0), 0x51000040 }, + { DDRC_FREQ2_DFITMG0(0), 0x03858204 }, + { DDRC_FREQ2_DFITMG1(0), 0x00020103 }, + { DDRC_FREQ2_DFITMG2(0), 0x00000504 }, + { DDRC_FREQ2_DFITMG3(0), 0x00000001 }, + /* FREQ1: BL8, CL=10, CWL=9, WR_PREAMBLE = 1,RD_PREAMBLE = 1, CRC_MODE = 1 */ + /* wr_odt_delay=DFITMG1.dfi_t_cmd_lat=0 */ + { DDRC_FREQ2_ODTCFG(0), 0x07000601 }, + + /* default start freq point */ + { DDRC_MSTR2(0), 0x0}, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr4_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ + { 0x1015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ + { 0x1105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ + { 0x1115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ + { 0x1205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ + { 0x1215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ + { 0x1305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ + { 0x1315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ + + { 0x11005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p1 */ + { 0x11015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p1 */ + { 0x11105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p1 */ + { 0x11115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p1 */ + { 0x11205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p1 */ + { 0x11215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p1 */ + { 0x11305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p1 */ + { 0x11315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p1 */ + + { 0x21005f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p2 */ + { 0x21015f, 0x2fd }, /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p2 */ + { 0x21105f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p2 */ + { 0x21115f, 0x2fd }, /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p2 */ + { 0x21205f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p2 */ + { 0x21215f, 0x2fd }, /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p2 */ + { 0x21305f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p2 */ + { 0x21315f, 0x2fd }, /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p2 */ + + { 0x55, 0x355 }, /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ + { 0x1055, 0x355 }, /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ + { 0x2055, 0x355 }, /* DWC_DDRPHYA_ANIB2_ATxSlewRate */ + { 0x3055, 0x355 }, /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ + { 0x4055, 0x55 }, /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ + { 0x5055, 0x55 }, /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ + { 0x6055, 0x355 }, /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ + { 0x7055, 0x355 }, /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ + { 0x8055, 0x355 }, /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ + { 0x9055, 0x355 }, /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ + { 0x200c5, 0xa }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ + { 0x1200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p1 */ + { 0x2200c5, 0x7 }, /* DWC_DDRPHYA_MASTER0_PllCtrl2_p2 */ + { 0x2002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ + { 0x12002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p1 */ + { 0x22002e, 0x2 }, /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p2 */ + { 0x20024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ + { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + { 0x120024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p1 */ + { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + { 0x220024, 0x8 }, /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p2 */ + { 0x2003a, 0x2 }, /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + { 0x20056, 0x6 }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ + { 0x120056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p1 */ + { 0x220056, 0xa }, /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p2 */ + { 0x1004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ + { 0x1014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ + { 0x1104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ + { 0x1114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ + { 0x1204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ + { 0x1214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ + { 0x1304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ + { 0x1314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ + { 0x11004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p1 */ + { 0x11014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p1 */ + { 0x11104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p1 */ + { 0x11114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p1 */ + { 0x11204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p1 */ + { 0x11214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p1 */ + { 0x11304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p1 */ + { 0x11314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p1 */ + { 0x21004d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p2 */ + { 0x21014d, 0x1a }, /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p2 */ + { 0x21104d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p2 */ + { 0x21114d, 0x1a }, /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p2 */ + { 0x21204d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p2 */ + { 0x21214d, 0x1a }, /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p2 */ + { 0x21304d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p2 */ + { 0x21314d, 0x1a }, /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p2 */ + { 0x10049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ + { 0x10149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ + { 0x11049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ + { 0x11149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ + { 0x12049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ + { 0x12149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ + { 0x13049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ + { 0x13149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ + { 0x110049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p1 */ + { 0x110149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p1 */ + { 0x111049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p1 */ + { 0x111149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p1 */ + { 0x112049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p1 */ + { 0x112149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p1 */ + { 0x113049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p1 */ + { 0x113149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p1 */ + { 0x210049, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p2 */ + { 0x210149, 0xe38 }, /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p2 */ + { 0x211049, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p2 */ + { 0x211149, 0xe38 }, /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p2 */ + { 0x212049, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p2 */ + { 0x212149, 0xe38 }, /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p2 */ + { 0x213049, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p2 */ + { 0x213149, 0xe38 }, /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p2 */ + { 0x43, 0x63 }, /* DWC_DDRPHYA_ANIB0_ATxImpedance */ + { 0x1043, 0x63 }, /* DWC_DDRPHYA_ANIB1_ATxImpedance */ + { 0x2043, 0x63 }, /* DWC_DDRPHYA_ANIB2_ATxImpedance */ + { 0x3043, 0x63 }, /* DWC_DDRPHYA_ANIB3_ATxImpedance */ + { 0x4043, 0x63 }, /* DWC_DDRPHYA_ANIB4_ATxImpedance */ + { 0x5043, 0x63 }, /* DWC_DDRPHYA_ANIB5_ATxImpedance */ + { 0x6043, 0x63 }, /* DWC_DDRPHYA_ANIB6_ATxImpedance */ + { 0x7043, 0x63 }, /* DWC_DDRPHYA_ANIB7_ATxImpedance */ + { 0x8043, 0x63 }, /* DWC_DDRPHYA_ANIB8_ATxImpedance */ + { 0x9043, 0x63 }, /* DWC_DDRPHYA_ANIB9_ATxImpedance */ + { 0x20018, 0x5 }, /* DWC_DDRPHYA_MASTER0_DfiMode */ + { 0x20075, 0x2 }, /* DWC_DDRPHYA_MASTER0_DfiCAMode */ + { 0x20050, 0x0 }, /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ + { 0x20008, 0x258 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ + { 0x120008, 0x64 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p1 */ + { 0x220008, 0x19 }, /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p2 */ + { 0x20088, 0x9 }, /* DWC_DDRPHYA_MASTER0_CalRate */ + { 0x200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ + { 0x10043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ + { 0x10143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ + { 0x11043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ + { 0x11143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ + { 0x12043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ + { 0x12143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ + { 0x13043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ + { 0x13143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ + { 0x1200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p1 */ + { 0x110043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p1 */ + { 0x110143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p1 */ + { 0x111043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p1 */ + { 0x111143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p1 */ + { 0x112043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p1 */ + { 0x112143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p1 */ + { 0x113043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p1 */ + { 0x113143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p1 */ + { 0x2200b2, 0x268 }, /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p2 */ + { 0x210043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p2 */ + { 0x210143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p2 */ + { 0x211043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p2 */ + { 0x211143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p2 */ + { 0x212043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p2 */ + { 0x212143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p2 */ + { 0x213043, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p2 */ + { 0x213143, 0x5b1 }, /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p2 */ + { 0x2005b, 0x7529 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl */ + { 0x2005c, 0x0 }, /* DWC_DDRPHYA_MASTER0_MemAlertControl2 */ + { 0x200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ + { 0x1200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p1 */ + { 0x2200fa, 0x1 }, /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p2 */ + { 0x20019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ + { 0x120019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p1 */ + { 0x220019, 0x5 }, /* DWC_DDRPHYA_MASTER0_TristateModeCA_p2 */ + { 0x200f0, 0x5665 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ + { 0x200f1, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ + { 0x200f2, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ + { 0x200f3, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ + { 0x200f4, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ + { 0x200f5, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ + { 0x200f6, 0x5555 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ + { 0x200f7, 0xf000 }, /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ + { 0x20025, 0x0 }, /* DWC_DDRPHYA_MASTER0_MasterX4Config */ + { 0x2002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */ + { 0x12002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p1 */ + { 0x22002d, 0x0 }, /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p2 */ + { 0x200c7, 0x21 }, /* DWC_DDRPHYA_MASTER0_PllCtrl1_p0 */ + { 0x200ca, 0x24 }, /* DWC_DDRPHYA_MASTER0_PllTestMode_p0 */ +}; + +/* ddr phy trained CSR */ +struct dram_cfg_param ddr4_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr4_fsp0_cfg[] = { + { 0x20060, 0x2 }, + { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 },/* no addr mirror, 0x200 addr mirror */ + { 0x5400a, 0x0 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0xa34 }, + { 0x54030, 0x105 }, + { 0x54031, 0x1028 }, + { 0x54032, 0x240 }, + { 0x54033, 0x200 }, + { 0x54034, 0x200 }, + { 0x54035, 0x814 }, + { 0x54036, 0x103 }, + { 0x54037, 0x0 }, + { 0x54038, 0x0 }, + { 0x54039, 0x0 }, + { 0x5403a, 0x0 }, + { 0x5403b, 0x0 }, + { 0x5403c, 0x0 }, + { 0x5403d, 0x0 }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr4_fsp1_cfg[] = { + { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x204 }, + { 0x54030, 0x104 }, + { 0x54031, 0x1000 }, + { 0x54032, 0x40 }, + { 0x54033, 0x200 }, + { 0x54034, 0x200 }, + { 0x54035, 0x14 }, + { 0x54036, 0x103 }, + { 0x54037, 0x0 }, + { 0x54038, 0x0 }, + { 0x54039, 0x0 }, + { 0x5403a, 0x0 }, + { 0x5403b, 0x0 }, + { 0x5403c, 0x0 }, + { 0x5403d, 0x0 }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr4_fsp2_cfg[] = { + { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x0 }, + { 0x5400e, 0x0 }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x204 }, + { 0x54030, 0x104 }, + { 0x54031, 0x1000 }, + { 0x54032, 0x40 }, + { 0x54033, 0x200 }, + { 0x54034, 0x200 }, + { 0x54035, 0x14 }, + { 0x54036, 0x103 }, + { 0x54037, 0x0 }, + { 0x54038, 0x0 }, + { 0x54039, 0x0 }, + { 0x5403a, 0x0 }, + { 0x5403b, 0x0 }, + { 0x5403c, 0x0 }, + { 0x5403d, 0x0 }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +}; + +struct dram_cfg_param ddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + { 0x54000, 0x0 }, + { 0x54001, 0x0 }, + { 0x54002, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x0 }, + { 0x54006, 0x25e }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400a, 0x0 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x5400f, 0x0 }, + { 0x54010, 0x0 }, + { 0x54011, 0x0 }, + { 0x54012, 0x1 }, + { 0x5402f, 0xa34 }, + { 0x54030, 0x105 }, + { 0x54031, 0x1028 }, + { 0x54032, 0x240 }, + { 0x54033, 0x200 }, + { 0x54034, 0x200 }, + { 0x54035, 0x814 }, + { 0x54036, 0x103 }, + { 0x54037, 0x0 }, + { 0x54038, 0x0 }, + { 0x54039, 0x0 }, + { 0x5403a, 0x0 }, + { 0x5403b, 0x0 }, + { 0x5403c, 0x0 }, + { 0x5403d, 0x0 }, + { 0x5403e, 0x0 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +}; +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr4_phy_pie[] = { + { 0xd0000, 0x0 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + { 0x90000, 0x10 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + { 0x90001, 0x400 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + { 0x90002, 0x10e }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + { 0x90003, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + { 0x90004, 0x0 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + { 0x90005, 0x8 }, /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + { 0x90029, 0xb }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + { 0x9002a, 0x480 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + { 0x9002b, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + { 0x9002c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + { 0x9002d, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + { 0x9002e, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + { 0x9002f, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + { 0x90030, 0x478 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + { 0x90031, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + { 0x90032, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + { 0x90033, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + { 0x90034, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + { 0x90035, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + { 0x90036, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + { 0x90037, 0x139 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + { 0x90038, 0x44 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + { 0x90039, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + { 0x9003a, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + { 0x9003b, 0x14f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + { 0x9003c, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + { 0x9003d, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + { 0x9003e, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + { 0x9003f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + { 0x90040, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + { 0x90041, 0x4f }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + { 0x90042, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + { 0x90043, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + { 0x90044, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + { 0x90045, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + { 0x90046, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + { 0x90047, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + { 0x90048, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + { 0x90049, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + { 0x9004a, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + { 0x9004b, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + { 0x9004c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + { 0x9004d, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + { 0x9004e, 0x45a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + { 0x9004f, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + { 0x90050, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + { 0x90051, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + { 0x90052, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + { 0x90053, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + { 0x90054, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + { 0x90055, 0x179 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + { 0x90056, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + { 0x90057, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + { 0x90058, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + { 0x90059, 0x40c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + { 0x9005a, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + { 0x9005b, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + { 0x9005c, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + { 0x9005d, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + { 0x9005e, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + { 0x9005f, 0x4040 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + { 0x90060, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + { 0x90061, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + { 0x90062, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + { 0x90063, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + { 0x90064, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + { 0x90065, 0x40 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + { 0x90066, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + { 0x90067, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + { 0x90068, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + { 0x90069, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + { 0x9006a, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + { 0x9006b, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + { 0x9006c, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + { 0x9006d, 0x78 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + { 0x9006e, 0x549 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + { 0x9006f, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + { 0x90070, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + { 0x90071, 0xd49 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + { 0x90072, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + { 0x90073, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + { 0x90074, 0x94a }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + { 0x90075, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + { 0x90076, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + { 0x90077, 0x441 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + { 0x90078, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + { 0x90079, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + { 0x9007a, 0x42 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + { 0x9007b, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + { 0x9007c, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + { 0x9007d, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + { 0x9007e, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + { 0x9007f, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + { 0x90080, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + { 0x90081, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + { 0x90082, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + { 0x90083, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + { 0x90084, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + { 0x90085, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + { 0x90086, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + { 0x90087, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + { 0x90088, 0x149 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + { 0x90089, 0x9 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + { 0x9008a, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + { 0x9008b, 0x159 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + { 0x9008c, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + { 0x9008d, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + { 0x9008e, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + { 0x9008f, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + { 0x90090, 0x3c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + { 0x90091, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + { 0x90092, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + { 0x90093, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + { 0x90094, 0x48 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + { 0x90095, 0x18 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + { 0x90096, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + { 0x90097, 0x58 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + { 0x90098, 0xa }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + { 0x90099, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + { 0x9009a, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + { 0x9009b, 0x2 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + { 0x9009c, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + { 0x9009d, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + { 0x9009e, 0x7 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + { 0x9009f, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + { 0x900a0, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + { 0x900a1, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + { 0x900a2, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + { 0x900a3, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + { 0x900a4, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + { 0x900a5, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + { 0x900a6, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + { 0x900a7, 0x10 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + { 0x900a8, 0x8138 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + { 0x900a9, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + { 0x900aa, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + { 0x900ab, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + { 0x900ac, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + { 0x900ad, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + { 0x900ae, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + { 0x900af, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + { 0x900b0, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + { 0x900b1, 0x448 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + { 0x900b2, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + { 0x900b3, 0xf }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + { 0x900b4, 0x7c0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + { 0x900b5, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + { 0x900b6, 0x47 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + { 0x900b7, 0x630 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + { 0x900b8, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + { 0x900b9, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + { 0x900ba, 0x618 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + { 0x900bb, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + { 0x900bc, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + { 0x900bd, 0xe0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + { 0x900be, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + { 0x900bf, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + { 0x900c0, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + { 0x900c1, 0x109 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + { 0x900c2, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + { 0x900c3, 0x8140 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + { 0x900c4, 0x10c }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + { 0x900c5, 0x0 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + { 0x900c6, 0x1 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + { 0x900c7, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + { 0x900c8, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + { 0x900c9, 0x4 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + { 0x900ca, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + { 0x900cb, 0x8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + { 0x900cc, 0x7c8 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + { 0x900cd, 0x101 }, /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + { 0x90006, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + { 0x90007, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + { 0x90008, 0x8 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + { 0x90009, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + { 0x9000a, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + { 0x9000b, 0x0 }, /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + { 0xd00e7, 0x400 }, /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + { 0x90017, 0x0 }, /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + { 0x90026, 0x2c }, /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + { 0x2000b, 0x4b }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + { 0x2000c, 0x96 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + { 0x2000d, 0x5dc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + { 0x2000e, 0x2c }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + { 0x12000b, 0xc }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p1 */ + { 0x12000c, 0x19 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p1 */ + { 0x12000d, 0xfa }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p1 */ + { 0x12000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p1 */ + { 0x22000b, 0x3 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p2 */ + { 0x22000c, 0x6 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p2 */ + { 0x22000d, 0x3e }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p2 */ + { 0x22000e, 0x10 }, /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p2 */ + { 0x9000c, 0x0 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + { 0x9000d, 0x173 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + { 0x9000e, 0x60 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + { 0x9000f, 0x6110 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + { 0x90010, 0x2152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + { 0x90011, 0xdfbd }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + { 0x90012, 0xffff }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + { 0x90013, 0x6152 }, /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + { 0xc0080, 0x0 }, /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + { 0xd0000, 0x1 }, /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +}; + +struct dram_fsp_msg ddr4_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_cfg), + }, +#if 1 + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr4_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr4_fsp0_2d_cfg), + }, +#endif +}; + +/* ddr4 timing config params on VAL board */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr4_ddrc_cfg), + .ddrphy_cfg = ddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr4_ddrphy_cfg), + .fsp_msg = ddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr4_dram_fsp_msg), + .ddrphy_trained_csr = ddr4_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr4_ddrphy_trained_csr), + .ddrphy_pie = ddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr4_phy_pie), +}; diff --git a/board/freescale/imx8mm_val/imx8mm_val.c b/board/freescale/imx8mm_val/imx8mm_val.c new file mode 100644 index 00000000000..fe07b66df48 --- /dev/null +++ b/board/freescale/imx8mm_val/imx8mm_val.c @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; +#endif + +#ifdef CONFIG_MXC_SPI +#define SPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) +static iomux_v3_cfg_t const ecspi1_pads[] = { + IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(5, 9), "ECSPI1 CS"); + + init_clk_ecspi(0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return IMX_GPIO_NR(5, 9); +} +#endif + +#ifdef CONFIG_NAND_MXS +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MM_PAD_NAND_ALE_RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + init_nand_clk(); +} +#endif + +int board_early_init_f(void) +{ +#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); +#endif + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(1); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL +#define FEC_RST_PAD IMX_GPIO_NR(4, 22) +static iomux_v3_cfg_t const fec1_rst_pads[] = { + IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads, + ARRAY_SIZE(fec1_rst_pads)); + + gpio_request(FEC_RST_PAD, "fec1_rst"); + gpio_direction_output(FEC_RST_PAD, 0); + udelay(500); + gpio_direction_output(FEC_RST_PAD, 1); +} +#endif + +static int setup_fec(void) +{ +#ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL + struct iomuxc_gpr_base_regs *gpr + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + /* + * GPR1 bit 13: + * 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also; + * 0:enet1 rmii clock comes from external phy or osc + */ + + setbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); + return set_clk_enet(ENET_50MHZ); +#else + + struct iomuxc_gpr_base_regs *gpr + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + setup_iomux_fec(); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0); + return set_clk_enet(ENET_125MHZ); +#endif +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifndef CONFIG_TARGET_IMX8MM_DDR3L_VAL + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(1, 0x72); + } else if (port == &port2) { + debug("Setup pd switch on port 2\n"); + return setup_pd_switch(1, 0x73); + } else + return -EINVAL; +} + +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x52, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 9000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +static int setup_typec(void) +{ + int ret; + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } else if (tcpc_pd_sink_check_charging(&port2)) { + /* Disable PD for USB1, since USB2 has priority */ + port1_config.disable_pd = true; + printf("Power supply on USB2\n"); + } + + debug("tcpc_init port 1\n"); + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } else { + if (!port1_config.disable_pd) + printf("Power supply on USB1\n"); + return ret; + } + + return ret; +} +#endif + +#ifdef CONFIG_USB_EHCI_HCD +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; +#ifdef CONFIG_USB_TCPC + struct tcpc_port *port_ptr; +#endif + + debug("board_usb_init %d, type %d\n", index, init); + + imx8m_usb_power(index, true); + +#ifdef CONFIG_USB_TCPC + if (index == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(port_ptr); + else + tcpc_setup_ufp_mode(port_ptr); +#endif + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + debug("board_usb_cleanup %d, type %d\n", index, init); + +#ifdef CONFIG_USB_TCPC + if (init == USB_INIT_HOST) { + if (index == 0) + ret = tcpc_disable_src_vbus(&port1); + else + ret = tcpc_disable_src_vbus(&port2); + } +#endif + + imx8m_usb_power(index, false); + return ret; +} + +#ifdef CONFIG_USB_TCPC +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + struct tcpc_port *port_ptr; + + if (dev_seq(dev) == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + tcpc_setup_ufp_mode(port_ptr); + + ret = tcpc_get_cc_status(port_ptr, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} +#endif +#endif + +int board_init(void) +{ +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "VAL"); + env_set("board_rev", "iMX8MM"); +#endif + return 0; +} diff --git a/board/freescale/imx8mm_val/spl.c b/board/freescale/imx8mm_val/spl.c new file mode 100644 index 00000000000..5a92b951e96 --- /dev/null +++ b/board/freescale/imx8mm_val/spl.c @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018-2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_dram_init(void) +{ + /* ddr train */ + ddr_init(&dram_timing); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MM_PAD_I2C1_SCL_I2C1_SCL | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MM_PAD_I2C1_SDA_I2C1_SDA | PC, + .gpio_mode = IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +/* + * The evk board uses DAT3 to detect CD card plugin, + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd. + */ +static iomux_v3_cfg_t const usdhc2_cd_pad = + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL); + +static iomux_v3_cfg_t const usdhc2_dat3_pad = + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | + MUX_PAD_CTRL(USDHC_PAD_CTRL); + + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 8}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(2); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + imx_iomux_v3_setup_pad(usdhc2_cd_pad); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_direction_input(USDHC2_CD_GPIO); + + /* + * Since it is the DAT3 pin, this pin is pulled to + * low voltage if no card + */ + ret = gpio_get_value(USDHC2_CD_GPIO); + + imx_iomux_v3_setup_pad(usdhc2_dat3_pad); + return ret; + } + + return 1; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + + ret = power_bd71837_init(I2C_PMIC); + if (ret) + printf("power init failed"); + + p = pmic_get("BD71837"); + pmic_probe(p); + + + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(p, BD718XX_PWRONCONFIG1, 0x0); + + /* unlock the PMIC regs */ + pmic_reg_write(p, BD718XX_REGLOCK, 0x1); + + /* increase VDD_SOC to typical value 0.85v before first DRAM access */ + pmic_reg_write(p, BD718XX_BUCK1_VOLT_RUN, 0x0f); + + /* increase VDD_DRAM to 0.9v for 3Ghz DDR */ + pmic_reg_write(p, BD718XX_1ST_NODVS_BUCK_VOLT, 0x2); + +#ifdef CONFIG_TARGET_IMX8MM_DDR4_VAL + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(p, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); +#elif defined(CONFIG_TARGET_IMX8MM_DDR3L_VAL) + /* increase NVCC_DRAM_1V35 to 1.35v for DDR3L */ + pmic_reg_write(p, BD718XX_4TH_NODVS_BUCK_VOLT, 0x37); +#endif + + /* lock the PMIC regs */ + pmic_reg_write(p, BD718XX_REGLOCK, 0x11); + + return 0; +} +#endif + +void spl_board_init(void) +{ +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage to 1.0V for 800M */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8mn_evk/Kconfig b/board/freescale/imx8mn_evk/Kconfig index 048fb7d97f0..135d5433358 100644 --- a/board/freescale/imx8mn_evk/Kconfig +++ b/board/freescale/imx8mn_evk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8MN_DDR4_EVK +if TARGET_IMX8MN_EVK || TARGET_IMX8MN_DDR4_EVK || TARGET_IMX8MN_DDR3_EVK config SYS_BOARD default "imx8mn_evk" @@ -9,6 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mn_evk" +config IMX8MN_LOW_DRIVE_MODE + bool "Enable the low drive mode of iMX8MN on EVK board" + default n + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/imx8mn_evk/Makefile b/board/freescale/imx8mn_evk/Makefile index 9511a70c315..ad3ef8edd64 100644 --- a/board/freescale/imx8mn_evk/Makefile +++ b/board/freescale/imx8mn_evk/Makefile @@ -8,5 +8,12 @@ obj-y += imx8mn_evk.o ifdef CONFIG_SPL_BUILD obj-y += spl.o +ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_ld.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing_ld.o +else +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o +obj-$(CONFIG_IMX8M_DDR3L) += ddr3l_timing.o +endif endif diff --git a/board/freescale/imx8mn_evk/ddr3l_timing.c b/board/freescale/imx8mn_evk/ddr3l_timing.c new file mode 100644 index 00000000000..14d18cb491f --- /dev/null +++ b/board/freescale/imx8mn_evk/ddr3l_timing.c @@ -0,0 +1,944 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + * For imx_v2019.04_5.4.x and above version: + * please replace #include with #include + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x20 }, + { 0x3d400000, 0xa1040001 }, + { 0x3d400064, 0x61008c }, + { 0x3d4000d0, 0xc00200c5 }, + { 0x3d4000d4, 0x1000b }, + { 0x3d4000dc, 0x1d700004 }, + { 0x3d4000e0, 0x180000 }, + { 0x3d4000e4, 0x90000 }, + { 0x3d4000f0, 0x0 }, + { 0x3d4000f4, 0xee5 }, + { 0x3d400100, 0xc101b0e }, + { 0x3d400104, 0x30314 }, + { 0x3d400108, 0x4060509 }, + { 0x3d40010c, 0x2006 }, + { 0x3d400110, 0x6020306 }, + { 0x3d400114, 0x4040302 }, + { 0x3d400120, 0x909 }, + { 0x3d400180, 0x40800020 }, + { 0x3d400184, 0xc350 }, + { 0x3d400190, 0x3868203 }, + { 0x3d400194, 0x20303 }, + { 0x3d4001b4, 0x603 }, + { 0x3d400198, 0x7000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001a0, 0x400018 }, + { 0x3d4001a4, 0x5003c }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400208, 0x0 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400240, 0x600060c }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + { 0x3d400250, 0x7ab50b07 }, + { 0x3d400254, 0x22 }, + { 0x3d40025c, 0x7b00665e }, + { 0x3d400264, 0xb0000040 }, + { 0x3d40026c, 0x50000a0c }, + { 0x3d400300, 0x17 }, + { 0x3d40036c, 0x10000 }, + { 0x3d400404, 0x3051 }, + { 0x3d400408, 0x61d2 }, + { 0x3d400494, 0xe00 }, + { 0x3d400498, 0x7ff }, + { 0x3d40049c, 0xe00 }, + { 0x3d4004a0, 0x7ff }, + { 0x3d402064, 0x28003b }, + { 0x3d4020dc, 0x12200004 }, + { 0x3d4020e0, 0x0 }, + { 0x3d402100, 0x7090b07 }, + { 0x3d402104, 0x20209 }, + { 0x3d402108, 0x3030407 }, + { 0x3d40210c, 0x2006 }, + { 0x3d402110, 0x3020203 }, + { 0x3d402114, 0x3030202 }, + { 0x3d402120, 0x909 }, + { 0x3d402180, 0x40800020 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x20303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xee5 }, + { 0x3d400028, 0x1 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x3ff }, + { 0x1015f, 0x3ff }, + { 0x1105f, 0x3ff }, + { 0x1115f, 0x3ff }, + { 0x11005f, 0x3ff }, + { 0x11015f, 0x3ff }, + { 0x11105f, 0x3ff }, + { 0x11115f, 0x3ff }, + { 0x55, 0x3ff }, + { 0x1055, 0x3ff }, + { 0x2055, 0x3ff }, + { 0x3055, 0x3ff }, + { 0x4055, 0xff }, + { 0x5055, 0xff }, + { 0x6055, 0x3ff }, + { 0x7055, 0x3ff }, + { 0x8055, 0x3ff }, + { 0x9055, 0x3ff }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x7 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x0 }, + { 0x2003a, 0x0 }, + { 0x120024, 0x0 }, + { 0x2003a, 0x0 }, + { 0x20056, 0xa }, + { 0x120056, 0xa }, + { 0x1004d, 0x208 }, + { 0x1014d, 0x208 }, + { 0x1104d, 0x208 }, + { 0x1114d, 0x208 }, + { 0x11004d, 0x208 }, + { 0x11014d, 0x208 }, + { 0x11104d, 0x208 }, + { 0x11114d, 0x208 }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x0 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0xa7 }, + { 0x20088, 0x9 }, + { 0x200b2, 0x32c }, + { 0x10043, 0x581 }, + { 0x10143, 0x581 }, + { 0x11043, 0x581 }, + { 0x11143, 0x581 }, + { 0x1200b2, 0x32c }, + { 0x110043, 0x581 }, + { 0x110143, 0x581 }, + { 0x111043, 0x581 }, + { 0x111143, 0x581 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2,0x0}, + {0x1200b2,0x0}, + {0x2200b2,0x0}, + {0x0200cb,0x0}, + {0x010043,0x0}, + {0x110043,0x0}, + {0x210043,0x0}, + {0x010143,0x0}, + {0x110143,0x0}, + {0x210143,0x0}, + {0x011043,0x0}, + {0x111043,0x0}, + {0x211043,0x0}, + {0x011143,0x0}, + {0x111143,0x0}, + {0x211143,0x0}, + {0x000080,0x0}, + {0x100080,0x0}, + {0x200080,0x0}, + {0x001080,0x0}, + {0x101080,0x0}, + {0x201080,0x0}, + {0x002080,0x0}, + {0x102080,0x0}, + {0x202080,0x0}, + {0x003080,0x0}, + {0x103080,0x0}, + {0x203080,0x0}, + {0x004080,0x0}, + {0x104080,0x0}, + {0x204080,0x0}, + {0x005080,0x0}, + {0x105080,0x0}, + {0x205080,0x0}, + {0x006080,0x0}, + {0x106080,0x0}, + {0x206080,0x0}, + {0x007080,0x0}, + {0x107080,0x0}, + {0x207080,0x0}, + {0x008080,0x0}, + {0x108080,0x0}, + {0x208080,0x0}, + {0x009080,0x0}, + {0x109080,0x0}, + {0x209080,0x0}, + {0x010080,0x0}, + {0x110080,0x0}, + {0x210080,0x0}, + {0x010180,0x0}, + {0x110180,0x0}, + {0x210180,0x0}, + {0x010081,0x0}, + {0x110081,0x0}, + {0x210081,0x0}, + {0x010181,0x0}, + {0x110181,0x0}, + {0x210181,0x0}, + {0x010082,0x0}, + {0x110082,0x0}, + {0x210082,0x0}, + {0x010182,0x0}, + {0x110182,0x0}, + {0x210182,0x0}, + {0x010083,0x0}, + {0x110083,0x0}, + {0x210083,0x0}, + {0x010183,0x0}, + {0x110183,0x0}, + {0x210183,0x0}, + {0x011080,0x0}, + {0x111080,0x0}, + {0x211080,0x0}, + {0x011180,0x0}, + {0x111180,0x0}, + {0x211180,0x0}, + {0x011081,0x0}, + {0x111081,0x0}, + {0x211081,0x0}, + {0x011181,0x0}, + {0x111181,0x0}, + {0x211181,0x0}, + {0x011082,0x0}, + {0x111082,0x0}, + {0x211082,0x0}, + {0x011182,0x0}, + {0x111182,0x0}, + {0x211182,0x0}, + {0x011083,0x0}, + {0x111083,0x0}, + {0x211083,0x0}, + {0x011183,0x0}, + {0x111183,0x0}, + {0x211183,0x0}, + {0x0100d0,0x0}, + {0x1100d0,0x0}, + {0x2100d0,0x0}, + {0x0101d0,0x0}, + {0x1101d0,0x0}, + {0x2101d0,0x0}, + {0x0100d1,0x0}, + {0x1100d1,0x0}, + {0x2100d1,0x0}, + {0x0101d1,0x0}, + {0x1101d1,0x0}, + {0x2101d1,0x0}, + {0x0100d2,0x0}, + {0x1100d2,0x0}, + {0x2100d2,0x0}, + {0x0101d2,0x0}, + {0x1101d2,0x0}, + {0x2101d2,0x0}, + {0x0100d3,0x0}, + {0x1100d3,0x0}, + {0x2100d3,0x0}, + {0x0101d3,0x0}, + {0x1101d3,0x0}, + {0x2101d3,0x0}, + {0x0110d0,0x0}, + {0x1110d0,0x0}, + {0x2110d0,0x0}, + {0x0111d0,0x0}, + {0x1111d0,0x0}, + {0x2111d0,0x0}, + {0x0110d1,0x0}, + {0x1110d1,0x0}, + {0x2110d1,0x0}, + {0x0111d1,0x0}, + {0x1111d1,0x0}, + {0x2111d1,0x0}, + {0x0110d2,0x0}, + {0x1110d2,0x0}, + {0x2110d2,0x0}, + {0x0111d2,0x0}, + {0x1111d2,0x0}, + {0x2111d2,0x0}, + {0x0110d3,0x0}, + {0x1110d3,0x0}, + {0x2110d3,0x0}, + {0x0111d3,0x0}, + {0x1111d3,0x0}, + {0x2111d3,0x0}, + {0x010068,0x0}, + {0x010168,0x0}, + {0x010268,0x0}, + {0x010368,0x0}, + {0x010468,0x0}, + {0x010568,0x0}, + {0x010668,0x0}, + {0x010768,0x0}, + {0x010868,0x0}, + {0x010069,0x0}, + {0x010169,0x0}, + {0x010269,0x0}, + {0x010369,0x0}, + {0x010469,0x0}, + {0x010569,0x0}, + {0x010669,0x0}, + {0x010769,0x0}, + {0x010869,0x0}, + {0x01006a,0x0}, + {0x01016a,0x0}, + {0x01026a,0x0}, + {0x01036a,0x0}, + {0x01046a,0x0}, + {0x01056a,0x0}, + {0x01066a,0x0}, + {0x01076a,0x0}, + {0x01086a,0x0}, + {0x01006b,0x0}, + {0x01016b,0x0}, + {0x01026b,0x0}, + {0x01036b,0x0}, + {0x01046b,0x0}, + {0x01056b,0x0}, + {0x01066b,0x0}, + {0x01076b,0x0}, + {0x01086b,0x0}, + {0x011068,0x0}, + {0x011168,0x0}, + {0x011268,0x0}, + {0x011368,0x0}, + {0x011468,0x0}, + {0x011568,0x0}, + {0x011668,0x0}, + {0x011768,0x0}, + {0x011868,0x0}, + {0x011069,0x0}, + {0x011169,0x0}, + {0x011269,0x0}, + {0x011369,0x0}, + {0x011469,0x0}, + {0x011569,0x0}, + {0x011669,0x0}, + {0x011769,0x0}, + {0x011869,0x0}, + {0x01106a,0x0}, + {0x01116a,0x0}, + {0x01126a,0x0}, + {0x01136a,0x0}, + {0x01146a,0x0}, + {0x01156a,0x0}, + {0x01166a,0x0}, + {0x01176a,0x0}, + {0x01186a,0x0}, + {0x01106b,0x0}, + {0x01116b,0x0}, + {0x01126b,0x0}, + {0x01136b,0x0}, + {0x01146b,0x0}, + {0x01156b,0x0}, + {0x01166b,0x0}, + {0x01176b,0x0}, + {0x01186b,0x0}, + {0x01008c,0x0}, + {0x11008c,0x0}, + {0x21008c,0x0}, + {0x01018c,0x0}, + {0x11018c,0x0}, + {0x21018c,0x0}, + {0x01008d,0x0}, + {0x11008d,0x0}, + {0x21008d,0x0}, + {0x01018d,0x0}, + {0x11018d,0x0}, + {0x21018d,0x0}, + {0x01008e,0x0}, + {0x11008e,0x0}, + {0x21008e,0x0}, + {0x01018e,0x0}, + {0x11018e,0x0}, + {0x21018e,0x0}, + {0x01008f,0x0}, + {0x11008f,0x0}, + {0x21008f,0x0}, + {0x01018f,0x0}, + {0x11018f,0x0}, + {0x21018f,0x0}, + {0x01108c,0x0}, + {0x11108c,0x0}, + {0x21108c,0x0}, + {0x01118c,0x0}, + {0x11118c,0x0}, + {0x21118c,0x0}, + {0x01108d,0x0}, + {0x11108d,0x0}, + {0x21108d,0x0}, + {0x01118d,0x0}, + {0x11118d,0x0}, + {0x21118d,0x0}, + {0x01108e,0x0}, + {0x11108e,0x0}, + {0x21108e,0x0}, + {0x01118e,0x0}, + {0x11118e,0x0}, + {0x21118e,0x0}, + {0x01108f,0x0}, + {0x11108f,0x0}, + {0x21108f,0x0}, + {0x01118f,0x0}, + {0x11118f,0x0}, + {0x21118f,0x0}, + {0x0100c0,0x0}, + {0x1100c0,0x0}, + {0x2100c0,0x0}, + {0x0101c0,0x0}, + {0x1101c0,0x0}, + {0x2101c0,0x0}, + {0x0102c0,0x0}, + {0x1102c0,0x0}, + {0x2102c0,0x0}, + {0x0103c0,0x0}, + {0x1103c0,0x0}, + {0x2103c0,0x0}, + {0x0104c0,0x0}, + {0x1104c0,0x0}, + {0x2104c0,0x0}, + {0x0105c0,0x0}, + {0x1105c0,0x0}, + {0x2105c0,0x0}, + {0x0106c0,0x0}, + {0x1106c0,0x0}, + {0x2106c0,0x0}, + {0x0107c0,0x0}, + {0x1107c0,0x0}, + {0x2107c0,0x0}, + {0x0108c0,0x0}, + {0x1108c0,0x0}, + {0x2108c0,0x0}, + {0x0100c1,0x0}, + {0x1100c1,0x0}, + {0x2100c1,0x0}, + {0x0101c1,0x0}, + {0x1101c1,0x0}, + {0x2101c1,0x0}, + {0x0102c1,0x0}, + {0x1102c1,0x0}, + {0x2102c1,0x0}, + {0x0103c1,0x0}, + {0x1103c1,0x0}, + {0x2103c1,0x0}, + {0x0104c1,0x0}, + {0x1104c1,0x0}, + {0x2104c1,0x0}, + {0x0105c1,0x0}, + {0x1105c1,0x0}, + {0x2105c1,0x0}, + {0x0106c1,0x0}, + {0x1106c1,0x0}, + {0x2106c1,0x0}, + {0x0107c1,0x0}, + {0x1107c1,0x0}, + {0x2107c1,0x0}, + {0x0108c1,0x0}, + {0x1108c1,0x0}, + {0x2108c1,0x0}, + {0x0100c2,0x0}, + {0x1100c2,0x0}, + {0x2100c2,0x0}, + {0x0101c2,0x0}, + {0x1101c2,0x0}, + {0x2101c2,0x0}, + {0x0102c2,0x0}, + {0x1102c2,0x0}, + {0x2102c2,0x0}, + {0x0103c2,0x0}, + {0x1103c2,0x0}, + {0x2103c2,0x0}, + {0x0104c2,0x0}, + {0x1104c2,0x0}, + {0x2104c2,0x0}, + {0x0105c2,0x0}, + {0x1105c2,0x0}, + {0x2105c2,0x0}, + {0x0106c2,0x0}, + {0x1106c2,0x0}, + {0x2106c2,0x0}, + {0x0107c2,0x0}, + {0x1107c2,0x0}, + {0x2107c2,0x0}, + {0x0108c2,0x0}, + {0x1108c2,0x0}, + {0x2108c2,0x0}, + {0x0100c3,0x0}, + {0x1100c3,0x0}, + {0x2100c3,0x0}, + {0x0101c3,0x0}, + {0x1101c3,0x0}, + {0x2101c3,0x0}, + {0x0102c3,0x0}, + {0x1102c3,0x0}, + {0x2102c3,0x0}, + {0x0103c3,0x0}, + {0x1103c3,0x0}, + {0x2103c3,0x0}, + {0x0104c3,0x0}, + {0x1104c3,0x0}, + {0x2104c3,0x0}, + {0x0105c3,0x0}, + {0x1105c3,0x0}, + {0x2105c3,0x0}, + {0x0106c3,0x0}, + {0x1106c3,0x0}, + {0x2106c3,0x0}, + {0x0107c3,0x0}, + {0x1107c3,0x0}, + {0x2107c3,0x0}, + {0x0108c3,0x0}, + {0x1108c3,0x0}, + {0x2108c3,0x0}, + {0x0110c0,0x0}, + {0x1110c0,0x0}, + {0x2110c0,0x0}, + {0x0111c0,0x0}, + {0x1111c0,0x0}, + {0x2111c0,0x0}, + {0x0112c0,0x0}, + {0x1112c0,0x0}, + {0x2112c0,0x0}, + {0x0113c0,0x0}, + {0x1113c0,0x0}, + {0x2113c0,0x0}, + {0x0114c0,0x0}, + {0x1114c0,0x0}, + {0x2114c0,0x0}, + {0x0115c0,0x0}, + {0x1115c0,0x0}, + {0x2115c0,0x0}, + {0x0116c0,0x0}, + {0x1116c0,0x0}, + {0x2116c0,0x0}, + {0x0117c0,0x0}, + {0x1117c0,0x0}, + {0x2117c0,0x0}, + {0x0118c0,0x0}, + {0x1118c0,0x0}, + {0x2118c0,0x0}, + {0x0110c1,0x0}, + {0x1110c1,0x0}, + {0x2110c1,0x0}, + {0x0111c1,0x0}, + {0x1111c1,0x0}, + {0x2111c1,0x0}, + {0x0112c1,0x0}, + {0x1112c1,0x0}, + {0x2112c1,0x0}, + {0x0113c1,0x0}, + {0x1113c1,0x0}, + {0x2113c1,0x0}, + {0x0114c1,0x0}, + {0x1114c1,0x0}, + {0x2114c1,0x0}, + {0x0115c1,0x0}, + {0x1115c1,0x0}, + {0x2115c1,0x0}, + {0x0116c1,0x0}, + {0x1116c1,0x0}, + {0x2116c1,0x0}, + {0x0117c1,0x0}, + {0x1117c1,0x0}, + {0x2117c1,0x0}, + {0x0118c1,0x0}, + {0x1118c1,0x0}, + {0x2118c1,0x0}, + {0x0110c2,0x0}, + {0x1110c2,0x0}, + {0x2110c2,0x0}, + {0x0111c2,0x0}, + {0x1111c2,0x0}, + {0x2111c2,0x0}, + {0x0112c2,0x0}, + {0x1112c2,0x0}, + {0x2112c2,0x0}, + {0x0113c2,0x0}, + {0x1113c2,0x0}, + {0x2113c2,0x0}, + {0x0114c2,0x0}, + {0x1114c2,0x0}, + {0x2114c2,0x0}, + {0x0115c2,0x0}, + {0x1115c2,0x0}, + {0x2115c2,0x0}, + {0x0116c2,0x0}, + {0x1116c2,0x0}, + {0x2116c2,0x0}, + {0x0117c2,0x0}, + {0x1117c2,0x0}, + {0x2117c2,0x0}, + {0x0118c2,0x0}, + {0x1118c2,0x0}, + {0x2118c2,0x0}, + {0x0110c3,0x0}, + {0x1110c3,0x0}, + {0x2110c3,0x0}, + {0x0111c3,0x0}, + {0x1111c3,0x0}, + {0x2111c3,0x0}, + {0x0112c3,0x0}, + {0x1112c3,0x0}, + {0x2112c3,0x0}, + {0x0113c3,0x0}, + {0x1113c3,0x0}, + {0x2113c3,0x0}, + {0x0114c3,0x0}, + {0x1114c3,0x0}, + {0x2114c3,0x0}, + {0x0115c3,0x0}, + {0x1115c3,0x0}, + {0x2115c3,0x0}, + {0x0116c3,0x0}, + {0x1116c3,0x0}, + {0x2116c3,0x0}, + {0x0117c3,0x0}, + {0x1117c3,0x0}, + {0x2117c3,0x0}, + {0x0118c3,0x0}, + {0x1118c3,0x0}, + {0x2118c3,0x0}, + {0x010020,0x0}, + {0x110020,0x0}, + {0x210020,0x0}, + {0x011020,0x0}, + {0x111020,0x0}, + {0x211020,0x0}, + {0x02007d,0x0}, + {0x12007d,0x0}, + {0x22007d,0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x283c }, + { 0x54006, 0x140 }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x1d70 }, + { 0x54030, 0x4 }, + { 0x54031, 0x18 }, + { 0x5403a, 0x1323 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x29c }, + { 0x54004, 0x2 }, + { 0x54005, 0x283c }, + { 0x54006, 0x140 }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x1220 }, + { 0x54030, 0x4 }, + { 0x5403a, 0x1323 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x26 }, + { 0x12000d, 0x1a1 }, + { 0x12000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 667, }, +}; + diff --git a/board/freescale/imx8mn_evk/ddr4_timing.c b/board/freescale/imx8mn_evk/ddr4_timing.c index cfd193a78da..84114a3e8aa 100644 --- a/board/freescale/imx8mn_evk/ddr4_timing.c +++ b/board/freescale/imx8mn_evk/ddr4_timing.c @@ -4,118 +4,71 @@ * SPDX-License-Identifier: GPL-2.0+ * * Generated code from MX8M_DDR_tool - * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga */ #include #include struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x3d400000, 0x81040010}, - {0x3d400030, 0x00000020}, - {0x3d400034, 0x00221306}, - {0x3d400050, 0x00210070}, - {0x3d400054, 0x00010008}, - {0x3d400060, 0x00000000}, - {0x3d400064, 0x0092014a}, - {0x3d4000c0, 0x00000000}, - {0x3d4000c4, 0x00001000}, - {0x3d4000d0, 0xc0030126}, - {0x3d4000d4, 0x00770000}, - {0x3d4000dc, 0x08340105}, - {0x3d4000e0, 0x00180200}, - {0x3d4000e4, 0x00110000}, - {0x3d4000e8, 0x02000740}, - {0x3d4000ec, 0x00000850}, - {0x3d4000f4, 0x00000ec7}, - {0x3d400100, 0x11122914}, - {0x3d400104, 0x0004051c}, - {0x3d400108, 0x0608050d}, - {0x3d40010c, 0x0000400c}, - {0x3d400110, 0x08030409}, - {0x3d400114, 0x06060403}, - {0x3d40011c, 0x00000606}, - {0x3d400120, 0x07070d0c}, - {0x3d400124, 0x0002040a}, - {0x3d40012c, 0x1809010e}, - {0x3d400130, 0x00000008}, - {0x3d40013c, 0x00000000}, - {0x3d400180, 0x01000040}, - {0x3d400184, 0x0000493e}, - {0x3d400190, 0x038b8207}, - {0x3d400194, 0x02020303}, - {0x3d400198, 0x07f04011}, - {0x3d40019c, 0x000000b0}, - {0x3d4001a0, 0xe0400018}, - {0x3d4001a4, 0x0048005a}, - {0x3d4001a8, 0x80000000}, - {0x3d4001b0, 0x00000001}, - {0x3d4001b4, 0x00000b07}, - {0x3d4001b8, 0x00000004}, - {0x3d4001c0, 0x00000001}, - {0x3d4001c4, 0x00000000}, - {0x3d400240, 0x06000610}, - {0x3d400244, 0x00001323}, - {0x3d400200, 0x00003f1f}, - {0x3d400204, 0x003f0909}, - {0x3d400208, 0x01010100}, - {0x3d40020c, 0x01010101}, - {0x3d400210, 0x00001f1f}, - {0x3d400214, 0x07070707}, - {0x3d400218, 0x07070707}, - {0x3d40021c, 0x00000f07}, - {0x3d400220, 0x00003f01}, - {0x3d402050, 0x00210070}, - {0x3d402064, 0x00180037}, - {0x3d4020dc, 0x00000105}, - {0x3d4020e0, 0x00000000}, - {0x3d4020e8, 0x02000740}, - {0x3d4020ec, 0x00000050}, - {0x3d402100, 0x08030604}, - {0x3d402104, 0x00020205}, - {0x3d402108, 0x05050309}, - {0x3d40210c, 0x0000400c}, - {0x3d402110, 0x02030202}, - {0x3d402114, 0x03030202}, - {0x3d402118, 0x0a070008}, - {0x3d40211c, 0x00000d09}, - {0x3d402120, 0x08084b09}, - {0x3d402124, 0x00020308}, - {0x3d402128, 0x000f0d06}, - {0x3d40212c, 0x12060111}, - {0x3d402130, 0x00000008}, - {0x3d40213c, 0x00000000}, - {0x3d402180, 0x01000040}, - {0x3d402190, 0x03848204}, - {0x3d402194, 0x02020303}, - {0x3d4021b4, 0x00000404}, - {0x3d4021b8, 0x00000004}, - {0x3d402240, 0x07000600}, - {0x3d403050, 0x00210070}, - {0x3d403064, 0x0006000d}, - {0x3d4030dc, 0x00000105}, - {0x3d4030e0, 0x00000000}, - {0x3d4030e8, 0x02000740}, - {0x3d4030ec, 0x00000050}, - {0x3d403100, 0x07010101}, - {0x3d403104, 0x00020202}, - {0x3d403108, 0x05050309}, - {0x3d40310c, 0x0000400c}, - {0x3d403110, 0x01030201}, - {0x3d403114, 0x03030202}, - {0x3d40311c, 0x00000303}, - {0x3d403120, 0x02020d02}, - {0x3d403124, 0x00020208}, - {0x3d403128, 0x000f0d06}, - {0x3d40312c, 0x0e02010e}, - {0x3d403130, 0x00000008}, - {0x3d40313c, 0x00000000}, - {0x3d403180, 0x01000040}, - {0x3d403190, 0x03848204}, - {0x3d403194, 0x02020303}, - {0x3d4031b4, 0x00000404}, - {0x3d4031b8, 0x00000004}, - {0x3d403240, 0x07000600}, + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x92014a }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340105 }, + { 0x3d4000e0, 0x180200 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x810 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x7070d0c }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1809010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, /* performance setting */ { 0x3d400250, 0x00001f05 }, @@ -126,141 +79,136 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400498, 0x03ff0000 }, { 0x3d40049c, 0x01000e00 }, { 0x3d4004a0, 0x03ff0000 }, + + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3848204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x404 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000600 }, + { 0x3d4020f4, 0xec7 }, }; /* PHY Initialize Configuration */ struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x0001005f, 0x000002fd}, - {0x0001015f, 0x000002fd}, - {0x0001105f, 0x000002fd}, - {0x0001115f, 0x000002fd}, - {0x0011005f, 0x000002fd}, - {0x0011015f, 0x000002fd}, - {0x0011105f, 0x000002fd}, - {0x0011115f, 0x000002fd}, - {0x0021005f, 0x000002fd}, - {0x0021015f, 0x000002fd}, - {0x0021105f, 0x000002fd}, - {0x0021115f, 0x000002fd}, - {0x00000055, 0x00000355}, - {0x00001055, 0x00000355}, - {0x00002055, 0x00000355}, - {0x00003055, 0x00000355}, - {0x00004055, 0x00000055}, - {0x00005055, 0x00000055}, - {0x00006055, 0x00000355}, - {0x00007055, 0x00000355}, - {0x00008055, 0x00000355}, - {0x00009055, 0x00000355}, - {0x000200c5, 0x0000000a}, - {0x001200c5, 0x00000007}, - {0x002200c5, 0x00000007}, - {0x0002002e, 0x00000002}, - {0x0012002e, 0x00000002}, - {0x0022002e, 0x00000002}, - {0x00020024, 0x00000008}, - {0x0002003a, 0x00000002}, - {0x0002007d, 0x00000212}, - {0x0002007c, 0x00000061}, - {0x00120024, 0x00000008}, - {0x0002003a, 0x00000002}, - {0x0012007d, 0x00000212}, - {0x0012007c, 0x00000061}, - {0x00220024, 0x00000008}, - {0x0002003a, 0x00000002}, - {0x0022007d, 0x00000212}, - {0x0022007c, 0x00000061}, - {0x00020056, 0x00000006}, - {0x00120056, 0x0000000a}, - {0x00220056, 0x0000000a}, - {0x0001004d, 0x0000001a}, - {0x0001014d, 0x0000001a}, - {0x0001104d, 0x0000001a}, - {0x0001114d, 0x0000001a}, - {0x0011004d, 0x0000001a}, - {0x0011014d, 0x0000001a}, - {0x0011104d, 0x0000001a}, - {0x0011114d, 0x0000001a}, - {0x0021004d, 0x0000001a}, - {0x0021014d, 0x0000001a}, - {0x0021104d, 0x0000001a}, - {0x0021114d, 0x0000001a}, - {0x00010049, 0x00000e38}, - {0x00010149, 0x00000e38}, - {0x00011049, 0x00000e38}, - {0x00011149, 0x00000e38}, - {0x00110049, 0x00000e38}, - {0x00110149, 0x00000e38}, - {0x00111049, 0x00000e38}, - {0x00111149, 0x00000e38}, - {0x00210049, 0x00000e38}, - {0x00210149, 0x00000e38}, - {0x00211049, 0x00000e38}, - {0x00211149, 0x00000e38}, - {0x00000043, 0x00000063}, - {0x00001043, 0x00000063}, - {0x00002043, 0x00000063}, - {0x00003043, 0x00000063}, - {0x00004043, 0x00000063}, - {0x00005043, 0x00000063}, - {0x00006043, 0x00000063}, - {0x00007043, 0x00000063}, - {0x00008043, 0x00000063}, - {0x00009043, 0x00000063}, - {0x00020018, 0x00000001}, - {0x00020075, 0x00000002}, - {0x00020050, 0x00000000}, - {0x00020008, 0x00000258}, - {0x00120008, 0x00000064}, - {0x00220008, 0x00000019}, - {0x00020088, 0x00000009}, - {0x000200b2, 0x00000268}, - {0x00010043, 0x000005b1}, - {0x00010143, 0x000005b1}, - {0x00011043, 0x000005b1}, - {0x00011143, 0x000005b1}, - {0x001200b2, 0x00000268}, - {0x00110043, 0x000005b1}, - {0x00110143, 0x000005b1}, - {0x00111043, 0x000005b1}, - {0x00111143, 0x000005b1}, - {0x002200b2, 0x00000268}, - {0x00210043, 0x000005b1}, - {0x00210143, 0x000005b1}, - {0x00211043, 0x000005b1}, - {0x00211143, 0x000005b1}, - {0x0002005b, 0x00007529}, - {0x0002005c, 0x00000000}, - {0x000200fa, 0x00000001}, - {0x001200fa, 0x00000001}, - {0x002200fa, 0x00000001}, - {0x00020019, 0x00000005}, - {0x00120019, 0x00000005}, - {0x00220019, 0x00000005}, - {0x000200f0, 0x00005665}, - {0x000200f1, 0x00005555}, - {0x000200f2, 0x00005555}, - {0x000200f3, 0x00005555}, - {0x000200f4, 0x00005555}, - {0x000200f5, 0x00005555}, - {0x000200f6, 0x00005555}, - {0x000200f7, 0x0000f000}, - {0x0001004a, 0x00000500}, - {0x0001104a, 0x00000500}, - {0x00020025, 0x00000000}, - {0x0002002d, 0x00000000}, - {0x0012002d, 0x00000000}, - {0x0022002d, 0x00000000}, - {0x0002002c, 0x00000000}, - {0x000200c7, 0x00000021}, - {0x000200ca, 0x00000024}, - {0x000200cc, 0x000001f7}, - {0x001200c7, 0x00000021}, - {0x001200ca, 0x00000024}, - {0x001200cc, 0x000001f7}, - {0x002200c7, 0x00000021}, - {0x002200ca, 0x00000024}, - {0x002200cc, 0x000001f7}, + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xa }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, }; /* ddr phy trained csr */ @@ -792,378 +740,280 @@ struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00020060, 0x00000002}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000000}, - {0x00054003, 0x00000960}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x0000025e}, - {0x00054007, 0x00001000}, - {0x00054008, 0x00000101}, - {0x00054009, 0x00000000}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x0000031f}, - {0x0005400c, 0x000000c8}, - {0x0005400d, 0x00000100}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000000}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000001}, - {0x0005402f, 0x00000834}, - {0x00054030, 0x00000105}, - {0x00054031, 0x00000018}, - {0x00054032, 0x00000200}, - {0x00054033, 0x00000200}, - {0x00054034, 0x00000740}, - {0x00054035, 0x00000850}, - {0x00054036, 0x00000103}, - {0x00054037, 0x00000000}, - {0x00054038, 0x00000000}, - {0x00054039, 0x00000000}, - {0x0005403a, 0x00000000}, - {0x0005403b, 0x00000000}, - {0x0005403c, 0x00000000}, - {0x0005403d, 0x00000000}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00001221}, - {0x000541fc, 0x00000100}, - {0x000d0000, 0x00000001}, + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, }; + /* P1 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp1_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000101}, - {0x00054003, 0x00000190}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x0000025e}, - {0x00054007, 0x00001000}, - {0x00054008, 0x00000101}, - {0x00054009, 0x00000000}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x0000021f}, - {0x0005400c, 0x000000c8}, - {0x0005400d, 0x00000100}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000000}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000001}, - {0x0005402f, 0x00000000}, - {0x00054030, 0x00000105}, - {0x00054031, 0x00000000}, - {0x00054032, 0x00000000}, - {0x00054033, 0x00000200}, - {0x00054034, 0x00000740}, - {0x00054035, 0x00000050}, - {0x00054036, 0x00000103}, - {0x00054037, 0x00000000}, - {0x00054038, 0x00000000}, - {0x00054039, 0x00000000}, - {0x0005403a, 0x00000000}, - {0x0005403b, 0x00000000}, - {0x0005403c, 0x00000000}, - {0x0005403d, 0x00000000}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00001221}, - {0x000541fc, 0x00000100}, - {0x000d0000, 0x00000001}, + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, }; -/* P2 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000102}, - {0x00054003, 0x00000064}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x0000025e}, - {0x00054007, 0x00001000}, - {0x00054008, 0x00000101}, - {0x00054009, 0x00000000}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x0000021f}, - {0x0005400c, 0x000000c8}, - {0x0005400d, 0x00000100}, - {0x0005400e, 0x00000000}, - {0x0005400f, 0x00000000}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000001}, - {0x0005402f, 0x00000000}, - {0x00054030, 0x00000105}, - {0x00054031, 0x00000000}, - {0x00054032, 0x00000000}, - {0x00054033, 0x00000200}, - {0x00054034, 0x00000740}, - {0x00054035, 0x00000050}, - {0x00054036, 0x00000103}, - {0x00054037, 0x00000000}, - {0x00054038, 0x00000000}, - {0x00054039, 0x00000000}, - {0x0005403a, 0x00000000}, - {0x0005403b, 0x00000000}, - {0x0005403c, 0x00000000}, - {0x0005403d, 0x00000000}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00001221}, - {0x000541fc, 0x00000100}, - {0x000d0000, 0x00000001}, -}; /* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0x000d0000, 0x00000000}, - {0x00054000, 0x00000000}, - {0x00054001, 0x00000000}, - {0x00054002, 0x00000000}, - {0x00054003, 0x00000960}, - {0x00054004, 0x00000002}, - {0x00054005, 0x00000000}, - {0x00054006, 0x0000025e}, - {0x00054007, 0x00001000}, - {0x00054008, 0x00000101}, - {0x00054009, 0x00000000}, - {0x0005400a, 0x00000000}, - {0x0005400b, 0x00000061}, - {0x0005400c, 0x000000c8}, - {0x0005400d, 0x00000100}, - {0x0005400e, 0x00001f7f}, - {0x0005400f, 0x00000000}, - {0x00054010, 0x00000000}, - {0x00054011, 0x00000000}, - {0x00054012, 0x00000001}, - {0x0005402f, 0x00000834}, - {0x00054030, 0x00000105}, - {0x00054031, 0x00000018}, - {0x00054032, 0x00000200}, - {0x00054033, 0x00000200}, - {0x00054034, 0x00000740}, - {0x00054035, 0x00000850}, - {0x00054036, 0x00000103}, - {0x00054037, 0x00000000}, - {0x00054038, 0x00000000}, - {0x00054039, 0x00000000}, - {0x0005403a, 0x00000000}, - {0x0005403b, 0x00000000}, - {0x0005403c, 0x00000000}, - {0x0005403d, 0x00000000}, - {0x0005403e, 0x00000000}, - {0x0005403f, 0x00001221}, - {0x000541fc, 0x00000100}, - {0x000d0000, 0x00000001}, + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x105 }, + { 0x54031, 0x18 }, + { 0x54032, 0x200 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x810 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, }; /* DRAM PHY init engine image */ struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x2}, - {0x90033, 0x10}, - {0x90034, 0x139}, - {0x90035, 0xb}, - {0x90036, 0x7c0}, - {0x90037, 0x139}, - {0x90038, 0x44}, - {0x90039, 0x633}, - {0x9003a, 0x159}, - {0x9003b, 0x14f}, - {0x9003c, 0x630}, - {0x9003d, 0x159}, - {0x9003e, 0x47}, - {0x9003f, 0x633}, - {0x90040, 0x149}, - {0x90041, 0x4f}, - {0x90042, 0x633}, - {0x90043, 0x179}, - {0x90044, 0x8}, - {0x90045, 0xe0}, - {0x90046, 0x109}, - {0x90047, 0x0}, - {0x90048, 0x7c8}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x1}, - {0x9004c, 0x8}, - {0x9004d, 0x0}, - {0x9004e, 0x45a}, - {0x9004f, 0x9}, - {0x90050, 0x0}, - {0x90051, 0x448}, - {0x90052, 0x109}, - {0x90053, 0x40}, - {0x90054, 0x633}, - {0x90055, 0x179}, - {0x90056, 0x1}, - {0x90057, 0x618}, - {0x90058, 0x109}, - {0x90059, 0x40c0}, - {0x9005a, 0x633}, - {0x9005b, 0x149}, - {0x9005c, 0x8}, - {0x9005d, 0x4}, - {0x9005e, 0x48}, - {0x9005f, 0x4040}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x0}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x40}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x10}, - {0x90069, 0x4}, - {0x9006a, 0x18}, - {0x9006b, 0x0}, - {0x9006c, 0x4}, - {0x9006d, 0x78}, - {0x9006e, 0x549}, - {0x9006f, 0x633}, - {0x90070, 0x159}, - {0x90071, 0xd49}, - {0x90072, 0x633}, - {0x90073, 0x159}, - {0x90074, 0x94a}, - {0x90075, 0x633}, - {0x90076, 0x159}, - {0x90077, 0x441}, - {0x90078, 0x633}, - {0x90079, 0x149}, - {0x9007a, 0x42}, - {0x9007b, 0x633}, - {0x9007c, 0x149}, - {0x9007d, 0x1}, - {0x9007e, 0x633}, - {0x9007f, 0x149}, - {0x90080, 0x0}, - {0x90081, 0xe0}, - {0x90082, 0x109}, - {0x90083, 0xa}, - {0x90084, 0x10}, - {0x90085, 0x109}, - {0x90086, 0x9}, - {0x90087, 0x3c0}, - {0x90088, 0x149}, - {0x90089, 0x9}, - {0x9008a, 0x3c0}, - {0x9008b, 0x159}, - {0x9008c, 0x18}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x0}, - {0x90090, 0x3c0}, - {0x90091, 0x109}, - {0x90092, 0x18}, - {0x90093, 0x4}, - {0x90094, 0x48}, - {0x90095, 0x18}, - {0x90096, 0x4}, - {0x90097, 0x58}, - {0x90098, 0xb}, - {0x90099, 0x10}, - {0x9009a, 0x109}, - {0x9009b, 0x1}, - {0x9009c, 0x10}, - {0x9009d, 0x109}, - {0x9009e, 0x5}, - {0x9009f, 0x7c0}, - {0x900a0, 0x109}, - {0x900a1, 0x0}, - {0x900a2, 0x8140}, - {0x900a3, 0x10c}, - {0x900a4, 0x10}, - {0x900a5, 0x8138}, - {0x900a6, 0x10c}, - {0x900a7, 0x8}, - {0x900a8, 0x7c8}, - {0x900a9, 0x101}, - {0x900aa, 0x8}, - {0x900ab, 0x448}, - {0x900ac, 0x109}, - {0x900ad, 0xf}, - {0x900ae, 0x7c0}, - {0x900af, 0x109}, - {0x900b0, 0x47}, - {0x900b1, 0x630}, - {0x900b2, 0x109}, - {0x900b3, 0x8}, - {0x900b4, 0x618}, - {0x900b5, 0x109}, - {0x900b6, 0x8}, - {0x900b7, 0xe0}, - {0x900b8, 0x109}, - {0x900b9, 0x0}, - {0x900ba, 0x7c8}, - {0x900bb, 0x109}, - {0x900bc, 0x8}, - {0x900bd, 0x8140}, - {0x900be, 0x10c}, - {0x900bf, 0x0}, - {0x900c0, 0x1}, - {0x900c1, 0x8}, - {0x900c2, 0x8}, - {0x900c3, 0x4}, - {0x900c4, 0x8}, - {0x900c5, 0x8}, - {0x900c6, 0x7c8}, - {0x900c7, 0x101}, - {0x90006, 0x0}, - {0x90007, 0x0}, - {0x90008, 0x8}, - {0x90009, 0x0}, - {0x9000a, 0x0}, - {0x9000b, 0x0}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x90026, 0x2b}, - {0x2000b, 0x4b}, - {0x2000c, 0x96}, - {0x2000d, 0x5dc}, - {0x2000e, 0x2c}, - {0x12000b, 0xc}, - {0x12000c, 0x16}, - {0x12000d, 0xfa}, - {0x12000e, 0x10}, - {0x22000b, 0x3}, - {0x22000c, 0x3}, - {0x22000d, 0x3e}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0xffff}, - {0x90013, 0x6152}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } }; struct dram_fsp_msg ddr_dram_fsp_msg[] = { @@ -1175,19 +1025,12 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), }, { - /* P1 400mts 1D */ - .drate = 400, + /* P1 1066mts 1D */ + .drate = 1066, .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp1_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, { /* P0 2400mts 2D */ .drate = 2400, @@ -1209,6 +1052,6 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 2400, 400, 100,}, + .fsp_table = { 2400, 1066, }, }; diff --git a/board/freescale/imx8mn_evk/ddr4_timing_ld.c b/board/freescale/imx8mn_evk/ddr4_timing_ld.c new file mode 100644 index 00000000000..0fba33a2348 --- /dev/null +++ b/board/freescale/imx8mn_evk/ddr4_timing_ld.c @@ -0,0 +1,1057 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0x20 }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0x6100dc }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc00200c5 }, + { 0x3d4000d4, 0x500000 }, + { 0x3d4000dc, 0x2340105 }, + { 0x3d4000e0, 0x0 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x410 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0xd0c1b0d }, + { 0x3d400104, 0x30313 }, + { 0x3d400108, 0x508060a }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x6030306 }, + { 0x3d400114, 0x4040302 }, + { 0x3d40011c, 0x404 }, + { 0x3d400120, 0x5050d08 }, + { 0x3d400124, 0x20308 }, + { 0x3d40012c, 0x1406010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x30d4 }, + { 0x3d400190, 0x38b8204 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb04 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f1f }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x600061c }, + { 0x3d400244, 0x1323 }, + { 0x3d400400, 0x100 }, + { 0x3d400250, 0x317d1a07 }, + { 0x3d400254, 0xf }, + { 0x3d40025c, 0x2a001b76 }, + { 0x3d400264, 0x7300b473 }, + { 0x3d40026c, 0x30000e06 }, + { 0x3d400300, 0x14 }, + { 0x3d40036c, 0x10 }, + { 0x3d400404, 0x13193 }, + { 0x3d400408, 0x6096 }, + { 0x3d400490, 0x1 }, + { 0x3d400494, 0x2000c00 }, + { 0x3d400498, 0x3c00db }, + { 0x3d40049c, 0x100009 }, + { 0x3d4004a0, 0x2 }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x400093 }, + { 0x3d4020dc, 0x40105 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x5030206 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1205010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3858204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x504 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2fd }, + { 0x1015f, 0x2fd }, + { 0x1105f, 0x2fd }, + { 0x1115f, 0x2fd }, + { 0x11005f, 0x2fd }, + { 0x11015f, 0x2fd }, + { 0x11105f, 0x2fd }, + { 0x11115f, 0x2fd }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0xa }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x10049, 0xe38 }, + { 0x10149, 0xe38 }, + { 0x11049, 0xe38 }, + { 0x11149, 0xe38 }, + { 0x110049, 0xe38 }, + { 0x110149, 0xe38 }, + { 0x111049, 0xe38 }, + { 0x111149, 0xe38 }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x268 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x1200b2, 0x268 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2,0x0}, + {0x1200b2,0x0}, + {0x2200b2,0x0}, + {0x0200cb,0x0}, + {0x010043,0x0}, + {0x110043,0x0}, + {0x210043,0x0}, + {0x010143,0x0}, + {0x110143,0x0}, + {0x210143,0x0}, + {0x011043,0x0}, + {0x111043,0x0}, + {0x211043,0x0}, + {0x011143,0x0}, + {0x111143,0x0}, + {0x211143,0x0}, + {0x000080,0x0}, + {0x100080,0x0}, + {0x200080,0x0}, + {0x001080,0x0}, + {0x101080,0x0}, + {0x201080,0x0}, + {0x002080,0x0}, + {0x102080,0x0}, + {0x202080,0x0}, + {0x003080,0x0}, + {0x103080,0x0}, + {0x203080,0x0}, + {0x004080,0x0}, + {0x104080,0x0}, + {0x204080,0x0}, + {0x005080,0x0}, + {0x105080,0x0}, + {0x205080,0x0}, + {0x006080,0x0}, + {0x106080,0x0}, + {0x206080,0x0}, + {0x007080,0x0}, + {0x107080,0x0}, + {0x207080,0x0}, + {0x008080,0x0}, + {0x108080,0x0}, + {0x208080,0x0}, + {0x009080,0x0}, + {0x109080,0x0}, + {0x209080,0x0}, + {0x010080,0x0}, + {0x110080,0x0}, + {0x210080,0x0}, + {0x010180,0x0}, + {0x110180,0x0}, + {0x210180,0x0}, + {0x010081,0x0}, + {0x110081,0x0}, + {0x210081,0x0}, + {0x010181,0x0}, + {0x110181,0x0}, + {0x210181,0x0}, + {0x010082,0x0}, + {0x110082,0x0}, + {0x210082,0x0}, + {0x010182,0x0}, + {0x110182,0x0}, + {0x210182,0x0}, + {0x010083,0x0}, + {0x110083,0x0}, + {0x210083,0x0}, + {0x010183,0x0}, + {0x110183,0x0}, + {0x210183,0x0}, + {0x011080,0x0}, + {0x111080,0x0}, + {0x211080,0x0}, + {0x011180,0x0}, + {0x111180,0x0}, + {0x211180,0x0}, + {0x011081,0x0}, + {0x111081,0x0}, + {0x211081,0x0}, + {0x011181,0x0}, + {0x111181,0x0}, + {0x211181,0x0}, + {0x011082,0x0}, + {0x111082,0x0}, + {0x211082,0x0}, + {0x011182,0x0}, + {0x111182,0x0}, + {0x211182,0x0}, + {0x011083,0x0}, + {0x111083,0x0}, + {0x211083,0x0}, + {0x011183,0x0}, + {0x111183,0x0}, + {0x211183,0x0}, + {0x0100d0,0x0}, + {0x1100d0,0x0}, + {0x2100d0,0x0}, + {0x0101d0,0x0}, + {0x1101d0,0x0}, + {0x2101d0,0x0}, + {0x0100d1,0x0}, + {0x1100d1,0x0}, + {0x2100d1,0x0}, + {0x0101d1,0x0}, + {0x1101d1,0x0}, + {0x2101d1,0x0}, + {0x0100d2,0x0}, + {0x1100d2,0x0}, + {0x2100d2,0x0}, + {0x0101d2,0x0}, + {0x1101d2,0x0}, + {0x2101d2,0x0}, + {0x0100d3,0x0}, + {0x1100d3,0x0}, + {0x2100d3,0x0}, + {0x0101d3,0x0}, + {0x1101d3,0x0}, + {0x2101d3,0x0}, + {0x0110d0,0x0}, + {0x1110d0,0x0}, + {0x2110d0,0x0}, + {0x0111d0,0x0}, + {0x1111d0,0x0}, + {0x2111d0,0x0}, + {0x0110d1,0x0}, + {0x1110d1,0x0}, + {0x2110d1,0x0}, + {0x0111d1,0x0}, + {0x1111d1,0x0}, + {0x2111d1,0x0}, + {0x0110d2,0x0}, + {0x1110d2,0x0}, + {0x2110d2,0x0}, + {0x0111d2,0x0}, + {0x1111d2,0x0}, + {0x2111d2,0x0}, + {0x0110d3,0x0}, + {0x1110d3,0x0}, + {0x2110d3,0x0}, + {0x0111d3,0x0}, + {0x1111d3,0x0}, + {0x2111d3,0x0}, + {0x010068,0x0}, + {0x010168,0x0}, + {0x010268,0x0}, + {0x010368,0x0}, + {0x010468,0x0}, + {0x010568,0x0}, + {0x010668,0x0}, + {0x010768,0x0}, + {0x010868,0x0}, + {0x010069,0x0}, + {0x010169,0x0}, + {0x010269,0x0}, + {0x010369,0x0}, + {0x010469,0x0}, + {0x010569,0x0}, + {0x010669,0x0}, + {0x010769,0x0}, + {0x010869,0x0}, + {0x01006a,0x0}, + {0x01016a,0x0}, + {0x01026a,0x0}, + {0x01036a,0x0}, + {0x01046a,0x0}, + {0x01056a,0x0}, + {0x01066a,0x0}, + {0x01076a,0x0}, + {0x01086a,0x0}, + {0x01006b,0x0}, + {0x01016b,0x0}, + {0x01026b,0x0}, + {0x01036b,0x0}, + {0x01046b,0x0}, + {0x01056b,0x0}, + {0x01066b,0x0}, + {0x01076b,0x0}, + {0x01086b,0x0}, + {0x011068,0x0}, + {0x011168,0x0}, + {0x011268,0x0}, + {0x011368,0x0}, + {0x011468,0x0}, + {0x011568,0x0}, + {0x011668,0x0}, + {0x011768,0x0}, + {0x011868,0x0}, + {0x011069,0x0}, + {0x011169,0x0}, + {0x011269,0x0}, + {0x011369,0x0}, + {0x011469,0x0}, + {0x011569,0x0}, + {0x011669,0x0}, + {0x011769,0x0}, + {0x011869,0x0}, + {0x01106a,0x0}, + {0x01116a,0x0}, + {0x01126a,0x0}, + {0x01136a,0x0}, + {0x01146a,0x0}, + {0x01156a,0x0}, + {0x01166a,0x0}, + {0x01176a,0x0}, + {0x01186a,0x0}, + {0x01106b,0x0}, + {0x01116b,0x0}, + {0x01126b,0x0}, + {0x01136b,0x0}, + {0x01146b,0x0}, + {0x01156b,0x0}, + {0x01166b,0x0}, + {0x01176b,0x0}, + {0x01186b,0x0}, + {0x01008c,0x0}, + {0x11008c,0x0}, + {0x21008c,0x0}, + {0x01018c,0x0}, + {0x11018c,0x0}, + {0x21018c,0x0}, + {0x01008d,0x0}, + {0x11008d,0x0}, + {0x21008d,0x0}, + {0x01018d,0x0}, + {0x11018d,0x0}, + {0x21018d,0x0}, + {0x01008e,0x0}, + {0x11008e,0x0}, + {0x21008e,0x0}, + {0x01018e,0x0}, + {0x11018e,0x0}, + {0x21018e,0x0}, + {0x01008f,0x0}, + {0x11008f,0x0}, + {0x21008f,0x0}, + {0x01018f,0x0}, + {0x11018f,0x0}, + {0x21018f,0x0}, + {0x01108c,0x0}, + {0x11108c,0x0}, + {0x21108c,0x0}, + {0x01118c,0x0}, + {0x11118c,0x0}, + {0x21118c,0x0}, + {0x01108d,0x0}, + {0x11108d,0x0}, + {0x21108d,0x0}, + {0x01118d,0x0}, + {0x11118d,0x0}, + {0x21118d,0x0}, + {0x01108e,0x0}, + {0x11108e,0x0}, + {0x21108e,0x0}, + {0x01118e,0x0}, + {0x11118e,0x0}, + {0x21118e,0x0}, + {0x01108f,0x0}, + {0x11108f,0x0}, + {0x21108f,0x0}, + {0x01118f,0x0}, + {0x11118f,0x0}, + {0x21118f,0x0}, + {0x0100c0,0x0}, + {0x1100c0,0x0}, + {0x2100c0,0x0}, + {0x0101c0,0x0}, + {0x1101c0,0x0}, + {0x2101c0,0x0}, + {0x0102c0,0x0}, + {0x1102c0,0x0}, + {0x2102c0,0x0}, + {0x0103c0,0x0}, + {0x1103c0,0x0}, + {0x2103c0,0x0}, + {0x0104c0,0x0}, + {0x1104c0,0x0}, + {0x2104c0,0x0}, + {0x0105c0,0x0}, + {0x1105c0,0x0}, + {0x2105c0,0x0}, + {0x0106c0,0x0}, + {0x1106c0,0x0}, + {0x2106c0,0x0}, + {0x0107c0,0x0}, + {0x1107c0,0x0}, + {0x2107c0,0x0}, + {0x0108c0,0x0}, + {0x1108c0,0x0}, + {0x2108c0,0x0}, + {0x0100c1,0x0}, + {0x1100c1,0x0}, + {0x2100c1,0x0}, + {0x0101c1,0x0}, + {0x1101c1,0x0}, + {0x2101c1,0x0}, + {0x0102c1,0x0}, + {0x1102c1,0x0}, + {0x2102c1,0x0}, + {0x0103c1,0x0}, + {0x1103c1,0x0}, + {0x2103c1,0x0}, + {0x0104c1,0x0}, + {0x1104c1,0x0}, + {0x2104c1,0x0}, + {0x0105c1,0x0}, + {0x1105c1,0x0}, + {0x2105c1,0x0}, + {0x0106c1,0x0}, + {0x1106c1,0x0}, + {0x2106c1,0x0}, + {0x0107c1,0x0}, + {0x1107c1,0x0}, + {0x2107c1,0x0}, + {0x0108c1,0x0}, + {0x1108c1,0x0}, + {0x2108c1,0x0}, + {0x0100c2,0x0}, + {0x1100c2,0x0}, + {0x2100c2,0x0}, + {0x0101c2,0x0}, + {0x1101c2,0x0}, + {0x2101c2,0x0}, + {0x0102c2,0x0}, + {0x1102c2,0x0}, + {0x2102c2,0x0}, + {0x0103c2,0x0}, + {0x1103c2,0x0}, + {0x2103c2,0x0}, + {0x0104c2,0x0}, + {0x1104c2,0x0}, + {0x2104c2,0x0}, + {0x0105c2,0x0}, + {0x1105c2,0x0}, + {0x2105c2,0x0}, + {0x0106c2,0x0}, + {0x1106c2,0x0}, + {0x2106c2,0x0}, + {0x0107c2,0x0}, + {0x1107c2,0x0}, + {0x2107c2,0x0}, + {0x0108c2,0x0}, + {0x1108c2,0x0}, + {0x2108c2,0x0}, + {0x0100c3,0x0}, + {0x1100c3,0x0}, + {0x2100c3,0x0}, + {0x0101c3,0x0}, + {0x1101c3,0x0}, + {0x2101c3,0x0}, + {0x0102c3,0x0}, + {0x1102c3,0x0}, + {0x2102c3,0x0}, + {0x0103c3,0x0}, + {0x1103c3,0x0}, + {0x2103c3,0x0}, + {0x0104c3,0x0}, + {0x1104c3,0x0}, + {0x2104c3,0x0}, + {0x0105c3,0x0}, + {0x1105c3,0x0}, + {0x2105c3,0x0}, + {0x0106c3,0x0}, + {0x1106c3,0x0}, + {0x2106c3,0x0}, + {0x0107c3,0x0}, + {0x1107c3,0x0}, + {0x2107c3,0x0}, + {0x0108c3,0x0}, + {0x1108c3,0x0}, + {0x2108c3,0x0}, + {0x0110c0,0x0}, + {0x1110c0,0x0}, + {0x2110c0,0x0}, + {0x0111c0,0x0}, + {0x1111c0,0x0}, + {0x2111c0,0x0}, + {0x0112c0,0x0}, + {0x1112c0,0x0}, + {0x2112c0,0x0}, + {0x0113c0,0x0}, + {0x1113c0,0x0}, + {0x2113c0,0x0}, + {0x0114c0,0x0}, + {0x1114c0,0x0}, + {0x2114c0,0x0}, + {0x0115c0,0x0}, + {0x1115c0,0x0}, + {0x2115c0,0x0}, + {0x0116c0,0x0}, + {0x1116c0,0x0}, + {0x2116c0,0x0}, + {0x0117c0,0x0}, + {0x1117c0,0x0}, + {0x2117c0,0x0}, + {0x0118c0,0x0}, + {0x1118c0,0x0}, + {0x2118c0,0x0}, + {0x0110c1,0x0}, + {0x1110c1,0x0}, + {0x2110c1,0x0}, + {0x0111c1,0x0}, + {0x1111c1,0x0}, + {0x2111c1,0x0}, + {0x0112c1,0x0}, + {0x1112c1,0x0}, + {0x2112c1,0x0}, + {0x0113c1,0x0}, + {0x1113c1,0x0}, + {0x2113c1,0x0}, + {0x0114c1,0x0}, + {0x1114c1,0x0}, + {0x2114c1,0x0}, + {0x0115c1,0x0}, + {0x1115c1,0x0}, + {0x2115c1,0x0}, + {0x0116c1,0x0}, + {0x1116c1,0x0}, + {0x2116c1,0x0}, + {0x0117c1,0x0}, + {0x1117c1,0x0}, + {0x2117c1,0x0}, + {0x0118c1,0x0}, + {0x1118c1,0x0}, + {0x2118c1,0x0}, + {0x0110c2,0x0}, + {0x1110c2,0x0}, + {0x2110c2,0x0}, + {0x0111c2,0x0}, + {0x1111c2,0x0}, + {0x2111c2,0x0}, + {0x0112c2,0x0}, + {0x1112c2,0x0}, + {0x2112c2,0x0}, + {0x0113c2,0x0}, + {0x1113c2,0x0}, + {0x2113c2,0x0}, + {0x0114c2,0x0}, + {0x1114c2,0x0}, + {0x2114c2,0x0}, + {0x0115c2,0x0}, + {0x1115c2,0x0}, + {0x2115c2,0x0}, + {0x0116c2,0x0}, + {0x1116c2,0x0}, + {0x2116c2,0x0}, + {0x0117c2,0x0}, + {0x1117c2,0x0}, + {0x2117c2,0x0}, + {0x0118c2,0x0}, + {0x1118c2,0x0}, + {0x2118c2,0x0}, + {0x0110c3,0x0}, + {0x1110c3,0x0}, + {0x2110c3,0x0}, + {0x0111c3,0x0}, + {0x1111c3,0x0}, + {0x2111c3,0x0}, + {0x0112c3,0x0}, + {0x1112c3,0x0}, + {0x2112c3,0x0}, + {0x0113c3,0x0}, + {0x1113c3,0x0}, + {0x2113c3,0x0}, + {0x0114c3,0x0}, + {0x1114c3,0x0}, + {0x2114c3,0x0}, + {0x0115c3,0x0}, + {0x1115c3,0x0}, + {0x2115c3,0x0}, + {0x0116c3,0x0}, + {0x1116c3,0x0}, + {0x2116c3,0x0}, + {0x0117c3,0x0}, + {0x1117c3,0x0}, + {0x2117c3,0x0}, + {0x0118c3,0x0}, + {0x1118c3,0x0}, + {0x2118c3,0x0}, + {0x010020,0x0}, + {0x110020,0x0}, + {0x210020,0x0}, + {0x011020,0x0}, + {0x111020,0x0}, + {0x211020,0x0}, + {0x02007d,0x0}, + {0x12007d,0x0}, + {0x22007d,0x0}, + {0x010040,0x0}, + {0x010140,0x0}, + {0x010240,0x0}, + {0x010340,0x0}, + {0x010440,0x0}, + {0x010540,0x0}, + {0x010640,0x0}, + {0x010740,0x0}, + {0x010840,0x0}, + {0x010030,0x0}, + {0x010130,0x0}, + {0x010230,0x0}, + {0x010330,0x0}, + {0x010430,0x0}, + {0x010530,0x0}, + {0x010630,0x0}, + {0x010730,0x0}, + {0x010830,0x0}, + {0x011040,0x0}, + {0x011140,0x0}, + {0x011240,0x0}, + {0x011340,0x0}, + {0x011440,0x0}, + {0x011540,0x0}, + {0x011640,0x0}, + {0x011740,0x0}, + {0x011840,0x0}, + {0x011030,0x0}, + {0x011130,0x0}, + {0x011230,0x0}, + {0x011330,0x0}, + {0x011430,0x0}, + {0x011530,0x0}, + {0x011630,0x0}, + {0x011730,0x0}, + {0x011830,0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x234 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x410 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x4 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2830 }, + { 0x54006, 0x25e }, + { 0x54007, 0x1000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x234 }, + { 0x54030, 0x105 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x410 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7c8 }, + { 0x900a9, 0x101 }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x448 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0xf }, + { 0x900ae, 0x7c0 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x47 }, + { 0x900b1, 0x630 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0x618 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0xe0 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x0 }, + { 0x900ba, 0x7c8 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0x8140 }, + { 0x900be, 0x10c }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x8 }, + { 0x900c5, 0x8 }, + { 0x900c6, 0x7c8 }, + { 0x900c7, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2b }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 1066, }, +}; + diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.c b/board/freescale/imx8mn_evk/imx8mn_evk.c index 9a0a0488bf4..75937612755 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.c +++ b/board/freescale/imx8mn_evk/imx8mn_evk.c @@ -7,24 +7,340 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; -int board_init(void) +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_NAND_MXS +#ifdef CONFIG_SPL_BUILD +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MN_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MN_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MN_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; +#endif + +static void setup_gpmi_nand(void) +{ +#ifdef CONFIG_SPL_BUILD + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); +#endif + + init_nand_clk(); +} +#endif + +int board_early_init_f(void) { + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + init_uart_clk(1); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + return 0; } -int board_mmc_get_env_dev(int devno) +#if IS_ENABLED(CONFIG_FEC_MXC) +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], 0x2000, 0); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + +#ifndef CONFIG_DM_ETH + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif + + return 0; +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; +} + +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(1, 0x72); + } else if (port == &port2) { + debug("Setup pd switch on port 2\n"); + return setup_pd_switch(1, 0x73); + } else + return -EINVAL; +} + +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 5000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x52, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 9000, + .max_snk_ma = 3000, + .max_snk_mw = 40000, + .op_snk_mv = 9000, + .switch_setup_func = &pd_switch_snk_enable, +}; + +static int setup_typec(void) +{ + int ret; + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } else if (tcpc_pd_sink_check_charging(&port2)) { + /* Disable PD for USB1, since USB2 has priority */ + port1_config.disable_pd = true; + printf("Power supply on USB2\n"); + } + + debug("tcpc_init port 1\n"); + ret = tcpc_init(&port1, port1_config, NULL); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } else { + if (!port1_config.disable_pd) + printf("Power supply on USB1\n"); + return ret; + } + + return ret; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + struct tcpc_port *port_ptr; + + debug("board_usb_init %d, type %d\n", index, init); + + if (index == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + imx8m_usb_power(index, true); + + if (init == USB_INIT_HOST) + tcpc_setup_dfp_mode(port_ptr); + else + tcpc_setup_ufp_mode(port_ptr); + + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) { - return devno; + int ret = 0; + + debug("board_usb_cleanup %d, type %d\n", index, init); + + if (init == USB_INIT_HOST) { + if (index == 0) + ret = tcpc_disable_src_vbus(&port1); + else + ret = tcpc_disable_src_vbus(&port2); + } + + imx8m_usb_power(index, false); + return ret; +} + +int board_ehci_usb_phy_mode(struct udevice *dev) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + struct tcpc_port *port_ptr; + + if (dev_seq(dev) == 0) + port_ptr = &port1; + else + port_ptr = &port2; + + tcpc_setup_ufp_mode(port_ptr); + + ret = tcpc_get_cc_status(port_ptr, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; +} + +#endif + +#define DISPMIX 9 +#define MIPI 10 + +int board_init(void) +{ + struct arm_smccc_res res; + +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + + if (IS_ENABLED(CONFIG_FEC_MXC)) + setup_fec(); + + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + DISPMIX, true, 0, 0, 0, 0, &res); + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + MIPI, true, 0, 0, 0, 0, &res); + + return 0; } int board_late_init(void) { +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "DDR4 EVK"); env_set("board_rev", "iMX8MN"); #endif return 0; } + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /* TODO */ +} +#endif /* CONFIG_ANDROID_RECOVERY */ +#endif /* CONFIG_FSL_FASTBOOT */ diff --git a/board/freescale/imx8mn_evk/lpddr4_timing.c b/board/freescale/imx8mn_evk/lpddr4_timing.c new file mode 100644 index 00000000000..0ce039a95fb --- /dev/null +++ b/board/freescale/imx8mn_evk/lpddr4_timing.c @@ -0,0 +1,1584 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Generated code from MX8M_DDR_tool + * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x3d400020, 0x00000213}, + {0x3d400024, 0x0003e800}, + {0x3d400030, 0x00000120}, + {0x3d400000, 0xa3080020}, + {0x3d400064, 0x006100e0}, + {0x3d4000d0, 0xc003061c}, + {0x3d4000d4, 0x009e0000}, + {0x3d4000dc, 0x00d4002d}, + {0x3d4000e0, 0x00310000}, + {0x3d4000e8, 0x0066004d}, + {0x3d4000ec, 0x0016004a}, + {0x3d400100, 0x1a201b22}, + {0x3d400104, 0x00060633}, + {0x3d40010c, 0x00c0c000}, + {0x3d400110, 0x0f04080f}, + {0x3d400114, 0x02040c0c}, + {0x3d400118, 0x01010007}, + {0x3d40011c, 0x00000401}, + {0x3d400130, 0x00020600}, + {0x3d400134, 0x0c100002}, + {0x3d400138, 0x000000e6}, + {0x3d400144, 0x00a00050}, + {0x3d400180, 0x03200018}, + {0x3d400184, 0x028061a8}, + {0x3d400188, 0x00000000}, + {0x3d400190, 0x0497820a}, + {0x3d4001b4, 0x0000170a}, + {0x3d400108, 0x070e1617}, + {0x3d4001c0, 0x00000001}, + {0x3d400194, 0x00080303}, + {0x3d4001a0, 0xe0400018}, + {0x3d4001a4, 0x00df00e4}, + {0x3d4001a8, 0x80000000}, + {0x3d4001b0, 0x00000011}, + {0x3d4001c4, 0x00000001}, + {0x3d4000f4, 0x00000c99}, + {0x3d400200, 0x00000017}, + {0x3d400204, 0x00080808}, + {0x3d400208, 0x00000000}, + {0x3d40020c, 0x00000000}, + {0x3d400210, 0x00001f1f}, + {0x3d400214, 0x07070707}, + {0x3d400218, 0x07070707}, + {0x3d40021c, 0x00000f0f}, + {0x3d400250, 0x29001701}, + {0x3d400254, 0x0000002c}, + {0x3d40025c, 0x04000030}, + {0x3d400264, 0x900093e7}, + {0x3d40026c, 0x20005574}, + {0x3d400400, 0x00000111}, + {0x3d400408, 0x000072ff}, + {0x3d400494, 0x02100e07}, + {0x3d400498, 0x00620096}, + {0x3d40049c, 0x01100e07}, + {0x3d4004a0, 0x00c8012c}, + {0x3d402020, 0x00000011}, + {0x3d402024, 0x00007d00}, + {0x3d402050, 0x0020d040}, + {0x3d402064, 0x000c001d}, + {0x3d4020f4, 0x00000c99}, + {0x3d402100, 0x0a040305}, + {0x3d402104, 0x00030407}, + {0x3d402108, 0x0203060b}, + {0x3d40210c, 0x00505000}, + {0x3d402110, 0x02040202}, + {0x3d402114, 0x02030202}, + {0x3d402118, 0x01010004}, + {0x3d40211c, 0x00000301}, + {0x3d402130, 0x00020300}, + {0x3d402134, 0x0a100002}, + {0x3d402138, 0x0000001d}, + {0x3d402144, 0x0014000a}, + {0x3d402180, 0x00650004}, + {0x3d402190, 0x03818200}, + {0x3d402194, 0x00080303}, + {0x3d4021b4, 0x00000100}, + {0x3d4020dc, 0x00840000}, + {0x3d4020e0, 0x00310000}, + {0x3d4020e8, 0x0066004d}, + {0x3d4020ec, 0x0016004a}, + {0x3d403020, 0x00000011}, + {0x3d403024, 0x00001f40}, + {0x3d403050, 0x0020d040}, + {0x3d403064, 0x00030007}, + {0x3d4030f4, 0x00000c99}, + {0x3d403100, 0x0a010102}, + {0x3d403104, 0x00030404}, + {0x3d403108, 0x0203060b}, + {0x3d40310c, 0x00505000}, + {0x3d403110, 0x02040202}, + {0x3d403114, 0x02030202}, + {0x3d403118, 0x01010004}, + {0x3d40311c, 0x00000301}, + {0x3d403130, 0x00020300}, + {0x3d403134, 0x0a100002}, + {0x3d403138, 0x00000008}, + {0x3d403144, 0x00050003}, + {0x3d403180, 0x00190004}, + {0x3d403190, 0x03818200}, + {0x3d403194, 0x00080303}, + {0x3d4031b4, 0x00000100}, + {0x3d4030dc, 0x00840000}, + {0x3d4030e0, 0x00310000}, + {0x3d4030e8, 0x0066004d}, + {0x3d4030ec, 0x0016004a}, + + /* default boot point */ + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x000100a0, 0x00000000}, + {0x000100a1, 0x00000001}, + {0x000100a2, 0x00000002}, + {0x000100a3, 0x00000003}, + {0x000100a4, 0x00000004}, + {0x000100a5, 0x00000005}, + {0x000100a6, 0x00000006}, + {0x000100a7, 0x00000007}, + {0x000110a0, 0x00000000}, + {0x000110a1, 0x00000001}, + {0x000110a2, 0x00000003}, + {0x000110a3, 0x00000004}, + {0x000110a4, 0x00000005}, + {0x000110a5, 0x00000002}, + {0x000110a6, 0x00000007}, + {0x000110a7, 0x00000006}, + {0x0001005f, 0x0000015f}, + {0x0001015f, 0x0000015f}, + {0x0001105f, 0x0000015f}, + {0x0001115f, 0x0000015f}, + {0x0011005f, 0x0000015f}, + {0x0011015f, 0x0000015f}, + {0x0011105f, 0x0000015f}, + {0x0011115f, 0x0000015f}, + {0x0021005f, 0x0000015f}, + {0x0021015f, 0x0000015f}, + {0x0021105f, 0x0000015f}, + {0x0021115f, 0x0000015f}, + {0x00000055, 0x0000016f}, + {0x00001055, 0x0000016f}, + {0x00002055, 0x0000016f}, + {0x00003055, 0x0000016f}, + {0x00004055, 0x0000016f}, + {0x00005055, 0x0000016f}, + {0x00006055, 0x0000016f}, + {0x00007055, 0x0000016f}, + {0x00008055, 0x0000016f}, + {0x00009055, 0x0000016f}, + {0x000200c5, 0x00000019}, + {0x001200c5, 0x00000007}, + {0x002200c5, 0x00000007}, + {0x0002002e, 0x00000002}, + {0x0012002e, 0x00000002}, + {0x0022002e, 0x00000002}, + {0x00090204, 0x00000000}, + {0x00190204, 0x00000000}, + {0x00290204, 0x00000000}, + {0x00020024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0002007d, 0x00000212}, + {0x0002007c, 0x00000061}, + {0x00120024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0012007d, 0x00000212}, + {0x0012007c, 0x00000061}, + {0x00220024, 0x000001a3}, + {0x0002003a, 0x00000002}, + {0x0022007d, 0x00000212}, + {0x0022007c, 0x00000061}, + {0x00020056, 0x00000003}, + {0x00120056, 0x00000003}, + {0x00220056, 0x00000003}, + {0x0001004d, 0x00000f80}, + {0x0001014d, 0x00000f80}, + {0x0001104d, 0x00000f80}, + {0x0001114d, 0x00000f80}, + {0x0011004d, 0x00000f80}, + {0x0011014d, 0x00000f80}, + {0x0011104d, 0x00000f80}, + {0x0011114d, 0x00000f80}, + {0x0021004d, 0x00000f80}, + {0x0021014d, 0x00000f80}, + {0x0021104d, 0x00000f80}, + {0x0021114d, 0x00000f80}, + {0x00010049, 0x00000fbe}, + {0x00010149, 0x00000fbe}, + {0x00011049, 0x00000fbe}, + {0x00011149, 0x00000fbe}, + {0x00110049, 0x00000fbe}, + {0x00110149, 0x00000fbe}, + {0x00111049, 0x00000fbe}, + {0x00111149, 0x00000fbe}, + {0x00210049, 0x00000fbe}, + {0x00210149, 0x00000fbe}, + {0x00211049, 0x00000fbe}, + {0x00211149, 0x00000fbe}, + {0x00000043, 0x00000063}, + {0x00001043, 0x00000063}, + {0x00002043, 0x00000063}, + {0x00003043, 0x00000063}, + {0x00004043, 0x00000063}, + {0x00005043, 0x00000063}, + {0x00006043, 0x00000063}, + {0x00007043, 0x00000063}, + {0x00008043, 0x00000063}, + {0x00009043, 0x00000063}, + {0x00020018, 0x00000001}, + {0x00020075, 0x00000004}, + {0x00020050, 0x00000000}, + {0x00020008, 0x00000320}, + {0x00120008, 0x00000064}, + {0x00220008, 0x00000019}, + {0x00020088, 0x00000009}, + {0x000200b2, 0x000000dc}, + {0x00010043, 0x000005a1}, + {0x00010143, 0x000005a1}, + {0x00011043, 0x000005a1}, + {0x00011143, 0x000005a1}, + {0x001200b2, 0x000000dc}, + {0x00110043, 0x000005a1}, + {0x00110143, 0x000005a1}, + {0x00111043, 0x000005a1}, + {0x00111143, 0x000005a1}, + {0x002200b2, 0x000000dc}, + {0x00210043, 0x000005a1}, + {0x00210143, 0x000005a1}, + {0x00211043, 0x000005a1}, + {0x00211143, 0x000005a1}, + {0x000200fa, 0x00000001}, + {0x001200fa, 0x00000001}, + {0x002200fa, 0x00000001}, + {0x00020019, 0x00000001}, + {0x00120019, 0x00000001}, + {0x00220019, 0x00000001}, + {0x000200f0, 0x00000660}, + {0x000200f1, 0x00000000}, + {0x000200f2, 0x00004444}, + {0x000200f3, 0x00008888}, + {0x000200f4, 0x00005665}, + {0x000200f5, 0x00000000}, + {0x000200f6, 0x00000000}, + {0x000200f7, 0x0000f000}, + {0x0001004a, 0x00000500}, + {0x0001104a, 0x00000500}, + {0x00020025, 0x00000000}, + {0x0002002d, 0x00000000}, + {0x0012002d, 0x00000000}, + {0x0022002d, 0x00000000}, + {0x0002002c, 0x00000000}, + {0x000200c7, 0x00000021}, + {0x000200ca, 0x00000024}, + {0x000200cc, 0x000001f7}, + {0x001200c7, 0x00000021}, + {0x001200ca, 0x00000024}, + {0x001200cc, 0x000001f7}, + {0x002200c7, 0x00000021}, + {0x002200ca, 0x00000024}, + {0x002200cc, 0x000001f7}, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000131f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000101}, + {0x00054003, 0x00000190}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000102}, + {0x00054003, 0x00000064}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x0000121f}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00000000}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00000084}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00000084}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x00008400}, + {0x00054033, 0x00003100}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x00008400}, + {0x00054039, 0x00003100}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0x000d0000, 0x00000000}, + {0x00054000, 0x00000000}, + {0x00054001, 0x00000000}, + {0x00054002, 0x00000000}, + {0x00054003, 0x00000c80}, + {0x00054004, 0x00000002}, + {0x00054005, 0x00000000}, + {0x00054006, 0x00000011}, + {0x00054007, 0x00000000}, + {0x00054008, 0x00000061}, + {0x00054009, 0x000000c8}, + {0x0005400a, 0x00000000}, + {0x0005400b, 0x00000002}, + {0x0005400c, 0x00000000}, + {0x0005400d, 0x00000000}, + {0x0005400e, 0x00000000}, + {0x0005400f, 0x00000100}, + {0x00054010, 0x00001f7f}, + {0x00054011, 0x00000000}, + {0x00054012, 0x00000310}, + {0x00054013, 0x00000000}, + {0x00054014, 0x00000000}, + {0x00054015, 0x00000000}, + {0x00054016, 0x00000000}, + {0x00054017, 0x00000000}, + {0x00054018, 0x00000000}, + {0x00054019, 0x00002dd4}, + {0x0005401a, 0x00000031}, + {0x0005401b, 0x00004d66}, + {0x0005401c, 0x00004a00}, + {0x0005401d, 0x00000000}, + {0x0005401e, 0x00000016}, + {0x0005401f, 0x00002dd4}, + {0x00054020, 0x00000031}, + {0x00054021, 0x00004d66}, + {0x00054022, 0x00004a00}, + {0x00054023, 0x00000000}, + {0x00054024, 0x0000002e}, + {0x00054025, 0x00000000}, + {0x00054026, 0x00000000}, + {0x00054027, 0x00000000}, + {0x00054028, 0x00000000}, + {0x00054029, 0x00000000}, + {0x0005402a, 0x00000000}, + {0x0005402b, 0x00000000}, + {0x0005402c, 0x00000000}, + {0x0005402d, 0x00000000}, + {0x0005402e, 0x00000000}, + {0x0005402f, 0x00000000}, + {0x00054030, 0x00000000}, + {0x00054031, 0x00000000}, + {0x00054032, 0x0000d400}, + {0x00054033, 0x0000312d}, + {0x00054034, 0x00006600}, + {0x00054035, 0x0000004d}, + {0x00054036, 0x0000004a}, + {0x00054037, 0x00001600}, + {0x00054038, 0x0000d400}, + {0x00054039, 0x0000312d}, + {0x0005403a, 0x00006600}, + {0x0005403b, 0x0000004d}, + {0x0005403c, 0x0000004a}, + {0x0005403d, 0x00002e00}, + {0x0005403e, 0x00000000}, + {0x0005403f, 0x00000000}, + {0x00054040, 0x00000000}, + {0x00054041, 0x00000000}, + {0x00054042, 0x00000000}, + {0x00054043, 0x00000000}, + {0x00054044, 0x00000000}, + {0x000d0000, 0x00000001}, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x0}, + {0x90051, 0x45a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x448}, + {0x90055, 0x109}, + {0x90056, 0x40}, + {0x90057, 0x633}, + {0x90058, 0x179}, + {0x90059, 0x1}, + {0x9005a, 0x618}, + {0x9005b, 0x109}, + {0x9005c, 0x40c0}, + {0x9005d, 0x633}, + {0x9005e, 0x149}, + {0x9005f, 0x8}, + {0x90060, 0x4}, + {0x90061, 0x48}, + {0x90062, 0x4040}, + {0x90063, 0x633}, + {0x90064, 0x149}, + {0x90065, 0x0}, + {0x90066, 0x4}, + {0x90067, 0x48}, + {0x90068, 0x40}, + {0x90069, 0x633}, + {0x9006a, 0x149}, + {0x9006b, 0x10}, + {0x9006c, 0x4}, + {0x9006d, 0x18}, + {0x9006e, 0x0}, + {0x9006f, 0x4}, + {0x90070, 0x78}, + {0x90071, 0x549}, + {0x90072, 0x633}, + {0x90073, 0x159}, + {0x90074, 0xd49}, + {0x90075, 0x633}, + {0x90076, 0x159}, + {0x90077, 0x94a}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0x441}, + {0x9007b, 0x633}, + {0x9007c, 0x149}, + {0x9007d, 0x42}, + {0x9007e, 0x633}, + {0x9007f, 0x149}, + {0x90080, 0x1}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x0}, + {0x90084, 0xe0}, + {0x90085, 0x109}, + {0x90086, 0xa}, + {0x90087, 0x10}, + {0x90088, 0x109}, + {0x90089, 0x9}, + {0x9008a, 0x3c0}, + {0x9008b, 0x149}, + {0x9008c, 0x9}, + {0x9008d, 0x3c0}, + {0x9008e, 0x159}, + {0x9008f, 0x18}, + {0x90090, 0x10}, + {0x90091, 0x109}, + {0x90092, 0x0}, + {0x90093, 0x3c0}, + {0x90094, 0x109}, + {0x90095, 0x18}, + {0x90096, 0x4}, + {0x90097, 0x48}, + {0x90098, 0x18}, + {0x90099, 0x4}, + {0x9009a, 0x58}, + {0x9009b, 0xb}, + {0x9009c, 0x10}, + {0x9009d, 0x109}, + {0x9009e, 0x1}, + {0x9009f, 0x10}, + {0x900a0, 0x109}, + {0x900a1, 0x5}, + {0x900a2, 0x7c0}, + {0x900a3, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x790}, + {0x900a6, 0x11a}, + {0x900a7, 0x8}, + {0x900a8, 0x7aa}, + {0x900a9, 0x2a}, + {0x900aa, 0x10}, + {0x900ab, 0x7b2}, + {0x900ac, 0x2a}, + {0x900ad, 0x0}, + {0x900ae, 0x7c8}, + {0x900af, 0x109}, + {0x900b0, 0x10}, + {0x900b1, 0x10}, + {0x900b2, 0x109}, + {0x900b3, 0x10}, + {0x900b4, 0x2a8}, + {0x900b5, 0x129}, + {0x900b6, 0x8}, + {0x900b7, 0x370}, + {0x900b8, 0x129}, + {0x900b9, 0xa}, + {0x900ba, 0x3c8}, + {0x900bb, 0x1a9}, + {0x900bc, 0xc}, + {0x900bd, 0x408}, + {0x900be, 0x199}, + {0x900bf, 0x14}, + {0x900c0, 0x790}, + {0x900c1, 0x11a}, + {0x900c2, 0x8}, + {0x900c3, 0x4}, + {0x900c4, 0x18}, + {0x900c5, 0xe}, + {0x900c6, 0x408}, + {0x900c7, 0x199}, + {0x900c8, 0x8}, + {0x900c9, 0x8568}, + {0x900ca, 0x108}, + {0x900cb, 0x18}, + {0x900cc, 0x790}, + {0x900cd, 0x16a}, + {0x900ce, 0x8}, + {0x900cf, 0x1d8}, + {0x900d0, 0x169}, + {0x900d1, 0x10}, + {0x900d2, 0x8558}, + {0x900d3, 0x168}, + {0x900d4, 0x70}, + {0x900d5, 0x788}, + {0x900d6, 0x16a}, + {0x900d7, 0x1ff8}, + {0x900d8, 0x85a8}, + {0x900d9, 0x1e8}, + {0x900da, 0x50}, + {0x900db, 0x798}, + {0x900dc, 0x16a}, + {0x900dd, 0x60}, + {0x900de, 0x7a0}, + {0x900df, 0x16a}, + {0x900e0, 0x8}, + {0x900e1, 0x8310}, + {0x900e2, 0x168}, + {0x900e3, 0x8}, + {0x900e4, 0xa310}, + {0x900e5, 0x168}, + {0x900e6, 0xa}, + {0x900e7, 0x408}, + {0x900e8, 0x169}, + {0x900e9, 0x6e}, + {0x900ea, 0x0}, + {0x900eb, 0x68}, + {0x900ec, 0x0}, + {0x900ed, 0x408}, + {0x900ee, 0x169}, + {0x900ef, 0x0}, + {0x900f0, 0x8310}, + {0x900f1, 0x168}, + {0x900f2, 0x0}, + {0x900f3, 0xa310}, + {0x900f4, 0x168}, + {0x900f5, 0x1ff8}, + {0x900f6, 0x85a8}, + {0x900f7, 0x1e8}, + {0x900f8, 0x68}, + {0x900f9, 0x798}, + {0x900fa, 0x16a}, + {0x900fb, 0x78}, + {0x900fc, 0x7a0}, + {0x900fd, 0x16a}, + {0x900fe, 0x68}, + {0x900ff, 0x790}, + {0x90100, 0x16a}, + {0x90101, 0x8}, + {0x90102, 0x8b10}, + {0x90103, 0x168}, + {0x90104, 0x8}, + {0x90105, 0xab10}, + {0x90106, 0x168}, + {0x90107, 0xa}, + {0x90108, 0x408}, + {0x90109, 0x169}, + {0x9010a, 0x58}, + {0x9010b, 0x0}, + {0x9010c, 0x68}, + {0x9010d, 0x0}, + {0x9010e, 0x408}, + {0x9010f, 0x169}, + {0x90110, 0x0}, + {0x90111, 0x8b10}, + {0x90112, 0x168}, + {0x90113, 0x1}, + {0x90114, 0xab10}, + {0x90115, 0x168}, + {0x90116, 0x0}, + {0x90117, 0x1d8}, + {0x90118, 0x169}, + {0x90119, 0x80}, + {0x9011a, 0x790}, + {0x9011b, 0x16a}, + {0x9011c, 0x18}, + {0x9011d, 0x7aa}, + {0x9011e, 0x6a}, + {0x9011f, 0xa}, + {0x90120, 0x0}, + {0x90121, 0x1e9}, + {0x90122, 0x8}, + {0x90123, 0x8080}, + {0x90124, 0x108}, + {0x90125, 0xf}, + {0x90126, 0x408}, + {0x90127, 0x169}, + {0x90128, 0xc}, + {0x90129, 0x0}, + {0x9012a, 0x68}, + {0x9012b, 0x9}, + {0x9012c, 0x0}, + {0x9012d, 0x1a9}, + {0x9012e, 0x0}, + {0x9012f, 0x408}, + {0x90130, 0x169}, + {0x90131, 0x0}, + {0x90132, 0x8080}, + {0x90133, 0x108}, + {0x90134, 0x8}, + {0x90135, 0x7aa}, + {0x90136, 0x6a}, + {0x90137, 0x0}, + {0x90138, 0x8568}, + {0x90139, 0x108}, + {0x9013a, 0xb7}, + {0x9013b, 0x790}, + {0x9013c, 0x16a}, + {0x9013d, 0x1f}, + {0x9013e, 0x0}, + {0x9013f, 0x68}, + {0x90140, 0x8}, + {0x90141, 0x8558}, + {0x90142, 0x168}, + {0x90143, 0xf}, + {0x90144, 0x408}, + {0x90145, 0x169}, + {0x90146, 0xd}, + {0x90147, 0x0}, + {0x90148, 0x68}, + {0x90149, 0x0}, + {0x9014a, 0x408}, + {0x9014b, 0x169}, + {0x9014c, 0x0}, + {0x9014d, 0x8558}, + {0x9014e, 0x168}, + {0x9014f, 0x8}, + {0x90150, 0x3c8}, + {0x90151, 0x1a9}, + {0x90152, 0x3}, + {0x90153, 0x370}, + {0x90154, 0x129}, + {0x90155, 0x20}, + {0x90156, 0x2aa}, + {0x90157, 0x9}, + {0x90158, 0x0}, + {0x90159, 0x400}, + {0x9015a, 0x10e}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x10c}, + {0x90164, 0x8}, + {0x90165, 0x7c8}, + {0x90166, 0x101}, + {0x90167, 0x8}, + {0x90168, 0x448}, + {0x90169, 0x109}, + {0x9016a, 0xf}, + {0x9016b, 0x7c0}, + {0x9016c, 0x109}, + {0x9016d, 0x0}, + {0x9016e, 0xe8}, + {0x9016f, 0x109}, + {0x90170, 0x47}, + {0x90171, 0x630}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0x618}, + {0x90175, 0x109}, + {0x90176, 0x8}, + {0x90177, 0xe0}, + {0x90178, 0x109}, + {0x90179, 0x0}, + {0x9017a, 0x7c8}, + {0x9017b, 0x109}, + {0x9017c, 0x8}, + {0x9017d, 0x8140}, + {0x9017e, 0x10c}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x8}, + {0x90185, 0x8}, + {0x90186, 0x7c8}, + {0x90187, 0x101}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x8}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x29}, + {0x90026, 0x6a}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x2000b, 0x64}, + {0x2000c, 0xc8}, + {0x2000d, 0x7d0}, + {0x2000e, 0x2c}, + {0x12000b, 0xc}, + {0x12000c, 0x19}, + {0x12000d, 0xfa}, + {0x12000e, 0x10}, + {0x22000b, 0x3}, + {0x22000c, 0x6}, + {0x22000d, 0x3e}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x2}, + {0xd0000, 0x1}, +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 400, 100, }, +}; diff --git a/board/freescale/imx8mn_evk/lpddr4_timing_ld.c b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c new file mode 100644 index 00000000000..08f86df4511 --- /dev/null +++ b/board/freescale/imx8mn_evk/lpddr4_timing_ld.c @@ -0,0 +1,1445 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x111 }, + { 0x3d400024, 0x1f400 }, + { 0x3d400064, 0x300070 }, + { 0x3d4000d0, 0xc002030f }, + { 0x3d4000d4, 0x500000 }, + { 0x3d4000dc, 0xa40012 }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x10100d11 }, + { 0x3d400104, 0x3041a }, + { 0x3d40010c, 0x606000 }, + { 0x3d400110, 0x8040408 }, + { 0x3d400114, 0x2030606 }, + { 0x3d400118, 0x1010004 }, + { 0x3d40011c, 0x301 }, + { 0x3d400130, 0x20300 }, + { 0x3d400134, 0xa100002 }, + { 0x3d400138, 0x73 }, + { 0x3d400144, 0x500028 }, + { 0x3d400180, 0x190000c }, + { 0x3d400184, 0x14030d4 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x4898204 }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x904 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x4070f0f }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x11 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, + { 0x3d403020, 0x11 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, + { 0x3d400028, 0x0 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0xb }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x1 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x1a3 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x1 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x190 }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x2005b, 0x7529 }, + { 0x2005c, 0x0 }, + { 0x200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x200cc, 0x1f7 }, + { 0x1200c7, 0x21 }, + { 0x1200ca, 0x24 }, + { 0x1200cc, 0x1f7 }, + { 0x2200c7, 0x21 }, + { 0x2200ca, 0x24 }, + { 0x2200cc, 0x1f7 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x22007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x22007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x0200b2, 0x0}, + {0x1200b2, 0x0}, + {0x2200b2, 0x0}, + {0x0200cb, 0x0}, + {0x010043, 0x0}, + {0x110043, 0x0}, + {0x210043, 0x0}, + {0x010143, 0x0}, + {0x110143, 0x0}, + {0x210143, 0x0}, + {0x011043, 0x0}, + {0x111043, 0x0}, + {0x211043, 0x0}, + {0x011143, 0x0}, + {0x111143, 0x0}, + {0x211143, 0x0}, + {0x000080, 0x0}, + {0x100080, 0x0}, + {0x200080, 0x0}, + {0x001080, 0x0}, + {0x101080, 0x0}, + {0x201080, 0x0}, + {0x002080, 0x0}, + {0x102080, 0x0}, + {0x202080, 0x0}, + {0x003080, 0x0}, + {0x103080, 0x0}, + {0x203080, 0x0}, + {0x004080, 0x0}, + {0x104080, 0x0}, + {0x204080, 0x0}, + {0x005080, 0x0}, + {0x105080, 0x0}, + {0x205080, 0x0}, + {0x006080, 0x0}, + {0x106080, 0x0}, + {0x206080, 0x0}, + {0x007080, 0x0}, + {0x107080, 0x0}, + {0x207080, 0x0}, + {0x008080, 0x0}, + {0x108080, 0x0}, + {0x208080, 0x0}, + {0x009080, 0x0}, + {0x109080, 0x0}, + {0x209080, 0x0}, + {0x010080, 0x0}, + {0x110080, 0x0}, + {0x210080, 0x0}, + {0x010180, 0x0}, + {0x110180, 0x0}, + {0x210180, 0x0}, + {0x011080, 0x0}, + {0x111080, 0x0}, + {0x211080, 0x0}, + {0x011180, 0x0}, + {0x111180, 0x0}, + {0x211180, 0x0}, + {0x010081, 0x0}, + {0x110081, 0x0}, + {0x210081, 0x0}, + {0x010181, 0x0}, + {0x110181, 0x0}, + {0x210181, 0x0}, + {0x011081, 0x0}, + {0x111081, 0x0}, + {0x211081, 0x0}, + {0x011181, 0x0}, + {0x111181, 0x0}, + {0x211181, 0x0}, + {0x0100d0, 0x0}, + {0x1100d0, 0x0}, + {0x2100d0, 0x0}, + {0x0101d0, 0x0}, + {0x1101d0, 0x0}, + {0x2101d0, 0x0}, + {0x0110d0, 0x0}, + {0x1110d0, 0x0}, + {0x2110d0, 0x0}, + {0x0111d0, 0x0}, + {0x1111d0, 0x0}, + {0x2111d0, 0x0}, + {0x0100d1, 0x0}, + {0x1100d1, 0x0}, + {0x2100d1, 0x0}, + {0x0101d1, 0x0}, + {0x1101d1, 0x0}, + {0x2101d1, 0x0}, + {0x0110d1, 0x0}, + {0x1110d1, 0x0}, + {0x2110d1, 0x0}, + {0x0111d1, 0x0}, + {0x1111d1, 0x0}, + {0x2111d1, 0x0}, + {0x010068, 0x0}, + {0x010168, 0x0}, + {0x010268, 0x0}, + {0x010368, 0x0}, + {0x010468, 0x0}, + {0x010568, 0x0}, + {0x010668, 0x0}, + {0x010768, 0x0}, + {0x010868, 0x0}, + {0x011068, 0x0}, + {0x011168, 0x0}, + {0x011268, 0x0}, + {0x011368, 0x0}, + {0x011468, 0x0}, + {0x011568, 0x0}, + {0x011668, 0x0}, + {0x011768, 0x0}, + {0x011868, 0x0}, + {0x010069, 0x0}, + {0x010169, 0x0}, + {0x010269, 0x0}, + {0x010369, 0x0}, + {0x010469, 0x0}, + {0x010569, 0x0}, + {0x010669, 0x0}, + {0x010769, 0x0}, + {0x010869, 0x0}, + {0x011069, 0x0}, + {0x011169, 0x0}, + {0x011269, 0x0}, + {0x011369, 0x0}, + {0x011469, 0x0}, + {0x011569, 0x0}, + {0x011669, 0x0}, + {0x011769, 0x0}, + {0x011869, 0x0}, + {0x01008c, 0x0}, + {0x11008c, 0x0}, + {0x21008c, 0x0}, + {0x01018c, 0x0}, + {0x11018c, 0x0}, + {0x21018c, 0x0}, + {0x01108c, 0x0}, + {0x11108c, 0x0}, + {0x21108c, 0x0}, + {0x01118c, 0x0}, + {0x11118c, 0x0}, + {0x21118c, 0x0}, + {0x01008d, 0x0}, + {0x11008d, 0x0}, + {0x21008d, 0x0}, + {0x01018d, 0x0}, + {0x11018d, 0x0}, + {0x21018d, 0x0}, + {0x01108d, 0x0}, + {0x11108d, 0x0}, + {0x21108d, 0x0}, + {0x01118d, 0x0}, + {0x11118d, 0x0}, + {0x21118d, 0x0}, + {0x0100c0, 0x0}, + {0x1100c0, 0x0}, + {0x2100c0, 0x0}, + {0x0101c0, 0x0}, + {0x1101c0, 0x0}, + {0x2101c0, 0x0}, + {0x0102c0, 0x0}, + {0x1102c0, 0x0}, + {0x2102c0, 0x0}, + {0x0103c0, 0x0}, + {0x1103c0, 0x0}, + {0x2103c0, 0x0}, + {0x0104c0, 0x0}, + {0x1104c0, 0x0}, + {0x2104c0, 0x0}, + {0x0105c0, 0x0}, + {0x1105c0, 0x0}, + {0x2105c0, 0x0}, + {0x0106c0, 0x0}, + {0x1106c0, 0x0}, + {0x2106c0, 0x0}, + {0x0107c0, 0x0}, + {0x1107c0, 0x0}, + {0x2107c0, 0x0}, + {0x0108c0, 0x0}, + {0x1108c0, 0x0}, + {0x2108c0, 0x0}, + {0x0110c0, 0x0}, + {0x1110c0, 0x0}, + {0x2110c0, 0x0}, + {0x0111c0, 0x0}, + {0x1111c0, 0x0}, + {0x2111c0, 0x0}, + {0x0112c0, 0x0}, + {0x1112c0, 0x0}, + {0x2112c0, 0x0}, + {0x0113c0, 0x0}, + {0x1113c0, 0x0}, + {0x2113c0, 0x0}, + {0x0114c0, 0x0}, + {0x1114c0, 0x0}, + {0x2114c0, 0x0}, + {0x0115c0, 0x0}, + {0x1115c0, 0x0}, + {0x2115c0, 0x0}, + {0x0116c0, 0x0}, + {0x1116c0, 0x0}, + {0x2116c0, 0x0}, + {0x0117c0, 0x0}, + {0x1117c0, 0x0}, + {0x2117c0, 0x0}, + {0x0118c0, 0x0}, + {0x1118c0, 0x0}, + {0x2118c0, 0x0}, + {0x0100c1, 0x0}, + {0x1100c1, 0x0}, + {0x2100c1, 0x0}, + {0x0101c1, 0x0}, + {0x1101c1, 0x0}, + {0x2101c1, 0x0}, + {0x0102c1, 0x0}, + {0x1102c1, 0x0}, + {0x2102c1, 0x0}, + {0x0103c1, 0x0}, + {0x1103c1, 0x0}, + {0x2103c1, 0x0}, + {0x0104c1, 0x0}, + {0x1104c1, 0x0}, + {0x2104c1, 0x0}, + {0x0105c1, 0x0}, + {0x1105c1, 0x0}, + {0x2105c1, 0x0}, + {0x0106c1, 0x0}, + {0x1106c1, 0x0}, + {0x2106c1, 0x0}, + {0x0107c1, 0x0}, + {0x1107c1, 0x0}, + {0x2107c1, 0x0}, + {0x0108c1, 0x0}, + {0x1108c1, 0x0}, + {0x2108c1, 0x0}, + {0x0110c1, 0x0}, + {0x1110c1, 0x0}, + {0x2110c1, 0x0}, + {0x0111c1, 0x0}, + {0x1111c1, 0x0}, + {0x2111c1, 0x0}, + {0x0112c1, 0x0}, + {0x1112c1, 0x0}, + {0x2112c1, 0x0}, + {0x0113c1, 0x0}, + {0x1113c1, 0x0}, + {0x2113c1, 0x0}, + {0x0114c1, 0x0}, + {0x1114c1, 0x0}, + {0x2114c1, 0x0}, + {0x0115c1, 0x0}, + {0x1115c1, 0x0}, + {0x2115c1, 0x0}, + {0x0116c1, 0x0}, + {0x1116c1, 0x0}, + {0x2116c1, 0x0}, + {0x0117c1, 0x0}, + {0x1117c1, 0x0}, + {0x2117c1, 0x0}, + {0x0118c1, 0x0}, + {0x1118c1, 0x0}, + {0x2118c1, 0x0}, + {0x010020, 0x0}, + {0x110020, 0x0}, + {0x210020, 0x0}, + {0x011020, 0x0}, + {0x111020, 0x0}, + {0x211020, 0x0}, + {0x020072, 0x0}, + {0x020073, 0x0}, + {0x020074, 0x0}, + {0x0100aa, 0x0}, + {0x0110aa, 0x0}, + {0x020010, 0x0}, + {0x120010, 0x0}, + {0x220010, 0x0}, + {0x020011, 0x0}, + {0x120011, 0x0}, + {0x220011, 0x0}, + {0x0100ae, 0x0}, + {0x1100ae, 0x0}, + {0x2100ae, 0x0}, + {0x0100af, 0x0}, + {0x1100af, 0x0}, + {0x2100af, 0x0}, + {0x0110ae, 0x0}, + {0x1110ae, 0x0}, + {0x2110ae, 0x0}, + {0x0110af, 0x0}, + {0x1110af, 0x0}, + {0x2110af, 0x0}, + {0x020020, 0x0}, + {0x120020, 0x0}, + {0x220020, 0x0}, + {0x0100a0, 0x0}, + {0x0100a1, 0x0}, + {0x0100a2, 0x0}, + {0x0100a3, 0x0}, + {0x0100a4, 0x0}, + {0x0100a5, 0x0}, + {0x0100a6, 0x0}, + {0x0100a7, 0x0}, + {0x0110a0, 0x0}, + {0x0110a1, 0x0}, + {0x0110a2, 0x0}, + {0x0110a3, 0x0}, + {0x0110a4, 0x0}, + {0x0110a5, 0x0}, + {0x0110a6, 0x0}, + {0x0110a7, 0x0}, + {0x02007c, 0x0}, + {0x12007c, 0x0}, + {0x22007c, 0x0}, + {0x02007d, 0x0}, + {0x12007d, 0x0}, + {0x22007d, 0x0}, + {0x0400fd, 0x0}, + {0x0400c0, 0x0}, + {0x090201, 0x0}, + {0x190201, 0x0}, + {0x290201, 0x0}, + {0x090202, 0x0}, + {0x190202, 0x0}, + {0x290202, 0x0}, + {0x090203, 0x0}, + {0x190203, 0x0}, + {0x290203, 0x0}, + {0x090204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x090205, 0x0}, + {0x190205, 0x0}, + {0x290205, 0x0}, + {0x090206, 0x0}, + {0x190206, 0x0}, + {0x290206, 0x0}, + {0x090207, 0x0}, + {0x190207, 0x0}, + {0x290207, 0x0}, + {0x090208, 0x0}, + {0x190208, 0x0}, + {0x290208, 0x0}, + {0x010062, 0x0}, + {0x010162, 0x0}, + {0x010262, 0x0}, + {0x010362, 0x0}, + {0x010462, 0x0}, + {0x010562, 0x0}, + {0x010662, 0x0}, + {0x010762, 0x0}, + {0x010862, 0x0}, + {0x011062, 0x0}, + {0x011162, 0x0}, + {0x011262, 0x0}, + {0x011362, 0x0}, + {0x011462, 0x0}, + {0x011562, 0x0}, + {0x011662, 0x0}, + {0x011762, 0x0}, + {0x011862, 0x0}, + {0x020077, 0x0}, + {0x010001, 0x0}, + {0x011001, 0x0}, + {0x010040, 0x0}, + {0x010140, 0x0}, + {0x010240, 0x0}, + {0x010340, 0x0}, + {0x010440, 0x0}, + {0x010540, 0x0}, + {0x010640, 0x0}, + {0x010740, 0x0}, + {0x010840, 0x0}, + {0x010030, 0x0}, + {0x010130, 0x0}, + {0x010230, 0x0}, + {0x010330, 0x0}, + {0x010430, 0x0}, + {0x010530, 0x0}, + {0x010630, 0x0}, + {0x010730, 0x0}, + {0x010830, 0x0}, + {0x011040, 0x0}, + {0x011140, 0x0}, + {0x011240, 0x0}, + {0x011340, 0x0}, + {0x011440, 0x0}, + {0x011540, 0x0}, + {0x011640, 0x0}, + {0x011740, 0x0}, + {0x011840, 0x0}, + {0x011030, 0x0}, + {0x011130, 0x0}, + {0x011230, 0x0}, + {0x011330, 0x0}, + {0x011430, 0x0}, + {0x011530, 0x0}, + {0x011630, 0x0}, + {0x011730, 0x0}, + {0x011830, 0x0}, +}; + +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x12a4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x12a4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0xa400 }, + { 0x54033, 0x3112 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xa400 }, + { 0x54039, 0x3112 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x12a4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x12a4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x54032, 0xa400 }, + { 0x54033, 0x3112 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xa400 }, + { 0x54039, 0x3112 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x109 }, + { 0x90035, 0x2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x139 }, + { 0x90038, 0xb }, + { 0x90039, 0x7c0 }, + { 0x9003a, 0x139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x633 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x14f }, + { 0x9003f, 0x630 }, + { 0x90040, 0x159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x633 }, + { 0x90043, 0x149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x633 }, + { 0x90046, 0x179 }, + { 0x90047, 0x8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x7c8 }, + { 0x9004c, 0x109 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x1 }, + { 0x9004f, 0x8 }, + { 0x90050, 0x0 }, + { 0x90051, 0x45a }, + { 0x90052, 0x9 }, + { 0x90053, 0x0 }, + { 0x90054, 0x448 }, + { 0x90055, 0x109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x633 }, + { 0x90058, 0x179 }, + { 0x90059, 0x1 }, + { 0x9005a, 0x618 }, + { 0x9005b, 0x109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x633 }, + { 0x9005e, 0x149 }, + { 0x9005f, 0x8 }, + { 0x90060, 0x4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x633 }, + { 0x90064, 0x149 }, + { 0x90065, 0x0 }, + { 0x90066, 0x4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x633 }, + { 0x9006a, 0x149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0x0 }, + { 0x9006f, 0x4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x549 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0xd49 }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x94a }, + { 0x90078, 0x633 }, + { 0x90079, 0x159 }, + { 0x9007a, 0x441 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x1 }, + { 0x90081, 0x633 }, + { 0x90082, 0x149 }, + { 0x90083, 0x0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x109 }, + { 0x90086, 0xa }, + { 0x90087, 0x10 }, + { 0x90088, 0x109 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x149 }, + { 0x9008c, 0x9 }, + { 0x9008d, 0x3c0 }, + { 0x9008e, 0x159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x109 }, + { 0x90092, 0x0 }, + { 0x90093, 0x3c0 }, + { 0x90094, 0x109 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 0x4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0xb }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x1 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x5 }, + { 0x900a2, 0x7c0 }, + { 0x900a3, 0x109 }, + { 0x40000, 0x811 }, + { 0x40020, 0x880 }, + { 0x40040, 0x0 }, + { 0x40060, 0x0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0x0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0x0 }, + { 0x40003, 0x811 }, + { 0x40023, 0x880 }, + { 0x40043, 0x0 }, + { 0x40063, 0x0 }, + { 0x40004, 0x720 }, + { 0x40024, 0xf }, + { 0x40044, 0x1740 }, + { 0x40064, 0x0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0x0 }, + { 0x40006, 0x716 }, + { 0x40026, 0xf }, + { 0x40046, 0x2001 }, + { 0x40066, 0x0 }, + { 0x40007, 0x716 }, + { 0x40027, 0xf }, + { 0x40047, 0x2800 }, + { 0x40067, 0x0 }, + { 0x40008, 0x716 }, + { 0x40028, 0xf }, + { 0x40048, 0xf00 }, + { 0x40068, 0x0 }, + { 0x40009, 0x720 }, + { 0x40029, 0xf }, + { 0x40049, 0x1400 }, + { 0x40069, 0x0 }, + { 0x4000a, 0xe08 }, + { 0x4002a, 0xc15 }, + { 0x4004a, 0x0 }, + { 0x4006a, 0x0 }, + { 0x4000b, 0x625 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0x0 }, + { 0x4006b, 0x0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0x0 }, + { 0x4006c, 0x0 }, + { 0x4000d, 0xe08 }, + { 0x4002d, 0xc1a }, + { 0x4004d, 0x0 }, + { 0x4006d, 0x0 }, + { 0x4000e, 0x625 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0x0 }, + { 0x4006e, 0x0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0x0 }, + { 0x4006f, 0x0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0x0 }, + { 0x40070, 0x0 }, + { 0x40011, 0x708 }, + { 0x40031, 0x5 }, + { 0x40051, 0x0 }, + { 0x40071, 0x2002 }, + { 0x40012, 0x8 }, + { 0x40032, 0x80 }, + { 0x40052, 0x0 }, + { 0x40072, 0x0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0x0 }, + { 0x40073, 0x0 }, + { 0x40014, 0x708 }, + { 0x40034, 0xa }, + { 0x40054, 0x0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0x0 }, + { 0x40075, 0x0 }, + { 0x40016, 0x60a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0x0 }, + { 0x40017, 0x61a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0x0 }, + { 0x40018, 0x60a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0x0 }, + { 0x40019, 0x642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0x0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x880 }, + { 0x4005a, 0x0 }, + { 0x4007a, 0x0 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x790 }, + { 0x900a6, 0x11a }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x7aa }, + { 0x900a9, 0x2a }, + { 0x900aa, 0x10 }, + { 0x900ab, 0x7b2 }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x0 }, + { 0x900ae, 0x7c8 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x10 }, + { 0x900b1, 0x10 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xd }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x448 }, + { 0x90169, 0x109 }, + { 0x9016a, 0xf }, + { 0x9016b, 0x7c0 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0x0 }, + { 0x9016e, 0xe8 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x47 }, + { 0x90171, 0x630 }, + { 0x90172, 0x109 }, + { 0x90173, 0x8 }, + { 0x90174, 0x618 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0xe0 }, + { 0x90178, 0x109 }, + { 0x90179, 0x0 }, + { 0x9017a, 0x7c8 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x8 }, + { 0x9017d, 0x8140 }, + { 0x9017e, 0x10c }, + { 0x9017f, 0x0 }, + { 0x90180, 0x1 }, + { 0x90181, 0x8 }, + { 0x90182, 0x8 }, + { 0x90183, 0x4 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x7c8 }, + { 0x90187, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x29 }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x32 }, + { 0x2000c, 0x64 }, + { 0x2000d, 0x3e8 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x2060 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 400mts 1D */ + .drate = 400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 100mts 1D */ + .drate = 100, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 1600mts 2D */ + .drate = 1600, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 1600, 400, 100, }, +}; + diff --git a/board/freescale/imx8mn_evk/spl.c b/board/freescale/imx8mn_evk/spl.c index 6d5c7a5b467..1c4f537a18a 100644 --- a/board/freescale/imx8mn_evk/spl.c +++ b/board/freescale/imx8mn_evk/spl.c @@ -21,16 +21,45 @@ #include #include +#include +#include +#include #include #include #include #include +#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; int spl_board_boot_device(enum boot_device boot_dev_spl) { +#ifdef CONFIG_SPL_BOOTROM_SUPPORT return BOOT_DEVICE_BOOTROM; +#else + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +#endif } void spl_dram_init(void) @@ -38,64 +67,132 @@ void spl_dram_init(void) ddr_init(&dram_timing); } -void spl_board_init(void) +#if CONFIG_IS_ENABLED(DM_PMIC_BD71837) +int power_init_board(void) { struct udevice *dev; int ret; - puts("Normal Boot\n"); + ret = pmic_get("pmic@4b", &dev); + if (ret == -ENODEV) { + puts("No pmic@4b\n"); + return 0; + } + if (ret != 0) + return ret; - ret = uclass_get_device_by_name(UCLASS_CLK, - "clock-controller@30380000", - &dev); - if (ret < 0) - printf("Failed to find clock node. Check device tree\n"); -} + /* decrease RESET key long push time from the default 10s to 10ms */ + pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0); -#ifdef CONFIG_SPL_LOAD_FIT -int board_fit_config_name_match(const char *name) -{ - /* Just empty function now - can't decide what to choose */ - debug("%s: %s\n", __func__, name); + /* unlock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x1); + + /* Set VDD_ARM to typical value 0.85v for 1.2Ghz */ + pmic_reg_write(dev, BD718XX_BUCK2_VOLT_RUN, 0xf); + +#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE + /* Set VDD_SOC/VDD_DRAM to typical value 0.8v for low drive mode */ + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0xa); +#else + /* Set VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */ + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0xf); +#endif /* CONFIG_IMX8MN_LOW_DRIVE_MODE */ + + /* Set VDD_SOC 0.75v for low-v suspend */ + pmic_reg_write(dev, BD718XX_BUCK1_VOLT_SUSP, 0x5); + + /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ + pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28); + + /* lock the PMIC regs */ + pmic_reg_write(dev, BD718XX_REGLOCK, 0x11); return 0; } #endif -#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) -#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) +int power_init_board(void) +{ + struct udevice *dev; + int ret; -static iomux_v3_cfg_t const uart_pads[] = { - IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), - IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), -}; + ret = pmic_get("pca9450@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + +#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE + /* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10); +#elif defined(CONFIG_TARGET_IMX8MN_DDR3_EVK) + /* Set VDD_SOC to 0.85v for DDR3L at 1600MTS */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); + + /* Disable the BUCK2 */ + pmic_reg_write(dev, PCA9450_BUCK2CTRL, 0x48); + + /* Set NVCC_DRAM to 1.35v */ + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x1E); +#else + /* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); +#endif + /* Set DVS1 to 0.75v for low-v suspend */ + /* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0xC); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); -static iomux_v3_cfg_t const wdog_pads[] = { - IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), -}; + /* set VDD_SNVS_0V8 from default 0.85V */ + pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0); -int board_early_init_f(void) -{ - struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + /* enable LDO4 to 1.2v */ + pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44); - imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + /* set WDOG_B_CFG to cold reset */ + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); - set_wdog_reset(wdog); + return 0; +} +#endif - imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); +void spl_board_init(void) +{ + struct udevice *dev; + uclass_find_first_device(UCLASS_MISC, &dev); - init_uart_clk(1); + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); return 0; } +#endif void board_init_f(ulong dummy) { + struct udevice *dev; int ret; - arch_cpu_init(); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); - init_uart_clk(1); + arch_cpu_init(); board_early_init_f(); @@ -103,19 +200,41 @@ void board_init_f(ulong dummy) preloader_console_init(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - ret = spl_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); hang(); } enable_tzc380(); + power_init_board(); + /* DDR initialization */ spl_dram_init(); board_init_r(NULL, 0); } +#ifdef CONFIG_SPL_MMC_SUPPORT + +#define UBOOT_RAW_SECTOR_OFFSET 0x40 +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) +{ + u32 boot_dev = spl_boot_device(); + switch (boot_dev) { + case BOOT_DEVICE_MMC1: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; + case BOOT_DEVICE_MMC2: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET; + } + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; +} +#endif diff --git a/board/freescale/imx8mp_evk/Kconfig b/board/freescale/imx8mp_evk/Kconfig index 49bb29a45d8..072caa360b4 100644 --- a/board/freescale/imx8mp_evk/Kconfig +++ b/board/freescale/imx8mp_evk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8MP_EVK +if TARGET_IMX8MP_EVK || TARGET_IMX8MP_DDR4_EVK config SYS_BOARD default "imx8mp_evk" diff --git a/board/freescale/imx8mp_evk/Makefile b/board/freescale/imx8mp_evk/Makefile index 106bf9a1edf..1970dc4132c 100644 --- a/board/freescale/imx8mp_evk/Makefile +++ b/board/freescale/imx8mp_evk/Makefile @@ -9,4 +9,5 @@ obj-y += imx8mp_evk.o ifdef CONFIG_SPL_BUILD obj-y += spl.o obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o endif diff --git a/board/freescale/imx8mp_evk/ddr4_timing.c b/board/freescale/imx8mp_evk/ddr4_timing.c new file mode 100644 index 00000000000..3e3cc01bcca --- /dev/null +++ b/board/freescale/imx8mp_evk/ddr4_timing.c @@ -0,0 +1,1311 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + * For imx_v2019.04_5.4.x and above version: + * please replace #include with #include + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0x81040010 }, + { 0x3d400030, 0xaa }, + { 0x3d400034, 0x221306 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x0 }, + { 0x3d400064, 0xc30118 }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400070, 0x1027f54 }, +#else + { 0x3d400070, 0x1027f10 }, +#endif + { 0x3d400074, 0x7b0 }, + { 0x3d4000d0, 0xc0030188 }, + { 0x3d4000d4, 0x9e0000 }, + { 0x3d4000dc, 0xc500501 }, + { 0x3d4000e0, 0x280400 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000600 }, + { 0x3d4000ec, 0x1010 }, + { 0x3d4000f0, 0x20 }, + { 0x3d4000f4, 0xec7 }, + { 0x3d400100, 0x1618361a }, + { 0x3d400104, 0x50626 }, + { 0x3d400108, 0x80b0610 }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0xc04060d }, + { 0x3d400114, 0x8080504 }, + { 0x3d40011c, 0x808 }, + { 0x3d400120, 0x6060d0a }, + { 0x3d400124, 0x2050c }, + { 0x3d40012c, 0x160b010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x61a8 }, + { 0x3d400190, 0x391820b }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0x110b }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x1f }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400204, 0x3f0505 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x14141400 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x4040403 }, + { 0x3d400218, 0x4040404 }, + { 0x3d40021c, 0xf04 }, +#else + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf07 }, +#endif + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000618 }, + { 0x3d400244, 0x1323 }, + { 0x3d400250, 0x00001a05 }, + { 0x3d400254, 0x1f }, + { 0x3d40025c, 0x10000010 }, + { 0x3d400264, 0x100000ff }, + { 0x3d40026c, 0x100002ff }, + { 0x3d40036c, 0x0 }, + { 0x3d400400, 0x100 }, + { 0x3d400404, 0x72ff }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x40005e }, + { 0x3d4020dc, 0x40501 }, + { 0x3d4020e0, 0x0 }, + { 0x3d4020e8, 0x2000600 }, + { 0x3d4020ec, 0x10 }, + { 0x3d402100, 0xb081209 }, + { 0x3d402104, 0x2020d }, + { 0x3d402108, 0x5050309 }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x4030205 }, + { 0x3d402114, 0x3030202 }, + { 0x3d40211c, 0x303 }, + { 0x3d402120, 0x3030d04 }, + { 0x3d402124, 0x20208 }, + { 0x3d40212c, 0x1005010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3858204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x504 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000604 }, + { 0x3d4020f4, 0xec7 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2df }, + { 0x1015f, 0x2df }, + { 0x1105f, 0x2df }, + { 0x1115f, 0x2df }, + { 0x1205f, 0x2df }, + { 0x1215f, 0x2df }, + { 0x1305f, 0x2df }, + { 0x1315f, 0x2df }, + { 0x11005f, 0x2df }, + { 0x11015f, 0x2df }, + { 0x11105f, 0x2df }, + { 0x11115f, 0x2df }, + { 0x11205f, 0x2df }, + { 0x11215f, 0x2df }, + { 0x11305f, 0x2df }, + { 0x11315f, 0x2df }, + { 0x55, 0x355 }, + { 0x1055, 0x355 }, + { 0x2055, 0x355 }, + { 0x3055, 0x355 }, + { 0x4055, 0x55 }, + { 0x5055, 0x55 }, + { 0x6055, 0x355 }, + { 0x7055, 0x355 }, + { 0x8055, 0x355 }, + { 0x9055, 0x355 }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x7 }, + { 0x120056, 0xa }, + { 0x1004d, 0x1a }, + { 0x1014d, 0x1a }, + { 0x1104d, 0x1a }, + { 0x1114d, 0x1a }, + { 0x1204d, 0x1a }, + { 0x1214d, 0x1a }, + { 0x1304d, 0x1a }, + { 0x1314d, 0x1a }, + { 0x11004d, 0x1a }, + { 0x11014d, 0x1a }, + { 0x11104d, 0x1a }, + { 0x11114d, 0x1a }, + { 0x11204d, 0x1a }, + { 0x11214d, 0x1a }, + { 0x11304d, 0x1a }, + { 0x11314d, 0x1a }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x43, 0xe7 }, + { 0x1043, 0xe7 }, + { 0x2043, 0xe7 }, + { 0x3043, 0xe7 }, + { 0x4043, 0xe7 }, + { 0x5043, 0xe7 }, + { 0x6043, 0xe7 }, + { 0x7043, 0xe7 }, + { 0x8043, 0xe7 }, + { 0x9043, 0xe7 }, + { 0x20018, 0x5 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x320 }, + { 0x120008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x248 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x12043, 0x5b1 }, + { 0x12143, 0x5b1 }, + { 0x13043, 0x5b1 }, + { 0x13143, 0x5b1 }, + { 0x1200b2, 0x248 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x112043, 0x5b1 }, + { 0x112143, 0x5b1 }, + { 0x113043, 0x5b1 }, + { 0x113143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x2007d, 0x212 }, + { 0x12007d, 0x212 }, + { 0x2007c, 0x61 }, + { 0x12007c, 0x61 }, + { 0x1004a, 0x500 }, + { 0x1104a, 0x500 }, + { 0x1204a, 0x500 }, + { 0x1304a, 0x500 }, + { 0x2002c, 0x0 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 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0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2230 }, + { 0x54006, 0x25b }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0xc50 }, + { 0x54030, 0x501 }, + { 0x54031, 0x28 }, + { 0x54032, 0x400 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x1010 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54002, 0x1 }, + { 0x54003, 0x42a }, + { 0x54004, 0x2 }, + { 0x54005, 0x2230 }, + { 0x54006, 0x25b }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x4 }, + { 0x54030, 0x501 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x10 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54003, 0xc80 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2230 }, + { 0x54006, 0x25b }, + { 0x54007, 0x2000 }, + { 0x54008, 0x101 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0xc8 }, + { 0x5400d, 0x100 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0xc50 }, + { 0x54030, 0x501 }, + { 0x54031, 0x28 }, + { 0x54032, 0x400 }, + { 0x54033, 0x200 }, + { 0x54034, 0x600 }, + { 0x54035, 0x1010 }, + { 0x54036, 0x101 }, + { 0x5403f, 0x1221 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xb }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x633 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x633 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x633 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x633 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x633 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x633 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x633 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x633 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x633 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x633 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x633 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x633 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x633 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xb }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x1 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x5 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x0 }, + { 0x900a2, 0x8140 }, + { 0x900a3, 0x10c }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x8138 }, + { 0x900a6, 0x104 }, + { 0x900a7, 0x8 }, + { 0x900a8, 0x448 }, + { 0x900a9, 0x109 }, + { 0x900aa, 0xf }, + { 0x900ab, 0x7c0 }, + { 0x900ac, 0x109 }, + { 0x900ad, 0x47 }, + { 0x900ae, 0x630 }, + { 0x900af, 0x109 }, + { 0x900b0, 0x8 }, + { 0x900b1, 0x618 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x8 }, + { 0x900b4, 0xe0 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x0 }, + { 0x900b7, 0x7c8 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x8 }, + { 0x900ba, 0x8140 }, + { 0x900bb, 0x10c }, + { 0x900bc, 0x0 }, + { 0x900bd, 0x478 }, + { 0x900be, 0x109 }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x1 }, + { 0x900c1, 0x8 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2a }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x7d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x21 }, + { 0x12000c, 0x42 }, + { 0x12000d, 0x29a }, + { 0x12000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0x20089, 0x1 }, + { 0x20088, 0x19 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1066mts 1D */ + .drate = 1066, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3200, 1066, }, +}; + +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC +void board_dram_ecc_scrub(void) +{ + ddrc_inline_ecc_scrub(0x0,0x7ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xfffffff); + ddrc_inline_ecc_scrub(0x10000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1fffffff); + ddrc_inline_ecc_scrub(0x20000000,0x27ffffff); + ddrc_inline_ecc_scrub(0x28000000,0x2fffffff); + ddrc_inline_ecc_scrub(0x30000000,0x37ffffff); + ddrc_inline_ecc_scrub_end(0x0,0x3fffffff); +} +#endif diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c b/board/freescale/imx8mp_evk/imx8mp_evk.c index 89cc17cbeac..c4997439cca 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.c +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c @@ -11,12 +11,23 @@ #include #include #include +#include #include #include #include #include #include #include +#include +#include +#include +#include +#include "../common/tcpc.h" +#include +#include +#include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -32,6 +43,14 @@ static iomux_v3_cfg_t const wdog_pads[] = { MX8MP_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; +#ifdef CONFIG_NAND_MXS + +static void setup_gpmi_nand(void) +{ + init_nand_clk(); +} +#endif + int board_early_init_f(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; @@ -42,41 +61,364 @@ int board_early_init_f(void) imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + init_uart_clk(1); + return 0; } -static void setup_fec(void) +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) { - struct iomuxc_gpr_base_regs *gpr = - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC +#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK + int rc; + phys_addr_t ecc_start = 0x120000000; + size_t ecc_size = 0x20000000; - /* Enable RGMII TX clk output */ - setbits_le32(&gpr->gpr[1], BIT(22)); + rc = add_res_mem_dt_node(blob, "ecc", ecc_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc reserved-memory node.\n"); + return rc; + } +#else + int rc; + phys_addr_t ecc0_start = 0xb0000000; + phys_addr_t ecc1_start = 0x130000000; + phys_addr_t ecc2_start = 0x1b0000000; + size_t ecc_size = 0x10000000; + + rc = add_res_mem_dt_node(blob, "ecc", ecc0_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc0 reserved-memory node.\n"); + return rc; + } + + rc = add_res_mem_dt_node(blob, "ecc", ecc1_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc1 reserved-memory node.\n"); + return rc; + } + + rc = add_res_mem_dt_node(blob, "ecc", ecc2_start, ecc_size); + if (rc < 0) { + printf("Could not create ecc2 reserved-memory node.\n"); + return rc; + } +#endif +#endif + + return 0; +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port1; +struct tcpc_port port2; + +static int setup_pd_switch(uint8_t i2c_bus, uint8_t addr) +{ + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + uint8_t valb; + + ret = uclass_get_device_by_seq(UCLASS_I2C, i2c_bus, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, addr, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, addr); + return -ENODEV; + } + + ret = dm_i2c_read(i2c_dev, 0xB, &valb, 1); + if (ret) { + printf("%s dm_i2c_read failed, err %d\n", __func__, ret); + return -EIO; + } + valb |= 0x4; /* Set DB_EXIT to exit dead battery mode */ + ret = dm_i2c_write(i2c_dev, 0xB, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + /* Set OVP threshold to 23V */ + valb = 0x6; + ret = dm_i2c_write(i2c_dev, 0x8, (const uint8_t *)&valb, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + return 0; } -#define EQOS_RST_PAD IMX_GPIO_NR(4, 22) -static iomux_v3_cfg_t const eqos_rst_pads[] = { - MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +int pd_switch_snk_enable(struct tcpc_port *port) +{ + if (port == &port1) { + debug("Setup pd switch on port 1\n"); + return setup_pd_switch(1, 0x72); + } else + return -EINVAL; +} + +/* Port2 is the power supply, port 1 does not support power */ +struct tcpc_port_config port1_config = { + .i2c_bus = 1, /*i2c2*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 45000, + .op_snk_mv = 15000, + .switch_setup_func = &pd_switch_snk_enable, + .disable_pd = true, +}; + +struct tcpc_port_config port2_config = { + .i2c_bus = 2, /*i2c3*/ + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 45000, + .op_snk_mv = 15000, }; -static void setup_iomux_eqos(void) +#define USB_TYPEC_SEL IMX_GPIO_NR(4, 20) +#define USB_TYPEC_EN IMX_GPIO_NR(2, 20) + +static iomux_v3_cfg_t ss_mux_gpio[] = { + MX8MP_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX8MP_PAD_SD2_WP__GPIO2_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void ss_mux_select(enum typec_cc_polarity pol) { - imx_iomux_v3_setup_multiple_pads(eqos_rst_pads, - ARRAY_SIZE(eqos_rst_pads)); + if (pol == TYPEC_POLARITY_CC1) + gpio_direction_output(USB_TYPEC_SEL, 0); + else + gpio_direction_output(USB_TYPEC_SEL, 1); +} + +static int setup_typec(void) +{ + int ret; + struct gpio_desc per_12v_desc; + + debug("tcpc_init port 2\n"); + ret = tcpc_init(&port2, port2_config, NULL); + if (ret) { + printf("%s: tcpc port2 init failed, err=%d\n", + __func__, ret); + } else if (tcpc_pd_sink_check_charging(&port2)) { + printf("Power supply on USB2\n"); + + /* Enable PER 12V, any check before it? */ + ret = dm_gpio_lookup_name("gpio@20_1", &per_12v_desc); + if (ret) { + printf("%s lookup gpio@20_1 failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + ret = dm_gpio_request(&per_12v_desc, "per_12v_en"); + if (ret) { + printf("%s request per_12v failed ret = %d\n", __func__, ret); + return -EIO; + } + + /* Enable PER 12V regulator */ + dm_gpio_set_dir_flags(&per_12v_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + } + + debug("tcpc_init port 1\n"); + imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + gpio_request(USB_TYPEC_SEL, "typec_sel"); + gpio_request(USB_TYPEC_EN, "typec_en"); + gpio_direction_output(USB_TYPEC_EN, 0); + + ret = tcpc_init(&port1, port1_config, &ss_mux_select); + if (ret) { + printf("%s: tcpc port1 init failed, err=%d\n", + __func__, ret); + } else { + return ret; + } - gpio_request(EQOS_RST_PAD, "eqos_rst"); - gpio_direction_output(EQOS_RST_PAD, 0); - mdelay(15); - gpio_direction_output(EQOS_RST_PAD, 1); - mdelay(100); + return ret; } +#endif -static int setup_eqos(void) +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +#define USB_PHY_CTRL6 0xF0058 + +#define HSIO_GPR_BASE (0x32F10000U) +#define HSIO_GPR_REG_0 (HSIO_GPR_BASE) +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1) +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT) + + +static struct dwc3_device dwc3_device_data = { +#ifdef CONFIG_SPL_BUILD + .maximum_speed = USB_SPEED_HIGH, +#else + .maximum_speed = USB_SPEED_SUPER, +#endif + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(int index) +{ + dwc3_uboot_handle_interrupt(index); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + /* enable usb clock via hsio gpr */ + RegData = readl(HSIO_GPR_REG_0); + RegData |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN; + writel(RegData, HSIO_GPR_REG_0); + + /* USB3.0 PHY signal fsel for 100M ref */ + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData = (RegData & 0xfffff81f) | (0x2a<<5); + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL6); + RegData &=~0x1; + writel(RegData, dwc3->base + USB_PHY_CTRL6); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) +#define USB2_PWR_EN IMX_GPIO_NR(1, 14) +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + imx8m_usb_power(index, true); + + if (index == 0 && init == USB_INIT_DEVICE) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port1); + if (ret) + return ret; +#endif + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port1); +#endif + return ret; + } else if (index == 1 && init == USB_INIT_HOST) { + /* Enable GPIO1_IO14 for 5V VBUS */ + gpio_request(USB2_PWR_EN, "usb2_pwr"); + gpio_direction_output(USB2_PWR_EN, 1); + } + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port1); +#endif + } else if (index == 1 && init == USB_INIT_HOST) { + /* Disable GPIO1_IO14 for 5V VBUS */ + gpio_direction_output(USB2_PWR_EN, 0); + } + + imx8m_usb_power(index, false); + + return ret; +} + +#ifdef CONFIG_USB_TCPC +/* Not used so far */ +int board_typec_get_mode(int index) +{ + int ret = 0; + enum typec_cc_polarity pol; + enum typec_cc_state state; + + if (index == 0) { + tcpc_setup_ufp_mode(&port1); + + ret = tcpc_get_cc_status(&port1, &pol, &state); + if (!ret) { + if (state == TYPEC_STATE_SRC_RD_RA || state == TYPEC_STATE_SRC_RD) + return USB_INIT_HOST; + } + + return USB_INIT_DEVICE; + } else { + return USB_INIT_HOST; + } +} +#endif +#endif + +static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; - setup_iomux_eqos(); + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); +} + +static int setup_eqos(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; /* set INTF as RGMII, enable RGMII TXC clock */ clrsetbits_le32(&gpr->gpr[1], @@ -95,22 +437,47 @@ int board_phy_config(struct phy_device *phydev) } #endif +#define DISPMIX 13 +#define MIPI 15 + int board_init(void) { - int ret = 0; + struct arm_smccc_res res; + +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif if (CONFIG_IS_ENABLED(FEC_MXC)) { setup_fec(); + } - if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) - ret = setup_eqos(); + if (CONFIG_IS_ENABLED(DWC_ETH_QOS)) { + setup_eqos(); } - return ret; +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) + init_usb_clk(); +#endif + + /* enable the dispmix & mipi phy power domain */ + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + DISPMIX, true, 0, 0, 0, 0, &res); + arm_smccc_smc(IMX_SIP_GPC, IMX_SIP_GPC_PM_DOMAIN, + MIPI, true, 0, 0, 0, 0, &res); + + return 0; } int board_late_init(void) { +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "EVK"); env_set("board_rev", "iMX8MP"); @@ -118,3 +485,43 @@ int board_late_init(void) return 0; } + +#ifdef CONFIG_IMX_BOOTAUX +ulong board_get_usable_ram_top(ulong total_size) +{ + /* Reserve 16M memory used by M core vring/buffer, which begins at 16MB before optee */ + if (rom_pointer[1]) + return gd->ram_top - SZ_16M; + + return gd->ram_top; +} +#endif + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); +} +#endif + +#ifdef CONFIG_SPL_MMC_SUPPORT +#define UBOOT_RAW_SECTOR_OFFSET 0x40 +unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc) +{ + u32 boot_dev = spl_boot_device(); + switch (boot_dev) { + case BOOT_DEVICE_MMC2: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR - UBOOT_RAW_SECTOR_OFFSET; + default: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR; + } +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /* TODO */ +} +#endif /* CONFIG_ANDROID_RECOVERY */ +#endif /* CONFIG_FSL_FASTBOOT */ diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c old mode 100644 new mode 100755 index 7658262b37d..ea63d54eab0 --- a/board/freescale/imx8mp_evk/lpddr4_timing.c +++ b/board/freescale/imx8mp_evk/lpddr4_timing.c @@ -11,15 +11,51 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400304, 0x1 }, { 0x3d400030, 0x1 }, { 0x3d400000, 0xa3080020 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x124f800 }, + { 0x3d400064, 0x4900a8 }, + { 0x3d400070, 0x1027f90 }, + { 0x3d400074, 0x790 }, + { 0x3d4000d0, 0xc0030495 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0xc40024 }, +#else { 0x3d400020, 0x1323 }, { 0x3d400024, 0x1e84800 }, - { 0x3d400064, 0x7a0118 }, + { 0x3d400064, 0x7a017c }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400070, 0x1027f54 }, +#else + { 0x3d400070, 0x1027f10 }, +#endif + { 0x3d400074, 0x7b0 }, { 0x3d4000d0, 0xc00307a3 }, { 0x3d4000d4, 0xc50000 }, { 0x3d4000dc, 0xf4003f }, +#endif { 0x3d4000e0, 0x330000 }, - { 0x3d4000e8, 0x460048 }, - { 0x3d4000ec, 0x150048 }, + { 0x3d4000e8, 0x660048 }, + { 0x3d4000ec, 0x160048 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400100, 0x1618141a }, + { 0x3d400104, 0x504a6 }, + { 0x3d40010c, 0x909000 }, + { 0x3d400110, 0xb04060b }, + { 0x3d400114, 0x2030909 }, + { 0x3d400118, 0x1010006 }, + { 0x3d40011c, 0x301 }, + { 0x3d400130, 0x20500 }, + { 0x3d400134, 0xb100002 }, + { 0x3d400138, 0xad }, + { 0x3d400144, 0x78003c }, + { 0x3d400180, 0x2580012 }, + { 0x3d400184, 0x1e0493e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x4938208 }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x1308 }, +#else { 0x3d400100, 0x2028222a }, { 0x3d400104, 0x807bf }, { 0x3d40010c, 0xe0e000 }, @@ -29,7 +65,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40011c, 0x501 }, { 0x3d400130, 0x20800 }, { 0x3d400134, 0xe100002 }, - { 0x3d400138, 0x120 }, + { 0x3d400138, 0x184 }, { 0x3d400144, 0xc80064 }, { 0x3d400180, 0x3e8001e }, { 0x3d400184, 0x3207a12 }, @@ -37,6 +73,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400190, 0x49f820e }, { 0x3d400194, 0x80303 }, { 0x3d4001b4, 0x1f0e }, +#endif { 0x3d4001a0, 0xe0400018 }, { 0x3d4001a4, 0xdf00e4 }, { 0x3d4001a8, 0x80000000 }, @@ -44,34 +81,68 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d4001c0, 0x1 }, { 0x3d4001c4, 0x1 }, { 0x3d4000f4, 0xc99 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x3d400108, 0x60c1514 }, + { 0x3d400200, 0x16 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x68070707 }, + { 0x3d40021c, 0xf08 }, + { 0x3d400250, 0x1f05 }, + { 0x3d400254, 0x1f }, + { 0x3d400264, 0x90003ff }, + { 0x3d40026c, 0x20003ff }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x1000e00 }, + { 0x3d400498, 0x3ff0000 }, + { 0x3d40049c, 0x1000e00 }, + { 0x3d4004a0, 0x3ff0000 }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc001c }, +#else { 0x3d400108, 0x9121c1c }, +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC + { 0x3d400200, 0x13 }, + { 0x3d40020c, 0x13131300 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x50505 }, + { 0x3d400214, 0x4040404 }, + { 0x3d400218, 0x68040404 }, +#else { 0x3d400200, 0x16 }, { 0x3d40020c, 0x0 }, { 0x3d400210, 0x1f1f }, { 0x3d400204, 0x80808 }, { 0x3d400214, 0x7070707 }, { 0x3d400218, 0x68070707 }, +#endif { 0x3d40021c, 0xf08 }, - { 0x3d400250, 0x00001705 }, + { 0x3d400250, 0x1705 }, { 0x3d400254, 0x2c }, { 0x3d40025c, 0x4000030 }, { 0x3d400264, 0x900093e7 }, { 0x3d40026c, 0x2005574 }, { 0x3d400400, 0x111 }, - { 0x3d400404, 0x72ff }, + { 0x3d400404, 0x72ff }, { 0x3d400408, 0x72ff }, { 0x3d400494, 0x2100e07 }, { 0x3d400498, 0x620096 }, { 0x3d40049c, 0x1100e07 }, { 0x3d4004a0, 0xc8012c }, - { 0x3d402020, 0x21 }, - { 0x3d402024, 0x7d00 }, - { 0x3d402050, 0x20d040 }, - { 0x3d402064, 0xc001c }, + { 0x3d402020, 0x1021 }, + { 0x3d402024, 0x30d400 }, + { 0x3d402050, 0x20d000 }, + { 0x3d402064, 0xc0026 }, +#endif { 0x3d4020dc, 0x840000 }, - { 0x3d4020e0, 0x310000 }, - { 0x3d4020e8, 0x66004d }, - { 0x3d4020ec, 0x16004d }, + { 0x3d4020e0, 0x330000 }, + { 0x3d4020e8, 0x660048 }, + { 0x3d4020ec, 0x160048 }, { 0x3d402100, 0xa040305 }, { 0x3d402104, 0x30407 }, { 0x3d402108, 0x203060b }, @@ -82,21 +153,28 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40211c, 0x301 }, { 0x3d402130, 0x20300 }, { 0x3d402134, 0xa100002 }, - { 0x3d402138, 0x1d }, + { 0x3d402138, 0x27 }, { 0x3d402144, 0x14000a }, { 0x3d402180, 0x640004 }, { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, { 0x3d4020f4, 0xc99 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS { 0x3d403020, 0x21 }, - { 0x3d403024, 0x30d400 }, - { 0x3d403050, 0x20d040 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, { 0x3d403064, 0x30007 }, +#else + { 0x3d403020, 0x1021 }, + { 0x3d403024, 0xc3500 }, + { 0x3d403050, 0x20d000 }, + { 0x3d403064, 0x3000a }, +#endif { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x310000 }, - { 0x3d4030e8, 0x66004d }, - { 0x3d4030ec, 0x16004d }, + { 0x3d4030e0, 0x330000 }, + { 0x3d4030e8, 0x660048 }, + { 0x3d4030ec, 0x160048 }, { 0x3d403100, 0xa010102 }, { 0x3d403104, 0x30404 }, { 0x3d403108, 0x203060b }, @@ -107,12 +185,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d40311c, 0x301 }, { 0x3d403130, 0x20300 }, { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, + { 0x3d403138, 0xa }, { 0x3d403144, 0x50003 }, { 0x3d403180, 0x190004 }, { 0x3d403190, 0x3818200 }, { 0x3d403194, 0x80303 }, { 0x3d4031b4, 0x100 }, + { 0x3d4030f4, 0xc99 }, { 0x3d400028, 0x0 }, }; @@ -184,7 +263,11 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x200c5, 0xa }, +#else { 0x200c5, 0x18 }, +#endif { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, @@ -263,7 +346,11 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x20008, 0x258 }, +#else { 0x20008, 0x3e8 }, +#endif { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, @@ -1050,6 +1137,38 @@ struct dram_cfg_param ddr_ddrphy_trained_csr[] = { /* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg[] = { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0xd0000, 0x0 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x24c4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x24c4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xc400 }, + { 0x54033, 0x3324 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xc400 }, + { 0x54039, 0x3324 }, +#else { 0xd0000, 0x0 }, { 0x54003, 0xfa0 }, { 0x54004, 0x2 }, @@ -1080,6 +1199,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0x54037, 0x1600 }, { 0x54038, 0xf400 }, { 0x54039, 0x333f }, +#endif { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1102,28 +1222,28 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54012, 0x310 }, { 0x54019, 0x84 }, { 0x5401a, 0x33 }, - { 0x5401b, 0x4846 }, + { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, - { 0x5401e, 0x15 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x33 }, - { 0x54021, 0x4846 }, + { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, - { 0x54024, 0x15 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, { 0x54033, 0x3300 }, - { 0x54034, 0x4600 }, + { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, - { 0x54037, 0x1500 }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, { 0x54039, 0x3300 }, - { 0x5403a, 0x4600 }, + { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, - { 0x5403d, 0x1500 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; @@ -1142,35 +1262,36 @@ struct dram_cfg_param ddr_fsp2_cfg[] = { { 0x54012, 0x310 }, { 0x54019, 0x84 }, { 0x5401a, 0x33 }, - { 0x5401b, 0x4846 }, + { 0x5401b, 0x4866 }, { 0x5401c, 0x4800 }, - { 0x5401e, 0x15 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, { 0x54020, 0x33 }, - { 0x54021, 0x4846 }, + { 0x54021, 0x4866 }, { 0x54022, 0x4800 }, - { 0x54024, 0x15 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0x8400 }, { 0x54033, 0x3300 }, - { 0x54034, 0x4600 }, + { 0x54034, 0x6600 }, { 0x54035, 0x48 }, { 0x54036, 0x48 }, - { 0x54037, 0x1500 }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, { 0x54039, 0x3300 }, - { 0x5403a, 0x4600 }, + { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, - { 0x5403d, 0x1500 }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54003, 0xfa0 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x54003, 0x960 }, { 0x54004, 0x2 }, { 0x54005, 0x2228 }, { 0x54006, 0x14 }, @@ -1181,6 +1302,37 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x5400f, 0x100 }, { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, + { 0x54019, 0x24c4 }, + { 0x5401a, 0x33 }, + { 0x5401b, 0x4866 }, + { 0x5401c, 0x4800 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x24c4 }, + { 0x54020, 0x33 }, + { 0x54021, 0x4866 }, + { 0x54022, 0x4800 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xc400 }, + { 0x54033, 0x3324 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x48 }, + { 0x54036, 0x48 }, + { 0x54037, 0x1600 }, + { 0x54038, 0xc400 }, + { 0x54039, 0x3324 }, +#else + { 0x54003, 0xfa0 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x14 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, { 0x54019, 0x3ff4 }, { 0x5401a, 0x33 }, { 0x5401b, 0x4866 }, @@ -1201,6 +1353,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54037, 0x1600 }, { 0x54038, 0xf400 }, { 0x54039, 0x333f }, +#endif { 0x5403a, 0x6600 }, { 0x5403b, 0x48 }, { 0x5403c, 0x48 }, @@ -1628,67 +1781,58 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x90155, 0x20 }, { 0x90156, 0x2aa }, { 0x90157, 0x9 }, - { 0x90158, 0x0 }, - { 0x90159, 0x400 }, - { 0x9015a, 0x10e }, - { 0x9015b, 0x8 }, - { 0x9015c, 0xe8 }, - { 0x9015d, 0x109 }, - { 0x9015e, 0x0 }, - { 0x9015f, 0x8140 }, - { 0x90160, 0x10c }, - { 0x90161, 0x10 }, - { 0x90162, 0x8138 }, - { 0x90163, 0x10c }, - { 0x90164, 0x8 }, - { 0x90165, 0x7c8 }, - { 0x90166, 0x101 }, - { 0x90167, 0x8 }, - { 0x90168, 0x448 }, + { 0x90158, 0x8 }, + { 0x90159, 0xe8 }, + { 0x9015a, 0x109 }, + { 0x9015b, 0x0 }, + { 0x9015c, 0x8140 }, + { 0x9015d, 0x10c }, + { 0x9015e, 0x10 }, + { 0x9015f, 0x8138 }, + { 0x90160, 0x104 }, + { 0x90161, 0x8 }, + { 0x90162, 0x448 }, + { 0x90163, 0x109 }, + { 0x90164, 0xf }, + { 0x90165, 0x7c0 }, + { 0x90166, 0x109 }, + { 0x90167, 0x0 }, + { 0x90168, 0xe8 }, { 0x90169, 0x109 }, - { 0x9016a, 0xf }, - { 0x9016b, 0x7c0 }, + { 0x9016a, 0x47 }, + { 0x9016b, 0x630 }, { 0x9016c, 0x109 }, - { 0x9016d, 0x0 }, - { 0x9016e, 0xe8 }, + { 0x9016d, 0x8 }, + { 0x9016e, 0x618 }, { 0x9016f, 0x109 }, - { 0x90170, 0x47 }, - { 0x90171, 0x630 }, + { 0x90170, 0x8 }, + { 0x90171, 0xe0 }, { 0x90172, 0x109 }, - { 0x90173, 0x8 }, - { 0x90174, 0x618 }, + { 0x90173, 0x0 }, + { 0x90174, 0x7c8 }, { 0x90175, 0x109 }, { 0x90176, 0x8 }, - { 0x90177, 0xe0 }, - { 0x90178, 0x109 }, + { 0x90177, 0x8140 }, + { 0x90178, 0x10c }, { 0x90179, 0x0 }, - { 0x9017a, 0x7c8 }, + { 0x9017a, 0x478 }, { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x8140 }, - { 0x9017e, 0x10c }, - { 0x9017f, 0x0 }, - { 0x90180, 0x478 }, - { 0x90181, 0x109 }, - { 0x90182, 0x0 }, - { 0x90183, 0x1 }, - { 0x90184, 0x8 }, - { 0x90185, 0x8 }, - { 0x90186, 0x4 }, - { 0x90187, 0x8 }, - { 0x90188, 0x8 }, - { 0x90189, 0x7c8 }, - { 0x9018a, 0x101 }, - { 0x90006, 0x0 }, - { 0x90007, 0x0 }, - { 0x90008, 0x8 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x1 }, + { 0x9017e, 0x8 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x4 }, + { 0x90181, 0x0 }, + { 0x90006, 0x8 }, + { 0x90007, 0x7c8 }, + { 0x90008, 0x109 }, { 0x90009, 0x0 }, - { 0x9000a, 0x0 }, - { 0x9000b, 0x0 }, + { 0x9000a, 0x400 }, + { 0x9000b, 0x106 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, { 0x9001f, 0x29 }, - { 0x90026, 0x6a }, + { 0x90026, 0x68 }, { 0x400d0, 0x0 }, { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, @@ -1698,9 +1842,16 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x400d6, 0x20a }, { 0x400d7, 0x20b }, { 0x2003a, 0x2 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, +#else + { 0x200be, 0x3 }, { 0x2000b, 0x7d }, { 0x2000c, 0xfa }, { 0x2000d, 0x9c4 }, +#endif { 0x2000e, 0x2c }, { 0x12000b, 0xc }, { 0x12000c, 0x19 }, @@ -1720,6 +1871,12 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, +#endif { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, @@ -1803,8 +1960,13 @@ struct dram_cfg_param ddr_phy_pie[] = { struct dram_fsp_msg ddr_dram_fsp_msg[] = { { +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + /* P0 2400mts 1D */ + .drate = 2400, +#else /* P0 4000mts 1D */ .drate = 4000, +#endif .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), @@ -1824,8 +1986,13 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { - /* P0 4000mts 2D */ - .drate = 4000, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + /* P0 2400mts 2D */ + .drate = 2400, +#else + /* P0 4000mts 2D */ + .drate = 4000, +#endif .fw_type = FW_2D_IMAGE, .fsp_cfg = ddr_fsp0_2d_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), @@ -1844,5 +2011,39 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 4000, 400, 100, }, +#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS + .fsp_table = { 2400, 400, 100, }, +#else + .fsp_table = { 4000, 400, 100, }, +#endif }; + +#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS +#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC +void board_dram_ecc_scrub(void) +{ + ddrc_inline_ecc_scrub(0x0,0x3ffffff); + ddrc_inline_ecc_scrub(0x20000000,0x23ffffff); + ddrc_inline_ecc_scrub(0x40000000,0x43ffffff); + ddrc_inline_ecc_scrub(0x4000000,0x7ffffff); + ddrc_inline_ecc_scrub(0x24000000,0x27ffffff); + ddrc_inline_ecc_scrub(0x44000000,0x47ffffff); + ddrc_inline_ecc_scrub(0x8000000,0xbffffff); + ddrc_inline_ecc_scrub(0x28000000,0x2bffffff); + ddrc_inline_ecc_scrub(0x48000000,0x4bffffff); + ddrc_inline_ecc_scrub(0xc000000,0xfffffff); + ddrc_inline_ecc_scrub(0x2c000000,0x2fffffff); + ddrc_inline_ecc_scrub(0x4c000000,0x4fffffff); + ddrc_inline_ecc_scrub(0x10000000,0x13ffffff); + ddrc_inline_ecc_scrub(0x30000000,0x33ffffff); + ddrc_inline_ecc_scrub(0x50000000,0x53ffffff); + ddrc_inline_ecc_scrub(0x14000000,0x17ffffff); + ddrc_inline_ecc_scrub(0x34000000,0x37ffffff); + ddrc_inline_ecc_scrub(0x54000000,0x57ffffff); + ddrc_inline_ecc_scrub(0x18000000,0x1bffffff); + ddrc_inline_ecc_scrub(0x38000000,0x3bffffff); + ddrc_inline_ecc_scrub(0x58000000,0x5bffffff); + ddrc_inline_ecc_scrub_end(0x0,0x5fffffff); +} +#endif +#endif diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c index ebfd94dc1fa..f527966119f 100644 --- a/board/freescale/imx8mp_evk/spl.c +++ b/board/freescale/imx8mp_evk/spl.c @@ -24,9 +24,13 @@ #include #include +#include +#include +#include +#include #include #include -#include +#include #include #include @@ -34,7 +38,28 @@ DECLARE_GLOBAL_DATA_PTR; int spl_board_boot_device(enum boot_device boot_dev_spl) { +#ifdef CONFIG_SPL_BOOTROM_SUPPORT return BOOT_DEVICE_BOOTROM; +#else + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC1; + case SD3_BOOT: + case MMC3_BOOT: + return BOOT_DEVICE_MMC2; + case QSPI_BOOT: + return BOOT_DEVICE_NOR; + case NAND_BOOT: + return BOOT_DEVICE_NAND; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +#endif } void spl_dram_init(void) @@ -42,59 +67,80 @@ void spl_dram_init(void) ddr_init(&dram_timing); } -void spl_board_init(void) -{ - puts("Normal Boot\n"); -} - -#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE) -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) -struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC, - .gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC, - .gp = IMX_GPIO_NR(5, 14), - }, - .sda = { - .i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC, - .gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC, - .gp = IMX_GPIO_NR(5, 15), - }, -}; - -#ifdef CONFIG_POWER -#define I2C_PMIC 0 +#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450) int power_init_board(void) { - struct pmic *p; + struct udevice *dev; int ret; - ret = power_pca9450_init(I2C_PMIC); - if (ret) - printf("power init failed"); - p = pmic_get("PCA9450"); - pmic_probe(p); + ret = pmic_get("pca9450@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + if (ret != 0) + return ret; /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(p, PCA9450_BUCK123_DVS, 0x29); + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); +#ifdef CONFIG_IMX8M_LPDDR4 /* * increase VDD_SOC to typical value 0.95V before first * DRAM access, set DVS1 to 0.85v for suspend. * Enable DVS control through PMIC_STBY_REQ and * set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */ - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C); - pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14); - pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59); +#ifdef CONFIG_IMX8M_VDD_SOC_850MV + /* set DVS0 to 0.85v for special case*/ + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x14); +#else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C); +#endif + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14); + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Kernel uses OD/OD freq for SOC */ + /* To avoid timing risk from SOC to ARM,increase VDD_ARM to OD voltage 0.95v */ + pmic_reg_write(dev, PCA9450_BUCK2OUT_DVS0, 0x1C); +#elif defined(CONFIG_IMX8M_DDR4) + /* DDR4 runs at 3200MTS, uses default ND 0.85v for VDD_SOC and VDD_ARM */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + /* Set NVCC_DRAM to 1.2v for DDR4 */ + pmic_reg_write(dev, PCA9450_BUCK6OUT, 0x18); +#endif /* set WDOG_B_CFG to cold reset */ - pmic_reg_write(p, PCA9450_RESET_CTRL, 0xA1); + pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1); return 0; } #endif +void spl_board_init(void) +{ + struct udevice *dev; + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + /* Set GIC clock to 500Mhz for OD VDD_SOC. Kernel driver does not allow to change it. + * Should set the clock after PMIC setting done. + * Default is 400Mhz (system_pll1_800m with div = 2) set by ROM for ND VDD_SOC + */ +#ifdef CONFIG_IMX8M_LPDDR4 + clock_enable(CCGR_GIC, 0); + clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(5)); + clock_enable(CCGR_GIC, 1); +#endif + + puts("Normal Boot\n"); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { @@ -105,31 +151,42 @@ int board_fit_config_name_match(const char *name) } #endif -/* Do not use BSS area in this phase */ void board_init_f(ulong dummy) { + struct udevice *dev; int ret; - arch_cpu_init(); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); - init_uart_clk(1); + arch_cpu_init(); board_early_init_f(); + timer_init(); + + preloader_console_init(); + ret = spl_early_init(); if (ret) { - debug("spl_init() failed: %d\n", ret); + debug("spl_early_init() failed: %d\n", ret); hang(); } - preloader_console_init(); + ret = uclass_get_device_by_name(UCLASS_CLK, + "clock-controller@30380000", + &dev); + if (ret < 0) { + printf("Failed to find clock node. Check device tree\n"); + hang(); + } enable_tzc380(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); - power_init_board(); /* DDR initialization */ spl_dram_init(); + + board_init_r(NULL, 0); } diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig index 421b081c761..3f3bddf324d 100644 --- a/board/freescale/imx8mq_evk/Kconfig +++ b/board/freescale/imx8mq_evk/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "imx8mq_evk" +source "board/freescale/common/Kconfig" + endif diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c index 93da67d7798..81a961883f1 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.c +++ b/board/freescale/imx8mq_evk/imx8mq_evk.c @@ -25,7 +25,10 @@ #include #include #include +#include "../common/tcpc.h" #include "../common/pfuze.h" +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -54,6 +57,15 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_FSL_QSPI +int board_qspi_init(void) +{ + set_clk_qspi(); + + return 0; +} +#endif + #ifdef CONFIG_FEC_MXC static int setup_fec(void) { @@ -61,37 +73,197 @@ static int setup_fec(void) (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; /* Use 125M anatop REF_CLK1 for ENET1, not from external */ - clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); + clrsetbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 0); return set_clk_enet(ENET_125MHZ); } int board_phy_config(struct phy_device *phydev) { + if (phydev->drv->config) + phydev->drv->config(phydev); + +#ifndef CONFIG_DM_ETH /* enable rgmii rxc skew and phy mode select to RGMII copper */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif - if (phydev->drv->config) - phydev->drv->config(phydev); return 0; } #endif -int board_init(void) +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +static struct dwc3_device dwc3_device_data = { +#ifdef CONFIG_SPL_BUILD + .maximum_speed = USB_SPEED_HIGH, +#else + .maximum_speed = USB_SPEED_SUPER, +#endif + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(int index) { -#ifdef CONFIG_FEC_MXC - setup_fec(); + dwc3_uboot_handle_interrupt(index); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} +#endif + +#ifdef CONFIG_USB_TCPC +struct tcpc_port port; +struct tcpc_port_config port_config = { + .i2c_bus = 0, + .addr = 0x50, + .port_type = TYPEC_PORT_UFP, + .max_snk_mv = 20000, + .max_snk_ma = 3000, + .max_snk_mw = 15000, + .op_snk_mv = 9000, +}; + +struct gpio_desc type_sel_desc; +static iomux_v3_cfg_t ss_mux_gpio[] = { + IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void ss_mux_select(enum typec_cc_polarity pol) +{ + if (pol == TYPEC_POLARITY_CC1) + dm_gpio_set_value(&type_sel_desc, 1); + else + dm_gpio_set_value(&type_sel_desc, 0); +} + +static int setup_typec(void) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + + ret = dm_gpio_lookup_name("GPIO3_15", &type_sel_desc); + if (ret) { + printf("%s lookup GPIO3_15 failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + ret = dm_gpio_request(&type_sel_desc, "typec_sel"); + if (ret) { + printf("%s request typec_sel failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT); + + ret = tcpc_init(&port, port_config, &ss_mux_select); + if (ret) { + printf("%s: tcpc init failed, err=%d\n", + __func__, ret); + } + + return ret; +} +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 0 && init == USB_INIT_DEVICE) { + imx8m_usb_power(index, true); +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port); #endif + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port); +#endif + return ret; + } return 0; } -int board_mmc_get_env_dev(int devno) +int board_usb_cleanup(int index, enum usb_init_type init) { - return devno; + int ret = 0; + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + imx8m_usb_power(index, false); + } else if (index == 0 && init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port); +#endif + } + + return ret; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) + init_usb_clk(); +#endif + +#ifdef CONFIG_USB_TCPC + setup_typec(); +#endif + return 0; } int board_late_init(void) @@ -101,5 +273,24 @@ int board_late_init(void) env_set("board_rev", "iMX8MQ"); #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + return 0; } + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + return (bool)(!!(readl(SNVS_HPSR) & (0x1 << 6))); +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /* TODO */ +} +#endif /* CONFIG_ANDROID_RECOVERY */ +#endif /* CONFIG_FSL_FASTBOOT */ diff --git a/board/freescale/imx8mq_evk/lpddr4_timing.c b/board/freescale/imx8mq_evk/lpddr4_timing.c index 46bc7f8591c..7bf35928daa 100644 --- a/board/freescale/imx8mq_evk/lpddr4_timing.c +++ b/board/freescale/imx8mq_evk/lpddr4_timing.c @@ -1,148 +1,168 @@ -// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include */ #include -#include #include -#include -#define WR_POST_EXT_3200 /* recommened to define */ - -struct dram_cfg_param lpddr4_ddrc_cfg[] = { - /* Start to config, default 3200mbps */ - { DDRC_DBG1(0), 0x00000001 }, - { DDRC_PWRCTL(0), 0x00000001 }, - { DDRC_MSTR(0), 0xa3080020 }, - { DDRC_MSTR2(0), 0x00000000 }, - { DDRC_RFSHTMG(0), 0x006100E0 }, - { DDRC_INIT0(0), 0xC003061B }, - { DDRC_INIT1(0), 0x009D0000 }, - { DDRC_INIT3(0), 0x00D4002D }, -#ifdef WR_POST_EXT_3200 - { DDRC_INIT4(0), 0x00330008 }, -#else - { DDRC_INIT4(0), 0x00310008 }, -#endif - { DDRC_INIT6(0), 0x0066004a }, - { DDRC_INIT7(0), 0x0006004a }, - - { DDRC_DRAMTMG0(0), 0x1A201B22 }, - { DDRC_DRAMTMG1(0), 0x00060633 }, - { DDRC_DRAMTMG3(0), 0x00C0C000 }, - { DDRC_DRAMTMG4(0), 0x0F04080F }, - { DDRC_DRAMTMG5(0), 0x02040C0C }, - { DDRC_DRAMTMG6(0), 0x01010007 }, - { DDRC_DRAMTMG7(0), 0x00000401 }, - { DDRC_DRAMTMG12(0), 0x00020600 }, - { DDRC_DRAMTMG13(0), 0x0C100002 }, - { DDRC_DRAMTMG14(0), 0x000000E6 }, - { DDRC_DRAMTMG17(0), 0x00A00050 }, - - { DDRC_ZQCTL0(0), 0x03200018 }, - { DDRC_ZQCTL1(0), 0x028061A8 }, - { DDRC_ZQCTL2(0), 0x00000000 }, - - { DDRC_DFITMG0(0), 0x0497820A }, - { DDRC_DFITMG1(0), 0x00080303 }, - { DDRC_DFIUPD0(0), 0xE0400018 }, - { DDRC_DFIUPD1(0), 0x00DF00E4 }, - { DDRC_DFIUPD2(0), 0x80000000 }, - { DDRC_DFIMISC(0), 0x00000011 }, - { DDRC_DFITMG2(0), 0x0000170A }, - - { DDRC_DBICTL(0), 0x00000001 }, - { DDRC_DFIPHYMSTR(0), 0x00000001 }, - { DDRC_RANKCTL(0), 0x00000c99 }, - { DDRC_DRAMTMG2(0), 0x070E171a }, - - /* address mapping */ - { DDRC_ADDRMAP0(0), 0x00000015 }, - { DDRC_ADDRMAP3(0), 0x00000000 }, - { DDRC_ADDRMAP4(0), 0x00001F1F }, - /* bank interleave */ - { DDRC_ADDRMAP1(0), 0x00080808 }, - { DDRC_ADDRMAP5(0), 0x07070707 }, - { DDRC_ADDRMAP6(0), 0x08080707 }, - - /* performance setting */ - { DDRC_ODTCFG(0), 0x0b060908 }, - { DDRC_ODTMAP(0), 0x00000000 }, - { DDRC_SCHED(0), 0x29511505 }, - { DDRC_SCHED1(0), 0x0000002c }, - { DDRC_PERFHPR1(0), 0x5900575b }, - /* 150T starve and 0x90 max tran len */ - { DDRC_PERFLPR1(0), 0x90000096 }, - /* 300T starve and 0x10 max tran len */ - { DDRC_PERFWR1(0), 0x1000012c }, - { DDRC_DBG0(0), 0x00000016 }, - { DDRC_DBG1(0), 0x00000000 }, - { DDRC_DBGCMD(0), 0x00000000 }, - { DDRC_SWCTL(0), 0x00000001 }, - { DDRC_POISONCFG(0), 0x00000011 }, - { DDRC_PCCFG(0), 0x00000111 }, - { DDRC_PCFGR_0(0), 0x000010f3 }, - { DDRC_PCFGW_0(0), 0x000072ff }, - { DDRC_PCTRL_0(0), 0x00000001 }, - /* disable Read Qos*/ - { DDRC_PCFGQOS0_0(0), 0x00000e00 }, - { DDRC_PCFGQOS1_0(0), 0x0062ffff }, - /* disable Write Qos*/ - { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, - { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, - - /* Frequency 1: 400mbps */ - { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c }, - { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 }, - { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, - { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 }, - { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 }, - { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, - { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, - { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, - { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, - { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, - { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, - { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, - { DDRC_FREQ1_DFITMG0(0), 0x03818200 }, - { DDRC_FREQ1_DFITMG2(0), 0x00000000 }, - { DDRC_FREQ1_RFSHTMG(0), 0x000C001c }, - { DDRC_FREQ1_INIT3(0), 0x00840000 }, - { DDRC_FREQ1_INIT4(0), 0x00310008 }, - { DDRC_FREQ1_INIT6(0), 0x0066004a }, - { DDRC_FREQ1_INIT7(0), 0x0006004a }, - - /* Frequency 2: 100mbps */ - { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c }, - { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 }, - { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c }, - { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 }, - { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 }, - { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 }, - { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 }, - { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e }, - { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 }, - { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b }, - { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 }, - { DDRC_FREQ2_DFITMG0(0), 0x03818200 }, - { DDRC_FREQ2_DFITMG2(0), 0x00000000 }, - { DDRC_FREQ2_RFSHTMG(0), 0x00030007 }, - { DDRC_FREQ2_INIT3(0), 0x00840000 }, - { DDRC_FREQ2_INIT4(0), 0x00310008 }, - { DDRC_FREQ2_INIT6(0), 0x0066004a }, - { DDRC_FREQ2_INIT7(0), 0x0006004a }, +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400028, 0x0 }, + { 0x3d400020, 0x203 }, + { 0x3d400024, 0x3e800 }, + { 0x3d400064, 0x6100e0 }, + { 0x3d4000d0, 0xc003061c }, + { 0x3d4000d4, 0x9e0000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310008 }, + { 0x3d4000e8, 0x66004a }, + { 0x3d4000ec, 0x16004a }, + { 0x3d400100, 0x1a201b22 }, + { 0x3d400104, 0x60633 }, + { 0x3d40010c, 0xc0c000 }, + { 0x3d400110, 0xf04080f }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xe6 }, + { 0x3d400144, 0xa00050 }, + { 0x3d400180, 0xc3200018 }, + { 0x3d400184, 0x28061a8 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0x639 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x15 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x48080707 }, + { 0x3d402020, 0x1 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004a }, + { 0x3d4020ec, 0x16004a }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0xc0640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d403020, 0x1 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004a }, + { 0x3d4030ec, 0x16004a }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0xc0190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d400244, 0x0 }, + { 0x3d400250, 0x29001505 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x5900575b }, + { 0x3d400264, 0x90000096 }, + { 0x3d40026c, 0x1000012c }, + { 0x3d400300, 0x16 }, + { 0x3d400304, 0x0 }, + { 0x3d40030c, 0x0 }, + { 0x3d400320, 0x1 }, + { 0x3d40036c, 0x11 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x10f3 }, + { 0x3d400408, 0x72ff }, + { 0x3d400490, 0x1 }, + { 0x3d400494, 0xe00 }, + { 0x3d400498, 0x62ffff }, + { 0x3d40049c, 0xe00 }, + { 0x3d4004a0, 0xffff }, }; /* PHY Initialize Configuration */ -struct dram_cfg_param lpddr4_ddrphy_cfg[] = { - { 0x20110, 0x02 }, - { 0x20111, 0x03 }, - { 0x20112, 0x04 }, - { 0x20113, 0x05 }, - { 0x20114, 0x00 }, - { 0x20115, 0x01 }, - +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x6 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -151,7 +171,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x1215f, 0x1ff }, { 0x1305f, 0x1ff }, { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, { 0x11015f, 0x1ff }, { 0x11105f, 0x1ff }, @@ -160,7 +179,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x11215f, 0x1ff }, { 0x11305f, 0x1ff }, { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, { 0x21015f, 0x1ff }, { 0x21105f, 0x1ff }, @@ -169,7 +187,6 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x21215f, 0x1ff }, { 0x21305f, 0x1ff }, { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, { 0x1055, 0x1ff }, { 0x2055, 0x1ff }, @@ -180,32 +197,24 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x7055, 0x1ff }, { 0x8055, 0x1ff }, { 0x9055, 0x1ff }, - { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, { 0x2200c5, 0x7 }, - { 0x2002e, 0x2 }, { 0x12002e, 0x2 }, { 0x22002e, 0x2 }, - { 0x90204, 0x0 }, { 0x190204, 0x0 }, { 0x290204, 0x0 }, - -#ifdef WR_POST_EXT_3200 - { 0x20024, 0xeb }, -#else - { 0x20024, 0xab }, -#endif + { 0x20024, 0x1ab }, { 0x2003a, 0x0 }, - { 0x120024, 0xab }, + { 0x120024, 0x1ab }, { 0x2003a, 0x0 }, - { 0x220024, 0xab }, + { 0x220024, 0x1ab }, { 0x2003a, 0x0 }, { 0x20056, 0x3 }, - { 0x120056, 0xa }, - { 0x220056, 0xa }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, { 0x1004d, 0xe00 }, { 0x1014d, 0xe00 }, { 0x1104d, 0xe00 }, @@ -230,43 +239,40 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x21214d, 0xe00 }, { 0x21304d, 0xe00 }, { 0x21314d, 0xe00 }, - - { 0x10049, 0xfbe }, - { 0x10149, 0xfbe }, - { 0x11049, 0xfbe }, - { 0x11149, 0xfbe }, - { 0x12049, 0xfbe }, - { 0x12149, 0xfbe }, - { 0x13049, 0xfbe }, - { 0x13149, 0xfbe }, - { 0x110049, 0xfbe }, - { 0x110149, 0xfbe }, - { 0x111049, 0xfbe }, - { 0x111149, 0xfbe }, - { 0x112049, 0xfbe }, - { 0x112149, 0xfbe }, - { 0x113049, 0xfbe }, - { 0x113149, 0xfbe }, - { 0x210049, 0xfbe }, - { 0x210149, 0xfbe }, - { 0x211049, 0xfbe }, - { 0x211149, 0xfbe }, - { 0x212049, 0xfbe }, - { 0x212149, 0xfbe }, - { 0x213049, 0xfbe }, - { 0x213149, 0xfbe }, - - { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) }, - + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, @@ -274,7 +280,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x120008, 0x64 }, { 0x220008, 0x19 }, { 0x20088, 0x9 }, - { 0x200b2, 0x104 }, + { 0x200b2, 0xdc }, { 0x10043, 0x5a1 }, { 0x10143, 0x5a1 }, { 0x11043, 0x5a1 }, @@ -283,7 +289,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x12143, 0x5a1 }, { 0x13043, 0x5a1 }, { 0x13143, 0x5a1 }, - { 0x1200b2, 0x104 }, + { 0x1200b2, 0xdc }, { 0x110043, 0x5a1 }, { 0x110143, 0x5a1 }, { 0x111043, 0x5a1 }, @@ -292,7 +298,7 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x112143, 0x5a1 }, { 0x113043, 0x5a1 }, { 0x113143, 0x5a1 }, - { 0x2200b2, 0x104 }, + { 0x2200b2, 0xdc }, { 0x210043, 0x5a1 }, { 0x210143, 0x5a1 }, { 0x211043, 0x5a1 }, @@ -319,376 +325,903 @@ struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x2002d, 0x0 }, { 0x12002d, 0x0 }, { 0x22002d, 0x0 }, - { 0x200c7, 0x80 }, { 0x1200c7, 0x80 }, { 0x2200c7, 0x80 }, { 0x200ca, 0x106 }, { 0x1200ca, 0x106 }, { 0x2200ca, 0x106 }, + { 0x20110, 0x2 }, + { 0x20111, 0x3 }, + { 0x20112, 0x4 }, + { 0x20113, 0x5 }, + { 0x20114, 0x0 }, + { 0x20115, 0x1 }, }; +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; /* P0 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp0_cfg[] = { +struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xc80 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */ - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x131f }, - { 0x54009, LPDDR4_HDT_CTL_3200_1D }, - { 0x5400a, 0x0 }, + { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - { 0x54019, 0x2dd4 }, -#ifdef WR_POST_EXT_3200 - { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, -#else - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, -#endif - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, -#ifdef WR_POST_EXT_3200 - { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, -#else - { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, -#endif - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0xd400 }, - /* MR3/MR2 */ -#ifdef WR_POST_EXT_3200 - { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ }, -#else - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, -#endif - /* MR11/MR4 */ - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - /* self:0x284d//MR13/MR12 */ - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, - /* MR16/MR14*/ - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ }, - /* MR1 */ + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, - /* MR3/MR2 */ -#ifdef WR_POST_EXT_3200 - { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ }, -#else - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ }, -#endif - /* MR11/MR4 */ - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - /* self:0x284d//MR13/MR12 */ - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ }, - /* MR16/MR14 */ - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, - /* { 0x5403d, 0x500 } */ - { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; + /* P1 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp1_cfg[] = { +struct dram_cfg_param ddr_fsp1_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x101 }, { 0x54003, 0x190 }, { 0x54004, 0x2 }, - /* PHY Ron/Rtt */ - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, - { 0x54008, LPDDR4_TRAIN_SEQ_400 }, - { 0x54009, LPDDR4_HDT_CTL_400_1D }, - { 0x5400a, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_400 << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x84 }, - /* MR4/MR3 */ - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, - /* MR12/MR11 */ - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | - LPDDR4_RTT_DQ)/*0x4d46*/ }, - /* self:0x4d28//MR14/MR13 */ - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */ - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | - LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */ - /* self:0x4d28//MR14/MR13 */ - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0x8400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, - { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, - { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; + /* P2 message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp2_cfg[] = { +struct dram_cfg_param ddr_fsp2_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x102 }, { 0x54003, 0x64 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, - { 0x54008, LPDDR4_TRAIN_SEQ_100 }, - { 0x54009, LPDDR4_HDT_CTL_100_1D }, - { 0x5400a, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_100 << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x84 }, - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | - LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x84 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) | - LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0x8400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, - { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, { 0x54038, 0x8400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 }, - { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; + /* P0 2D message block paremeter for training firmware */ -struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xc80 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x61 }, - { 0x54009, LPDDR4_HDT_CTL_2D }, - { 0x5400a, 0x0 }, + { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, - { 0x54010, LPDDR4_2D_WEIGHT }, - { 0x54011, 0x0 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x2dd4 }, -#ifdef WR_POST_EXT_3200 - { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, -#else - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, -#endif - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, -#ifdef WR_POST_EXT_3200 - { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, -#else - { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, -#endif - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, - { 0x54032, 0xd400 }, -#ifdef WR_POST_EXT_3200 - { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, -#else - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, -#endif - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, -#ifdef WR_POST_EXT_3200 - { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, -#else - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d }, -#endif - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; /* DRAM PHY init engine image */ -struct dram_cfg_param lpddr4_phy_pie[] = { +struct dram_cfg_param ddr_phy_pie[] = { { 0xd0000, 0x0 }, { 0x90000, 0x10 }, { 0x90001, 0x400 }, @@ -1199,6 +1732,10 @@ struct dram_cfg_param lpddr4_phy_pie[] = { { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, @@ -1276,49 +1813,52 @@ struct dram_cfg_param lpddr4_phy_pie[] = { { 0x138b4, 0x1 }, { 0x2003a, 0x2 }, { 0xc0080, 0x2 }, - { 0xd0000, 0x1 }, + { 0xd0000, 0x1 } }; -struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { +struct dram_fsp_msg ddr_dram_fsp_msg[] = { { /* P0 3200mts 1D */ .drate = 3200, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), }, { /* P1 400mts 1D */ .drate = 400, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), }, { - /* P1 100mts 1D */ + /* P2 100mts 1D */ .drate = 100, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), }, { /* P0 3200mts 2D */ .drate = 3200, .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), }, }; -/* lpddr4 timing config params on EVK board */ +/* ddr timing config params */ struct dram_timing_info dram_timing = { - .ddrc_cfg = lpddr4_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), - .ddrphy_cfg = lpddr4_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), - .fsp_msg = lpddr4_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), - .ddrphy_pie = lpddr4_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 400, 100, }, }; + diff --git a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c index ec68edaf690..b8a147d3bb7 100644 --- a/board/freescale/imx8mq_evk/lpddr4_timing_b0.c +++ b/board/freescale/imx8mq_evk/lpddr4_timing_b0.c @@ -1,147 +1,144 @@ -// SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2019.04_5.4.x and above version + * For imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga: + * please replace #include with #include */ #include -#include #include -#include -#define WR_POST_EXT_3200 /* recommened to define */ - -static struct dram_cfg_param lpddr4_ddrc_cfg[] = { - /* Start to config, default 3200mbps */ - /* dis_dq=1, indicates no reads or writes are issued to SDRAM */ - { DDRC_DBG1(0), 0x00000001 }, - /* selfref_en=1, SDRAM enter self-refresh state */ - { DDRC_PWRCTL(0), 0x00000001 }, - { DDRC_MSTR(0), 0xa3080020 }, - { DDRC_MSTR2(0), 0x00000000 }, - { DDRC_RFSHTMG(0), 0x006100E0 }, - { DDRC_INIT0(0), 0xC003061B }, - { DDRC_INIT1(0), 0x009D0000 }, - { DDRC_INIT3(0), 0x00D4002D }, -#ifdef WR_POST_EXT_3200 /* recommened to define */ - { DDRC_INIT4(0), 0x00330008 }, -#else - { DDRC_INIT4(0), 0x00310008 }, -#endif - { DDRC_INIT6(0), 0x0066004a }, - { DDRC_INIT7(0), 0x0006004a }, - - { DDRC_DRAMTMG0(0), 0x1A201B22 }, - { DDRC_DRAMTMG1(0), 0x00060633 }, - { DDRC_DRAMTMG3(0), 0x00C0C000 }, - { DDRC_DRAMTMG4(0), 0x0F04080F }, - { DDRC_DRAMTMG5(0), 0x02040C0C }, - { DDRC_DRAMTMG6(0), 0x01010007 }, - { DDRC_DRAMTMG7(0), 0x00000401 }, - { DDRC_DRAMTMG12(0), 0x00020600 }, - { DDRC_DRAMTMG13(0), 0x0C100002 }, - { DDRC_DRAMTMG14(0), 0x000000E6 }, - { DDRC_DRAMTMG17(0), 0x00A00050 }, - - { DDRC_ZQCTL0(0), 0x03200018 }, - { DDRC_ZQCTL1(0), 0x028061A8 }, - { DDRC_ZQCTL2(0), 0x00000000 }, - - { DDRC_DFITMG0(0), 0x0497820A }, - { DDRC_DFITMG1(0), 0x00080303 }, - { DDRC_DFIUPD0(0), 0xE0400018 }, - { DDRC_DFIUPD1(0), 0x00DF00E4 }, - { DDRC_DFIUPD2(0), 0x80000000 }, - { DDRC_DFIMISC(0), 0x00000011 }, - { DDRC_DFITMG2(0), 0x0000170A }, - - { DDRC_DBICTL(0), 0x00000001 }, - { DDRC_DFIPHYMSTR(0), 0x00000001 }, - - /* need be refined by ddrphy trained value */ - { DDRC_RANKCTL(0), 0x00000c99 }, - { DDRC_DRAMTMG2(0), 0x070E171a }, - - /* address mapping */ - /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ - { DDRC_ADDRMAP0(0), 0x00000015 }, - { DDRC_ADDRMAP3(0), 0x00000000 }, - /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */ - { DDRC_ADDRMAP4(0), 0x00001F1F }, - /* bank interleave */ - /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ - { DDRC_ADDRMAP1(0), 0x00080808 }, - /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */ - { DDRC_ADDRMAP5(0), 0x07070707 }, - /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */ - { DDRC_ADDRMAP6(0), 0x08080707 }, - - /* 667mts frequency setting */ - { DDRC_FREQ1_DERATEEN(0), 0x0000000 }, - { DDRC_FREQ1_DERATEINT(0), 0x0800000 }, - { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 }, - { DDRC_FREQ1_RFSHTMG(0), 0x014001E }, - { DDRC_FREQ1_INIT3(0), 0x0140009 }, - { DDRC_FREQ1_INIT4(0), 0x00310008 }, - { DDRC_FREQ1_INIT6(0), 0x0066004a }, - { DDRC_FREQ1_INIT7(0), 0x0006004a }, - { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 }, - { DDRC_FREQ1_DRAMTMG1(0), 0x003040A }, - { DDRC_FREQ1_DRAMTMG2(0), 0x305080C }, - { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 }, - { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 }, - { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 }, - { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 }, - { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 }, - { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 }, - { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 }, - { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 }, - { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 }, - { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 }, - { DDRC_FREQ1_DFITMG0(0), 0x3858202 }, - { DDRC_FREQ1_DFITMG1(0), 0x0000404 }, - { DDRC_FREQ1_DFITMG2(0), 0x0000502 }, - - /* performance setting */ - { DDRC_ODTCFG(0), 0x0b060908 }, - { DDRC_ODTMAP(0), 0x00000000 }, - { DDRC_SCHED(0), 0x29511505 }, - { DDRC_SCHED1(0), 0x0000002c }, - { DDRC_PERFHPR1(0), 0x5900575b }, - /* 150T starve and 0x90 max tran len */ - { DDRC_PERFLPR1(0), 0x90000096 }, - /* 300T starve and 0x10 max tran len */ - { DDRC_PERFWR1(0), 0x1000012c }, - { DDRC_DBG0(0), 0x00000016 }, - { DDRC_DBG1(0), 0x00000000 }, - { DDRC_DBGCMD(0), 0x00000000 }, - { DDRC_SWCTL(0), 0x00000001 }, - { DDRC_POISONCFG(0), 0x00000011 }, - { DDRC_PCCFG(0), 0x00000111 }, - { DDRC_PCFGR_0(0), 0x000010f3 }, - { DDRC_PCFGW_0(0), 0x000072ff }, - { DDRC_PCTRL_0(0), 0x00000001 }, - /* disable Read Qos*/ - { DDRC_PCFGQOS0_0(0), 0x00000e00 }, - { DDRC_PCFGQOS1_0(0), 0x0062ffff }, - /* disable Write Qos*/ - { DDRC_PCFGWQOS0_0(0), 0x00000e00 }, - { DDRC_PCFGWQOS1_0(0), 0x0000ffff }, - { DDRC_FREQ1_DERATEEN(0), 0x00000202 }, - { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 }, - { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 }, - { DDRC_FREQ1_RFSHTMG(0), 0x00610090 }, +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400028, 0x0 }, + { 0x3d400020, 0x203 }, + { 0x3d400024, 0x3e800 }, + { 0x3d400064, 0x6100e0 }, + { 0x3d4000d0, 0xc003061c }, + { 0x3d4000d4, 0x9e0000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310008 }, + { 0x3d4000e8, 0x66004a }, + { 0x3d4000ec, 0x16004a }, + { 0x3d400100, 0x1a201b22 }, + { 0x3d400104, 0x60633 }, + { 0x3d40010c, 0xc0c000 }, + { 0x3d400110, 0xf04080f }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xe6 }, + { 0x3d400144, 0xa00050 }, + { 0x3d400180, 0xc3200018 }, + { 0x3d400184, 0x28061a8 }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0x639 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x15 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x48080707 }, + { 0x3d402020, 0x1 }, + { 0x3d402024, 0xd0c0 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0x14002f }, + { 0x3d4020dc, 0x940009 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004a }, + { 0x3d4020ec, 0x16004a }, + { 0x3d402100, 0xb070508 }, + { 0x3d402104, 0x3040b }, + { 0x3d402108, 0x305090c }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x4040204 }, + { 0x3d402114, 0x2030303 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x31 }, + { 0x3d402144, 0x220011 }, + { 0x3d402180, 0xc0a70006 }, + { 0x3d402190, 0x3858202 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x502 }, + { 0x3d400244, 0x0 }, + { 0x3d400250, 0x29001505 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x5900575b }, + { 0x3d400264, 0x90000096 }, + { 0x3d40026c, 0x1000012c }, + { 0x3d400300, 0x16 }, + { 0x3d400304, 0x0 }, + { 0x3d40030c, 0x0 }, + { 0x3d400320, 0x1 }, + { 0x3d40036c, 0x11 }, + { 0x3d400400, 0x111 }, + { 0x3d400404, 0x10f3 }, + { 0x3d400408, 0x72ff }, + { 0x3d400490, 0x1 }, + { 0x3d400494, 0xe00 }, + { 0x3d400498, 0x62ffff }, + { 0x3d40049c, 0xe00 }, + { 0x3d4004a0, 0xffff }, }; /* PHY Initialize Configuration */ -static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { - { 0x20110, 0x02 }, /* MapCAB0toDFI */ - { 0x20111, 0x03 }, /* MapCAB1toDFI */ - { 0x20112, 0x04 }, /* MapCAB2toDFI */ - { 0x20113, 0x05 }, /* MapCAB3toDFI */ - { 0x20114, 0x00 }, /* MapCAB4toDFI */ - { 0x20115, 0x01 }, /* MapCAB5toDFI */ - - /* Initialize PHY Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x2 }, + { 0x110a3, 0x3 }, + { 0x110a4, 0x4 }, + { 0x110a5, 0x5 }, + { 0x110a6, 0x6 }, + { 0x110a7, 0x7 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x2 }, + { 0x120a3, 0x3 }, + { 0x120a4, 0x4 }, + { 0x120a5, 0x5 }, + { 0x120a6, 0x6 }, + { 0x120a7, 0x7 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, { 0x1005f, 0x1ff }, { 0x1015f, 0x1ff }, { 0x1105f, 0x1ff }, @@ -150,7 +147,6 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x1215f, 0x1ff }, { 0x1305f, 0x1ff }, { 0x1315f, 0x1ff }, - { 0x11005f, 0x1ff }, { 0x11015f, 0x1ff }, { 0x11105f, 0x1ff }, @@ -159,16 +155,6 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x11215f, 0x1ff }, { 0x11305f, 0x1ff }, { 0x11315f, 0x1ff }, - - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, - { 0x55, 0x1ff }, { 0x1055, 0x1ff }, { 0x2055, 0x1ff }, @@ -181,25 +167,16 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x9055, 0x1ff }, { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, { 0x12002e, 0x1 }, - { 0x22002e, 0x2 }, { 0x90204, 0x0 }, { 0x190204, 0x0 }, - { 0x290204, 0x0 }, - - { 0x20024, 0xe3 }, - { 0x2003a, 0x2 }, - { 0x120024, 0xa3 }, - { 0x2003a, 0x2 }, - { 0x220024, 0xa3 }, - { 0x2003a, 0x2 }, - + { 0x20024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x120024, 0x1ab }, + { 0x2003a, 0x0 }, { 0x20056, 0x3 }, - { 0x120056, 0xa }, - { 0x220056, 0xa }, - + { 0x120056, 0x3 }, { 0x1004d, 0xe00 }, { 0x1014d, 0xe00 }, { 0x1104d, 0xe00 }, @@ -216,42 +193,22 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x11214d, 0xe00 }, { 0x11304d, 0xe00 }, { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - - { 0x10049, 0xfbe }, - { 0x10149, 0xfbe }, - { 0x11049, 0xfbe }, - { 0x11149, 0xfbe }, - { 0x12049, 0xfbe }, - { 0x12149, 0xfbe }, - { 0x13049, 0xfbe }, - { 0x13149, 0xfbe }, - - { 0x110049, 0xfbe }, - { 0x110149, 0xfbe }, - { 0x111049, 0xfbe }, - { 0x111149, 0xfbe }, - { 0x112049, 0xfbe }, - { 0x112149, 0xfbe }, - { 0x113049, 0xfbe }, - { 0x113149, 0xfbe }, - - { 0x210049, 0xfbe }, - { 0x210149, 0xfbe }, - { 0x211049, 0xfbe }, - { 0x211149, 0xfbe }, - { 0x212049, 0xfbe }, - { 0x212149, 0xfbe }, - { 0x213049, 0xfbe }, - { 0x213149, 0xfbe }, - + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, { 0x43, 0x63 }, { 0x1043, 0x63 }, { 0x2043, 0x63 }, @@ -262,15 +219,13 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x7043, 0x63 }, { 0x8043, 0x63 }, { 0x9043, 0x63 }, - { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, { 0x20008, 0x320 }, { 0x120008, 0xa7 }, - { 0x220008, 0x19 }, { 0x20088, 0x9 }, - { 0x200b2, 0x104 }, + { 0x200b2, 0xdc }, { 0x10043, 0x5a1 }, { 0x10143, 0x5a1 }, { 0x11043, 0x5a1 }, @@ -279,7 +234,7 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x12143, 0x5a1 }, { 0x13043, 0x5a1 }, { 0x13143, 0x5a1 }, - { 0x1200b2, 0x104 }, + { 0x1200b2, 0xdc }, { 0x110043, 0x5a1 }, { 0x110143, 0x5a1 }, { 0x111043, 0x5a1 }, @@ -288,270 +243,876 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { { 0x112143, 0x5a1 }, { 0x113043, 0x5a1 }, { 0x113143, 0x5a1 }, - { 0x2200b2, 0x104 }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, { 0x200fa, 0x1 }, { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, { 0x20019, 0x1 }, { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x600 }, + { 0x200f0, 0x0 }, { 0x200f1, 0x0 }, { 0x200f2, 0x4444 }, { 0x200f3, 0x8888 }, - { 0x200f4, 0x5655 }, + { 0x200f4, 0x5555 }, { 0x200f5, 0x0 }, { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, { 0x2002d, 0x0 }, { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x200ca, 0x106 }, + { 0x1200ca, 0x106 }, + { 0x20110, 0x2 }, + { 0x20111, 0x3 }, + { 0x20112, 0x4 }, + { 0x20113, 0x5 }, + { 0x20114, 0x0 }, + { 0x20115, 0x1 }, }; +/* ddr phy trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; /* P0 message block paremeter for training firmware */ -static struct dram_cfg_param lpddr4_fsp0_cfg[] = { +static struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xc80 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x131f }, - { 0x54009, LPDDR4_HDT_CTL_3200_1D }, - { 0x5400a, 0x0 }, + { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, { 0x54019, 0x2dd4 }, - { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0xd400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, }; + /* P1 message block paremeter for training firmware */ -static struct dram_cfg_param lpddr4_fsp1_cfg[] = { +static struct dram_cfg_param ddr_fsp1_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, { 0x54002, 0x1 }, { 0x54003, 0x29c }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, - { 0x5400a, 0x0 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, 0x0 }, - { 0x5400e, 0x0 }, - { 0x5400f, 0x0 }, - { 0x54010, 0x0 }, - { 0x54011, 0x0 }, { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - { 0x54019, 0x914 }, - { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) }, - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401e, 0x6 }, - { 0x5401f, 0x914 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x1) }, - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54019, 0x994 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x994 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, - { 0x54032, 0x1400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, 0x600 }, - { 0x54038, 0x1400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 }, - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, + { 0x54032, 0x9400 }, + { 0x54033, 0x3109 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0x9400 }, + { 0x54039, 0x3109 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, - }; + /* P0 2D message block paremeter for training firmware */ -static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, - { 0x54000, 0x0 }, - { 0x54001, 0x0 }, - { 0x54002, 0x0 }, { 0x54003, 0xc80 }, { 0x54004, 0x2 }, - { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, - { 0x54006, LPDDR4_PHY_VREF_VALUE }, - { 0x54007, 0x0 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, { 0x54008, 0x61 }, - { 0x54009, LPDDR4_HDT_CTL_2D }, - { 0x5400a, 0x0 }, + { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400c, 0x0 }, - { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) }, - { 0x5400e, 0x0 }, - { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 }, - { 0x54010, LPDDR4_2D_WEIGHT }, - { 0x54011, 0x0 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, { 0x54012, 0x310 }, - { 0x54013, 0x0 }, - { 0x54014, 0x0 }, - { 0x54015, 0x0 }, - { 0x54016, 0x0 }, - { 0x54017, 0x0 }, - { 0x54018, 0x0 }, - { 0x54024, 0x5 }, { 0x54019, 0x2dd4 }, - { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) }, - { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) }, - { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) }, - { 0x5401d, 0x0 }, - { 0x5401e, LPDDR4_MR22_RANK0 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, { 0x5401f, 0x2dd4 }, - { 0x54020, (((LPDDR4_RON) << 3) | 0x3) }, - { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | - (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) }, - { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) }, - { 0x54023, 0x0 }, - { 0x54024, LPDDR4_MR22_RANK1 }, - { 0x54025, 0x0 }, - { 0x54026, 0x0 }, - { 0x54027, 0x0 }, - { 0x54028, 0x0 }, - { 0x54029, 0x0 }, - { 0x5402a, 0x0 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, - { 0x5402d, 0x0 }, - { 0x5402e, 0x0 }, - { 0x5402f, 0x0 }, - { 0x54030, 0x0 }, - { 0x54031, 0x0 }, { 0x54032, 0xd400 }, - { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, - { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 }, - { 0x54037, (LPDDR4_MR22_RANK0 << 8) }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x84a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, { 0x54038, 0xd400 }, - { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d }, - { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) }, - { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) }, - { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 }, - { 0x5403d, (LPDDR4_MR22_RANK1 << 8) }, - { 0x5403e, 0x0 }, - { 0x5403f, 0x0 }, - { 0x54040, 0x0 }, - { 0x54041, 0x0 }, - { 0x54042, 0x0 }, - { 0x54043, 0x0 }, - { 0x54044, 0x0 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x84a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, - }; /* DRAM PHY init engine image */ -static struct dram_cfg_param lpddr4_phy_pie[] = { +static struct dram_cfg_param ddr_phy_pie[] = { { 0xd0000, 0x0 }, { 0x90000, 0x10 }, { 0x90001, 0x400 }, @@ -574,7 +1135,7 @@ static struct dram_cfg_param lpddr4_phy_pie[] = { { 0x90035, 0x2 }, { 0x90036, 0x10 }, { 0x90037, 0x139 }, - { 0x90038, 0xb }, + { 0x90038, 0xf }, { 0x90039, 0x7c0 }, { 0x9003a, 0x139 }, { 0x9003b, 0x44 }, @@ -682,12 +1243,9 @@ static struct dram_cfg_param lpddr4_phy_pie[] = { { 0x900a1, 0x5 }, { 0x900a2, 0x7c0 }, { 0x900a3, 0x109 }, - { 0x900a4, 0xd }, - { 0x900a5, 0x7c0 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, { 0x900a6, 0x109 }, - { 0x900a7, 0x4 }, - { 0x900a8, 0x7c0 }, - { 0x900a9, 0x109 }, { 0x40000, 0x811 }, { 0x40020, 0x880 }, { 0x40040, 0x0 }, @@ -796,237 +1354,234 @@ static struct dram_cfg_param lpddr4_phy_pie[] = { { 0x4003a, 0x880 }, { 0x4005a, 0x0 }, { 0x4007a, 0x0 }, - { 0x900aa, 0x0 }, - { 0x900ab, 0x790 }, - { 0x900ac, 0x11a }, - { 0x900ad, 0x8 }, - { 0x900ae, 0x7aa }, + { 0x900a7, 0x0 }, + { 0x900a8, 0x790 }, + { 0x900a9, 0x11a }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x7b2 }, { 0x900af, 0x2a }, - { 0x900b0, 0x10 }, - { 0x900b1, 0x7b2 }, - { 0x900b2, 0x2a }, - { 0x900b3, 0x0 }, - { 0x900b4, 0x7c8 }, - { 0x900b5, 0x109 }, - { 0x900b6, 0x10 }, - { 0x900b7, 0x10 }, - { 0x900b8, 0x109 }, - { 0x900b9, 0x10 }, - { 0x900ba, 0x2a8 }, - { 0x900bb, 0x129 }, - { 0x900bc, 0x8 }, - { 0x900bd, 0x370 }, - { 0x900be, 0x129 }, - { 0x900bf, 0xa }, - { 0x900c0, 0x3c8 }, - { 0x900c1, 0x1a9 }, - { 0x900c2, 0xc }, - { 0x900c3, 0x408 }, - { 0x900c4, 0x199 }, - { 0x900c5, 0x14 }, - { 0x900c6, 0x790 }, - { 0x900c7, 0x11a }, + { 0x900b0, 0x0 }, + { 0x900b1, 0x7c8 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x2a8 }, + { 0x900b5, 0x129 }, + { 0x900b6, 0x8 }, + { 0x900b7, 0x370 }, + { 0x900b8, 0x129 }, + { 0x900b9, 0xa }, + { 0x900ba, 0x3c8 }, + { 0x900bb, 0x1a9 }, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, { 0x900c8, 0x8 }, - { 0x900c9, 0x4 }, - { 0x900ca, 0x18 }, - { 0x900cb, 0xe }, - { 0x900cc, 0x408 }, - { 0x900cd, 0x199 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, { 0x900ce, 0x8 }, - { 0x900cf, 0x8568 }, - { 0x900d0, 0x108 }, - { 0x900d1, 0x18 }, - { 0x900d2, 0x790 }, - { 0x900d3, 0x16a }, - { 0x900d4, 0x8 }, - { 0x900d5, 0x1d8 }, - { 0x900d6, 0x169 }, - { 0x900d7, 0x10 }, - { 0x900d8, 0x8558 }, - { 0x900d9, 0x168 }, - { 0x900da, 0x70 }, - { 0x900db, 0x788 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, { 0x900dc, 0x16a }, - { 0x900dd, 0x1ff8 }, - { 0x900de, 0x85a8 }, - { 0x900df, 0x1e8 }, - { 0x900e0, 0x50 }, - { 0x900e1, 0x798 }, - { 0x900e2, 0x16a }, - { 0x900e3, 0x60 }, - { 0x900e4, 0x7a0 }, - { 0x900e5, 0x16a }, - { 0x900e6, 0x8 }, - { 0x900e7, 0x8310 }, - { 0x900e8, 0x168 }, - { 0x900e9, 0x8 }, - { 0x900ea, 0xa310 }, - { 0x900eb, 0x168 }, - { 0x900ec, 0xa }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, { 0x900ed, 0x408 }, { 0x900ee, 0x169 }, - { 0x900ef, 0x6e }, - { 0x900f0, 0x0 }, - { 0x900f1, 0x68 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, { 0x900f2, 0x0 }, - { 0x900f3, 0x408 }, - { 0x900f4, 0x169 }, - { 0x900f5, 0x0 }, - { 0x900f6, 0x8310 }, - { 0x900f7, 0x168 }, - { 0x900f8, 0x0 }, - { 0x900f9, 0xa310 }, - { 0x900fa, 0x168 }, - { 0x900fb, 0x1ff8 }, - { 0x900fc, 0x85a8 }, - { 0x900fd, 0x1e8 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, { 0x900fe, 0x68 }, - { 0x900ff, 0x798 }, + { 0x900ff, 0x790 }, { 0x90100, 0x16a }, - { 0x90101, 0x78 }, - { 0x90102, 0x7a0 }, - { 0x90103, 0x16a }, - { 0x90104, 0x68 }, - { 0x90105, 0x790 }, - { 0x90106, 0x16a }, - { 0x90107, 0x8 }, - { 0x90108, 0x8b10 }, - { 0x90109, 0x168 }, - { 0x9010a, 0x8 }, - { 0x9010b, 0xab10 }, - { 0x9010c, 0x168 }, - { 0x9010d, 0xa }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, { 0x9010e, 0x408 }, { 0x9010f, 0x169 }, - { 0x90110, 0x58 }, - { 0x90111, 0x0 }, - { 0x90112, 0x68 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, { 0x90113, 0x0 }, - { 0x90114, 0x408 }, - { 0x90115, 0x169 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, { 0x90116, 0x0 }, - { 0x90117, 0x8b10 }, - { 0x90118, 0x168 }, - { 0x90119, 0x0 }, - { 0x9011a, 0xab10 }, - { 0x9011b, 0x168 }, - { 0x9011c, 0x0 }, - { 0x9011d, 0x1d8 }, - { 0x9011e, 0x169 }, - { 0x9011f, 0x80 }, - { 0x90120, 0x790 }, - { 0x90121, 0x16a }, - { 0x90122, 0x18 }, - { 0x90123, 0x7aa }, - { 0x90124, 0x6a }, - { 0x90125, 0xa }, - { 0x90126, 0x0 }, - { 0x90127, 0x1e9 }, - { 0x90128, 0x8 }, - { 0x90129, 0x8080 }, - { 0x9012a, 0x108 }, - { 0x9012b, 0xf }, - { 0x9012c, 0x408 }, - { 0x9012d, 0x169 }, - { 0x9012e, 0xc }, - { 0x9012f, 0x0 }, - { 0x90130, 0x68 }, - { 0x90131, 0x9 }, - { 0x90132, 0x0 }, - { 0x90133, 0x1a9 }, - { 0x90134, 0x0 }, - { 0x90135, 0x408 }, - { 0x90136, 0x169 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, { 0x90137, 0x0 }, - { 0x90138, 0x8080 }, + { 0x90138, 0x8568 }, { 0x90139, 0x108 }, - { 0x9013a, 0x8 }, - { 0x9013b, 0x7aa }, - { 0x9013c, 0x6a }, - { 0x9013d, 0x0 }, - { 0x9013e, 0x8568 }, - { 0x9013f, 0x108 }, - { 0x90140, 0xb7 }, - { 0x90141, 0x790 }, - { 0x90142, 0x16a }, - { 0x90143, 0x1f }, - { 0x90144, 0x0 }, - { 0x90145, 0x68 }, - { 0x90146, 0x8 }, - { 0x90147, 0x8558 }, - { 0x90148, 0x168 }, - { 0x90149, 0xf }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, { 0x9014a, 0x408 }, { 0x9014b, 0x169 }, - { 0x9014c, 0xc }, - { 0x9014d, 0x0 }, - { 0x9014e, 0x68 }, - { 0x9014f, 0x0 }, - { 0x90150, 0x408 }, - { 0x90151, 0x169 }, - { 0x90152, 0x0 }, - { 0x90153, 0x8558 }, - { 0x90154, 0x168 }, - { 0x90155, 0x8 }, - { 0x90156, 0x3c8 }, - { 0x90157, 0x1a9 }, - { 0x90158, 0x3 }, - { 0x90159, 0x370 }, - { 0x9015a, 0x129 }, - { 0x9015b, 0x20 }, - { 0x9015c, 0x2aa }, - { 0x9015d, 0x9 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, { 0x9015e, 0x0 }, - { 0x9015f, 0x400 }, - { 0x90160, 0x10e }, - { 0x90161, 0x8 }, - { 0x90162, 0xe8 }, - { 0x90163, 0x109 }, - { 0x90164, 0x0 }, - { 0x90165, 0x8140 }, - { 0x90166, 0x10c }, - { 0x90167, 0x10 }, - { 0x90168, 0x8138 }, - { 0x90169, 0x10c }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, { 0x9016a, 0x8 }, - { 0x9016b, 0x7c8 }, - { 0x9016c, 0x101 }, - { 0x9016d, 0x8 }, - { 0x9016e, 0x0 }, - { 0x9016f, 0x8 }, - { 0x90170, 0x8 }, - { 0x90171, 0x448 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, { 0x90172, 0x109 }, - { 0x90173, 0xf }, - { 0x90174, 0x7c0 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, { 0x90175, 0x109 }, - { 0x90176, 0x0 }, - { 0x90177, 0xe8 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, { 0x90178, 0x109 }, - { 0x90179, 0x47 }, - { 0x9017a, 0x630 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, { 0x9017b, 0x109 }, - { 0x9017c, 0x8 }, - { 0x9017d, 0x618 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, { 0x9017e, 0x109 }, { 0x9017f, 0x8 }, - { 0x90180, 0xe0 }, - { 0x90181, 0x109 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, { 0x90182, 0x0 }, - { 0x90183, 0x7c8 }, - { 0x90184, 0x109 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, { 0x90185, 0x8 }, - { 0x90186, 0x8140 }, - { 0x90187, 0x10c }, - { 0x90188, 0x0 }, - { 0x90189, 0x1 }, - { 0x9018a, 0x8 }, - { 0x9018b, 0x8 }, - { 0x9018c, 0x4 }, - { 0x9018d, 0x8 }, - { 0x9018e, 0x8 }, - { 0x9018f, 0x7c8 }, - { 0x90190, 0x101 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, { 0x90006, 0x0 }, { 0x90007, 0x0 }, { 0x90008, 0x8 }, @@ -1035,8 +1590,8 @@ static struct dram_cfg_param lpddr4_phy_pie[] = { { 0x9000b, 0x0 }, { 0xd00e7, 0x400 }, { 0x90017, 0x0 }, - { 0x9001f, 0x2b }, - { 0x90026, 0x6c }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, { 0x400d0, 0x0 }, { 0x400d1, 0x101 }, { 0x400d2, 0x105 }, @@ -1054,10 +1609,6 @@ static struct dram_cfg_param lpddr4_phy_pie[] = { { 0x12000c, 0x29 }, { 0x12000d, 0x1a1 }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, { 0x9000c, 0x0 }, { 0x9000d, 0x173 }, { 0x9000e, 0x60 }, @@ -1068,6 +1619,8 @@ static struct dram_cfg_param lpddr4_phy_pie[] = { { 0x90013, 0x6152 }, { 0x20010, 0x5a }, { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, @@ -1080,12 +1633,6 @@ static struct dram_cfg_param lpddr4_phy_pie[] = { { 0x140083, 0x12 }, { 0x140084, 0xe0 }, { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, { 0x400fd, 0xf }, { 0x10011, 0x1 }, { 0x10012, 0x1 }, @@ -1143,49 +1690,47 @@ static struct dram_cfg_param lpddr4_phy_pie[] = { { 0x136b4, 0x1 }, { 0x137b4, 0x1 }, { 0x138b4, 0x1 }, - { 0x20089, 0x1 }, - { 0x20088, 0x19 }, + { 0x2003a, 0x2 }, { 0xc0080, 0x2 }, - { 0xd0000, 0x1 }, + { 0xd0000, 0x1 } }; -static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { { /* P0 3200mts 1D */ .drate = 3200, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), }, { /* P1 667mts 1D */ .drate = 667, .fw_type = FW_1D_IMAGE, - .fsp_cfg = lpddr4_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), }, { /* P0 3200mts 2D */ .drate = 3200, .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), }, }; -/* lpddr4 timing config params on EVK board */ +/* ddr timing config params */ struct dram_timing_info dram_timing_b0 = { - .ddrc_cfg = lpddr4_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), - .ddrphy_cfg = lpddr4_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), - .fsp_msg = lpddr4_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), - .ddrphy_pie = lpddr4_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), - /* - * this table must be initialized if DDRPHY bypass mode is - * not used: all fsp drate > 666MTS. - */ + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), .fsp_table = { 3200, 667, }, }; + diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index 82753585f2f..4dd8613e489 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -22,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -36,7 +38,7 @@ extern struct dram_timing_info dram_timing_b0; static void spl_dram_init(void) { /* ddr init */ - if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1) + if (soc_rev() >= CHIP_REV_2_1) ddr_init(&dram_timing); else ddr_init(&dram_timing_b0); @@ -125,7 +127,7 @@ int board_mmc_init(struct bd_info *bis) switch (i) { case 0: init_clk_usdhc(0); - usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); @@ -135,7 +137,7 @@ int board_mmc_init(struct bd_info *bis) break; case 1: init_clk_usdhc(1); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); @@ -199,6 +201,21 @@ int power_init_board(void) void spl_board_init(void) { +#ifdef CONFIG_FSL_CAAM + if (sec_init()) { + printf("\nsec_init failed!\n"); + } +#endif +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + + init_usb_clk(); + puts("Normal Boot\n"); } @@ -216,8 +233,8 @@ void board_init_f(ulong dummy) { int ret; - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); arch_cpu_init(); @@ -229,9 +246,6 @@ void board_init_f(ulong dummy) preloader_console_init(); - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - ret = spl_init(); if (ret) { debug("spl_init() failed: %d\n", ret); diff --git a/board/freescale/imx8mq_val/Kconfig b/board/freescale/imx8mq_val/Kconfig new file mode 100644 index 00000000000..56c4919f2b8 --- /dev/null +++ b/board/freescale/imx8mq_val/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MQ_DDR3L_VAL || TARGET_IMX8MQ_DDR4_VAL + +config SYS_BOARD + default "imx8mq_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8mq_val" + +endif diff --git a/board/freescale/imx8mq_val/Makefile b/board/freescale/imx8mq_val/Makefile new file mode 100644 index 00000000000..3681638bd7f --- /dev/null +++ b/board/freescale/imx8mq_val/Makefile @@ -0,0 +1,17 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mq_val.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += ddr/helper.o +ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL +obj-y += ddr/ddr3l/ddr_init.o ddr/ddr3l/ddrphy_train.o +else +obj-$(CONFIG_IMX8M_DDR4) += ddr4_timing.o +endif +endif diff --git a/board/freescale/imx8mq_val/ddr/ddr.h b/board/freescale/imx8mq_val/ddr/ddr.h new file mode 100644 index 00000000000..b42b04c1ebe --- /dev/null +++ b/board/freescale/imx8mq_val/ddr/ddr.h @@ -0,0 +1,17 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef SRC_DDRC_RCR_ADDR +#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000 +#endif +#ifndef DDR_CSD1_BASE_ADDR +#define DDR_CSD1_BASE_ADDR 0x40000000 +#endif + +void ddr_load_train_code(enum fw_type type); +int wait_ddrphy_training_complete(void); +void ddr3_phyinit_train_1600mts(void); +void ddr4_phyinit_train_2400mts(void); diff --git a/board/freescale/imx8mq_val/ddr/ddr3l/ddr_init.c b/board/freescale/imx8mq_val/ddr/ddr3l/ddr_init.c new file mode 100644 index 00000000000..0dfbb4a4a00 --- /dev/null +++ b/board/freescale/imx8mq_val/ddr/ddr3l/ddr_init.c @@ -0,0 +1,195 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include "../ddr.h" + +#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG +#define ddr_printf(args...) printf(args) +#else +#define ddr_printf(args...) +#endif + +#include "../wait_ddrphy_training_complete.c" + +static inline void reg32clrbit(unsigned long addr, u32 bit) +{ + clrbits_le32(addr, (1 << bit)); +} + +volatile unsigned int tmp; +void umctl2_cfg(void){ + reg32_write(DDRC_DBG1(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x00000001); + do{ + tmp = 0x7 & (reg32_read(DDRC_STAT(0))); + } while (tmp);/* wait init state */ + + reg32_write(DDRC_MSTR(0), 0x83040001);/* two rank */ + + reg32_write(DDRC_MRCTRL0(0), 0x40004030); + reg32_write(DDRC_MRCTRL1(0), 0x0001c68e); + reg32_write(DDRC_MRCTRL2(0), 0x921b7e95); + reg32_write(DDRC_DERATEEN(0), 0x00000506); + reg32_write(DDRC_DERATEINT(0), 0x9a4fbdf1); + reg32_write(DDRC_MSTR2(0), 0x00000001); + reg32_write(DDRC_PWRCTL(0), 0x000000a8); + reg32_write(DDRC_PWRTMG(0), 0x00532203); + reg32_write(DDRC_HWLPCTL(0), 0x0b6d0000); + reg32_write(DDRC_HWFFCCTL(0), 0x00000030); + reg32_write(DDRC_RFSHCTL0(0), 0x00203020); + reg32_write(DDRC_RFSHCTL1(0), 0x0001000d); + reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + reg32_write(DDRC_RFSHTMG(0), 0x0061008c); + reg32_write(DDRC_CRCPARCTL0(0), 0x00000000); + reg32_write(DDRC_CRCPARCTL1(0), 0x00000000); + reg32_write(DDRC_INIT0(0), 0xc0030002); + reg32_write(DDRC_INIT1(0), 0x0001000b); + reg32_write(DDRC_INIT2(0), 0x00006303); + reg32_write(DDRC_INIT3(0), 0x0d700044);/* MR1, MR0 */ + reg32_write(DDRC_INIT4(0), 0x00180000);/* MR2 */ + reg32_write(DDRC_INIT5(0), 0x00090071); + reg32_write(DDRC_INIT6(0), 0x00000000); + reg32_write(DDRC_INIT7(0), 0x00000000); + reg32_write(DDRC_DIMMCTL(0), 0x00000032); + reg32_write(DDRC_RANKCTL(0), 0x00000ee5); + reg32_write(DDRC_DRAMTMG0(0), 0x0c101a0e); + reg32_write(DDRC_DRAMTMG1(0), 0x000a0314); + reg32_write(DDRC_DRAMTMG2(0), 0x04060509); + reg32_write(DDRC_DRAMTMG3(0), 0x00002006); + reg32_write(DDRC_DRAMTMG4(0), 0x06020306); + reg32_write(DDRC_DRAMTMG5(0), 0x0b060202); + reg32_write(DDRC_DRAMTMG6(0), 0x060a0009); + reg32_write(DDRC_DRAMTMG7(0), 0x0000060b); + reg32_write(DDRC_DRAMTMG8(0), 0x01017c0a); + reg32_write(DDRC_DRAMTMG9(0), 0x4000000e); + reg32_write(DDRC_DRAMTMG10(0), 0x00070803); + reg32_write(DDRC_DRAMTMG11(0), 0x0101000b); + reg32_write(DDRC_DRAMTMG12(0), 0x00000000); + reg32_write(DDRC_DRAMTMG13(0), 0x5d000000); + reg32_write(DDRC_DRAMTMG14(0), 0x00000b39); + reg32_write(DDRC_DRAMTMG15(0), 0x80000000); + reg32_write(DDRC_DRAMTMG17(0), 0x00f1006a); + reg32_write(DDRC_ZQCTL0(0), 0x50800020); + reg32_write(DDRC_ZQCTL1(0), 0x00000070); + reg32_write(DDRC_ZQCTL2(0), 0x00000000); + reg32_write(DDRC_DFITMG0(0), 0x03868203); + reg32_write(DDRC_DFITMG1(0), 0x00020103); + reg32_write(DDRC_DFILPCFG0(0), 0x07713121); + reg32_write(DDRC_DFILPCFG1(0), 0x00000010); + reg32_write(DDRC_DFIUPD0(0), 0xe0400018); + reg32_write(DDRC_DFIUPD1(0), 0x0005003c); + reg32_write(DDRC_DFIUPD2(0), 0x00000000); + reg32_write(DDRC_DFIMISC(0), 0x00000011); + reg32_write(DDRC_DFITMG2(0), 0x00000603); + reg32_write(DDRC_DFITMG3(0), 0x00000001); + reg32_write(DDRC_DBICTL(0), 0x00000001); + reg32_write(DDRC_DFIPHYMSTR(0), 0x00000000); + + reg32_write(DDRC_ADDRMAP0(0), 0x00000016); /* [4:0] cs-bit0: 6+22=28; [12:8] cs-bit1: 7+0 */ + reg32_write(DDRC_ADDRMAP1(0), 0x00080808); /* [5:0] bank b0: 2+8; [13:8] b1: P3+8 ; [21:16] b2: 4+8 */ + reg32_write(DDRC_ADDRMAP2(0), 0x00000000); /* [3:0] col-b2: 2; [11:8] col-b3: 3; [19:16] col-b4: 4 ; [27:24] col-b5: 5 */ + reg32_write(DDRC_ADDRMAP3(0), 0x00000000); /* [3:0] col-b6: 6; [11:8] col-b7: 7; [19:16] col-b8: 8 ; [27:24] col-b9: 9 */ + reg32_write(DDRC_ADDRMAP4(0), 0x00001f1f); /* col-b10, col-b11 not used */ + reg32_write(DDRC_ADDRMAP5(0), 0x07070707); /* [3:0] row-b0: 6; [11:8] row-b1: 7; [19:16] row-b2_b10 ; [27:24] row-b11: 17 */ + reg32_write(DDRC_ADDRMAP6(0), 0x0f070707); /* [3:0] row-b12:18; [11:8] row-b13: 19; [19:16] row-b14:20 */ + reg32_write(DDRC_ADDRMAP7(0), 0x00000f0f); + reg32_write(DDRC_ADDRMAP8(0), 0x00000000); /* [5:0] bg-b0; [13:8]bg-b1 */ + reg32_write(DDRC_ADDRMAP9(0), 0x0a020b06); /* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP10(0), 0x0a0a0a0a);/* it's valid only when ADDRMAP5.addrmap_row_b2_10 is set to value 15 */ + reg32_write(DDRC_ADDRMAP11(0), 0x00000000); + + + reg32_write(DDRC_ODTCFG(0), 0x041d0f5c); + reg32_write(DDRC_ODTMAP(0), 0x00000201); + reg32_write(DDRC_SCHED(0), 0x7ab50b07); + reg32_write(DDRC_SCHED1(0), 0x00000022); + reg32_write(DDRC_PERFHPR1(0), 0x7b00665e); + reg32_write(DDRC_PERFLPR1(0), 0x2b00c4e1); + reg32_write(DDRC_PERFWR1(0), 0xb700c9fe); + reg32_write(DDRC_DBG0(0), 0x00000017); + reg32_write(DDRC_DBG1(0), 0x00000000); + reg32_write(DDRC_DBGCMD(0), 0x00000000); + reg32_write(DDRC_SWCTL(0), 0x00000001); + reg32_write(DDRC_POISONCFG(0), 0x00010000); + reg32_write(DDRC_PCCFG(0), 0x00000100); + reg32_write(DDRC_PCFGR_0(0), 0x00003051); + reg32_write(DDRC_PCFGW_0(0), 0x000061d2); + reg32_write(DDRC_PCTRL_0(0), 0x00000001); + reg32_write(DDRC_PCFGQOS0_0(0), 0x02100b04); + reg32_write(DDRC_PCFGQOS1_0(0), 0x003f0353); + reg32_write(DDRC_PCFGWQOS0_0(0), 0x00000002); + reg32_write(DDRC_PCFGWQOS1_0(0), 0x000005fd); +} + +int ddr_init(struct dram_timing_info *timing_info) +{ + /* change the clock source of dram_apb_clk_root */ + clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON | + CLK_ROOT_SOURCE_SEL(4) | + CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4)); + + /* disable the clock gating */ + reg32_write(0x303A00EC,0x0000ffff); + reg32setbit(0x303A00F8,5); + reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000); + + dram_pll_init(MHZ(400)); + + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006); + + /* Configure uMCTL2's registers */ + umctl2_cfg(); + + reg32setbit(DDRC_RFSHCTL3(0),0); /* dis_auto_refresh */ + reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000); + + ddr_load_train_code(FW_1D_IMAGE); + + reg32_write(DDRC_DBG1(0), 0x00000000); /* ('b00000000_00000000_00000000_00000000) ('d0) */ + reg32setbit(DDRC_PWRCTL(0),5); /* selfref_sw=1, self-refresh */ + reg32clrbit(DDRC_SWCTL(0), 0); /* sw_done=0, enable quasi-dynamic programming */ + reg32_write(DDRC_DFIMISC(0), 0x00000000); + + /* Configure DDR3L PHY's registers */ + ddr3_phyinit_train_1600mts(); + + do { + tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0x00020097); + } while (tmp != 0); + + reg32setbit(DDRC_DFIMISC(0),5);/* dfi_init_start=1 */ + do{ + tmp = 0x1 & (reg32_read(DDRC_DFISTAT(0))); + } while (!tmp);/* wait DFISTAT.dfi_init_complete to 1 */ + + reg32clrbit(DDRC_DFIMISC(0),5);/* dfi_init_start=0 */ + reg32setbit(DDRC_DFIMISC(0),0);/* dfi_init_complete_en=1 */ + + reg32clrbit(DDRC_PWRCTL(0),5);/* selfref_sw=0, exit self-refresh */ + + reg32setbit(DDRC_SWCTL(0), 0);/* sw_done=1, disable quasi-dynamic programming */ + + /* wait SWSTAT.sw_done_ack to 1 */ + do{ + tmp = 0x1 & (reg32_read(DDRC_SWSTAT(0))); + } while (!tmp); + + /* wait STAT to normal state */ + do{ + tmp = 0x7 & (reg32_read(DDRC_STAT(0))); + } while (tmp != 0x1); + + reg32_write(DDRC_PCTRL_0(0), 0x00000001); /* enable port 0 */ + + reg32clrbit(DDRC_RFSHCTL3(0), 0); /* auto-refresh enable */ + + return 0; +} diff --git a/board/freescale/imx8mq_val/ddr/ddr3l/ddrphy_train.c b/board/freescale/imx8mq_val/ddr/ddr3l/ddrphy_train.c new file mode 100644 index 00000000000..066ca7ff4b5 --- /dev/null +++ b/board/freescale/imx8mq_val/ddr/ddr3l/ddrphy_train.c @@ -0,0 +1,352 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include "../ddr.h" + +#define DDR3_MR1_RTT120_RON40 ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=00:40ohm */ +#define DDR3_MR1_RTT120_RON34 ((0L << 9) | (1L << 6) | (0L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=010:120ohm;Ron:M[5,1]=01:34ohm */ +#define DDR3_MR1_RTT60_RON40 ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=00:40ohm */ +#define DDR3_MR1_RTT60_RON34 ((0L << 9) | (0L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=001:60ohm;Ron:M[5,1]=01:34ohm */ +#define DDR3_MR1_RTT40_RON34 ((0L << 9) | (1L << 6) | (1L << 2) | (0L << 5) | (1L << 1)) /* RTT(NOM):M[9,6,2]=011:40ohm;Ron:M[5,1]=01:34ohm */ +#define DDR3_MR1_RTT_DIS_RON40 ((0L << 9) | (0L << 6) | (0L << 2) | (0L << 5) | (0L << 1)) /* RTT(NOM):M[9,6,2]=000:disable;Ron:M[5,1]=00:40ohm */ + +#define DDR3_PHY_RON40 40 /* 40ohm */ +#define DDR3_PHY_RON34 34 /* 34ohm */ + +#define DDR3_PHY_RTT120 120 /* 120ohm */ +#define DDR3_PHY_RTT60 60 /* 60ohm */ +#define DDR3_PHY_RTT40 40 /* 40ohm */ +#define DDR3_PHY_RTT48 48 /* 48ohm */ + +#define DDR3_RTT_WR_DIS 0UL +#define DDR3_RTT_WR_60 1UL +#define DDR3_RTT_WR_120 2UL + +#define DDR3_MR1_VAL DDR3_MR1_RTT120_RON40 +#define DDR3_MR2_RTT_WR_VAL DDR3_RTT_WR_DIS + +#define DDR3_PHY_RON DDR3_PHY_RON40 +#define DDR3_PHY_RTT DDR3_PHY_RTT120 + + +void ddr3_phyinit_train_1600mts(void){ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x1005f,0x3ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1015f,0x3ff); /* DWC_DDRPHYA_DBYTE0_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1105f,0x3ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1115f,0x3ff); /* DWC_DDRPHYA_DBYTE1_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1205f,0x3ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1215f,0x3ff); /* DWC_DDRPHYA_DBYTE2_TxSlewRate_b1_p0 */ + dwc_ddrphy_apb_wr(0x1305f,0x3ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b0_p0 */ + dwc_ddrphy_apb_wr(0x1315f,0x3ff); /* DWC_DDRPHYA_DBYTE3_TxSlewRate_b1_p0 */ + + dwc_ddrphy_apb_wr(0x55,0x3ff); /* DWC_DDRPHYA_ANIB0_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x1055,0x3ff); /* DWC_DDRPHYA_ANIB1_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x2055,0x3ff); /* DWC_DDRPHYA_ANIB2_ATxSlewRat */ + dwc_ddrphy_apb_wr(0x3055,0x3ff); /* DWC_DDRPHYA_ANIB3_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x4055,0xff); /* DWC_DDRPHYA_ANIB4_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x5055,0xff); /* DWC_DDRPHYA_ANIB5_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x6055,0x3ff); /* DWC_DDRPHYA_ANIB6_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x7055,0x3ff); /* DWC_DDRPHYA_ANIB7_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x8055,0x3ff); /* DWC_DDRPHYA_ANIB8_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x9055,0x3ff); /* DWC_DDRPHYA_ANIB9_ATxSlewRate */ + dwc_ddrphy_apb_wr(0x200c5,0xb); /* DWC_DDRPHYA_MASTER0_PllCtrl2_p0 */ + dwc_ddrphy_apb_wr(0x2002e,0x1); /* DWC_DDRPHYA_MASTER0_ARdPtrInitVal_p0 */ + + dwc_ddrphy_apb_wr(0x20024,0x8); /* DWC_DDRPHYA_MASTER0_DqsPreambleControl_p0 */ + dwc_ddrphy_apb_wr(0x2003a,0x0); /* DWC_DDRPHYA_MASTER0_DbyteDllModeCntrl */ + dwc_ddrphy_apb_wr(0x20056,0xa); /* DWC_DDRPHYA_MASTER0_ProcOdtTimeCtl_p0 */ + dwc_ddrphy_apb_wr(0x1004d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1014d,0x208); /* DWC_DDRPHYA_DBYTE0_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1104d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1114d,0x208); /* DWC_DDRPHYA_DBYTE1_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1204d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1214d,0x208); /* DWC_DDRPHYA_DBYTE2_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x1304d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b0_p0 */ + dwc_ddrphy_apb_wr(0x1314d,0x208); /* DWC_DDRPHYA_DBYTE3_TxOdtDrvStren_b1_p0 */ + dwc_ddrphy_apb_wr(0x10049,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x10149,0xe38); /* DWC_DDRPHYA_DBYTE0_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x11049,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x11149,0xe38); /* DWC_DDRPHYA_DBYTE1_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x12049,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x12149,0xe38); /* DWC_DDRPHYA_DBYTE2_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x13049,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b0_p0 */ + dwc_ddrphy_apb_wr(0x13149,0xe38); /* DWC_DDRPHYA_DBYTE3_TxImpedanceCtrl1_b1_p0 */ + dwc_ddrphy_apb_wr(0x43,0x63); /* DWC_DDRPHYA_ANIB0_ATxImpedance */ + dwc_ddrphy_apb_wr(0x1043,0x63); /* DWC_DDRPHYA_ANIB1_ATxImpedance */ + dwc_ddrphy_apb_wr(0x2043,0x63); /* DWC_DDRPHYA_ANIB2_ATxImpedance */ + dwc_ddrphy_apb_wr(0x3043,0x63); /* DWC_DDRPHYA_ANIB3_ATxImpedance */ + dwc_ddrphy_apb_wr(0x4043,0x63); /* DWC_DDRPHYA_ANIB4_ATxImpedance */ + dwc_ddrphy_apb_wr(0x5043,0x63); /* DWC_DDRPHYA_ANIB5_ATxImpedance */ + dwc_ddrphy_apb_wr(0x6043,0x63); /* DWC_DDRPHYA_ANIB6_ATxImpedance */ + dwc_ddrphy_apb_wr(0x7043,0x63); /* DWC_DDRPHYA_ANIB7_ATxImpedance */ + dwc_ddrphy_apb_wr(0x8043,0x63); /* DWC_DDRPHYA_ANIB8_ATxImpedance */ + dwc_ddrphy_apb_wr(0x9043,0x63); /* DWC_DDRPHYA_ANIB9_ATxImpedance */ + dwc_ddrphy_apb_wr(0x20018,0x5); /* DWC_DDRPHYA_MASTER0_DfiMode */ + dwc_ddrphy_apb_wr(0x20075,0x0); /* DWC_DDRPHYA_MASTER0_DfiCAMode */ + dwc_ddrphy_apb_wr(0x20050,0x0); /* DWC_DDRPHYA_MASTER0_CalDrvStr0 */ + dwc_ddrphy_apb_wr(0x20008,0x190); /* DWC_DDRPHYA_MASTER0_CalUclkInfo_p0 */ + dwc_ddrphy_apb_wr(0x20088,0x9); /* DWC_DDRPHYA_MASTER0_CalRate */ + dwc_ddrphy_apb_wr(0x200b2,0xf8); /* DWC_DDRPHYA_MASTER0_VrefInGlobal_p0 */ + dwc_ddrphy_apb_wr(0x10043,0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x10143,0x581); /* DWC_DDRPHYA_DBYTE0_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x11043,0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x11143,0x581); /* DWC_DDRPHYA_DBYTE1_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x12043,0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x12143,0x581); /* DWC_DDRPHYA_DBYTE2_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x13043,0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b0_p0 */ + dwc_ddrphy_apb_wr(0x13143,0x581); /* DWC_DDRPHYA_DBYTE3_DqDqsRcvCntrl_b1_p0 */ + dwc_ddrphy_apb_wr(0x200fa,0x1); /* DWC_DDRPHYA_MASTER0_DfiFreqRatio_p0 */ + dwc_ddrphy_apb_wr(0x20019,0x5); /* DWC_DDRPHYA_MASTER0_TristateModeCA_p0 */ + dwc_ddrphy_apb_wr(0x200f0,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat0 */ + dwc_ddrphy_apb_wr(0x200f1,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat1 */ + dwc_ddrphy_apb_wr(0x200f2,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat2 */ + dwc_ddrphy_apb_wr(0x200f3,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat3 */ + dwc_ddrphy_apb_wr(0x200f4,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat4 */ + dwc_ddrphy_apb_wr(0x200f5,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat5 */ + dwc_ddrphy_apb_wr(0x200f6,0x5555); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat6 */ + dwc_ddrphy_apb_wr(0x200f7,0xf000); /* DWC_DDRPHYA_MASTER0_DfiFreqXlat7 */ + dwc_ddrphy_apb_wr(0x2000b,0x33); /* DWC_DDRPHYA_MASTER0_Seq0BDLY0_p0 */ + dwc_ddrphy_apb_wr(0x2000c,0x65); /* DWC_DDRPHYA_MASTER0_Seq0BDLY1_p0 */ + dwc_ddrphy_apb_wr(0x2000d,0x3e9); /* DWC_DDRPHYA_MASTER0_Seq0BDLY2_p0 */ + dwc_ddrphy_apb_wr(0x2000e,0x2c); /* DWC_DDRPHYA_MASTER0_Seq0BDLY3_p0 */ + dwc_ddrphy_apb_wr(0x20025,0x0); /* DWC_DDRPHYA_MASTER0_MasterX4Config */ + dwc_ddrphy_apb_wr(0x2002d,0x0); /* DWC_DDRPHYA_MASTER0_DMIPinPresent_p0 */ + + dwc_ddrphy_apb_wr(0x20060,0x2); /* DWC_DDRPHYA_MASTER0_MemResetL */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x54000,0x0); + dwc_ddrphy_apb_wr(0x54001,0x0); + dwc_ddrphy_apb_wr(0x54002,0x0); + dwc_ddrphy_apb_wr(0x54003,0x640); + dwc_ddrphy_apb_wr(0x54004,0x2); + dwc_ddrphy_apb_wr(0x54005,((DDR3_PHY_RON << 8) | (DDR3_PHY_RTT << 0))); + dwc_ddrphy_apb_wr(0x54006,0x13b); + dwc_ddrphy_apb_wr(0x54007,0x2000); + + dwc_ddrphy_apb_wr(0x54008,0x303); /* two ranks */ + + dwc_ddrphy_apb_wr(0x54009,0x200); + dwc_ddrphy_apb_wr(0x5400a,0x0); + dwc_ddrphy_apb_wr(0x5400b,0x31f); + dwc_ddrphy_apb_wr(0x5400c,0xc8); + + dwc_ddrphy_apb_wr(0x54012,0x1); + dwc_ddrphy_apb_wr(0x5402f,0xd70); /* MR0 */ + dwc_ddrphy_apb_wr(0x54030,DDR3_MR1_VAL); /* MR1=6:Ron=34ohm/Rtt(NOM)=60ohm */ + dwc_ddrphy_apb_wr(0x54031,(0x18 | (DDR3_MR2_RTT_WR_VAL << 9))); /*MR2 */ + dwc_ddrphy_apb_wr(0x5403a,0x1221); + dwc_ddrphy_apb_wr(0x5403b,0x4884); + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0099,0x9); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0099,0x0); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + + wait_ddrphy_training_complete(); + + dwc_ddrphy_apb_wr(0xd0099,0x1); /* DWC_DDRPHYA_APBONLY0_MicroReset */ + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + + dwc_ddrphy_apb_wr(0xd0000,0x0); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ + dwc_ddrphy_apb_wr(0x90000,0x10); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90001,0x400); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90002,0x10e); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90003,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x90004,0x0); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x90005,0x8); /* DWC_DDRPHYA_INITENG0_PreSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x90029,0xb); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x9002a,0x480); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x9002b,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x9002c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9002d,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9002e,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0x9002f,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s0 */ + dwc_ddrphy_apb_wr(0x90030,0x478); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s1 */ + dwc_ddrphy_apb_wr(0x90031,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b2s2 */ + dwc_ddrphy_apb_wr(0x90032,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s0 */ + dwc_ddrphy_apb_wr(0x90033,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s1 */ + dwc_ddrphy_apb_wr(0x90034,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b3s2 */ + dwc_ddrphy_apb_wr(0x90035,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s0 */ + dwc_ddrphy_apb_wr(0x90036,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s1 */ + dwc_ddrphy_apb_wr(0x90037,0x139); /* DWC_DDRPHYA_INITENG0_SequenceReg0b4s2 */ + dwc_ddrphy_apb_wr(0x90038,0x44); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s0 */ + dwc_ddrphy_apb_wr(0x90039,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s1 */ + dwc_ddrphy_apb_wr(0x9003a,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b5s2 */ + dwc_ddrphy_apb_wr(0x9003b,0x14f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s0 */ + dwc_ddrphy_apb_wr(0x9003c,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s1 */ + dwc_ddrphy_apb_wr(0x9003d,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b6s2 */ + dwc_ddrphy_apb_wr(0x9003e,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s0 */ + dwc_ddrphy_apb_wr(0x9003f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s1 */ + dwc_ddrphy_apb_wr(0x90040,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b7s2 */ + dwc_ddrphy_apb_wr(0x90041,0x4f); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s0 */ + dwc_ddrphy_apb_wr(0x90042,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s1 */ + dwc_ddrphy_apb_wr(0x90043,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b8s2 */ + dwc_ddrphy_apb_wr(0x90044,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s0 */ + dwc_ddrphy_apb_wr(0x90045,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s1 */ + dwc_ddrphy_apb_wr(0x90046,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b9s2 */ + dwc_ddrphy_apb_wr(0x90047,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s0 */ + dwc_ddrphy_apb_wr(0x90048,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s1 */ + dwc_ddrphy_apb_wr(0x90049,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b10s2 */ + dwc_ddrphy_apb_wr(0x9004a,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s0 */ + dwc_ddrphy_apb_wr(0x9004b,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s1 */ + dwc_ddrphy_apb_wr(0x9004c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b11s2 */ + dwc_ddrphy_apb_wr(0x9004d,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s0 */ + dwc_ddrphy_apb_wr(0x9004e,0x45a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s1 */ + dwc_ddrphy_apb_wr(0x9004f,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b12s2 */ + dwc_ddrphy_apb_wr(0x90050,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s0 */ + dwc_ddrphy_apb_wr(0x90051,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s1 */ + dwc_ddrphy_apb_wr(0x90052,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b13s2 */ + dwc_ddrphy_apb_wr(0x90053,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s0 */ + dwc_ddrphy_apb_wr(0x90054,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s1 */ + dwc_ddrphy_apb_wr(0x90055,0x179); /* DWC_DDRPHYA_INITENG0_SequenceReg0b14s2 */ + dwc_ddrphy_apb_wr(0x90056,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s0 */ + dwc_ddrphy_apb_wr(0x90057,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s1 */ + dwc_ddrphy_apb_wr(0x90058,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b15s2 */ + dwc_ddrphy_apb_wr(0x90059,0x40c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s0 */ + dwc_ddrphy_apb_wr(0x9005a,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s1 */ + dwc_ddrphy_apb_wr(0x9005b,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b16s2 */ + dwc_ddrphy_apb_wr(0x9005c,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s0 */ + dwc_ddrphy_apb_wr(0x9005d,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s1 */ + dwc_ddrphy_apb_wr(0x9005e,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b17s2 */ + dwc_ddrphy_apb_wr(0x9005f,0x4040); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s0 */ + dwc_ddrphy_apb_wr(0x90060,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s1 */ + dwc_ddrphy_apb_wr(0x90061,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b18s2 */ + dwc_ddrphy_apb_wr(0x90062,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s0 */ + dwc_ddrphy_apb_wr(0x90063,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s1 */ + dwc_ddrphy_apb_wr(0x90064,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b19s2 */ + dwc_ddrphy_apb_wr(0x90065,0x40); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s0 */ + dwc_ddrphy_apb_wr(0x90066,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s1 */ + dwc_ddrphy_apb_wr(0x90067,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b20s2 */ + dwc_ddrphy_apb_wr(0x90068,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s0 */ + dwc_ddrphy_apb_wr(0x90069,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s1 */ + dwc_ddrphy_apb_wr(0x9006a,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b21s2 */ + dwc_ddrphy_apb_wr(0x9006b,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s0 */ + dwc_ddrphy_apb_wr(0x9006c,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s1 */ + dwc_ddrphy_apb_wr(0x9006d,0x78); /* DWC_DDRPHYA_INITENG0_SequenceReg0b22s2 */ + dwc_ddrphy_apb_wr(0x9006e,0x549); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s0 */ + dwc_ddrphy_apb_wr(0x9006f,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s1 */ + dwc_ddrphy_apb_wr(0x90070,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b23s2 */ + dwc_ddrphy_apb_wr(0x90071,0xd49); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s0 */ + dwc_ddrphy_apb_wr(0x90072,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s1 */ + dwc_ddrphy_apb_wr(0x90073,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b24s2 */ + dwc_ddrphy_apb_wr(0x90074,0x94a); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s0 */ + dwc_ddrphy_apb_wr(0x90075,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s1 */ + dwc_ddrphy_apb_wr(0x90076,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b25s2 */ + dwc_ddrphy_apb_wr(0x90077,0x441); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s0 */ + dwc_ddrphy_apb_wr(0x90078,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s1 */ + dwc_ddrphy_apb_wr(0x90079,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b26s2 */ + dwc_ddrphy_apb_wr(0x9007a,0x42); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s0 */ + dwc_ddrphy_apb_wr(0x9007b,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s1 */ + dwc_ddrphy_apb_wr(0x9007c,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b27s2 */ + dwc_ddrphy_apb_wr(0x9007d,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s0 */ + dwc_ddrphy_apb_wr(0x9007e,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s1 */ + dwc_ddrphy_apb_wr(0x9007f,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b28s2 */ + dwc_ddrphy_apb_wr(0x90080,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s0 */ + dwc_ddrphy_apb_wr(0x90081,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s1 */ + dwc_ddrphy_apb_wr(0x90082,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b29s2 */ + dwc_ddrphy_apb_wr(0x90083,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s0 */ + dwc_ddrphy_apb_wr(0x90084,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s1 */ + dwc_ddrphy_apb_wr(0x90085,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b30s2 */ + dwc_ddrphy_apb_wr(0x90086,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s0 */ + dwc_ddrphy_apb_wr(0x90087,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s1 */ + dwc_ddrphy_apb_wr(0x90088,0x149); /* DWC_DDRPHYA_INITENG0_SequenceReg0b31s2 */ + dwc_ddrphy_apb_wr(0x90089,0x9); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s0 */ + dwc_ddrphy_apb_wr(0x9008a,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s1 */ + dwc_ddrphy_apb_wr(0x9008b,0x159); /* DWC_DDRPHYA_INITENG0_SequenceReg0b32s2 */ + dwc_ddrphy_apb_wr(0x9008c,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s0 */ + dwc_ddrphy_apb_wr(0x9008d,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s1 */ + dwc_ddrphy_apb_wr(0x9008e,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b33s2 */ + dwc_ddrphy_apb_wr(0x9008f,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s0 */ + dwc_ddrphy_apb_wr(0x90090,0x3c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s1 */ + dwc_ddrphy_apb_wr(0x90091,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b34s2 */ + dwc_ddrphy_apb_wr(0x90092,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s0 */ + dwc_ddrphy_apb_wr(0x90093,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s1 */ + dwc_ddrphy_apb_wr(0x90094,0x48); /* DWC_DDRPHYA_INITENG0_SequenceReg0b35s2 */ + dwc_ddrphy_apb_wr(0x90095,0x18); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s0 */ + dwc_ddrphy_apb_wr(0x90096,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s1 */ + dwc_ddrphy_apb_wr(0x90097,0x58); /* DWC_DDRPHYA_INITENG0_SequenceReg0b36s2 */ + dwc_ddrphy_apb_wr(0x90098,0xa); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s0 */ + dwc_ddrphy_apb_wr(0x90099,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s1 */ + dwc_ddrphy_apb_wr(0x9009a,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b37s2 */ + dwc_ddrphy_apb_wr(0x9009b,0x2); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s0 */ + dwc_ddrphy_apb_wr(0x9009c,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s1 */ + dwc_ddrphy_apb_wr(0x9009d,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b38s2 */ + dwc_ddrphy_apb_wr(0x9009e,0x7); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s0 */ + dwc_ddrphy_apb_wr(0x9009f,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s1 */ + dwc_ddrphy_apb_wr(0x900a0,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b39s2 */ + dwc_ddrphy_apb_wr(0x900a1,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s0 */ + dwc_ddrphy_apb_wr(0x900a2,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s1 */ + dwc_ddrphy_apb_wr(0x900a3,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b40s2 */ + dwc_ddrphy_apb_wr(0x900a4,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s0 */ + dwc_ddrphy_apb_wr(0x900a5,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s1 */ + dwc_ddrphy_apb_wr(0x900a6,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b41s2 */ + dwc_ddrphy_apb_wr(0x900a7,0x10); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s0 */ + dwc_ddrphy_apb_wr(0x900a8,0x8138); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s1 */ + dwc_ddrphy_apb_wr(0x900a9,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b42s2 */ + dwc_ddrphy_apb_wr(0x900aa,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s0 */ + dwc_ddrphy_apb_wr(0x900ab,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s1 */ + dwc_ddrphy_apb_wr(0x900ac,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b43s2 */ + dwc_ddrphy_apb_wr(0x900ad,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s0 */ + dwc_ddrphy_apb_wr(0x900ae,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s1 */ + dwc_ddrphy_apb_wr(0x900af,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b44s2 */ + dwc_ddrphy_apb_wr(0x900b0,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s0 */ + dwc_ddrphy_apb_wr(0x900b1,0x448); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s1 */ + dwc_ddrphy_apb_wr(0x900b2,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b45s2 */ + dwc_ddrphy_apb_wr(0x900b3,0xf); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s0 */ + dwc_ddrphy_apb_wr(0x900b4,0x7c0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s1 */ + dwc_ddrphy_apb_wr(0x900b5,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b46s2 */ + dwc_ddrphy_apb_wr(0x900b6,0x47); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s0 */ + dwc_ddrphy_apb_wr(0x900b7,0x630); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s1 */ + dwc_ddrphy_apb_wr(0x900b8,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b47s2 */ + dwc_ddrphy_apb_wr(0x900b9,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s0 */ + dwc_ddrphy_apb_wr(0x900ba,0x618); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s1 */ + dwc_ddrphy_apb_wr(0x900bb,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b48s2 */ + dwc_ddrphy_apb_wr(0x900bc,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s0 */ + dwc_ddrphy_apb_wr(0x900bd,0xe0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s1 */ + dwc_ddrphy_apb_wr(0x900be,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b49s2 */ + dwc_ddrphy_apb_wr(0x900bf,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s0 */ + dwc_ddrphy_apb_wr(0x900c0,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s1 */ + dwc_ddrphy_apb_wr(0x900c1,0x109); /* DWC_DDRPHYA_INITENG0_SequenceReg0b50s2 */ + dwc_ddrphy_apb_wr(0x900c2,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s0 */ + dwc_ddrphy_apb_wr(0x900c3,0x8140); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s1 */ + dwc_ddrphy_apb_wr(0x900c4,0x10c); /* DWC_DDRPHYA_INITENG0_SequenceReg0b51s2 */ + dwc_ddrphy_apb_wr(0x900c5,0x0); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s0 */ + dwc_ddrphy_apb_wr(0x900c6,0x1); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s1 */ + dwc_ddrphy_apb_wr(0x900c7,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b52s2 */ + dwc_ddrphy_apb_wr(0x900c8,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s0 */ + dwc_ddrphy_apb_wr(0x900c9,0x4); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s1 */ + dwc_ddrphy_apb_wr(0x900ca,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b53s2 */ + dwc_ddrphy_apb_wr(0x900cb,0x8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s0 */ + dwc_ddrphy_apb_wr(0x900cc,0x7c8); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s1 */ + dwc_ddrphy_apb_wr(0x900cd,0x101); /* DWC_DDRPHYA_INITENG0_SequenceReg0b54s2 */ + dwc_ddrphy_apb_wr(0x90006,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s0 */ + dwc_ddrphy_apb_wr(0x90007,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s1 */ + dwc_ddrphy_apb_wr(0x90008,0x8); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b0s2 */ + dwc_ddrphy_apb_wr(0x90009,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s0 */ + dwc_ddrphy_apb_wr(0x9000a,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s1 */ + dwc_ddrphy_apb_wr(0x9000b,0x0); /* DWC_DDRPHYA_INITENG0_PostSequenceReg0b1s2 */ + dwc_ddrphy_apb_wr(0xd00e7,0x400); /* DWC_DDRPHYA_APBONLY0_SequencerOverride */ + dwc_ddrphy_apb_wr(0x90017,0x0); /* DWC_DDRPHYA_INITENG0_StartVector0b0 */ + dwc_ddrphy_apb_wr(0x90026,0x2c); /* DWC_DDRPHYA_INITENG0_StartVector0b15 */ + dwc_ddrphy_apb_wr(0x9000c,0x0); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag0 */ + dwc_ddrphy_apb_wr(0x9000d,0x173); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag1 */ + dwc_ddrphy_apb_wr(0x9000e,0x60); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag2 */ + dwc_ddrphy_apb_wr(0x9000f,0x6110); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag3 */ + dwc_ddrphy_apb_wr(0x90010,0x2152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag4 */ + dwc_ddrphy_apb_wr(0x90011,0xdfbd); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag5 */ + dwc_ddrphy_apb_wr(0x90012,0xffff); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag6 */ + dwc_ddrphy_apb_wr(0x90013,0x6152); /* DWC_DDRPHYA_INITENG0_Seq0BDisableFlag7 */ + dwc_ddrphy_apb_wr(0xc0080,0x0); /* DWC_DDRPHYA_DRTUB0_UcclkHclkEnables */ + dwc_ddrphy_apb_wr(0xd0000,0x1); /* DWC_DDRPHYA_APBONLY0_MicroContMuxSel */ +} diff --git a/board/freescale/imx8mq_val/ddr/helper.c b/board/freescale/imx8mq_val/ddr/helper.c new file mode 100644 index 00000000000..b9a9bd24635 --- /dev/null +++ b/board/freescale/imx8mq_val/ddr/helper.c @@ -0,0 +1,104 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define IMEM_LEN 32768 +#define DMEM_LEN 16384 +#define IMEM_2D_OFFSET 49152 + +#define IMEM_OFFSET_ADDR 0x00050000 +#define DMEM_OFFSET_ADDR 0x00054000 +#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0) + +/* We need PHY iMEM PHY is 32KB padded */ +void ddr_load_train_code(enum fw_type type) +{ + u32 tmp32, i; + u32 error = 0; + unsigned long pr_to32, pr_from32; + unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0; + unsigned long imem_start = (unsigned long)&_end + fw_offset; + unsigned long dmem_start = imem_start + IMEM_LEN; + + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN; ){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = readl(pr_from32); + writew(tmp32 & 0x0000ffff, pr_to32); + pr_to32 += 4; + writew((tmp32 >> 16) & 0x0000ffff, pr_to32); + pr_to32 += 4; + pr_from32 += 4; + i += 4; + } + + printf("check ddr_imem code\n"); + pr_from32 = imem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR; + for(i = 0x0; i < IMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + if(error){ + printf("check ddr_imem code fail=%d\n",error); + }else{ + printf("check ddr_imem code pass\n"); + } + + printf("check ddr_dmem code\n"); + pr_from32 = dmem_start; + pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR; + for(i = 0x0; i < DMEM_LEN;){ + tmp32 = (readw(pr_to32) & 0x0000ffff); + pr_to32 += 4; + tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16); + if(tmp32 != readl(pr_from32)){ + printf("%lx %lx\n", pr_from32, pr_to32); + error++; + } + pr_from32 += 4; + pr_to32 += 4; + i += 4; + } + + if(error){ + printf("check ddr_dmem code fail=%d",error); + }else{ + printf("check ddr_dmem code pass\n"); + } +} diff --git a/board/freescale/imx8mq_val/ddr/wait_ddrphy_training_complete.c b/board/freescale/imx8mq_val/ddr/wait_ddrphy_training_complete.c new file mode 100644 index 00000000000..e44072280ee --- /dev/null +++ b/board/freescale/imx8mq_val/ddr/wait_ddrphy_training_complete.c @@ -0,0 +1,96 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +static inline void poll_pmu_message_ready(void) +{ + unsigned int reg; + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (reg & 0x1); +} + +static inline void ack_pmu_message_recieve(void) +{ + unsigned int reg; + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x0); + + do { + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0004); + } while (!(reg & 0x1)); + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0031,0x1); +} + +static inline unsigned int get_mail(void) +{ + unsigned int reg; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + ack_pmu_message_recieve(); + + return reg; +} + +static inline unsigned int get_stream_message(void) +{ + unsigned int reg, reg2; + + poll_pmu_message_ready(); + + reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0032); + + reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0)+4*0xd0034); + + reg2 = (reg2 << 16) | reg; + + ack_pmu_message_recieve(); + + return reg2; +} + +static inline void decode_major_message(unsigned int mail) +{ + ddr_printf("[PMU Major message = 0x%08x]\n", mail); +} + +static inline void decode_streaming_message(void) +{ + unsigned int string_index, arg __maybe_unused; + int i = 0; + + string_index = get_stream_message(); + ddr_printf(" PMU String index = 0x%08x\n", string_index); + while (i < (string_index & 0xffff)){ + arg = get_stream_message(); + ddr_printf(" arg[%d] = 0x%08x\n", i, arg); + i++; + } + + ddr_printf("\n"); +} + +int wait_ddrphy_training_complete(void) +{ + unsigned int mail; + while (1) { + mail = get_mail(); + decode_major_message(mail); + if (mail == 0x08) { + decode_streaming_message(); + } else if (mail == 0x07) { + printf("Training PASS\n"); + return 0; + } else if (mail == 0xff) { + printf("Training FAILED\n"); + return -1; + } + } +} diff --git a/board/freescale/imx8mq_val/ddr4_timing.c b/board/freescale/imx8mq_val/ddr4_timing.c new file mode 100644 index 00000000000..5c8c3dcfe18 --- /dev/null +++ b/board/freescale/imx8mq_val/ddr4_timing.c @@ -0,0 +1,1409 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga + * For imx_v2019.04_5.4.x and above version: + * please replace #include with #include + */ + +#include +#include + +struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0x83040010 }, + { 0x3d400028, 0x1 }, + { 0x3d400030, 0xaa }, + { 0x3d400034, 0x221306 }, + { 0x3d400038, 0x840000 }, + { 0x3d40003c, 0x30 }, + { 0x3d400050, 0x210070 }, + { 0x3d400054, 0x10008 }, + { 0x3d400060, 0x10 }, + { 0x3d400064, 0x49009c }, + { 0x3d4000c0, 0x0 }, + { 0x3d4000c4, 0x1000 }, + { 0x3d4000d0, 0xc0030126 }, + { 0x3d4000d4, 0x770000 }, + { 0x3d4000dc, 0x8340001 }, + { 0x3d4000e0, 0x180240 }, + { 0x3d4000e4, 0x110000 }, + { 0x3d4000e8, 0x2000640 }, + { 0x3d4000ec, 0x816 }, + { 0x3d4000f0, 0x22 }, + { 0x3d4000f4, 0x527 }, + { 0x3d400100, 0x11122914 }, + { 0x3d400104, 0x4051c }, + { 0x3d400108, 0x608050d }, + { 0x3d40010c, 0x400c }, + { 0x3d400110, 0x8030409 }, + { 0x3d400114, 0x6060403 }, + { 0x3d40011c, 0x606 }, + { 0x3d400120, 0x5050d08 }, + { 0x3d400124, 0x2040a }, + { 0x3d40012c, 0x1409010e }, + { 0x3d400130, 0x8 }, + { 0x3d40013c, 0x0 }, + { 0x3d400180, 0x1000040 }, + { 0x3d400184, 0x493e }, + { 0x3d400190, 0x38b8207 }, + { 0x3d400194, 0x2020303 }, + { 0x3d400198, 0x7f04011 }, + { 0x3d40019c, 0xb0 }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0x48005a }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x1 }, + { 0x3d4001b4, 0xb07 }, + { 0x3d4001b8, 0x4 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x0 }, + { 0x3d400200, 0x3f17 }, + { 0x3d400204, 0x3f0909 }, + { 0x3d400208, 0x700 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d40021c, 0xf0f }, + { 0x3d400220, 0x3f01 }, + { 0x3d400240, 0x6000610 }, + { 0x3d400244, 0x1323 }, + { 0x3d400250, 0x317d1a07 }, + { 0x3d400254, 0xf }, + { 0x3d40025c, 0x2a001b76 }, + { 0x3d400264, 0x9 }, + { 0x3d40026c, 0x30000e06 }, + { 0x3d400300, 0x14 }, + { 0x3d400304, 0x0 }, + { 0x3d40030c, 0x0 }, + { 0x3d400320, 0x1 }, + { 0x3d40036c, 0x10 }, + { 0x3d400400, 0x11 }, + { 0x3d400404, 0x13193 }, + { 0x3d400408, 0x6096 }, + { 0x3d400490, 0x1 }, + { 0x3d400494, 0x2000c00 }, + { 0x3d400498, 0x3c00db }, + { 0x3d40049c, 0x100001 }, + { 0x3d4004a0, 0x41f }, + { 0x3d402050, 0x210070 }, + { 0x3d402064, 0x300068 }, + { 0x3d4020dc, 0x2100001 }, + { 0x3d4020e0, 0x40 }, + { 0x3d4020e8, 0x2000640 }, + { 0x3d4020ec, 0x416 }, + { 0x3d402100, 0xd0c1b0d }, + { 0x3d402104, 0x30313 }, + { 0x3d402108, 0x506040a }, + { 0x3d40210c, 0x400c }, + { 0x3d402110, 0x6030306 }, + { 0x3d402114, 0x4040302 }, + { 0x3d40211c, 0x404 }, + { 0x3d402120, 0x4040d06 }, + { 0x3d402124, 0x20308 }, + { 0x3d40212c, 0x1206010e }, + { 0x3d402130, 0x8 }, + { 0x3d40213c, 0x0 }, + { 0x3d402180, 0x1000040 }, + { 0x3d402190, 0x3868204 }, + { 0x3d402194, 0x2020303 }, + { 0x3d4021b4, 0x604 }, + { 0x3d4021b8, 0x4 }, + { 0x3d402240, 0x6000608 }, + { 0x3d403050, 0x210070 }, + { 0x3d403064, 0x200045 }, + { 0x3d4030dc, 0x1 }, + { 0x3d4030e0, 0x40 }, + { 0x3d4030e8, 0x2000640 }, + { 0x3d4030ec, 0x16 }, + { 0x3d403100, 0xb081209 }, + { 0x3d403104, 0x2020d }, + { 0x3d403108, 0x5050309 }, + { 0x3d40310c, 0x400c }, + { 0x3d403110, 0x4030205 }, + { 0x3d403114, 0x3030202 }, + { 0x3d40311c, 0x303 }, + { 0x3d403120, 0x3040d04 }, + { 0x3d403124, 0x20208 }, + { 0x3d40312c, 0x1005010e }, + { 0x3d403130, 0x8 }, + { 0x3d40313c, 0x0 }, + { 0x3d403180, 0x1000040 }, + { 0x3d403190, 0x3848204 }, + { 0x3d403194, 0x2020303 }, + { 0x3d4031b4, 0x404 }, + { 0x3d4031b8, 0x4 }, + { 0x3d403240, 0x6000600 }, + { 0x3d400060, 0x11 }, +}; + +/* PHY Initialize Configuration */ +struct dram_cfg_param ddr_ddrphy_cfg[] = { + { 0x1005f, 0x2ff }, + { 0x1015f, 0x2ff }, + { 0x1105f, 0x2ff }, + { 0x1115f, 0x2ff }, + { 0x1205f, 0x2ff }, + { 0x1215f, 0x2ff }, + { 0x1305f, 0x2ff }, + { 0x1315f, 0x2ff }, + { 0x11005f, 0x2ff }, + { 0x11015f, 0x2ff }, + { 0x11105f, 0x2ff }, + { 0x11115f, 0x2ff }, + { 0x11205f, 0x2ff }, + { 0x11215f, 0x2ff }, + { 0x11305f, 0x2ff }, + { 0x11315f, 0x2ff }, + { 0x21005f, 0x2ff }, + { 0x21015f, 0x2ff }, + { 0x21105f, 0x2ff }, + { 0x21115f, 0x2ff }, + { 0x21205f, 0x2ff }, + { 0x21215f, 0x2ff }, + { 0x21305f, 0x2ff }, + { 0x21315f, 0x2ff }, + { 0x55, 0x3ff }, + { 0x1055, 0x3ff }, + { 0x2055, 0x3ff }, + { 0x3055, 0x3ff }, + { 0x4055, 0xff }, + { 0x5055, 0xff }, + { 0x6055, 0x3ff }, + { 0x7055, 0x3ff }, + { 0x8055, 0x3ff }, + { 0x9055, 0x3ff }, + { 0x200c5, 0xa }, + { 0x1200c5, 0xb }, + { 0x2200c5, 0x6 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x1 }, + { 0x22002e, 0x1 }, + { 0x20024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x120024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x220024, 0x8 }, + { 0x2003a, 0x2 }, + { 0x20056, 0x6 }, + { 0x120056, 0xa }, + { 0x220056, 0xa }, + { 0x1004d, 0x38 }, + { 0x1014d, 0x38 }, + { 0x1104d, 0x38 }, + { 0x1114d, 0x38 }, + { 0x1204d, 0x38 }, + { 0x1214d, 0x38 }, + { 0x1304d, 0x38 }, + { 0x1314d, 0x38 }, + { 0x11004d, 0x38 }, + { 0x11014d, 0x38 }, + { 0x11104d, 0x38 }, + { 0x11114d, 0x38 }, + { 0x11204d, 0x38 }, + { 0x11214d, 0x38 }, + { 0x11304d, 0x38 }, + { 0x11314d, 0x38 }, + { 0x21004d, 0x38 }, + { 0x21014d, 0x38 }, + { 0x21104d, 0x38 }, + { 0x21114d, 0x38 }, + { 0x21204d, 0x38 }, + { 0x21214d, 0x38 }, + { 0x21304d, 0x38 }, + { 0x21314d, 0x38 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x5 }, + { 0x20075, 0x2 }, + { 0x20050, 0x0 }, + { 0x20008, 0x258 }, + { 0x120008, 0x190 }, + { 0x220008, 0x10a }, + { 0x20088, 0x9 }, + { 0x200b2, 0x78 }, + { 0x10043, 0x5b1 }, + { 0x10143, 0x5b1 }, + { 0x11043, 0x5b1 }, + { 0x11143, 0x5b1 }, + { 0x12043, 0x5b1 }, + { 0x12143, 0x5b1 }, + { 0x13043, 0x5b1 }, + { 0x13143, 0x5b1 }, + { 0x1200b2, 0x78 }, + { 0x110043, 0x5b1 }, + { 0x110143, 0x5b1 }, + { 0x111043, 0x5b1 }, + { 0x111143, 0x5b1 }, + { 0x112043, 0x5b1 }, + { 0x112143, 0x5b1 }, + { 0x113043, 0x5b1 }, + { 0x113143, 0x5b1 }, + { 0x2200b2, 0x78 }, + { 0x210043, 0x5b1 }, + { 0x210143, 0x5b1 }, + { 0x211043, 0x5b1 }, + { 0x211143, 0x5b1 }, + { 0x212043, 0x5b1 }, + { 0x212143, 0x5b1 }, + { 0x213043, 0x5b1 }, + { 0x213143, 0x5b1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x5 }, + { 0x120019, 0x5 }, + { 0x220019, 0x5 }, + { 0x200f0, 0x5555 }, + { 0x200f1, 0x5555 }, + { 0x200f2, 0x5555 }, + { 0x200f3, 0x5555 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0x5555 }, + { 0x200f6, 0x5555 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x2200c7, 0x80 }, + { 0x200ca, 0x106 }, + { 0x1200ca, 0x106 }, + { 0x2200ca, 0x106 }, + { 0x20110, 0x2 }, + { 0x20111, 0x3 }, + { 0x20112, 0x4 }, + { 0x20113, 0x5 }, + { 0x20114, 0x0 }, + { 0x20115, 0x1 }, +}; + +/* ddr phy trained csr */ +struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x200b2, 0x0 }, + { 0x1200b2, 0x0 }, + { 0x2200b2, 0x0 }, + { 0x200cb, 0x0 }, + { 0x10043, 0x0 }, + { 0x110043, 0x0 }, + { 0x210043, 0x0 }, + { 0x10143, 0x0 }, + { 0x110143, 0x0 }, + { 0x210143, 0x0 }, + { 0x11043, 0x0 }, + { 0x111043, 0x0 }, + { 0x211043, 0x0 }, + { 0x11143, 0x0 }, + { 0x111143, 0x0 }, + { 0x211143, 0x0 }, + { 0x12043, 0x0 }, + { 0x112043, 0x0 }, + { 0x212043, 0x0 }, + { 0x12143, 0x0 }, + { 0x112143, 0x0 }, + { 0x212143, 0x0 }, + { 0x13043, 0x0 }, + { 0x113043, 0x0 }, + { 0x213043, 0x0 }, + { 0x13143, 0x0 }, + { 0x113143, 0x0 }, + { 0x213143, 0x0 }, + { 0x80, 0x0 }, + { 0x100080, 0x0 }, + { 0x200080, 0x0 }, + { 0x1080, 0x0 }, + { 0x101080, 0x0 }, + { 0x201080, 0x0 }, + { 0x2080, 0x0 }, + { 0x102080, 0x0 }, + { 0x202080, 0x0 }, + { 0x3080, 0x0 }, + { 0x103080, 0x0 }, + { 0x203080, 0x0 }, + { 0x4080, 0x0 }, + { 0x104080, 0x0 }, + { 0x204080, 0x0 }, + { 0x5080, 0x0 }, + { 0x105080, 0x0 }, + { 0x205080, 0x0 }, + { 0x6080, 0x0 }, + { 0x106080, 0x0 }, + { 0x206080, 0x0 }, + { 0x7080, 0x0 }, + { 0x107080, 0x0 }, + { 0x207080, 0x0 }, + { 0x8080, 0x0 }, + { 0x108080, 0x0 }, + { 0x208080, 0x0 }, + { 0x9080, 0x0 }, + { 0x109080, 0x0 }, + { 0x209080, 0x0 }, + { 0x10080, 0x0 }, + { 0x110080, 0x0 }, + { 0x210080, 0x0 }, + { 0x10180, 0x0 }, + { 0x110180, 0x0 }, + { 0x210180, 0x0 }, + { 0x11080, 0x0 }, + { 0x111080, 0x0 }, + { 0x211080, 0x0 }, + { 0x11180, 0x0 }, + { 0x111180, 0x0 }, + { 0x211180, 0x0 }, + { 0x12080, 0x0 }, + { 0x112080, 0x0 }, + { 0x212080, 0x0 }, + { 0x12180, 0x0 }, + { 0x112180, 0x0 }, + { 0x212180, 0x0 }, + { 0x13080, 0x0 }, + { 0x113080, 0x0 }, + { 0x213080, 0x0 }, + { 0x13180, 0x0 }, + { 0x113180, 0x0 }, + { 0x213180, 0x0 }, + { 0x10081, 0x0 }, + { 0x110081, 0x0 }, + { 0x210081, 0x0 }, + { 0x10181, 0x0 }, + { 0x110181, 0x0 }, + { 0x210181, 0x0 }, + { 0x11081, 0x0 }, + { 0x111081, 0x0 }, + { 0x211081, 0x0 }, + { 0x11181, 0x0 }, + { 0x111181, 0x0 }, + { 0x211181, 0x0 }, + { 0x12081, 0x0 }, + { 0x112081, 0x0 }, + { 0x212081, 0x0 }, + { 0x12181, 0x0 }, + { 0x112181, 0x0 }, + { 0x212181, 0x0 }, + { 0x13081, 0x0 }, + { 0x113081, 0x0 }, + { 0x213081, 0x0 }, + { 0x13181, 0x0 }, + { 0x113181, 0x0 }, + { 0x213181, 0x0 }, + { 0x100d0, 0x0 }, + { 0x1100d0, 0x0 }, + { 0x2100d0, 0x0 }, + { 0x101d0, 0x0 }, + { 0x1101d0, 0x0 }, + { 0x2101d0, 0x0 }, + { 0x110d0, 0x0 }, + { 0x1110d0, 0x0 }, + { 0x2110d0, 0x0 }, + { 0x111d0, 0x0 }, + { 0x1111d0, 0x0 }, + { 0x2111d0, 0x0 }, + { 0x120d0, 0x0 }, + { 0x1120d0, 0x0 }, + { 0x2120d0, 0x0 }, + { 0x121d0, 0x0 }, + { 0x1121d0, 0x0 }, + { 0x2121d0, 0x0 }, + { 0x130d0, 0x0 }, + { 0x1130d0, 0x0 }, + { 0x2130d0, 0x0 }, + { 0x131d0, 0x0 }, + { 0x1131d0, 0x0 }, + { 0x2131d0, 0x0 }, + { 0x100d1, 0x0 }, + { 0x1100d1, 0x0 }, + { 0x2100d1, 0x0 }, + { 0x101d1, 0x0 }, + { 0x1101d1, 0x0 }, + { 0x2101d1, 0x0 }, + { 0x110d1, 0x0 }, + { 0x1110d1, 0x0 }, + { 0x2110d1, 0x0 }, + { 0x111d1, 0x0 }, + { 0x1111d1, 0x0 }, + { 0x2111d1, 0x0 }, + { 0x120d1, 0x0 }, + { 0x1120d1, 0x0 }, + { 0x2120d1, 0x0 }, + { 0x121d1, 0x0 }, + { 0x1121d1, 0x0 }, + { 0x2121d1, 0x0 }, + { 0x130d1, 0x0 }, + { 0x1130d1, 0x0 }, + { 0x2130d1, 0x0 }, + { 0x131d1, 0x0 }, + { 0x1131d1, 0x0 }, + { 0x2131d1, 0x0 }, + { 0x10068, 0x0 }, + { 0x10168, 0x0 }, + { 0x10268, 0x0 }, + { 0x10368, 0x0 }, + { 0x10468, 0x0 }, + { 0x10568, 0x0 }, + { 0x10668, 0x0 }, + { 0x10768, 0x0 }, + { 0x10868, 0x0 }, + { 0x11068, 0x0 }, + { 0x11168, 0x0 }, + { 0x11268, 0x0 }, + { 0x11368, 0x0 }, + { 0x11468, 0x0 }, + { 0x11568, 0x0 }, + { 0x11668, 0x0 }, + { 0x11768, 0x0 }, + { 0x11868, 0x0 }, + { 0x12068, 0x0 }, + { 0x12168, 0x0 }, + { 0x12268, 0x0 }, + { 0x12368, 0x0 }, + { 0x12468, 0x0 }, + { 0x12568, 0x0 }, + { 0x12668, 0x0 }, + { 0x12768, 0x0 }, + { 0x12868, 0x0 }, + { 0x13068, 0x0 }, + { 0x13168, 0x0 }, + { 0x13268, 0x0 }, + { 0x13368, 0x0 }, + { 0x13468, 0x0 }, + { 0x13568, 0x0 }, + { 0x13668, 0x0 }, + { 0x13768, 0x0 }, + { 0x13868, 0x0 }, + { 0x10069, 0x0 }, + { 0x10169, 0x0 }, + { 0x10269, 0x0 }, + { 0x10369, 0x0 }, + { 0x10469, 0x0 }, + { 0x10569, 0x0 }, + { 0x10669, 0x0 }, + { 0x10769, 0x0 }, + { 0x10869, 0x0 }, + { 0x11069, 0x0 }, + { 0x11169, 0x0 }, + { 0x11269, 0x0 }, + { 0x11369, 0x0 }, + { 0x11469, 0x0 }, + { 0x11569, 0x0 }, + { 0x11669, 0x0 }, + { 0x11769, 0x0 }, + { 0x11869, 0x0 }, + { 0x12069, 0x0 }, + { 0x12169, 0x0 }, + { 0x12269, 0x0 }, + { 0x12369, 0x0 }, + { 0x12469, 0x0 }, + { 0x12569, 0x0 }, + { 0x12669, 0x0 }, + { 0x12769, 0x0 }, + { 0x12869, 0x0 }, + { 0x13069, 0x0 }, + { 0x13169, 0x0 }, + { 0x13269, 0x0 }, + { 0x13369, 0x0 }, + { 0x13469, 0x0 }, + { 0x13569, 0x0 }, + { 0x13669, 0x0 }, + { 0x13769, 0x0 }, + { 0x13869, 0x0 }, + { 0x1008c, 0x0 }, + { 0x11008c, 0x0 }, + { 0x21008c, 0x0 }, + { 0x1018c, 0x0 }, + { 0x11018c, 0x0 }, + { 0x21018c, 0x0 }, + { 0x1108c, 0x0 }, + { 0x11108c, 0x0 }, + { 0x21108c, 0x0 }, + { 0x1118c, 0x0 }, + { 0x11118c, 0x0 }, + { 0x21118c, 0x0 }, + { 0x1208c, 0x0 }, + { 0x11208c, 0x0 }, + { 0x21208c, 0x0 }, + { 0x1218c, 0x0 }, + { 0x11218c, 0x0 }, + { 0x21218c, 0x0 }, + { 0x1308c, 0x0 }, + { 0x11308c, 0x0 }, + { 0x21308c, 0x0 }, + { 0x1318c, 0x0 }, + { 0x11318c, 0x0 }, + { 0x21318c, 0x0 }, + { 0x1008d, 0x0 }, + { 0x11008d, 0x0 }, + { 0x21008d, 0x0 }, + { 0x1018d, 0x0 }, + { 0x11018d, 0x0 }, + { 0x21018d, 0x0 }, + { 0x1108d, 0x0 }, + { 0x11108d, 0x0 }, + { 0x21108d, 0x0 }, + { 0x1118d, 0x0 }, + { 0x11118d, 0x0 }, + { 0x21118d, 0x0 }, + { 0x1208d, 0x0 }, + { 0x11208d, 0x0 }, + { 0x21208d, 0x0 }, + { 0x1218d, 0x0 }, + { 0x11218d, 0x0 }, + { 0x21218d, 0x0 }, + { 0x1308d, 0x0 }, + { 0x11308d, 0x0 }, + { 0x21308d, 0x0 }, + { 0x1318d, 0x0 }, + { 0x11318d, 0x0 }, + { 0x21318d, 0x0 }, + { 0x100c0, 0x0 }, + { 0x1100c0, 0x0 }, + { 0x2100c0, 0x0 }, + { 0x101c0, 0x0 }, + { 0x1101c0, 0x0 }, + { 0x2101c0, 0x0 }, + { 0x102c0, 0x0 }, + { 0x1102c0, 0x0 }, + { 0x2102c0, 0x0 }, + { 0x103c0, 0x0 }, + { 0x1103c0, 0x0 }, + { 0x2103c0, 0x0 }, + { 0x104c0, 0x0 }, + { 0x1104c0, 0x0 }, + { 0x2104c0, 0x0 }, + { 0x105c0, 0x0 }, + { 0x1105c0, 0x0 }, + { 0x2105c0, 0x0 }, + { 0x106c0, 0x0 }, + { 0x1106c0, 0x0 }, + { 0x2106c0, 0x0 }, + { 0x107c0, 0x0 }, + { 0x1107c0, 0x0 }, + { 0x2107c0, 0x0 }, + { 0x108c0, 0x0 }, + { 0x1108c0, 0x0 }, + { 0x2108c0, 0x0 }, + { 0x110c0, 0x0 }, + { 0x1110c0, 0x0 }, + { 0x2110c0, 0x0 }, + { 0x111c0, 0x0 }, + { 0x1111c0, 0x0 }, + { 0x2111c0, 0x0 }, + { 0x112c0, 0x0 }, + { 0x1112c0, 0x0 }, + { 0x2112c0, 0x0 }, + { 0x113c0, 0x0 }, + { 0x1113c0, 0x0 }, + { 0x2113c0, 0x0 }, + { 0x114c0, 0x0 }, + { 0x1114c0, 0x0 }, + { 0x2114c0, 0x0 }, + { 0x115c0, 0x0 }, + { 0x1115c0, 0x0 }, + { 0x2115c0, 0x0 }, + { 0x116c0, 0x0 }, + { 0x1116c0, 0x0 }, + { 0x2116c0, 0x0 }, + { 0x117c0, 0x0 }, + { 0x1117c0, 0x0 }, + { 0x2117c0, 0x0 }, + { 0x118c0, 0x0 }, + { 0x1118c0, 0x0 }, + { 0x2118c0, 0x0 }, + { 0x120c0, 0x0 }, + { 0x1120c0, 0x0 }, + { 0x2120c0, 0x0 }, + { 0x121c0, 0x0 }, + { 0x1121c0, 0x0 }, + { 0x2121c0, 0x0 }, + { 0x122c0, 0x0 }, + { 0x1122c0, 0x0 }, + { 0x2122c0, 0x0 }, + { 0x123c0, 0x0 }, + { 0x1123c0, 0x0 }, + { 0x2123c0, 0x0 }, + { 0x124c0, 0x0 }, + { 0x1124c0, 0x0 }, + { 0x2124c0, 0x0 }, + { 0x125c0, 0x0 }, + { 0x1125c0, 0x0 }, + { 0x2125c0, 0x0 }, + { 0x126c0, 0x0 }, + { 0x1126c0, 0x0 }, + { 0x2126c0, 0x0 }, + { 0x127c0, 0x0 }, + { 0x1127c0, 0x0 }, + { 0x2127c0, 0x0 }, + { 0x128c0, 0x0 }, + { 0x1128c0, 0x0 }, + { 0x2128c0, 0x0 }, + { 0x130c0, 0x0 }, + { 0x1130c0, 0x0 }, + { 0x2130c0, 0x0 }, + { 0x131c0, 0x0 }, + { 0x1131c0, 0x0 }, + { 0x2131c0, 0x0 }, + { 0x132c0, 0x0 }, + { 0x1132c0, 0x0 }, + { 0x2132c0, 0x0 }, + { 0x133c0, 0x0 }, + { 0x1133c0, 0x0 }, + { 0x2133c0, 0x0 }, + { 0x134c0, 0x0 }, + { 0x1134c0, 0x0 }, + { 0x2134c0, 0x0 }, + { 0x135c0, 0x0 }, + { 0x1135c0, 0x0 }, + { 0x2135c0, 0x0 }, + { 0x136c0, 0x0 }, + { 0x1136c0, 0x0 }, + { 0x2136c0, 0x0 }, + { 0x137c0, 0x0 }, + { 0x1137c0, 0x0 }, + { 0x2137c0, 0x0 }, + { 0x138c0, 0x0 }, + { 0x1138c0, 0x0 }, + { 0x2138c0, 0x0 }, + { 0x100c1, 0x0 }, + { 0x1100c1, 0x0 }, + { 0x2100c1, 0x0 }, + { 0x101c1, 0x0 }, + { 0x1101c1, 0x0 }, + { 0x2101c1, 0x0 }, + { 0x102c1, 0x0 }, + { 0x1102c1, 0x0 }, + { 0x2102c1, 0x0 }, + { 0x103c1, 0x0 }, + { 0x1103c1, 0x0 }, + { 0x2103c1, 0x0 }, + { 0x104c1, 0x0 }, + { 0x1104c1, 0x0 }, + { 0x2104c1, 0x0 }, + { 0x105c1, 0x0 }, + { 0x1105c1, 0x0 }, + { 0x2105c1, 0x0 }, + { 0x106c1, 0x0 }, + { 0x1106c1, 0x0 }, + { 0x2106c1, 0x0 }, + { 0x107c1, 0x0 }, + { 0x1107c1, 0x0 }, + { 0x2107c1, 0x0 }, + { 0x108c1, 0x0 }, + { 0x1108c1, 0x0 }, + { 0x2108c1, 0x0 }, + { 0x110c1, 0x0 }, + { 0x1110c1, 0x0 }, + { 0x2110c1, 0x0 }, + { 0x111c1, 0x0 }, + { 0x1111c1, 0x0 }, + { 0x2111c1, 0x0 }, + { 0x112c1, 0x0 }, + { 0x1112c1, 0x0 }, + { 0x2112c1, 0x0 }, + { 0x113c1, 0x0 }, + { 0x1113c1, 0x0 }, + { 0x2113c1, 0x0 }, + { 0x114c1, 0x0 }, + { 0x1114c1, 0x0 }, + { 0x2114c1, 0x0 }, + { 0x115c1, 0x0 }, + { 0x1115c1, 0x0 }, + { 0x2115c1, 0x0 }, + { 0x116c1, 0x0 }, + { 0x1116c1, 0x0 }, + { 0x2116c1, 0x0 }, + { 0x117c1, 0x0 }, + { 0x1117c1, 0x0 }, + { 0x2117c1, 0x0 }, + { 0x118c1, 0x0 }, + { 0x1118c1, 0x0 }, + { 0x2118c1, 0x0 }, + { 0x120c1, 0x0 }, + { 0x1120c1, 0x0 }, + { 0x2120c1, 0x0 }, + { 0x121c1, 0x0 }, + { 0x1121c1, 0x0 }, + { 0x2121c1, 0x0 }, + { 0x122c1, 0x0 }, + { 0x1122c1, 0x0 }, + { 0x2122c1, 0x0 }, + { 0x123c1, 0x0 }, + { 0x1123c1, 0x0 }, + { 0x2123c1, 0x0 }, + { 0x124c1, 0x0 }, + { 0x1124c1, 0x0 }, + { 0x2124c1, 0x0 }, + { 0x125c1, 0x0 }, + { 0x1125c1, 0x0 }, + { 0x2125c1, 0x0 }, + { 0x126c1, 0x0 }, + { 0x1126c1, 0x0 }, + { 0x2126c1, 0x0 }, + { 0x127c1, 0x0 }, + { 0x1127c1, 0x0 }, + { 0x2127c1, 0x0 }, + { 0x128c1, 0x0 }, + { 0x1128c1, 0x0 }, + { 0x2128c1, 0x0 }, + { 0x130c1, 0x0 }, + { 0x1130c1, 0x0 }, + { 0x2130c1, 0x0 }, + { 0x131c1, 0x0 }, + { 0x1131c1, 0x0 }, + { 0x2131c1, 0x0 }, + { 0x132c1, 0x0 }, + { 0x1132c1, 0x0 }, + { 0x2132c1, 0x0 }, + { 0x133c1, 0x0 }, + { 0x1133c1, 0x0 }, + { 0x2133c1, 0x0 }, + { 0x134c1, 0x0 }, + { 0x1134c1, 0x0 }, + { 0x2134c1, 0x0 }, + { 0x135c1, 0x0 }, + { 0x1135c1, 0x0 }, + { 0x2135c1, 0x0 }, + { 0x136c1, 0x0 }, + { 0x1136c1, 0x0 }, + { 0x2136c1, 0x0 }, + { 0x137c1, 0x0 }, + { 0x1137c1, 0x0 }, + { 0x2137c1, 0x0 }, + { 0x138c1, 0x0 }, + { 0x1138c1, 0x0 }, + { 0x2138c1, 0x0 }, + { 0x10020, 0x0 }, + { 0x110020, 0x0 }, + { 0x210020, 0x0 }, + { 0x11020, 0x0 }, + { 0x111020, 0x0 }, + { 0x211020, 0x0 }, + { 0x12020, 0x0 }, + { 0x112020, 0x0 }, + { 0x212020, 0x0 }, + { 0x13020, 0x0 }, + { 0x113020, 0x0 }, + { 0x213020, 0x0 }, + { 0x20072, 0x0 }, + { 0x20073, 0x0 }, + { 0x20074, 0x0 }, + { 0x100aa, 0x0 }, + { 0x110aa, 0x0 }, + { 0x120aa, 0x0 }, + { 0x130aa, 0x0 }, + { 0x20010, 0x0 }, + { 0x120010, 0x0 }, + { 0x220010, 0x0 }, + { 0x20011, 0x0 }, + { 0x120011, 0x0 }, + { 0x220011, 0x0 }, + { 0x100ae, 0x0 }, + { 0x1100ae, 0x0 }, + { 0x2100ae, 0x0 }, + { 0x100af, 0x0 }, + { 0x1100af, 0x0 }, + { 0x2100af, 0x0 }, + { 0x110ae, 0x0 }, + { 0x1110ae, 0x0 }, + { 0x2110ae, 0x0 }, + { 0x110af, 0x0 }, + { 0x1110af, 0x0 }, + { 0x2110af, 0x0 }, + { 0x120ae, 0x0 }, + { 0x1120ae, 0x0 }, + { 0x2120ae, 0x0 }, + { 0x120af, 0x0 }, + { 0x1120af, 0x0 }, + { 0x2120af, 0x0 }, + { 0x130ae, 0x0 }, + { 0x1130ae, 0x0 }, + { 0x2130ae, 0x0 }, + { 0x130af, 0x0 }, + { 0x1130af, 0x0 }, + { 0x2130af, 0x0 }, + { 0x20020, 0x0 }, + { 0x120020, 0x0 }, + { 0x220020, 0x0 }, + { 0x100a0, 0x0 }, + { 0x100a1, 0x0 }, + { 0x100a2, 0x0 }, + { 0x100a3, 0x0 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x0 }, + { 0x100a6, 0x0 }, + { 0x100a7, 0x0 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x0 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x0 }, + { 0x110a4, 0x0 }, + { 0x110a5, 0x0 }, + { 0x110a6, 0x0 }, + { 0x110a7, 0x0 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x0 }, + { 0x120a2, 0x0 }, + { 0x120a3, 0x0 }, + { 0x120a4, 0x0 }, + { 0x120a5, 0x0 }, + { 0x120a6, 0x0 }, + { 0x120a7, 0x0 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x0 }, + { 0x130a2, 0x0 }, + { 0x130a3, 0x0 }, + { 0x130a4, 0x0 }, + { 0x130a5, 0x0 }, + { 0x130a6, 0x0 }, + { 0x130a7, 0x0 }, + { 0x2007c, 0x0 }, + { 0x12007c, 0x0 }, + { 0x22007c, 0x0 }, + { 0x2007d, 0x0 }, + { 0x12007d, 0x0 }, + { 0x22007d, 0x0 }, + { 0x400fd, 0x0 }, + { 0x400c0, 0x0 }, + { 0x90201, 0x0 }, + { 0x190201, 0x0 }, + { 0x290201, 0x0 }, + { 0x90202, 0x0 }, + { 0x190202, 0x0 }, + { 0x290202, 0x0 }, + { 0x90203, 0x0 }, + { 0x190203, 0x0 }, + { 0x290203, 0x0 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x90205, 0x0 }, + { 0x190205, 0x0 }, + { 0x290205, 0x0 }, + { 0x90206, 0x0 }, + { 0x190206, 0x0 }, + { 0x290206, 0x0 }, + { 0x90207, 0x0 }, + { 0x190207, 0x0 }, + { 0x290207, 0x0 }, + { 0x90208, 0x0 }, + { 0x190208, 0x0 }, + { 0x290208, 0x0 }, + { 0x10062, 0x0 }, + { 0x10162, 0x0 }, + { 0x10262, 0x0 }, + { 0x10362, 0x0 }, + { 0x10462, 0x0 }, + { 0x10562, 0x0 }, + { 0x10662, 0x0 }, + { 0x10762, 0x0 }, + { 0x10862, 0x0 }, + { 0x11062, 0x0 }, + { 0x11162, 0x0 }, + { 0x11262, 0x0 }, + { 0x11362, 0x0 }, + { 0x11462, 0x0 }, + { 0x11562, 0x0 }, + { 0x11662, 0x0 }, + { 0x11762, 0x0 }, + { 0x11862, 0x0 }, + { 0x12062, 0x0 }, + { 0x12162, 0x0 }, + { 0x12262, 0x0 }, + { 0x12362, 0x0 }, + { 0x12462, 0x0 }, + { 0x12562, 0x0 }, + { 0x12662, 0x0 }, + { 0x12762, 0x0 }, + { 0x12862, 0x0 }, + { 0x13062, 0x0 }, + { 0x13162, 0x0 }, + { 0x13262, 0x0 }, + { 0x13362, 0x0 }, + { 0x13462, 0x0 }, + { 0x13562, 0x0 }, + { 0x13662, 0x0 }, + { 0x13762, 0x0 }, + { 0x13862, 0x0 }, + { 0x20077, 0x0 }, + { 0x10001, 0x0 }, + { 0x11001, 0x0 }, + { 0x12001, 0x0 }, + { 0x13001, 0x0 }, + { 0x10040, 0x0 }, + { 0x10140, 0x0 }, + { 0x10240, 0x0 }, + { 0x10340, 0x0 }, + { 0x10440, 0x0 }, + { 0x10540, 0x0 }, + { 0x10640, 0x0 }, + { 0x10740, 0x0 }, + { 0x10840, 0x0 }, + { 0x10030, 0x0 }, + { 0x10130, 0x0 }, + { 0x10230, 0x0 }, + { 0x10330, 0x0 }, + { 0x10430, 0x0 }, + { 0x10530, 0x0 }, + { 0x10630, 0x0 }, + { 0x10730, 0x0 }, + { 0x10830, 0x0 }, + { 0x11040, 0x0 }, + { 0x11140, 0x0 }, + { 0x11240, 0x0 }, + { 0x11340, 0x0 }, + { 0x11440, 0x0 }, + { 0x11540, 0x0 }, + { 0x11640, 0x0 }, + { 0x11740, 0x0 }, + { 0x11840, 0x0 }, + { 0x11030, 0x0 }, + { 0x11130, 0x0 }, + { 0x11230, 0x0 }, + { 0x11330, 0x0 }, + { 0x11430, 0x0 }, + { 0x11530, 0x0 }, + { 0x11630, 0x0 }, + { 0x11730, 0x0 }, + { 0x11830, 0x0 }, + { 0x12040, 0x0 }, + { 0x12140, 0x0 }, + { 0x12240, 0x0 }, + { 0x12340, 0x0 }, + { 0x12440, 0x0 }, + { 0x12540, 0x0 }, + { 0x12640, 0x0 }, + { 0x12740, 0x0 }, + { 0x12840, 0x0 }, + { 0x12030, 0x0 }, + { 0x12130, 0x0 }, + { 0x12230, 0x0 }, + { 0x12330, 0x0 }, + { 0x12430, 0x0 }, + { 0x12530, 0x0 }, + { 0x12630, 0x0 }, + { 0x12730, 0x0 }, + { 0x12830, 0x0 }, + { 0x13040, 0x0 }, + { 0x13140, 0x0 }, + { 0x13240, 0x0 }, + { 0x13340, 0x0 }, + { 0x13440, 0x0 }, + { 0x13540, 0x0 }, + { 0x13640, 0x0 }, + { 0x13740, 0x0 }, + { 0x13840, 0x0 }, + { 0x13030, 0x0 }, + { 0x13130, 0x0 }, + { 0x13230, 0x0 }, + { 0x13330, 0x0 }, + { 0x13430, 0x0 }, + { 0x13530, 0x0 }, + { 0x13630, 0x0 }, + { 0x13730, 0x0 }, + { 0x13830, 0x0 }, +}; +/* P0 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x80 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x236 }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400b, 0x31f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x1 }, + { 0x54031, 0x18 }, + { 0x54032, 0x240 }, + { 0x54033, 0x200 }, + { 0x54034, 0x640 }, + { 0x54035, 0x816 }, + { 0x54036, 0x103 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P1 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x80 }, + { 0x54002, 0x1 }, + { 0x54003, 0x640 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x236 }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x5402f, 0x210 }, + { 0x54030, 0x1 }, + { 0x54032, 0x40 }, + { 0x54033, 0x200 }, + { 0x54034, 0x640 }, + { 0x54035, 0x416 }, + { 0x54036, 0x103 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P2 message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x80 }, + { 0x54002, 0x2 }, + { 0x54003, 0x428 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x236 }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400b, 0x21f }, + { 0x5400c, 0xc8 }, + { 0x54012, 0x1 }, + { 0x54030, 0x1 }, + { 0x54032, 0x40 }, + { 0x54033, 0x200 }, + { 0x54034, 0x640 }, + { 0x54035, 0x16 }, + { 0x54036, 0x103 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + + +/* P0 2D message block paremeter for training firmware */ +struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0 }, + { 0x54000, 0x80 }, + { 0x54003, 0x960 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x236 }, + { 0x54007, 0x2000 }, + { 0x54008, 0x303 }, + { 0x54009, 0x200 }, + { 0x5400b, 0x61 }, + { 0x5400c, 0x1c8 }, + { 0x5400d, 0x101 }, + { 0x5400e, 0x1f7f }, + { 0x54012, 0x1 }, + { 0x5402f, 0x834 }, + { 0x54030, 0x1 }, + { 0x54031, 0x18 }, + { 0x54032, 0x240 }, + { 0x54033, 0x200 }, + { 0x54034, 0x640 }, + { 0x54035, 0x816 }, + { 0x54036, 0x103 }, + { 0x5403f, 0x1323 }, + { 0x541fc, 0x100 }, + { 0xd0000, 0x1 }, +}; + +/* DRAM PHY init engine image */ +struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x400 }, + { 0x90002, 0x10e }, + { 0x90003, 0x0 }, + { 0x90004, 0x0 }, + { 0x90005, 0x8 }, + { 0x90029, 0xb }, + { 0x9002a, 0x480 }, + { 0x9002b, 0x109 }, + { 0x9002c, 0x8 }, + { 0x9002d, 0x448 }, + { 0x9002e, 0x139 }, + { 0x9002f, 0x8 }, + { 0x90030, 0x478 }, + { 0x90031, 0x109 }, + { 0x90032, 0x2 }, + { 0x90033, 0x10 }, + { 0x90034, 0x139 }, + { 0x90035, 0xf }, + { 0x90036, 0x7c0 }, + { 0x90037, 0x139 }, + { 0x90038, 0x44 }, + { 0x90039, 0x630 }, + { 0x9003a, 0x159 }, + { 0x9003b, 0x14f }, + { 0x9003c, 0x630 }, + { 0x9003d, 0x159 }, + { 0x9003e, 0x47 }, + { 0x9003f, 0x630 }, + { 0x90040, 0x149 }, + { 0x90041, 0x4f }, + { 0x90042, 0x630 }, + { 0x90043, 0x179 }, + { 0x90044, 0x8 }, + { 0x90045, 0xe0 }, + { 0x90046, 0x109 }, + { 0x90047, 0x0 }, + { 0x90048, 0x7c8 }, + { 0x90049, 0x109 }, + { 0x9004a, 0x0 }, + { 0x9004b, 0x1 }, + { 0x9004c, 0x8 }, + { 0x9004d, 0x0 }, + { 0x9004e, 0x45a }, + { 0x9004f, 0x9 }, + { 0x90050, 0x0 }, + { 0x90051, 0x448 }, + { 0x90052, 0x109 }, + { 0x90053, 0x40 }, + { 0x90054, 0x630 }, + { 0x90055, 0x179 }, + { 0x90056, 0x1 }, + { 0x90057, 0x618 }, + { 0x90058, 0x109 }, + { 0x90059, 0x40c0 }, + { 0x9005a, 0x630 }, + { 0x9005b, 0x149 }, + { 0x9005c, 0x8 }, + { 0x9005d, 0x4 }, + { 0x9005e, 0x48 }, + { 0x9005f, 0x4040 }, + { 0x90060, 0x630 }, + { 0x90061, 0x149 }, + { 0x90062, 0x0 }, + { 0x90063, 0x4 }, + { 0x90064, 0x48 }, + { 0x90065, 0x40 }, + { 0x90066, 0x630 }, + { 0x90067, 0x149 }, + { 0x90068, 0x10 }, + { 0x90069, 0x4 }, + { 0x9006a, 0x18 }, + { 0x9006b, 0x0 }, + { 0x9006c, 0x4 }, + { 0x9006d, 0x78 }, + { 0x9006e, 0x549 }, + { 0x9006f, 0x630 }, + { 0x90070, 0x159 }, + { 0x90071, 0xd49 }, + { 0x90072, 0x630 }, + { 0x90073, 0x159 }, + { 0x90074, 0x94a }, + { 0x90075, 0x630 }, + { 0x90076, 0x159 }, + { 0x90077, 0x441 }, + { 0x90078, 0x630 }, + { 0x90079, 0x149 }, + { 0x9007a, 0x42 }, + { 0x9007b, 0x630 }, + { 0x9007c, 0x149 }, + { 0x9007d, 0x1 }, + { 0x9007e, 0x630 }, + { 0x9007f, 0x149 }, + { 0x90080, 0x0 }, + { 0x90081, 0xe0 }, + { 0x90082, 0x109 }, + { 0x90083, 0xa }, + { 0x90084, 0x10 }, + { 0x90085, 0x109 }, + { 0x90086, 0x9 }, + { 0x90087, 0x3c0 }, + { 0x90088, 0x149 }, + { 0x90089, 0x9 }, + { 0x9008a, 0x3c0 }, + { 0x9008b, 0x159 }, + { 0x9008c, 0x18 }, + { 0x9008d, 0x10 }, + { 0x9008e, 0x109 }, + { 0x9008f, 0x0 }, + { 0x90090, 0x3c0 }, + { 0x90091, 0x109 }, + { 0x90092, 0x18 }, + { 0x90093, 0x4 }, + { 0x90094, 0x48 }, + { 0x90095, 0x18 }, + { 0x90096, 0x4 }, + { 0x90097, 0x58 }, + { 0x90098, 0xa }, + { 0x90099, 0x10 }, + { 0x9009a, 0x109 }, + { 0x9009b, 0x2 }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x109 }, + { 0x9009e, 0x7 }, + { 0x9009f, 0x7c0 }, + { 0x900a0, 0x109 }, + { 0x900a1, 0x10 }, + { 0x900a2, 0x10 }, + { 0x900a3, 0x109 }, + { 0x900a4, 0x0 }, + { 0x900a5, 0x8140 }, + { 0x900a6, 0x10c }, + { 0x900a7, 0x10 }, + { 0x900a8, 0x8138 }, + { 0x900a9, 0x10c }, + { 0x900aa, 0x8 }, + { 0x900ab, 0x7c8 }, + { 0x900ac, 0x101 }, + { 0x900ad, 0x8 }, + { 0x900ae, 0x0 }, + { 0x900af, 0x8 }, + { 0x900b0, 0x8 }, + { 0x900b1, 0x448 }, + { 0x900b2, 0x109 }, + { 0x900b3, 0xf }, + { 0x900b4, 0x7c0 }, + { 0x900b5, 0x109 }, + { 0x900b6, 0x47 }, + { 0x900b7, 0x630 }, + { 0x900b8, 0x109 }, + { 0x900b9, 0x8 }, + { 0x900ba, 0x618 }, + { 0x900bb, 0x109 }, + { 0x900bc, 0x8 }, + { 0x900bd, 0xe0 }, + { 0x900be, 0x109 }, + { 0x900bf, 0x0 }, + { 0x900c0, 0x7c8 }, + { 0x900c1, 0x109 }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x8140 }, + { 0x900c4, 0x10c }, + { 0x900c5, 0x0 }, + { 0x900c6, 0x1 }, + { 0x900c7, 0x8 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x4 }, + { 0x900ca, 0x8 }, + { 0x900cb, 0x8 }, + { 0x900cc, 0x7c8 }, + { 0x900cd, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x90026, 0x2c }, + { 0x2000b, 0x4b }, + { 0x2000c, 0x96 }, + { 0x2000d, 0x5dc }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x32 }, + { 0x12000c, 0x64 }, + { 0x12000d, 0x3e8 }, + { 0x12000e, 0x2c }, + { 0x22000b, 0x21 }, + { 0x22000c, 0x42 }, + { 0x22000d, 0x299 }, + { 0x22000e, 0x21 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0xffff }, + { 0x90013, 0x6152 }, + { 0xc0080, 0x0 }, + { 0xd0000, 0x1 } +}; + +struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1600mts 1D */ + .drate = 1600, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 1064mts 1D */ + .drate = 1064, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1600, 1064, }, +}; + diff --git a/board/freescale/imx8mq_val/imx8mq_val.c b/board/freescale/imx8mq_val/imx8mq_val.c new file mode 100644 index 00000000000..afda2f926ca --- /dev/null +++ b/board/freescale/imx8mq_val/imx8mq_val.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define NAND_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_HYS) +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL2 | PAD_CTL_PUE) + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_QSPI +int board_qspi_init(void) +{ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_MXS +#ifdef CONFIG_SPL_BUILD +static iomux_v3_cfg_t const gpmi_pads[] = { + IMX8MQ_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), + IMX8MQ_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + IMX8MQ_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; +#endif + +static void setup_gpmi_nand(void) +{ +#ifdef CONFIG_SPL_BUILD + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); +#endif + + init_nand_clk(); +} +#endif + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); /* SPL will call the board_early_init_f */ +#endif + + return 0; +} + +#ifdef CONFIG_FEC_MXC +static int setup_fec(void) +{ +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + /* + * GPR1 bit 13: + * 1:enet1 rmii clock comes from ccm->pad->loopback, SION bit for the pad (iomuxc_sw_input_on_pad_enet_td2) should be set also; + * 0:enet1 rmii clock comes from external phy or osc + */ + + setbits_le32(&gpr->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); + return set_clk_enet(ENET_50MHZ); +#else + return set_clk_enet(ENET_125MHZ); +#endif +} + + +int board_phy_config(struct phy_device *phydev) +{ +#ifndef CONFIG_TARGET_IMX8MQ_DDR3L_VAL + + /* enable rgmii rxc skew and phy mode select to RGMII copper */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#ifdef CONFIG_USB_DWC3 + +#define USB_PHY_CTRL0 0xF0040 +#define USB_PHY_CTRL0_REF_SSP_EN BIT(2) + +#define USB_PHY_CTRL1 0xF0044 +#define USB_PHY_CTRL1_RESET BIT(0) +#define USB_PHY_CTRL1_COMMONONN BIT(1) +#define USB_PHY_CTRL1_ATERESET BIT(3) +#define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) +#define USB_PHY_CTRL1_VDATDETENB0 BIT(20) + +#define USB_PHY_CTRL2 0xF0048 +#define USB_PHY_CTRL2_TXENABLEN0 BIT(8) + +static struct dwc3_device dwc3_device_data = { +#ifdef CONFIG_SPL_BUILD + .maximum_speed = USB_SPEED_HIGH, +#else + .maximum_speed = USB_SPEED_SUPER, +#endif + .base = USB1_BASE_ADDR, + .dr_mode = USB_DR_MODE_PERIPHERAL, + .index = 0, + .power_down_scale = 2, +}; + +int usb_gadget_handle_interrupts(int index) +{ + dwc3_uboot_handle_interrupt(index); + return 0; +} + +static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) +{ + u32 RegData; + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | + USB_PHY_CTRL1_COMMONONN); + RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; + writel(RegData, dwc3->base + USB_PHY_CTRL1); + + RegData = readl(dwc3->base + USB_PHY_CTRL0); + RegData |= USB_PHY_CTRL0_REF_SSP_EN; + writel(RegData, dwc3->base + USB_PHY_CTRL0); + + RegData = readl(dwc3->base + USB_PHY_CTRL2); + RegData |= USB_PHY_CTRL2_TXENABLEN0; + writel(RegData, dwc3->base + USB_PHY_CTRL2); + + RegData = readl(dwc3->base + USB_PHY_CTRL1); + RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); + writel(RegData, dwc3->base + USB_PHY_CTRL1); +} + +int board_usb_init(int index, enum usb_init_type init) +{ + if (index == 0 && init == USB_INIT_DEVICE) { + imx8m_usb_power(index, true); + dwc3_nxp_usb_phy_init(&dwc3_device_data); + return dwc3_uboot_init(&dwc3_device_data); + } + + return 0; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + if (index == 0 && init == USB_INIT_DEVICE) { + dwc3_uboot_exit(index); + imx8m_usb_power(index, false); + } + return 0; +} +#endif + +int board_init(void) +{ +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) + init_usb_clk(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL + env_set("board_name", "DDR3L-VAL"); +#else + env_set("board_name", "DDR4-VAL"); +#endif + env_set("board_rev", "iMX8MQ"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} diff --git a/board/freescale/imx8mq_val/spl.c b/board/freescale/imx8mq_val/spl.c new file mode 100644 index 00000000000..f44487ed82b --- /dev/null +++ b/board/freescale/imx8mq_val/spl.c @@ -0,0 +1,273 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include + +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL +#include "ddr/ddr.h" +#else +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +void spl_dram_init(void) +{ + /* ddr init */ +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL + ddr_init(NULL); +#else + ddr_init(&dram_timing); +#endif +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL + ret = !gpio_get_value(USDHC2_CD_GPIO); +#else + ret = gpio_get_value(USDHC2_CD_GPIO); +#endif + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_GPIO1_IO04__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); + gpio_direction_output(USDHC2_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return -ENODEV; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return -ENODEV; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, ®); + if ((reg & 0x3f) != 0x1c) { + reg &= ~0x3f; + reg |= 0x1c; + pmic_reg_write(p, PFUZE100_SW1ABVOL, reg); + } + + pmic_reg_read(p, PFUZE100_SW1CVOL, ®); + if ((reg & 0x3f) != 0x1c) { + reg &= ~0x3f; + reg |= 0x1c; + pmic_reg_write(p, PFUZE100_SW1CVOL, reg); + } + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} +#endif + +void spl_board_init(void) +{ +#ifndef CONFIG_SPL_USB_SDP_SUPPORT + /* Serial download mode */ + if (is_usb_boot()) { + puts("Back to ROM, SDP\n"); + restore_boot_params(); + } +#endif + + init_usb_clk(); + + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + init_uart_clk(0); /* Init UART0 clock */ + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + /* Adjust pmic voltage VDD_DRAM to 1.0V for DRAM RUN >= 2400MHZ */ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8qm_mek/Kconfig b/board/freescale/imx8qm_mek/Kconfig index 93d7d5f9c57..cd994cae382 100644 --- a/board/freescale/imx8qm_mek/Kconfig +++ b/board/freescale/imx8qm_mek/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8QM_MEK +if TARGET_IMX8QM_MEK || TARGET_IMX8QM_MEK_A53_ONLY || TARGET_IMX8QM_MEK_A72_ONLY config SYS_BOARD default "imx8qm_mek" diff --git a/board/freescale/imx8qm_mek/imx8qm_mek.c b/board/freescale/imx8qm_mek/imx8qm_mek.c index c6772206244..13bdecf42da 100644 --- a/board/freescale/imx8qm_mek/imx8qm_mek.c +++ b/board/freescale/imx8qm_mek/imx8qm_mek.c @@ -16,24 +16,48 @@ #include #include #include +#include +#include #include #include +#include "../common/tcpc.h" +#include "command.h" DECLARE_GLOBAL_DATA_PTR; -#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ - (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ - (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ - (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY +static iomux_cfg_t uart2_pads[] = { + SC_P_UART0_RTS_B | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_CTS_B | MUX_MODE_ALT(2) | MUX_PAD_CTRL(UART_PAD_CTRL), +}; +#else static iomux_cfg_t uart0_pads[] = { SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#endif static void setup_iomux_uart(void) { +#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY + imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +#else imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +#endif } int board_early_init_f(void) @@ -41,32 +65,110 @@ int board_early_init_f(void) sc_pm_clock_rate_t rate = SC_80MHZ; int ret; + /* When start u-boot in XEN VM, directly return */ + if (IS_ENABLED(CONFIG_XEN)) { + writel(0xF53535F5, (void __iomem *)0x80000000); + return 0; + } + +#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY + /* Set UART2 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_2, rate); + if (ret) + return ret; +#else /* Set UART0 clock root to 80 MHz */ ret = sc_pm_setup_uart(SC_R_UART_0, rate); if (ret) return ret; +#endif /* CONFIG_TARGET_IMX8QM_MEK_A72_ONLY */ setup_iomux_uart(); - sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON); - return 0; } -#if CONFIG_IS_ENABLED(DM_GPIO) -static void board_gpio_init(void) -{ - /* TODO */ -} -#else -static inline void board_gpio_init(void) {} -#endif #if IS_ENABLED(CONFIG_FEC_MXC) #include +#ifndef CONFIG_DM_ETH +static iomux_cfg_t pad_enet1[] = { + SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + int board_phy_config(struct phy_device *phydev) { + if (phydev->drv->config) + phydev->drv->config(phydev); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); @@ -75,39 +177,259 @@ int board_phy_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; } #endif +#endif + +#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20) +#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24) +#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23) + +static void board_gpio_init(void) +{ +#if defined(CONFIG_TARGET_IMX8QM_MEK) || defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) + int ret; + struct gpio_desc desc; + + ret = dm_gpio_lookup_name("GPIO4_20", &desc); + if (ret) { + printf("%s lookup GPIO@4_20 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "bb_3v3_1"); + if (ret) { + printf("%s request bb_3v3_1 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + ret = dm_gpio_lookup_name("GPIO4_24", &desc); + if (ret) { + printf("%s lookup GPIO@4_24 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "bb_3v3_2"); + if (ret) { + printf("%s request bb_3v3_2 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + ret = dm_gpio_lookup_name("GPIO4_23", &desc); + if (ret) { + printf("%s lookup GPIO@4_23 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "bb_3v3_3"); + if (ret) { + printf("%s request bb_3v3_3 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* enable LVDS SAS boards */ + ret = dm_gpio_lookup_name("GPIO1_6", &desc); + if (ret) { + printf("%s lookup GPIO1_6 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "lvds_enable"); + if (ret) { + printf("%s request lvds_enable failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* enable MIPI SAS boards */ + ret = dm_gpio_lookup_name("GPIO1_7", &desc); + if (ret) { + printf("%s lookup GPIO1_7 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "mipi_enable"); + if (ret) { + printf("%s request mipi_enable failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +#endif + +} int checkboard(void) { puts("Board: iMX8QM MEK\n"); - build_info(); print_bootinfo(); return 0; } +#ifdef CONFIG_USB + +#ifdef CONFIG_USB_TCPC +struct gpio_desc type_sel_desc; + +static iomux_cfg_t ss_mux_gpio[] = { + SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +struct tcpc_port port; +struct tcpc_port_config port_config = { + .i2c_bus = 0, + .addr = 0x51, + .port_type = TYPEC_PORT_DFP, +}; + +void ss_mux_select(enum typec_cc_polarity pol) +{ + if (pol == TYPEC_POLARITY_CC1) + dm_gpio_set_value(&type_sel_desc, 0); + else + dm_gpio_set_value(&type_sel_desc, 1); +} + +static void setup_typec(void) +{ + int ret; + struct gpio_desc typec_en_desc; + + imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + ret = dm_gpio_lookup_name("GPIO4_6", &type_sel_desc); + if (ret) { + printf("%s lookup GPIO4_6 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&type_sel_desc, "typec_sel"); + if (ret) { + printf("%s request typec_sel failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT); + + ret = dm_gpio_lookup_name("GPIO4_19", &typec_en_desc); + if (ret) { + printf("%s lookup GPIO4_19 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&typec_en_desc, "typec_en"); + if (ret) { + printf("%s request typec_en failed ret = %d\n", __func__, ret); + return; + } + + /* Enable SS MUX */ + dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + tcpc_init(&port, port_config, &ss_mux_select); +} +#endif + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port); +#endif +#ifdef CONFIG_USB_CDNS3_GADGET + } else { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port); + printf("%d setufp mode %d\n", index, ret); +#endif +#endif + } + } + + return ret; + +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port); +#endif + } + } + + return ret; +} +#endif + int board_init(void) { - /* Power up base board */ - sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON); + if (IS_ENABLED(CONFIG_XEN)) + return 0; board_gpio_init(); + +#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC) + setup_typec(); +#endif + +#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO + { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } +#endif + return 0; } +void board_quiesce_devices(void) +{ + const char *power_on_devices[] = { +#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY + "dma_lpuart2", + "PD_UART2_TX", + "PD_UART2_RX", +#else + "dma_lpuart0", +#endif + }; + + if (IS_ENABLED(CONFIG_XEN)) { + /* Clear magic number to let xen know uboot is over */ + writel(0x0, (void __iomem *)0x80000000); + return; + } + + imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + /* * Board specific reset that is system reset. */ void reset_cpu(ulong addr) { - /* TODO */ + sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD); + while(1); } #ifdef CONFIG_OF_BOARD_SETUP @@ -119,28 +441,100 @@ int ft_board_setup(void *blob, struct bd_info *bd) int board_mmc_get_env_dev(int devno) { + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + return devno; } +int mmc_map_to_kernel_blk(int dev_no) +{ + /* Use EMMC */ + if (IS_ENABLED(CONFIG_XEN)) + return 0; + + return dev_no; +} + +extern uint32_t _end_ofs; int board_late_init(void) { char *fdt_file; +#if !defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) && !defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) bool m4_booted; +#endif + + build_info(); #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "MEK"); env_set("board_rev", "iMX8QM"); #endif + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + fdt_file = env_get("fdt_file"); - m4_booted = m4_parts_booted(); if (fdt_file && !strcmp(fdt_file, "undefined")) { +#if defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) + env_set("fdt_file", "imx8qm-mek-cockpit-ca53.dtb"); +#elif defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) + env_set("fdt_file", "imx8qm-mek-cockpit-ca72.dtb"); +#else + m4_booted = m4_parts_booted(); if (m4_booted) env_set("fdt_file", "imx8qm-mek-rpmsg.dtb"); else env_set("fdt_file", "imx8qm-mek.dtb"); +#endif } +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + +#if defined(CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX) || defined(CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX) + char *end_of_uboot; + char command[256]; + end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob)); + end_of_uboot += 9; + + /* load hdmitxfw.bin and hdmirxfw.bin*/ + memcpy((void *)IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot, + IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE); + +#ifdef CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX + sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR); + run_command(command, 0); +#endif +#ifdef CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX + sprintf(command, "hdprx load 0x%x", + IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE); + run_command(command, 0); +#endif +#endif /* CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX || CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX */ + return 0; } + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + sc_bool_t status = SC_FALSE; + + sc_misc_get_button_status(-1, &status); + return (bool)status; +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /* TODO */ +} +#endif /* CONFIG_ANDROID_RECOVERY */ +#endif /* CONFIG_FSL_FASTBOOT */ diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c index 944ba745c09..adfe51178ec 100644 --- a/board/freescale/imx8qm_mek/spl.c +++ b/board/freescale/imx8qm_mek/spl.c @@ -16,35 +16,44 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; void spl_board_init(void) { struct udevice *dev; + int node, ret; - uclass_find_first_device(UCLASS_MISC, &dev); + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu"); + + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &dev); + if (ret) { + return; + } + device_probe(dev); + uclass_find_first_device(UCLASS_MISC, &dev); for (; dev; uclass_find_next_device(&dev)) { if (device_probe(dev)) continue; } - arch_cpu_init(); - board_early_init_f(); timer_init(); +#ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); puts("Normal Boot\n"); +#endif + } void spl_board_prepare_for_boot(void) { - imx8_power_off_pd_devices(NULL, 0); + board_quiesce_devices(); } #ifdef CONFIG_SPL_LOAD_FIT @@ -59,11 +68,10 @@ int board_fit_config_name_match(const char *name) void board_init_f(ulong dummy) { - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); + arch_cpu_init(); + board_init_r(NULL, 0); } diff --git a/board/freescale/imx8qm_val/Kconfig b/board/freescale/imx8qm_val/Kconfig new file mode 100644 index 00000000000..6fc5399781e --- /dev/null +++ b/board/freescale/imx8qm_val/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8QM_LPDDR4_VAL || TARGET_IMX8QM_DDR4_VAL + +config SYS_BOARD + default "imx8qm_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qm_val" + +endif diff --git a/board/freescale/imx8qm_val/Makefile b/board/freescale/imx8qm_val/Makefile new file mode 100644 index 00000000000..706bd9a966a --- /dev/null +++ b/board/freescale/imx8qm_val/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qm_val.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8qm_val/imx8qm_val.c b/board/freescale/imx8qm_val/imx8qm_val.c new file mode 100644 index 00000000000..376d633a8d0 --- /dev/null +++ b/board/freescale/imx8qm_val/imx8qm_val.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2017-2018 NXP + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pca953x.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +#ifndef CONFIG_DM_ETH +static iomux_cfg_t pad_enet1[] = { + SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +static void enet_device_phy_reset(void) +{ + struct gpio_desc desc_enet0; + struct gpio_desc desc_enet1; + int ret; + + ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet0, "enet0_reset"); + if (ret) + return; + ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet1, "enet1_reset"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet0, 0); + udelay(50); + dm_gpio_set_value(&desc_enet0, 1); + + dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet1, 0); + udelay(50); + dm_gpio_set_value(&desc_enet1, 1); + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + /* Reset ENET PHY */ + enet_device_phy_reset(); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} +#endif + +#define MAX7322_I2C_ADDR 0x68 +#define MAX7322_I2C_BUS 2 /* I2C2 */ + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->addr == 1) { + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + uint8_t value; + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, MAX7322_I2C_ADDR); + return -ENODEV; + } + + i2c_set_chip_offset_len(i2c_dev, 0); + + value = 0x1; + + ret = dm_i2c_write(i2c_dev, 0x0, (const uint8_t *)&value, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + mdelay(1); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + +#ifndef CONFIG_DM_ETH + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif + return 0; +} + +#endif + +#define LVDS_ENABLE IMX_GPIO_NR(1, 6) +#define MIPI_ENABLE IMX_GPIO_NR(1, 7) +#define DEBUG_LED IMX_GPIO_NR(2, 15) +#define IOEXP_RESET IMX_GPIO_NR(1, 12) + + +static void board_gpio_init(void) +{ + int ret; + struct gpio_desc desc; + struct udevice *dev; + + /* enable i2c port expander assert reset line first */ + /* we can't use dm_gpio_lookup_name for GPIO1_12, because the func will probe the + * uclass list until find the device. The expander device is at begin of the list due to + * I2c nodes is prior than gpio in the DTS. So if the func goes through the uclass list, + * probe to expander will fail, and exit the dm_gpio_lookup_name func. Thus, we always + * fail to get the device + */ + ret = uclass_get_device_by_seq(UCLASS_GPIO, 1, &dev); + if (ret) { + printf("%s failed to find GPIO1 device, ret = %d\n", __func__, ret); + return; + } + + desc.dev = dev; + desc.offset = 12; + desc.flags = 0; + + ret = dm_gpio_request(&desc, "ioexp_rst"); + if (ret) { + printf("%s request ioexp_rst failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + + ret = dm_gpio_lookup_name("GPIO2_15", &desc); + if (ret) { + printf("%s lookup GPIO@2_15 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "debug_led"); + if (ret) { + printf("%s request debug_led failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + + ret = dm_gpio_lookup_name("GPIO1_6", &desc); + if (ret) { + printf("%s lookup GPIO@1_6 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "lvds_enable"); + if (ret) { + printf("%s request lvds_enable failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + ret = dm_gpio_lookup_name("GPIO1_7", &desc); + if (ret) { + printf("%s lookup GPIO@1_7 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "mipi_enable"); + if (ret) { + printf("%s request mipi_enable failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_VAL + puts("Board: iMX8QM LPDDR4 VAL\n"); +#else + puts("Board: iMX8QM DDR4 VAL\n"); +#endif + + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + board_gpio_init(); + + +#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO + { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + const char *power_on_devices[] = { + "dma_lpuart0", + }; + + imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + +int board_late_init(void) +{ + build_info(); + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "VAL"); + env_set("board_rev", "iMX8QM"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} diff --git a/board/freescale/imx8qm_val/imximage.cfg b/board/freescale/imx8qm_val/imximage.cfg new file mode 100644 index 00000000000..7dc6b93eb58 --- /dev/null +++ b/board/freescale/imx8qm_val/imximage.cfg @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QM */ +SOC_TYPE IMX8QM +/* Append seco container image */ +APPEND mx8qm-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qm-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8qm_val/spl.c b/board/freescale/imx8qm_val/spl.c new file mode 100644 index 00000000000..1d930304872 --- /dev/null +++ b/board/freescale/imx8qm_val/spl.c @@ -0,0 +1,66 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ + board_quiesce_devices(); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8qm_val/uboot-container.cfg b/board/freescale/imx8qm_val/uboot-container.cfg new file mode 100644 index 00000000000..6cc47cd1027 --- /dev/null +++ b/board/freescale/imx8qm_val/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QM +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig index b67300d816c..796b90c880c 100644 --- a/board/freescale/imx8qxp_mek/Kconfig +++ b/board/freescale/imx8qxp_mek/Kconfig @@ -1,4 +1,4 @@ -if TARGET_IMX8QXP_MEK +if TARGET_IMX8QXP_MEK || TARGET_IMX8DX_MEK config SYS_BOARD default "imx8qxp_mek" diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c index 7179823a223..a4f9fab986b 100644 --- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c +++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c @@ -21,9 +21,17 @@ #include #include #include +#include +#include "../common/tcpc.h" DECLARE_GLOBAL_DATA_PTR; +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ @@ -85,35 +93,246 @@ static inline void board_gpio_init(void) {} #if IS_ENABLED(CONFIG_FEC_MXC) #include +#ifndef CONFIG_DM_ETH +static iomux_cfg_t pad_enet1[] = { + SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_SPDIF0_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX3_RX2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX2_RX3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_SCKR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_SCKT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FSR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +static void enet_device_phy_reset(void) +{ + struct gpio_desc desc; + int ret; + + /* The BB_PER_RST_B will reset the ENET1 PHY */ + if (0 == CONFIG_FEC_ENET_DEV) { + ret = dm_gpio_lookup_name("gpio@1a_4", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "enet0_reset"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + udelay(50); + dm_gpio_set_value(&desc, 1); + } + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + /* Reset ENET PHY */ + enet_device_phy_reset(); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + int board_phy_config(struct phy_device *phydev) { + if (phydev->drv->config) + phydev->drv->config(phydev); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); - if (phydev->drv->config) - phydev->drv->config(phydev); - return 0; } #endif +#endif int checkboard(void) { +#ifdef CONFIG_TARGET_IMX8DX_MEK + puts("Board: iMX8DX MEK\n"); +#else puts("Board: iMX8QXP MEK\n"); +#endif - build_info(); print_bootinfo(); return 0; } +#ifdef CONFIG_USB + +#ifdef CONFIG_USB_TCPC +struct gpio_desc type_sel_desc; +static iomux_cfg_t ss_mux_gpio[] = { + SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +struct tcpc_port port; +struct tcpc_port_config port_config = { + .i2c_bus = 1, + .addr = 0x50, + .port_type = TYPEC_PORT_DFP, +}; + +void ss_mux_select(enum typec_cc_polarity pol) +{ + if (pol == TYPEC_POLARITY_CC1) + dm_gpio_set_value(&type_sel_desc, 0); + else + dm_gpio_set_value(&type_sel_desc, 1); +} + +static void setup_typec(void) +{ + int ret; + struct gpio_desc typec_en_desc; + + imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); + ret = dm_gpio_lookup_name("GPIO5_9", &type_sel_desc); + if (ret) { + printf("%s lookup GPIO5_9 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&type_sel_desc, "typec_sel"); + if (ret) { + printf("%s request typec_sel failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&type_sel_desc, GPIOD_IS_OUT); + + ret = dm_gpio_lookup_name("gpio@1a_7", &typec_en_desc); + if (ret) { + printf("%s lookup gpio@1a_7 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&typec_en_desc, "typec_en"); + if (ret) { + printf("%s request typec_en failed ret = %d\n", __func__, ret); + return; + } + + /* Enable SS MUX */ + dm_gpio_set_dir_flags(&typec_en_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + tcpc_init(&port, port_config, &ss_mux_select); +} +#endif + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_dfp_mode(&port); +#endif +#ifdef CONFIG_USB_CDNS3_GADGET + } else { +#ifdef CONFIG_USB_TCPC + ret = tcpc_setup_ufp_mode(&port); + printf("%d setufp mode %d\n", index, ret); +#endif +#endif + } + } + + return ret; + +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 1) { + if (init == USB_INIT_HOST) { +#ifdef CONFIG_USB_TCPC + ret = tcpc_disable_src_vbus(&port); +#endif + } + } + + return ret; +} +#endif + int board_init(void) { board_gpio_init(); +#if defined(CONFIG_USB) && defined(CONFIG_USB_TCPC) + setup_typec(); +#endif + #ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO { int ret = snvs_security_sc_init(); @@ -126,12 +345,27 @@ int board_init(void) return 0; } +void board_quiesce_devices(void) +{ + const char *power_on_devices[] = { + "dma_lpuart0", + + /* HIFI DSP boot */ + "audio_sai0", + "audio_ocram", + }; + + imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + /* * Board specific reset that is system reset. */ void reset_cpu(ulong addr) { - /* TODO */ + sc_pm_reboot(-1, SC_PM_RESET_TYPE_COLD); + while(1); + } #ifdef CONFIG_OF_BOARD_SETUP @@ -141,30 +375,65 @@ int ft_board_setup(void *blob, struct bd_info *bd) } #endif -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - int board_late_init(void) { char *fdt_file; bool m4_booted; + build_info(); + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "MEK"); +#ifdef CONFIG_TARGET_IMX8DX_MEK + env_set("board_rev", "iMX8DX"); +#else env_set("board_rev", "iMX8QXP"); #endif +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif fdt_file = env_get("fdt_file"); m4_booted = m4_parts_booted(); if (fdt_file && !strcmp(fdt_file, "undefined")) { +#ifdef CONFIG_TARGET_IMX8DX_MEK + if (m4_booted) + env_set("fdt_file", "imx8dx-mek-rpmsg.dtb"); + else + env_set("fdt_file", "imx8dx-mek.dtb"); +#else if (m4_booted) env_set("fdt_file", "imx8qxp-mek-rpmsg.dtb"); else env_set("fdt_file", "imx8qxp-mek.dtb"); +#endif } +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + return 0; } + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + sc_bool_t status = SC_FALSE; + + sc_misc_get_button_status(-1, &status); + return (bool)status; +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY +int is_recovery_key_pressing(void) +{ + return 0; /* TODO */ +} +#endif /* CONFIG_ANDROID_RECOVERY */ +#endif /* CONFIG_FSL_FASTBOOT */ diff --git a/board/freescale/imx8qxp_mek/spl.c b/board/freescale/imx8qxp_mek/spl.c index ae6b64ff6ea..1fdc3fc6dd0 100644 --- a/board/freescale/imx8qxp_mek/spl.c +++ b/board/freescale/imx8qxp_mek/spl.c @@ -22,6 +22,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -38,16 +39,22 @@ static iomux_cfg_t usdhc2_sd_pwr[] = { void spl_board_init(void) { struct udevice *dev; + int node, ret; - uclass_find_first_device(UCLASS_MISC, &dev); + node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx8-mu"); + + ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &dev); + if (ret) { + return; + } + device_probe(dev); + uclass_find_first_device(UCLASS_MISC, &dev); for (; dev; uclass_find_next_device(&dev)) { if (device_probe(dev)) continue; } - arch_cpu_init(); - board_early_init_f(); timer_init(); @@ -55,14 +62,16 @@ void spl_board_init(void) imx8_iomux_setup_multiple_pads(usdhc2_sd_pwr, ARRAY_SIZE(usdhc2_sd_pwr)); gpio_direction_output(USDHC2_SD_PWR, 0); +#ifdef CONFIG_SPL_SERIAL_SUPPORT preloader_console_init(); puts("Normal Boot\n"); +#endif } void spl_board_prepare_for_boot(void) { - imx8_power_off_pd_devices(NULL, 0); + board_quiesce_devices(); } #ifdef CONFIG_SPL_LOAD_FIT @@ -77,11 +86,10 @@ int board_fit_config_name_match(const char *name) void board_init_f(ulong dummy) { - /* Clear global data */ - memset((void *)gd, 0, sizeof(gd_t)); - /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start); + arch_cpu_init(); + board_init_r(NULL, 0); } diff --git a/board/freescale/imx8qxp_val/Kconfig b/board/freescale/imx8qxp_val/Kconfig new file mode 100644 index 00000000000..d472cffff75 --- /dev/null +++ b/board/freescale/imx8qxp_val/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8QXP_LPDDR4_VAL || TARGET_IMX8QXP_DDR3_VAL || TARGET_IMX8X_17X17_VAL + +config SYS_BOARD + default "imx8qxp_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "imx8qxp_val" + +endif diff --git a/board/freescale/imx8qxp_val/Makefile b/board/freescale/imx8qxp_val/Makefile new file mode 100644 index 00000000000..0b4e005a69c --- /dev/null +++ b/board/freescale/imx8qxp_val/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2017-2019 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8qxp_val.o +obj-$(CONFIG_SPL_BUILD) += spl.o diff --git a/board/freescale/imx8qxp_val/imx8qxp_val.c b/board/freescale/imx8qxp_val/imx8qxp_val.c new file mode 100644 index 00000000000..b747fed50c3 --- /dev/null +++ b/board/freescale/imx8qxp_val/imx8qxp_val.c @@ -0,0 +1,499 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pca953x.h" + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define GPMI_NAND_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \ + | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + + +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \ + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_NAND_MXS +static iomux_cfg_t gpmi_nand_pads[] = { + SC_P_EMMC0_CLK | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA4 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA5 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA6 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_DATA7 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_STROBE | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_EMMC0_RESET_B | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_DATA2 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_DATA3 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + + /* i.MX8QXP NAND use nand_re_dqs_pins */ + SC_P_USDHC1_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + +}; + +static void setup_iomux_gpmi_nand(void) +{ + imx8_iomux_setup_multiple_pads(gpmi_nand_pads, ARRAY_SIZE(gpmi_nand_pads)); +} + +static void imx8qxp_gpmi_nand_initialize(void) +{ + int ret; + + ret = sc_pm_set_resource_power_mode(-1, SC_R_NAND, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + return; + + init_clk_gpmi_nand(); + setup_iomux_gpmi_nand(); +} +#endif +#endif + +static iomux_cfg_t uart0_pads[] = { + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate = SC_80MHZ; + int ret; + + /* Set UART0 clock root to 80 MHz */ + ret = sc_pm_setup_uart(SC_R_UART_0, rate); + if (ret) + return ret; + + setup_iomux_uart(); + +#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_NAND_MXS + imx8qxp_gpmi_nand_initialize(); +#endif +#endif + + return 0; +} + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +#ifndef CONFIG_DM_ETH +static iomux_cfg_t pad_enet1[] = { + SC_P_SPDIF0_TX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_SPDIF0_RX | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX3_RX2 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX2_RX3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_TX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ESAI0_SCKR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FST | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_SCKT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ESAI0_FSR | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static iomux_cfg_t pad_enet0[] = { + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL), + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + + /* Shared MDIO */ + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + if (0 == CONFIG_FEC_ENET_DEV) + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0)); + else + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1)); +} + +static void enet_device_phy_reset(void) +{ + struct gpio_desc desc_enet0; + struct gpio_desc desc_enet1; + int ret; + + ret = dm_gpio_lookup_name("gpio@18_1", &desc_enet0); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet0, "enet0_reset"); + if (ret) + return; + + ret = dm_gpio_lookup_name("gpio@18_4", &desc_enet1); + if (ret) + return; + + ret = dm_gpio_request(&desc_enet1, "enet1_reset"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc_enet0, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet0, 0); + udelay(50); + dm_gpio_set_value(&desc_enet0, 1); + + dm_gpio_set_dir_flags(&desc_enet1, GPIOD_IS_OUT); + dm_gpio_set_value(&desc_enet1, 0); + udelay(50); + dm_gpio_set_value(&desc_enet1, 1); + + /* The board has a long delay for this reset to become stable */ + mdelay(200); +} + +int board_eth_init(bd_t *bis) +{ + int ret; + struct power_domain pd; + + printf("[%s] %d\n", __func__, __LINE__); + + /* Reset ENET PHY */ + enet_device_phy_reset(); + + if (CONFIG_FEC_ENET_DEV) { + if (!power_domain_lookup_name("conn_enet1", &pd)) + power_domain_on(&pd); + } else { + if (!power_domain_lookup_name("conn_enet0", &pd)) + power_domain_on(&pd); + } + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} +#endif + +#define MAX7322_I2C_ADDR 0x68 +#define MAX7322_I2C_BUS 0 /* I2C1 */ +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->addr == 1) { + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + uint8_t value; + struct udevice *bus; + struct udevice *i2c_dev = NULL; + int ret; + + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS, &bus); + if (ret) { + printf("%s: Can't find bus\n", __func__); + return -EINVAL; + } + + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &i2c_dev); + if (ret) { + printf("%s: Can't find device id=0x%x\n", + __func__, MAX7322_I2C_ADDR); + return -ENODEV; + } + + i2c_set_chip_offset_len(i2c_dev, 0); + + value = 0x1; + + ret = dm_i2c_write(i2c_dev, 0x0, (const uint8_t *)&value, 1); + if (ret) { + printf("%s dm_i2c_write failed, err %d\n", __func__, ret); + return -EIO; + } + + mdelay(1); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + +#ifndef CONFIG_DM_ETH + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); +#endif + + return 0; +} +#endif + +#define DEBUG_LED IMX_GPIO_NR(3, 23) +#define IOEXP_RESET IMX_GPIO_NR(0, 19) +#define BB_PWR_EN IMX_GPIO_NR(5, 9) + +static iomux_cfg_t board_gpios[] = { + SC_P_QSPI0B_SS0_B | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_MCLK_IN0 | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), + SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static void board_gpio_init(void) +{ + int ret; + struct gpio_desc desc; + struct udevice *dev; + + imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios)); + + /* enable i2c port expander assert reset line first */ + /* we can't use dm_gpio_lookup_name for GPIO1_12, because the func will probe the + * uclass list until find the device. The expander device is at begin of the list due to + * I2c nodes is prior than gpio in the DTS. So if the func goes through the uclass list, + * probe to expander will fail, and exit the dm_gpio_lookup_name func. Thus, we always + * fail to get the device + */ + ret = uclass_get_device_by_seq(UCLASS_GPIO, 0, &dev); + if (ret) { + printf("%s failed to find GPIO1 device, ret = %d\n", __func__, ret); + return; + } + + desc.dev = dev; + desc.offset = 19; + desc.flags = 0; + + ret = dm_gpio_request(&desc, "ioexp_rst"); + if (ret) { + printf("%s request ioexp_rst failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + ret = dm_gpio_lookup_name("GPIO3_23", &desc); + if (ret) { + printf("%s lookup GPIO@3_23 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "debug_led"); + if (ret) { + printf("%s request debug_led failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + ret = dm_gpio_lookup_name("GPIO5_9", &desc); + if (ret) { + printf("%s lookup GPIO@5_9 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "bb_pwr_en"); + if (ret) { + printf("%s request bb_pwr_en failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +int checkboard(void) +{ +#if defined(CONFIG_TARGET_IMX8QXP_DDR3_VAL) + puts("Board: iMX8QXP DDR3 VAL\n"); +#elif defined(CONFIG_TARGET_IMX8X_17X17_VAL) + puts("Board: iMX8X(QXP/DX) 17x17 Validation Board\n"); +#else + puts("Board: iMX8QXP LPDDR4 VAL\n"); +#endif + + print_bootinfo(); + + return 0; +} + +int board_usb_init(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 0) { + if (init == USB_INIT_DEVICE) { +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB) + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + printf("conn_usb0 Power up failed! (error = %d)\n", ret); + + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_ON); + if (ret != SC_ERR_NONE) + printf("conn_usb0_phy Power up failed! (error = %d)\n", ret); +#endif + } + } + return ret; +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + int ret = 0; + + if (index == 0) { + if (init == USB_INIT_DEVICE) { +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) && !CONFIG_IS_ENABLED(DM_USB) + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0, SC_PM_PW_MODE_OFF); + if (ret != SC_ERR_NONE) + printf("conn_usb0 Power down failed! (error = %d)\n", ret); + + ret = sc_pm_set_resource_power_mode(-1, SC_R_USB_0_PHY, SC_PM_PW_MODE_OFF); + if (ret != SC_ERR_NONE) + printf("conn_usb0_phy Power down failed! (error = %d)\n", ret); +#endif + } + } + return ret; +} + +int board_init(void) +{ + board_gpio_init(); + +#ifdef CONFIG_IMX_SNVS_SEC_SC_AUTO + { + int ret = snvs_security_sc_init(); + + if (ret) + return ret; + } +#endif + + return 0; +} + +void board_quiesce_devices(void) +{ + const char *power_on_devices[] = { + "dma_lpuart0", + + /* HIFI DSP boot */ + "audio_sai0", + "audio_ocram", + }; + + imx8_power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices)); +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} +#endif + + +int board_late_init(void) +{ + build_info(); + +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "VAL"); + env_set("board_rev", "iMX8QXP"); +#endif + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} diff --git a/board/freescale/imx8qxp_val/imximage.cfg b/board/freescale/imx8qxp_val/imximage.cfg new file mode 100644 index 00000000000..259a1646bf9 --- /dev/null +++ b/board/freescale/imx8qxp_val/imximage.cfg @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + * + * Refer doc/README.imx8image for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM SD 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-mek-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 spl/u-boot-spl.bin 0x00100000 diff --git a/board/freescale/imx8qxp_val/spl.c b/board/freescale/imx8qxp_val/spl.c new file mode 100644 index 00000000000..1d930304872 --- /dev/null +++ b/board/freescale/imx8qxp_val/spl.c @@ -0,0 +1,66 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + struct udevice *dev; + + uclass_find_first_device(UCLASS_MISC, &dev); + + for (; dev; uclass_find_next_device(&dev)) { + if (device_probe(dev)) + continue; + } + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + puts("Normal Boot\n"); +} + +void spl_board_prepare_for_boot(void) +{ + board_quiesce_devices(); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + arch_cpu_init(); + + board_init_r(NULL, 0); +} diff --git a/board/freescale/imx8qxp_val/uboot-container.cfg b/board/freescale/imx8qxp_val/uboot-container.cfg new file mode 100644 index 00000000000..81658118185 --- /dev/null +++ b/board/freescale/imx8qxp_val/uboot-container.cfg @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#define __ASSEMBLY__ + +/* This file is to create a container image could be loaded by SPL */ +BOOT_FROM SD 0x400 +SOC_TYPE IMX8QX +CONTAINER +IMAGE A35 bl31.bin 0x80000000 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c index 2cd651b943f..62d6bec1a18 100644 --- a/board/freescale/ls1012afrdm/ls1012afrdm.c +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017-2018 NXP + * Copyright 2017-2018, 2021 NXP */ #include @@ -22,7 +22,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -175,10 +174,6 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index cfe3f3360cd..282d9dc7419 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -28,7 +28,6 @@ #include #include #include -#include #include "../common/qixis.h" #include "ls1012aqds_qixis.h" #include "ls1012aqds_pfe.h" @@ -153,10 +152,6 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c index 41bcf6f935e..9e452e855e3 100644 --- a/board/freescale/ls1012ardb/ls1012ardb.c +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -27,7 +27,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -176,10 +175,6 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index bfe61376042..7b7b1139209 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -209,10 +209,7 @@ int misc_init_r(void) device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); #endif - -#ifdef CONFIG_FSL_CAAM - return sec_init(); -#endif + return 0; } #endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index aa1f6025c13..00fa9f7fc45 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -408,9 +407,6 @@ int misc_init_r(void) #ifdef CONFIG_FSL_DEVICE_DISABLE device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); -#endif -#ifdef CONFIG_FSL_CAAM - return sec_init(); #endif return 0; } diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index c1acd3040c4..b89629b6acb 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -238,10 +238,7 @@ int misc_init_r(void) #ifdef CONFIG_FSL_DEVICE_DISABLE device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); #endif - -#ifdef CONFIG_FSL_CAAM - return sec_init(); -#endif + return 0; } #endif diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 4c3be421795..fe42510eb84 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -555,10 +554,7 @@ int misc_init_r(void) #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) config_board_mux(); #endif - -#ifdef CONFIG_FSL_CAAM - return sec_init(); -#endif + return 0; } #endif diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index 5269fd34c69..af8966cf666 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ #include @@ -77,10 +77,6 @@ int board_init(void) gd->env_addr = (ulong)&default_environment[0]; #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -336,3 +332,8 @@ int checkboard(void) return 0; } #endif + +void *video_hw_init(void) +{ + return NULL; +} diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index beef26b084b..b39ff003ad3 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "cpld.h" #ifdef CONFIG_U_QE #include @@ -211,10 +210,6 @@ int board_init(void) out_le32(SMMU_NSCR0, val); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index f1709dcd1cd..2cd9cc9fcec 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #include @@ -20,7 +20,6 @@ #include #include #include -#include #include #define LS1046A_PORSR1_REG 0x1EE0000 @@ -160,10 +159,6 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); out_le32(SMMU_NSCR0, val); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 20694426af3..5f9f59551a7 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include "../common/vid.h" @@ -448,10 +447,6 @@ int board_init(void) out_le32(SMMU_NSCR0, val); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - return 0; } diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 93ef903f299..d8b907181d3 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -23,7 +23,6 @@ #include #include #include "cpld.h" -#include DECLARE_GLOBAL_DATA_PTR; @@ -85,10 +84,6 @@ int board_init(void) out_le32(SMMU_NSCR0, val); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index f5dc449d898..7f119ca43e7 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -839,9 +838,6 @@ int board_init(void) out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index 95723192349..f155150a944 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2015 Freescale Semiconductor + * Copyright 2015, 2021 Freescale Semiconductor */ #include #include @@ -20,7 +20,6 @@ #include #include #include -#include #include #include @@ -245,10 +244,6 @@ int board_init(void) #endif #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif - #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index 3a026b08274..c521868dac2 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #ifdef CONFIG_FSL_QIXIS @@ -273,9 +272,6 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif #ifdef CONFIG_FSL_LS_PPA ppa_init(); #endif @@ -284,9 +280,6 @@ int board_init(void) /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); #endif -#ifdef CONFIG_FSL_CAAM - sec_init(); -#endif #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) pci_init(); diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig index 7556f7dd215..ce2ef5d23c2 100644 --- a/board/freescale/lx2160a/Kconfig +++ b/board/freescale/lx2160a/Kconfig @@ -12,6 +12,15 @@ config SYS_SOC config SYS_CONFIG_NAME default "lx2160ardb" +config QSFP_EEPROM + bool "Support for reading QSFP+ transceiver eeprom" + default y if PHY_CORTINA + help + This option enables the functionality for reading + QSFP+ cable eeprom. It can be used when PHYs are + requiring different initialization based on cable + type. + source "board/freescale/common/Kconfig" endif diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c index 15cbc58d59a..30a3af9f473 100644 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018, 2020 NXP + * Copyright 2018-2021 NXP * */ @@ -41,6 +41,49 @@ static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad) return false; } +int setup_eth_rev_c(u32 srds_p) +{ + struct mii_dev *bus; + int i; + + /* difference between SerDes1 protocols 18/19 is 4x10G vs. 40G */ + switch (srds_p) { + case 19: + wriop_init_dpmac_enet_if(WRIOP1_DPMAC2, + PHY_INTERFACE_MODE_XLAUI); + break; + case 18: + for (i = WRIOP1_DPMAC7; i <= WRIOP1_DPMAC10; i++) + wriop_init_dpmac_enet_if(i, PHY_INTERFACE_MODE_XFI); + break; + default: + printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n", + srds_p); + return -1; + } + + /* common interfaces for SerDes1 protocols 18 and 19 initialization */ + wriop_set_phy_address(WRIOP1_DPMAC3, 0, AQR113C_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC4, 0, AQR113C_PHY_ADDR2); + wriop_set_phy_address(WRIOP1_DPMAC5, 0, INPHI_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC6, 0, INPHI_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1); + wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2); + + /* assign DPMAC/PHY to MDIO bus */ + bus = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + wriop_set_mdio(WRIOP1_DPMAC3, bus); + wriop_set_mdio(WRIOP1_DPMAC4, bus); + wriop_set_mdio(WRIOP1_DPMAC17, bus); + wriop_set_mdio(WRIOP1_DPMAC18, bus); + + bus = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + wriop_set_mdio(WRIOP1_DPMAC5, bus); + wriop_set_mdio(WRIOP1_DPMAC6, bus); + + return 0; +} + int board_eth_init(struct bd_info *bis) { #if defined(CONFIG_FSL_MC_ENET) @@ -70,6 +113,13 @@ int board_eth_init(struct bd_info *bis) fm_memac_mdio_init(bis, &mdio_info); dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + + /* new LX2160A-RDB2 revC board uses phy-less 25G/40G interfaces */ + if (get_board_rev() == 'C') { + setup_eth_rev_c(srds_s1); + goto next; + } + switch (srds_s1) { case 19: wriop_set_phy_address(WRIOP1_DPMAC2, 0, @@ -181,6 +231,112 @@ void reset_phy(void) } #endif /* CONFIG_RESET_PHY_R */ +static int fdt_get_dpmac_node(void *fdt, int dpmac_id) +{ + char dpmac_str[] = "dpmacs@00"; + int offset, dpmacs_offset; + + /* get the dpmac offset */ + dpmacs_offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs"); + if (dpmacs_offset < 0) + dpmacs_offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs"); + + if (dpmacs_offset < 0) { + printf("dpmacs node not found in device tree\n"); + return dpmacs_offset; + } + + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); + if (offset < 0) { + sprintf(dpmac_str, "ethernet@%x", dpmac_id); + offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); + if (offset < 0) { + printf("dpmac@%x/ethernet@%x node not found in device tree\n", + dpmac_id, dpmac_id); + return offset; + } + } + + return offset; +} + +static int fdt_update_phy_addr(void *fdt, int dpmac_id, int phy_addr) +{ + char dpmac_str[] = "dpmacs@00"; + const u32 *phyhandle; + int offset; + int err; + + /* get the dpmac offset */ + offset = fdt_get_dpmac_node(fdt, dpmac_id); + if (offset < 0) + return offset; + + /* get dpmac phy-handle */ + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); + if (!phyhandle) { + printf("%s node not found in device tree\n", dpmac_str); + return offset; + } + + offset = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyhandle)); + if (offset < 0) { + printf("Could not get the ph node offset for dpmac %d\n", + dpmac_id); + return offset; + } + + phy_addr = cpu_to_fdt32(phy_addr); + err = fdt_setprop(fdt, offset, "reg", &phy_addr, sizeof(phy_addr)); + if (err < 0) { + printf("Could not set phy node's reg for dpmac %d: %s.\n", + dpmac_id, fdt_strerror(err)); + return err; + } + + return 0; +} + +static int fdt_delete_phy_handle(void *fdt, int dpmac_id) +{ + const u32 *phyhandle; + int offset; + + /* get the dpmac offset */ + offset = fdt_get_dpmac_node(fdt, dpmac_id); + if (offset < 0) + return offset; + + /* verify if the node has a phy-handle */ + phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); + if (!phyhandle) + return 0; + + return fdt_delprop(fdt, offset, "phy-handle"); +} + +int fdt_fixup_board_phy_revc(void *fdt) +{ + int ret; + + if (get_board_rev() != 'C') + return 0; + + /* DPMACs 3,4 have their Aquantia PHYs at new addresses */ + ret = fdt_update_phy_addr(fdt, 3, AQR113C_PHY_ADDR1); + if (ret) + return ret; + + ret = fdt_update_phy_addr(fdt, 4, AQR113C_PHY_ADDR2); + if (ret) + return ret; + + /* There is no PHY for the DPMAC2, so remove the phy-handle */ + return fdt_delete_phy_handle(fdt, 2); +} + int fdt_fixup_board_phy(void *fdt) { int mdio_offset; @@ -210,5 +366,5 @@ int fdt_fixup_board_phy(void *fdt) } } - return ret; + return fdt_fixup_board_phy_revc(fdt); } diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 47a7024f331..334c5d6af3e 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP */ #include @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -34,6 +33,7 @@ #include #include #include "lx2160a.h" +#include "../common/qsfp_eeprom.h" #ifdef CONFIG_EMC2305 #include "../common/emc2305.h" @@ -100,6 +100,27 @@ int select_i2c_ch_pca9547(u8 ch) return 0; } +int select_i2c_ch_pca9547_sec(u8 ch) +{ + int ret; + +#ifndef CONFIG_DM_I2C + ret = i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &ch, 1); +#else + struct udevice *dev; + + ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_SEC, 1, &dev); + if (!ret) + ret = dm_i2c_write(dev, 0, &ch, 1); +#endif + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + static void uart_get_clock(void) { serial0.clock = get_serial_clock(); @@ -189,6 +210,11 @@ int board_fix_fdt(void *fdt) "fsl,lx2160a-pcie"); } + /* Fixup u-boot's DTS in case this is a revC board and + * we're using DM_ETH. + */ + if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB) && IS_ENABLED(CONFIG_DM_ETH)) + fdt_fixup_board_phy_revc(fdt); return 0; } #endif @@ -564,6 +590,15 @@ int config_board_mux(void) } #endif +#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB) +u8 get_board_rev(void) +{ + u8 board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A'; + + return board_rev; +} +#endif + unsigned long get_board_sys_clk(void) { #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) @@ -602,6 +637,32 @@ unsigned long get_board_ddr_clk(void) #endif } +#if defined(CONFIG_TARGET_LX2160ARDB) && defined(CONFIG_QSFP_EEPROM) && defined(CONFIG_PHY_CORTINA) +void qsfp_cortina_detect(void) +{ + u8 qsfp_compat_code; + + /* read qsfp+ eeprom & update environment for cs4223 init */ + select_i2c_ch_pca9547(I2C_MUX_CH_SEC); + select_i2c_ch_pca9547_sec(I2C_MUX_CH_QSFP); + qsfp_compat_code = get_qsfp_compat0(); + switch (qsfp_compat_code) { + case QSFP_COMPAT_CR4: + env_set(CS4223_CONFIG_ENV, CS4223_CONFIG_CR4); + break; + case QSFP_COMPAT_XLPPI: + case QSFP_COMPAT_SR4: + env_set(CS4223_CONFIG_ENV, CS4223_CONFIG_SR4); + break; + default: + /* do nothing if detection fails or not supported*/ + break; + } + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); +} + +#endif /* CONFIG_QSFP_EEPROM & CONFIG_PHY_CORTINA */ + int board_init(void) { #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) @@ -616,10 +677,10 @@ int board_init(void) #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB) /* invert AQR107 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); -#endif -#ifdef CONFIG_FSL_CAAM - sec_init(); +#if defined(CONFIG_QSFP_EEPROM) && defined(CONFIG_PHY_CORTINA) + qsfp_cortina_detect(); +#endif #endif #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH) @@ -714,6 +775,9 @@ void fdt_fixup_board_enet(void *fdt) fdt_status_okay(fdt, offset); #ifndef CONFIG_DM_ETH fdt_fixup_board_phy(fdt); +#else + if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB)) + fdt_fixup_board_phy_revc(fdt); #endif } else { fdt_status_fail(fdt, offset); @@ -726,6 +790,116 @@ void board_quiesce_devices(void) } #endif +#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB) +int fdt_fixup_add_thermal(void *blob, int mux_node, int channel, int reg) +{ + int err; + int noff; + int offset; + char channel_node_name[50]; + char thermal_node_name[50]; + u32 phandle; + + snprintf(channel_node_name, sizeof(channel_node_name), + "i2c@%x", channel); + debug("channel_node_name = %s\n", channel_node_name); + + snprintf(thermal_node_name, sizeof(thermal_node_name), + "temperature-sensor@%x", reg); + debug("thermal_node_name = %s\n", thermal_node_name); + + err = fdt_increase_size(blob, 200); + if (err) { + printf("fdt_increase_size: err=%s\n", fdt_strerror(err)); + return err; + } + + noff = fdt_subnode_offset(blob, mux_node, (const char *) + channel_node_name); + if (noff < 0) { + /* channel node not found - create it */ + noff = fdt_add_subnode(blob, mux_node, channel_node_name); + if (noff < 0) { + printf("fdt_add_subnode: err=%s\n", fdt_strerror(err)); + return err; + } + fdt_setprop_u32 (blob, noff, "#address-cells", 1); + fdt_setprop_u32 (blob, noff, "#size-cells", 0); + fdt_setprop_u32 (blob, noff, "reg", channel); + } + + /* Create thermal node*/ + offset = fdt_add_subnode(blob, noff, thermal_node_name); + fdt_setprop(blob, offset, "compatible", "nxp,sa56004", + strlen("nxp,sa56004") + 1); + fdt_setprop_u32 (blob, offset, "reg", reg); + + /* fixup phandle*/ + noff = fdt_node_offset_by_compatible(blob, -1, "regulator-fixed"); + if (noff < 0) { + printf("%s : failed to get phandle\n", __func__); + return noff; + } + phandle = fdt_get_phandle(blob, noff); + fdt_setprop_u32 (blob, offset, "vcc-supply", phandle); + + return 0; +} + +void fdt_fixup_delete_thermal(void *blob, int mux_node, int channel, int reg) +{ + int node; + int value; + int err; + int subnode; + + fdt_for_each_subnode(subnode, blob, mux_node) { + value = fdtdec_get_uint(blob, subnode, "reg", -1); + if (value == channel) { + /* delete thermal node */ + fdt_for_each_subnode(node, blob, subnode) { + value = fdtdec_get_uint(blob, node, "reg", -1); + err = fdt_node_check_compatible(blob, node, + "nxp,sa56004"); + if (!err && value == reg) { + fdt_del_node(blob, node); + break; + } + } + } + } +} + +void fdt_fixup_i2c_thermal_node(void *blob) +{ + int i2coffset; + int mux_node; + int reg; + int err; + + i2coffset = fdt_node_offset_by_compat_reg(blob, "fsl,vf610-i2c", + 0x2000000); + if (i2coffset != -FDT_ERR_NOTFOUND) { + fdt_for_each_subnode(mux_node, blob, i2coffset) { + reg = fdtdec_get_uint(blob, mux_node, "reg", -1); + err = fdt_node_check_compatible(blob, mux_node, + "nxp,pca9547"); + if (!err && reg == 0x77) { + fdt_fixup_delete_thermal(blob, mux_node, + 0x3, 0x4d); + err = fdt_fixup_add_thermal(blob, mux_node, + 0x3, 0x48); + if (err) + printf("%s: Add thermal node failed\n", + __func__); + } + } + } else { + printf("%s: i2c node not found\n", __func__); + } +} +#endif + #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) { @@ -791,6 +965,11 @@ int ft_board_setup(void *blob, struct bd_info *bd) #endif fdt_fixup_icid(blob); +if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB)) { + if (get_board_rev() >= 'C') + fdt_fixup_i2c_thermal_node(blob); + } + return 0; } #endif diff --git a/board/freescale/lx2160a/lx2160a.h b/board/freescale/lx2160a/lx2160a.h index 52b020765dc..ac17365d507 100644 --- a/board/freescale/lx2160a/lx2160a.h +++ b/board/freescale/lx2160a/lx2160a.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #ifndef __LX2160_H @@ -58,4 +58,22 @@ #endif #endif +#if defined(CONFIG_QSFP_EEPROM) && defined(CONFIG_PHY_CORTINA) +#define CS4223_CONFIG_ENV "cs4223_autoconfig" +#define CS4223_CONFIG_CR4 "copper" +#define CS4223_CONFIG_SR4 "optical" + +enum qsfp_compat_codes { + QSFP_COMPAT_XLPPI = 0x01, + QSFP_COMPAT_LR4 = 0x02, + QSFP_COMPAT_SR4 = 0x04, + QSFP_COMPAT_CR4 = 0x08, +}; +#endif /* CONFIG_QSFP_EEPROM && CONFIG_PHY_CORTINA */ + +#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB) +u8 get_board_rev(void); +int fdt_fixup_board_phy_revc(void *fdt); +#endif + #endif /* __LX2160_H */ diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig index 8ab8b460f92..6d2c75151c0 100644 --- a/board/freescale/mx6qarm2/Kconfig +++ b/board/freescale/mx6qarm2/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MX6QARM2 +if TARGET_MX6QARM2 || TARGET_MX6DLARM2 config SYS_BOARD default "mx6qarm2" @@ -9,4 +9,10 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6qarm2" +config SYS_TEXT_BASE + default 0x17800000 + +config MX6DQ_POP_LPDDR2 + bool "Select this if it is a MX6Q POP LPDDR2 board" + endif diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index 74a33c25032..7d27529bfe2 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. * Jason Liu * * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure @@ -9,6 +9,9 @@ * The syntax is taken as close as possible with the kwbimage */ +#define __ASSEMBLY__ +#include + /* image version */ IMAGE_VERSION 2 @@ -18,6 +21,15 @@ IMAGE_VERSION 2 */ BOOT_FROM sd +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + /* * Device Configuration Data (DCD) * @@ -29,8 +41,179 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ -#ifdef CONFIG_MX6DQ_LPDDR2 +#ifdef CONFIG_MX6DQ_POP_LPDDR2 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* DCD */ +DATA 4 0x020e0798 0x00080000 +DATA 4 0x020e0758 0x00000000 + +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 + +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 + +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 + +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00003030 +DATA 4 0x020e05b0 0x00003030 +DATA 4 0x020e0524 0x00003030 +DATA 4 0x020e051c 0x00003030 +DATA 4 0x020e0518 0x00003030 +DATA 4 0x020e050c 0x00003030 +DATA 4 0x020e05b8 0x00003030 +DATA 4 0x020e05c0 0x00003030 + +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 + +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b401c 0x00008000 + +DATA 4 0x021b085c 0x1B5F0107 +DATA 4 0x021b485c 0x1B5F0107 + +DATA 4 0x021b0800 0xA1390003 + +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b4890 0x00400000 + +DATA 4 0x021b0848 0x3C3A3A44 +DATA 4 0x021b4848 0x3C3A3A44 + +DATA 4 0x021b0850 0x4238423A +DATA 4 0x021b4850 0x4238423A + +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x00000000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b482c 0xf3333333 +DATA 4 0x021b4830 0xf3333333 +DATA 4 0x021b4834 0xf3333333 +DATA 4 0x021b4838 0xf3333333 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b000c 0x444961A5 +DATA 4 0x021b0010 0x00160E83 +DATA 4 0x021b0014 0x000000DD + +DATA 4 0x021b0018 0x0000174C +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x149F26D2 +DATA 4 0x021b0030 0x00000010 +DATA 4 0x021b0038 0x0021099B +DATA 4 0x021b0040 0x0000004F +DATA 4 0x021b0400 0x11420000 +DATA 4 0x021b0000 0x83110000 + +DATA 4 0x021b4004 0x00020036 +DATA 4 0x021b4008 0x00000000 +DATA 4 0x021b400c 0x444961A5 +DATA 4 0x021b4010 0x00160E83 +DATA 4 0x021b4014 0x000000DD + +DATA 4 0x021b4018 0x0000174C +DATA 4 0x021b401c 0x00008000 +DATA 4 0x021b402c 0x149F26D2 +DATA 4 0x021b4030 0x00000010 +DATA 4 0x021b4038 0x0021099B +DATA 4 0x021b4040 0x00000017 +DATA 4 0x021b4400 0x11420000 +DATA 4 0x021b4000 0x83110000 + +DATA 4 0x021b001c 0x003F8030 +DATA 4 0x021b001c 0xFF0A8030 +DATA 4 0x021b001c 0xC2018030 +DATA 4 0x021b001c 0x06028030 +DATA 4 0x021b001c 0x02038030 + +DATA 4 0x021b401c 0x003F8030 +DATA 4 0x021b401c 0xFF0A8030 +DATA 4 0x021b401c 0xC2018030 +DATA 4 0x021b401c 0x06028030 +DATA 4 0x021b401c 0x02038030 + +DATA 4 0x021b0800 0xA1390003 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b4020 0x00001800 + +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b4818 0x00000000 + +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b4004 0x00025576 + +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b4404 0x00011006 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b401c 0x00000000 + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F + +#elif defined(CONFIG_MX6DQ_LPDDR2) /* DCD */ +DATA 4 0x020C4018 0x21324 +DATA 4 0x020C4014 0x2018D00 +CHECK_BITS_CLR 4 0x020C4048 0x3F +DATA 4 0x020C4018 0x61324 +DATA 4 0x020C4014 0x18D00 +CHECK_BITS_CLR 4 0x020C4048 0x3F DATA 4 0x020C4018 0x60324 DATA 4 0x020E05a8 0x00003038 @@ -335,3 +518,4 @@ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F #endif /* CONFIG_MX6DQ_LPDDR2 */ +#endif diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg index 0d1353119ba..386d21f8e04 100644 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. * Jason Liu * * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure @@ -9,6 +9,9 @@ * The syntax is taken as close as possible with the kwbimage */ +#define __ASSEMBLY__ +#include + /* image version */ IMAGE_VERSION 2 @@ -18,6 +21,15 @@ IMAGE_VERSION 2 */ BOOT_FROM sd +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + /* * Device Configuration Data (DCD) * @@ -459,3 +471,4 @@ DATA 4 0x020e0010 0xF00000CF DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F #endif /* CONFIG_MX6DL_LPDDR2 */ +#endif diff --git a/board/freescale/mx6qarm2/mt128x64mx32.cfg b/board/freescale/mx6qarm2/mt128x64mx32.cfg new file mode 100644 index 00000000000..8fe02fcb88f --- /dev/null +++ b/board/freescale/mx6qarm2/mt128x64mx32.cfg @@ -0,0 +1,301 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_MX6DQ_POP_LPDDR2 +/* set ddr to 400Mhz */ +DATA 4 0x020C4018 0x21324 +DATA 4 0x020C4014 0x2018100 +CHECK_BITS_CLR 4 0x020C4048 0x3F +DATA 4 0x020C4018 0x61324 +DATA 4 0x020C4014 0x18900 +CHECK_BITS_CLR 4 0x020C4048 0x3F +DATA 4 0x020C4018 0x60324 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff +// Switch PL301_FAST2 to DDR dual channel mapping +//DATA 4 0x00B00000 0x1 + +//============================================================================= +/// IOMUX +//============================================================================= +//DDR IO TYPE: +DATA 4 0x020e0774 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE +DATA 4 0x020e0758 0x00000000 // IOMUXC_SW_PAD_CTL_GRP_DDRPKE + +//CLOCK: +DATA 4 0x020e0588 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 +DATA 4 0x020e0594 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 + +//Control: +DATA 4 0x020e056c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS +DATA 4 0x020e0578 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS +DATA 4 0x020e057c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET +DATA 4 0x020e058c 0x00000000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS +DATA 4 0x020e059c 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 +DATA 4 0x020e05a0 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 +DATA 4 0x020e074c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_ADDDS +DATA 4 0x020e078c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_CTLDS + +//Data Strobes: +DATA 4 0x020e0750 0x00020000 // IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL +DATA 4 0x020e05a8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 +DATA 4 0x020e05b0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 +DATA 4 0x020e0524 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 +DATA 4 0x020e051c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 +DATA 4 0x020e0518 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4 +DATA 4 0x020e050c 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5 +DATA 4 0x020e05b8 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6 +DATA 4 0x020e05c0 0x00003030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7 + +//Data: +DATA 4 0x020e0798 0x00080000 // IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE +DATA 4 0x020e0784 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B0DS +DATA 4 0x020e0788 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B1DS +DATA 4 0x020e0794 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B2DS +DATA 4 0x020e079c 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B3DS +DATA 4 0x020e07a0 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B4DS +DATA 4 0x020e07a4 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B5DS +DATA 4 0x020e07a8 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B6DS +DATA 4 0x020e0748 0x00000030 // IOMUXC_SW_PAD_CTL_GRP_B7DS + +DATA 4 0x020e05ac 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 +DATA 4 0x020e05b4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 +DATA 4 0x020e0528 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 +DATA 4 0x020e0520 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 +DATA 4 0x020e0514 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 +DATA 4 0x020e0510 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 +DATA 4 0x020e05bc 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 +DATA 4 0x020e05c4 0x00000030 // IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 + +//============================================================================= +// DDR Controller Registers +//============================================================================= +// Manufacturer: Micron - POP Package +// Device Part Number: MT42L128M64D2LL-25WT +// Clock Freq.: 400MHz +// Density per CS in Gb: 4 +// Chip Selects used: 1 +// Number of channels 2 +// Density per channel (Gb) 4 +// Total DRAM density (Gb) 8 +// Number of Banks: 8 +// Row address: 14 +// Column address: 10 +// Data bus width 32 +//============================================================================= + +// MMDC0_MDSCR, set the Configuration request bit during MMDC set up +DATA 4 0x021b001c 0x00008000 // Chan 0 +DATA 4 0x021b401c 0x00008000 // Chan 1 +// Adjust ZQ delay for MMDC clock frequency at 400MHz +DATA 4 0x021b085c 0x1b4700c7 //LPDDR2 ZQ params +DATA 4 0x021b485c 0x1b4700c7 //LPDDR2 ZQ params + +//============================================================================= +// Calibration setup. +// +//============================================================================= +DATA 4 0x021b0800 0xa1390003 // DDR_PHY_P0_MPZQHWCTRL, enable one time ZQ calibration +DATA 4 0x021b4800 0xa1380003 // DDR_PHY_P1_MPZQHWCTRL + +DATA 4 0x021b0890 0x00400000 //ca bus abs delay +DATA 4 0x021b4890 0x00400000 //ca bus abs delay + +//DATA 4 0x021b48bc0x00055555 // DDR_PHY_P1_MPWRCADL + +DATA 4 0x021b08b8 0x00000800 //frc_msr. +DATA 4 0x021b48b8 0x00000800 //frc_msr. + +// read delays, settings recommended by design to remain constant +DATA 4 0x021b081c 0x33333333 // DDR_PHY_P0_MPREDQBY0DL3 +DATA 4 0x021b0820 0x33333333 // DDR_PHY_P0_MPREDQBY1DL3 +DATA 4 0x021b0824 0x33333333 // DDR_PHY_P0_MPREDQBY2DL3 +DATA 4 0x021b0828 0x33333333 // DDR_PHY_P0_MPREDQBY3DL3 +DATA 4 0x021b481c 0x33333333 // DDR_PHY_P1_MPREDQBY0DL3 +DATA 4 0x021b4820 0x33333333 // DDR_PHY_P1_MPREDQBY1DL3 +DATA 4 0x021b4824 0x33333333 // DDR_PHY_P1_MPREDQBY2DL3 +DATA 4 0x021b4828 0x33333333 // DDR_PHY_P1_MPREDQBY3DL3 + +// write delays, settings recommended by design to remain constant +DATA 4 0x021b082c 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b0830 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b0834 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b0838 0xF3333333 //DDR_PHY_P0 all byte 0 data & dm delayed by 3 +DATA 4 0x021b482c 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 +DATA 4 0x021b4830 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 +DATA 4 0x021b4834 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 +DATA 4 0x021b4838 0xF3333333 //DDR_PHY_P1 all byte 0 data & dm delayed by 3 + +DATA 4 0x021b0848 0x36383644 // MPRDDLCTL PHY0 +DATA 4 0x021b4848 0x3a383846 // MPRDDLCTL PHY1 + +DATA 4 0x021b0850 0x38343E34 // MPWRDLCTL PHY0 +DATA 4 0x021b4850 0x48384A44 // MPWRDLCTL PHY1 + +DATA 4 0x021b083c 0x20000000 //PHY0 dqs gating dis +DATA 4 0x021b0840 0x0 +DATA 4 0x021b483c 0x20000000 //PHY0 dqs gating dis +DATA 4 0x021b4840 0x0 + +//For i.mx6qd parts of versions C and later (v1.2, v1.3). +DATA 4 0x021b08c0 0x24921492 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6 +DATA 4 0x021b48c0 0x24921492 + +DATA 4 0x021b08b8 0x00000800 //frc_msr. +DATA 4 0x021b48b8 0x00000800 //frc_msr. +//============================================================================= +// Calibration setup end +//============================================================================= + +// Channel0 - starting address 0x80000000 +DATA 4 0x021b000c 0x33374133 // MMDC0_MDCFG0 +DATA 4 0x021b0004 0x00020024 // MMDC0_MDPDC +DATA 4 0x021b0010 0x00100A82 // MMDC0_MDCFG1 +DATA 4 0x021b0014 0x00000093 // MMDC0_MDCFG2 + +//MDMISC: RALAT kept to the high level of 5. +//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: +//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3 +//b. Small performence improvment +DATA 4 0x021b0018 0x0000174C // MMDC0_MDMISC +DATA 4 0x021b002c 0x0F9F26D2 // MMDC0_MDRWD +DATA 4 0x021b0030 0x009F0E10 // MMDC0_MDOR +DATA 4 0x021b0038 0x001A0889 // MMDC0_MDCFG3LP +DATA 4 0x021b0008 0x00000000 // MMDC0_MDOTC +DATA 4 0x021b0040 0x0000004F // Chan0 CS0_END 2 channel with 2 Channel fixed mode +// DATA 4 0x021b0400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled +DATA 4 0x021b0000 0x83110000 // MMDC0_MDCTL + +// Channel1 - starting address 0x10000000 +// Note: the values for Chan1 should match those of Chan0 +DATA 4 0x021b400c 0x33374133 // MMDC1_MDCFG0 +DATA 4 0x021b4004 0x00020024 // MMDC1_MDPDC +DATA 4 0x021b4010 0x00100A82 // MMDC1_MDCFG1 +DATA 4 0x021b4014 0x00000093 // MMDC1_MDCFG2 +DATA 4 0x021b4018 0x0000174C // MMDC1_MDMISC +DATA 4 0x021b402c 0x0F9F26D2 // MMDC1_MDRWD +DATA 4 0x021b4030 0x009F0E10 // MMDC1_MDOR +DATA 4 0x021b4038 0x001A0889 // MMDC1_MDCFG3LP +DATA 4 0x021b4008 0x00000000 // MMDC1_MDOTC +DATA 4 0x021b4040 0x00000017 // Chan1 CS0_END +// DATA 4 0x021b4400 0x11420000 //MMDC0_MAARCR ADOPT optimized priorities. Dyn jump disabled +DATA 4 0x021b4000 0x83110000 // MMDC1_MDCTL + +// Precharge all commands per JEDEC +// The memory controller may optionally issue a Precharge-All command +// prior to the MRW Reset command. +// This is strongly recommended to ensure a robust DRAM initialization +DATA 4 0x021b001c 0x00008010 // precharge-all commnad CS0 - Chan 0 +DATA 4 0x021b401c 0x00008010 // precharge-all commnad CS0 - Chan 1 + +//============================================================================= +// LPDDR2 Mode Register Writes +//============================================================================= +// Channel 0 CS0 +DATA 4 0x021b001c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset) +DATA 4 0x021b001c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +DATA 4 0x021b001c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration +DATA 4 0x021b001c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration +DATA 4 0x021b001c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration +// Channel 0 CS1 +// Note, CS1 does not exist in this memory hence these writes are commented out +// They are only shown here for completeness +// If you use a memory where CS1 exists, simply uncomment these lines +//DATA 4 0x021b001c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset) +//DATA 4 0x021b001c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +//DATA 4 0x021b001c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration +//DATA 4 0x021b001c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration +//DATA 4 0x021b001c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration + +// For Channel 1 mode register writes - these should match channel 0 settings +// Channel 1 CS0 +DATA 4 0x021b401c 0x003F8030 // MRW: BA=0 CS=0 MR_ADDR=63 MR_OP=0 (Reset) +DATA 4 0x021b401c 0xFF0A8030 // MRW: BA=0 CS=0 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +DATA 4 0x021b401c 0xC2018030 // MRW: BA=0 CS=0 MR_ADDR=1 MR_OP=see Register Configuration +DATA 4 0x021b401c 0x04028030 // MRW: BA=0 CS=0 MR_ADDR=2 MR_OP=see Register Configuration +DATA 4 0x021b401c 0x03038030 // MRW: BA=0 CS=0 MR_ADDR=3 MR_OP=see Register Configuration +// Channel 1 CS1 +// Note, CS1 does not exist in this memory hence these writes are commented out +// They are only shown here for completeness +// If you use a memory where CS1 exists, simply uncomment these lines +//DATA 4 0x021b401c 0x003F8038 // MRW: BA=0 CS=1 MR_ADDR=63 MR_OP=0 (Reset) +//DATA 4 0x021b401c 0xFF0A8038 // MRW: BA=0 CS=1 MR_ADDR=10 MR_OP=0xff (IO calibration, calibration code) +//DATA 4 0x021b401c 0xC2018038 // MRW: BA=0 CS=1 MR_ADDR=1 MR_OP=see Register Configuration +//DATA 4 0x021b401c 0x04028038 // MRW: BA=0 CS=1 MR_ADDR=2 MR_OP=see Register Configuration +//DATA 4 0x021b401c 0x03038038 // MRW: BA=0 CS=1 MR_ADDR=3 MR_OP=see Register Configuration + +//////////#################################################// +//final DDR setup, before operation start: + +DATA 4 0x021b0020 0x00001800 // MMDC0_MDREF +DATA 4 0x021b4020 0x00001800 // MMDC1_MDREF, align with Chan 0 setting + +DATA 4 0x021b0818 0x0 // DDR_PHY_P0_MPODTCTRL +DATA 4 0x021b4818 0x0 // DDR_PHY_P1_MPODTCTRL + +DATA 4 0x021b08b8 0x00000800 // DDR_PHY_P0_MPMUR0, frc_msr +DATA 4 0x021b48b8 0x00000800 // DDR_PHY_P1_MPMUR0, frc_msr + +DATA 4 0x021b0004 0x00025564 // MMDC0_MDPDC now SDCTL power down enabled +DATA 4 0x021b4004 0x00025564 // MMDC1_MDPDC now SDCTL power down enabled, align with Chan 0 setting + +DATA 4 0x021b0404 0x00011006 //MMDC0_MAPSR ADOPT power down enabled +DATA 4 0x021b4404 0x00011006 //MMDC1_MAPSR ADOPT power down enabled, align with Chan 0 setting + +DATA 4 0x021b001c 0x00000000 // MMDC0_MDSCR, clear this register +DATA 4 0x021b401c 0x00000000 // MMDC1_MDSCR, clear this register + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif +#endif diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index c06fd643677..0c3d1004192 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -14,11 +14,13 @@ #include #include #include +#include #include #include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -33,6 +35,10 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + int dram_init(void) { #if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \ @@ -45,11 +51,24 @@ int dram_init(void) return 0; } +#if defined(CONFIG_MX6DQ_POP_LPDDR2) +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_0; + gd->bd->bi_dram[0].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + + return 0; +} +#endif + iomux_v3_cfg_t const uart4_pads[] = { MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#ifndef CONFIG_DM_MMC iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -61,7 +80,11 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#ifdef CONFIG_MX6DQ_POP_LPDDR2 + MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#else MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +#endif }; iomux_v3_cfg_t const usdhc4_pads[] = { @@ -76,6 +99,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#endif iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -107,27 +131,24 @@ static void setup_iomux_enet(void) } #ifdef CONFIG_FSL_ESDHC_IMX +#ifndef CONFIG_DM_MMC struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, }; -int board_mmc_get_env_dev(int devno) -{ - return devno - 2; -} - int board_mmc_getcd(struct mmc *mmc) { + int ret = 1; +#ifndef CONFIG_MX6DQ_POP_LPDDR2 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; if (cfg->esdhc_base == USDHC3_BASE_ADDR) { gpio_direction_input(IMX_GPIO_NR(6, 11)); ret = !gpio_get_value(IMX_GPIO_NR(6, 11)); } else /* Don't have the CD GPIO pin on board */ ret = 1; - +#endif return ret; } @@ -164,70 +185,61 @@ int board_mmc_init(struct bd_info *bis) return 0; } #endif +#endif #define MII_MMD_ACCESS_CTRL_REG 0xd #define MII_MMD_ACCESS_ADDR_DATA_REG 0xe #define MII_DBG_PORT_REG 0x1d #define MII_DBG_PORT2_REG 0x1e -int fecmxc_mii_postcall(int phy) +static int ar8031_phy_fixup(struct phy_device *phydev) { unsigned short val; - /* - * Due to the i.MX6Q Armadillo2 board HW design,there is - * no 125Mhz clock input from SOC. In order to use RGMII, - * We need enable AR8031 ouput a 125MHz clk from CLK_25M - */ - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7); - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); - miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007); - miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); + /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_CTRL_REG, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_CTRL_REG, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_ADDR_DATA_REG); val &= 0xffe3; val |= 0x18; - miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACCESS_ADDR_DATA_REG, val); - /* For the RGMII phy, we need enable tx clock delay */ - miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5); - miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, MII_DBG_PORT_REG, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_DBG_PORT2_REG); val |= 0x0100; - miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val); - - miiphy_write("FEC", phy, MII_BMCR, 0xa100); + phy_write(phydev, MDIO_DEVAD_NONE, MII_DBG_PORT2_REG, val); return 0; } -int board_eth_init(struct bd_info *bis) +int board_phy_config(struct phy_device *phydev) { - struct eth_device *dev; - int ret = cpu_eth_init(bis); + ar8031_phy_fixup(phydev); - if (ret) - return ret; + if (phydev->drv->config) + phydev->drv->config(phydev); - dev = eth_get_dev_by_name("FEC"); - if (!dev) { - printf("FEC MXC: Unable to get FEC device entry\n"); - return -EINVAL; - } + return 0; +} - ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); - if (ret) { - printf("FEC MXC: Unable to register FEC mii postcall\n"); - return ret; - } +int board_eth_init(struct bd_info *bis) +{ + setup_iomux_enet(); - return 0; + return cpu_eth_init(bis); } #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), }; static void setup_usb(void) @@ -257,11 +269,11 @@ int board_ehci_hcd_init(int port) return 0; } #endif +#endif int board_early_init_f(void) { setup_iomux_uart(); - setup_iomux_enet(); return 0; } @@ -272,7 +284,24 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB setup_usb(); +#else + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 1); +#endif +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); #endif return 0; @@ -288,3 +317,11 @@ int checkboard(void) return 0; } + +#ifdef CONFIG_LDO_BYPASS_CHECK +/* no external pmic, always ldo_enable */ +void ldo_mode_set(int ldo_bypass) +{ + return; +} +#endif diff --git a/board/freescale/mx6qarm2/plugin.S b/board/freescale/mx6qarm2/plugin.S new file mode 100644 index 00000000000..fe697598e36 --- /dev/null +++ b/board/freescale/mx6qarm2/plugin.S @@ -0,0 +1,1176 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +.macro imx6dlarm2_ddr_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00003000 + str r1, [r0, #0x590] + str r1, [r0, #0x598] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00003030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x00370037 + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x422f0220 + str r2, [r0, #0x83c] + ldr r2, =0x021f0219 + str r2, [r0, #0x840] + + ldr r2, =0x422f0220 + str r2, [r1, #0x83c] + ldr r2, =0x022d022f + str r2, [r1, #0x840] + + ldr r2, =0x47494b49 + str r2, [r0, #0x848] + ldr r2, =0x48484c47 + str r2, [r1, #0x848] + + ldr r2, =0x39382b2f + str r2, [r0, #0x850] + ldr r2, =0x2f35312c + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x00000800 + str r2, [r1, #0x8b8] + + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x40445323 + str r2, [r0, #0x00c] + ldr r2, =0xb66e8c63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00081740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00440e21 + str r2, [r0, #0x030] + +#ifdef CONFIG_DDR_32BIT + ldr r2, =0x00000017 + str r2, [r0, #0x040] + ldr r2, =0xc3190000 + str r2, [r0, #0x000] +#else + ldr r2, =0x00000027 + str r2, [r0, #0x040] + ldr r2, =0xc31a0000 + str r2, [r0, #0x000] +#endif + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x0400803a + str r2, [r0, #0x01c] + + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x0000803b + str r2, [r0, #0x01c] + + ldr r2, =0x00428031 + str r2, [r0, #0x01c] + ldr r2, =0x00428039 + str r2, [r0, #0x01c] + + ldr r2, =0x07208030 + str r2, [r0, #0x01c] + ldr r2, =0x07208038 + str r2, [r0, #0x01c] + + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x04008048 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + + ldr r2, =0x00000007 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0x0002556d + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r1, #0x004] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dqarm2_ddr_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + ldr r1, =0x00000030 + str r1, [r0, #0x594] + + ldr r1, =0x00000030 + str r1, [r0, #0x56c] + ldr r1, =0x00000030 + str r1, [r0, #0x578] + ldr r1, =0x00000030 + str r1, [r0, #0x74c] + + ldr r1, =0x00000030 + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + ldr r1, =0x00000030 + str r1, [r0, #0x5a0] + ldr r1, =0x00000030 + str r1, [r0, #0x78c] + + ldr r1, =0x00000000 + str r1, [r0, #0x750] + + ldr r1, =0x00000038 + str r1, [r0, #0x5a8] + ldr r1, =0x00000038 + str r1, [r0, #0x5b0] + ldr r1, =0x00000038 + str r1, [r0, #0x524] + ldr r1, =0x00000038 + str r1, [r0, #0x51c] + ldr r1, =0x00000038 + str r1, [r0, #0x518] + ldr r1, =0x00000038 + str r1, [r0, #0x50c] + ldr r1, =0x00000038 + str r1, [r0, #0x5b8] + ldr r1, =0x00000038 + str r1, [r0, #0x5c0] + + ldr r1, =0x00000000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + ldr r1, =0x00000030 + str r1, [r0, #0x788] + ldr r1, =0x00000030 + str r1, [r0, #0x794] + ldr r1, =0x00000030 + str r1, [r0, #0x79c] + ldr r1, =0x00000030 + str r1, [r0, #0x7a0] + ldr r1, =0x00000030 + str r1, [r0, #0x7a4] + ldr r1, =0x00000030 + str r1, [r0, #0x7a8] + ldr r1, =0x00000030 + str r1, [r0, #0x748] + + ldr r1, =0x00000030 + str r1, [r0, #0x5ac] + ldr r1, =0x00000030 + str r1, [r0, #0x5b4] + ldr r1, =0x00000030 + str r1, [r0, #0x528] + ldr r1, =0x00000030 + str r1, [r0, #0x520] + ldr r1, =0x00000030 + str r1, [r0, #0x514] + ldr r1, =0x00000030 + str r1, [r0, #0x510] + ldr r1, =0x00000030 + str r1, [r0, #0x5bc] + ldr r1, =0x00000030 + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + ldr r2, =0x001F001F + str r2, [r0, #0x810] + + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00440044 + str r2, [r1, #0x80c] + ldr r2, =0x00440044 + str r2, [r1, #0x810] + + ldr r2, =0x4333033F + str r2, [r0, #0x83c] + ldr r2, =0x0339033E + str r2, [r0, #0x840] + ldr r2, =0x433F0343 + str r2, [r1, #0x83c] + ldr r2, =0x03490320 + str r2, [r1, #0x840] + + ldr r2, =0x42363838 + str r2, [r0, #0x848] + ldr r2, =0x3F343242 + str r2, [r1, #0x848] + + ldr r2, =0x37424844 + str r2, [r0, #0x850] + ldr r2, =0x48264731 + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + ldr r2, =0x33333333 + str r2, [r0, #0x820] + ldr r2, =0x33333333 + str r2, [r0, #0x824] + ldr r2, =0x33333333 + str r2, [r0, #0x828] + ldr r2, =0x33333333 + str r2, [r1, #0x81c] + ldr r2, =0x33333333 + str r2, [r1, #0x820] + ldr r2, =0x33333333 + str r2, [r1, #0x824] + ldr r2, =0x33333333 + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x00000800 + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + ldr r2, =0x555A7975 + str r2, [r0, #0x00c] + ldr r2, =0xFF538F64 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00081740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005a1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x11420000 + str r2, [r0, #0x400] + ldr r2, =0x11420000 + str r2, [r1, #0x400] + + ldr r2, =0xc31a0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x0408803a + str r2, [r0, #0x01c] + + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x0000803b + str r2, [r0, #0x01c] + + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x00048039 + str r2, [r0, #0x01c] + + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x09408038 + str r2, [r0, #0x01c] + + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x04008048 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dlarm2_lpddr2_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00003028 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00000038 + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x494] + str r1, [r0, #0x4a4] + str r1, [r0, #0x4a8] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + ldr r1, =0x00000038 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x74c] + str r1, [r0, #0x76c] + ldr r1, =0x00020000 + str r1, [r0, #0x750] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + ldr r1, =0x00020000 + str r1, [r0, #0x760] + ldr r1, =0x00080000 + str r1, [r0, #0x774] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + ldr r2, =0x1b5f01ff + str r2, [r0, #0x85c] + str r2, [r1, #0x85c] + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00400000 + str r2, [r0, #0x890] + str r2, [r1, #0x890] + ldr r2, =0x00055555 + str r2, [r1, #0x8bc] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x4b4b524f + str r2, [r0, #0x848] + ldr r2, =0x494f4c44 + str r2, [r1, #0x848] + + ldr r2, =0x3c3d303c + str r2, [r0, #0x850] + ldr r2, =0x3c343d38 + str r2, [r1, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + str r2, [r1, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + str r2, [r1, #0x840] + + ldr r2, =0x00000a00 + str r2, [r0, #0x858] + str r2, [r1, #0x858] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x34386145 + str r2, [r0, #0xc] + ldr r2, =0x00020036 + str r2, [r0, #0x4] + ldr r2, =0x00100c83 + str r2, [r0, #0x10] + ldr r2, =0x000000Dc + str r2, [r0, #0x14] + ldr r2, =0x0000174C + str r2, [r0, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x2c] + ldr r2, =0x0000020e + str r2, [r0, #0x30] + ldr r2, =0x00190778 + str r2, [r0, #0x38] + ldr r2, =0x00000000 + str r2, [r0, #0x8] + + ldr r2, =0x0000005f + str r2, [r0, #0x40] + ldr r2, =0x0000000f + str r2, [r0, #0x404] + + ldr r2, =0xc3010000 + str r2, [r0, #0x0] + + ldr r2, =0x34386145 + str r2, [r1, #0xc] + + ldr r2, =0x00020036 + str r2, [r1, #0x4] + ldr r2, =0x00100c83 + str r2, [r1, #0x10] + ldr r2, =0x000000Dc + str r2, [r1, #0x14] + ldr r2, =0x0000174C + str r2, [r1, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r1, #0x2c] + ldr r2, =0x0000020e + str r2, [r1, #0x30] + ldr r2, =0x00190778 + str r2, [r1, #0x38] + ldr r2, =0x00000000 + str r2, [r1, #0x8] + + ldr r2, =0x0000003f + str r2, [r1, #0x40] + + ldr r2, =0xc3010000 + str r2, [r1, #0x0] + + ldr r2, =0x003f8030 + str r2, [r0, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x1c] + ldr r2, =0xa2018030 + str r2, [r0, #0x1c] + ldr r2, =0x06028030 + str r2, [r0, #0x1c] + ldr r2, =0x01038030 + str r2, [r0, #0x1c] + + ldr r2, =0x003f8030 + str r2, [r1, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r1, #0x1c] + ldr r2, =0xa2018030 + str r2, [r1, #0x1c] + ldr r2, =0x06028030 + str r2, [r1, #0x1c] + ldr r2, =0x01038030 + str r2, [r1, #0x1c] + + ldr r2, =0x00005800 + str r2, [r0, #0x20] + str r2, [r1, #0x20] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00000000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + ldr r1, =0x007F007F + str r1, [r0, #0x18] + ldr r1, =0x007F007F + str r1, [r0, #0x1c] +.endm + +.macro imx6dqarm2_lpddr2_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x60324 + str r1, [r0, #0x18] + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00003038 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00000038 + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x57c] + str r1, [r0, #0x590] + str r1, [r0, #0x598] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + ldr r1, =0x00000038 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x74c] + ldr r1, =0x00020000 + str r1, [r0, #0x750] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + ldr r1, =0x00020000 + str r1, [r0, #0x774] + ldr r1, =0x00000038 + str r1, [r0, #0x78c] + ldr r1, =0x00080000 + str r1, [r0, #0x798] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + ldr r2, =0x1b5f01ff + str r2, [r0, #0x85c] + str r2, [r1, #0x85c] + ldr r2, =0xa1390000 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + ldr r2, =0x00400000 + str r2, [r0, #0x890] + str r2, [r1, #0x890] + ldr r2, =0x00055555 + str r2, [r1, #0x8bc] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0xf3333333 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + str r2, [r1, #0x82c] + str r2, [r1, #0x830] + str r2, [r1, #0x834] + str r2, [r1, #0x838] + + ldr r2, =0x49383b39 + str r2, [r0, #0x848] + ldr r2, =0x30364738 + str r2, [r0, #0x850] + + ldr r2, =0x3e3c3846 + str r2, [r1, #0x848] + ldr r2, =0x4c294b35 + str r2, [r1, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + str r2, [r1, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + str r2, [r1, #0x840] + + ldr r2, =0x00000f00 + str r2, [r0, #0x858] + str r2, [r1, #0x858] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x555a61a5 + str r2, [r0, #0xc] + ldr r2, =0x00020036 + str r2, [r0, #0x4] + ldr r2, =0x00160e83 + str r2, [r0, #0x10] + ldr r2, =0x000000dd + str r2, [r0, #0x14] + ldr r2, =0x0008174C + str r2, [r0, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x2c] + ldr r2, =0x0000020e + str r2, [r0, #0x30] + ldr r2, =0x200aac + str r2, [r0, #0x38] + ldr r2, =0x00000000 + str r2, [r0, #0x8] + + ldr r2, =0x0000005f + str r2, [r0, #0x40] + + ldr r2, =0xc3010000 + str r2, [r0, #0x0] + + ldr r2, =0x555a61a5 + str r2, [r1, #0xc] + ldr r2, =0x00020036 + str r2, [r1, #0x4] + ldr r2, =0x00160e83 + str r2, [r1, #0x10] + ldr r2, =0x000000dd + str r2, [r1, #0x14] + ldr r2, =0x0008174C + str r2, [r1, #0x18] + ldr r2, =0x0f9f26d2 + str r2, [r1, #0x2c] + ldr r2, =0x0000020e + str r2, [r1, #0x30] + ldr r2, =0x00200aac + str r2, [r1, #0x38] + ldr r2, =0x00000000 + str r2, [r1, #0x8] + + ldr r2, =0x0000003f + str r2, [r1, #0x40] + + ldr r2, =0xc3010000 + str r2, [r1, #0x0] + + ldr r2, =0x003f8030 + str r2, [r0, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x1c] + ldr r2, =0xc2018030 + str r2, [r0, #0x1c] + ldr r2, =0x06028030 + str r2, [r0, #0x1c] + ldr r2, =0x02038030 + str r2, [r0, #0x1c] + + ldr r2, =0x003f8030 + str r2, [r1, #0x1c] + ldr r2, =0xff0a8030 + str r2, [r1, #0x1c] + ldr r2, =0xc2018030 + str r2, [r1, #0x1c] + ldr r2, =0x06028030 + str r2, [r1, #0x1c] + ldr r2, =0x02038030 + str r2, [r1, #0x1c] + + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + + ldr r2, =0x00007800 + str r2, [r0, #0x20] + str r2, [r1, #0x20] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + str r2, [r1, #0x800] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00000000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + + ldr r2, =0x00011006 + str r2, [r0, #0x404] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + ldr r1, =0x007F007F + str r1, [r0, #0x18] + ldr r1, =0x007F007F + str r1, [r0, #0x1c] +.endm + +.macro imx6dq_pop_arm2_lpddr2_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + ldr r1, =0xffffffff + str r1, [r0, #0x06c] + ldr r1, =0xffffffff + str r1, [r0, #0x070] + ldr r1, =0xffffffff + str r1, [r0, #0x074] + ldr r1, =0xffffffff + str r1, [r0, #0x078] + ldr r1, =0xffffffff + str r1, [r0, #0x07c] + ldr r1, =0xffffffff + str r1, [r0, #0x080] + ldr r1, =0xffffffff + str r1, [r0, #0x084] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + str r1, [r0, #0x58c] + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + ldr r1, =0x00003030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + ldr r2, =0x1B5F0107 + str r2, [r0, #0x85c] + str r2, [r1, #0x85c] + ldr r2, =0xA1390003 + str r2, [r0, #0x800] + ldr r2, =0x00400000 + str r2, [r0, #0x890] + str r2, [r1, #0x890] + ldr r2, =0x3C3A3A44 + str r2, [r0, #0x848] + str r2, [r1, #0x848] + ldr r2, =0x4238423A + str r2, [r0, #0x850] + str r2, [r1, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + ldr r2, =0x20000000 + str r2, [r1, #0x83c] + ldr r2, =0x00000000 + str r2, [r1, #0x840] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0xf3333333 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + str r2, [r1, #0x82c] + str r2, [r1, #0x830] + str r2, [r1, #0x834] + str r2, [r1, #0x838] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x4] + ldr r2, =0x00000000 + str r2, [r0, #0x8] + ldr r2, =0x444961A5 + str r2, [r0, #0xc] + ldr r2, =0x00160E83 + str r2, [r0, #0x10] + ldr r2, =0x000000DD + str r2, [r0, #0x14] + + ldr r2, =0x0000174C + str r2, [r0, #0x18] + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + ldr r2, =0x149F26D2 + str r2, [r0, #0x2c] + ldr r2, =0x00000010 + str r2, [r0, #0x30] + ldr r2, =0x0021099B + str r2, [r0, #0x38] + ldr r2, =0x0000004F + str r2, [r0, #0x40] + ldr r2, =0x11420000 + str r2, [r0, #0x400] + ldr r2, =0x83110000 + str r2, [r0, #0x0] + + ldr r2, =0x00020036 + str r2, [r1, #0x4] + ldr r2, =0x00000000 + str r2, [r1, #0x8] + ldr r2, =0x444961A5 + str r2, [r1, #0xc] + ldr r2, =0x00160E83 + str r2, [r1, #0x10] + ldr r2, =0x000000DD + str r2, [r1, #0x14] + + ldr r2, =0x0000174C + str r2, [r1, #0x18] + ldr r2, =0x00008000 + str r2, [r1, #0x1c] + ldr r2, =0x149F26D2 + str r2, [r1, #0x2c] + ldr r2, =0x00000010 + str r2, [r1, #0x30] + ldr r2, =0x0021099B + str r2, [r1, #0x38] + ldr r2, =0x00000017 + str r2, [r1, #0x40] + ldr r2, =0x11420000 + str r2, [r1, #0x400] + ldr r2, =0x83110000 + str r2, [r1, #0x0] + + ldr r2, =0x003F8030 + str r2, [r0, #0x1c] + ldr r2, =0xFF0A8030 + str r2, [r0, #0x1c] + ldr r2, =0xC2018030 + str r2, [r0, #0x1c] + ldr r2, =0x06028030 + str r2, [r0, #0x1c] + ldr r2, =0x02038030 + str r2, [r0, #0x1c] + + ldr r2, =0x003F8030 + str r2, [r1, #0x1c] + ldr r2, =0xFF0A8030 + str r2, [r1, #0x1c] + ldr r2, =0xC2018030 + str r2, [r1, #0x1c] + ldr r2, =0x06028030 + str r2, [r1, #0x1c] + ldr r2, =0x02038030 + str r2, [r1, #0x1c] + + ldr r2, =0xA1390003 + str r2, [r0, #0x800] + + ldr r2, =0x00001800 + str r2, [r0, #0x20] + str r2, [r1, #0x20] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + + ldr r2, =0x00025576 + str r2, [r0, #0x4] + str r2, [r1, #0x4] + + ldr r2, =0x00011006 + str r2, [r0, #0x404] + str r2, [r1, #0x404] + + ldr r2, =0x00000000 + str r2, [r0, #0x1c] + str r2, [r1, #0x1c] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + ldr r1, =0x007F007F + str r1, [r0, #0x18] + ldr r1, =0x007F007F + str r1, [r0, #0x1c] +.endm + +.macro imx6_ddr_setting + #if defined (CONFIG_MX6DQ_POP_LPDDR2) + imx6dq_pop_arm2_lpddr2_setting + #elif defined (CONFIG_MX6DQ_LPDDR2) + imx6dqarm2_lpddr2_setting + #elif defined (CONFIG_MX6Q) + imx6dqarm2_ddr_setting + #elif defined (CONFIG_MX6DL_LPDDR2) + imx6dlarm2_lpddr2_setting + #elif defined (CONFIG_MX6DL) + imx6dlarm2_ddr_setting + #else + #error "SOC not configured" + #endif +.endm + +.macro imx6_clock_gating +.endm + +.macro imx6_qos_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sabreauto/Kconfig b/board/freescale/mx6sabreauto/Kconfig index 5b4faf6d5fd..0486b5e9453 100644 --- a/board/freescale/mx6sabreauto/Kconfig +++ b/board/freescale/mx6sabreauto/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MX6SABREAUTO +if TARGET_MX6SABREAUTO || TARGET_MX6SABREAUTO_COMMON config SYS_BOARD default "mx6sabreauto" @@ -9,4 +9,12 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sabreauto" +config SYS_TEXT_BASE + default 0x17800000 + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. endif diff --git a/board/freescale/mx6sabreauto/imximage.cfg b/board/freescale/mx6sabreauto/imximage.cfg new file mode 100644 index 00000000000..4b4d360d833 --- /dev/null +++ b/board/freescale/mx6sabreauto/imximage.cfg @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000028 +DATA 4 0x020e05b0 0x00000028 +DATA 4 0x020e0524 0x00000028 +DATA 4 0x020e051c 0x00000028 +DATA 4 0x020e0518 0x00000028 +DATA 4 0x020e050c 0x00000028 +DATA 4 0x020e05b8 0x00000028 +DATA 4 0x020e05c0 0x00000028 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000028 +DATA 4 0x020e0788 0x00000028 +DATA 4 0x020e0794 0x00000028 +DATA 4 0x020e079c 0x00000028 +DATA 4 0x020e07a0 0x00000028 +DATA 4 0x020e07a4 0x00000028 +DATA 4 0x020e07a8 0x00000028 +DATA 4 0x020e0748 0x00000028 +DATA 4 0x020e05ac 0x00000028 +DATA 4 0x020e05b4 0x00000028 +DATA 4 0x020e0528 0x00000028 +DATA 4 0x020e0520 0x00000028 +DATA 4 0x020e0514 0x00000028 +DATA 4 0x020e0510 0x00000028 +DATA 4 0x020e05bc 0x00000028 +DATA 4 0x020e05c4 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x43260335 +DATA 4 0x021b0840 0x031A030B +DATA 4 0x021b483c 0x4323033B +DATA 4 0x021b4840 0x0323026F +DATA 4 0x021b0848 0x483D4545 +DATA 4 0x021b4848 0x44433E48 +DATA 4 0x021b0850 0x41444840 +DATA 4 0x021b4850 0x4835483E +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x8A8F7955 +DATA 4 0x021b0010 0xFF328F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008F1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFF000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000F3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/freescale/mx6sabreauto/mx6dl.cfg b/board/freescale/mx6sabreauto/mx6dl.cfg new file mode 100644 index 00000000000..41a8bbcd2de --- /dev/null +++ b/board/freescale/mx6sabreauto/mx6dl.cfg @@ -0,0 +1,158 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000028 +DATA 4 0x020e04c0 0x00000028 +DATA 4 0x020e04c4 0x00000028 +DATA 4 0x020e04c8 0x00000028 +DATA 4 0x020e04cc 0x00000028 +DATA 4 0x020e04d0 0x00000028 +DATA 4 0x020e04d4 0x00000028 +DATA 4 0x020e04d8 0x00000028 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000028 +DATA 4 0x020e0770 0x00000028 +DATA 4 0x020e0778 0x00000028 +DATA 4 0x020e077c 0x00000028 +DATA 4 0x020e0780 0x00000028 +DATA 4 0x020e0784 0x00000028 +DATA 4 0x020e078c 0x00000028 +DATA 4 0x020e0748 0x00000028 +DATA 4 0x020e0470 0x00000028 +DATA 4 0x020e0474 0x00000028 +DATA 4 0x020e0478 0x00000028 +DATA 4 0x020e047c 0x00000028 +DATA 4 0x020e0480 0x00000028 +DATA 4 0x020e0484 0x00000028 +DATA 4 0x020e0488 0x00000028 +DATA 4 0x020e048c 0x00000028 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x42190217 +DATA 4 0x021b0840 0x017B017B +DATA 4 0x021b483c 0x4176017B +DATA 4 0x021b4840 0x015F016C +DATA 4 0x021b0848 0x4C4C4D4C +DATA 4 0x021b4848 0x4A4D4C48 +DATA 4 0x021b0850 0x3F3F3F40 +DATA 4 0x021b4850 0x3538382E +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020025 +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676B5313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006B1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025565 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFF000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0xFFFFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/freescale/mx6sabreauto/mx6qp.cfg b/board/freescale/mx6sabreauto/mx6qp.cfg new file mode 100644 index 00000000000..120d70df7ab --- /dev/null +++ b/board/freescale/mx6sabreauto/mx6qp.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ +/* image version */ + +#define __ASSEMBLY__ +#include + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001b001e +DATA 4 0x021b0810 0x002e0029 +DATA 4 0x021b480c 0x001b002a +DATA 4 0x021b4810 0x0019002c +DATA 4 0x021b083c 0x43240334 +DATA 4 0x021b0840 0x0324031a +DATA 4 0x021b483c 0x43340344 +DATA 4 0x021b4840 0x03280276 +DATA 4 0x021b0848 0x44383A3E +DATA 4 0x021b4848 0x3C3C3846 +DATA 4 0x021b0850 0x2e303230 +DATA 4 0x021b4850 0x38283E34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08c0 0x24912249 +DATA 4 0x021b48c0 0x24914289 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x24444040 +DATA 4 0x021b000c 0x898E7955 +DATA 4 0x021b0010 0xFF320F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 + +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x008E1023 +DATA 4 0x021b0040 0x00000047 +DATA 4 0x021b0400 0x14420000 +DATA 4 0x021b0000 0x841A0000 +DATA 4 0x021b0890 0x00400C58 +DATA 4 0x00bb0008 0x00000000 +DATA 4 0x00bb000c 0x2891E41A +DATA 4 0x00bb0038 0x00000564 +DATA 4 0x00bb0014 0x00000040 +DATA 4 0x00bb0028 0x00000020 +DATA 4 0x00bb002c 0x00000020 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 +#endif diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c index e92ef26d0ad..d1b9e01aba6 100644 --- a/board/freescale/mx6sabreauto/mx6sabreauto.c +++ b/board/freescale/mx6sabreauto/mx6sabreauto.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Author: Fabio Estevam */ @@ -35,6 +36,12 @@ #include #include #include "../common/pfuze.h" +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -46,6 +53,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) +/*Need more drive strength for SD1 slot on base board*/ +#define USDHC1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) @@ -60,10 +72,18 @@ DECLARE_GLOBAL_DATA_PTR; #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + #define I2C_PMIC 1 int dram_init(void) @@ -78,30 +98,17 @@ static iomux_v3_cfg_t const uart4_pads[] = { IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; - +#ifdef CONFIG_SYS_I2C /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */ -static struct i2c_pads_info mx6q_i2c_pad_info1 = { +static struct i2c_pads_info i2c_pad_info1 = { .scl = { - .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC, + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, .gp = IMX_GPIO_NR(2, 30) }, .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC, - .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC, - .gp = IMX_GPIO_NR(2, 30) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, .gp = IMX_GPIO_NR(4, 13) } }; @@ -111,36 +118,20 @@ static struct i2c_pads_info mx6dl_i2c_pad_info1 = { * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor, * Compass Sensor, Accelerometer, Res Touch */ -static struct i2c_pads_info mx6q_i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, - .gp = IMX_GPIO_NR(1, 3) - }, - .sda = { - .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - -static struct i2c_pads_info mx6dl_i2c_pad_info2 = { +static struct i2c_pads_info i2c_pad_info2 = { .scl = { - .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, - .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC, .gp = IMX_GPIO_NR(1, 3) }, .sda = { - .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC, + .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, .gp = IMX_GPIO_NR(3, 18) } }; #endif - -static iomux_v3_cfg_t const i2c3_pads[] = { - IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), -}; +#endif static iomux_v3_cfg_t const port_exp[] = { IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -236,15 +227,48 @@ static void eim_clk_setup(void) static void setup_iomux_eimnor(void) { + int ret; + struct gpio_desc desc; + SETUP_IOMUX_PADS(eimnor_pads); - gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + ret = dm_gpio_lookup_name("GPIO5_4", &desc); + if (ret) { + printf("%s lookup GPIO5_4 failed ret = %d\n", __func__, ret); + return; + } + ret = dm_gpio_request(&desc, "steer ctrl"); + if (ret) { + printf("%s request steer logic failed ret = %d\n", __func__, ret); + return; + } + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); eimnor_cs_setup(); } #endif +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart4_pads); +} + +#ifdef CONFIG_FSL_ESDHC_IMX +#if !CONFIG_IS_ENABLED(DM_MMC) +static iomux_v3_cfg_t const usdhc1_pads[] = { + /*To avoid pin conflict with NAND, set usdhc1 to 4 pins*/ + IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC1_PAD_CTRL)), + + /*CD pin*/ + IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), @@ -260,30 +284,71 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; -static void setup_iomux_uart(void) -{ - SETUP_IOMUX_PADS(uart4_pads); -} +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1) +#define USDHC3_CD_GPIO IMX_GPIO_NR(6, 15) -#ifdef CONFIG_FSL_ESDHC_IMX -static struct fsl_esdhc_cfg usdhc_cfg[1] = { +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 4}, {USDHC3_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { - gpio_direction_input(IMX_GPIO_NR(6, 15)); - return !gpio_get_value(IMX_GPIO_NR(6, 15)); + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + gpio_direction_input(USDHC1_CD_GPIO); + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + gpio_direction_input(USDHC3_CD_GPIO); + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; } int board_mmc_init(struct bd_info *bis) { - SETUP_IOMUX_PADS(usdhc3_pads); + int i; - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; } #endif +#endif #ifdef CONFIG_NAND_MXS static iomux_v3_cfg_t gpmi_pads[] = { @@ -321,6 +386,24 @@ static void setup_gpmi_nand(void) } #endif +static void setup_fec(void) +{ + int ret; + + if (is_mx6dqp()) { + /* + * select ENET MAC0 TX clock from PLL + */ + imx_iomux_set_gpr_register(5, 9, 1, 1); + } else { + imx_iomux_set_gpr_register(1, 21, 1, 1); + } + + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + printf("Error fec anatop clock settings!\n"); +} + u32 get_board_rev(void) { int rev = nxp_board_rev(); @@ -401,7 +484,7 @@ struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, + .detect = NULL, .enable = do_enable_hdmi, .mode = { .name = "HDMI", @@ -426,8 +509,22 @@ iomux_v3_cfg_t const backlight_pads[] = { static void setup_iomux_backlight(void) { - gpio_request(IMX_GPIO_NR(2, 9), "backlight"); - gpio_direction_output(IMX_GPIO_NR(2, 9), 1); + int ret; + struct gpio_desc desc; + + ret = dm_gpio_lookup_name("GPIO2_9", &desc); + if (ret) { + printf("%s lookup GPIO2_9 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "backlight"); + if (ret) { + printf("%s request backlight failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); SETUP_IOMUX_PADS(backlight_pads); } @@ -495,6 +592,37 @@ int overwrite_console(void) return 1; } +#ifdef CONFIG_MXC_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), + /* Steer logic */ + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +void setup_spinor(void) +{ + int ret; + struct gpio_desc desc; + + SETUP_IOMUX_PADS(ecspi1_pads); + + ret = dm_gpio_lookup_name("GPIO5_4", &desc); + if (ret) { + printf("%s lookup GPIO5_4 failed ret = %d\n", __func__, ret); + return; + } + ret = dm_gpio_request(&desc, "steer ctrl"); + if (ret) { + printf("%s request steer logic failed ret = %d\n", __func__, ret); + return; + } + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -511,64 +639,262 @@ int board_early_init_f(void) int board_init(void) { + int ret; + struct gpio_desc desc; + /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_SYS_I2C /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */ - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - else - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); - /* I2C 3 Steer */ - gpio_request(IMX_GPIO_NR(5, 4), "steer logic"); - gpio_direction_output(IMX_GPIO_NR(5, 4), 1); - SETUP_IOMUX_PADS(i2c3_pads); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #ifndef CONFIG_SYS_FLASH_CFI - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); - else - setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); #endif - gpio_request(IMX_GPIO_NR(1, 15), "expander en"); - gpio_direction_output(IMX_GPIO_NR(1, 15), 1); +#endif + + ret = dm_gpio_lookup_name("GPIO1_15", &desc); + if (ret) { + printf("%s lookup GPIO1_15 failed ret = %d\n", __func__, ret); + return -ENODEV; + } + ret = dm_gpio_request(&desc, "expander en"); + if (ret) { + printf("%s request steer logic failed ret = %d\n", __func__, ret); + return -ENODEV; + } + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); SETUP_IOMUX_PADS(port_exp); #ifdef CONFIG_VIDEO_IPUV3 setup_display(); #endif +#ifdef CONFIG_MXC_SPI + setup_spinor(); +#endif + #ifdef CONFIG_MTD_NOR_FLASH setup_iomux_eimnor(); #endif - return 0; -} -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; -} +#ifdef CONFIG_FEC_MXC + setup_fec(); #endif + return 0; +} + +#ifdef CONFIG_POWER int power_init_board(void) { - struct pmic *p; + struct pmic *pfuze; unsigned int value; + int ret; - p = pfuze_common_init(I2C_PMIC); - if (!p) + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) return -ENODEV; + if (is_mx6dqp()) + ret = pfuze_mode_init(pfuze, APS_APS); + else + ret = pfuze_mode_init(pfuze, APS_PFM); + + if (ret < 0) + return ret; + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); + value &= ~0x3f; + value |= 0x1f; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); + /* set SW2 staby volatage 0.975V*/ - pmic_reg_read(p, PFUZE100_SW2STBY, &value); + pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value); value &= ~0x3f; value |= 0x17; - pmic_reg_write(p, PFUZE100_SW2STBY, value); + pmic_reg_write(pfuze, PFUZE100_SW2STBY, value); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW2CONF, value); + } else { + /* set SW1AB staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* set SW1C staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); + value &= ~0x3f; + value |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); + } + + return 0; +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + unsigned int reg; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + if (is_mx6dqp()) + ret = pfuze_mode_init(dev, APS_APS); + else + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW2STBY); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(dev, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW2CONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); } - return pfuze_mode_init(p, APS_PFM); + return 0; } +#endif + +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x29; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } + /* increase VDDSOC to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + } +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29); + } else { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d); + } + /* increase VDDSOC to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d); + } +} +#endif +#endif #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { @@ -584,6 +910,11 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "SABREAUTO"); @@ -595,6 +926,10 @@ int board_late_init(void) env_set("board_rev", "MX6DL"); #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + return 0; } @@ -626,6 +961,49 @@ int board_ehci_hcd_init(int port) } #endif +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY + +iomux_v3_cfg_t const recovery_key_pads[] = { + IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + int ret; + struct gpio_desc desc; + + /* Check Recovery Combo Button press or not. */ + SETUP_IOMUX_PADS(recovery_key_pads); + + ret = dm_gpio_lookup_name("GPIO5_14", &desc); + if (ret) { + printf("%s lookup GPIO5_14 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "volume_dn_key"); + if (ret) { + printf("%s request volume_dn_key failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + if (dm_gpio_get_value(&desc) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#endif /*CONFIG_FSL_FASTBOOT*/ + + #ifdef CONFIG_SPL_BUILD #include #include diff --git a/board/freescale/mx6sabreauto/mx6solo.cfg b/board/freescale/mx6sabreauto/mx6solo.cfg new file mode 100644 index 00000000000..956d5464416 --- /dev/null +++ b/board/freescale/mx6sabreauto/mx6solo.cfg @@ -0,0 +1,134 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of spi, sd, eimnor, nand, sata: + * spinor: flash_offset: 0x0400 + * nand: flash_offset: 0x0400 + * sata: flash_offset: 0x0400 + * sd/mmc: flash_offset: 0x0400 + * eimnor: flash_offset: 0x1000 + */ + +#if defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else /* others has the same flash_offset as sd */ +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4, 0x020e0774, 0x000C0000 +DATA 4, 0x020e0754, 0x00000000 +DATA 4, 0x020e04ac, 0x00000030 +DATA 4, 0x020e04b0, 0x00000030 +DATA 4, 0x020e0464, 0x00000030 +DATA 4, 0x020e0490, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e0494, 0x00000030 +DATA 4, 0x020e04a0, 0x00000000 +DATA 4, 0x020e04b4, 0x00000030 +DATA 4, 0x020e04b8, 0x00000030 +DATA 4, 0x020e076c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e04bc, 0x00000028 +DATA 4, 0x020e04c0, 0x00000028 +DATA 4, 0x020e04c4, 0x00000028 +DATA 4, 0x020e04c8, 0x00000028 +DATA 4, 0x020e0760, 0x00020000 +DATA 4, 0x020e0764, 0x00000028 +DATA 4, 0x020e0770, 0x00000028 +DATA 4, 0x020e0778, 0x00000028 +DATA 4, 0x020e077c, 0x00000028 +DATA 4, 0x020e0470, 0x00000028 +DATA 4, 0x020e0474, 0x00000028 +DATA 4, 0x020e0478, 0x00000028 +DATA 4, 0x020e047c, 0x00000028 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b083c, 0x421C0216 +DATA 4, 0x021b0840, 0x017B017A +DATA 4, 0x021b0848, 0x4B4A4E4C +DATA 4, 0x021b0850, 0x3F3F3334 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020025 +DATA 4, 0x021b0008, 0x00333030 +DATA 4, 0x021b000c, 0x676B5313 +DATA 4, 0x021b0010, 0xB66E8B63 +DATA 4, 0x021b0014, 0x01FF00DB +DATA 4, 0x021b0018, 0x00001740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x006B1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0000, 0x84190000 +DATA 4, 0x021b001c, 0x04008032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x05208030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b0004, 0x00025565 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0xFFFFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x00000FFF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif diff --git a/board/freescale/mx6sabreauto/plugin.S b/board/freescale/mx6sabreauto/plugin.S new file mode 100644 index 00000000000..6301ae1990f --- /dev/null +++ b/board/freescale/mx6sabreauto/plugin.S @@ -0,0 +1,675 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6dqpsabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001b001e + str r2, [r0, #0x80c] + ldr r2, =0x002e0029 + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x001b002a + str r2, [r1, #0x80c] + ldr r2, =0x0019002c + str r2, [r1, #0x810] + + ldr r2, =0x43240334 + str r2, [r0, #0x83c] + ldr r2, =0x0324031a + str r2, [r0, #0x840] + + ldr r2, =0x43340344 + str r2, [r1, #0x83c] + ldr r2, =0x03280276 + str r2, [r1, #0x840] + + ldr r2, =0x44383A3E + str r2, [r0, #0x848] + ldr r2, =0x3C3C3846 + str r2, [r1, #0x848] + + ldr r2, =0x2e303230 + str r2, [r0, #0x850] + ldr r2, =0x38283E34 + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x24912249 + str r2, [r0, #0x8c0] + ldr r2, =0x24914289 + str r2, [r1, #0x8c0] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x24444040 + str r2, [r0, #0x008] + + ldr r2, =0x898E7955 + str r2, [r0, #0x00c] + ldr r2, =0xFF320F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x008E1023 + str r2, [r0, #0x030] + ldr r2, =0x00000047 + str r2, [r0, #0x040] + + ldr r2, =0x14420000 + str r2, [r0, #0x400] + ldr r2, =0x841A0000 + str r2, [r0, #0x000] + + ldr r2, =0x00400C58 + str r2, [r0, #0x890] + + ldr r3, =0x00bb0000 + ldr r2, =0x00000000 + str r2, [r3, #0x008] + ldr r2, =0x2891E41A + str r2, [r3, #0x00c] + ldr r2, =0x00000564 + str r2, [r3, #0x038] + ldr r2, =0x00000040 + str r2, [r3, #0x014] + ldr r2, =0x00000020 + str r2, [r3, #0x028] + str r2, [r3, #0x02c] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dqsabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000028 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000028 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x43260335 + str r2, [r0, #0x83c] + ldr r2, =0x031A030B + str r2, [r0, #0x840] + + ldr r2, =0x4323033B + str r2, [r1, #0x83c] + ldr r2, =0x0323026F + str r2, [r1, #0x840] + + ldr r2, =0x483D4545 + str r2, [r0, #0x848] + ldr r2, =0x44433E48 + str r2, [r1, #0x848] + + ldr r2, =0x41444840 + str r2, [r0, #0x850] + ldr r2, =0x4835483E + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + + ldr r2, =0x8A8F7955 + str r2, [r0, #0x00c] + ldr r2, =0xFF328F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x008F1023 + str r2, [r0, #0x030] + ldr r2, =0x00000047 + str r2, [r0, #0x040] + + ldr r2, =0x841A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dlsabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000028 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000028 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001f001f + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x42190217 + str r2, [r0, #0x83c] + ldr r2, =0x017b017b + str r2, [r0, #0x840] + + ldr r2, =0x4176017b + str r2, [r1, #0x83c] + ldr r2, =0x015f016c + str r2, [r1, #0x840] + + ldr r2, =0x4c4c4d4c + str r2, [r0, #0x848] + ldr r2, =0x4a4d4c48 + str r2, [r1, #0x848] + + ldr r2, =0x3f3f3f40 + str r2, [r0, #0x850] + ldr r2, =0x3538382e + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020025 + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x676b5313 + str r2, [r0, #0x00c] + ldr r2, =0xb66e8b63 + str r2, [r0, #0x010] + + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x00000047 + str r2, [r0, #0x040] + + ldr r2, =0x841a0000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025565 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6solosabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000028 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000028 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x421C0216 + str r2, [r0, #0x83c] + ldr r2, =0x017B017A + str r2, [r0, #0x840] + + ldr r2, =0x4B4A4E4C + str r2, [r0, #0x848] + + ldr r2, =0x3F3F3334 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x00020025 + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x676B5313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006B1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x84190000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x00025565 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00C03F3F + str r1, [r0, #0x068] + ldr r1, =0x0030FC03 + str r1, [r0, #0x06c] + ldr r1, =0x0FFFF000 + str r1, [r0, #0x070] + ldr r1, =0x3FF00000 + str r1, [r0, #0x074] + ldr r1, =0xFFFFF300 + str r1, [r0, #0x078] + ldr r1, =0x0F0000C3 + str r1, [r0, #0x07c] + ldr r1, =0x00000FFF + str r1, [r0, #0x080] + +#ifdef CONFIG_IMX_OPTEE +#ifndef CONFIG_MX6QP + ldr r0, =0x20e0024 + ldr r1, =0x3 + str r1, [r0] +#endif +#endif +.endm + +.macro imx6_qos_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + +#if defined(CONFIG_MX6QP) + ldr r1, =0x77177717 + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#else + ldr r1, =0x007F007F + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#endif +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_MX6S) + imx6solosabreauto_ddr_setting +#elif defined (CONFIG_MX6DL) + imx6dlsabreauto_ddr_setting +#elif defined (CONFIG_MX6QP) + imx6dqpsabreauto_ddr_setting +#elif defined (CONFIG_MX6Q) + imx6dqsabreauto_ddr_setting +#else + #error "SOC not configured" +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig index e87dea0d7a2..124ba8b48fe 100644 --- a/board/freescale/mx6sabresd/Kconfig +++ b/board/freescale/mx6sabresd/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MX6SABRESD +if TARGET_MX6SABRESD || TARGET_MX6SABRESD_COMMON config SYS_BOARD default "mx6sabresd" @@ -9,4 +9,7 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sabresd" +config SYS_TEXT_BASE + default 0x17800000 + endif diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg new file mode 100644 index 00000000000..7e0642579b4 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4 0x020e0774 0x000C0000 +DATA 4 0x020e0754 0x00000000 +DATA 4 0x020e04ac 0x00000030 +DATA 4 0x020e04b0 0x00000030 +DATA 4 0x020e0464 0x00000030 +DATA 4 0x020e0490 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e0494 0x00000030 +DATA 4 0x020e04a0 0x00000000 +DATA 4 0x020e04b4 0x00000030 +DATA 4 0x020e04b8 0x00000030 +DATA 4 0x020e076c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e04bc 0x00000030 +DATA 4 0x020e04c0 0x00000030 +DATA 4 0x020e04c4 0x00000030 +DATA 4 0x020e04c8 0x00000030 +DATA 4 0x020e04cc 0x00000030 +DATA 4 0x020e04d0 0x00000030 +DATA 4 0x020e04d4 0x00000030 +DATA 4 0x020e04d8 0x00000030 +DATA 4 0x020e0760 0x00020000 +DATA 4 0x020e0764 0x00000030 +DATA 4 0x020e0770 0x00000030 +DATA 4 0x020e0778 0x00000030 +DATA 4 0x020e077c 0x00000030 +DATA 4 0x020e0780 0x00000030 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e0470 0x00000030 +DATA 4 0x020e0474 0x00000030 +DATA 4 0x020e0478 0x00000030 +DATA 4 0x020e047c 0x00000030 +DATA 4 0x020e0480 0x00000030 +DATA 4 0x020e0484 0x00000030 +DATA 4 0x020e0488 0x00000030 +DATA 4 0x020e048c 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x4220021F +DATA 4 0x021b0840 0x0207017E +DATA 4 0x021b483c 0x4201020C +DATA 4 0x021b4840 0x01660172 +DATA 4 0x021b0848 0x4A4D4E4D +DATA 4 0x021b4848 0x4A4F5049 +DATA 4 0x021b0850 0x3F3C3D31 +DATA 4 0x021b4850 0x3238372B +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x0002002D +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x3F435313 +DATA 4 0x021b0010 0xB66E8B63 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x00431023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x0002556D +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFF000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F +#endif diff --git a/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg new file mode 100644 index 00000000000..3a15c4ed0f1 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg @@ -0,0 +1,160 @@ +/* + * Copyright (C) 2011-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4 0x020e0798 0x000C0000 +DATA 4 0x020e0758 0x00000000 +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00000030 +DATA 4 0x020e05b0 0x00000030 +DATA 4 0x020e0524 0x00000030 +DATA 4 0x020e051c 0x00000030 +DATA 4 0x020e0518 0x00000030 +DATA 4 0x020e050c 0x00000030 +DATA 4 0x020e05b8 0x00000030 +DATA 4 0x020e05c0 0x00000030 +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x001F001F +DATA 4 0x021b0810 0x001F001F +DATA 4 0x021b480c 0x001F001F +DATA 4 0x021b4810 0x001F001F +DATA 4 0x021b083c 0x43270338 +DATA 4 0x021b0840 0x03200314 +DATA 4 0x021b483c 0x431A032F +DATA 4 0x021b4840 0x03200263 +DATA 4 0x021b0848 0x4B434748 +DATA 4 0x021b4848 0x4445404C +DATA 4 0x021b0850 0x38444542 +DATA 4 0x021b4850 0x4935493A +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x09444040 +DATA 4 0x021b000c 0x555A7975 +DATA 4 0x021b0010 0xFF538F64 +DATA 4 0x021b0014 0x01FF00DB +DATA 4 0x021b0018 0x00001740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x005A1023 +DATA 4 0x021b0040 0x00000027 +DATA 4 0x021b0000 0x831A0000 +DATA 4 0x021b001c 0x04088032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00048031 +DATA 4 0x021b001c 0x09408030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00005800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b4818 0x00011117 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFF000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000F3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb +#endif diff --git a/board/freescale/mx6sabresd/mx6qp.cfg b/board/freescale/mx6sabresd/mx6qp.cfg new file mode 100644 index 00000000000..3b5b6780d79 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6qp.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4, 0x020e0798, 0x000c0000 +DATA 4, 0x020e0758, 0x00000000 +DATA 4, 0x020e0588, 0x00000030 +DATA 4, 0x020e0594, 0x00000030 +DATA 4, 0x020e056c, 0x00000030 +DATA 4, 0x020e0578, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e057c, 0x00000030 +DATA 4, 0x020e058c, 0x00000000 +DATA 4, 0x020e059c, 0x00000030 +DATA 4, 0x020e05a0, 0x00000030 +DATA 4, 0x020e078c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e05a8, 0x00000030 +DATA 4, 0x020e05b0, 0x00000030 +DATA 4, 0x020e0524, 0x00000030 +DATA 4, 0x020e051c, 0x00000030 +DATA 4, 0x020e0518, 0x00000030 +DATA 4, 0x020e050c, 0x00000030 +DATA 4, 0x020e05b8, 0x00000030 +DATA 4, 0x020e05c0, 0x00000030 + +DATA 4, 0x020e0534, 0x00018200 +DATA 4, 0x020e0538, 0x00008000 +DATA 4, 0x020e053c, 0x00018200 +DATA 4, 0x020e0540, 0x00018200 +DATA 4, 0x020e0544, 0x00018200 +DATA 4, 0x020e0548, 0x00018200 +DATA 4, 0x020e054c, 0x00018200 +DATA 4, 0x020e0550, 0x00018200 + +DATA 4, 0x020e0774, 0x00020000 +DATA 4, 0x020e0784, 0x00000030 +DATA 4, 0x020e0788, 0x00000030 +DATA 4, 0x020e0794, 0x00000030 +DATA 4, 0x020e079c, 0x00000030 +DATA 4, 0x020e07a0, 0x00000030 +DATA 4, 0x020e07a4, 0x00000030 +DATA 4, 0x020e07a8, 0x00000030 +DATA 4, 0x020e0748, 0x00000030 +DATA 4, 0x020e05ac, 0x00000030 +DATA 4, 0x020e05b4, 0x00000030 +DATA 4, 0x020e0528, 0x00000030 +DATA 4, 0x020e0520, 0x00000030 +DATA 4, 0x020e0514, 0x00000030 +DATA 4, 0x020e0510, 0x00000030 +DATA 4, 0x020e05bc, 0x00000030 +DATA 4, 0x020e05c4, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001b001e +DATA 4, 0x021b0810, 0x002e0029 +DATA 4, 0x021b480c, 0x001b002a +DATA 4, 0x021b4810, 0x0019002c +DATA 4, 0x021b083c, 0x43240334 +DATA 4, 0x021b0840, 0x0324031a +DATA 4, 0x021b483c, 0x43340344 +DATA 4, 0x021b4840, 0x03280276 +DATA 4, 0x021b0848, 0x44383A3E +DATA 4, 0x021b4848, 0x3C3C3846 +DATA 4, 0x021b0850, 0x2e303230 +DATA 4, 0x021b4850, 0x38283E34 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x33333333 +DATA 4, 0x021b4828, 0x33333333 +DATA 4, 0x021b08c0, 0x24912489 +DATA 4, 0x021b48c0, 0x24914452 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x24444040 +DATA 4, 0x021b000c, 0x555A7955 +DATA 4, 0x021b0010, 0xFF320F64 +DATA 4, 0x021b0014, 0x01ff00db +DATA 4, 0x021b0018, 0x00011740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x005A1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0400, 0x14420000 +DATA 4, 0x021b0000, 0x831A0000 +DATA 4, 0x021b0890, 0x00400C58 +DATA 4, 0x00bb0008, 0x00000000 +DATA 4, 0x00bb000c, 0x2891E41A +DATA 4, 0x00bb0038, 0x00000564 +DATA 4, 0x00bb0014, 0x00000040 +DATA 4, 0x00bb0028, 0x00000020 +DATA 4, 0x00bb002c, 0x00000020 +DATA 4, 0x021b001c, 0x04088032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x09408030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b4818, 0x00011117 +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 +#endif diff --git a/board/freescale/mx6sabresd/mx6qp_optee.cfg b/board/freescale/mx6sabresd/mx6qp_optee.cfg new file mode 100644 index 00000000000..12a24706f71 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6qp_optee.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4, 0x020e0798, 0x000c0000 +DATA 4, 0x020e0758, 0x00000000 +DATA 4, 0x020e0588, 0x00000030 +DATA 4, 0x020e0594, 0x00000030 +DATA 4, 0x020e056c, 0x00000030 +DATA 4, 0x020e0578, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e057c, 0x00000030 +DATA 4, 0x020e058c, 0x00000000 +DATA 4, 0x020e059c, 0x00000030 +DATA 4, 0x020e05a0, 0x00000030 +DATA 4, 0x020e078c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e05a8, 0x00000030 +DATA 4, 0x020e05b0, 0x00000030 +DATA 4, 0x020e0524, 0x00000030 +DATA 4, 0x020e051c, 0x00000030 +DATA 4, 0x020e0518, 0x00000030 +DATA 4, 0x020e050c, 0x00000030 +DATA 4, 0x020e05b8, 0x00000030 +DATA 4, 0x020e05c0, 0x00000030 + +DATA 4, 0x020e0534, 0x00018200 +DATA 4, 0x020e0538, 0x00008000 +DATA 4, 0x020e053c, 0x00018200 +DATA 4, 0x020e0540, 0x00018200 +DATA 4, 0x020e0544, 0x00018200 +DATA 4, 0x020e0548, 0x00018200 +DATA 4, 0x020e054c, 0x00018200 +DATA 4, 0x020e0550, 0x00018200 + +DATA 4, 0x020e0774, 0x00020000 +DATA 4, 0x020e0784, 0x00000030 +DATA 4, 0x020e0788, 0x00000030 +DATA 4, 0x020e0794, 0x00000030 +DATA 4, 0x020e079c, 0x00000030 +DATA 4, 0x020e07a0, 0x00000030 +DATA 4, 0x020e07a4, 0x00000030 +DATA 4, 0x020e07a8, 0x00000030 +DATA 4, 0x020e0748, 0x00000030 +DATA 4, 0x020e05ac, 0x00000030 +DATA 4, 0x020e05b4, 0x00000030 +DATA 4, 0x020e0528, 0x00000030 +DATA 4, 0x020e0520, 0x00000030 +DATA 4, 0x020e0514, 0x00000030 +DATA 4, 0x020e0510, 0x00000030 +DATA 4, 0x020e05bc, 0x00000030 +DATA 4, 0x020e05c4, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001b001e +DATA 4, 0x021b0810, 0x002e0029 +DATA 4, 0x021b480c, 0x001b002a +DATA 4, 0x021b4810, 0x0019002c +DATA 4, 0x021b083c, 0x43240334 +DATA 4, 0x021b0840, 0x0324031a +DATA 4, 0x021b483c, 0x43340344 +DATA 4, 0x021b4840, 0x03280276 +DATA 4, 0x021b0848, 0x44383A3E +DATA 4, 0x021b4848, 0x3C3C3846 +DATA 4, 0x021b0850, 0x2e303230 +DATA 4, 0x021b4850, 0x38283E34 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b481c, 0x33333333 +DATA 4, 0x021b4820, 0x33333333 +DATA 4, 0x021b4824, 0x33333333 +DATA 4, 0x021b4828, 0x33333333 +DATA 4, 0x021b08c0, 0x24912489 +DATA 4, 0x021b48c0, 0x24914452 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b48b8, 0x00000800 +DATA 4, 0x021b0004, 0x00020036 +DATA 4, 0x021b0008, 0x24444040 +DATA 4, 0x021b000c, 0x555A7955 +DATA 4, 0x021b0010, 0xFF320F64 +DATA 4, 0x021b0014, 0x01ff00db +DATA 4, 0x021b0018, 0x00011740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x005A1023 +DATA 4, 0x021b0040, 0x00000027 +DATA 4, 0x021b0400, 0x10420000 +DATA 4, 0x021b0000, 0x831A0000 +DATA 4, 0x021b0890, 0x00400C58 +DATA 4, 0x021b001c, 0x04088032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x09408030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b4818, 0x00011117 +DATA 4, 0x021b0004, 0x00025576 +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000F3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */ +DATA 4, 0x020e0018, 0x77177717 +DATA 4, 0x020e001c, 0x77177717 +#endif diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 8c352308553..d1b31eb29a4 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * Author: Fabio Estevam */ @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +37,18 @@ #include "../common/pfuze.h" #include #include +#include +#include +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#ifdef CONFIG_FSL_FASTBOOT +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif +#endif /*CONFIG_FSL_FASTBOOT*/ DECLARE_GLOBAL_DATA_PTR; @@ -53,12 +67,18 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + + #define I2C_PMIC 1 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) -#define DISP0_PWR_EN IMX_GPIO_NR(1, 21) - #define KEY_VOL_UP IMX_GPIO_NR(1, 4) int dram_init(void) @@ -72,47 +92,7 @@ static iomux_v3_cfg_t const uart1_pads[] = { IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), }; -static iomux_v3_cfg_t const usdhc2_pads[] = { - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc3_pads[] = { - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ -}; - -static iomux_v3_cfg_t const usdhc4_pads[] = { - IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), - IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), -}; - +#ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi1_pads[] = { IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)), IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)), @@ -120,6 +100,12 @@ static iomux_v3_cfg_t const ecspi1_pads[] = { IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), }; +static void setup_spi(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); +} +#endif + static iomux_v3_cfg_t const rgb_pads[] = { IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)), IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)), @@ -158,9 +144,20 @@ static iomux_v3_cfg_t const bl_pads[] = { static void enable_backlight(void) { + struct gpio_desc desc; + int ret; + SETUP_IOMUX_PADS(bl_pads); - gpio_request(DISP0_PWR_EN, "Display Power Enable"); - gpio_direction_output(DISP0_PWR_EN, 1); + + ret = dm_gpio_lookup_name("GPIO1_21", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "Display Power Enable"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); } static void enable_rgb(struct display_info_t const *dev) @@ -174,36 +171,34 @@ static void enable_lvds(struct display_info_t const *dev) enable_backlight(); } -static struct i2c_pads_info mx6q_i2c_pad_info1 = { +#ifdef CONFIG_SYS_I2C +static struct i2c_pads_info i2c_pad_info1 = { .scl = { - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, .gp = IMX_GPIO_NR(4, 12) }, .sda = { - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, .gp = IMX_GPIO_NR(4, 13) } }; +#endif -static struct i2c_pads_info mx6dl_i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD, - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, - .gp = IMX_GPIO_NR(4, 13) - } +#if defined(CONFIG_PCIE_IMX) && !defined(CONFIG_DM_PCI) +iomux_v3_cfg_t const pcie_pads[] = { + IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */ + IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */ }; -static void setup_spi(void) +static void setup_pcie(void) { - SETUP_IOMUX_PADS(ecspi1_pads); + SETUP_IOMUX_PADS(pcie_pads); + gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable"); + gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset"); } +#endif iomux_v3_cfg_t const di0_pads[] = { IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */ @@ -216,7 +211,97 @@ static void setup_iomux_uart(void) SETUP_IOMUX_PADS(uart1_pads); } +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +static iomux_v3_cfg_t const epdc_enable_pads[] = { + IOMUX_PADS(PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22), + IOMUX_PADS(PAD_EIM_DA10__GPIO3_IO10), + IOMUX_PADS(PAD_EIM_DA12__GPIO3_IO12), + IOMUX_PADS(PAD_EIM_DA11__GPIO3_IO11), + IOMUX_PADS(PAD_EIM_LBA__GPIO2_IO27), + IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30), + IOMUX_PADS(PAD_EIM_CS0__GPIO2_IO23), + IOMUX_PADS(PAD_EIM_RW__GPIO2_IO26), + IOMUX_PADS(PAD_EIM_A21__GPIO2_IO17), + IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16), + IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06), + IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04), + IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31), + IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27), + IOMUX_PADS(PAD_EIM_DA1__GPIO3_IO01), + IOMUX_PADS(PAD_EIM_EB1__GPIO2_IO29), + IOMUX_PADS(PAD_EIM_DA2__GPIO3_IO02), + IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04), + IOMUX_PADS(PAD_EIM_DA5__GPIO3_IO05), + IOMUX_PADS(PAD_EIM_DA6__GPIO3_IO06), +}; +#endif + #ifdef CONFIG_FSL_ESDHC_IMX +#if !CONFIG_IS_ENABLED(DM_MMC) +static iomux_v3_cfg_t const usdhc2_pads[] = { + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */ +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + struct fsl_esdhc_cfg usdhc_cfg[3] = { {USDHC2_BASE_ADDR}, {USDHC3_BASE_ADDR}, @@ -226,11 +311,6 @@ struct fsl_esdhc_cfg usdhc_cfg[3] = { #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2) #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0) -int board_mmc_get_env_dev(int devno) -{ - return devno - 1; -} - int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; @@ -288,20 +368,27 @@ int board_mmc_init(struct bd_info *bis) return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); } #endif +#endif static int ar8031_phy_fixup(struct phy_device *phydev) { unsigned short val; /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + if (!is_mx6dqp()) { + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + } - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + /* set the IO voltage to 1.8v */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); /* introduce tx clock delay */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); @@ -322,6 +409,227 @@ int board_phy_config(struct phy_device *phydev) return 0; } +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 800, + .vl_row = 600, + .vl_pixclock = 26666667, + .vl_left_margin = 8, + .vl_right_margin = 100, + .vl_upper_margin = 4, + .vl_lower_margin = 8, + .vl_hsync = 4, + .vl_vsync = 1, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 419, + .gdsp_offs = 20, + .gdoe_offs = 0, + .gdclk_offs = 5, + .num_ce = 1, +}; + +static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = { + IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D17__GPIO3_IO17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EIM_A18__GPIO2_IO20 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +struct gpio_desc epd_pwrstat_desc; +struct gpio_desc epd_vcom_desc; +struct gpio_desc epd_wakeup_desc; +struct gpio_desc epd_pwr_ctl0_desc; + +static void setup_epdc_power(void) +{ + int ret; + + SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads); + + /* Setup epdc voltage */ + + /* EIM_A17 - GPIO2[21] for PWR_GOOD status */ + /* Set as input */ + ret = dm_gpio_lookup_name("GPIO2_21", &epd_pwrstat_desc); + if (ret) { + printf("%s lookup GPIO2_21 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_pwrstat_desc, "EPDC PWRSTAT"); + if (ret) { + printf("%s request EPDC PWRSTAT failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_pwrstat_desc, GPIOD_IS_IN); + + /* EIM_D17 - GPIO3[17] for VCOM control */ + /* Set as output */ + ret = dm_gpio_lookup_name("GPIO3_17", &epd_vcom_desc); + if (ret) { + printf("%s lookup GPIO3_17 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_vcom_desc, "EPDC VCOM0"); + if (ret) { + printf("%s request EPDC VCOM0 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_vcom_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */ + /* Set as output */ + ret = dm_gpio_lookup_name("GPIO3_20", &epd_wakeup_desc); + if (ret) { + printf("%s lookup GPIO3_20 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_wakeup_desc, "EPDC PWR WAKEUP"); + if (ret) { + printf("%s request EPDC PWR WAKEUP failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_wakeup_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */ + /* Set as output */ + ret = dm_gpio_lookup_name("GPIO2_20", &epd_pwr_ctl0_desc); + if (ret) { + printf("%s lookup GPIO2_20 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_pwr_ctl0_desc, "EPDC PWR CTRL0"); + if (ret) { + printf("%s request EPDC PWR CTRL0 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_pwr_ctl0_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + SETUP_IOMUX_PADS(epdc_enable_pads); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO */ + SETUP_IOMUX_PADS(epdc_disable_pads); +} + +static void setup_epdc(void) +{ + unsigned int reg; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /*** Set pixel clock rates for EPDC ***/ + + /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */ + reg = readl(&ccm_regs->cscdr3); + reg &= ~0x7C000; + reg |= (1 << 16) | (1 << 14); + writel(reg, &ccm_regs->cscdr3); + + /* EPDC AXI clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x00C0; + writel(reg, &ccm_regs->CCGR3); + + /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */ + reg = readl(&ccm_regs->cscdr2); + reg &= ~0x3FE00; + reg |= (2 << 15) | (5 << 12); + writel(reg, &ccm_regs->cscdr2); + + /* PLL5 enable (defaults to 650) */ + reg = readl(&ccm_regs->analog_pll_video); + reg &= ~((1 << 16) | (1 << 12)); + reg |= (1 << 13); + writel(reg, &ccm_regs->analog_pll_video); + + /* EPDC PIX clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x0C00; + writel(reg, &ccm_regs->CCGR3); + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + dm_gpio_set_value(&epd_pwr_ctl0_desc, 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + dm_gpio_set_value(&epd_wakeup_desc, 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 21))) + break; + + udelay(100); + } + + /* Enable VCOM */ + dm_gpio_set_value(&epd_vcom_desc, 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + dm_gpio_set_value(&epd_wakeup_desc, 0); + + /* Disable VCOM */ + dm_gpio_set_value(&epd_vcom_desc, 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + dm_gpio_set_value(&epd_pwr_ctl0_desc, 0); +} +#endif + #if defined(CONFIG_VIDEO_IPUV3) static void disable_lvds(struct display_info_t const *dev) { @@ -365,21 +673,21 @@ struct display_info_t const displays[] = {{ .bus = -1, .addr = 0, .pixfmt = IPU_PIX_FMT_RGB24, - .detect = detect_hdmi, + .detect = NULL, .enable = do_enable_hdmi, .mode = { .name = "HDMI", .refresh = 60, - .xres = 1024, - .yres = 768, - .pixclock = 15384, - .left_margin = 160, - .right_margin = 24, - .upper_margin = 29, - .lower_margin = 3, - .hsync_len = 136, - .vsync_len = 6, - .sync = FB_SYNC_EXT, + .xres = 640, + .yres = 480, + .pixclock = 39721, + .left_margin = 48, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, .vmode = FB_VMODE_NONINTERLACED } }, { .bus = 0, @@ -469,20 +777,46 @@ int overwrite_console(void) return 1; } +static void setup_fec(void) +{ + if (is_mx6dqp()) { + int ret; + + /* select ENET MAC0 TX clock from PLL */ + imx_iomux_set_gpr_register(5, 9, 1, 1); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + printf("Error fec anatop clock settings!\n"); + } +} + #ifdef CONFIG_USB_EHCI_MX6 -static void setup_usb(void) +int board_ehci_hcd_init(int port) { - /* - * set daisy chain for otg_pin_id on 6q. - * for 6dl, this bit is reserved - */ - imx_iomux_set_gpr_register(1, 13, 1, 0); + switch (port) { + case 0: + /* + * Set daisy chain for otg_pin_id on 6q. + * For 6dl, this bit is reserved. + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + return 0; } #endif int board_early_init_f(void) { setup_iomux_uart(); +#if defined(CONFIG_VIDEO_IPUV3) + setup_display(); +#endif return 0; } @@ -492,58 +826,396 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#if defined(CONFIG_DM_REGULATOR) + regulators_enable_boot_on(false); +#endif + #ifdef CONFIG_MXC_SPI setup_spi(); #endif - if (is_mx6dq() || is_mx6dqp()) - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); - else - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); -#if defined(CONFIG_VIDEO_IPUV3) - setup_display(); + +#ifdef CONFIG_SYS_I2C + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); #endif -#ifdef CONFIG_USB_EHCI_MX6 - setup_usb(); + +#if defined(CONFIG_PCIE_IMX) && !defined(CONFIG_DM_PCI) + setup_pcie(); +#endif + +#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC) + setup_epdc(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); #endif return 0; } +#ifdef CONFIG_POWER int power_init_board(void) { - struct pmic *p; + struct pmic *pfuze; unsigned int reg; int ret; - p = pfuze_common_init(I2C_PMIC); - if (!p) + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) return -ENODEV; - ret = pfuze_mode_init(p, APS_PFM); + if (is_mx6dqp()) + ret = pfuze_mode_init(pfuze, APS_APS); + else + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) return ret; + /* VGEN3 and VGEN5 corrected on i.mx6qp board */ + if (!is_mx6dqp()) { + /* Increase VGEN3 from 2.5 to 2.8V */ + pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); + } - /* Increase VGEN3 from 2.5 to 2.8V */ - pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_2_80V; - pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW2STBY, ®); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW2CONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + } - /* Increase VGEN5 from 2.8 to 3V */ - pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); - reg &= ~LDO_VOL_MASK; - reg |= LDOB_3_00V; - pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + return 0; +} + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + unsigned int reg; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + if (is_mx6dqp()) + ret = pfuze_mode_init(dev, APS_APS); + else + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + /* VGEN3 and VGEN5 corrected on i.mx6qp board */ + if (!is_mx6dqp()) { + /* Increase VGEN3 from 2.5 to 2.8V */ + reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + } + + if (is_mx6dqp()) { + /* set SW1C staby volatage 1.075V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1f; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + + /* set SW2/VDDARM staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW2STBY); + reg &= ~0x3f; + reg |= 0x17; + pmic_reg_write(dev, PFUZE100_SW2STBY, reg); + + /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW2CONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW2CONF, reg); + } else { + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + } return 0; } +#endif -#ifdef CONFIG_MXC_SPI -int board_spi_cs_gpio(unsigned bus, unsigned cs) +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) { - return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1; + unsigned int value; + int is_400M; + unsigned char vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x29; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* increase VDDARM to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } + /* increase VDDSOC to 1.425V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x2d; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + } + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + if (is_mx6dqp()) { + /* decrease VDDARM for 400Mhz DQP:1.1V*/ + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + value |= 0x1c; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } else { + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + if (is_mx6dl()) + value |= 0x27; + else + value |= 0x20; + + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + } + /* increase VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x28; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + /* + * MX6Q/DQP: + * VDDARM:1.15V@800M; VDDSOC:1.175V@800M + * VDDARM:0.975V@400M; VDDSOC:1.175V@400M + * MX6DL: + * VDDARM:1.175V@800M; VDDSOC:1.175V@800M + * VDDARM:1.15V@400M; VDDSOC:1.175V@400M + */ + is_400M = set_anatop_bypass(2); + if (is_mx6dqp()) { + pmic_reg_read(p, PFUZE100_SW2VOL, &value); + value &= ~0x3f; + if (is_400M) + value |= 0x17; + else + value |= 0x1e; + pmic_reg_write(p, PFUZE100_SW2VOL, value); + } + + if (is_400M) { + if (is_mx6dl()) + vddarm = 0x22; + else + vddarm = 0x1b; + } else { + if (is_mx6dl()) + vddarm = 0x23; + else + vddarm = 0x22; + } + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.175V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x23; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + int is_400M; + unsigned char vddarm; + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* increase VDDARM/VDDSOC to support 1.2G chip */ + if (check_1_2G()) { + ldo_bypass = 0; /* ldo_enable on 1.2G chip */ + printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n"); + if (is_mx6dqp()) { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29); + } else { + /* increase VDDARM to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d); + } + /* increase VDDSOC to 1.425V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d); + } + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + if (is_mx6dqp()) { + /* decrease VDDARM for 400Mhz DQP:1.1V*/ + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1c); + } else { + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + if (is_mx6dl()) + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x27); + else + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20); + } + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28); + + /* + * MX6Q/DQP: + * VDDARM:1.15V@800M; VDDSOC:1.175V@800M + * VDDARM:0.975V@400M; VDDSOC:1.175V@400M + * MX6DL: + * VDDARM:1.175V@800M; VDDSOC:1.175V@800M + * VDDARM:1.15V@400M; VDDSOC:1.175V@400M + */ + is_400M = set_anatop_bypass(2); + if (is_mx6dqp()) { + if (is_400M) + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x17); + else + pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1e); + } + + if (is_400M) { + if (is_mx6dl()) + vddarm = 0x22; + else + vddarm = 0x1b; + } else { + if (is_mx6dl()) + vddarm = 0x23; + else + vddarm = 0x22; + } + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } } #endif +#endif #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { @@ -562,6 +1234,11 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "SABRESD"); @@ -573,9 +1250,56 @@ int board_late_init(void) env_set("board_rev", "MX6DL"); #endif +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + return 0; } +#ifdef CONFIG_FSL_FASTBOOT +#ifdef CONFIG_ANDROID_RECOVERY + +#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5) +iomux_v3_cfg_t const recovery_key_pads[] = { + IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)), +}; + +int is_recovery_key_pressing(void) +{ + int button_pressed = 0; + int ret; + struct gpio_desc desc; + + /* Check Recovery Combo Button press or not. */ + SETUP_IOMUX_PADS(recovery_key_pads); + + ret = dm_gpio_lookup_name("GPIO1_5", &desc); + if (ret) { + printf("%s lookup GPIO1_5 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "volume_dn_key"); + if (ret) { + printf("%s request volume_dn_key failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN); + + if (dm_gpio_get_value(&desc) == 0) { /* VOL_DN key is low assert */ + button_pressed = 1; + printf("Recovery key pressed\n"); + } + + return button_pressed; +} + +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#endif /*CONFIG_FSL_FASTBOOT*/ + #ifdef CONFIG_SPL_BUILD #include #include diff --git a/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg new file mode 100644 index 00000000000..8968feb3335 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Jason Liu + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +#ifdef CONFIG_IMX_OPTEE +SET_BIT 4 0x20c4070 0x3c00000 +DATA 4 0x20e0024 0x00000003 +CHECK_BITS_SET 4 0x20e0024 0x3 +#endif +DATA 4, 0x020e0774, 0x000C0000 +DATA 4, 0x020e0754, 0x00000000 +DATA 4, 0x020e04ac, 0x00000030 +DATA 4, 0x020e04b0, 0x00000030 +DATA 4, 0x020e0464, 0x00000030 +DATA 4, 0x020e0490, 0x00000030 +DATA 4, 0x020e074c, 0x00000030 +DATA 4, 0x020e0494, 0x00000030 +DATA 4, 0x020e04a0, 0x00000000 +DATA 4, 0x020e04b4, 0x00000030 +DATA 4, 0x020e04b8, 0x00000030 +DATA 4, 0x020e076c, 0x00000030 +DATA 4, 0x020e0750, 0x00020000 +DATA 4, 0x020e04bc, 0x00000030 +DATA 4, 0x020e04c0, 0x00000030 +DATA 4, 0x020e04c4, 0x00000030 +DATA 4, 0x020e04c8, 0x00000030 +DATA 4, 0x020e0760, 0x00020000 +DATA 4, 0x020e0764, 0x00000030 +DATA 4, 0x020e0770, 0x00000030 +DATA 4, 0x020e0778, 0x00000030 +DATA 4, 0x020e077c, 0x00000030 +DATA 4, 0x020e0470, 0x00000030 +DATA 4, 0x020e0474, 0x00000030 +DATA 4, 0x020e0478, 0x00000030 +DATA 4, 0x020e047c, 0x00000030 +DATA 4, 0x021b0800, 0xa1390003 +DATA 4, 0x021b080c, 0x001F001F +DATA 4, 0x021b0810, 0x001F001F +DATA 4, 0x021b083c, 0x42190219 +DATA 4, 0x021b0840, 0x017B0177 +DATA 4, 0x021b0848, 0x4B4D4E4D +DATA 4, 0x021b0850, 0x3F3E2D36 +DATA 4, 0x021b081c, 0x33333333 +DATA 4, 0x021b0820, 0x33333333 +DATA 4, 0x021b0824, 0x33333333 +DATA 4, 0x021b0828, 0x33333333 +DATA 4, 0x021b08b8, 0x00000800 +DATA 4, 0x021b0004, 0x0002002D +DATA 4, 0x021b0008, 0x00333030 +DATA 4, 0x021b000c, 0x3F435313 +DATA 4, 0x021b0010, 0xB66E8B63 +DATA 4, 0x021b0014, 0x01FF00DB +DATA 4, 0x021b0018, 0x00001740 +DATA 4, 0x021b001c, 0x00008000 +DATA 4, 0x021b002c, 0x000026d2 +DATA 4, 0x021b0030, 0x00431023 +DATA 4, 0x021b0040, 0x00000017 +DATA 4, 0x021b0000, 0x83190000 +DATA 4, 0x021b001c, 0x04008032 +DATA 4, 0x021b001c, 0x00008033 +DATA 4, 0x021b001c, 0x00048031 +DATA 4, 0x021b001c, 0x05208030 +DATA 4, 0x021b001c, 0x04008040 +DATA 4, 0x021b0020, 0x00005800 +DATA 4, 0x021b0818, 0x00011117 +DATA 4, 0x021b0004, 0x0002556D +DATA 4, 0x021b0404, 0x00011006 +DATA 4, 0x021b001c, 0x00000000 + +/* set the default clock gate to save power */ +DATA 4, 0x020c4068, 0x00C03F3F +DATA 4, 0x020c406c, 0x0030FC03 +DATA 4, 0x020c4070, 0x0FFFF000 +DATA 4, 0x020c4074, 0x3FF00000 +DATA 4, 0x020c4078, 0x00FFF300 +DATA 4, 0x020c407c, 0x0F0000C3 +DATA 4, 0x020c4080, 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F +#endif diff --git a/board/freescale/mx6sabresd/plugin.S b/board/freescale/mx6sabresd/plugin.S new file mode 100644 index 00000000000..d99349f48e0 --- /dev/null +++ b/board/freescale/mx6sabresd/plugin.S @@ -0,0 +1,690 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6dqpsabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00018200 + str r1, [r0, #0x534] + ldr r1, =0x00008000 + str r1, [r0, #0x538] + ldr r1, =0x00018200 + str r1, [r0, #0x53c] + str r1, [r0, #0x540] + str r1, [r0, #0x544] + str r1, [r0, #0x548] + str r1, [r0, #0x54c] + str r1, [r0, #0x550] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001b001e + str r2, [r0, #0x80c] + ldr r2, =0x002e0029 + str r2, [r0, #0x810] + + ldr r1, =MMDC_P1_BASE_ADDR + ldr r2, =0x001b002a + str r2, [r1, #0x80c] + ldr r2, =0x0019002c + str r2, [r1, #0x810] + + ldr r2, =0x43240334 + str r2, [r0, #0x83c] + ldr r2, =0x0324031a + str r2, [r0, #0x840] + + ldr r2, =0x43340344 + str r2, [r1, #0x83c] + ldr r2, =0x03280276 + str r2, [r1, #0x840] + + ldr r2, =0x44383A3E + str r2, [r0, #0x848] + ldr r2, =0x3C3C3846 + str r2, [r1, #0x848] + + ldr r2, =0x2e303230 + str r2, [r0, #0x850] + ldr r2, =0x38283E34 + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x24912489 + str r2, [r0, #0x8c0] + ldr r2, =0x24914452 + str r2, [r1, #0x8c0] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x24444040 + str r2, [r0, #0x008] + + ldr r2, =0x555A7955 + str r2, [r0, #0x00c] + ldr r2, =0xFF320F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005A1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x14420000 + str r2, [r0, #0x400] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x00400C58 + str r2, [r0, #0x890] + + ldr r3, =0x00bb0000 + ldr r2, =0x00000000 + str r2, [r3, #0x008] + ldr r2, =0x2891E41A + str r2, [r3, #0x00C] + ldr r2, =0x00000564 + str r2, [r3, #0x038] + ldr r2, =0x00000040 + str r2, [r3, #0x014] + ldr r2, =0x00000020 + str r2, [r3, #0x028] + ldr r2, =0x00000020 + str r2, [r3, #0x02c] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dqsabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x798] + ldr r1, =0x00000000 + str r1, [r0, #0x758] + + ldr r1, =0x00000030 + str r1, [r0, #0x588] + str r1, [r0, #0x594] + str r1, [r0, #0x56c] + str r1, [r0, #0x578] + str r1, [r0, #0x74c] + str r1, [r0, #0x57c] + + ldr r1, =0x00000000 + str r1, [r0, #0x58c] + + ldr r1, =0x00000030 + str r1, [r0, #0x59c] + str r1, [r0, #0x5a0] + str r1, [r0, #0x78c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x5a8] + str r1, [r0, #0x5b0] + str r1, [r0, #0x524] + str r1, [r0, #0x51c] + str r1, [r0, #0x518] + str r1, [r0, #0x50c] + str r1, [r0, #0x5b8] + str r1, [r0, #0x5c0] + + ldr r1, =0x00020000 + str r1, [r0, #0x774] + + ldr r1, =0x00000030 + str r1, [r0, #0x784] + str r1, [r0, #0x788] + str r1, [r0, #0x794] + str r1, [r0, #0x79c] + str r1, [r0, #0x7a0] + str r1, [r0, #0x7a4] + str r1, [r0, #0x7a8] + str r1, [r0, #0x748] + str r1, [r0, #0x5ac] + str r1, [r0, #0x5b4] + str r1, [r0, #0x528] + str r1, [r0, #0x520] + str r1, [r0, #0x514] + str r1, [r0, #0x510] + str r1, [r0, #0x5bc] + str r1, [r0, #0x5c4] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x43270338 + str r2, [r0, #0x83c] + ldr r2, =0x03200314 + str r2, [r0, #0x840] + + ldr r2, =0x431A032F + str r2, [r1, #0x83c] + ldr r2, =0x03200263 + str r2, [r1, #0x840] + + ldr r2, =0x4B434748 + str r2, [r0, #0x848] + ldr r2, =0x4445404C + str r2, [r1, #0x848] + + ldr r2, =0x38444542 + str r2, [r0, #0x850] + ldr r2, =0x4935493A + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x00020036 + str r2, [r0, #0x004] + ldr r2, =0x09444040 + str r2, [r0, #0x008] + + ldr r2, =0x555A7975 + str r2, [r0, #0x00c] + ldr r2, =0xFF538F64 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x005A1023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04088032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x09408030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6dlsabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + str r1, [r0, #0x4cc] + str r1, [r0, #0x4d0] + str r1, [r0, #0x4d4] + str r1, [r0, #0x4d8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000030 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x780] + str r1, [r0, #0x784] + str r1, [r0, #0x78c] + str r1, [r0, #0x748] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + str r1, [r0, #0x480] + str r1, [r0, #0x484] + str r1, [r0, #0x488] + str r1, [r0, #0x48c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001f001f + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + ldr r1, =MMDC_P1_BASE_ADDR + str r2, [r1, #0x80c] + str r2, [r1, #0x810] + + ldr r2, =0x4220021F + str r2, [r0, #0x83c] + ldr r2, =0x0207017E + str r2, [r0, #0x840] + + ldr r2, =0x4201020C + str r2, [r1, #0x83c] + ldr r2, =0x01660172 + str r2, [r1, #0x840] + + ldr r2, =0x4A4D4E4D + str r2, [r0, #0x848] + ldr r2, =0x4A4F5049 + str r2, [r1, #0x848] + + ldr r2, =0x3F3C3D31 + str r2, [r0, #0x850] + ldr r2, =0x3238372B + str r2, [r1, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r1, #0x81c] + str r2, [r1, #0x820] + str r2, [r1, #0x824] + str r2, [r1, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + str r2, [r1, #0x8b8] + + ldr r2, =0x0002002D + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x3F435313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00431023 + str r2, [r0, #0x030] + ldr r2, =0x00000027 + str r2, [r0, #0x040] + + ldr r2, =0x831A0000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + str r2, [r1, #0x818] + ldr r2, =0x0002556D + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6solosabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x774] + ldr r1, =0x00000000 + str r1, [r0, #0x754] + + ldr r1, =0x00000030 + str r1, [r0, #0x4ac] + str r1, [r0, #0x4b0] + str r1, [r0, #0x464] + str r1, [r0, #0x490] + str r1, [r0, #0x74c] + str r1, [r0, #0x494] + + ldr r1, =0x00000000 + str r1, [r0, #0x4a0] + + ldr r1, =0x00000030 + str r1, [r0, #0x4b4] + str r1, [r0, #0x4b8] + str r1, [r0, #0x76c] + + ldr r1, =0x00020000 + str r1, [r0, #0x750] + + ldr r1, =0x00000030 + str r1, [r0, #0x4bc] + str r1, [r0, #0x4c0] + str r1, [r0, #0x4c4] + str r1, [r0, #0x4c8] + + ldr r1, =0x00020000 + str r1, [r0, #0x760] + + ldr r1, =0x00000030 + str r1, [r0, #0x764] + str r1, [r0, #0x770] + str r1, [r0, #0x778] + str r1, [r0, #0x77c] + str r1, [r0, #0x470] + str r1, [r0, #0x474] + str r1, [r0, #0x478] + str r1, [r0, #0x47c] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x001F001F + str r2, [r0, #0x80c] + str r2, [r0, #0x810] + + ldr r2, =0x42190219 + str r2, [r0, #0x83c] + ldr r2, =0x017B0177 + str r2, [r0, #0x840] + + ldr r2, =0x4B4D4E4D + str r2, [r0, #0x848] + + ldr r2, =0x3F3E2D36 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x0002002D + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + + ldr r2, =0x3F435313 + str r2, [r0, #0x00c] + ldr r2, =0xB66E8B63 + str r2, [r0, #0x010] + + ldr r2, =0x01FF00DB + str r2, [r0, #0x014] + ldr r2, =0x00001740 + str r2, [r0, #0x018] + + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x00431023 + str r2, [r0, #0x030] + ldr r2, =0x00000017 + str r2, [r0, #0x040] + + ldr r2, =0x83190000 + str r2, [r0, #0x000] + + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + + ldr r2, =0x00005800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x0002556D + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00C03F3F + str r1, [r0, #0x068] + ldr r1, =0x0030FC03 + str r1, [r0, #0x06c] + ldr r1, =0x0FFFF000 + str r1, [r0, #0x070] + ldr r1, =0x3FF00000 + str r1, [r0, #0x074] + ldr r1, =0x00FFF300 + str r1, [r0, #0x078] + ldr r1, =0x0F0000C3 + str r1, [r0, #0x07c] + ldr r1, =0x000003FF + str r1, [r0, #0x080] +#ifdef CONFIG_IMX_OPTEE +#ifndef CONFIG_MX6QP + ldr r0, =0x20e0024 + ldr r1, =0x3 + str r1, [r0] +#endif +#endif +.endm + +.macro imx6_qos_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0xF00000CF + str r1, [r0, #0x10] + +#if defined(CONFIG_MX6QP) + ldr r1, =0x77177717 + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#else + ldr r1, =0x007F007F + str r1, [r0, #0x18] + str r1, [r0, #0x1c] +#endif +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_MX6S) + imx6solosabresd_ddr_setting +#elif defined (CONFIG_MX6DL) + imx6dlsabresd_ddr_setting +#elif defined (CONFIG_MX6QP) + imx6dqpsabresd_ddr_setting +#elif defined (CONFIG_MX6Q) + imx6dqsabresd_ddr_setting +#else + #error "SOC not configured" +#endif + +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig index 18482b551e5..42a2debf195 100644 --- a/board/freescale/mx6slevk/Kconfig +++ b/board/freescale/mx6slevk/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6slevk" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6slevk/imximage.cfg b/board/freescale/mx6slevk/imximage.cfg index b97761a5162..81f7d8b57bf 100644 --- a/board/freescale/mx6slevk/imximage.cfg +++ b/board/freescale/mx6slevk/imximage.cfg @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013 Freescale Semiconductor, Inc. + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure * and create imximage boot image @@ -21,9 +22,11 @@ IMAGE_VERSION 2 BOOT_FROM sd -/* - * Secure boot support - */ +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6slevk/plugin.bin 0x00907000 +#else + #ifdef CONFIG_IMX_HAB CSF CONFIG_CSF_SIZE #endif @@ -49,6 +52,11 @@ DATA 4 0x020c4078 0xffffffff DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x020e0024 0x00000001 +CHECK_BITS_SET 4 0x020e0024 0x1 +#endif + DATA 4 0x020e0344 0x00003030 DATA 4 0x020e0348 0x00003030 DATA 4 0x020e034c 0x00003030 @@ -105,6 +113,7 @@ DATA 4 0x021b0038 0x00190778 DATA 4 0x021b0008 0x00000000 DATA 4 0x021b0040 0x0000004f DATA 4 0x021b0000 0xc3110000 +DATA 4 0x021b001c 0x00008010 DATA 4 0x021b001c 0x003f8030 DATA 4 0x021b001c 0xff0a8030 DATA 4 0x021b001c 0x82018030 @@ -121,3 +130,4 @@ DATA 4 0x021b08b8 0x00000800 DATA 4 0x021b0004 0x00025564 DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 +#endif diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 2c90a35e2c9..b5e704e99e5 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -16,10 +16,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -27,6 +29,12 @@ #include #include #include "../common/pfuze.h" +#include +#include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -42,11 +50,22 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ PAD_CTL_SRE_FAST) +#define ELAN_INTR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_HYS) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + #define ETH_PHY_POWER IMX_GPIO_NR(4, 21) int dram_init(void) @@ -56,6 +75,19 @@ int dram_init(void) return 0; } +phys_size_t get_effective_memsize(void) +{ + return SZ_512M; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -104,60 +136,263 @@ static iomux_v3_cfg_t const usdhc3_pads[] = { }; #endif +static iomux_v3_cfg_t const elan_pads[] = { + MX6_PAD_EPDC_PWRCTRL2__GPIO_2_9 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWRCTRL3__GPIO_2_10 | MUX_PAD_CTRL(ELAN_INTR_PAD_CTRL), + MX6_PAD_KEY_COL6__GPIO_4_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_EPDC_D0__EPDC_SDDO_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D1__EPDC_SDDO_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D2__EPDC_SDDO_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D3__EPDC_SDDO_3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D4__EPDC_SDDO_4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D5__EPDC_SDDO_5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D6__EPDC_SDDO_6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_D7__EPDC_SDDO_7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_BDR0__EPDC_BDR_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE_0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE1__EPDC_SDCE_1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE2__EPDC_SDCE_2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_EPDC_D0__GPIO_1_7, + MX6_PAD_EPDC_D1__GPIO_1_8, + MX6_PAD_EPDC_D2__GPIO_1_9, + MX6_PAD_EPDC_D3__GPIO_1_10, + MX6_PAD_EPDC_D4__GPIO_1_11, + MX6_PAD_EPDC_D5__GPIO_1_12, + MX6_PAD_EPDC_D6__GPIO_1_13, + MX6_PAD_EPDC_D7__GPIO_1_14, + MX6_PAD_EPDC_GDCLK__GPIO_1_31, + MX6_PAD_EPDC_GDSP__GPIO_2_2, + MX6_PAD_EPDC_GDOE__GPIO_2_0, + MX6_PAD_EPDC_GDRL__GPIO_2_1, + MX6_PAD_EPDC_SDCLK__GPIO_1_23, + MX6_PAD_EPDC_SDOE__GPIO_1_25, + MX6_PAD_EPDC_SDLE__GPIO_1_24, + MX6_PAD_EPDC_SDSHR__GPIO_1_26, + MX6_PAD_EPDC_BDR0__GPIO_2_5, + MX6_PAD_EPDC_SDCE0__GPIO_1_27, + MX6_PAD_EPDC_SDCE1__GPIO_1_28, + MX6_PAD_EPDC_SDCE2__GPIO_1_29, +}; +#endif + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -int board_mmc_get_env_dev(int devno) -{ - return devno; -} +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .sda = { + .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC, + .gp = IMX_GPIO_NR(3, 13), + }, + .scl = { + .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC, + .gp = IMX_GPIO_NR(3, 12), + }, +}; +#endif -#ifdef CONFIG_DM_PMIC_PFUZE100 +#ifdef CONFIG_POWER int power_init_board(void) { - struct udevice *dev; + struct pmic *pfuze; + unsigned int reg; int ret; - u32 dev_id, rev_id, i; - u32 switch_num = 6; - u32 offset = PFUZE100_SW1CMODE; - ret = pmic_get("pfuze100@08", &dev); - if (ret == -ENODEV) - return 0; + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; - if (ret != 0) + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) return ret; - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); - /* set SW1AB staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); /* set SW1C staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x1b); + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + return 0; +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + unsigned int reg; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); - /* Init mode to APS_PFM */ - pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= 0x1b; + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); - for (i = 0; i < switch_num - 1; i++) - pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); return 0; } #endif -#ifdef CONFIG_FEC_MXC +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) +{ + u32 value; + int is_400M; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No pmic!\n"); + return; + } + + /* swith to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM to 1.1V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= 0x20; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* increase VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x28; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(0); + + /* + * MX6SL: VDDARM:1.175V@800M; VDDSOC:1.175V@800M + * VDDARM:0.975V@400M; VDDSOC:1.175V@400M + */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + if (is_400M) + value |= 0x1b; + else + value |= 0x23; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.175V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= 0x23; + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28); + + is_400M = set_anatop_bypass(0); + if (is_400M) + vddarm = 0x1b; + else + vddarm = 0x23; + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23); + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + +#ifdef CONFIG_FEC_MXC static int setup_fec(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -169,6 +404,52 @@ static int setup_fec(void) } #endif +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OTG1 */ + MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL), + /* OTG2 */ + MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -176,15 +457,257 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_MXC_EPDC +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 800, + .vl_row = 600, + .vl_rot = 0, + .vl_pixclock = 26666667, + .vl_left_margin = 8, + .vl_right_margin = 100, + .vl_upper_margin = 4, + .vl_lower_margin = 8, + .vl_hsync = 4, + .vl_vsync = 1, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 419, + .gdsp_offs = 20, + .gdoe_offs = 0, + .gdclk_offs = 5, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRSTAT__GPIO_2_13 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 13), "EPDC PWRSTAT"); + gpio_direction_input(IMX_GPIO_NR(2, 13)); + + /* EPDC_VCOM0 - GPIO2[3] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO_2_3 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 3), "EPDC VCOM0"); + gpio_direction_output(IMX_GPIO_NR(2, 3), 1); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRWAKEUP__GPIO_2_14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 14), "EPDC PWR WAKEUP"); + gpio_direction_output(IMX_GPIO_NR(2, 14), 1); + + /* EPDC_PWRCTRL0 - GPIO2[7] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWRCTRL0__GPIO_2_7 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 7), "EPDC PWRCTRL0"); + gpio_direction_output(IMX_GPIO_NR(2, 7), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + unsigned int reg; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /*** Set pixel clock rates for EPDC ***/ + + /* EPDC AXI clk from PFD_400M, set to 396/2 = 198MHz */ + reg = readl(&ccm_regs->chsccdr); + reg &= ~0x3F000; + reg |= (0x4 << 15) | (1 << 12); + writel(reg, &ccm_regs->chsccdr); + + /* EPDC AXI clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x0030; + writel(reg, &ccm_regs->CCGR3); + + /* EPDC PIX clk from PFD_540M, set to 540/4/5 = 27MHz */ + reg = readl(&ccm_regs->cscdr2); + reg &= ~0x03F000; + reg |= (0x5 << 15) | (4 << 12); + writel(reg, &ccm_regs->cscdr2); + + reg = readl(&ccm_regs->cbcmr); + reg &= ~0x03800000; + reg |= (0x3 << 23); + writel(reg, &ccm_regs->cbcmr); + + /* EPDC PIX clk enable */ + reg = readl(&ccm_regs->CCGR3); + reg |= 0x0C00; + writel(reg, &ccm_regs->CCGR3); + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 13))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 0); +} +#endif + +void setup_elan_pads(void) +{ +#define TOUCH_CS IMX_GPIO_NR(2, 9) +#define TOUCH_INT IMX_GPIO_NR(2, 10) +#define TOUCH_RST IMX_GPIO_NR(4, 4) + imx_iomux_v3_setup_multiple_pads(elan_pads, ARRAY_SIZE(elan_pads)); + gpio_request(TOUCH_CS, "TOUCH CS"); + gpio_request(TOUCH_INT, "TOUCH Interrupt"); + gpio_request(TOUCH_RST, "TOUCH Reset"); +} + int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + + setup_elan_pads(); + #ifdef CONFIG_FEC_MXC setup_fec(); #endif +#ifdef CONFIG_MXC_EPDC + setup_epdc(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + + return 0; +} + +void elan_init(void) +{ + gpio_direction_input(TOUCH_INT); + /* + * If epdc panel not plugged in, gpio_get_value(TOUCH_INT) will + * return 1. And no need to mdelay, which will make i2c operation + * slow. + * If epdc panel plugged in, gpio_get_value(TOUCH_INT) will + * return 0. And elan init flow will be executed. + */ + if (gpio_get_value(TOUCH_INT)) + return; + gpio_direction_output(TOUCH_CS , 1); + gpio_set_value(TOUCH_CS, 0); + gpio_direction_output(TOUCH_RST , 1); + gpio_set_value(TOUCH_RST, 0); + mdelay(10); + gpio_set_value(TOUCH_RST, 1); + gpio_set_value(TOUCH_CS, 1); + mdelay(100); +} + +/* + * This function overwrite the function defined in + * drivers/i2c/mxc_i2c.c, which is a weak symbol + */ +void i2c_force_reset_slave(void) +{ + elan_init(); +} + +int board_late_init(void) +{ + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif return 0; } @@ -195,6 +718,30 @@ int checkboard(void) return 0; } +#ifdef CONFIG_MXC_KPD +#define MX6SL_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_120ohm) + +iomux_v3_cfg_t const mxc_kpd_pads[] = { + (MX6_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL)), + (MX6_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL)), + (MX6_PAD_KEY_COL2__KPP_COL_2 | MUX_PAD_CTRL(NO_PAD_CTRL)), + (MX6_PAD_KEY_COL3__KPP_COL_3 | MUX_PAD_CTRL(NO_PAD_CTRL)), + + (MX6_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), + (MX6_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), + (MX6_PAD_KEY_ROW2__KPP_ROW_2 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), + (MX6_PAD_KEY_ROW3__KPP_ROW_3 | MUX_PAD_CTRL(MX6SL_KEYPAD_CTRL)), +}; +int setup_mxc_kpd(void) +{ + imx_iomux_v3_setup_multiple_pads(mxc_kpd_pads, + ARRAY_SIZE(mxc_kpd_pads)); + + return 0; +} +#endif /*CONFIG_MXC_KPD*/ + #ifdef CONFIG_SPL_BUILD #include #include diff --git a/board/freescale/mx6slevk/plugin.S b/board/freescale/mx6slevk/plugin.S new file mode 100644 index 00000000000..e23146d74a4 --- /dev/null +++ b/board/freescale/mx6slevk/plugin.S @@ -0,0 +1,189 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6slevk_ddr_setting + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x00260324 + str r1, [r0, #0x018] + + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00020000 + str r1, [r0, #0x5c0] + ldr r1, =0x00000000 + str r1, [r0, #0x5b4] + + ldr r1, =0x00000028 + str r1, [r0, #0x338] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x31c] + str r1, [r0, #0x320] + + ldr r1, =0x00000000 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x5ac] + str r1, [r0, #0x5c8] + + ldr r1, =0x00020000 + str r1, [r0, #0x5b0] + + ldr r1, =0x00003030 + str r1, [r0, #0x344] + str r1, [r0, #0x348] + str r1, [r0, #0x34c] + str r1, [r0, #0x350] + + ldr r1, =0x00080000 + str r1, [r0, #0x5d0] + + ldr r1, =0x00000030 + str r1, [r0, #0x5c4] + str r1, [r0, #0x5cc] + str r1, [r0, #0x5d4] + str r1, [r0, #0x5d8] + + str r1, [r0, #0x30c] + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x318] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + + ldr r2, =0x1b4700c7 + str r2, [r0, #0x85c] + + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + + ldr r2, =0x00300000 + str r2, [r0, #0x890] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + + ldr r2, =0x4241444a + str r2, [r0, #0x848] + + ldr r2, =0x3030312b + str r2, [r0, #0x850] + + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + + ldr r2, =0x00000000 + str r2, [r0, #0x840] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33374133 + str r2, [r0, #0x00c] + + ldr r2, =0x00020024 + str r2, [r0, #0x004] + + ldr r2, =0x00100A82 + str r2, [r0, #0x010] + ldr r2, =0x00000093 + str r2, [r0, #0x014] + ldr r2, =0x00001688 + str r2, [r0, #0x018] + ldr r2, =0x0F9F26D2 + str r2, [r0, #0x02c] + + ldr r2, =0x0000020E + str r2, [r0, #0x030] + ldr r2, =0x00190778 + str r2, [r0, #0x038] + ldr r2, =0x00000000 + str r2, [r0, #0x008] + ldr r2, =0x0000004F + str r2, [r0, #0x040] + ldr r2, =0xC3110000 + str r2, [r0, #0x000] + + ldr r2, =0x00008010 + str r2, [r0, #0x01c] + ldr r2, =0x003F8030 + str r2, [r0, #0x01c] + ldr r2, =0xFF0A8030 + str r2, [r0, #0x01c] + ldr r2, =0x82018030 + str r2, [r0, #0x01c] + ldr r2, =0x04028030 + str r2, [r0, #0x01c] + ldr r2, =0x02038030 + str r2, [r0, #0x01c] + ldr r2, =0xFF0A8038 + str r2, [r0, #0x01c] + ldr r2, =0x82018038 + str r2, [r0, #0x01c] + ldr r2, =0x04028038 + str r2, [r0, #0x01c] + ldr r2, =0x02038038 + str r2, [r0, #0x01c] + + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + + ldr r2, =0x00001800 + str r2, [r0, #0x020] + + ldr r2, =0x00000000 + str r2, [r0, #0x818] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x00025564 + str r2, [r0, #0x004] + + ldr r2, =0x00011006 + str r2, [r0, #0x404] + + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6slevk_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sll_val/Kconfig b/board/freescale/mx6sll_val/Kconfig new file mode 100644 index 00000000000..9964eccf895 --- /dev/null +++ b/board/freescale/mx6sll_val/Kconfig @@ -0,0 +1,18 @@ +if TARGET_MX6SLL_VAL + +config SYS_BOARD + default "mx6sll_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6sll_val" + +config LPDDR2_BOARD + bool "set if the board uses the LPDDR2 not default LPDDR3" + +config SYS_TEXT_BASE + default 0x87800000 + +endif diff --git a/board/freescale/mx6sll_val/Makefile b/board/freescale/mx6sll_val/Makefile new file mode 100644 index 00000000000..f3d2f83728f --- /dev/null +++ b/board/freescale/mx6sll_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sll_val.o diff --git a/board/freescale/mx6sll_val/imximage.cfg b/board/freescale/mx6sll_val/imximage.cfg new file mode 100644 index 00000000000..1f5cfa5fb95 --- /dev/null +++ b/board/freescale/mx6sll_val/imximage.cfg @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sll_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E0550 0x00080000 +DATA 4 0x020E0534 0x00000000 +DATA 4 0x020E02AC 0x00000030 +DATA 4 0x020E0548 0x00000030 +DATA 4 0x020E052C 0x00000030 +DATA 4 0x020E0530 0x00020000 +DATA 4 0x020E02B0 0x00003030 +DATA 4 0x020E02B4 0x00003030 +DATA 4 0x020E02B8 0x00003030 +DATA 4 0x020E02BC 0x00003030 +DATA 4 0x020E0540 0x00020000 +DATA 4 0x020E0544 0x00000030 +DATA 4 0x020E054C 0x00000030 +DATA 4 0x020E0554 0x00000030 +DATA 4 0x020E0558 0x00000030 +DATA 4 0x020E0294 0x00000030 +DATA 4 0x020E0298 0x00000030 +DATA 4 0x020E029C 0x00000030 +DATA 4 0x020E02A0 0x00000030 +DATA 4 0x020E02C0 0x00082030 + +DATA 4 0x021B001C 0x00008000 + +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B085c 0x084700C7 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B0848 0x3C3A3C3C +DATA 4 0x021B0850 0x24293625 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B0824 0x33333333 +DATA 4 0x021B0828 0x33333333 + +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B0834 0xf3333333 +DATA 4 0x021B0838 0xf3333333 +DATA 4 0x021B08C0 0x24922492 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B000C 0x53574333 +DATA 4 0x021B0010 0x00100B22 +DATA 4 0x021B0038 0x00170778 +DATA 4 0x021B0014 0x00C700DB +DATA 4 0x021B0018 0x00201718 +DATA 4 0x021B002C 0x0F9F26D2 +DATA 4 0x021B0030 0x009F0E10 +DATA 4 0x021B0040 0x0000005F +DATA 4 0x021B0000 0xC4190000 + +DATA 4 0x021B001C 0x00008050 +DATA 4 0x021B001C 0x00008058 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0x003F8038 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0xFF0A8038 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x04028038 +DATA 4 0x021B001C 0x83018030 +DATA 4 0x021B001C 0x83018038 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B001C 0x01038038 + +DATA 4 0x021B083C 0x20000000 + +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6sll_val/imximage_lpddr2.cfg b/board/freescale/mx6sll_val/imximage_lpddr2.cfg new file mode 100644 index 00000000000..71dc6e132d1 --- /dev/null +++ b/board/freescale/mx6sll_val/imximage_lpddr2.cfg @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sll_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E0550 0x00080000 +DATA 4 0x020E0534 0x00000000 +DATA 4 0x020E02AC 0x00000030 +DATA 4 0x020E0548 0x00000030 +DATA 4 0x020E052C 0x00000030 +DATA 4 0x020E0530 0x00020000 +DATA 4 0x020E02B0 0x00003030 +DATA 4 0x020E02B4 0x00003030 +DATA 4 0x020E02B8 0x00003030 +DATA 4 0x020E02BC 0x00003030 +DATA 4 0x020E0540 0x00020000 +DATA 4 0x020E0544 0x00000030 +DATA 4 0x020E054C 0x00000030 +DATA 4 0x020E0554 0x00000030 +DATA 4 0x020E0558 0x00000030 +DATA 4 0x020E0294 0x00000030 +DATA 4 0x020E0298 0x00000030 +DATA 4 0x020E029C 0x00000030 +DATA 4 0x020E02A0 0x00000030 +DATA 4 0x020E02C0 0x00082030 + +DATA 4 0x021B001C 0x00008000 + +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B085c 0x084700C7 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B0848 0x3A383C40 +DATA 4 0x021B0850 0x242C3020 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B0824 0x33333333 +DATA 4 0x021B0828 0x33333333 + +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B0834 0xf3333333 +DATA 4 0x021B0838 0xf3333333 +DATA 4 0x021B08C0 0x24922492 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B000C 0x53574333 +DATA 4 0x021B0010 0x00100A82 +DATA 4 0x021B0038 0x00170777 +DATA 4 0x021B0014 0x00C70093 +DATA 4 0x021B0018 0x00201708 +DATA 4 0x021B002C 0x0F9F26D2 +DATA 4 0x021B0030 0x009F0E10 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0xC3110000 + +DATA 4 0x021B001C 0x00008050 +DATA 4 0x021B001C 0x00008058 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0x003F8038 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0xFF0A8038 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x04028038 +DATA 4 0x021B001C 0x82018030 +DATA 4 0x021B001C 0x82018038 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B001C 0x01038038 + +DATA 4 0x021B083C 0x20000000 + +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6sll_val/mx6sll_val.c b/board/freescale/mx6sll_val/mx6sll_val.c new file mode 100644 index 00000000000..69778cf0967 --- /dev/null +++ b/board/freescale/mx6sll_val/mx6sll_val.c @@ -0,0 +1,751 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EPD */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_I2C1_SCL__GPIO3_IO12 | PC, + .gp = IMX_GPIO_NR(3, 12), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_I2C1_SDA__GPIO3_IO13 | PC, + .gp = IMX_GPIO_NR(3, 13), + }, +}; + +/* I2C2 for LCD and ADV */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_I2C2_SCL__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_I2C2_SCL__GPIO3_IO14 | PC, + .gp = IMX_GPIO_NR(3, 14), + }, + .sda = { + .i2c_mode = MX6_PAD_I2C2_SDA__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_I2C2_SDA__GPIO3_IO15 | PC, + .gp = IMX_GPIO_NR(3, 15), + }, +}; + +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const wdog_pads[] = { + MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const led_pads[] = { + MX6_PAD_EPDC_VCOM1__GPIO2_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TXD__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RXD__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +/* 8bit SD1 */ +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA4__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA5__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA6__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA7__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD */ + MX6_PAD_KEY_ROW7__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* WP */ + MX6_PAD_GPIO4_IO22__SD1_WP | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* EMMC */ +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* DQS */ + MX6_PAD_GPIO4_IO21__SD2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_SD2_RESET__GPIO4_IO27 | MUX_PAD_CTRL(USDHC_PAD_CTRL | PAD_CTL_LVE), +}; + +/* Wifi SD */ +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD */ + MX6_PAD_REF_CLK_32K__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); + + SETUP_IOMUX_PADS(led_pads); +} + +#ifdef CONFIG_FSL_ESDHC_IMX +static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { + {USDHC1_BASE_ADDR, 0, 8, 1}, + {USDHC2_BASE_ADDR, 0, 8, 0, 1}, /* fixed 1.8v IO voltage for eMMC chip */ + {USDHC3_BASE_ADDR, 0, 4}, +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 27) +#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC2_BASE_ADDR: + ret = 1; + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 2: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* set SW1AB standby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* set SW1C staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value); + value &= ~0x3f; + value |= 0x1b; + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value); + + return 0; +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} + +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS0 */ + MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 11), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 11), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1; +} +#endif +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCD_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCD_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCD_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCD_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCD_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCD_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCD_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCD_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCD_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCD_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_ECSPI1_SCLK__GPIO4_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_PWM1__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) + +{ + int ret; + + ret = enable_lcdif_clock(dev->bus, 1); + if (ret) { + printf("Enable LCDIF clock failed, %d\n", ret); + return; + } + + SETUP_IOMUX_PADS(lcd_pads); + + /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(2, 19), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(2, 19) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(2, 19) , 1); + + gpio_request(IMX_GPIO_NR(4, 8), "lcd pwr en"); + gpio_direction_output(IMX_GPIO_NR(4, 8) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(3, 23), "backlight"); + gpio_direction_output(IMX_GPIO_NR(3, 23) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = MX6SLL_LCDIF_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_EPDC_DATA00__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA01__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA02__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA03__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA04__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA05__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA06__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA07__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA08__EPDC_DATA08 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA09__EPDC_DATA09 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA10__EPDC_DATA10 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA11__EPDC_DATA11 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA12__EPDC_DATA12 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA13__EPDC_DATA13 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA14__EPDC_DATA14 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA15__EPDC_DATA15 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_EPDC_DATA01__GPIO1_IO08, + MX6_PAD_EPDC_DATA02__GPIO1_IO09, + MX6_PAD_EPDC_DATA03__GPIO1_IO10, + MX6_PAD_EPDC_DATA04__GPIO1_IO11, + MX6_PAD_EPDC_DATA05__GPIO1_IO12, + MX6_PAD_EPDC_DATA06__GPIO1_IO13, + MX6_PAD_EPDC_DATA07__GPIO1_IO14, + MX6_PAD_EPDC_DATA08__GPIO1_IO15, + MX6_PAD_EPDC_DATA09__GPIO1_IO16, + MX6_PAD_EPDC_DATA10__GPIO1_IO17, + MX6_PAD_EPDC_DATA11__GPIO1_IO18, + MX6_PAD_EPDC_DATA12__GPIO1_IO19, + MX6_PAD_EPDC_DATA13__GPIO1_IO20, + MX6_PAD_EPDC_DATA14__GPIO1_IO21, + MX6_PAD_EPDC_DATA15__GPIO1_IO22, + MX6_PAD_EPDC_SDCLK__GPIO1_IO23, + MX6_PAD_EPDC_SDLE__GPIO1_IO24, + MX6_PAD_EPDC_SDOE__GPIO1_IO25, + MX6_PAD_EPDC_SDSHR__GPIO1_IO26, + MX6_PAD_EPDC_SDCE0__GPIO1_IO27, + MX6_PAD_EPDC_GDCLK__GPIO1_IO31, + MX6_PAD_EPDC_GDOE__GPIO2_IO00, + MX6_PAD_EPDC_GDRL__GPIO2_IO01, + MX6_PAD_EPDC_GDSP__GPIO2_IO02, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = { + IOMUX_PADS(PAD_EPDC_PWR_STAT__GPIO2_IO13 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EPDC_VCOM0__GPIO2_IO03 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EPDC_PWR_WAKE__GPIO2_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_EPDC_PWR_CTRL0__GPIO2_IO07 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +static void setup_epdc_power(void) +{ + SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads); + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + gpio_request(IMX_GPIO_NR(2, 13), "EPDC_PWRSTAT"); + gpio_direction_input(IMX_GPIO_NR(2, 13)); + + /* EPDC_VCOM0 - GPIO2[03] for VCOM control */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 3), "EPDC_VCOM0"); + gpio_direction_output(IMX_GPIO_NR(2, 3), 1); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 14), "EPDC_PWRWAKEUP"); + gpio_direction_output(IMX_GPIO_NR(2, 14), 1); + + /* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 7), "EPDC_PWRCTRL0"); + gpio_direction_output(IMX_GPIO_NR(2, 7), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + SETUP_IOMUX_PADS(epdc_enable_pads); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + SETUP_IOMUX_PADS(epdc_disable_pads); +} + +static void setup_epdc(void) +{ + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 13))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 0); +} +#endif + + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_KEY_COL4__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_KEY_ROW4__USB_OTG1_OC | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWR_COM__USB_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX6_PAD_KEY_COL5__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ECSPI2_SCLK__USB_OTG2_OC | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EPDC_PWR_IRQ__USB_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + enable_uart_clk(true); + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + +#ifdef CONFIG_MXC_EPDC + enable_epdc_clock(); + setup_epdc(); +#endif + + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + SETUP_IOMUX_PADS(wdog_pads); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ +#ifdef CONFIG_LPDDR2_BOARD + puts("Board: MX6SLL LPDDR2 VAL\n"); +#else + puts("Board: MX6SLL LPDDR3 VAL\n"); +#endif + + return 0; +} diff --git a/board/freescale/mx6sll_val/plugin.S b/board/freescale/mx6sll_val/plugin.S new file mode 100644 index 00000000000..61bc34e5c77 --- /dev/null +++ b/board/freescale/mx6sll_val/plugin.S @@ -0,0 +1,285 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sll_lpddr3_val_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x550] + ldr r1, =0x00000000 + str r1, [r0, #0x534] + ldr r1, =0x00000030 + str r1, [r0, #0x2AC] + str r1, [r0, #0x548] + str r1, [r0, #0x52C] + ldr r1, =0x00020000 + str r1, [r0, #0x530] + ldr r1, =0x00003030 + str r1, [r0, #0x2B0] + str r1, [r0, #0x2B4] + str r1, [r0, #0x2B8] + str r1, [r0, #0x2BC] + + ldr r1, =0x00020000 + str r1, [r0, #0x540] + ldr r1, =0x00000030 + str r1, [r0, #0x544] + str r1, [r0, #0x54C] + str r1, [r0, #0x554] + str r1, [r0, #0x558] + str r1, [r0, #0x294] + str r1, [r0, #0x298] + str r1, [r0, #0x29C] + str r1, [r0, #0x2A0] + + ldr r1, =0x00082030 + str r1, [r0, #0x2C0] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x084700C7 + str r1, [r0, #0x85C] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x3C3A3C3C + str r1, [r0, #0x848] + ldr r1, =0x24293625 + str r1, [r0, #0x850] + + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + str r1, [r0, #0x824] + str r1, [r0, #0x828] + + ldr r1, =0xf3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + str r1, [r0, #0x834] + str r1, [r0, #0x838] + + ldr r1, =0x24922492 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x53574333 + str r1, [r0, #0x00C] + ldr r1, =0x00100B22 + str r1, [r0, #0x010] + ldr r1, =0x00170778 + str r1, [r0, #0x038] + ldr r1, =0x00C700DB + str r1, [r0, #0x014] + ldr r1, =0x00201718 + str r1, [r0, #0x018] + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x02C] + ldr r1, =0x009F0E10 + str r1, [r0, #0x030] + ldr r1, =0x0000005F + str r1, [r0, #0x040] + ldr r1, =0xC4190000 + str r1, [r0, #0x000] + + ldr r1, =0x00008050 + str r1, [r0, #0x01C] + ldr r1, =0x00008058 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0x003F8038 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x04028038 + str r1, [r0, #0x01C] + ldr r1, =0x83018030 + str r1, [r0, #0x01C] + ldr r1, =0x83018038 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x01038038 + str r1, [r0, #0x01C] + + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6sll_lpddr2_val_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x550] + ldr r1, =0x00000000 + str r1, [r0, #0x534] + ldr r1, =0x00000030 + str r1, [r0, #0x2AC] + str r1, [r0, #0x548] + str r1, [r0, #0x52C] + ldr r1, =0x00020000 + str r1, [r0, #0x530] + ldr r1, =0x00003030 + str r1, [r0, #0x2B0] + str r1, [r0, #0x2B4] + str r1, [r0, #0x2B8] + str r1, [r0, #0x2BC] + + ldr r1, =0x00020000 + str r1, [r0, #0x540] + ldr r1, =0x00000030 + str r1, [r0, #0x544] + str r1, [r0, #0x54C] + str r1, [r0, #0x554] + str r1, [r0, #0x558] + str r1, [r0, #0x294] + str r1, [r0, #0x298] + str r1, [r0, #0x29C] + str r1, [r0, #0x2A0] + + ldr r1, =0x00082030 + str r1, [r0, #0x2C0] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x084700C7 + str r1, [r0, #0x85C] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x3A383C40 + str r1, [r0, #0x848] + ldr r1, =0x242C3020 + str r1, [r0, #0x850] + + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + str r1, [r0, #0x824] + str r1, [r0, #0x828] + + ldr r1, =0xf3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + str r1, [r0, #0x834] + str r1, [r0, #0x838] + + ldr r1, =0x24922492 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x53574333 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170777 + str r1, [r0, #0x038] + ldr r1, =0x00C70093 + str r1, [r0, #0x014] + ldr r1, =0x00201708 + str r1, [r0, #0x018] + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x02C] + ldr r1, =0x009F0E10 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0xC3110000 + str r1, [r0, #0x000] + + ldr r1, =0x00008050 + str r1, [r0, #0x01C] + ldr r1, =0x00008058 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0x003F8038 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x04028038 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x82018038 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x01038038 + str r1, [r0, #0x01C] + + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_LPDDR2_BOARD) + imx6sll_lpddr2_val_setting +#else + imx6sll_lpddr3_val_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig index 4ba9bbf1418..7c179c72f63 100644 --- a/board/freescale/mx6sllevk/Kconfig +++ b/board/freescale/mx6sllevk/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sllevk" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6sllevk/imximage.cfg b/board/freescale/mx6sllevk/imximage.cfg index 74b3a907bf2..3d36dc6e5f0 100644 --- a/board/freescale/mx6sllevk/imximage.cfg +++ b/board/freescale/mx6sllevk/imximage.cfg @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Refer docs/README.imxmage for more details about how-to configure * and create imximage boot image @@ -52,6 +53,11 @@ DATA 4 0x020c4078 0xffffffff DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + DATA 4 0x020E0550 0x00080000 DATA 4 0x020E0534 0x00000000 DATA 4 0x020E02AC 0x00000030 diff --git a/board/freescale/mx6sllevk/mx6sllevk.c b/board/freescale/mx6sllevk/mx6sllevk.c index b4fddafe640..22e43dffe7c 100644 --- a/board/freescale/mx6sllevk/mx6sllevk.c +++ b/board/freescale/mx6sllevk/mx6sllevk.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP */ #include @@ -17,17 +18,32 @@ #include #include #include +#include #include +#include #include #include #include "../common/pfuze.h" +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include +#include + DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -58,7 +74,7 @@ int power_init_board(void) u32 switch_num = 6; u32 offset = PFUZE100_SW1CMODE; - ret = pmic_get("pfuze100@08", &dev); + ret = pmic_get("pfuze100@8", &dev); if (ret == -ENODEV) return 0; @@ -92,6 +108,259 @@ int power_init_board(void) } #endif +#ifdef CONFIG_DM_VIDEO +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_KEY_ROW5__GPIO4_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_PWM1__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static int setup_lcd(void) +{ + int ret; + + ret = enable_lcdif_clock(MX6SLL_LCDIF_BASE_ADDR, 1); + if (ret) { + printf("Enable LCDIF clock failed, %d\n", ret); + return -EPERM; + } + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(2, 19), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(2, 19) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(2, 19) , 1); + + gpio_request(IMX_GPIO_NR(4, 3), "lcd pwr en"); + gpio_direction_output(IMX_GPIO_NR(4, 3) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(3, 23), "backlight"); + gpio_direction_output(IMX_GPIO_NR(3, 23) , 1); + + return 0; +} +#else +static inline int setup_lcd(void) { return 0; } +#endif + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_EPDC_DATA00__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA01__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA02__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA03__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA04__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA05__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA06__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA07__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA08__EPDC_DATA08 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA09__EPDC_DATA09 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA10__EPDC_DATA10 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA11__EPDC_DATA11 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA12__EPDC_DATA12 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA13__EPDC_DATA13 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA14__EPDC_DATA14 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_DATA15__EPDC_DATA15 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCLK__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_EPDC_DATA01__GPIO1_IO08, + MX6_PAD_EPDC_DATA02__GPIO1_IO09, + MX6_PAD_EPDC_DATA03__GPIO1_IO10, + MX6_PAD_EPDC_DATA04__GPIO1_IO11, + MX6_PAD_EPDC_DATA05__GPIO1_IO12, + MX6_PAD_EPDC_DATA06__GPIO1_IO13, + MX6_PAD_EPDC_DATA07__GPIO1_IO14, + MX6_PAD_EPDC_DATA08__GPIO1_IO15, + MX6_PAD_EPDC_DATA09__GPIO1_IO16, + MX6_PAD_EPDC_DATA10__GPIO1_IO17, + MX6_PAD_EPDC_DATA11__GPIO1_IO18, + MX6_PAD_EPDC_DATA12__GPIO1_IO19, + MX6_PAD_EPDC_DATA13__GPIO1_IO20, + MX6_PAD_EPDC_DATA14__GPIO1_IO21, + MX6_PAD_EPDC_DATA15__GPIO1_IO22, + MX6_PAD_EPDC_SDCLK__GPIO1_IO23, + MX6_PAD_EPDC_SDLE__GPIO1_IO24, + MX6_PAD_EPDC_SDOE__GPIO1_IO25, + MX6_PAD_EPDC_SDSHR__GPIO1_IO26, + MX6_PAD_EPDC_SDCE0__GPIO1_IO27, + MX6_PAD_EPDC_GDCLK__GPIO1_IO31, + MX6_PAD_EPDC_GDOE__GPIO2_IO00, + MX6_PAD_EPDC_GDRL__GPIO2_IO01, + MX6_PAD_EPDC_GDSP__GPIO2_IO02, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 13), "epdc_pwrstat"); + gpio_direction_input(IMX_GPIO_NR(2, 13)); + + /* EPDC_VCOM0 - GPIO2[03] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO2_IO03 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 3), "epdc_vcom0"); + gpio_direction_output(IMX_GPIO_NR(2, 3), 1); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 14), "epdc_pwr_wake"); + gpio_direction_output(IMX_GPIO_NR(2, 14), 1); + + /* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(2, 7), "epdc_pwr_ctrl0"); + gpio_direction_output(IMX_GPIO_NR(2, 7), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[13] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_STAT__GPIO2_IO13 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO2[03] for VCOM control */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_VCOM0__GPIO2_IO03 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO2[14] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_WAKE__GPIO2_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO2[07] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX6_PAD_EPDC_PWR_CTRL0__GPIO2_IO07 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 13))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(2, 14), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(2, 3), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(2, 7), 0); +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -104,13 +373,32 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_MXC_EPDC + enable_epdc_clock(); + setup_epdc(); +#endif + return 0; } int board_late_init(void) { + + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + setup_lcd(); + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } @@ -120,13 +408,3 @@ int checkboard(void) return 0; } - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int mmc_map_to_kernel_blk(int devno) -{ - return devno; -} diff --git a/board/freescale/mx6sx_17x17_val/Kconfig b/board/freescale/mx6sx_17x17_val/Kconfig new file mode 100644 index 00000000000..07a3e7a5def --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/Kconfig @@ -0,0 +1,23 @@ +if TARGET_MX6SX_17X17_VAL || TARGET_MX6SX_14X14_VAL + +config SYS_BOARD + default "mx6sx_17x17_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6sx_17x17_val" + +config SYS_TEXT_BASE + default 0x87800000 + +config LPDDR2_BOARD + bool "Select for the board using LPDDR2 not default DDR3" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx6sx_17x17_val/Makefile b/board/freescale/mx6sx_17x17_val/Makefile new file mode 100644 index 00000000000..b44bb36c4fd --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sx_17x17_val.o diff --git a/board/freescale/mx6sx_17x17_val/imximage.cfg b/board/freescale/mx6sx_17x17_val/imximage.cfg new file mode 100644 index 00000000000..0718e230f39 --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/imximage.cfg @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_17x17_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x00270025 +DATA 4 0x021b0810 0x001B001E +DATA 4 0x021b083c 0x4144013C +DATA 4 0x021b0840 0x01300128 +DATA 4 0x021b0848 0x4044464A +DATA 4 0x021b0850 0x3A383C34 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00068031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00011117 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_17x17_val/imximage_wp.cfg b/board/freescale/mx6sx_17x17_val/imximage_wp.cfg new file mode 100644 index 00000000000..a3328400496 --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/imximage_wp.cfg @@ -0,0 +1,118 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b080c 0x002E003C +DATA 4 0x021b0810 0x001A003F +DATA 4 0x021b083c 0x41480150 +DATA 4 0x021b0840 0x012C0150 +DATA 4 0x021b0848 0x40404646 +DATA 4 0x021b0850 0x38363C32 +DATA 4 0x021b08c0 0x2492244A +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 +DATA 4 0x021b001c 0x04008032 +DATA 4 0x021b001c 0x00008033 +DATA 4 0x021b001c 0x00068031 +DATA 4 0x021b001c 0x05208030 +DATA 4 0x021b001c 0x04008040 +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 diff --git a/board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg b/board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg new file mode 100644 index 00000000000..beb7d2e906f --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_17x17_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020c4018 0x00260324 + +DATA 4 0x020e0618 0x00080000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000028 +DATA 4 0x020e02fc 0x00000028 +DATA 4 0x020e05f4 0x00000028 +DATA 4 0x020e0340 0x00000028 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000000 +DATA 4 0x020e0314 0x00000000 +DATA 4 0x020e0614 0x00000028 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00003028 +DATA 4 0x020e0334 0x00003028 +DATA 4 0x020e0338 0x00003028 +DATA 4 0x020e033c 0x00003028 + +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 + +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 + +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00380000 +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +DATA 4 0x021b082c 0x51111111 +DATA 4 0x021b0830 0x51111111 +DATA 4 0x021b0834 0x51111111 +DATA 4 0x021b0838 0x51111111 + +DATA 4 0x021b0848 0x42424244 + +DATA 4 0x021b0850 0x2E30322E +DATA 4 0x021b08c0 0x2492244A +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x0 + +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A42 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001748 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 + +DATA 4 0x021b001c 0x00008010 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x01038030 + +DATA 4 0x021b001c 0x00008018 +DATA 4 0x021b001c 0x003f8038 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x01038038 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 + +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c b/board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c new file mode 100644 index 00000000000..3d1390cc0f3 --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/mx6sx_17x17_val.c @@ -0,0 +1,803 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *pfuze; + unsigned int reg; + int ret; + + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11750); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } + +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750)); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifndef CONFIG_MXC_SPI +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /*CD pin*/ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + /* AR8031 PHY Reset. For validation board, silder the resistance */ + MX6_PAD_QSPI1A_SS0_B__GPIO4_IO_22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + SETUP_IOMUX_PADS(fec1_pads); +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) + +#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /*always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /*always present */ + break; + } + + return ret; +} + +#ifdef CONFIG_MXC_SPI +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SD3 (SDB) + * mmc1 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} + +#else +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SD2 (SDA) + * mmc1 SD3 (SDB) + * mmc2 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc2_pads); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + SETUP_IOMUX_PADS(usdhc3_pads); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_direction_input(USDHC3_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: + SETUP_IOMUX_PADS(usdhc4_pads); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +iomux_v3_cfg_t eimnor_pads[] = { + MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , + MX6_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_NAND_CE0_B__WEIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), + + MX6_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), +}; +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00610089, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x1c022000, WEIM_BASE_ADDR + 0x008); + writel(0x00000000, WEIM_BASE_ADDR + 0x00c); + writel(0x1404a38e, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} +#endif + +#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(gpmi_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +#define MAX7322_I2C_ADDR 0x68 +#define MAX7322_I2C_BUS 1 + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + unsigned char value = 1; + + /* clear gpr1[13], gpr1[17] to select anatop clock */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + +/* Reset AR8031 PHY */ + gpio_request(IMX_GPIO_NR(4, 22), "ar8031 reset"); + gpio_direction_output(IMX_GPIO_NR(4, 22) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(4, 22), 1); + +#ifdef CONFIG_DM_I2C + struct udevice *bus, *dev; + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus); + if (ret) { + printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret); + return ret; + } + + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev); + if (ret) { + printf("MAX7322 Not found, ret = %d\n", ret); + return ret; + } + + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + ret = dm_i2c_write(dev, 0, &value, 1); + if (ret) { + printf("MAX7322 write failed, ret = %d\n", ret); + return ret; + } +#else + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(MAX7322_I2C_BUS); + + if (!i2c_probe(MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } +#endif + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifdef CONFIG_FEC_ENABLE_MAX7322 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); +#endif + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +iomux_v3_cfg_t const usb_otg_pads[] = { + /*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +static void setup_usb(void) +{ + SETUP_IOMUX_PADS(usb_otg_pads); +} + +int board_usb_phy_mode(int port) +{ + return USB_INIT_HOST; +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port >= 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x60, 0x38, 0x00, 0x00)}, + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)}, + {"nand", MAKE_CFGVAL(0x80, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_MX6SX_14X14_VAL + puts("Board: MX6SX 14x14 VAL\n"); +#else + puts("Board: MX6SX 17x17 VAL\n"); +#endif + + return 0; +} diff --git a/board/freescale/mx6sx_17x17_val/plugin.S b/board/freescale/mx6sx_17x17_val/plugin.S new file mode 100644 index 00000000000..1b739b3fae3 --- /dev/null +++ b/board/freescale/mx6sx_17x17_val/plugin.S @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_17x17_ddr3_evk_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00270025 + str r2, [r0, #0x80c] + ldr r2, =0x001B001E + str r2, [r0, #0x810] + ldr r2, =0x4144013C + str r2, [r0, #0x83c] + ldr r2, =0x01300128 + str r2, [r0, #0x840] + ldr r2, =0x4044464A + str r2, [r0, #0x848] + ldr r2, =0x3A383C34 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000005f + str r2, [r0, #0x040] + ldr r2, =0x84190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6sx_14x14_lpddr2_val_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000028 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + str r1, [r0, #0x310] + str r1, [r0, #0x314] + ldr r1, =0x00000028 + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00003028 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000028 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + ldr r2, =0x1b4700c7 + str r2, [r0, #0x85c] + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00380000 + str r2, [r0, #0x890] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x51111111 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + + ldr r2, =0x42424244 + str r2, [r0, #0x848] + ldr r2, =0x2E30322E + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33374133 + str r2, [r0, #0x00c] + ldr r2, =0x00020024 + str r2, [r0, #0x004] + ldr r2, =0x00100A42 + str r2, [r0, #0x010] + ldr r2, =0x00000093 + str r2, [r0, #0x014] + ldr r2, =0x00001748 + str r2, [r0, #0x018] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x02c] + ldr r2, =0x0000020e + str r2, [r0, #0x030] + ldr r2, =0x00190778 + str r2, [r0, #0x038] + ldr r2, =0x00000000 + str r2, [r0, #0x008] + ldr r2, =0x0000004f + str r2, [r0, #0x040] + ldr r2, =0xc3110000 + str r2, [r0, #0x000] + + ldr r2, =0x00008010 + str r2, [r0, #0x01c] + ldr r2, =0x003f8030 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x01c] + ldr r2, =0x82018030 + str r2, [r0, #0x01c] + ldr r2, =0x04028030 + str r2, [r0, #0x01c] + ldr r2, =0x01038030 + str r2, [r0, #0x01c] + + ldr r2, =0x00008018 + str r2, [r0, #0x01c] + ldr r2, =0x003f8038 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8038 + str r2, [r0, #0x01c] + ldr r2, =0x82018038 + str r2, [r0, #0x01c] + ldr r2, =0x04028038 + str r2, [r0, #0x01c] + ldr r2, =0x01038038 + str r2, [r0, #0x01c] + + ldr r2, =0x00001800 + str r2, [r0, #0x020] + ldr r2, =0x00000000 + str r2, [r0, #0x818] + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm + +.macro imx6_ddr_setting +#if defined(CONFIG_TARGET_MX6SX_14X14_VAL) && defined (CONFIG_LPDDR2_BOARD) + imx6sx_14x14_lpddr2_val_ddr_setting +#else + imx6sx_17x17_ddr3_evk_ddr_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sx_19x19_val/Kconfig b/board/freescale/mx6sx_19x19_val/Kconfig new file mode 100644 index 00000000000..2e3f14fc252 --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/Kconfig @@ -0,0 +1,23 @@ +if TARGET_MX6SX_19X19_VAL + +config SYS_BOARD + default "mx6sx_19x19_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6sx_19x19_val" + +config SYS_TEXT_BASE + default 0x87800000 + +config LPDDR2_BOARD + bool "Select for the board using LPDDR2 not default DDR3" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx6sx_19x19_val/Makefile b/board/freescale/mx6sx_19x19_val/Makefile new file mode 100644 index 00000000000..eec06e97eba --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6sx_19x19_val.o diff --git a/board/freescale/mx6sx_19x19_val/imximage.cfg b/board/freescale/mx6sx_19x19_val/imximage.cfg new file mode 100644 index 00000000000..a90fed967bd --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/imximage.cfg @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_19x19_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* IOMUX */ +/* DDR IO TYPE */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 + +/* CLOCK */ +DATA 4 0x020e032c 0x00000030 + +/* ADDRESS */ +DATA 4 0x020e0300 0x00000030 +DATA 4 0x020e02fc 0x00000030 +DATA 4 0x020e05f4 0x00000030 + +/* CONTROL */ +DATA 4 0x020e0340 0x00000030 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000030 +DATA 4 0x020e0314 0x00000030 +DATA 4 0x020e0614 0x00000030 + +/* DATA STROBE */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000030 +DATA 4 0x020e0334 0x00000030 +DATA 4 0x020e0338 0x00000030 +DATA 4 0x020e033c 0x00000030 + +/* DATA */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000030 +DATA 4 0x020e0610 0x00000030 +DATA 4 0x020e061c 0x00000030 +DATA 4 0x020e0620 0x00000030 +DATA 4 0x020e02ec 0x00000030 +DATA 4 0x020e02f0 0x00000030 +DATA 4 0x020e02f4 0x00000030 +DATA 4 0x020e02f8 0x00000030 + +/* Calibrations */ +/* ZQ */ +DATA 4 0x021b0800 0xa1390003 +/* write leveling */ +DATA 4 0x021b080c 0x002C003D +DATA 4 0x021b0810 0x00110046 + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x4160016C +DATA 4 0x021b0840 0x013C016C + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x46424446 +DATA 4 0x021b0850 0x3A3C3C3A + +DATA 4 0x021b08c0 0x2492244A + +/* read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +/* Complete calibration by forced measurment */ +DATA 4 0x021b08b8 0x00000800 + +/* MMDC init */ +/* in DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333030 +DATA 4 0x021b000c 0x676b52f3 +DATA 4 0x021b0010 0xb66d8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000007f +DATA 4 0x021b0000 0x85190000 + +/* Initialize CS0: MT41K256M16HA-125 */ +/* MR2 */ +DATA 4 0x021b001c 0x04008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00068031 +/* MR0 */ +DATA 4 0x021b001c 0x05208030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 + +/* final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00000800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b0004 0x0002556d +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg b/board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg new file mode 100644 index 00000000000..9cd33360f4a --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sx_19x19_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020e0618 0x00080000 +DATA 4 0x020e05fc 0x00000000 +DATA 4 0x020e032c 0x00000030 + +DATA 4 0x020e0300 0x00000028 +DATA 4 0x020e02fc 0x00000028 +DATA 4 0x020e05f4 0x00000028 +DATA 4 0x020e0340 0x00000028 +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000000 +DATA 4 0x020e0314 0x00000000 +DATA 4 0x020e0614 0x00000028 + +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00003028 +DATA 4 0x020e0334 0x00003028 +DATA 4 0x020e0338 0x00003028 +DATA 4 0x020e033c 0x00003028 +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b085c 0x1b4700c7 +DATA 4 0x021b0800 0xa1390003 +DATA 4 0x021b0890 0x00380000 +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b082c 0x51111111 +DATA 4 0x021b0830 0x51111111 +DATA 4 0x021b0834 0x51111111 +DATA 4 0x021b0838 0x51111111 +DATA 4 0x021b0848 0x42424244 +DATA 4 0x021b0850 0x2E30322E +DATA 4 0x021b08c0 0x2492244A +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b08b8 0x00000800 + +DATA 4 0x021b000c 0x33374133 +DATA 4 0x021b0004 0x00020024 +DATA 4 0x021b0010 0x00100A42 +DATA 4 0x021b0014 0x00000093 +DATA 4 0x021b0018 0x00001748 +DATA 4 0x021b002c 0x0f9f26d2 +DATA 4 0x021b0030 0x0000020e +DATA 4 0x021b0038 0x00190778 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b0040 0x0000004f +DATA 4 0x021b0000 0xc3110000 + +DATA 4 0x021b001c 0x00008010 +DATA 4 0x021b001c 0x003f8030 +DATA 4 0x021b001c 0xff0a8030 +DATA 4 0x021b001c 0x82018030 +DATA 4 0x021b001c 0x04028030 +DATA 4 0x021b001c 0x01038030 + +DATA 4 0x021b001c 0x00008018 +DATA 4 0x021b001c 0x003f8038 +DATA 4 0x021b001c 0xff0a8038 +DATA 4 0x021b001c 0x82018038 +DATA 4 0x021b001c 0x04028038 +DATA 4 0x021b001c 0x01038038 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b0800 0xa1310003 +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b001c 0x00000000 + +#endif diff --git a/board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c b/board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c new file mode 100644 index 00000000000..15dbd2796bb --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/mx6sx_19x19_val.c @@ -0,0 +1,830 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_MED | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define WEIM_NOR_PAD_CTRL2 (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + struct pmic *pfuze; + unsigned int reg; + int ret; + + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11750); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } + +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750)); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lvds_ctrl_pads[] = { + /* CABC enable */ + MX6_PAD_KEY_ROW1__GPIO2_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_GPIO1_IO12__GPIO1_IO_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_lvds(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + enable_lvds_bridge(dev->bus); + + SETUP_IOMUX_PADS(lvds_ctrl_pads); + + /* Enable CABC */ + gpio_request(IMX_GPIO_NR(2, 16), "cabc enable"); + gpio_direction_output(IMX_GPIO_NR(2, 16) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 12), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); +} + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 27), "lcd pwr"); + gpio_direction_output(IMX_GPIO_NR(3, 27) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 12), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = LCDIF2_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .enable = do_enable_lvds, + .detect = NULL, + .mode = { + .name = "Hannstar-XGA", + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = MX6SX_LCDIF1_BASE_ADDR, + .pixfmt = 24, + .addr = 0, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + /* AR8031 PHY Reset. For arm2 board, silder the resistance */ + MX6_PAD_SD4_DATA4__GPIO6_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + SETUP_IOMUX_PADS(fec1_pads); +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_60ohm) + +#define QSPI_PAD_CTRL2 (QSPI_PAD_CTRL1 | PAD_CTL_DSE_34ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI2_A_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI2_A_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI2_A_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI2_A_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI2_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_ALE__QSPI2_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA01__QSPI2_B_DATA_0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI2_B_DATA_1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI2_B_DATA_2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_RE_B__QSPI2_B_DATA_3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI2_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI2_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + + /* Set the clock */ + enable_qspi_clk(1); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Assume boot SD always present */ +} +int board_mmc_init(struct bd_info *bis) +{ + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 (SDA) + */ + SETUP_IOMUX_PADS(usdhc1_pads); + + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +iomux_v3_cfg_t eimnor_pads[] = { + MX6_PAD_QSPI1A_SCLK__WEIM_DATA_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_SS0_B__WEIM_DATA_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_SS1_B__WEIM_DATA_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA3__WEIM_DATA_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA2__WEIM_DATA_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA1__WEIM_DATA_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DATA0__WEIM_DATA_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1A_DQS__WEIM_DATA_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_SCLK__WEIM_DATA_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_SS0_B__WEIM_DATA_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_SS1_B__WEIM_DATA_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA3__WEIM_DATA_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA2__WEIM_DATA_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA1__WEIM_DATA_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DATA0__WEIM_DATA_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + MX6_PAD_QSPI1B_DQS__WEIM_DATA_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL2), + + MX6_PAD_NAND_DATA00__WEIM_AD_0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__WEIM_AD_1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__WEIM_AD_2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__WEIM_AD_3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__WEIM_AD_4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__WEIM_AD_5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__WEIM_AD_6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__WEIM_AD_7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA08__WEIM_AD_8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA09__WEIM_AD_9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA10__WEIM_AD_10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA11__WEIM_AD_11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) , + MX6_PAD_LCD1_DATA12__WEIM_AD_12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA13__WEIM_AD_13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA14__WEIM_AD_14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA15__WEIM_AD_15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA16__WEIM_ADDR_16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA17__WEIM_ADDR_17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA18__WEIM_ADDR_18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA19__WEIM_ADDR_19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA20__WEIM_ADDR_20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA21__WEIM_ADDR_21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA22__WEIM_ADDR_22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA23__WEIM_ADDR_23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA03__WEIM_ADDR_24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA04__WEIM_ADDR_25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD1_DATA05__WEIM_ADDR_26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_NAND_CE1_B__WEIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_RE_B__WEIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_WE_B__WEIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), + + MX6_PAD_NAND_ALE__WEIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), +}; +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00010181, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x0a020000, WEIM_BASE_ADDR + 0x008); + writel(0x0000c000, WEIM_BASE_ADDR + 0x00c); + writel(0x0804a240, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} +#endif + +#ifdef CONFIG_NAND_MXS +iomux_v3_cfg_t gpmi_pads[] = { + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(gpmi_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_FEC_MXC + +#define MAX7322_I2C_ADDR 0x68 +#define MAX7322_I2C_BUS 1 + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + unsigned char value = 1; + + /* clear gpr1[13], gpr1[17] to select anatop clock */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) + return ret; + + /* Reset AR8031 PHY */ + gpio_request(IMX_GPIO_NR(6, 18), "ar8031 reset"); + gpio_direction_output(IMX_GPIO_NR(6, 18) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(6, 18), 1); + +#ifdef CONFIG_DM_I2C + struct udevice *bus, *dev; + ret = uclass_get_device_by_seq(UCLASS_I2C, MAX7322_I2C_BUS - 1, &bus); + if (ret) { + printf("Get i2c bus %u failed, ret = %d\n", MAX7322_I2C_BUS - 1, ret); + return ret; + } + + ret = dm_i2c_probe(bus, MAX7322_I2C_ADDR, 0, &dev); + if (ret) { + printf("MAX7322 Not found, ret = %d\n", ret); + return ret; + } + + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + ret = dm_i2c_write(dev, 0, &value, 1); + if (ret) { + printf("MAX7322 write failed, ret = %d\n", ret); + return ret; + } +#else + /* This is needed to drive the pads to 1.8V instead of 1.5V */ + i2c_set_bus_num(MAX7322_I2C_BUS); + + if (!i2c_probe(MAX7322_I2C_ADDR)) { + /* Write 0x1 to enable O0 output, this device has no addr */ + /* hence addr length is 0 */ + value = 0x1; + if (i2c_write(MAX7322_I2C_ADDR, 0, 0, &value, 1)) + printf("MAX7322 write failed\n"); + } else { + printf("MAX7322 Not found\n"); + } +#endif + + return 0; +} + +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ +#ifdef CONFIG_FEC_ENABLE_MAX7322 + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); +#endif + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + SETUP_IOMUX_PADS(usb_otg_pads); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port >= 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, + {"spinor", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x0B)}, + {"eimnor", MAKE_CFGVAL(0x00, 0x80, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6SX 19x19 ARM2\n"); + + return 0; +} diff --git a/board/freescale/mx6sx_19x19_val/plugin.S b/board/freescale/mx6sx_19x19_val/plugin.S new file mode 100644 index 00000000000..0e6b8066247 --- /dev/null +++ b/board/freescale/mx6sx_19x19_val/plugin.S @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_19x19_ddr3_val_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x002C003D + str r2, [r0, #0x80c] + ldr r2, =0x00110046 + str r2, [r0, #0x810] + ldr r2, =0x4160016C + str r2, [r0, #0x83c] + ldr r2, =0x013C016C + str r2, [r0, #0x840] + ldr r2, =0x46424446 + str r2, [r0, #0x848] + ldr r2, =0x3A3C3C3A + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000007f + str r2, [r0, #0x040] + ldr r2, =0x85190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00022227 + str r2, [r0, #0x818] + ldr r2, =0x0002556d + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm + +.macro imx6sx_19x19_lpddr2_val_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000028 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + str r1, [r0, #0x310] + str r1, [r0, #0x314] + ldr r1, =0x00000028 + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00003028 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000028 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0x00008000 + str r2, [r0, #0x1c] + ldr r2, =0x1b4700c7 + str r2, [r0, #0x85c] + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00380000 + str r2, [r0, #0x890] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x51111111 + str r2, [r0, #0x82c] + str r2, [r0, #0x830] + str r2, [r0, #0x834] + str r2, [r0, #0x838] + + ldr r2, =0x42424244 + str r2, [r0, #0x848] + ldr r2, =0x2E30322E + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + ldr r2, =0x20000000 + str r2, [r0, #0x83c] + ldr r2, =0x00000000 + str r2, [r0, #0x840] + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + + ldr r2, =0x33374133 + str r2, [r0, #0x00c] + ldr r2, =0x00020024 + str r2, [r0, #0x004] + ldr r2, =0x00100A42 + str r2, [r0, #0x010] + ldr r2, =0x00000093 + str r2, [r0, #0x014] + ldr r2, =0x00001748 + str r2, [r0, #0x018] + ldr r2, =0x0f9f26d2 + str r2, [r0, #0x02c] + ldr r2, =0x0000020e + str r2, [r0, #0x030] + ldr r2, =0x00190778 + str r2, [r0, #0x038] + ldr r2, =0x00000000 + str r2, [r0, #0x008] + ldr r2, =0x0000004f + str r2, [r0, #0x040] + ldr r2, =0xc3110000 + str r2, [r0, #0x000] + + ldr r2, =0x00008010 + str r2, [r0, #0x01c] + ldr r2, =0x003f8030 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8030 + str r2, [r0, #0x01c] + ldr r2, =0x82018030 + str r2, [r0, #0x01c] + ldr r2, =0x04028030 + str r2, [r0, #0x01c] + ldr r2, =0x01038030 + str r2, [r0, #0x01c] + + ldr r2, =0x00008018 + str r2, [r0, #0x01c] + ldr r2, =0x003f8038 + str r2, [r0, #0x01c] + ldr r2, =0xff0a8038 + str r2, [r0, #0x01c] + ldr r2, =0x82018038 + str r2, [r0, #0x01c] + ldr r2, =0x04028038 + str r2, [r0, #0x01c] + ldr r2, =0x01038038 + str r2, [r0, #0x01c] + + ldr r2, =0x00001800 + str r2, [r0, #0x020] + ldr r2, =0x00000000 + str r2, [r0, #0x818] + ldr r2, =0xa1310003 + str r2, [r0, #0x800] + ldr r2, =0x00025576 + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_LPDDR2_BOARD) + imx6sx_19x19_lpddr2_val_ddr_setting +#else + imx6sx_19x19_ddr3_val_ddr_setting +#endif + +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig index ae2ea024394..5e9c06cde0d 100644 --- a/board/freescale/mx6sxsabreauto/Kconfig +++ b/board/freescale/mx6sxsabreauto/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sxsabreauto" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6sxsabreauto/imximage.cfg b/board/freescale/mx6sxsabreauto/imximage.cfg index 4a0bcc5f7d6..cd9f5dc46ce 100644 --- a/board/freescale/mx6sxsabreauto/imximage.cfg +++ b/board/freescale/mx6sxsabreauto/imximage.cfg @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. */ #define __ASSEMBLY__ @@ -15,7 +15,22 @@ IMAGE_VERSION 2 * spi/sd/nand/onenand, qspi/nor */ +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sxsabreauto/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif /* * Device Configuration Data (DCD) @@ -39,6 +54,11 @@ DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff DATA 4 0x020c4084 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + /* IOMUX - DDR IO Type */ DATA 4 0x020e0618 0x000c0000 DATA 4 0x020e05fc 0x00000000 @@ -133,3 +153,4 @@ DATA 4 0x021b0818 0x00022227 DATA 4 0x021b0004 0x0002556d DATA 4 0x021b0404 0x00011006 DATA 4 0x021b001c 0x00000000 +#endif diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 7340a344023..5462cf8c531 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2018 nxp * * Author: Ye Li */ @@ -30,6 +31,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -52,6 +54,13 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SRE_FAST) #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -64,23 +73,6 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; -static iomux_v3_cfg_t const fec2_pads[] = { - MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -88,27 +80,28 @@ static void setup_iomux_uart(void) static int setup_fec(void) { + int ret; struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - - return enable_fec_anatop_clock(1, ENET_125MHZ); -} + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); -int board_eth_init(struct bd_info *bis) -{ - int ret; + /* Use 125M anatop REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); - imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); - setup_fec(); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); + if (ret) { + printf("enable fec0 clock failed\n"); + return ret; + } - ret = fecmxc_initialize_multi(bis, 1, - CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); - if (ret) - printf("FEC%d MXC: %s:failed\n", 1, __func__); + ret = enable_fec_anatop_clock(1, ENET_125MHZ); + if (ret) { + printf("enable fec0 clock failed\n"); + return ret; + } - return ret; + return 0; } int board_phy_config(struct phy_device *phydev) @@ -134,51 +127,64 @@ int power_init_board(void) { struct udevice *dev; int ret; - u32 dev_id, rev_id, i; - u32 switch_num = 6; - u32 offset = PFUZE100_SW1CMODE; - ret = pmic_get("pfuze100", &dev); - if (ret == -ENODEV) - return 0; + dev = pfuze_common_init(); + if (!dev) + return -ENODEV; - if (ret != 0) + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) return ret; - dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); - rev_id = pmic_reg_read(dev, PFUZE100_REVID); - printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + /* set SW1C staby volatage 1.10V */ + pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + /* Enable power of VGEN5 3V3, needed for SD3 */ + pmic_clrsetbits(dev, PFUZE100_SW1CCONF, LDO_VOL_MASK, (LDOB_3_30V | (1 << LDO_EN))); - /* Init mode to APS_PFM */ - pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM); + return 0; +} - for (i = 0; i < switch_num - 1; i++) - pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM); +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; - /* set SW1AB staby volatage 0.975V */ - pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b); + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } - /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40); + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.15V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, SW1x_1_150V); - /* set SW1C staby volatage 1.10V */ - pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20); + /* decrease VDDSOC to 1.15V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, SW1x_1_150V); - /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ - pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40); + set_anatop_bypass(1); - return 0; + printf("switch to ldo_bypass mode!\n"); + } } +#endif #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + #define USB_OTHERREGS_OFFSET 0x800 #define UCTRL_PWR_POL (1 << 9) static iomux_v3_cfg_t const usb_otg_pads[] = { /* OGT1 */ MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), /* OTG2 */ MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) }; @@ -213,6 +219,7 @@ int board_ehci_hcd_init(int port) return 0; } #endif +#endif int board_early_init_f(void) { @@ -221,6 +228,136 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lvds_ctrl_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_lvds(struct display_info_t const *dev) +{ + struct gpio_desc desc; + int ret; + + enable_lcdif_clock(dev->bus, 1); + enable_lvds_bridge(dev->bus); + + imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, + ARRAY_SIZE(lvds_ctrl_pads)); + + /* LVDS Enable pin */ + ret = dm_gpio_lookup_name("gpio@30_7", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "lvds_en"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 1); + + /* Set Brightness to high */ + ret = dm_gpio_lookup_name("GPIO6_3", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "lcd backlight"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + struct gpio_desc desc; + int ret; + + enable_lcdif_clock(dev->bus, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Power up the LCD */ + ret = dm_gpio_lookup_name("GPIO3_27", &desc); + if (ret) + return; + + ret = dm_gpio_request(&desc, "lcd reset"); + if (ret) + return; + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +struct display_info_t const displays[] = {{ + .bus = LCDIF2_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .detect = NULL, + .enable = do_enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = MX6SX_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "Boundary-LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + #ifdef CONFIG_FSL_QSPI int board_qspi_init(void) { @@ -300,8 +437,10 @@ int board_init(void) dm_gpio_set_value(&desc, 0); #ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB setup_usb(); #endif +#endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); @@ -311,6 +450,11 @@ int board_init(void) setup_gpmi_nand(); #endif + /* Also used for OF_CONTROL enabled */ +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + return 0; } @@ -330,6 +474,18 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + /* set WDOG_B to reset whole system */ + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } diff --git a/board/freescale/mx6sxsabreauto/plugin.S b/board/freescale/mx6sxsabreauto/plugin.S new file mode 100644 index 00000000000..ea5640ca15d --- /dev/null +++ b/board/freescale/mx6sxsabreauto/plugin.S @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_sabreauto_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000030 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000030 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000030 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000030 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x002C003D + str r2, [r0, #0x80c] + ldr r2, =0x00110046 + str r2, [r0, #0x810] + ldr r2, =0x4160016C + str r2, [r0, #0x83c] + ldr r2, =0x013C016C + str r2, [r0, #0x840] + ldr r2, =0x46424446 + str r2, [r0, #0x848] + ldr r2, =0x3A3C3C3A + str r2, [r0, #0x850] + ldr r2, =0x2492244A + str r2, [r0, #0x8c0] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000007f + str r2, [r0, #0x040] + ldr r2, =0x85190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00068031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00022227 + str r2, [r0, #0x818] + ldr r2, =0x0002556d + str r2, [r0, #0x004] + ldr r2, =0x00011006 + str r2, [r0, #0x404] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] + +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x20e4024 + ldr r1, =0x1 + str r1, [r0] +#endif +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6sx_sabreauto_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig index fcfac0aae4e..9a4e3057799 100644 --- a/board/freescale/mx6sxsabresd/Kconfig +++ b/board/freescale/mx6sxsabresd/Kconfig @@ -9,4 +9,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6sxsabresd" +config MX6SXSABRESD_EMMC_REWORK + bool "Select for the board with eMMC rework" + +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6sxsabresd/imximage.cfg b/board/freescale/mx6sxsabresd/imximage.cfg index 28ffb2f8bc9..7ad849ec00e 100644 --- a/board/freescale/mx6sxsabresd/imximage.cfg +++ b/board/freescale/mx6sxsabresd/imximage.cfg @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. */ #define __ASSEMBLY__ @@ -15,7 +15,16 @@ IMAGE_VERSION 2 * spi/sd/nand/onenand, qspi/nor */ +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#else BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6sxsabresd/plugin.bin 0x00907000 +#else /* * Secure boot support @@ -46,6 +55,11 @@ DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff DATA 4 0x020c4084 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + /* IOMUX - DDR IO Type */ DATA 4 0x020e0618 0x000c0000 DATA 4 0x020e05fc 0x00000000 @@ -136,3 +150,4 @@ DATA 4 0x021b001c 0x04008040 DATA 4 0x021b0020 0x00000800 DATA 4 0x021b0818 0x00011117 DATA 4 0x021b001c 0x00000000 +#endif diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 57fab238641..ac252f7b045 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Author: Fabio Estevam */ @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -30,7 +32,15 @@ #include #include #include "../common/pfuze.h" - +#include +#include +#include +#include + +#ifdef CONFIG_IMX_RDC +#include +#include +#endif DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ @@ -41,6 +51,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) @@ -51,12 +66,21 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm) +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -69,25 +93,63 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* CD pin */ + MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* RST_B, used for power reset cycle */ + MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK +static iomux_v3_cfg_t const usdhc4_emmc_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_RESET_B__USDHC4_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + static iomux_v3_cfg_t const wdog_b_pad = { MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), }; -static iomux_v3_cfg_t const fec1_pads[] = { - MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), - MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; static iomux_v3_cfg_t const peri_3v3_pads[] = { MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -104,6 +166,20 @@ static iomux_v3_cfg_t const phy_control_pads[] = { MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL), }; +#if defined(CONFIG_PCIE_IMX) && !defined(CONFIG_DM_PCI) +iomux_v3_cfg_t const pcie_pads[] = { + MX6_PAD_ENET1_COL__GPIO2_IO_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */ + MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */ +}; + +static void setup_pcie(void) +{ + imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); + gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable"); + gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset"); +} +#endif + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); @@ -114,26 +190,57 @@ static int setup_fec(void) struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; int reg, ret; + struct gpio_desc desc; - /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */ + /* Use 125M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0); + /* Use 125M anatop loopback REF_CLK1 for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0); + ret = enable_fec_anatop_clock(0, ENET_125MHZ); if (ret) return ret; + ret = enable_fec_anatop_clock(1, ENET_125MHZ); + if (ret) + return ret; + imx_iomux_v3_setup_multiple_pads(phy_control_pads, ARRAY_SIZE(phy_control_pads)); /* Enable the ENET power, active low */ - gpio_request(IMX_GPIO_NR(2, 6), "enet_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 6) , 0); + ret = dm_gpio_lookup_name("GPIO2_6", &desc); + if (ret) { + printf("%s lookup GPIO2_6 failed ret = %d\n", __func__, ret); + return ret; + } + + ret = dm_gpio_request(&desc, "fec power en"); + if (ret) { + printf("%s request fec power en failed ret = %d\n", __func__, ret); + return ret; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); + + ret = dm_gpio_lookup_name("GPIO2_7", &desc); + if (ret) { + printf("%s lookup GPIO2_7 failed ret = %d\n", __func__, ret); + return ret; + } + + ret = dm_gpio_request(&desc, "ar8031 reset"); + if (ret) { + printf("%s request ar8031 reset failed ret = %d\n", __func__, ret); + return ret; + } - /* Reset AR8031 PHY */ - gpio_request(IMX_GPIO_NR(2, 7), "phy_rst"); - gpio_direction_output(IMX_GPIO_NR(2, 7) , 0); + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); mdelay(10); - gpio_set_value(IMX_GPIO_NR(2, 7), 1); + dm_gpio_set_value(&desc, 1); reg = readl(&anatop->pll_enet); reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE; @@ -142,14 +249,85 @@ static int setup_fec(void) return 0; } -int board_eth_init(struct bd_info *bis) +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO_2 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO_3 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +#ifdef CONFIG_POWER +int power_init_board(void) { - imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); - setup_fec(); + struct pmic *pfuze; + unsigned int reg; + int ret; - return cpu_eth_init(bis); -} + pfuze = pfuze_common_init(I2C_PMIC); + if (!pfuze) + return -ENODEV; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + /* set SW1AB standby volatage 1.10V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(11000); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg); + + /* set SW1C standby volatage 1.10V */ + pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, ®); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(11000); + pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1CCONF, ®); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg); + + /* Enable power of VGEN5 3V3, needed for SD3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= (LDOB_3_30V | (1 << LDO_EN)); + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg); + return 0; +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) int power_init_board(void) { struct udevice *dev; @@ -164,14 +342,176 @@ int power_init_board(void) if (ret < 0) return ret; + /* set SW1AB staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(11000); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* set SW1C staby volatage 0.975V*/ + reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY); + reg &= ~0x3f; + reg |= PFUZE100_SW1ABC_SETP(11000); + pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg); + + /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1CCONF); + reg &= ~0xc0; + reg |= 0x40; + pmic_reg_write(dev, PFUZE100_SW1CCONF, reg); + /* Enable power of VGEN5 3V3, needed for SD3 */ reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); reg &= ~LDO_VOL_MASK; reg |= (LDOB_3_30V | (1 << LDO_EN)); pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + return 0; +} +#endif + +#ifdef CONFIG_LDO_BYPASS_CHECK +#ifdef CONFIG_POWER +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + /* decrease VDDSOC to 1.3V */ + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(p, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(p, PFUZE100_SW1ABVOL, value); + + pmic_reg_read(p, PFUZE100_SW1CVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(11750); + pmic_reg_write(p, PFUZE100_SW1CVOL, value); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } + +} +#elif defined(CONFIG_DM_PMIC_PFUZE100) +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode , boot on 800Mhz */ + if (ldo_bypass) { + prep_anatop_bypass(); + + /* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + /* increase VDDSOC to 1.3V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(13000)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + /* decrease VDDSOC to 1.175V */ + pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, PFUZE100_SW1ABC_SETP(11750)); + + finish_anatop_bypass(); + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OGT1 */ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), + /* OTG2 */ + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); return 0; } +#endif +#endif int board_phy_config(struct phy_device *phydev) { @@ -192,8 +532,22 @@ int board_phy_config(struct phy_device *phydev) return 0; } +#ifdef CONFIG_IMX_RDC +static rdc_peri_cfg_t const shared_resources[] = { + (RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)), +}; +#endif + int board_early_init_f(void) { +#ifdef CONFIG_IMX_RDC + imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources)); +#endif + +#ifdef CONFIG_SYS_AUXCORE_FASTUP + arch_auxiliary_core_up(0, CONFIG_SYS_AUXCORE_BOOTDATA); +#endif + setup_iomux_uart(); /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ @@ -203,9 +557,105 @@ int board_early_init_f(void) return 0; } -int board_mmc_get_env_dev(int devno) +#ifdef CONFIG_IMX_BOOTAUX +ulong board_get_usable_ram_top(ulong total_size) +{ + /* Reserve top 1M memory used by M core vring/buffer */ + return gd->ram_top - SZ_1M; +} +#endif + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + {USDHC4_BASE_ADDR, 0, 8}, +#else + {USDHC4_BASE_ADDR}, +#endif +}; + +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11) +#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21) + +int board_mmc_getcd(struct mmc *mmc) { - return devno; + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = 1; /* Assume uSDHC2 is always present */ + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + case USDHC4_BASE_ADDR: +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + ret = 1; +#else + ret = !gpio_get_value(USDHC4_CD_GPIO); +#endif + break; + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC2 + * mmc1 USDHC3 + * mmc2 USDHC4 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_request(USDHC3_CD_GPIO, "usdhc3 cd"); + gpio_request(USDHC3_PWR_GPIO, "usdhc3 pwr"); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + case 2: +#ifdef CONFIG_MX6SXSABRESD_EMMC_REWORK + imx_iomux_v3_setup_multiple_pads( + usdhc4_emmc_pads, ARRAY_SIZE(usdhc4_emmc_pads)); +#else + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_request(USDHC4_CD_GPIO, "usdhc4 cd"); + gpio_direction_input(USDHC4_CD_GPIO); +#endif + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; } #ifdef CONFIG_FSL_QSPI @@ -219,7 +669,25 @@ int board_qspi_init(void) } #endif +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd3", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)}, + {"sd4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {"qspi2", MAKE_CFGVAL(0x18, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + #ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lvds_ctrl_pads[] = { + /* CABC enable */ + MX6_PAD_QSPI1A_DATA2__GPIO4_IO_18 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX6_PAD_SD1_DATA1__GPIO6_IO_3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const lcd_pads[] = { MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), @@ -255,9 +723,43 @@ static iomux_v3_cfg_t const lcd_pads[] = { MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static int setup_lcd(void) +void do_enable_lvds(struct display_info_t const *dev) +{ + int ret; + + ret = enable_lcdif_clock(dev->bus, 1); + if (ret) { + printf("Enable LCDIF clock failed, %d\n", ret); + return; + } + ret = enable_lvds_bridge(dev->bus); + if (ret) { + printf("Enable LVDS bridge failed, %d\n", ret); + return; + } + + imx_iomux_v3_setup_multiple_pads(lvds_ctrl_pads, + ARRAY_SIZE(lvds_ctrl_pads)); + + /* Enable CABC */ + gpio_request(IMX_GPIO_NR(4, 18), "CABC enable"); + gpio_direction_output(IMX_GPIO_NR(4, 18) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(6, 3), "lvds backlight"); + gpio_direction_output(IMX_GPIO_NR(6, 3) , 1); +} + +void do_enable_parallel_lcd(struct display_info_t const *dev) + { - enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); + int ret; + + ret = enable_lcdif_clock(dev->bus, 1); + if (ret) { + printf("Enable LCDIF clock failed, %d\n", ret); + return; + } imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); @@ -270,9 +772,48 @@ static int setup_lcd(void) /* Set Brightness to high */ gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright"); gpio_direction_output(IMX_GPIO_NR(6, 4) , 1); - - return 0; } + +struct display_info_t const displays[] = {{ + .bus = LCDIF2_BASE_ADDR, + .addr = 0, + .pixfmt = 18, + .detect = NULL, + .enable = do_enable_lvds, + .mode = { + .name = "Hannstar-XGA", + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} }, { + .bus = MX6SX_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); #endif int board_init(void) @@ -289,16 +830,32 @@ int board_init(void) */ imx_iomux_v3_setup_pad(wdog_b_pad); - /* Active high for ncp692 */ - gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en"); - gpio_direction_output(IMX_GPIO_NR(4, 16), 1); +#if defined(CONFIG_DM_REGULATOR) + regulators_enable_boot_on(false); +#endif + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif #ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); +#if defined(CONFIG_PCIE_IMX) && !defined(CONFIG_DM_PCI) + setup_pcie(); +#endif + + /* Also used for OF_CONTROL enabled */ +#ifdef CONFIG_FEC_MXC + setup_fec(); #endif return 0; @@ -315,6 +872,19 @@ int board_late_init(void) if (is_reva()) env_set("board_rev", "REVA"); #endif + +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif return 0; } diff --git a/board/freescale/mx6sxsabresd/plugin.S b/board/freescale/mx6sxsabresd/plugin.S new file mode 100644 index 00000000000..afdb781c749 --- /dev/null +++ b/board/freescale/mx6sxsabresd/plugin.S @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6sx_sabresd_ddr_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000c0000 + str r1, [r0, #0x618] + ldr r1, =0x00000000 + str r1, [r0, #0x5fc] + ldr r1, =0x00000030 + str r1, [r0, #0x32c] + + ldr r1, =0x00000020 + str r1, [r0, #0x300] + str r1, [r0, #0x2fc] + str r1, [r0, #0x5f4] + str r1, [r0, #0x340] + + ldr r1, =0x00000000 + str r1, [r0, #0x320] + ldr r1, =0x00000020 + str r1, [r0, #0x310] + str r1, [r0, #0x314] + str r1, [r0, #0x614] + + ldr r1, =0x00020000 + str r1, [r0, #0x5f8] + ldr r1, =0x00000028 + str r1, [r0, #0x330] + str r1, [r0, #0x334] + str r1, [r0, #0x338] + str r1, [r0, #0x33c] + ldr r1, =0x00020000 + str r1, [r0, #0x608] + ldr r1, =0x00000028 + str r1, [r0, #0x60c] + str r1, [r0, #0x610] + str r1, [r0, #0x61c] + str r1, [r0, #0x620] + str r1, [r0, #0x2ec] + str r1, [r0, #0x2f0] + str r1, [r0, #0x2f4] + str r1, [r0, #0x2f8] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r2, =0xa1390003 + str r2, [r0, #0x800] + ldr r2, =0x00290025 + str r2, [r0, #0x80c] + ldr r2, =0x00220022 + str r2, [r0, #0x810] + ldr r2, =0x41480144 + str r2, [r0, #0x83c] + ldr r2, =0x01340130 + str r2, [r0, #0x840] + ldr r2, =0x3C3E4244 + str r2, [r0, #0x848] + ldr r2, =0x34363638 + str r2, [r0, #0x850] + + ldr r2, =0x33333333 + str r2, [r0, #0x81c] + str r2, [r0, #0x820] + str r2, [r0, #0x824] + str r2, [r0, #0x828] + + ldr r2, =0x00000800 + str r2, [r0, #0x8b8] + ldr r2, =0x0002002d + str r2, [r0, #0x004] + ldr r2, =0x00333030 + str r2, [r0, #0x008] + ldr r2, =0x676b52f3 + str r2, [r0, #0x00c] + ldr r2, =0xb66d8b63 + str r2, [r0, #0x010] + ldr r2, =0x01ff00db + str r2, [r0, #0x014] + ldr r2, =0x00011740 + str r2, [r0, #0x018] + ldr r2, =0x00008000 + str r2, [r0, #0x01c] + ldr r2, =0x000026d2 + str r2, [r0, #0x02c] + ldr r2, =0x006b1023 + str r2, [r0, #0x030] + ldr r2, =0x0000005f + str r2, [r0, #0x040] + ldr r2, =0x84190000 + str r2, [r0, #0x000] + ldr r2, =0x04008032 + str r2, [r0, #0x01c] + ldr r2, =0x00008033 + str r2, [r0, #0x01c] + ldr r2, =0x00048031 + str r2, [r0, #0x01c] + ldr r2, =0x05208030 + str r2, [r0, #0x01c] + ldr r2, =0x04008040 + str r2, [r0, #0x01c] + ldr r2, =0x00000800 + str r2, [r0, #0x020] + ldr r2, =0x00011117 + str r2, [r0, #0x818] + ldr r2, =0x00000000 + str r2, [r0, #0x01c] +.endm +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xffffffff + str r1, [r0, #0x068] + str r1, [r0, #0x06c] + str r1, [r0, #0x070] + str r1, [r0, #0x074] + str r1, [r0, #0x078] + str r1, [r0, #0x07c] + str r1, [r0, #0x080] + str r1, [r0, #0x084] + +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x20e4024 + ldr r1, =0x1 + str r1, [r0] +#endif +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6sx_sabresd_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ul_14x14_ddr3_val/Kconfig b/board/freescale/mx6ul_14x14_ddr3_val/Kconfig new file mode 100644 index 00000000000..2f057ef8c6e --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/Kconfig @@ -0,0 +1,26 @@ +if TARGET_MX6UL_14X14_DDR3_VAL + +config SYS_BOARD + default "mx6ul_14x14_ddr3_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ul_14x14_ddr3_val" + +config MX6UL_DDR3_VAL_EMMC_REWORK + bool "Select this for the board with eMMC rework" + +config SYS_TEXT_BASE + default 0x87800000 + +config MX6UL_DDR3_VAL_USDHC2_REWORK + bool "Select this for the board with 8bits USDHC2 rework" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx6ul_14x14_ddr3_val/Makefile b/board/freescale/mx6ul_14x14_ddr3_val/Makefile new file mode 100644 index 00000000000..e9f6edc422a --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_14x14_ddr3_val.o diff --git a/board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg b/board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg new file mode 100644 index 00000000000..cd3372bd7ac --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_ddr3_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x0013000F +DATA 4 0x021B083C 0x415D0159 +DATA 4 0x021B0848 0x4040484F +DATA 4 0x021B0850 0x40405247 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00922012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333000 +DATA 4 0x021B000C 0x676B54B3 +DATA 4 0x021B0010 0xB68E0A83 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00211740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000005F +DATA 4 0x021B0000 0x85180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c b/board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c new file mode 100644 index 00000000000..31076f6c3d3 --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/mx6ul_14x14_ddr3_val.c @@ -0,0 +1,1066 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC_IMX +#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* + * The following 4 pins conflicts with qspi. + * You can comment out the following 4 pins and change + * {USDHC1_BASE_ADDR, 0, 8} -> {USDHC1_BASE_ADDR, 0, 4} + * to make emmc and qspi coexists. + */ + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* Default NO WP for emmc, since we use pull down */ + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#if !defined(CONFIG_CMD_NAND) +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_CSI_VSYNC__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_HSYNC__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#ifdef CONFIG_MX6UL_DDR3_VAL_USDHC2_REWORK +#if defined(CONFIG_MTD_NOR_FLASH) || defined(CONFIG_MXC_SPI) +#error "Pin conflicts!" +#endif + /* conflict with eimnor/spinor */ + MX6_PAD_CSI_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_CSI_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#endif + /* VSELECT */ + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* + * Pin conflicts with NAND ALE, if want to test nand, + * Connect R169(B), disconnect R169(A). + * + * RST_B + */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nand_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +/* pin conflicts with eim nor */ +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS Pin */ + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 26), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 26), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1; +} +#endif +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +/* pin conflicts with nand usdhc2 lcd enet, ecspi */ +static iomux_v3_cfg_t const eimnor_pads[] = { + MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__EIM_ADDR26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_PIXCLK__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_VSYNC__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_LCD_DATA08__EIM_DATA00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA09__EIM_DATA01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA10__EIM_DATA02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA11__EIM_DATA03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA12__EIM_DATA04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA13__EIM_DATA05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA14__EIM_DATA06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA15__EIM_DATA07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA16__EIM_DATA08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA17__EIM_DATA09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA18__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA19__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA20__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA21__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA22__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_LCD_DATA23__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00010181, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x0a020000, WEIM_BASE_ADDR + 0x008); + writel(0x0000c000, WEIM_BASE_ADDR + 0x00c); + writel(0x0804a240, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + if (check_module_fused(MODULE_EIM)) { + printf("WEIM@0x%x is fused, disable it\n", WEIM_BASE_ADDR); + return; + } + + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} + +int board_flash_wp_on(void) +{ + if (check_module_fused(MODULE_EIM)) + return 1; /* Skip flash init */ + + return 0; +} + +#endif + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + /* Pin conflicts with LCD PWM1 */ + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_phy_rst[] = { + /* + * ALT5 mode is only valid when TAMPER pin is used for GPIO. + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]. + * + * ENET1_RST + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_phy_rst[] = { + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) { + SETUP_IOMUX_PADS(fec1_pads); + } else { + SETUP_IOMUX_PADS(fec2_pads); + } +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +static struct fsl_esdhc_cfg usdhc_cfg[2] = { +#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK + /* If want to use qspi, should change to 4 bit width */ + {USDHC1_BASE_ADDR, 0, 8}, +#else + {USDHC1_BASE_ADDR, 0, 4}, +#endif +#if !defined(CONFIG_CMD_NAND) + {USDHC2_BASE_ADDR, 0, 4}, +#endif +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5) +#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 17) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: +#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK + ret = 1; +#else + ret = !gpio_get_value(USDHC1_CD_GPIO); +#endif + break; +#if !defined(CONFIG_CMD_NAND) + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; +#endif + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: +#ifdef CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK + SETUP_IOMUX_PADS(usdhc1_emmc_pads); +#else + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); +#endif + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + /* 3.3V */ + gpio_request(USDHC1_VSELECT, "usdhc1 vsel"); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); + gpio_direction_output(USDHC1_VSELECT, 0); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; +#if !defined(CONFIG_CMD_NAND) + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; +#endif + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * PWM1, pin conflicts with ENET1_RX_DATA0 + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + /* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/ +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + /* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */ +} + +struct display_info_t const displays[] = {{ + .bus = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + if (check_module_fused(MODULE_ENET1)) + return -1; + + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] + */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + SETUP_IOMUX_PADS(fec1_phy_rst); + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 2), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 2), 1); + + } else { + if (check_module_fused(MODULE_ENET2)) + return -1; + + /* clk from phy, set gpr1[14], clear gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK); + + SETUP_IOMUX_PADS(fec2_phy_rst); + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + } + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (CONFIG_FEC_ENET_DEV == 0) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + } else if (CONFIG_FEC_ENET_DEV == 1) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + static struct pmic *pfuze; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* set SW1AB standby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* Enable power of VGEN5 3V3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value); + value &= ~0x1F; + value |= 0x1F; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + + struct pmic *p = pmic_get("PFUZE100"); + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Because kernel set WDOG_B mux before pad with the commone pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + * + * Here we can not set this, since SD1_RST_B conflicts with GWDOG. + * We use SD1, so will not set WDOG pads, also GWDOG default is + * DNP. + */ + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6UL 14X14 DDR3 Validation\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + /* conflict with i2c1_scl */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* conflict with sd1_vselect */ + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif diff --git a/board/freescale/mx6ul_14x14_ddr3_val/plugin.S b/board/freescale/mx6ul_14x14_ddr3_val/plugin.S new file mode 100644 index 00000000000..06b939fc244 --- /dev/null +++ b/board/freescale/mx6ul_14x14_ddr3_val/plugin.S @@ -0,0 +1,135 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_ddr3_val_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0013000F + str r1, [r0, #0x80C] + ldr r1, =0x415D0159 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333000 + str r1, [r0, #0x008] + ldr r1, =0x676B54B3 + str r1, [r0, #0x00C] + ldr r1, =0xB68E0A83 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00211740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000005F + str r1, [r0, #0x040] + ldr r1, =0x85180000 + str r1, [r0, #0x000] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] + str r1, [r0, #0x84] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ul_ddr3_val_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig index 8210cd3cb88..c81a613d853 100644 --- a/board/freescale/mx6ul_14x14_evk/Kconfig +++ b/board/freescale/mx6ul_14x14_evk/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6ul_14x14_evk" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6ul_14x14_evk/imximage.cfg b/board/freescale/mx6ul_14x14_evk/imximage.cfg new file mode 100644 index 00000000000..aa35cc49c43 --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/imximage.cfg @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_evk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#ifdef CONFIG_DDR3L_MT41K256M16HA + +/* DDR type MT41K256M16HA-125 which is EOL */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41490145 +DATA 4 0x021B0848 0x40404546 +DATA 4 0x021B0850 0x4040524D +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x00333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D8B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 + +#else + +/* New DDR type MT41K256M16TW-107 */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00000000 +DATA 4 0x021B083C 0x41570155 +DATA 4 0x021B0848 0x4040474A +DATA 4 0x021B0850 0x40405550 +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00201740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000004F +DATA 4 0x021B0000 0x84180000 +DATA 4 0x021B0890 0x23400A38 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif +#endif diff --git a/board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg b/board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg new file mode 100644 index 00000000000..43cf8d11540 --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_evk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + +DATA 4 0x020E04B4 0x00080000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000000 +DATA 4 0x020E0264 0x00000000 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00003030 +DATA 4 0x020E0284 0x00003030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B085C 0x1b4700c7 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0890 0x00470000 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B083C 0x20000000 +DATA 4 0x021B0848 0x4040484F +DATA 4 0x021B0850 0x40405247 +DATA 4 0x021B08C0 0x00922012 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020012 +DATA 4 0x021B0008 0x00000000 +DATA 4 0x021B000C 0x33374133 +DATA 4 0x021B0010 0x00100A82 +DATA 4 0x021B0038 0x00170557 +DATA 4 0x021B0014 0x00000093 +DATA 4 0x021B0018 0x00001748 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x0F9F0682 +DATA 4 0x021B0030 0x009F0010 +DATA 4 0x021B0040 0x00000047 +DATA 4 0x021B0000 0x83100000 +DATA 4 0x021B001C 0x00008010 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0x82018030 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0818 0x00000000 +DATA 4 0x021B0800 0xA1310003 +DATA 4 0x021B0004 0x00025576 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index b916ea01029..221a1ba791e 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -48,6 +48,11 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) @@ -67,7 +72,7 @@ int power_init_board(void) int ret, dev_id, rev_id; unsigned int reg; - ret = pmic_get("pfuze3000", &dev); + ret = pmic_get("pfuze3000@8", &dev); if (ret == -ENODEV) return 0; if (ret != 0) @@ -93,6 +98,44 @@ int power_init_board(void) return 0; } + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(12750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(11750); + + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif #endif int dram_init(void) @@ -198,32 +241,74 @@ int board_ehci_hcd_init(int port) #endif #endif +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + #ifdef CONFIG_FEC_MXC -static int setup_fec(int fec_id) +static int setup_fec(void) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; - if (fec_id == 0) { - /* - * Use 50M anatop loopback REF_CLK1 for ENET1, - * clear gpr1[13], set gpr1[17]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, - IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); - } else { - /* - * Use 50M anatop loopback REF_CLK2 for ENET2, - * clear gpr1[14], set gpr1[18]. - */ + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + if (!check_module_fused(MODULE_ENET2)) { clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); } - ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; + if (!check_module_fused(MODULE_ENET2)) { + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + } + enable_enet_clk(1); return 0; @@ -280,8 +365,8 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; -#ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); +#ifdef CONFIG_FEC_MXC + setup_fec(); #endif #ifdef CONFIG_USB_EHCI_MX6 @@ -294,6 +379,10 @@ int board_init(void) board_qspi_init(); #endif +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + return 0; } @@ -313,6 +402,11 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG env_set("board_name", "EVK"); @@ -324,6 +418,12 @@ int board_late_init(void) setup_lcd(); +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } diff --git a/board/freescale/mx6ul_14x14_evk/plugin.S b/board/freescale/mx6ul_14x14_evk/plugin.S new file mode 100644 index 00000000000..e420d5d2d33 --- /dev/null +++ b/board/freescale/mx6ul_14x14_evk/plugin.S @@ -0,0 +1,373 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_ddr3_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41570155 + str r1, [r0, #0x83C] + ldr r1, =0x4040474A + str r1, [r0, #0x848] + ldr r1, =0x40405550 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D0B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x23400A38 + str r1, [r0, #0x890] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6ul_ddr3_eol_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + ldr r1, =0x00000030 + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + ldr r1, =0x00000030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x80C] + ldr r1, =0x41490145 + str r1, [r0, #0x83C] + ldr r1, =0x40404546 + str r1, [r0, #0x848] + ldr r1, =0x4040524D + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x00333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D8B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00201740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x84180000 + str r1, [r0, #0x000] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6ul_lpddr2_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + str r1, [r0, #0x260] + str r1, [r0, #0x264] + + ldr r1, =0x00000030 + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00003030 + str r1, [r0, #0x280] + ldr r1, =0x00003030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0x1b4700c7 + str r1, [r0, #0x85c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00470000 + str r1, [r0, #0x890] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020012 + str r1, [r0, #0x004] + ldr r1, =0x00000000 + str r1, [r0, #0x008] + ldr r1, =0x33374133 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170557 + str r1, [r0, #0x038] + ldr r1, =0x00000093 + str r1, [r0, #0x014] + ldr r1, =0x00001748 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x0F9F0682 + str r1, [r0, #0x02C] + ldr r1, =0x009F0010 + str r1, [r0, #0x030] + ldr r1, =0x00000047 + str r1, [r0, #0x040] + ldr r1, =0x83100000 + str r1, [r0, #0x000] + ldr r1, =0x00008010 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0x00000000 + str r1, [r0, #0x818] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00025576 + str r1, [r0, #0x004] + ldr r1, =0x00010106 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] + +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x20e4024 + ldr r1, =1 + str r1, [r0] +#endif +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting +#if defined (CONFIG_TARGET_MX6UL_9X9_EVK) + imx6ul_lpddr2_evk_setting +#elif defined(CONFIG_DDR3L_MT41K256M16HA) + imx6ul_ddr3_eol_evk_setting +#else + imx6ul_ddr3_evk_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/Kconfig b/board/freescale/mx6ul_14x14_lpddr2_val/Kconfig new file mode 100644 index 00000000000..28c4515b73c --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/Kconfig @@ -0,0 +1,24 @@ +if TARGET_MX6UL_14X14_LPDDR2_VAL + +config SYS_BOARD + default "mx6ul_14x14_lpddr2_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ul_14x14_lpddr2_val" + +config SYS_TEXT_BASE + default 0x87800000 + +config MX6UL_LPDDR2_VAL_USDHC2_REWORK + bool "Select this for the board with 8bits USDHC2 rework" + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. + +endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/Makefile b/board/freescale/mx6ul_14x14_lpddr2_val/Makefile new file mode 100644 index 00000000000..e056bae1572 --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ul_14x14_lpddr2_val.o diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg b/board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg new file mode 100644 index 00000000000..ae47a81ee1f --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ul_14x14_lpddr2_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +DATA 4 0x020E04B4 0x00080000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000028 +DATA 4 0x020E0250 0x00000028 +DATA 4 0x020E024C 0x00000028 +DATA 4 0x020E0490 0x00000028 +DATA 4 0x020E0288 0x00000028 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000000 +DATA 4 0x020E0264 0x00000000 +DATA 4 0x020E04A0 0x00000028 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00003028 +DATA 4 0x020E0284 0x00003028 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000028 +DATA 4 0x020E04A4 0x00000028 +DATA 4 0x020E0244 0x00000028 +DATA 4 0x020E0248 0x00000028 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B085C 0x1b4700c7 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0890 0x00470000 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B083C 0x20000000 +DATA 4 0x021B0848 0x4040484F +DATA 4 0x021B0850 0x40405247 +DATA 4 0x021B08C0 0x00922012 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020012 +DATA 4 0x021B0008 0x00000000 +DATA 4 0x021B000C 0x33374133 +DATA 4 0x021B0010 0x00100A82 +DATA 4 0x021B0038 0x00170557 +DATA 4 0x021B0014 0x00000093 +DATA 4 0x021B0018 0x00001748 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x0F9F0682 +DATA 4 0x021B0030 0x009F0010 +DATA 4 0x021B0040 0x00000047 +DATA 4 0x021B0000 0x83100000 +DATA 4 0x021B001C 0x00008010 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0x82018030 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0818 0x00000000 +DATA 4 0x021B0800 0xA1310003 +DATA 4 0x021B0004 0x00025576 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c b/board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c new file mode 100644 index 00000000000..d94d14f113b --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/mx6ul_14x14_lpddr2_val.c @@ -0,0 +1,1022 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + +#if !defined(CONFIG_CMD_NAND) + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#endif + + MX6_PAD_CSI_DATA04__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#if !defined(CONFIG_CMD_NAND) + +#ifdef CONFIG_MX6UL_LPDDR2_VAL_USDHC2_REWORK +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = { + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* Default NO WP for emmc, since we use pull down */ + MX6_PAD_UART1_CTS_B__USDHC2_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP), + + /* RST_B */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nand_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +/* pin conflicts with eim nor */ +static iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS Pin */ + MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 22), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 22), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 1 && cs == 0) ? (IMX_GPIO_NR(4, 22)) : -1; +} +#endif +#endif + +#ifdef CONFIG_MTD_NOR_FLASH +/* pin conflicts with ECSIP2, USDHC1, USDCH2, NAND, SIM, ENET2 */ +static iomux_v3_cfg_t const eimnor_pads[] = { + MX6_PAD_NAND_CLE__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_ALE__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_CE1_B__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CMD__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_CLK__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA0__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA1__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA2__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_SD1_DATA3__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_PIXCLK__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_VSYNC__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_HSYNC__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_DATA00__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA01__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA02__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA03__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA04__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA05__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA06__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_CSI_DATA07__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA00__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA01__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA02__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA03__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA04__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA05__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA06__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DATA07__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX6_PAD_CSI_MCLK__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_WP_B__EIM_BCLK | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX6_PAD_NAND_DQS__EIM_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_BASE_ADDR + 0x090); + writel(0x00610089, WEIM_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_BASE_ADDR + 0x004); + writel(0x1c022000, WEIM_BASE_ADDR + 0x008); + writel(0x00000000, WEIM_BASE_ADDR + 0x00c); + writel(0x1404a38e, WEIM_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + SETUP_IOMUX_PADS(eimnor_pads); + + eimnor_cs_setup(); +} +#endif + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_phy_rst[] = { + /* + * ALT5 mode is only valid when TAMPER pin is used for GPIO. + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]. + * + * ENET1_RST + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* Conflict with UART1 */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_TX_DATA__ENET1_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_RX_DATA__ENET1_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_TX_DATA__ENET1_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__ENET1_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART1_CTS_B__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_RTS_B__ENET1_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART2_CTS_B__ENET1_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_phy_rst[] = { + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) { + SETUP_IOMUX_PADS(fec1_pads); + } else { + SETUP_IOMUX_PADS(fec2_pads); + } +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +#if !defined(CONFIG_CMD_NAND) +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 1}, + {USDHC2_BASE_ADDR, 0, 8}, +}; +#else +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; +#endif + +#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 26) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(4, 11) +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5) +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; +#if !defined(CONFIG_CMD_NAND) + case USDHC2_BASE_ADDR: +#ifdef CONFIG_MX6UL_LPDDR2_VAL_USDHC2_REWORK + ret = !gpio_get_value(USDHC2_CD_GPIO); +#else + ret = 1; +#endif + break; +#endif + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; +#if !defined(CONFIG_CMD_NAND) + case 1: +#ifdef CONFIG_MX6UL_LPDDR2_VAL_USDHC2_REWORK + SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd"); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#else + SETUP_IOMUX_PADS(usdhc2_emmc_pads); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); +#endif + break; +#endif + default: + printf("Warning: you configured more USDHC controllers (%d)" + " than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * PWM1, pin conflicts with ENET1_RX_DATA0 + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + MX6_PAD_NAND_DQS__GPIO4_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(4, 16), "backlight"); + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = MX6UL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + if (1 == fec_id) { + if (check_module_fused(MODULE_ENET2)) + return -1; + + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18] + */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + SETUP_IOMUX_PADS(fec1_phy_rst); + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 2), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 2), 1); + } else { + if (check_module_fused(MODULE_ENET1)) + return -1; + + /* clk from phy, set gpr1[13], clear gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK); + + SETUP_IOMUX_PADS(fec2_phy_rst); + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + } + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (CONFIG_FEC_ENET_DEV == 1) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + } else if (CONFIG_FEC_ENET_DEV == 0) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* set SW1AB standby volatage 1.3V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* Enable power of VGEN5 3V3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value); + value &= ~0x1F; + value |= 0x1F; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 1.3V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= PFUZE100_SW1ABC_SETP(13000); + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + /* + * This function should be invoked after setup_fec, + * because ENET2_RX_ER conflicts. However, we rarely need + * ENET2_RX_ER for enet, and when use eimnor, we do not + * have sd1/sd2, enet is a must to boot kernel and nfsrootfs. + */ + setup_eimnor(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6UL 14X14 LPDDR2 Validation\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + /* conflict with i2c1_scl */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* conflict with sd1_vselect */ + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif diff --git a/board/freescale/mx6ul_14x14_lpddr2_val/plugin.S b/board/freescale/mx6ul_14x14_lpddr2_val/plugin.S new file mode 100644 index 00000000000..6ef2013eece --- /dev/null +++ b/board/freescale/mx6ul_14x14_lpddr2_val/plugin.S @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ul_lpddr2_val_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000028 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + str r1, [r0, #0x260] + str r1, [r0, #0x264] + + ldr r1, =0x00000028 + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00003028 + str r1, [r0, #0x280] + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000028 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0x1b4700c7 + str r1, [r0, #0x5C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00470000 + str r1, [r0, #0x890] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + ldr r1, =0x4040484F + str r1, [r0, #0x848] + ldr r1, =0x40405247 + str r1, [r0, #0x850] + ldr r1, =0x00922012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020012 + str r1, [r0, #0x004] + ldr r1, =0x00000000 + str r1, [r0, #0x008] + ldr r1, =0x33374133 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170557 + str r1, [r0, #0x038] + ldr r1, =0x00000093 + str r1, [r0, #0x014] + ldr r1, =0x00001748 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x0F9F0682 + str r1, [r0, #0x02C] + ldr r1, =0x009F0010 + str r1, [r0, #0x030] + ldr r1, =0x0000004F + str r1, [r0, #0x040] + ldr r1, =0x83100000 + str r1, [r0, #0x000] + ldr r1, =0x00008010 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0x00000000 + str r1, [r0, #0x818] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00025576 + str r1, [r0, #0x004] + ldr r1, =0x00010106 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] + str r1, [r0, #0x84] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ul_lpddr2_val_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ull_ddr3_val/Kconfig b/board/freescale/mx6ull_ddr3_val/Kconfig new file mode 100644 index 00000000000..26903c37939 --- /dev/null +++ b/board/freescale/mx6ull_ddr3_val/Kconfig @@ -0,0 +1,24 @@ +if TARGET_MX6ULL_DDR3_VAL + +config SYS_BOARD + default "mx6ull_ddr3_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx6ull_ddr3_val" + +config MX6ULL_DDR3_VAL_EMMC_REWORK + bool "Select this for the board with eMMC rework" + +config SYS_TEXT_BASE + default 0x87800000 + +config MX6ULL_DDR3_VAL_TSC_REWORK + bool "Select this for the board with screen touch rework" + +config MX6ULL_DDR3_VAL_QSPIB_REWORK + bool "Select this for the board with flash on QSPI-B port rework" + +endif diff --git a/board/freescale/mx6ull_ddr3_val/Makefile b/board/freescale/mx6ull_ddr3_val/Makefile new file mode 100644 index 00000000000..f7d79a77039 --- /dev/null +++ b/board/freescale/mx6ull_ddr3_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx6ull_ddr3_val.o diff --git a/board/freescale/mx6ull_ddr3_val/imximage.cfg b/board/freescale/mx6ull_ddr3_val/imximage.cfg new file mode 100644 index 00000000000..cacdf0c6b0a --- /dev/null +++ b/board/freescale/mx6ull_ddr3_val/imximage.cfg @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ull_ddr3_val/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +DATA 4 0x020E04B4 0x000C0000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x000C0030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000030 +DATA 4 0x020E0264 0x00000030 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00000030 +DATA 4 0x020E0284 0x00000030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B080C 0x00150019 +DATA 4 0x021B083C 0x41550153 +DATA 4 0x021B0848 0x40403A3E +DATA 4 0x021B0850 0x40402F2A +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B08C0 0x00944009 +DATA 4 0x021B08b8 0x00000800 +DATA 4 0x021B0004 0x0002002D +DATA 4 0x021B0008 0x1B333030 +DATA 4 0x021B000C 0x676B52F3 +DATA 4 0x021B0010 0xB66D0B63 +DATA 4 0x021B0014 0x01FF00DB +DATA 4 0x021B0018 0x00211740 +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B002C 0x000026D2 +DATA 4 0x021B0030 0x006B1023 +DATA 4 0x021B0040 0x0000005F +DATA 4 0x021B0000 0x85180000 +DATA 4 0x021B0890 0x00400000 +DATA 4 0x021B001C 0x02008032 +DATA 4 0x021B001C 0x00008033 +DATA 4 0x021B001C 0x00048031 +DATA 4 0x021B001C 0x15208030 +DATA 4 0x021B001C 0x04008040 +DATA 4 0x021B0020 0x00000800 +DATA 4 0x021B0818 0x00000227 +DATA 4 0x021B0004 0x0002552D +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ull_ddr3_val/mx6ull_ddr3_val.c b/board/freescale/mx6ull_ddr3_val/mx6ull_ddr3_val.c new file mode 100644 index 00000000000..8e7bf5c30fe --- /dev/null +++ b/board/freescale/mx6ull_ddr3_val/mx6ull_ddr3_val.c @@ -0,0 +1,1168 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL_WP (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define EPDC_PAD_CTRL 0x010b1 + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC and EEPROM */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + /* conflict with usb_otg2_pwr */ + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + /* conflict with usb_otg2_oc */ + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* + * The following 4 pins conflicts with qspi and nand flash. + * You can comment out the following 4 pins and change + * {USDHC1_BASE_ADDR, 0, 8} -> {USDHC1_BASE_ADDR, 0, 4} + * to make emmc and qspi coexists. + */ + MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* Default NO WP for emmc, since we use pull down */ + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL_WP), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#else +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_UART1_CTS_B__USDHC1_WP | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* VSELECT */ + MX6_PAD_GPIO1_IO05__GPIO1_IO05 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD */ + MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_B */ + MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK) +static iomux_v3_cfg_t const usdhc2_pads[] = { + /* usdhc2_clk, nand_re_b, qspi1b_clk */ + MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_cmd, nand_we_b, qspi1b_cs0_b */ + MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_data0, nand_data0, qspi1b_cs1_b */ + MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_data1, nand_data1 */ + MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_data2, nand_data2, qspi1b_dat0 */ + MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* usdhc2_data3, nand_data3, qspi1b_dat1 */ + MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + /* + * VSELECT + * Conflicts with WDOG1, so default disabled. + * MX6_PAD_GPIO1_IO08__USDHC2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + */ + /* + * CD + * Share with sdhc1 + * MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + */ + /* + * RST_B + * Pin conflicts with NAND ALE, if want to test nand, + * Connect R169(B), disconnect R169(A). + */ + MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_MCLK__RAWNAND_CE2_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_CSI_PIXCLK__RAWNAND_CE3_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + SETUP_IOMUX_PADS(nand_pads); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_CSI_DATA06__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA04__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_CSI_DATA07__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS Pin */ + MX6_PAD_CSI_DATA05__GPIO4_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_spinor(void) +{ + SETUP_IOMUX_PADS(ecspi1_pads); + gpio_request(IMX_GPIO_NR(4, 26), "escpi cs"); + gpio_direction_output(IMX_GPIO_NR(4, 26), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 26)) : -1; +} +#endif +#endif + +#ifdef CONFIG_FEC_MXC +/* + * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only + * be used for ENET1 or ENET2, cannot be used for both. + */ +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + /* Pin conflicts with LCD PWM1 */ + MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_phy_rst[] = { + /* + * ALT5 mode is only valid when TAMPER pin is used for GPIO. + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0]. + * + * ENET1_RST + */ + MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_pads[] = { + MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_TX_DATA__ENET2_RDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_RX_DATA__ENET2_RDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART3_CTS_B__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_TX_DATA__ENET2_TDATA02 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_RX_DATA__ENET2_TDATA03 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + + MX6_PAD_UART5_RX_DATA__ENET2_COL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART5_TX_DATA__ENET2_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec2_phy_rst[] = { + /* + * ENET2_RST + * + * This depends on FUSE settings, TAMPER_PIN_DISABLE[1:0] + */ + MX6_PAD_SNVS_TAMPER4__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(int fec_id) +{ + if (fec_id == 0) { + SETUP_IOMUX_PADS(fec1_pads); + } else { + SETUP_IOMUX_PADS(fec2_pads); + } +} +#endif + +static void setup_iomux_uart(void) +{ + SETUP_IOMUX_PADS(uart1_pads); +} + +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + +#ifdef CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK + MX6_PAD_NAND_RE_B__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_WE_B__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA00__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA02__QSPI_B_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA03__QSPI_B_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA04__QSPI_B_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DATA05__QSPI_B_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +#endif +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + SETUP_IOMUX_PADS(quadspi_pads); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX +static struct fsl_esdhc_cfg usdhc_cfg[2] = { +#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK + /* If want to use qspi, should change to 4 bit width */ + {USDHC1_BASE_ADDR, 0, 8}, +#else + {USDHC1_BASE_ADDR, 0, 4}, +#endif +#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK) + {USDHC2_BASE_ADDR, 0, 4}, +#endif +}; + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9) +#define USDHC1_VSELECT IMX_GPIO_NR(1, 5) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: +#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK + ret = 1; +#else + ret = !gpio_get_value(USDHC1_CD_GPIO); +#endif + break; +#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK) + case USDHC2_BASE_ADDR: + ret = 1; + break; +#endif + } + + return ret; +} + +int board_mmc_init(struct bd_info *bis) +{ + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: +#ifdef CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK + SETUP_IOMUX_PADS(usdhc1_emmc_pads); +#else + SETUP_IOMUX_PADS(usdhc1_pads); + gpio_request(USDHC1_CD_GPIO, "usdhc1 cd"); + gpio_direction_input(USDHC1_CD_GPIO); +#endif + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + /* 3.3V */ + gpio_request(USDHC1_VSELECT, "usdhc1 vsel"); + gpio_request(USDHC1_PWR_GPIO, "usdhc1 pwr"); + gpio_direction_output(USDHC1_VSELECT, 0); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; +#if !defined(CONFIG_NAND_MXS) && !defined(CONFIG_MX6ULL_DDR3_VAL_QSPIB_REWORK) + case 1: + SETUP_IOMUX_PADS(usdhc2_pads); + gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr"); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; +#endif + default: + printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX6_PAD_LCD_RESET__GPIO3_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + + /* + * PWM1, pin conflicts with ENET1_RX_DATA0 + * Use GPIO for Brightness adjustment, duty cycle = period. + */ + /* MX6_PAD_ENET1_RX_DATA0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),*/ +}; + +struct lcd_panel_info_t { + unsigned int lcdif_base_addr; + int depth; + void (*enable)(struct lcd_panel_info_t const *dev); + struct fb_videomode mode; +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + enable_lcdif_clock(dev->bus, 1); + + SETUP_IOMUX_PADS(lcd_pads); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd power"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + /* gpio_direction_output(IMX_GPIO_NR(2, 0) , 1); */ +} + +struct display_info_t const displays[] = {{ + .bus = MX6ULL_LCDIF1_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX6_PAD_ENET2_RX_DATA0__EPDC_SDDO08 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__EPDC_SDDO09 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__EPDC_SDDO10 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__EPDC_SDDO11 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__EPDC_SDDO12 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__EPDC_SDDO13 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__EPDC_SDDO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__EPDC_SDDO15 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_CLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_ENABLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_HSYNC__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_VSYNC__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA00__EPDC_SDDO00 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA01__EPDC_SDDO01 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA02__EPDC_SDDO02 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA03__EPDC_SDDO03 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA04__EPDC_SDDO04 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA05__EPDC_SDDO05 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA06__EPDC_SDDO06 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA07__EPDC_SDDO07 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA14__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA15__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA16__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_DATA17__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX6_PAD_LCD_RESET__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX6_PAD_ENET2_RX_DATA0__GPIO2_IO08, + MX6_PAD_ENET2_RX_DATA1__GPIO2_IO09, + MX6_PAD_ENET2_RX_EN__GPIO2_IO10, + MX6_PAD_ENET2_TX_DATA0__GPIO2_IO11, + MX6_PAD_ENET2_TX_DATA1__GPIO2_IO12, + MX6_PAD_ENET2_TX_EN__GPIO2_IO13, + MX6_PAD_ENET2_TX_CLK__GPIO2_IO14, + MX6_PAD_ENET2_RX_ER__GPIO2_IO15, + MX6_PAD_LCD_CLK__GPIO3_IO00, + MX6_PAD_LCD_ENABLE__GPIO3_IO01, + MX6_PAD_LCD_HSYNC__GPIO3_IO02, + MX6_PAD_LCD_VSYNC__GPIO3_IO03, + MX6_PAD_LCD_DATA00__GPIO3_IO05, + MX6_PAD_LCD_DATA01__GPIO3_IO06, + MX6_PAD_LCD_DATA02__GPIO3_IO07, + MX6_PAD_LCD_DATA03__GPIO3_IO08, + MX6_PAD_LCD_DATA04__GPIO3_IO09, + MX6_PAD_LCD_DATA05__GPIO3_IO10, + MX6_PAD_LCD_DATA06__GPIO3_IO11, + MX6_PAD_LCD_DATA07__GPIO3_IO12, + MX6_PAD_LCD_DATA14__GPIO3_IO19, + MX6_PAD_LCD_DATA15__GPIO3_IO20, + MX6_PAD_LCD_DATA16__GPIO3_IO21, + MX6_PAD_LCD_DATA17__GPIO3_IO22, + MX6_PAD_LCD_RESET__GPIO3_IO04, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = { + IOMUX_PADS(PAD_LCD_DATA11__GPIO3_IO16 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_LCD_DATA19__GPIO3_IO24 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_LCD_DATA09__GPIO3_IO14 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), + IOMUX_PADS(PAD_LCD_DATA12__GPIO3_IO17 | MUX_PAD_CTRL(EPDC_PAD_CTRL)), +}; + +static void setup_epdc_power(void) +{ + SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO3[16] for PWR_GOOD status */ + gpio_request(IMX_GPIO_NR(3, 16), "EPDC_PWRSTAT"); + gpio_direction_input(IMX_GPIO_NR(3, 16)); + + /* EPDC_VCOM0 - GPIO3[24] for VCOM control */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 24), "EPDC_VCOM0"); + gpio_direction_output(IMX_GPIO_NR(3, 24), 1); + + /* EPDC_PWRWAKEUP - GPIO3[14] for EPD PMIC WAKEUP */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 14), "EPDC_PWRWAKEUP"); + gpio_direction_output(IMX_GPIO_NR(3, 14), 1); + + /* EPDC_PWRCTRL0 - GPIO3[17] for EPD PWR CTL0 */ + /* Set as output */ + gpio_request(IMX_GPIO_NR(3, 17), "EPDC_PWRCTRL0"); + gpio_direction_output(IMX_GPIO_NR(3, 17), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + SETUP_IOMUX_PADS(epdc_enable_pads); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + SETUP_IOMUX_PADS(epdc_disable_pads); +} + +static void setup_epdc(void) +{ + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO3_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(3, 17), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 14), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 16))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 24), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(3, 14), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(3, 24), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(3, 17), 0); +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec(CONFIG_FEC_ENET_DEV); + + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC%d MXC: %s:failed\n", CONFIG_FEC_ENET_DEV, __func__); + + return 0; +} + +static int setup_fec(int fec_id) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + int ret; + + if (0 == fec_id) { + if (check_module_fused(MODULE_ENET1)) + return -1; + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17] + */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + if (ret) + return ret; + + SETUP_IOMUX_PADS(fec1_phy_rst); + gpio_request(IMX_GPIO_NR(5, 2), "fec1 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 2), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 2), 1); + + } else { + if (check_module_fused(MODULE_ENET2)) + return -1; + + /* clk from phy, set gpr1[14], clear gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK); + + SETUP_IOMUX_PADS(fec2_phy_rst); + gpio_request(IMX_GPIO_NR(5, 4), "fec2 reset"); + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + udelay(50); + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + } + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + if (CONFIG_FEC_ENET_DEV == 0) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x202); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + } else if (CONFIG_FEC_ENET_DEV == 1) { + phy_write(phydev, MDIO_DEVAD_NONE, 0x16, 0x201); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8110); + } + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + u32 rev_id, value; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE100"); + if (!pfuze) + return -ENODEV; + + ret = pmic_probe(pfuze); + if (ret) + return ret; + + ret = pfuze_mode_init(pfuze, APS_PFM); + if (ret < 0) + return ret; + + pmic_reg_read(pfuze, PFUZE100_DEVICEID, &value); + pmic_reg_read(pfuze, PFUZE100_REVID, &rev_id); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", value, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* set SW1AB standby volatage 0.975V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(9750); + pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value); + + /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value); + value &= ~0xc0; + value |= 0x40; + pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value); + + /* Enable power of VGEN5 3V3 */ + pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &value); + value &= ~0x1F; + value |= 0x1F; + pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, value); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + int is_400M; + u32 vddarm; + + struct pmic *p = pfuze; + + if (!p) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= PFUZE100_SW1ABC_SETP(12750); + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_reg_read(pfuze, PFUZE100_SW1ABVOL, &value); + value &= ~0x3f; + value |= vddarm; + pmic_reg_write(pfuze, PFUZE100_SW1ABVOL, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#elif defined(CONFIG_DM_PMIC_PFUZE100) +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int reg, dev_id, rev_id; + + ret = pmic_get("pfuze100@8", &dev); + if (ret == -ENODEV) + return ret; + + ret = pfuze_mode_init(dev, APS_PFM); + if (ret < 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE100_REVID); + printf("PMIC: PFUZE200! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* + * Our PFUZE0200 is PMPF0200X0AEP, the Pre-programmed OTP + * Configuration is F0. + * Default VOLT: + * VSNVS_VOLT | 3.0V + * SW1AB | 1.375V + * SW2 | 3.3V + * SW3A | 1.5V + * SW3B | 1.5V + * VGEN1 | 1.5V + * VGEN2 | 1.5V + * VGEN3 | 2.5V + * VGEN4 | 1.8V + * VGEN5 | 2.8V + * VGEN6 | 3.3V + * + * According to schematic, we need SW3A 1.35V, SW3B 3.3V, + * VGEN1 1.2V, VGEN2 1.5V, VGEN3 2.8V, VGEN4 1.8V, + * VGEN5 3.3V, VGEN6 3.0V. + * + * Here we just use the default VOLT, but not configure + * them, when needed, configure them to our requested voltage. + */ + + /* Set SW1AB stanby volage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg); + + /* Enable power of VGEN5 3V3 */ + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL); + reg &= ~0x1F; + reg |= 0x1F; + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + struct udevice *dev; + int ret; + int is_400M; + u32 vddarm; + + ret = pmic_get("pfuze100", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + /* decrease VDDARM to 1.275V */ + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, PFUZE100_SW1ABC_SETP(12750)); + + is_400M = set_anatop_bypass(1); + if (is_400M) + vddarm = PFUZE100_SW1ABC_SETP(10750); + else + vddarm = PFUZE100_SW1ABC_SETP(11750); + + pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm); + + set_anatop_bypass(1); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif + +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(CONFIG_FEC_ENET_DEV); +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_MXC_EPDC + enable_epdc_clock(); + setup_epdc(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, + {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX6ULL 14X14 DDR3 Validation\n"); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +#ifndef CONFIG_DM_USB + +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX6_PAD_GPIO1_IO04__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +/* + * Leave it here, but default configuration only supports 1 port now, + * because we need sd1 and i2c1 + */ +iomux_v3_cfg_t const usb_otg2_pads[] = { + /* conflict with i2c1_scl */ + MX6_PAD_GPIO1_IO02__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* conflict with sd1_vselect */ + MX6_PAD_GPIO1_IO05__ANATOP_OTG2_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), +}; + +int board_usb_phy_mode(int port) +{ + return usb_phy_mode(port); +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + switch (port) { + case 0: + SETUP_IOMUX_PADS(usb_otg1_pads); + break; + case 1: + SETUP_IOMUX_PADS(usb_otg2_pads); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return 1; + } + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; +} +#endif +#endif diff --git a/board/freescale/mx6ull_ddr3_val/plugin.S b/board/freescale/mx6ull_ddr3_val/plugin.S new file mode 100644 index 00000000000..0538d1d5713 --- /dev/null +++ b/board/freescale/mx6ull_ddr3_val/plugin.S @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx6ull_ddr3_val_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x000C0000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + ldr r1, =0x000C0030 + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + + ldr r1, =0x00000030 + str r1, [r0, #0x260] + str r1, [r0, #0x264] + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00000030 + str r1, [r0, #0x280] + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00150019 + str r1, [r0, #0x80C] + ldr r1, =0x41550153 + str r1, [r0, #0x83C] + ldr r1, =0x40403A3E + str r1, [r0, #0x848] + ldr r1, =0x40402F2A + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x00944009 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + ldr r1, =0x0002002D + str r1, [r0, #0x004] + ldr r1, =0x1B333030 + str r1, [r0, #0x008] + ldr r1, =0x676B52F3 + str r1, [r0, #0x00C] + ldr r1, =0xB66D0B63 + str r1, [r0, #0x010] + ldr r1, =0x01FF00DB + str r1, [r0, #0x014] + ldr r1, =0x00211740 + str r1, [r0, #0x018] + ldr r1, =0x00008000 + str r1, [r0, #0x01C] + ldr r1, =0x000026D2 + str r1, [r0, #0x02C] + ldr r1, =0x006B1023 + str r1, [r0, #0x030] + ldr r1, =0x0000005F + str r1, [r0, #0x040] + ldr r1, =0x85180000 + str r1, [r0, #0x000] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + ldr r1, =0x02008032 + str r1, [r0, #0x01C] + ldr r1, =0x00008033 + str r1, [r0, #0x01C] + ldr r1, =0x00048031 + str r1, [r0, #0x01C] + ldr r1, =0x15208030 + str r1, [r0, #0x01C] + ldr r1, =0x04008040 + str r1, [r0, #0x01C] + ldr r1, =0x00000800 + str r1, [r0, #0x020] + ldr r1, =0x00000227 + str r1, [r0, #0x818] + ldr r1, =0x0002552D + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + +.macro imx6_clock_gating + ldr r0, =CCM_BASE_ADDR + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x68] + str r1, [r0, #0x6C] + str r1, [r0, #0x70] + str r1, [r0, #0x74] + str r1, [r0, #0x78] + str r1, [r0, #0x7C] + str r1, [r0, #0x80] +.endm + +.macro imx6_qos_setting +.endm + +.macro imx6_ddr_setting + imx6ull_ddr3_val_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig index 7eec497e3ea..985763c84f0 100644 --- a/board/freescale/mx6ullevk/Kconfig +++ b/board/freescale/mx6ullevk/Kconfig @@ -1,4 +1,4 @@ -if TARGET_MX6ULL_14X14_EVK +if TARGET_MX6ULL_14X14_EVK || TARGET_MX6ULL_9X9_EVK config SYS_BOARD default "mx6ullevk" @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx6ullevk" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx6ullevk/imximage.cfg b/board/freescale/mx6ullevk/imximage.cfg index 155503997d2..11db2ced9df 100644 --- a/board/freescale/mx6ullevk/imximage.cfg +++ b/board/freescale/mx6ullevk/imximage.cfg @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure * and create imximage boot image @@ -58,6 +59,11 @@ DATA 4 0x020c4078 0xffffffff DATA 4 0x020c407c 0xffffffff DATA 4 0x020c4080 0xffffffff +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + DATA 4 0x020E04B4 0x000C0000 DATA 4 0x020E04AC 0x00000000 DATA 4 0x020E027C 0x00000030 diff --git a/board/freescale/mx6ullevk/imximage_lpddr2.cfg b/board/freescale/mx6ullevk/imximage_lpddr2.cfg new file mode 100644 index 00000000000..bceec0485f6 --- /dev/null +++ b/board/freescale/mx6ullevk/imximage_lpddr2.cfg @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_QSPI_BOOT +BOOT_FROM qspi +#elif defined(CONFIG_NOR_BOOT) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x20e4024 0x00000001 +CHECK_BITS_SET 4 0x20e4024 0x1 +#endif + +DATA 4 0x020E04B4 0x00080000 +DATA 4 0x020E04AC 0x00000000 +DATA 4 0x020E027C 0x00000030 +DATA 4 0x020E0250 0x00000030 +DATA 4 0x020E024C 0x00000030 +DATA 4 0x020E0490 0x00000030 +DATA 4 0x020E0288 0x00000030 +DATA 4 0x020E0270 0x00000000 +DATA 4 0x020E0260 0x00000000 +DATA 4 0x020E0264 0x00000000 +DATA 4 0x020E04A0 0x00000030 +DATA 4 0x020E0494 0x00020000 +DATA 4 0x020E0280 0x00003030 +DATA 4 0x020E0284 0x00003030 +DATA 4 0x020E04B0 0x00020000 +DATA 4 0x020E0498 0x00000030 +DATA 4 0x020E04A4 0x00000030 +DATA 4 0x020E0244 0x00000030 +DATA 4 0x020E0248 0x00000030 + +DATA 4 0x021B001C 0x00008000 +DATA 4 0x021B085C 0x1b4700c7 +DATA 4 0x021B0800 0xA1390003 +DATA 4 0x021B0890 0x23400A38 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B081C 0x33333333 +DATA 4 0x021B0820 0x33333333 +DATA 4 0x021B082C 0xf3333333 +DATA 4 0x021B0830 0xf3333333 +DATA 4 0x021B083C 0x20000000 +DATA 4 0x021B0848 0x40403439 +DATA 4 0x021B0850 0x4040342D +DATA 4 0x021B08C0 0x00921012 +DATA 4 0x021B08b8 0x00000800 + +DATA 4 0x021B0004 0x00020052 +DATA 4 0x021B0008 0x00000000 +DATA 4 0x021B000C 0x33374133 +DATA 4 0x021B0010 0x00100A82 +DATA 4 0x021B0038 0x00170557 +DATA 4 0x021B0014 0x00000093 +DATA 4 0x021B0018 0x00201748 +DATA 4 0x021B002C 0x0F9F26D2 +DATA 4 0x021B0030 0x009F0010 +DATA 4 0x021B0040 0x00000047 +DATA 4 0x021B0000 0x83100000 +DATA 4 0x021B001C 0x00008010 +DATA 4 0x021B001C 0x003F8030 +DATA 4 0x021B001C 0xFF0A8030 +DATA 4 0x021B001C 0x82018030 +DATA 4 0x021B001C 0x04028030 +DATA 4 0x021B001C 0x01038030 +DATA 4 0x021B0020 0x00001800 +DATA 4 0x021B0818 0x00000000 +DATA 4 0x021B0800 0xA1310003 +DATA 4 0x021B0004 0x00025552 +DATA 4 0x021B0404 0x00011006 +DATA 4 0x021B001C 0x00000000 +#endif diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c index 86c11c7bd3a..72e4898ae86 100644 --- a/board/freescale/mx6ullevk/mx6ullevk.c +++ b/board/freescale/mx6ullevk/mx6ullevk.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP */ #include @@ -14,13 +15,20 @@ #include #include #include +#include #include #include #include #include +#include +#include #include +#include #include #include +#include +#include +#include "../common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; @@ -28,6 +36,93 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm) + +#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) +#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ + PAD_CTL_SRE_FAST) +#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1) + + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id; + unsigned int reg; + + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40); + + /* SW1B mode to APS/PFM */ + pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc); + + /* SW1B standby voltage set to 0.975V */ + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb); + + return 0; +} + +#ifdef CONFIG_LDO_BYPASS_CHECK +void ldo_mode_set(int ldo_bypass) +{ + unsigned int value; + u32 vddarm; + struct udevice *dev; + int ret; + + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) { + printf("No PMIC found!\n"); + return; + } + + /* switch to ldo_bypass mode */ + if (ldo_bypass) { + prep_anatop_bypass(); + /* decrease VDDARM to 1.275V */ + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + value &= ~0x1f; + value |= PFUZE3000_SW1AB_SETP(12750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); + + set_anatop_bypass(1); + vddarm = PFUZE3000_SW1AB_SETP(11750); + + value = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + value &= ~0x1f; + value |= vddarm; + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, value); + + finish_anatop_bypass(); + + printf("switch to ldo_bypass mode!\n"); + } +} +#endif +#endif + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -45,49 +140,105 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -int board_mmc_get_env_dev(int devno) -{ - return devno; -} +#ifdef CONFIG_FSL_QSPI + +#ifndef CONFIG_DM_SPI +#define QSPI_PAD_CTRL1 \ + (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \ + PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm) + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX6_PAD_NAND_WP_B__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_READY_B__QSPI_A_DATA00 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE0_B__QSPI_A_DATA01 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CE1_B__QSPI_A_DATA02 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_CLE__QSPI_A_DATA03 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX6_PAD_NAND_DQS__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif -int mmc_map_to_kernel_blk(int devno) +static int board_qspi_init(void) { - return devno; +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, + ARRAY_SIZE(quadspi_pads)); +#endif + /* Set the clock */ + enable_qspi_clk(0); + + return 0; } +#endif -int board_early_init_f(void) +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const nand_pads[] = { + MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_CE1_B__RAWNAND_CE1_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2), + MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2), +}; + +static void setup_gpmi_nand(void) { - setup_iomux_uart(); + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - return 0; + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads)); + + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); } +#endif #ifdef CONFIG_FEC_MXC -static int setup_fec(int fec_id) +static int setup_fec(void) { struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; - if (fec_id == 0) { - /* - * Use 50MHz anatop loopback REF_CLK1 for ENET1, - * clear gpr1[13], set gpr1[17]. - */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, - IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); - } else { - /* - * Use 50MHz anatop loopback REF_CLK2 for ENET2, - * clear gpr1[14], set gpr1[18]. - */ + /* + * Use 50M anatop loopback REF_CLK1 for ENET1, + * clear gpr1[13], set gpr1[17]. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK); + /* + * Use 50M anatop loopback REF_CLK2 for ENET2, + * clear gpr1[14], set gpr1[18]. + */ + if (!check_module_fused(MODULE_ENET2)) { clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); } - ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ); + ret = enable_fec_anatop_clock(0, ENET_50MHZ); if (ret) return ret; + if (!check_module_fused(MODULE_ENET2)) { + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + } + enable_enet_clk(1); return 0; @@ -104,13 +255,56 @@ int board_phy_config(struct phy_device *phydev) } #endif +#ifdef CONFIG_DM_VIDEO +static iomux_v3_cfg_t const lcd_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period. */ + MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static int setup_lcd(void) +{ + enable_lcdif_clock(LCDIF1_BASE_ADDR, 1); + + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + /* Reset the LCD */ + gpio_request(IMX_GPIO_NR(5, 9), "lcd reset"); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 0); + udelay(500); + gpio_direction_output(IMX_GPIO_NR(5, 9) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 8), "backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 8) , 1); + + return 0; +} +#else +static inline int setup_lcd(void) { return 0; } +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + int board_init(void) { /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; #ifdef CONFIG_FEC_MXC - setup_fec(CONFIG_FEC_ENET_DEV); + setup_fec(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); #endif return 0; @@ -132,20 +326,41 @@ int board_late_init(void) add_board_boot_modes(board_boot_modes); #endif + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (is_cpu_type(MXC_CPU_MX6ULZ)) - env_set("board_name", "ULZ-EVK"); + env_set("board_name", "EVK"); + + if (is_mx6ull_9x9_evk()) + env_set("board_rev", "9X9"); else - env_set("board_name", "EVK"); - env_set("board_rev", "14X14"); + env_set("board_rev", "14X14"); + + if (is_cpu_type(MXC_CPU_MX6ULZ)) { + env_set("board_name", "ULZ-EVK"); + env_set("usb_net_cmd", "usb start"); + } #endif + setup_lcd(); + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } int checkboard(void) { - if (is_cpu_type(MXC_CPU_MX6ULZ)) + if (is_mx6ull_9x9_evk()) + puts("Board: MX6ULL 9x9 EVK\n"); + else if (is_cpu_type(MXC_CPU_MX6ULZ)) puts("Board: MX6ULZ 14x14 EVK\n"); else puts("Board: MX6ULL 14x14 EVK\n"); diff --git a/board/freescale/mx6ullevk/plugin.S b/board/freescale/mx6ullevk/plugin.S index 1f631ff5e3e..812088d13c1 100644 --- a/board/freescale/mx6ullevk/plugin.S +++ b/board/freescale/mx6ullevk/plugin.S @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP */ #include @@ -115,6 +116,120 @@ str r1, [r0, #0x01C] .endm +.macro imx6ull_lpddr2_evk_setting + ldr r0, =IOMUXC_BASE_ADDR + ldr r1, =0x00080000 + str r1, [r0, #0x4B4] + ldr r1, =0x00000000 + str r1, [r0, #0x4AC] + ldr r1, =0x00000030 + str r1, [r0, #0x27C] + str r1, [r0, #0x250] + str r1, [r0, #0x24C] + str r1, [r0, #0x490] + str r1, [r0, #0x288] + + ldr r1, =0x00000000 + str r1, [r0, #0x270] + str r1, [r0, #0x260] + str r1, [r0, #0x264] + + ldr r1, =0x00000030 + str r1, [r0, #0x4A0] + + ldr r1, =0x00020000 + str r1, [r0, #0x494] + + ldr r1, =0x00003030 + str r1, [r0, #0x280] + ldr r1, =0x00003030 + str r1, [r0, #0x284] + + ldr r1, =0x00020000 + str r1, [r0, #0x4B0] + + ldr r1, =0x00000030 + str r1, [r0, #0x498] + str r1, [r0, #0x4A4] + str r1, [r0, #0x244] + str r1, [r0, #0x248] + + ldr r0, =MMDC_P0_BASE_ADDR + ldr r1, =0x00008000 + str r1, [r0, #0x1C] + ldr r1, =0x1b4700c7 + str r1, [r0, #0x85c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x23400A38 + str r1, [r0, #0x890] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + ldr r1, =0x33333333 + str r1, [r0, #0x81C] + str r1, [r0, #0x820] + ldr r1, =0xF3333333 + str r1, [r0, #0x82C] + str r1, [r0, #0x830] + ldr r1, =0x20000000 + str r1, [r0, #0x83C] + ldr r1, =0x40403439 + str r1, [r0, #0x848] + ldr r1, =0x4040342D + str r1, [r0, #0x850] + ldr r1, =0x00921012 + str r1, [r0, #0x8C0] + ldr r1, =0x00000800 + str r1, [r0, #0x8B8] + + ldr r1, =0x00020052 + str r1, [r0, #0x004] + ldr r1, =0x00000000 + str r1, [r0, #0x008] + ldr r1, =0x33374133 + str r1, [r0, #0x00C] + ldr r1, =0x00100A82 + str r1, [r0, #0x010] + ldr r1, =0x00170557 + str r1, [r0, #0x038] + ldr r1, =0x00000093 + str r1, [r0, #0x014] + ldr r1, =0x00201748 + str r1, [r0, #0x018] + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x02C] + ldr r1, =0x009F0010 + str r1, [r0, #0x030] + ldr r1, =0x00000047 + str r1, [r0, #0x040] + ldr r1, =0x83100000 + str r1, [r0, #0x000] + ldr r1, =0x00008010 + str r1, [r0, #0x01C] + ldr r1, =0x003F8030 + str r1, [r0, #0x01C] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x01C] + ldr r1, =0x82018030 + str r1, [r0, #0x01C] + ldr r1, =0x04028030 + str r1, [r0, #0x01C] + ldr r1, =0x01038030 + str r1, [r0, #0x01C] + ldr r1, =0x00001800 + str r1, [r0, #0x020] + ldr r1, =0x00000000 + str r1, [r0, #0x818] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00025552 + str r1, [r0, #0x004] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x01C] +.endm + .macro imx6_clock_gating ldr r0, =CCM_BASE_ADDR ldr r1, =0xFFFFFFFF @@ -125,13 +240,23 @@ str r1, [r0, #0x78] str r1, [r0, #0x7C] str r1, [r0, #0x80] + +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x20e4024 + ldr r1, =0x1 + str r1, [r0] +#endif .endm .macro imx6_qos_setting .endm .macro imx6_ddr_setting +#if defined (CONFIG_TARGET_MX6ULL_9X9_EVK) + imx6ull_lpddr2_evk_setting +#else imx6ull_ddr3_evk_setting +#endif .endm /* include the common plugin code here */ diff --git a/board/freescale/mx7d_12x12_ddr3_val/Kconfig b/board/freescale/mx7d_12x12_ddr3_val/Kconfig new file mode 100644 index 00000000000..efe29ed8bec --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_val/Kconfig @@ -0,0 +1,14 @@ +if TARGET_MX7D_12X12_DDR3_VAL + +config SYS_BOARD + default "mx7d_12x12_ddr3_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7d_12x12_ddr3_val" + +config SYS_TEXT_BASE + default 0x87800000 +endif diff --git a/board/freescale/mx7d_12x12_ddr3_val/Makefile b/board/freescale/mx7d_12x12_ddr3_val/Makefile new file mode 100644 index 00000000000..21985cfe56a --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7d_12x12_ddr3_val.o diff --git a/board/freescale/mx7d_12x12_ddr3_val/imximage.cfg b/board/freescale/mx7d_12x12_ddr3_val/imximage.cfg new file mode 100644 index 00000000000..8c2adfc826f --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_val/imximage.cfg @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * sd/onenand, nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000b24 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7d_12x12_ddr3_val/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_ddr3_val/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..89a14259444 --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_val/imximage_TO_1_1.cfg @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * sd/onenand, nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_ddr3_val/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30360070 0x00703021 +DATA 4 0x30360090 0x0 +DATA 4 0x30360070 0x00603021 +CHECK_BITS_SET 4 0x30360070 0x80000000 +DATA 4 0x30389880 0x1 + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000dee +DATA 4 0x3079007c 0x18181818 +DATA 4 0x30790080 0x18181818 +DATA 4 0x30790084 0x40401818 +DATA 4 0x30790088 0x00000040 +DATA 4 0x3079006c 0x40404040 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7d_12x12_ddr3_val/mx7d_12x12_ddr3_val.c b/board/freescale/mx7d_12x12_ddr3_val/mx7d_12x12_ddr3_val.c new file mode 100644 index 00000000000..cb83f835742 --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_val/mx7d_12x12_ddr3_val.c @@ -0,0 +1,183 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SD1_WP__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SD1_CD_B__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + /* Chip selects CS0:CS3 */ + MX7D_PAD_SD1_CLK__GPIO5_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_SD1_CMD__GPIO5_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_SD1_DATA0__GPIO5_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_SD1_DATA1__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(5, 3), "ecspi1_cs"); + gpio_direction_output(IMX_GPIO_NR(5, 3), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 3 && cs == 0) ? (IMX_GPIO_NR(5, 3)) : -1; +} +#endif +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id, reg; + + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* set SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX7D 12x12 DDR3 VAL\n"); + + return 0; +} diff --git a/board/freescale/mx7d_12x12_ddr3_val/plugin.S b/board/freescale/mx7d_12x12_ddr3_val/plugin.S new file mode 100644 index 00000000000..f1980b8879e --- /dev/null +++ b/board/freescale/mx7d_12x12_ddr3_val/plugin.S @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_12x12_ddr3_val_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_12x12_ddr3_val_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7d_12x12_lpddr3_val/Kconfig b/board/freescale/mx7d_12x12_lpddr3_val/Kconfig new file mode 100644 index 00000000000..31ede4d88cf --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_val/Kconfig @@ -0,0 +1,14 @@ +if TARGET_MX7D_12X12_LPDDR3_VAL + +config SYS_BOARD + default "mx7d_12x12_lpddr3_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7d_12x12_lpddr3_val" + +config SYS_TEXT_BASE + default 0x87800000 +endif diff --git a/board/freescale/mx7d_12x12_lpddr3_val/Makefile b/board/freescale/mx7d_12x12_lpddr3_val/Makefile new file mode 100644 index 00000000000..ca48fa0b950 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7d_12x12_lpddr3_val.o diff --git a/board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg b/board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg new file mode 100644 index 00000000000..5d650b2a5e3 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_lpddr3_val/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00090909 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x08080808 +DATA 4 0x307a0218 0x0f0f0808 + +DATA 4 0x307a0240 0x06000600 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x00000b24 + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x0e487304 +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e4c7306 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_12x12_lpddr3_val/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_lpddr3_val/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..76de211a2dd --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_val/imximage_TO_1_1.cfg @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_12x12_lpddr3_val/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00090909 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x08080808 +DATA 4 0x307a0218 0x0f0f0808 + +DATA 4 0x307a0240 0x06000601 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x3079007c 0x1c1c1c1c +DATA 4 0x30790080 0x1c1c1c1c +DATA 4 0x30790084 0x30301c1c +DATA 4 0x30790088 0x00000030 +DATA 4 0x3079006c 0x30303030 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x0db60d6e + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487306 +DATA 4 0x307900c0 0x1e4c7304 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x1e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_12x12_lpddr3_val/mx7d_12x12_lpddr3_val.c b/board/freescale/mx7d_12x12_lpddr3_val/mx7d_12x12_lpddr3_val.c new file mode 100644 index 00000000000..195b43a1609 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_val/mx7d_12x12_lpddr3_val.c @@ -0,0 +1,654 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#include +#include +#include + +#ifdef CONFIG_VIDEO_MXS +#include +#endif +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define EPDC_PAD_CTRL 0x0 + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwm_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = ELCDIF1_IPS_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + + +static iomux_v3_cfg_t const per_rst_pads[] = { + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_TX_CLK__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec1(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec1(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS0 */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs"); + gpio_direction_output(IMX_GPIO_NR(4, 19), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1; +} +#endif +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_MXC_EPDC +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__EPDC_SDCE3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX7D_PAD_EPDC_DATA00__GPIO2_IO0, + MX7D_PAD_EPDC_DATA01__GPIO2_IO1, + MX7D_PAD_EPDC_DATA02__GPIO2_IO2, + MX7D_PAD_EPDC_DATA03__GPIO2_IO3, + MX7D_PAD_EPDC_DATA04__GPIO2_IO4, + MX7D_PAD_EPDC_DATA05__GPIO2_IO5, + MX7D_PAD_EPDC_DATA06__GPIO2_IO6, + MX7D_PAD_EPDC_DATA07__GPIO2_IO7, + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, + MX7D_PAD_EPDC_SDLE__GPIO2_IO17, + MX7D_PAD_EPDC_SDOE__GPIO2_IO18, + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, + MX7D_PAD_EPDC_SDCE2__GPIO2_IO22, + MX7D_PAD_EPDC_SDCE3__GPIO2_IO23, + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, + MX7D_PAD_EPDC_GDOE__GPIO2_IO25, + MX7D_PAD_EPDC_GDRL__GPIO2_IO26, + MX7D_PAD_EPDC_GDSP__GPIO2_IO27, + MX7D_PAD_EPDC_BDR0__GPIO2_IO28, + MX7D_PAD_EPDC_BDR1__GPIO2_IO29, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +static void setup_epdc_power(void) +{ + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat"); + gpio_direction_input(IMX_GPIO_NR(2, 31)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom0"); + gpio_direction_output(IMX_GPIO_NR(4, 14), 1); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 23), "epdc_pwrwakeup"); + gpio_direction_output(IMX_GPIO_NR(4, 23), 1); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + /* Set as output */ + gpio_request(IMX_GPIO_NR(4, 20), "epdc_pwrctrl0"); + gpio_direction_output(IMX_GPIO_NR(4, 20), 1); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(4, 20), 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + gpio_set_value(IMX_GPIO_NR(4, 23), 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 31))) + break; + + udelay(100); + } + + /* Enable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + gpio_set_value(IMX_GPIO_NR(4, 23), 0); + + /* Disable VCOM */ + gpio_set_value(IMX_GPIO_NR(4, 14), 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + gpio_set_value(IMX_GPIO_NR(4, 20), 0); +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Reset peripherals */ + imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 3), "per_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 3) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 3), 1); + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + +#ifdef CONFIG_MXC_EPDC + setup_epdc(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)}, + {"emmc", MAKE_CFGVAL(0x10, 0x2a, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id, reg; + + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* below are for LPSR mode support */ + reg = pmic_reg_read(dev, PFUZE3000_SW3MODE); + reg |= 0x20; + pmic_reg_write(dev, PFUZE3000_SW3MODE, reg); + + reg = pmic_reg_read(dev, PFUZE3000_VLDO1CTL); + reg |= 0x80; + pmic_reg_write(dev, PFUZE3000_VLDO1CTL, reg); + + reg = pmic_reg_read(dev, PFUZE3000_VLDO3CTL); + reg |= 0x80; + pmic_reg_write(dev, PFUZE3000_VLDO3CTL, reg); + + reg = pmic_reg_read(dev, PFUZE3000_SW2MODE); + reg |= 0x20; + pmic_reg_write(dev, PFUZE3000_SW2MODE, reg); + + /* set SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX7D 12x12 LPDDR3 VAL\n"); + + return 0; +} diff --git a/board/freescale/mx7d_12x12_lpddr3_val/plugin.S b/board/freescale/mx7d_12x12_lpddr3_val/plugin.S new file mode 100644 index 00000000000..ff629c865a5 --- /dev/null +++ b/board/freescale/mx7d_12x12_lpddr3_val/plugin.S @@ -0,0 +1,657 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne TUNE_END + + /*TO 1.1*/ + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x7c] + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x80] + ldr r1, =0x30301c1c + str r1, [r0, #0x84] + ldr r1, =0x00000030 + str r1, [r0, #0x88] + ldr r1, =0x30303030 + str r1, [r0, #0x6c] + +TUNE_END: +.endm + +.macro imx7d_12x12_lpddr3_val_setting + + /* check whether it is a LPSR resume */ + ldr r1, =0x30270000 + ldr r7, [r1] + cmp r7, #0 + beq 16f + + /* disable wdog powerdown counter */ + ldr r0, =0x30280000 + ldrh r1, =0x0 + strh r1, [r0, #0x8] + + /* initialize AIPs 1-3 port */ + ldr r0, =0x301f0000 + ldr r1, =0x77777777 + str r1, [r0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4c] + str r1, [r0, #0x50] + + ldr r0, =0x305f0000 + ldr r1, =0x77777777 + str r1, [r0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4c] + str r1, [r0, #0x50] + + ldr r0, =0x309f0000 + ldr r1, =0x77777777 + str r1, [r0] + str r1, [r0, #0x4] + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4c] + str r1, [r0, #0x50] + + ldr r1, =0x30360000 + ldr r2, =0x30390000 + ldr r3, =0x307a0000 + ldr r4, =0x30790000 + ldr r10, =0x30380000 + ldr r11, =0x30340000 + + /* turn on ddr power */ + ldr r7, =(0x1 << 29) + str r7, [r1, #0x388] + + ldr r6, =50 +1: + subs r6, r6, #0x1 + bne 1b + + /* clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + orr r7, r7, #0x3 + str r7, [r2, r6] + ldr r7, [r2, r6] + bic r7, r7, #0x1 + str r7, [r2, r6] + + /* restore DDRC */ + ldr r6, =0x0 + ldr r7, =0x03040008 + str r7, [r3, r6] + + ldr r6, =0x1a0 + ldr r7, =0x80400003 + str r7, [r3, r6] + + ldr r6, =0x1a4 + ldr r7, =0x00100020 + str r7, [r3, r6] + + ldr r6, =0x1a8 + ldr r7, =0x80100004 + str r7, [r3, r6] + + ldr r6, =0x64 + ldr r7, =0x00200038 + str r7, [r3, r6] + + ldr r6, =0xd0 + ldr r7, =0xc0350001 + str r7, [r3, r6] + + ldr r6, =0xdc + ldr r7, =0x00C3000A + str r7, [r3, r6] + + ldr r6, =0xe0 + ldr r7, =0x00010000 + str r7, [r3, r6] + + ldr r6, =0xe4 + ldr r7, =0x00110006 + str r7, [r3, r6] + + ldr r6, =0xf4 + ldr r7, =0x0000033F + str r7, [r3, r6] + + ldr r6, =0x100 + ldr r7, =0x0A0E110B + str r7, [r3, r6] + + ldr r6, =0x104 + ldr r7, =0x00020211 + str r7, [r3, r6] + + ldr r6, =0x108 + ldr r7, =0x03060708 + str r7, [r3, r6] + + ldr r6, =0x10c + ldr r7, =0x00A0500C + str r7, [r3, r6] + + ldr r6, =0x110 + ldr r7, =0x05020307 + str r7, [r3, r6] + + ldr r6, =0x114 + ldr r7, =0x02020404 + str r7, [r3, r6] + + ldr r6, =0x118 + ldr r7, =0x02020003 + str r7, [r3, r6] + + ldr r6, =0x11c + ldr r7, =0x00000202 + str r7, [r3, r6] + + ldr r6, =0x120 + ldr r7, =0x00000202 + str r7, [r3, r6] + + ldr r6, =0x180 + ldr r7, =0x00600018 + str r7, [r3, r6] + + ldr r6, =0x184 + ldr r7, =0x00e00100 + str r7, [r3, r6] + + ldr r6, =0x190 + ldr r7, =0x02098205 + str r7, [r3, r6] + + ldr r6, =0x194 + ldr r7, =0x00060303 + str r7, [r3, r6] + + ldr r6, =0x200 + ldr r7, =0x00000016 + str r7, [r3, r6] + + ldr r6, =0x204 + ldr r7, =0x00090909 + str r7, [r3, r6] + + ldr r6, =0x210 + ldr r7, =0xF00 + str r7, [r3, r6] + + ldr r6, =0x214 + ldr r7, =0x08080808 + str r7, [r3, r6] + + ldr r6, =0x218 + ldr r7, =0x0f0f0808 + str r7, [r3, r6] + + ldr r6, =0x240 + ldr r7, =0x06000600 + str r7, [r3, r6] + + ldr r6, =0x244 + ldr r7, =0x00000000 + str r7, [r3, r6] + + ldr r7, =0x20 + str r7, [r3, #0x30] + ldr r7, =0x0 + str r7, [r3, #0x1b0] + + /* do PHY, clear ddr_phy reset */ + ldr r6, =0x1000 + ldr r7, [r2, r6] + bic r7, r7, #0x2 + str r7, [r2, r6] + + ldr r7, [r1, #0x800] + and r7, r7, #0xFF + cmp r7, #0x11 + bne 2f + + /* for TO1.1 */ + ldr r7, [r11] + bic r7, r7, #(1 << 27) + str r7, [r11] + ldr r7, [r11] + bic r7, r7, #(1 << 29) + str r7, [r11] +2: + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r7, =(0x1 << 30) + str r7, [r1, #0x388] + ldr r7, =(0x1 << 30) + str r7, [r1, #0x384] + + /* need to delay ~5mS */ + ldr r6, =0x100000 +3: + subs r6, r6, #0x1 + bne 3b + + /* restore DDR PHY */ + ldr r6, =0x0 + ldr r7, =0x17421E40 + str r7, [r4, r6] + + ldr r6, =0x4 + ldr r7, =0x10210100 + str r7, [r4, r6] + + ldr r6, =0x8 + ldr r7, =0x00010000 + str r7, [r4, r6] + + ldr r6, =0x10 + ldr r7, =0x0007080C + str r7, [r4, r6] + + ldr r6, =0xb0 + ldr r7, =0x1010007e + str r7, [r4, r6] + + ldr r7, [r1, #0x800] + and r7, r7, #0xFF + cmp r7, #0x11 + bne 4f + + ldr r6, =0x7c + ldr r7, =0x1c1c1c1c + str r7, [r4, r6] + + ldr r6, =0x80 + ldr r7, =0x1c1c1c1c + str r7, [r4, r6] + + ldr r6, =0x84 + ldr r7, =0x30301c1c + str r7, [r4, r6] + + ldr r6, =0x88 + ldr r7, =0x00000030 + str r7, [r4, r6] + + ldr r6, =0x6c + ldr r7, =0x30303030 + str r7, [r4, r6] + + ldr r6, =0x1c + ldr r7, =0x01010000 + str r7, [r4, r6] + + ldr r6, =0x9c + ldr r7, =0x0DB60D6E + str r7, [r4, r6] + + b 5f + +4: + ldr r6, =0x1c + ldr r7, =0x01010000 + str r7, [r4, r6] + + ldr r6, =0x9c + ldr r7, =0x00000b24 + str r7, [r4, r6] + +5: + ldr r6, =0x20 + ldr r7, =0x0a0a0a0a + str r7, [r4, r6] + + ldr r6, =0x30 + ldr r7, =0x06060606 + str r7, [r4, r6] + + ldr r6, =0x50 + ldr r7, =0x01000008 + str r7, [r4, r6] + + ldr r6, =0x50 + ldr r7, =0x00000008 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e487304 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e4c7304 + str r7, [r4, r6] + + ldr r6, =0xc0 + ldr r7, =0x0e4c7306 + str r7, [r4, r6] + +6: + ldr r7, [r4, #0xc4] + tst r7, #0x1 + beq 6b + + ldr r6, =0xc0 + ldr r7, =0x0e487304 + str r7, [r4, r6] + + ldr r7, =0x0 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0x170 + orr r7, r7, #0x8 + str r7, [r11, #0x20] + + ldr r7, =0x2 + add r9, r10, #0x4000 + str r7, [r9, #0x130] + + ldr r7, =0xf + str r7, [r4, #0x18] + + /* wait until self-refresh mode entered */ +11: + ldr r7, [r3, #0x4] + and r7, r7, #0x3 + cmp r7, #0x3 + bne 11b + ldr r7, =0x0 + str r7, [r3, #0x320] + ldr r7, =0x1 + str r7, [r3, #0x1b0] + ldr r7, =0x1 + str r7, [r3, #0x320] +12: + ldr r7, [r3, #0x324] + and r7, r7, #0x1 + cmp r7, #0x1 + bne 12b +13: + ldr r7, [r3, #0x4] + and r7, r7, #0x20 + cmp r7, #0x20 + bne 13b + + /* let DDR out of self-refresh */ + ldr r7, =0x0 + str r7, [r3, #0x30] +14: + ldr r7, [r3, #0x4] + and r7, r7, #0x30 + cmp r7, #0x0 + bne 14b + +15: + ldr r7, [r3, #0x4] + and r7, r7, #0x3 + cmp r7, #0x1 + bne 15b + + imx7_qos_setting + + /* enable port */ + ldr r7, =0x1 + str r7, [r3, #0x490] + + /* jump to kernel resume */ + ldr r1, =0x30270000 + ldr r7, [r1] + + mov pc, r7 +16: + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x03040008 + str r1, [r0] + ldr r1, =0x00200038 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00350001 + str r1, [r0, #0xd0] + ldr r1, =0x00c3000a + str r1, [r0, #0xdc] + ldr r1, =0x00010000 + str r1, [r0, #0xe0] + ldr r1, =0x00110006 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x0a0e110b + str r1, [r0, #0x100] + ldr r1, =0x00020211 + str r1, [r0, #0x104] + ldr r1, =0x03060708 + str r1, [r0, #0x108] + ldr r1, =0x00a0500c + str r1, [r0, #0x10c] + ldr r1, =0x05020307 + str r1, [r0, #0x110] + ldr r1, =0x02020404 + str r1, [r0, #0x114] + ldr r1, =0x02020003 + str r1, [r0, #0x118] + ldr r1, =0x00000202 + str r1, [r0, #0x11c] + ldr r1, =0x00000202 + str r1, [r0, #0x120] + ldr r1, =0x00600018 + str r1, [r0, #0x180] + ldr r1, =0x00e00100 + str r1, [r0, #0x184] + ldr r1, =0x02098205 + str r1, [r0, #0x190] + ldr r1, =0x00060303 + str r1, [r0, #0x194] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00090909 + str r1, [r0, #0x204] + ldr r1, =0x00000f00 + str r1, [r0, #0x210] + ldr r1, =0x08080808 + str r1, [r0, #0x214] + ldr r1, =0x0f0f0808 + str r1, [r0, #0x218] + + ldr r1, =0x06000600 + str r1, [r0, #0x240] + mov r1, #0x0 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17421e40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00010000 + str r1, [r0, #0x8] + ldr r1, =0x0007080c + str r1, [r0, #0x10] + imx7d_ddrphy_latency_setting + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + ldr r1, =0x01010000 + str r1, [r0, #0x1c] + + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne 17f + + ldr r1, =0x0db60d6e + str r1, [r0, #0x9c] + b 18f +17: + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] +18: + ldr r1, =0x06060606 + str r1, [r0, #0x30] + ldr r1, =0x0a0a0a0a + str r1, [r0, #0x20] + ldr r1, =0x01000008 + str r1, [r0, #0x50] + ldr r1, =0x00000008 + str r1, [r0, #0x50] + + ldr r1, =0x0000000f + str r1, [r0, #0x18] + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x30340024 + ldr r1, =0x1 + str r1, [r0] +#endif +.endm + +.macro imx7_qos_setting + ldr r0, =REGS_QOS_BASE + ldr r1, =0 + str r1, [r0, #0] + + ldr r1, =0 + str r1, [r0, #0x60] + + ldr r0, =REGS_QOS_EPDC + ldr r1, =0 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_PXP1 + ldr r1, =0 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_EPDC + ldr r1, =0x0f020f22 + str r1, [r0, #0xd0] + str r1, [r0, #0xe0] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x1 + str r1, [r0, #0] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x0f020222 + str r1, [r0, #0x50] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0x50] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x0f020222 + str r1, [r0, #0x60] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0x60] + + ldr r0, =REGS_QOS_PXP0 + ldr r1, =0x0f020422 + str r1, [r0, #0x70] + ldr r0, =REGS_QOS_PXP1 + str r1, [r0, #0x70] + + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0xe080 + str r1, [r0, #0x34] +.endm + +.macro imx7_ddr_setting + imx7d_12x12_lpddr3_val_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7d_19x19_ddr3_val/Kconfig b/board/freescale/mx7d_19x19_ddr3_val/Kconfig new file mode 100644 index 00000000000..52c8c49001a --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_val/Kconfig @@ -0,0 +1,14 @@ +if TARGET_MX7D_19X19_DDR3_VAL + +config SYS_BOARD + default "mx7d_19x19_ddr3_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7d_19x19_ddr3_val" + +config SYS_TEXT_BASE + default 0x87800000 +endif diff --git a/board/freescale/mx7d_19x19_ddr3_val/Makefile b/board/freescale/mx7d_19x19_ddr3_val/Makefile new file mode 100644 index 00000000000..5e48257e15e --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7d_19x19_ddr3_val.o diff --git a/board/freescale/mx7d_19x19_ddr3_val/imximage.cfg b/board/freescale/mx7d_19x19_ddr3_val/imximage.cfg new file mode 100644 index 00000000000..81a974901b2 --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_val/imximage.cfg @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_ddr3_val/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000b24 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7d_19x19_ddr3_val/imximage_TO_1_1.cfg b/board/freescale/mx7d_19x19_ddr3_val/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..85d04e74043 --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_val/imximage_TO_1_1.cfg @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_ddr3_val/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30360070 0x00703021 +DATA 4 0x30360090 0x0 +DATA 4 0x30360070 0x00603021 +CHECK_BITS_SET 4 0x30360070 0x80000000 +DATA 4 0x30389880 0x1 + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000dee +DATA 4 0x3079007c 0x18181818 +DATA 4 0x30790080 0x18181818 +DATA 4 0x30790084 0x40401818 +DATA 4 0x30790088 0x00000040 +DATA 4 0x3079006c 0x40404040 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7d_19x19_ddr3_val/mx7d_19x19_ddr3_val.c b/board/freescale/mx7d_19x19_ddr3_val/mx7d_19x19_ddr3_val.c new file mode 100644 index 00000000000..dc23f5a691f --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_val/mx7d_19x19_ddr3_val.c @@ -0,0 +1,611 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, + .gp = IMX_GPIO_NR(4, 8), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, + .gp = IMX_GPIO_NR(4, 9), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC, + .gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC, + .gp = IMX_GPIO_NR(4, 10), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC, + .gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC, + .gp = IMX_GPIO_NR(4, 11), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_emmc_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_ECSPI2_SCLK__SD1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_ECSPI2_MOSI__SD1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_ECSPI2_MISO__SD1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_ECSPI2_SS0__SD1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX7D_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_GPIO1_IO12__SD2_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD2_CD_B__GPIO5_IO9 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_GPIO1_IO13__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), + + MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwm_pads[] = { + /* Use GPIO for Brightness adjustment, duty cycle = period */ + MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void do_enable_parallel_lcd(struct display_info_t const *dev) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); + + /* Power up the LCD */ + gpio_request(IMX_GPIO_NR(3, 4), "lcd_pwr"); + gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + + /* Set Brightness to high */ + gpio_request(IMX_GPIO_NR(1, 1), "lcd_backlight"); + gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); +} + +struct display_info_t const displays[] = {{ + .bus = ELCDIF1_IPS_BASE_ADDR, + .addr = 0, + .pixfmt = 24, + .detect = NULL, + .enable = do_enable_parallel_lcd, + .mode = { + .name = "MCIMX28LCD", + .xres = 800, + .yres = 480, + .pixclock = 29850, + .left_margin = 89, + .right_margin = 164, + .upper_margin = 23, + .lower_margin = 10, + .hsync_len = 10, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +} } }; +size_t display_count = ARRAY_SIZE(displays); +#endif + +static iomux_v3_cfg_t const per_rst_pads[] = { + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec2_pads[] = { + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec2(void) +{ + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI + +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 9) +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14) + +#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) +#define USDHC2_PWR_GPIO IMX_GPIO_NR(5, 11) +#define USDHC3_PWR_GPIO IMX_GPIO_NR(6, 11) + + +static struct fsl_esdhc_cfg usdhc_cfg[3] = { + {USDHC1_BASE_ADDR}, + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; /* Assume uSDHC1 emmc is always present */ + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC3_BASE_ADDR: + ret = !gpio_get_value(USDHC3_CD_GPIO); + break; + } + + return ret; +} +int board_mmc_init(struct bd_info *bis) +{ + int i; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 (eMMC) + * mmc1 USDHC2 + * mmc2 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_emmc_pads, ARRAY_SIZE(usdhc1_emmc_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_PWR_GPIO, "usdhc2_pwr"); + gpio_request(USDHC2_CD_GPIO, "usdhc2_cd"); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_request(USDHC3_PWR_GPIO, "usdhc3_pwr"); + gpio_request(USDHC3_CD_GPIO, "usdhc3_cd"); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return 0; + } + + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i])) + printf("Warning: failed to initialize mmc dev %d\n", i); + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec2(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS0 */ + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_request(IMX_GPIO_NR(4, 19), "ecspi1_cs"); + gpio_direction_output(IMX_GPIO_NR(4, 19), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 19)) : -1; +} +#endif +#endif + +#ifdef CONFIG_USB_EHCI_MX7 +#ifndef CONFIG_DM_USB +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads)); + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads)); +} +#endif +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_USB_EHCI_MX7 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Reset peripherals */ + imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 3), "per_rst"); + gpio_direction_output(IMX_GPIO_NR(1, 3), 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 3), 1); + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)}, + {"sd2", MAKE_CFGVAL(0x10, 0x16, 0x00, 0x00)}, + {"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id, reg; + + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* set SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ + puts("Board: MX7D 19x19 DDR3 VAL\n"); + + return 0; +} diff --git a/board/freescale/mx7d_19x19_ddr3_val/plugin.S b/board/freescale/mx7d_19x19_ddr3_val/plugin.S new file mode 100644 index 00000000000..26914e41eba --- /dev/null +++ b/board/freescale/mx7d_19x19_ddr3_val/plugin.S @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_19x19_ddr3_val_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_19x19_ddr3_val_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7d_19x19_lpddr3_val/Kconfig b/board/freescale/mx7d_19x19_lpddr3_val/Kconfig new file mode 100644 index 00000000000..a5db2d220da --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_val/Kconfig @@ -0,0 +1,20 @@ +if TARGET_MX7D_19X19_LPDDR3_VAL || TARGET_MX7D_19X19_LPDDR2_VAL + +config SYS_BOARD + default "mx7d_19x19_lpddr3_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7d_19x19_lpddr3_val" + +config SYS_TEXT_BASE + default 0x87800000 + +config NOR + bool "Support for NOR flash" + help + The i.MX SoC supports having a NOR flash connected to the WEIM. + Need to set this for NOR_BOOT. +endif diff --git a/board/freescale/mx7d_19x19_lpddr3_val/Makefile b/board/freescale/mx7d_19x19_lpddr3_val/Makefile new file mode 100644 index 00000000000..48148c17717 --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7d_19x19_lpddr3_val.o diff --git a/board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg b/board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg new file mode 100644 index 00000000000..b014f118024 --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_lpddr3_val/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00090909 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x08080808 +DATA 4 0x307a0218 0x0f0f0808 + +DATA 4 0x307a0240 0x06000600 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x00000b24 + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x0e487304 +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e4c7306 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_19x19_lpddr3_val/imximage_TO_1_1.cfg b/board/freescale/mx7d_19x19_lpddr3_val/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..f29b9eac354 --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_val/imximage_TO_1_1.cfg @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_lpddr3_val/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03040008 +DATA 4 0x307a0064 0x00200038 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00dc 0x00c3000a +DATA 4 0x307a00e0 0x00010000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x0a0e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x03060708 +DATA 4 0x307a010c 0x00a0500c +DATA 4 0x307a0110 0x05020307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098205 +DATA 4 0x307a0194 0x00060303 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 + +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00090909 +DATA 4 0x307a0210 0x00000f00 +DATA 4 0x307a0214 0x08080808 +DATA 4 0x307a0218 0x0f0f0808 + +DATA 4 0x307a0240 0x06000601 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421e40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x0007080c +DATA 4 0x3079007c 0x1c1c1c1c +DATA 4 0x30790080 0x1c1c1c1c +DATA 4 0x30790084 0x30301c1c +DATA 4 0x30790088 0x00000030 +DATA 4 0x3079006c 0x30303030 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009c 0x0db60d6e + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x30790018 0x0000000f +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487304 +DATA 4 0x307900c0 0x1e487306 +DATA 4 0x307900c0 0x1e4c7304 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x1e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2.cfg b/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2.cfg new file mode 100644 index 00000000000..c20fbf792ee --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2.cfg @@ -0,0 +1,119 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_lpddr3_val/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03020004 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00200023 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00d8 0x00001105 +DATA 4 0x307a00dc 0x00c20006 +DATA 4 0x307a00e0 0x00020000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x080e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x02040706 +DATA 4 0x307a010c 0x00504000 +DATA 4 0x307a0110 0x05010307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098203 +DATA 4 0x307a0194 0x00060303 + +DATA 4 0x307a0200 0x00000015 +DATA 4 0x307a0204 0x00161616 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x04040404 +DATA 4 0x307a0218 0x0f0f0404 + +DATA 4 0x307a0240 0x06000600 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421640 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x00050408 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009C 0x00000d6e +DATA 4 0x30790018 0x0000000f + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x307900c0 0x0e487304 +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e4c7306 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x000001f8 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2_TO_1_1.cfg b/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2_TO_1_1.cfg new file mode 100644 index 00000000000..f5888499cf3 --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2_TO_1_1.cfg @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +#ifdef CONFIG_SYS_BOOT_QSPI +BOOT_FROM qspi +#elif defined(CONFIG_SYS_BOOT_EIMNOR) +BOOT_FROM nor +#else +BOOT_FROM sd +#endif + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7d_19x19_lpddr3_val/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +DATA 4 0x30340004 0x4F400005 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x03020004 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00200023 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00350001 +DATA 4 0x307a00d8 0x00001105 +DATA 4 0x307a00dc 0x00c20006 +DATA 4 0x307a00e0 0x00020000 +DATA 4 0x307a00e4 0x00110006 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x080e110b +DATA 4 0x307a0104 0x00020211 +DATA 4 0x307a0108 0x02040706 +DATA 4 0x307a010c 0x00504000 +DATA 4 0x307a0110 0x05010307 +DATA 4 0x307a0114 0x02020404 +DATA 4 0x307a0118 0x02020003 +DATA 4 0x307a011c 0x00000202 +DATA 4 0x307a0120 0x00000202 + +DATA 4 0x307a0180 0x00600018 +DATA 4 0x307a0184 0x00e00100 +DATA 4 0x307a0190 0x02098203 +DATA 4 0x307a0194 0x00060303 + +DATA 4 0x307a0200 0x00000015 +DATA 4 0x307a0204 0x00161616 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x04040404 +DATA 4 0x307a0218 0x0f0f0404 + +DATA 4 0x307a0240 0x06000600 +DATA 4 0x307a0244 0x00000000 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17421640 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790008 0x00010000 +DATA 4 0x30790010 0x00050408 +DATA 4 0x307900b0 0x1010007e + +DATA 4 0x3079001C 0x01010000 +DATA 4 0x3079009C 0x00000dee +DATA 4 0x3079007c 0x08080808 +DATA 4 0x30790080 0x08080808 +DATA 4 0x30790084 0x0a0a0808 +DATA 4 0x30790088 0x0000000a +DATA 4 0x3079006c 0x0a0a0a0a +DATA 4 0x30790018 0x0000000f + +DATA 4 0x30790030 0x06060606 +DATA 4 0x30790020 0x0a0a0a0a +DATA 4 0x30790050 0x01000008 +DATA 4 0x30790050 0x00000008 +DATA 4 0x307900c0 0x0e487304 +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e4c7306 +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e4c7304 +DATA 4 0x307900c0 0x0e487304 + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x000001f8 +DATA 4 0x30384130 0x00000002 + +CHECK_BITS_SET 4 0x307a0004 0x1 +#endif diff --git a/board/freescale/mx7d_19x19_lpddr3_val/mx7d_19x19_lpddr3_val.c b/board/freescale/mx7d_19x19_lpddr3_val/mx7d_19x19_lpddr3_val.c new file mode 100644 index 00000000000..a2d025c01e8 --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_val/mx7d_19x19_lpddr3_val.c @@ -0,0 +1,603 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/pfuze.h" +#ifdef CONFIG_SYS_I2C_MXC +#include +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_98OHM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define QSPI_PAD_CTRL \ + (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) + +#define WEIM_NOR_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_PUS_PU100KOHM) + + +#ifdef CONFIG_SYS_I2C +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, + .gp = IMX_GPIO_NR(4, 8), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, + .gp = IMX_GPIO_NR(4, 9), + }, +}; + +/* I2C2 */ +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX7D_PAD_I2C2_SCL__I2C2_SCL | PC, + .gpio_mode = MX7D_PAD_I2C2_SCL__GPIO4_IO10 | PC, + .gp = IMX_GPIO_NR(4, 10), + }, + .sda = { + .i2c_mode = MX7D_PAD_I2C2_SDA__I2C2_SDA | PC, + .gpio_mode = MX7D_PAD_I2C2_SDA__GPIO4_IO11 | PC, + .gp = IMX_GPIO_NR(4, 11), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_GPIO1_IO08__SD1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_MTD_NOR_FLASH +static iomux_v3_cfg_t const eimnor_pads[] = { + MX7D_PAD_LCD_DATA00__EIM_DATA0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA01__EIM_DATA1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA02__EIM_DATA2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA03__EIM_DATA3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA04__EIM_DATA4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA05__EIM_DATA5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA06__EIM_DATA6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA07__EIM_DATA7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA08__EIM_DATA8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA09__EIM_DATA9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA10__EIM_DATA10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA11__EIM_DATA11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA12__EIM_DATA12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA13__EIM_DATA13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA14__EIM_DATA14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA15__EIM_DATA15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX7D_PAD_EPDC_DATA00__EIM_AD0 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EIM_AD1 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EIM_AD2 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EIM_AD3 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EIM_AD4 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EIM_AD5 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EIM_AD6 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EIM_AD7 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EIM_AD8 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_PWR_COM__EIM_AD9 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA20__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA21__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_LCD_DATA22__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + + MX7D_PAD_EPDC_DATA08__EIM_OE | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA09__EIM_RW | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__EIM_CS0_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__EIM_LBA_B | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), + MX7D_PAD_EPDC_DATA13__EIM_WAIT | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL), +}; + +static void eimnor_cs_setup(void) +{ + writel(0x00000120, WEIM_IPS_BASE_ADDR + 0x090); + writel(0x00210081, WEIM_IPS_BASE_ADDR + 0x000); + writel(0x00000001, WEIM_IPS_BASE_ADDR + 0x004); + writel(0x0e020000, WEIM_IPS_BASE_ADDR + 0x008); + writel(0x00000000, WEIM_IPS_BASE_ADDR + 0x00c); + writel(0x0704a040, WEIM_IPS_BASE_ADDR + 0x010); +} + +static void setup_eimnor(void) +{ + imx_iomux_v3_setup_multiple_pads(eimnor_pads, + ARRAY_SIZE(eimnor_pads)); + + eimnor_cs_setup(); +} +#endif + +static iomux_v3_cfg_t const per_rst_pads[] = { + MX7D_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX7D_PAD_ENET1_COL__WDOG1_WDOG_ANY | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec2_pads[] = { + MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec2(void) +{ + imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +static iomux_v3_cfg_t const quadspi_pads[] = { + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__QSPI_A_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + + MX7D_PAD_EPDC_DATA08__QSPI_B_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA09__QSPI_B_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA10__QSPI_B_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA11__QSPI_B_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA12__QSPI_B_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA13__QSPI_B_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA14__QSPI_B_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + MX7D_PAD_EPDC_DATA15__QSPI_B_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), + +}; +#endif + +int board_qspi_init(void) +{ +#ifndef CONFIG_DM_SPI + /* Set the iomux */ + imx_iomux_v3_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif + + /* Set the clock */ + set_clk_qspi(); + + return 0; +} +#endif + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* + * NAND_USDHC_BUS_CLK is set in rom + */ + + set_clk_nand(); + + /* + * APBH clock root is set in init_esdhc, USDHC3_CLK. + * There is no clk gate for APBHDMA. + * No touch here. + */ +} +#endif + + +#ifdef CONFIG_FSL_ESDHC_IMX + +#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2) + + +static struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC1 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr"); + gpio_direction_input(USDHC1_CD_GPIO); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(struct bd_info *bis) +{ + int ret; + + setup_iomux_fec2(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return 0; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + int ret; + + /* Use 125M anatop REF_CLK for ENET2, clear gpr1[14], gpr1[18]*/ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0); + + ret = set_clk_enet(ENET_125MHZ); + if (ret) + return ret; + + return 0; +} + + +int board_phy_config(struct phy_device *phydev) +{ + /* Enable 1.8V(SEL_1P5_1P8_POS_REG) on + Phy control debug reg 0 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI +iomux_v3_cfg_t const ecspi1_pads[] = { + MX7D_PAD_UART3_RX_DATA__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_UART3_TX_DATA__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_UART3_RTS_B__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + + /* CS0 */ + MX7D_PAD_UART3_CTS_B__GPIO4_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, + ARRAY_SIZE(ecspi1_pads)); + gpio_direction_output(IMX_GPIO_NR(4, 7), 0); +} + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 7)) : -1; +} +#endif +#endif + +#ifdef CONFIG_USB_EHCI_MX7 +#ifndef CONFIG_DM_USB + +iomux_v3_cfg_t const usb_otg1_pads[] = { + MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const usb_otg2_pads[] = { + MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads, ARRAY_SIZE(usb_otg1_pads)); + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, ARRAY_SIZE(usb_otg2_pads)); +} +#endif +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_SYS_I2C + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_USB_EHCI_MX7 +#ifndef CONFIG_DM_USB + setup_usb(); +#endif +#endif + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* Reset peripherals */ + imx_iomux_v3_setup_multiple_pads(per_rst_pads, ARRAY_SIZE(per_rst_pads)); + + gpio_request(IMX_GPIO_NR(1, 3), "per rst"); + gpio_direction_output(IMX_GPIO_NR(1, 3) , 0); + udelay(500); + gpio_set_value(IMX_GPIO_NR(1, 3), 1); + +#ifdef CONFIG_MXC_SPI +#ifndef CONFIG_DM_SPI + setup_spinor(); +#endif +#endif + +#ifdef CONFIG_MTD_NOR_FLASH + setup_eimnor(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd1", MAKE_CFGVAL(0x10, 0x12, 0x00, 0x00)}, + {"qspi", MAKE_CFGVAL(0x00, 0x40, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +#ifdef CONFIG_DM_PMIC +int power_init_board(void) +{ + struct udevice *dev; + int ret, dev_id, rev_id, reg; + + ret = pmic_get("pfuze3000@8", &dev); + if (ret == -ENODEV) + return 0; + if (ret != 0) + return ret; + + dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID); + rev_id = pmic_reg_read(dev, PFUZE3000_REVID); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id); + + /* disable Low Power Mode during standby mode */ + reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL); + reg |= 0x1; + pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg); + + /* SW1A/1B mode set to APS/APS */ + reg = 0x8; + pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg); + pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg); + + /* SW1A/1B standby voltage set to 0.975V */ + reg = 0xb; + pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg); + pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg); + + /* set SW1B normal voltage to 0.975V */ + reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT); + reg &= ~0x1f; + reg |= PFUZE3000_SW1AB_SETP(9750); + pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg); + + return 0; +} +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + + return 0; +} + +u32 get_board_rev(void) +{ + return get_cpu_rev(); +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_VAL + puts("Board: MX7D 19x19 LPDDR2 VAL\n"); +#else + puts("Board: MX7D 19x19 LPDDR3 VAL\n"); +#endif + return 0; +} diff --git a/board/freescale/mx7d_19x19_lpddr3_val/plugin.S b/board/freescale/mx7d_19x19_lpddr3_val/plugin.S new file mode 100644 index 00000000000..29d76d5daf1 --- /dev/null +++ b/board/freescale/mx7d_19x19_lpddr3_val/plugin.S @@ -0,0 +1,378 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_lpddr3_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne TUNE_END + + /*TO 1.1*/ + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x7c] + ldr r1, =0x1c1c1c1c + str r1, [r0, #0x80] + ldr r1, =0x30301c1c + str r1, [r0, #0x84] + ldr r1, =0x00000030 + str r1, [r0, #0x88] + ldr r1, =0x30303030 + str r1, [r0, #0x6c] + +TUNE_END: +.endm + +.macro imx7d_ddrphy_lpddr2_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x08080808 + str r1, [r0, #0x7c] + ldr r1, =0x08080808 + str r1, [r0, #0x80] + ldr r1, =0x0a0a0808 + str r1, [r0, #0x84] + ldr r1, =0x0000000a + str r1, [r0, #0x88] + ldr r1, =0x0a0a0a0a + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000d6e + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_19x19_lpddr3_val_setting + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x03040008 + str r1, [r0] + ldr r1, =0x00200038 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00350001 + str r1, [r0, #0xd0] + ldr r1, =0x00c3000a + str r1, [r0, #0xdc] + ldr r1, =0x00010000 + str r1, [r0, #0xe0] + ldr r1, =0x00110006 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x0a0e110b + str r1, [r0, #0x100] + ldr r1, =0x00020211 + str r1, [r0, #0x104] + ldr r1, =0x03060708 + str r1, [r0, #0x108] + ldr r1, =0x00a0500c + str r1, [r0, #0x10c] + ldr r1, =0x05020307 + str r1, [r0, #0x110] + ldr r1, =0x02020404 + str r1, [r0, #0x114] + ldr r1, =0x02020003 + str r1, [r0, #0x118] + ldr r1, =0x00000202 + str r1, [r0, #0x11c] + ldr r1, =0x00000202 + str r1, [r0, #0x120] + ldr r1, =0x00600018 + str r1, [r0, #0x180] + ldr r1, =0x00e00100 + str r1, [r0, #0x184] + ldr r1, =0x02098205 + str r1, [r0, #0x190] + ldr r1, =0x00060303 + str r1, [r0, #0x194] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00090909 + str r1, [r0, #0x204] + ldr r1, =0x00000f00 + str r1, [r0, #0x210] + ldr r1, =0x08080808 + str r1, [r0, #0x214] + ldr r1, =0x0f0f0808 + str r1, [r0, #0x218] + + ldr r1, =0x06000600 + str r1, [r0, #0x240] + mov r1, #0x0 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17421e40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00010000 + str r1, [r0, #0x8] + ldr r1, =0x0007080c + str r1, [r0, #0x10] + imx7d_ddrphy_lpddr3_latency_setting + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + ldr r1, =0x01010000 + str r1, [r0, #0x1c] + + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne 1f + + ldr r1, =0x0db60d6e + str r1, [r0, #0x9c] + b 2f +1: + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] +2: + ldr r1, =0x06060606 + str r1, [r0, #0x30] + ldr r1, =0x0a0a0a0a + str r1, [r0, #0x20] + ldr r1, =0x01000008 + str r1, [r0, #0x50] + ldr r1, =0x00000008 + str r1, [r0, #0x50] + + ldr r1, =0x0000000f + str r1, [r0, #0x18] + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7d_19x19_lpddr2_val_setting + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x03020004 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00200023 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00350001 + str r1, [r0, #0xd0] + ldr r1, =0x00001105 + str r1, [r0, #0xd8] + ldr r1, =0x00c20006 + str r1, [r0, #0xdc] + ldr r1, =0x00020000 + str r1, [r0, #0xe0] + ldr r1, =0x00110006 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x080e110b + str r1, [r0, #0x100] + ldr r1, =0x00020211 + str r1, [r0, #0x104] + ldr r1, =0x02040706 + str r1, [r0, #0x108] + ldr r1, =0x00504000 + str r1, [r0, #0x10c] + ldr r1, =0x05010307 + str r1, [r0, #0x110] + ldr r1, =0x02020404 + str r1, [r0, #0x114] + ldr r1, =0x02020003 + str r1, [r0, #0x118] + ldr r1, =0x00000202 + str r1, [r0, #0x11c] + ldr r1, =0x00000202 + str r1, [r0, #0x120] + ldr r1, =0x00600018 + str r1, [r0, #0x180] + ldr r1, =0x00e00100 + str r1, [r0, #0x184] + ldr r1, =0x02098203 + str r1, [r0, #0x190] + ldr r1, =0x00060303 + str r1, [r0, #0x194] + + ldr r1, =0x00000015 + str r1, [r0, #0x200] + ldr r1, =0x00161616 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x04040404 + str r1, [r0, #0x214] + ldr r1, =0x0f0f0404 + str r1, [r0, #0x218] + + ldr r1, =0x06000600 + str r1, [r0, #0x240] + mov r1, #0x0 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17421640 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00010000 + str r1, [r0, #0x8] + ldr r1, =0x00050408 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + ldr r1, =0x01010000 + str r1, [r0, #0x1c] + imx7d_ddrphy_lpddr2_latency_setting + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r1, =0x06060606 + str r1, [r0, #0x30] + ldr r1, =0x0a0a0a0a + str r1, [r0, #0x20] + ldr r1, =0x01000008 + str r1, [r0, #0x50] + ldr r1, =0x00000008 + str r1, [r0, #0x50] + + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7304 + str r1, [r0, #0xc0] + ldr r1, =0x0e4c7306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e4c7304 + str r1, [r0, #0xc0] + ldr r1, =0x0e487304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x1f8 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting +#if defined (TARGET_MX7D_19X19_LPDDR2_VAL) + imx7d_19x19_lpddr2_val_setting +#else + imx7d_19x19_lpddr3_val_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig index c6a969ca67f..beef4c06d1a 100644 --- a/board/freescale/mx7dsabresd/Kconfig +++ b/board/freescale/mx7dsabresd/Kconfig @@ -9,4 +9,6 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "mx7dsabresd" +config SYS_TEXT_BASE + default 0x87800000 endif diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg index 05446ac833d..c587e10c012 100644 --- a/board/freescale/mx7dsabresd/imximage.cfg +++ b/board/freescale/mx7dsabresd/imximage.cfg @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure * and create imximage boot image @@ -21,6 +22,10 @@ IMAGE_VERSION 2 BOOT_FROM sd +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000 +#else /* * Secure boot support */ @@ -40,7 +45,14 @@ CSF CONFIG_CSF_SIZE * value value to be stored in the register */ +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x30340024 0x1 +CHECK_BITS_SET 4 0x30340024 0x1 +#endif DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 DATA 4 0x30391000 0x00000002 DATA 4 0x307a0000 0x01040001 @@ -67,9 +79,10 @@ DATA 4 0x307a0184 0x02000100 DATA 4 0x307a0190 0x02098204 DATA 4 0x307a0194 0x00030303 DATA 4 0x307a0200 0x00000016 -DATA 4 0x307a0204 0x00171717 -DATA 4 0x307a0214 0x04040404 -DATA 4 0x307a0218 0x0f040404 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 DATA 4 0x307a0240 0x06000604 DATA 4 0x307a0244 0x00000001 DATA 4 0x30391000 0x00000000 @@ -77,7 +90,7 @@ DATA 4 0x30790000 0x17420f40 DATA 4 0x30790004 0x10210100 DATA 4 0x30790010 0x00060807 DATA 4 0x307900b0 0x1010007e -DATA 4 0x3079009c 0x00000d6e +DATA 4 0x3079009c 0x00000b24 DATA 4 0x30790020 0x08080808 DATA 4 0x30790030 0x08080808 DATA 4 0x30790050 0x01000010 @@ -89,7 +102,6 @@ DATA 4 0x307900c0 0x0e447306 CHECK_BITS_SET 4 0x307900c4 0x1 -DATA 4 0x307900c0 0x0e447304 DATA 4 0x307900c0 0x0e407304 DATA 4 0x30384130 0x00000000 @@ -98,3 +110,5 @@ DATA 4 0x30384130 0x00000002 DATA 4 0x30790018 0x0000000f CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg new file mode 100644 index 00000000000..aa0018658c3 --- /dev/null +++ b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Refer doc/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +#ifdef CONFIG_IMX_OPTEE +DATA 4 0x30340024 0x1 +CHECK_BITS_SET 4 0x30340024 0x1 +#endif +DATA 4 0x30360070 0x00703021 +DATA 4 0x30360090 0x0 +DATA 4 0x30360070 0x00603021 +CHECK_BITS_SET 4 0x30360070 0x80000000 +DATA 4 0x30389880 0x1 + +DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 + +DATA 4 0x30391000 0x00000002 +DATA 4 0x307a0000 0x01040001 +DATA 4 0x307a01a0 0x80400003 +DATA 4 0x307a01a4 0x00100020 +DATA 4 0x307a01a8 0x80100004 +DATA 4 0x307a0064 0x00400046 +DATA 4 0x307a0490 0x00000001 +DATA 4 0x307a00d0 0x00020083 +DATA 4 0x307a00d4 0x00690000 +DATA 4 0x307a00dc 0x09300004 +DATA 4 0x307a00e0 0x04080000 +DATA 4 0x307a00e4 0x00100004 +DATA 4 0x307a00f4 0x0000033f +DATA 4 0x307a0100 0x09081109 +DATA 4 0x307a0104 0x0007020d +DATA 4 0x307a0108 0x03040407 +DATA 4 0x307a010c 0x00002006 +DATA 4 0x307a0110 0x04020205 +DATA 4 0x307a0114 0x03030202 +DATA 4 0x307a0120 0x00000803 +DATA 4 0x307a0180 0x00800020 +DATA 4 0x307a0184 0x02000100 +DATA 4 0x307a0190 0x02098204 +DATA 4 0x307a0194 0x00030303 +DATA 4 0x307a0200 0x00000016 +DATA 4 0x307a0204 0x00080808 +DATA 4 0x307a0210 0x00000f0f +DATA 4 0x307a0214 0x07070707 +DATA 4 0x307a0218 0x0f070707 +DATA 4 0x307a0240 0x06000604 +DATA 4 0x307a0244 0x00000001 +DATA 4 0x30391000 0x00000000 +DATA 4 0x30790000 0x17420f40 +DATA 4 0x30790004 0x10210100 +DATA 4 0x30790010 0x00060807 +DATA 4 0x307900b0 0x1010007e +DATA 4 0x3079009c 0x00000dee +DATA 4 0x3079007c 0x18181818 +DATA 4 0x30790080 0x18181818 +DATA 4 0x30790084 0x40401818 +DATA 4 0x30790088 0x00000040 +DATA 4 0x3079006c 0x40404040 +DATA 4 0x30790020 0x08080808 +DATA 4 0x30790030 0x08080808 +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 + +CHECK_BITS_SET 4 0x307900c4 0x1 + +DATA 4 0x307900c0 0x0e407304 + + +DATA 4 0x30384130 0x00000000 +DATA 4 0x30340020 0x00000178 +DATA 4 0x30384130 0x00000002 +DATA 4 0x30790018 0x0000000f + +CHECK_BITS_SET 4 0x307a0004 0x1 + +#endif diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index 2777ae13bce..c418b13a366 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP */ #include @@ -12,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +27,11 @@ #include #include #include +#if defined(CONFIG_MXC_EPDC) +#include +#include +#endif +#include DECLARE_GLOBAL_DATA_PTR; @@ -41,6 +48,8 @@ DECLARE_GLOBAL_DATA_PTR; #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) +#define EPDC_PAD_CTRL 0x0 + #ifdef CONFIG_MXC_SPI static iomux_v3_cfg_t const ecspi3_pads[] = { MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), @@ -76,6 +85,55 @@ static iomux_v3_cfg_t const uart1_pads[] = { MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), }; +#define BOARD_REV_C 0x300 +#define BOARD_REV_B 0x200 +#define BOARD_REV_A 0x100 + +static int mx7sabre_rev(void) +{ + /* + * Get Board ID information from OCOTP_GP1[15:8] + * i.MX7D SDB RevA: 0x41 + * i.MX7D SDB RevB: 0x42 + */ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[14]; + int reg = readl(&bank->fuse_regs[0]); + int ret; + + if (reg != 0) { + switch (reg >> 8 & 0x0F) { + case 0x3: + ret = BOARD_REV_C; + break; + case 0x02: + ret = BOARD_REV_B; + break; + case 0x01: + default: + ret = BOARD_REV_A; + break; + } + } else { + /* If the gp1 fuse is not burn, we have to use TO rev for the board rev */ + if (is_soc_rev(CHIP_REV_1_0)) + ret = BOARD_REV_A; + else if (is_soc_rev(CHIP_REV_1_1)) + ret = BOARD_REV_B; + else + ret = BOARD_REV_C; + } + + return ret; +} + +u32 get_board_rev(void) +{ + int rev = mx7sabre_rev(); + + return (get_cpu_rev() & ~(0xF << 8)) | rev; +} + #ifdef CONFIG_NAND_MXS static iomux_v3_cfg_t const gpmi_pads[] = { MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), @@ -108,37 +166,8 @@ static void setup_gpmi_nand(void) } #endif -#ifdef CONFIG_VIDEO_MXS +#ifdef CONFIG_DM_VIDEO static iomux_v3_cfg_t const lcd_pads[] = { - MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL), - MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL), }; @@ -149,22 +178,50 @@ static iomux_v3_cfg_t const pwm_pads[] = { static int setup_lcd(void) { + int ret; + struct gpio_desc desc; + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads)); /* Reset LCD */ - gpio_request(IMX_GPIO_NR(3, 4), "lcd reset"); - gpio_direction_output(IMX_GPIO_NR(3, 4) , 0); + ret = dm_gpio_lookup_name("GPIO3_4", &desc); + if (ret) { + printf("%s lookup GPIO3_4 failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + ret = dm_gpio_request(&desc, "lcd reset"); + if (ret) { + printf("%s request lcd reset failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT); + dm_gpio_set_value(&desc, 0); udelay(500); - gpio_direction_output(IMX_GPIO_NR(3, 4) , 1); + dm_gpio_set_value(&desc, 1); /* Set Brightness to high */ - gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight"); - gpio_direction_output(IMX_GPIO_NR(1, 1) , 1); + ret = dm_gpio_lookup_name("GPIO1_1", &desc); + if (ret) { + printf("%s lookup GPIO1_1 failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + ret = dm_gpio_request(&desc, "lcd backlight"); + if (ret) { + printf("%s request lcd backlight failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); return 0; } +#else +static inline int setup_lcd(void) { return 0; } #endif static void setup_iomux_uart(void) @@ -172,21 +229,13 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } -int board_mmc_get_env_dev(int devno) -{ - if (devno == 2) - devno--; - - return devno; -} - -int mmc_map_to_kernel_blk(int dev_no) +#ifdef CONFIG_IMX_BOOTAUX +ulong board_get_usable_ram_top(ulong total_size) { - if (dev_no == 1) - dev_no++; - - return dev_no; + /* Reserve top 1M memory used by M core vring/buffer */ + return gd->ram_top - SZ_1M; } +#endif #ifdef CONFIG_FEC_MXC static int setup_fec(void) @@ -199,6 +248,10 @@ static int setup_fec(void) (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK | IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0); + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + (IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK | + IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK), 0); + return set_clk_enet(ENET_125MHZ); } @@ -226,6 +279,263 @@ int board_qspi_init(void) } #endif +#ifdef CONFIG_MXC_EPDC +iomux_v3_cfg_t const epdc_en_pads[] = { + MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_enable_pads[] = { + MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL), + MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const epdc_disable_pads[] = { + MX7D_PAD_EPDC_DATA00__GPIO2_IO0, + MX7D_PAD_EPDC_DATA01__GPIO2_IO1, + MX7D_PAD_EPDC_DATA02__GPIO2_IO2, + MX7D_PAD_EPDC_DATA03__GPIO2_IO3, + MX7D_PAD_EPDC_DATA04__GPIO2_IO4, + MX7D_PAD_EPDC_DATA05__GPIO2_IO5, + MX7D_PAD_EPDC_DATA06__GPIO2_IO6, + MX7D_PAD_EPDC_DATA07__GPIO2_IO7, + MX7D_PAD_EPDC_SDCLK__GPIO2_IO16, + MX7D_PAD_EPDC_SDLE__GPIO2_IO17, + MX7D_PAD_EPDC_SDOE__GPIO2_IO18, + MX7D_PAD_EPDC_SDSHR__GPIO2_IO19, + MX7D_PAD_EPDC_SDCE0__GPIO2_IO20, + MX7D_PAD_EPDC_SDCE1__GPIO2_IO21, + MX7D_PAD_EPDC_GDCLK__GPIO2_IO24, + MX7D_PAD_EPDC_GDOE__GPIO2_IO25, + MX7D_PAD_EPDC_GDRL__GPIO2_IO26, + MX7D_PAD_EPDC_GDSP__GPIO2_IO27, + MX7D_PAD_EPDC_BDR0__GPIO2_IO28, + MX7D_PAD_EPDC_BDR1__GPIO2_IO29, +}; + +vidinfo_t panel_info = { + .vl_refresh = 85, + .vl_col = 1024, + .vl_row = 758, + .vl_pixclock = 40000000, + .vl_left_margin = 12, + .vl_right_margin = 76, + .vl_upper_margin = 4, + .vl_lower_margin = 5, + .vl_hsync = 12, + .vl_vsync = 2, + .vl_sync = 0, + .vl_mode = 0, + .vl_flag = 0, + .vl_bpix = 3, + .cmap = 0, +}; + +struct epdc_timing_params panel_timings = { + .vscan_holdoff = 4, + .sdoed_width = 10, + .sdoed_delay = 20, + .sdoez_width = 10, + .sdoez_delay = 20, + .gdclk_hp_offs = 524, + .gdsp_offs = 327, + .gdoe_offs = 0, + .gdclk_offs = 19, + .num_ce = 1, +}; + +struct gpio_desc epd_pwrstat_desc; +struct gpio_desc epd_vcom_desc; +struct gpio_desc epd_wakeup_desc; +struct gpio_desc epd_pwr_ctl0_desc; + +static void setup_epdc_power(void) +{ + int ret; + + /* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; + + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0); + + /* Setup epdc voltage */ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + ret = dm_gpio_lookup_name("GPIO2_31", &epd_pwrstat_desc); + if (ret) { + printf("%s lookup GPIO2_31 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_pwrstat_desc, "epdc_pwrstat"); + if (ret) { + printf("%s request epdc_pwrstat failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_pwrstat_desc, GPIOD_IS_IN); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + /* Set as output */ + ret = dm_gpio_lookup_name("GPIO4_14", &epd_vcom_desc); + if (ret) { + printf("%s lookup GPIO4_14 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_vcom_desc, "epdc_vcom"); + if (ret) { + printf("%s request epdc_vcom failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_vcom_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */ + /* Set as output */ + ret = dm_gpio_lookup_name("GPIO2_23", &epd_wakeup_desc); + if (ret) { + printf("%s lookup GPIO2_23 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_wakeup_desc, "epdc_pmic"); + if (ret) { + printf("%s request epdc_pmic failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_wakeup_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */ + /* Set as output */ + ret = dm_gpio_lookup_name("GPIO2_30", &epd_pwr_ctl0_desc); + if (ret) { + printf("%s lookup GPIO2_30 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&epd_pwr_ctl0_desc, "epdc_pwr_ctl0"); + if (ret) { + printf("%s request epdc_pwr_ctl0 failed ret = %d\n", __func__, ret); + return; + } + + dm_gpio_set_dir_flags(&epd_pwr_ctl0_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +static void epdc_enable_pins(void) +{ + /* epdc iomux settings */ + imx_iomux_v3_setup_multiple_pads(epdc_enable_pads, + ARRAY_SIZE(epdc_enable_pads)); +} + +static void epdc_disable_pins(void) +{ + /* Configure MUX settings for EPDC pins to GPIO and drive to 0 */ + imx_iomux_v3_setup_multiple_pads(epdc_disable_pads, + ARRAY_SIZE(epdc_disable_pads)); +} + +static void setup_epdc(void) +{ + /*** epdc Maxim PMIC settings ***/ + + /* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_VCOM0 - GPIO4[14] for VCOM control */ + imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */ + imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 | + MUX_PAD_CTRL(EPDC_PAD_CTRL)); + + /* Set pixel clock rates for EPDC in clock.c */ + + panel_info.epdc_data.wv_modes.mode_init = 0; + panel_info.epdc_data.wv_modes.mode_du = 1; + panel_info.epdc_data.wv_modes.mode_gc4 = 3; + panel_info.epdc_data.wv_modes.mode_gc8 = 2; + panel_info.epdc_data.wv_modes.mode_gc16 = 2; + panel_info.epdc_data.wv_modes.mode_gc32 = 2; + + panel_info.epdc_data.epdc_timings = panel_timings; + + setup_epdc_power(); +} + +void epdc_power_on(void) +{ + unsigned int reg; + struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR; + + /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */ + dm_gpio_set_value(&epd_pwr_ctl0_desc, 1); + udelay(1000); + + /* Enable epdc signal pin */ + epdc_enable_pins(); + + /* Set PMIC Wakeup to high - enable Display power */ + dm_gpio_set_value(&epd_wakeup_desc, 1); + + /* Wait for PWRGOOD == 1 */ + while (1) { + reg = readl(&gpio_regs->gpio_psr); + if (!(reg & (1 << 31))) + break; + + udelay(100); + } + + /* Enable VCOM */ + dm_gpio_set_value(&epd_vcom_desc, 1); + + udelay(500); +} + +void epdc_power_off(void) +{ + /* Set PMIC Wakeup to low - disable Display power */ + dm_gpio_set_value(&epd_wakeup_desc, 0); + + /* Disable VCOM */ + dm_gpio_set_value(&epd_vcom_desc, 0); + + epdc_disable_pins(); + + /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */ + dm_gpio_set_value(&epd_pwr_ctl0_desc, 0); +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -246,14 +556,39 @@ int board_init(void) setup_gpmi_nand(); #endif -#ifdef CONFIG_VIDEO_MXS - setup_lcd(); -#endif - #ifdef CONFIG_FSL_QSPI board_qspi_init(); #endif +#ifdef CONFIG_MXC_EPDC + if (mx7sabre_rev() >= BOARD_REV_B) { + int ret; + struct gpio_desc desc; + /* + * From RevB, GPIO1_IO04 is used for ENET2 EN, + * so set its output to high to isolate the + * ENET2 signals for EPDC + */ + imx_iomux_v3_setup_multiple_pads(epdc_en_pads, + ARRAY_SIZE(epdc_en_pads)); + + ret = dm_gpio_lookup_name("GPIO1_4", &desc); + if (ret) { + printf("%s lookup GPIO1_4 failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + ret = dm_gpio_request(&desc, "epdc_en"); + if (ret) { + printf("%s request epdc_en failed ret = %d\n", __func__, ret); + return -ENODEV; + } + + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + } + setup_epdc(); +#endif + #ifdef CONFIG_MXC_SPI setup_spi(); #endif @@ -261,11 +596,13 @@ int board_init(void) return 0; } + #ifdef CONFIG_DM_PMIC int power_init_board(void) { struct udevice *dev; int ret, dev_id, rev_id; + u32 sw3mode; ret = pmic_get("pfuze3000@8", &dev); if (ret == -ENODEV) @@ -285,6 +622,12 @@ int power_init_board(void) */ pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA); + /* change sw3 mode to avoid DDR power off */ + sw3mode = pmic_reg_read(dev, PFUZE3000_SW3MODE); + ret = pmic_reg_write(dev, PFUZE3000_SW3MODE, sw3mode | 0x20); + if (ret < 0) + printf("PMIC: PFUZE3000 change sw3 mode failed\n"); + return 0; } #endif @@ -293,29 +636,49 @@ int board_late_init(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + setup_lcd(); + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); set_wdog_reset(wdog); - /* - * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), - * since we use PMIC_PWRON to reset the board. - */ - clrsetbits_le16(&wdog->wcr, 0, 0x10); - return 0; } int checkboard(void) { + int rev = mx7sabre_rev(); char *mode; + char *revname; if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) mode = "secure"; else mode = "non-secure"; - printf("Board: i.MX7D SABRESD in %s mode\n", mode); + switch (rev) { + case BOARD_REV_C: + revname = "C"; + break; + case BOARD_REV_B: + revname = "B"; + break; + case BOARD_REV_A: + default: + revname = "A"; + break; + } + + printf("Board: i.MX7D SABRESD Rev%s in %s mode\n", revname, mode); return 0; } diff --git a/board/freescale/mx7dsabresd/plugin.S b/board/freescale/mx7dsabresd/plugin.S new file mode 100644 index 00000000000..1f64e468350 --- /dev/null +++ b/board/freescale/mx7dsabresd/plugin.S @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +/* DDR script */ +.macro imx7d_ddrphy_latency_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne NO_DELAY + + /*TO 1.1*/ + ldr r1, =0x00000dee + str r1, [r0, #0x9c] + ldr r1, =0x18181818 + str r1, [r0, #0x7c] + ldr r1, =0x18181818 + str r1, [r0, #0x80] + ldr r1, =0x40401818 + str r1, [r0, #0x84] + ldr r1, =0x00000040 + str r1, [r0, #0x88] + ldr r1, =0x40404040 + str r1, [r0, #0x6c] + b TUNE_END + +NO_DELAY: + /*TO 1.0*/ + ldr r1, =0x00000b24 + str r1, [r0, #0x9c] + +TUNE_END: +.endm + +.macro imx7d_ddr_freq_setting + ldr r2, =ANATOP_BASE_ADDR + ldr r3, [r2, #0x800] + and r3, r3, #0xFF + cmp r3, #0x11 + bne FREQ_DEFAULT_533 + + /* Change to 400Mhz for TO1.1 */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =0x70 + ldr r2, =0x00703021 + str r2, [r0, r1] + ldr r1, =0x90 + ldr r2, =0x0 + str r2, [r0, r1] + ldr r1, =0x70 + ldr r2, =0x00603021 + str r2, [r0, r1] + + ldr r3, =0x80000000 +wait_lock: + ldr r2, [r0, r1] + and r2, r3 + cmp r2, r3 + bne wait_lock + + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x9880 + ldr r2, =0x1 + str r2, [r0, r1] + +FREQ_DEFAULT_533: +.endm + +.macro imx7d_sabresd_ddr_setting + imx7d_ddr_freq_setting + + /* Configure ocram_epdc */ + ldr r0, =IOMUXC_GPR_BASE_ADDR + ldr r1, =0x4f400005 + str r1, [r0, #0x4] + + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + + ldr r0, =SRC_BASE_ADDR + ldr r1, =0x2 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRC_IPS_BASE_ADDR + ldr r1, =0x01040001 + str r1, [r0] + ldr r1, =0x80400003 + str r1, [r0, #0x1a0] + ldr r1, =0x00100020 + str r1, [r0, #0x1a4] + ldr r1, =0x80100004 + str r1, [r0, #0x1a8] + ldr r1, =0x00400046 + str r1, [r0, #0x64] + ldr r1, =0x1 + str r1, [r0, #0x490] + ldr r1, =0x00020001 + str r1, [r0, #0xd0] + ldr r1, =0x00690000 + str r1, [r0, #0xd4] + ldr r1, =0x09300004 + str r1, [r0, #0xdc] + ldr r1, =0x04080000 + str r1, [r0, #0xe0] + ldr r1, =0x00100004 + str r1, [r0, #0xe4] + ldr r1, =0x33f + str r1, [r0, #0xf4] + ldr r1, =0x09081109 + str r1, [r0, #0x100] + ldr r1, =0x0007020d + str r1, [r0, #0x104] + ldr r1, =0x03040407 + str r1, [r0, #0x108] + ldr r1, =0x00002006 + str r1, [r0, #0x10c] + ldr r1, =0x04020205 + str r1, [r0, #0x110] + ldr r1, =0x03030202 + str r1, [r0, #0x114] + ldr r1, =0x00000803 + str r1, [r0, #0x120] + ldr r1, =0x00800020 + str r1, [r0, #0x180] + ldr r1, =0x02000100 + str r1, [r0, #0x184] + ldr r1, =0x02098204 + str r1, [r0, #0x190] + ldr r1, =0x00030303 + str r1, [r0, #0x194] + + ldr r1, =0x00000016 + str r1, [r0, #0x200] + ldr r1, =0x00080808 + str r1, [r0, #0x204] + ldr r1, =0x00000f0f + str r1, [r0, #0x210] + ldr r1, =0x07070707 + str r1, [r0, #0x214] + ldr r1, =0x0f070707 + str r1, [r0, #0x218] + + ldr r1, =0x06000604 + str r1, [r0, #0x240] + ldr r1, =0x00000001 + str r1, [r0, #0x244] + + ldr r0, =SRC_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x1000 + str r1, [r0, r2] + + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x17420f40 + str r1, [r0] + ldr r1, =0x10210100 + str r1, [r0, #0x4] + ldr r1, =0x00060807 + str r1, [r0, #0x10] + ldr r1, =0x1010007e + str r1, [r0, #0xb0] + imx7d_ddrphy_latency_setting + ldr r1, =0x08080808 + str r1, [r0, #0x20] + ldr r1, =0x08080808 + str r1, [r0, #0x30] + ldr r1, =0x01000010 + str r1, [r0, #0x50] + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447304 + str r1, [r0, #0xc0] + ldr r1, =0x0e447306 + str r1, [r0, #0xc0] + +wait_zq: + ldr r1, [r0, #0xc4] + tst r1, #0x1 + beq wait_zq + + ldr r1, =0x0e407304 + str r1, [r0, #0xc0] + + ldr r0, =CCM_BASE_ADDR + mov r1, #0x0 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =IOMUXC_GPR_BASE_ADDR + mov r1, #0x178 + str r1, [r0, #0x20] + ldr r0, =CCM_BASE_ADDR + mov r1, #0x2 + ldr r2, =0x4130 + str r1, [r0, r2] + ldr r0, =DDRPHY_IPS_BASE_ADDR + ldr r1, =0x0000000f + str r1, [r0, #0x18] + + ldr r0, =DDRC_IPS_BASE_ADDR +wait_stat: + ldr r1, [r0, #0x4] + tst r1, #0x1 + beq wait_stat +.endm + +.macro imx7_clock_gating +#ifdef CONFIG_IMX_OPTEE + ldr r0, =0x30340024 + ldr r1, =0x1 + str r1, [r0] +#endif +.endm + +.macro imx7_qos_setting +.endm + +.macro imx7_ddr_setting + imx7d_sabresd_ddr_setting +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index 01e32136532..34a12cf1080 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -12,10 +12,24 @@ #include #include #include +#include +#include +#include +#include + +#ifdef CONFIG_BOOTLOADER_MENU +#include "video.h" +#include "dm/uclass.h" +#include "video_font_data.h" +#include "video_console.h" +#include "recovery.h" +#endif DECLARE_GLOBAL_DATA_PTR; #define UART_PAD_CTRL (PAD_CTL_PUS_UP) +#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE) +#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE) int dram_init(void) { @@ -24,6 +38,12 @@ int dram_init(void) return 0; } +ulong board_get_usable_ram_top(ulong total_size) +{ + /* Reserve top 1M memory used by M core vring/buffer */ + return gd->ram_top - SZ_1M; +} + static iomux_cfg_t const lpuart4_pads[] = { MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), @@ -35,6 +55,40 @@ static void setup_iomux_uart(void) ARRAY_SIZE(lpuart4_pads)); } +#ifdef CONFIG_FSL_QSPI +#ifndef CONFIG_DM_SPI +static iomux_cfg_t const quadspi_pads[] = { + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), +}; +#endif + +int board_qspi_init(void) +{ + u32 val; +#ifndef CONFIG_DM_SPI + mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); +#endif + + /* enable clock */ + val = readl(PCC1_RBASE + 0x94); + + if (!(val & 0x20000000)) { + writel(0x03000003, (PCC1_RBASE + 0x94)); + writel(0x43000003, (PCC1_RBASE + 0x94)); + } + + /* Enable QSPI as a wakeup source on B0 */ + if (soc_rev() >= CHIP_REV_2_0) + setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL); + return 0; +} +#endif + int board_early_init_f(void) { setup_iomux_uart(); @@ -47,6 +101,10 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + return 0; } @@ -94,3 +152,125 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } #endif + +#ifdef CONFIG_BOOTLOADER_MENU +static iomux_cfg_t const vol_pad[] = { + MX7ULP_PAD_PTA3__PTA3 | MUX_PAD_CTRL(PAD_CTL_IBE_ENABLE), +}; +#define VOLP_GPIO IMX_GPIO_NR(1, 3) +bool is_vol_key_pressed(void); +int show_bootloader_menu(void); +#endif + +int board_late_init(void) +{ + env_set("tee", "no"); +#ifdef CONFIG_IMX_OPTEE + env_set("tee", "yes"); +#endif + +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + +#ifdef CONFIG_BOOTLOADER_MENU + mx7ulp_iomux_setup_multiple_pads(vol_pad, ARRAY_SIZE(vol_pad)); + if (gpio_request(VOLP_GPIO, "volp")) + printf("request error\n"); + gpio_direction_input(VOLP_GPIO); + + if (is_vol_key_pressed()) + show_bootloader_menu(); +#endif + + return 0; +} + +#ifdef CONFIG_ANDROID_SUPPORT +bool is_power_key_pressed(void) { + /* the onoff button is 'pressed' by default on evk board */ + return (bool)(!(readl(SNVS_HPSR_REVB) & (0x1 << 6))); +} + +#ifdef CONFIG_BOOTLOADER_MENU +char bootloader_menu[4][40] = { + " * Power off the device\n", + " * Start the device normally\n", + " * Restart the bootloader\n", + " * Boot into recovery mode\n" +}; + +bool is_vol_key_pressed(void) { + int ret = 0; + ret = gpio_get_value(VOLP_GPIO); + return (bool)(!!ret); +} + +int show_bootloader_menu(void) { + struct udevice *dev, *dev_console; + uint32_t focus = 0, i; + bool stop_menu = false; + + /* clear screen first */ + if (uclass_first_device_err(UCLASS_VIDEO, &dev)) { + printf("no video device found!\n"); + return -1; + } + video_clear(dev); + + if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev_console)) { + printf("no text console device found!\n"); + return -1; + } + + vidconsole_position_cursor(dev_console, 0, 1); + vidconsole_put_string(dev_console, "Press 'vol+' to choose an item, press\n"); + vidconsole_put_string(dev_console, "power key to confirm:\n"); + while (!stop_menu) { + /* reset the cursor position. */ + vidconsole_position_cursor(dev_console, 0, 4); + /* show menu */ + for (i = 0; i < 4; i++) { + /* reverse color for the 'focus' line. */ + if (i == focus) + vidconsole_put_string(dev_console, "\x1b[7m"); + /* show text */ + vidconsole_put_string(dev_console, bootloader_menu[i]); + /* reset color back for the 'next' line. */ + if (i == focus) + vidconsole_put_string(dev_console, "\x1b[0m"); + } + /* check button status */ + while (1) { + if (is_power_key_pressed()) { + switch (focus) { + case 0: /*TODO*/ + case 1: + break; + case 2: + do_reset(NULL, 0, 0, NULL); + break; + case 3: + board_recovery_setup(); + break; + default: + break; + } + stop_menu = true; + break; + } else if (is_vol_key_pressed()) { + focus++; + if (focus > 3) + focus = 0; + mdelay(400); + break; + } + } + } + + /* clear screen before exit */ + video_clear(dev); + return 0; +} +#endif /* CONFIG_BOOTLOADER_MENU */ +#endif /* CONFIG_ANDROID_SUPPORT*/ diff --git a/board/freescale/mx7ulp_val/Kconfig b/board/freescale/mx7ulp_val/Kconfig new file mode 100644 index 00000000000..b68cb6f2594 --- /dev/null +++ b/board/freescale/mx7ulp_val/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX7ULP_10X10_VAL || TARGET_MX7ULP_14X14_VAL + +config SYS_BOARD + default "mx7ulp_val" + +config SYS_VENDOR + default "freescale" + +config SYS_CONFIG_NAME + default "mx7ulp_val" + +endif diff --git a/board/freescale/mx7ulp_val/Makefile b/board/freescale/mx7ulp_val/Makefile new file mode 100644 index 00000000000..ce82e631c80 --- /dev/null +++ b/board/freescale/mx7ulp_val/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := mx7ulp_val.o diff --git a/board/freescale/mx7ulp_val/imximage.cfg b/board/freescale/mx7ulp_val/imximage.cfg new file mode 100644 index 00000000000..ace3bd93220 --- /dev/null +++ b/board/freescale/mx7ulp_val/imximage.cfg @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7ulp_val/plugin.bin 0x2F020000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x403f00e0 0x00000000 +DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808080 +DATA 4 0x403e0508 0x00160002 +DATA 4 0x403E0510 0x00000000 +DATA 4 0x403E0514 0x00000001 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808019 +CHECK_BITS_SET 4 0x403e050c 0x00000040 +DATA 4 0x403E0030 0x00000001 +DATA 4 0x403e0040 0x11000020 +DATA 4 0x403f00e0 0x42000000 + +DATA 4 0x40B300AC 0x40000000 + +DATA 4 0x40AD0128 0x00040000 +DATA 4 0x40AD00F8 0x00000000 +DATA 4 0x40AD00D8 0x00000180 +DATA 4 0x40AD0108 0x00000180 +DATA 4 0x40AD0104 0x00000180 +DATA 4 0x40AD0124 0x00010000 +DATA 4 0x40AD0080 0x0000018C +DATA 4 0x40AD0084 0x0000018C +DATA 4 0x40AD0088 0x0000018C +DATA 4 0x40AD008C 0x0000018C + +DATA 4 0x40AD0120 0x00010000 +DATA 4 0x40AD010C 0x00000180 +DATA 4 0x40AD0110 0x00000180 +DATA 4 0x40AD0114 0x00000180 +DATA 4 0x40AD0118 0x00000180 +DATA 4 0x40AD0090 0x00000180 +DATA 4 0x40AD0094 0x00000180 +DATA 4 0x40AD0098 0x00000180 +DATA 4 0x40AD009C 0x00000180 + +DATA 4 0x40AD00E0 0x00040000 +DATA 4 0x40AD00E4 0x00040000 + +DATA 4 0x40AB001C 0x00008000 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB085C 0x0D3900A0 +DATA 4 0x40AB0890 0x00400000 + +DATA 4 0x40AB0848 0x39373939 +DATA 4 0x40AB0850 0x2F313D36 +DATA 4 0x40AB081C 0x33333333 +DATA 4 0x40AB0820 0x33333333 +DATA 4 0x40AB0824 0x33333333 +DATA 4 0x40AB0828 0x33333333 + +DATA 4 0x40AB08C0 0x24922492 +DATA 4 0x40AB08B8 0x00000800 + +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB000C 0x424642F3 +DATA 4 0x40AB0010 0x00100A22 +DATA 4 0x40AB0038 0x00120556 +DATA 4 0x40AB0014 0x00C700DA +DATA 4 0x40AB0018 0x00211718 +DATA 4 0x40AB002C 0x0F9F26D2 +DATA 4 0x40AB0030 0x009F0E10 +DATA 4 0x40AB0040 0x0000004F +DATA 4 0x40AB0000 0x84190000 + +DATA 4 0x40AB001C 0x00008010 +DATA 4 0x40AB001C 0x003F8030 +DATA 4 0x40AB001C 0xFF0A8030 +DATA 4 0x40AB001C 0x04028030 +DATA 4 0x40AB001C 0x83018030 +DATA 4 0x40AB001C 0x01038030 + +DATA 4 0x40AB083C 0x20000000 + +DATA 4 0x40AB0020 0x00001800 +DATA 4 0x40AB0800 0xA1310003 +DATA 4 0x40AB001C 0x00000000 + +#endif diff --git a/board/freescale/mx7ulp_val/imximage_lpddr2.cfg b/board/freescale/mx7ulp_val/imximage_lpddr2.cfg new file mode 100644 index 00000000000..9896cf39211 --- /dev/null +++ b/board/freescale/mx7ulp_val/imximage_lpddr2.cfg @@ -0,0 +1,133 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +#ifdef CONFIG_USE_IMXIMG_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx7ulp_val/plugin.bin 0x2F020000 +#else + +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ +DATA 4 0x403f00e0 0x00000000 +DATA 4 0x403e0040 0x01000020 +DATA 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808080 +DATA 4 0x403e0508 0x00160002 +DATA 4 0x403E0510 0x00000000 +DATA 4 0x403E0514 0x00000001 +DATA 4 0x403e0500 0x00000001 +CHECK_BITS_SET 4 0x403e0500 0x01000000 +DATA 4 0x403e050c 0x80808019 +CHECK_BITS_SET 4 0x403e050c 0x00000040 +DATA 4 0x403E0030 0x00000001 +DATA 4 0x403e0040 0x11000020 +DATA 4 0x403f00e0 0x42000000 + +DATA 4 0x40B300AC 0x40000000 + +DATA 4 0x40AD0128 0x00040000 +DATA 4 0x40AD00F8 0x00000000 +DATA 4 0x40AD00D8 0x0000018C +DATA 4 0x40AD0108 0x00000180 +DATA 4 0x40AD0104 0x00000180 +DATA 4 0x40AD0124 0x00010000 +DATA 4 0x40AD0080 0x0000018C +DATA 4 0x40AD0084 0x0000018C +DATA 4 0x40AD0088 0x0000018C +DATA 4 0x40AD008C 0x0000018C + +DATA 4 0x40AD0120 0x00010000 +DATA 4 0x40AD010C 0x00000180 +DATA 4 0x40AD0110 0x00000180 +DATA 4 0x40AD0114 0x00000180 +DATA 4 0x40AD0118 0x00000180 +DATA 4 0x40AD0090 0x00000180 +DATA 4 0x40AD0094 0x00000180 +DATA 4 0x40AD0098 0x00000180 +DATA 4 0x40AD009C 0x00000180 + +DATA 4 0x40AD00E0 0x00040000 +DATA 4 0x40AD00E4 0x00040000 + +DATA 4 0x40AB001C 0x00008000 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB085C 0x0D3900A0 +DATA 4 0x40AB0890 0x00400000 + +DATA 4 0x40AB0848 0x40404040 +DATA 4 0x40AB0850 0x40404040 +DATA 4 0x40AB081C 0x33333333 +DATA 4 0x40AB0820 0x33333333 +DATA 4 0x40AB0824 0x33333333 +DATA 4 0x40AB0828 0x33333333 + +DATA 4 0x40AB08C0 0x24922492 +DATA 4 0x40AB08B8 0x00000800 + +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB000C 0x292C42F3 +DATA 4 0x40AB0010 0x00100A22 +DATA 4 0x40AB0038 0x00120556 +DATA 4 0x40AB0014 0x00C700DB +DATA 4 0x40AB0018 0x00211708 +DATA 4 0x40AB002C 0x0F9F26D2 +DATA 4 0x40AB0030 0x009F0E10 +DATA 4 0x40AB0040 0x0000003F +DATA 4 0x40AB0000 0xC3110000 + +DATA 4 0x40AB001C 0x00008010 +DATA 4 0x40AB001C 0x00008018 +DATA 4 0x40AB001C 0x003F8030 +DATA 4 0x40AB001C 0x003F8038 +DATA 4 0x40AB001C 0xFF0A8030 +DATA 4 0x40AB001C 0xFF0A8038 +DATA 4 0x40AB001C 0x04028030 +DATA 4 0x40AB001C 0x04028038 +DATA 4 0x40AB001C 0x82018030 +DATA 4 0x40AB001C 0x82018038 +DATA 4 0x40AB001C 0x01038030 +DATA 4 0x40AB001C 0x01038038 + +DATA 4 0x40AB083C 0x20000000 + +DATA 4 0x40AB0020 0x00001800 +DATA 4 0x40AB0800 0xA1390003 +DATA 4 0x40AB0004 0x00020052 +DATA 4 0x40AB0404 0x00011006 +DATA 4 0x40AB001C 0x00000000 + +#endif diff --git a/board/freescale/mx7ulp_val/mx7ulp_val.c b/board/freescale/mx7ulp_val/mx7ulp_val.c new file mode 100644 index 00000000000..d1e03a20183 --- /dev/null +++ b/board/freescale/mx7ulp_val/mx7ulp_val.c @@ -0,0 +1,220 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_UP) + +#define GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE) + +#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE) +#define OTG_PWR_GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE) + +#define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE) + +#define QSPI_PAD_CTRL0 (PAD_CTL_PUS_UP | PAD_CTL_DSE \ + | PAD_CTL_OBE_ENABLE) + + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_SIZE; + + return 0; +} + +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL +/* PTF11 and PTF10 also can mux to LPUART6 on 10x10 validation, depends on rework*/ +static iomux_cfg_t const lpuart6_pads[] = { + MX7ULP_PAD_PTE11__LPUART6_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7ULP_PAD_PTE10__LPUART6_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; +#else +static iomux_cfg_t const lpuart4_pads[] = { + MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; +#endif + +static void setup_iomux_uart(void) +{ +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL + mx7ulp_iomux_setup_multiple_pads(lpuart6_pads, ARRAY_SIZE(lpuart6_pads)); +#else + mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, ARRAY_SIZE(lpuart4_pads)); +#endif +} + +#ifdef CONFIG_USB_EHCI_MX7 + +static iomux_cfg_t const usb_otg1_pads[] = { + +#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 + MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */ + MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */ +#else + /*Need rework for ID and PWR_EN pins on 14x14 ARM2*/ + MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */ + MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */ +#endif +}; + +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 0) +#define OTG0_PWR_EN IMX_GPIO_NR(3, 1) +#else +#define OTG0_ID_GPIO IMX_GPIO_NR(3, 18) +#define OTG0_PWR_EN IMX_GPIO_NR(1, 31) +#endif +static void setup_usb(void) +{ + mx7ulp_iomux_setup_multiple_pads(usb_otg1_pads, + ARRAY_SIZE(usb_otg1_pads)); + + gpio_request(OTG0_ID_GPIO, "otg_id"); + gpio_direction_input(OTG0_ID_GPIO); +} + +/*Needs to override the ehci power if controlled by GPIO */ +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + if (on) + gpio_direction_output(OTG0_PWR_EN, 1); + else + gpio_direction_output(OTG0_PWR_EN, 0); + break; + default: + printf("MXC USB port %d not yet supported\n", port); + return -EINVAL; + } + + return 0; +} + +int board_usb_phy_mode(int port) +{ + int ret = 0; + + if (port == 0) { + ret = gpio_get_value(OTG0_ID_GPIO); + + if (ret) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + } + + return USB_INIT_HOST; +} + +#endif + + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +#ifdef CONFIG_FSL_QSPI +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL +static iomux_cfg_t const quadspi_pads[] = { + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB14__QSPIA_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX7ULP_PAD_PTB5__PTB5 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 5) +#else +/* MT35XU512ABA supports 8 bits I/O, since our driver only support 4, so mux 4 data pins*/ +static iomux_cfg_t const quadspi_pads[] = { + MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB9__QSPIA_DQS | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB15__QSPIA_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL0), + MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1), + + MX7ULP_PAD_PTB12__PTB12 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +#define QSPI_RST_GPIO IMX_GPIO_NR(2, 12) + +#endif +int board_qspi_init(void) +{ + u32 val; + mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads)); + /* enable clock */ + val = readl(PCC1_RBASE + 0x94); + + if (!(val & 0x20000000)) { + writel(0x03000003, (PCC1_RBASE + 0x94)); + writel(0x43000003, (PCC1_RBASE + 0x94)); + } + + /* Enable QSPI as a wakeup source on B0 */ + if (soc_rev() >= CHIP_REV_2_0) + setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL); + + gpio_request(QSPI_RST_GPIO, "qspi_reset"); + gpio_direction_output(QSPI_RST_GPIO, 0); + mdelay(10); + gpio_direction_output(QSPI_RST_GPIO, 1); + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_USB_EHCI_MX7 + setup_usb(); +#endif + +#ifdef CONFIG_FSL_QSPI + board_qspi_init(); +#endif + + return 0; +} + +int board_late_init(void) +{ + return 0; +} + +int checkboard(void) +{ +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL + printf("Board: i.MX7ULP 10x10 Validation board\n"); +#else + printf("Board: i.MX7ULP 14x14 Validation board\n"); +#endif + return 0; +} diff --git a/board/freescale/mx7ulp_val/plugin.S b/board/freescale/mx7ulp_val/plugin.S new file mode 100644 index 00000000000..554ee8fe828 --- /dev/null +++ b/board/freescale/mx7ulp_val/plugin.S @@ -0,0 +1,352 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +.macro imx7ulp_ddr_freq_decrease + ldr r2, =0x403f0000 + ldr r3, =0x00000000 + str r3, [r2, #0xe0] + + ldr r2, =0x403e0000 + ldr r3, =0x01000020 + str r3, [r2, #0x40] + ldr r3, =0x01000000 + str r3, [r2, #0x500] + + ldr r3, =0x80808080 + str r3, [r2, #0x50c] + ldr r3, =0x00160002 + str r3, [r2, #0x508] + ldr r3, =0x00000000 + str r3, [r2, #0x510] + ldr r3, =0x00000001 + str r3, [r2, #0x514] + ldr r3, =0x00000001 + str r3, [r2, #0x500] + + ldr r3, =0x01000000 +wait1: + ldr r4, [r2, #0x500] + and r4, r3 + cmp r4, r3 + bne wait1 + + ldr r3, =0x80808019 + str r3, [r2, #0x50c] + + ldr r3, =0x00000040 +wait2: + ldr r4, [r2, #0x50c] + and r4, r3 + cmp r4, r3 + bne wait2 + + ldr r3, =0x00000001 + str r3, [r2, #0x30] + ldr r3, =0x11000020 + str r3, [r2, #0x40] + + ldr r2, =0x403f0000 + ldr r3, =0x42000000 + str r3, [r2, #0xe0] + +.endm + +.macro imx7ulp_arm2_lpddr3_setting + + imx7ulp_ddr_freq_decrease + + /* Enable MMDC PCC clock */ + ldr r2, =0x40b30000 + ldr r3, =0x40000000 + str r3, [r2, #0xac] + + /* Configure DDR pad */ + ldr r0, =0x40ad0000 + ldr r1, =0x00040000 + str r1, [r0, #0x128] + ldr r1, =0x0 + str r1, [r0, #0xf8] + ldr r1, =0x00000180 + str r1, [r0, #0xd8] + ldr r1, =0x00000180 + str r1, [r0, #0x108] + ldr r1, =0x00000180 + str r1, [r0, #0x104] + ldr r1, =0x00010000 + str r1, [r0, #0x124] + ldr r1, =0x0000018C + str r1, [r0, #0x80] + ldr r1, =0x0000018C + str r1, [r0, #0x84] + ldr r1, =0x0000018C + str r1, [r0, #0x88] + ldr r1, =0x0000018C + str r1, [r0, #0x8c] + + ldr r1, =0x00010000 + str r1, [r0, #0x120] + ldr r1, =0x00000180 + str r1, [r0, #0x10c] + ldr r1, =0x00000180 + str r1, [r0, #0x110] + ldr r1, =0x00000180 + str r1, [r0, #0x114] + ldr r1, =0x00000180 + str r1, [r0, #0x118] + ldr r1, =0x00000180 + str r1, [r0, #0x90] + ldr r1, =0x00000180 + str r1, [r0, #0x94] + ldr r1, =0x00000180 + str r1, [r0, #0x98] + ldr r1, =0x00000180 + str r1, [r0, #0x9c] + ldr r1, =0x00040000 + str r1, [r0, #0xe0] + ldr r1, =0x00040000 + str r1, [r0, #0xe4] + + ldr r0, =0x40ab0000 + ldr r1, =0x00008000 + str r1, [r0, #0x1c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0D3900A0 + str r1, [r0, #0x85c] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x39373939 + str r1, [r0, #0x848] + ldr r1, =0x2F313D36 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81c] + ldr r1, =0x33333333 + str r1, [r0, #0x820] + ldr r1, =0x33333333 + str r1, [r0, #0x824] + ldr r1, =0x33333333 + str r1, [r0, #0x828] + + ldr r1, =0x24922492 + str r1, [r0, #0x8c0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x424642F3 + str r1, [r0, #0xc] + ldr r1, =0x00100A22 + str r1, [r0, #0x10] + ldr r1, =0x00120556 + str r1, [r0, #0x38] + ldr r1, =0x00C700DA + str r1, [r0, #0x14] + ldr r1, =0x00211718 + str r1, [r0, #0x18] + + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x2c] + ldr r1, =0x009F0E10 + str r1, [r0, #0x30] + ldr r1, =0x0000004F + str r1, [r0, #0x40] + ldr r1, =0x84190000 + str r1, [r0, #0x0] + + ldr r1, =0x00008010 + str r1, [r0, #0x1c] + ldr r1, =0x003F8030 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x1c] + ldr r1, =0x04028030 + str r1, [r0, #0x1c] + ldr r1, =0x83018030 + str r1, [r0, #0x1c] + ldr r1, =0x01038030 + str r1, [r0, #0x1c] + + ldr r1, =0x20000000 + str r1, [r0, #0x83c] + + ldr r1, =0x00001800 + str r1, [r0, #0x20] + ldr r1, =0xA1310003 + str r1, [r0, #0x800] + ldr r1, =0x00000000 + str r1, [r0, #0x1c] + +.endm + +.macro imx7ulp_arm2_lpddr2_setting + + imx7ulp_ddr_freq_decrease + + /* Enable MMDC PCC clock */ + ldr r2, =0x40b30000 + ldr r3, =0x40000000 + str r3, [r2, #0xac] + + /* Configure DDR pad */ + ldr r0, =0x40ad0000 + ldr r1, =0x00040000 + str r1, [r0, #0x128] + ldr r1, =0x0 + str r1, [r0, #0xf8] + ldr r1, =0x0000018C + str r1, [r0, #0xd8] + ldr r1, =0x00000180 + str r1, [r0, #0x108] + ldr r1, =0x00000180 + str r1, [r0, #0x104] + ldr r1, =0x00010000 + str r1, [r0, #0x124] + ldr r1, =0x0000018C + str r1, [r0, #0x80] + ldr r1, =0x0000018C + str r1, [r0, #0x84] + ldr r1, =0x0000018C + str r1, [r0, #0x88] + ldr r1, =0x0000018C + str r1, [r0, #0x8c] + + ldr r1, =0x00010000 + str r1, [r0, #0x120] + ldr r1, =0x00000180 + str r1, [r0, #0x10c] + ldr r1, =0x00000180 + str r1, [r0, #0x110] + ldr r1, =0x00000180 + str r1, [r0, #0x114] + ldr r1, =0x00000180 + str r1, [r0, #0x118] + ldr r1, =0x00000180 + str r1, [r0, #0x90] + ldr r1, =0x00000180 + str r1, [r0, #0x94] + ldr r1, =0x00000180 + str r1, [r0, #0x98] + ldr r1, =0x00000180 + str r1, [r0, #0x9c] + ldr r1, =0x00040000 + str r1, [r0, #0xe0] + ldr r1, =0x00040000 + str r1, [r0, #0xe4] + + ldr r0, =0x40ab0000 + ldr r1, =0x00008000 + str r1, [r0, #0x1c] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x0D3900A0 + str r1, [r0, #0x85c] + ldr r1, =0x00400000 + str r1, [r0, #0x890] + + ldr r1, =0x40404040 + str r1, [r0, #0x848] + ldr r1, =0x40404040 + str r1, [r0, #0x850] + ldr r1, =0x33333333 + str r1, [r0, #0x81c] + ldr r1, =0x33333333 + str r1, [r0, #0x820] + ldr r1, =0x33333333 + str r1, [r0, #0x824] + ldr r1, =0x33333333 + str r1, [r0, #0x828] + + ldr r1, =0x24922492 + str r1, [r0, #0x8c0] + ldr r1, =0x00000800 + str r1, [r0, #0x8b8] + + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x292C42F3 + str r1, [r0, #0xc] + ldr r1, =0x00100A22 + str r1, [r0, #0x10] + ldr r1, =0x00120556 + str r1, [r0, #0x38] + ldr r1, =0x00C700DB + str r1, [r0, #0x14] + ldr r1, =0x00211708 + str r1, [r0, #0x18] + + ldr r1, =0x0F9F26D2 + str r1, [r0, #0x2c] + ldr r1, =0x009F0E10 + str r1, [r0, #0x30] + ldr r1, =0x0000003F + str r1, [r0, #0x40] + ldr r1, =0xC3110000 + str r1, [r0, #0x0] + + ldr r1, =0x00008010 + str r1, [r0, #0x1c] + ldr r1, =0x00008018 + str r1, [r0, #0x1c] + ldr r1, =0x003F8030 + str r1, [r0, #0x1c] + ldr r1, =0x003F8038 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8030 + str r1, [r0, #0x1c] + ldr r1, =0xFF0A8038 + str r1, [r0, #0x1c] + ldr r1, =0x04028030 + str r1, [r0, #0x1c] + ldr r1, =0x04028038 + str r1, [r0, #0x1c] + ldr r1, =0x82018030 + str r1, [r0, #0x1c] + ldr r1, =0x82018038 + str r1, [r0, #0x1c] + ldr r1, =0x01038030 + str r1, [r0, #0x1c] + ldr r1, =0x01038038 + str r1, [r0, #0x1c] + + ldr r1, =0x20000000 + str r1, [r0, #0x83c] + + ldr r1, =0x00001800 + str r1, [r0, #0x20] + ldr r1, =0xA1390003 + str r1, [r0, #0x800] + ldr r1, =0x00020052 + str r1, [r0, #0x4] + ldr r1, =0x00011006 + str r1, [r0, #0x404] + ldr r1, =0x00000000 + str r1, [r0, #0x1c] + +.endm + + +.macro imx7ulp_clock_gating +.endm + +.macro imx7ulp_qos_setting +.endm + +.macro imx7ulp_ddr_setting +#if defined (CONFIG_TARGET_MX7ULP_10X10_VAL) + imx7ulp_arm2_lpddr2_setting +#else + imx7ulp_arm2_lpddr3_setting +#endif +.endm + +/* include the common plugin code here */ +#include diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c index e77f3f7146f..b0ff4b1f375 100644 --- a/board/freescale/t208xrdb/eth_t208xrdb.c +++ b/board/freescale/t208xrdb/eth_t208xrdb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2021 NXP * * Shengzhou Liu */ @@ -104,6 +105,40 @@ int board_eth_init(struct bd_info *bis) return pci_eth_init(bis); } +/* Disable the MAC5 and MAC6 "fsl,fman-memac" nodes and the two + * "fsl,dpa-ethernet" nodes that reference them. + */ +void fdt_fixup_board_fman_ethernet(void *fdt) +{ + int mac_off, eth_off, i; + char mac_path[2][42] = { + "/soc@ffe000000/fman@400000/ethernet@e8000", + "/soc@ffe000000/fman@400000/ethernet@ea000", + }; + u32 eth_ph; + + for (i = 0; i < 2; i++) { + /* Disable the MAC node */ + mac_off = fdt_path_offset(fdt, mac_path[i]); + if (mac_off < 0) + continue; + fdt_status_disabled(fdt, mac_off); + + /* Disable the fsl,dpa-ethernet node that points to the MAC. + * The fsl,fman-mac property refers to the MAC's phandle. + */ + eth_ph = fdt_get_phandle(fdt, mac_off); + if (eth_ph <= 0) + continue; + + eth_off = fdt_node_offset_by_prop_value(fdt, -1, "fsl,fman-mac", + ð_ph, + sizeof(eth_ph)); + if (eth_off >= 0) + fdt_status_disabled(fdt, eth_off); + } +} + void fdt_fixup_board_enet(void *fdt) { return; diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c index a18459841c6..7ccb205c647 100644 --- a/board/freescale/t208xrdb/t208xrdb.c +++ b/board/freescale/t208xrdb/t208xrdb.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2009-2013 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #include @@ -137,6 +138,8 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN #ifndef CONFIG_DM_ETH fdt_fixup_fman_ethernet(blob); +#else + fdt_fixup_board_fman_ethernet(blob); #endif fdt_fixup_board_enet(blob); #endif diff --git a/board/freescale/t208xrdb/t208xrdb.h b/board/freescale/t208xrdb/t208xrdb.h index 22a496fb8cf..cd0a9f44da7 100644 --- a/board/freescale/t208xrdb/t208xrdb.h +++ b/board/freescale/t208xrdb/t208xrdb.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #ifndef __CORENET_DS_H__ @@ -8,5 +9,6 @@ void fdt_fixup_board_enet(void *blob); void pci_of_setup(void *blob, struct bd_info *bd); +void fdt_fixup_board_fman_ethernet(void *blob); #endif diff --git a/cmd/Kconfig b/cmd/Kconfig index 863b7f9fda4..832b2ceb4c0 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -397,6 +397,12 @@ config CMD_SPL_WRITE_SIZE flash used by Falcon-mode boot. See the documentation until CMD_SPL for detail. +config CMD_FSL_CAAM_KB + bool "Freescale i.MX CAAM command" + help + Implement the "caam" command to generate DEK blob for one block of data + or decap the DEK blob to its original data. + config CMD_THOR_DOWNLOAD bool "thor - TIZEN 'thor' download" select DFU @@ -1960,6 +1966,9 @@ config CMD_AES config CMD_BLOB bool "Enable the 'blob' command" + select FSL_BLOB + depends on !MX6ULL && !MX6SLL && !MX6SL + select IMX_HAB if ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_IMX8M help This is used with the Freescale secure boot mechanism. @@ -2203,6 +2212,12 @@ config MTDPARTS_DEFAULT Defines a default MTD partitioning scheme in the Linux MTD command line partitions format +config MTDPARTS_SKIP_INVALID + bool "Skip invalid devices and keep checking the next one" + depends on CMD_MTDPARTS + help + Enable this feature will look for next device rather than quit. + config CMD_REISER bool "reiser - Access to reiserfs filesystems" help diff --git a/cmd/Makefile b/cmd/Makefile index 567e2b79d25..d46ffd70214 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_CMD_FLASH) += flash.o obj-$(CONFIG_CMD_FPGA) += fpga.o obj-$(CONFIG_CMD_FPGAD) += fpgad.o obj-$(CONFIG_CMD_FS_GENERIC) += fs.o +obj-$(CONFIG_CMD_FSL_CAAM_KB) += cmd_fsl_caam.o obj-$(CONFIG_CMD_FUSE) += fuse.o obj-$(CONFIG_CMD_GETTIME) += gettime.o obj-$(CONFIG_CMD_GPIO) += gpio.o diff --git a/cmd/blob.c b/cmd/blob.c index c80e6977b4b..887219cc079 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -9,6 +9,11 @@ #include #include #include +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8M) +#include +#include +#endif /** * blob_decap() - Decapsulate the data as a blob @@ -74,6 +79,17 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc, src_ptr = (uint8_t *)(uintptr_t)src_addr; dst_ptr = (uint8_t *)(uintptr_t)dst_addr; +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8M) + + hab_caam_clock_enable(1); + + u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + FSL_CAAM_ORSR_JRa_OFFSET); + if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) + sec_init(); +#endif + if (enc) ret = blob_encap(km_ptr, src_ptr, dst_ptr, len); else diff --git a/cmd/bmp.c b/cmd/bmp.c index 6040fa5d95d..92fcbce6119 100644 --- a/cmd/bmp.c +++ b/cmd/bmp.c @@ -20,6 +20,7 @@ #include #include #include +#include #include static int bmp_info (ulong addr); @@ -255,8 +256,15 @@ int bmp_display(ulong addr, int x, int y) addr = map_to_sysmem(bmp); #ifdef CONFIG_DM_VIDEO +#ifdef CONFIG_VIDEO_LINK + dev = video_link_get_video_device(); + if (!dev) { + ret = -ENODEV; + } else { +#else ret = uclass_first_device_err(UCLASS_VIDEO, &dev); if (!ret) { +#endif bool align = false; if (CONFIG_IS_ENABLED(SPLASH_SCREEN_ALIGN) || diff --git a/cmd/booti.c b/cmd/booti.c index 3df70ea9caa..d7b5fb64120 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -78,6 +78,16 @@ static int booti_start(struct cmd_tbl *cmdtp, int flag, int argc, if (ret != 0) return 1; +#if defined(CONFIG_IMX_HAB) && !defined(CONFIG_AVB_SUPPORT) + extern int authenticate_image( + uint32_t ddr_start, uint32_t raw_image_size); + if (authenticate_image(ld, image_size) != 0) { + printf("Authenticate Image Fail, Please check\n"); + return 1; + } + +#endif + /* Handle BOOTM_STATE_LOADOS */ if (relocated_addr != ld) { printf("Moving Image from 0x%lx to 0x%lx, end=%lx\n", ld, diff --git a/cmd/bootm.c b/cmd/bootm.c index 81c6b939781..93604453f97 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -125,6 +125,67 @@ int do_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return do_bootm_subcommand(cmdtp, flag, argc, argv); } +#ifdef CONFIG_IMX_HAB + extern int authenticate_image( + uint32_t ddr_start, uint32_t raw_image_size); + +#ifdef CONFIG_IMX_OPTEE + ulong tee_addr = 0; + int ret; + ulong zi_start, zi_end; + + tee_addr = env_get_ulong("tee_addr", 16, tee_addr); + if (!tee_addr) { + printf("Not valid tee_addr, Please check\n"); + return 1; + } + + switch (genimg_get_format((const void *)tee_addr)) { + case IMAGE_FORMAT_LEGACY: + if (authenticate_image(tee_addr, + image_get_image_size((image_header_t *)tee_addr)) != 0) { + printf("Authenticate uImage Fail, Please check\n"); + return 1; + } + break; + default: + printf("Not valid image format for Authentication, Please check\n"); + return 1; + }; + + ret = bootz_setup(image_load_addr, &zi_start, &zi_end); + if (ret != 0) + return 1; + + if (authenticate_image(image_load_addr, zi_end - zi_start) != 0) { + printf("Authenticate zImage Fail, Please check\n"); + return 1; + } + +#else + + switch (genimg_get_format((const void *)image_load_addr)) { +#if defined(CONFIG_LEGACY_IMAGE_FORMAT) + case IMAGE_FORMAT_LEGACY: + if (authenticate_image(image_load_addr, + image_get_image_size((image_header_t *)image_load_addr)) != 0) { + printf("Authenticate uImage Fail, Please check\n"); + return 1; + } + break; +#endif +#ifdef CONFIG_ANDROID_BOOT_IMAGE + case IMAGE_FORMAT_ANDROID: + /* Do this authentication in boota command */ + break; +#endif + default: + printf("Not valid image format for Authentication, Please check\n"); + return 1; + } +#endif +#endif + return do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START | BOOTM_STATE_FINDOS | BOOTM_STATE_FINDOTHER | BOOTM_STATE_LOADOS | diff --git a/cmd/bootz.c b/cmd/bootz.c index 7556cd2752a..497fa81aff4 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -57,6 +57,14 @@ static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc, if (bootm_find_images(flag, argc, argv, images->ep, zi_end - zi_start)) return 1; +#ifdef CONFIG_IMX_HAB + extern int authenticate_image( + uint32_t ddr_start, uint32_t raw_image_size); + if (authenticate_image(images->ep, zi_end - zi_start) != 0) { + printf("Authenticate zImage Fail, Please check\n"); + return 1; + } +#endif return 0; } diff --git a/cmd/cmd_fsl_caam.c b/cmd/cmd_fsl_caam.c new file mode 100644 index 00000000000..b0550138f5e --- /dev/null +++ b/cmd/cmd_fsl_caam.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include +#include +#include + +static int do_caam(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + + int ret, i; + + if (argc < 2) + return CMD_RET_USAGE; + + if (strcmp(argv[1], "genblob") == 0) { + + if (argc != 5) + return CMD_RET_USAGE; + + void *data_addr; + void *blob_addr; + int size; + + data_addr = (void *)simple_strtoul(argv[2], NULL, 16); + blob_addr = (void *)simple_strtoul(argv[3], NULL, 16); + size = simple_strtoul(argv[4], NULL, 10); + if (size <= 48) + return CMD_RET_USAGE; + + caam_open(); + ret = caam_gen_blob((uint32_t)data_addr, (uint32_t)blob_addr, (uint32_t)size); + + if(ret != SUCCESS){ + printf("Error during blob encap operation: 0x%x\n", ret); + return 0; + } + + /* Print the generated DEK blob */ + printf("DEK blob is available at 0x%08X and equals:\n",(unsigned int)blob_addr); + for(i=0;i= 0) + controller_index = index; + else + return CMD_RET_USAGE; + } else { + usb_controller = argv[1]; + controller_index = simple_strtoul(usb_controller, &endp, 0); + if (*endp != '\0') { + pr_err("Error: Wrong USB controller index format\n"); + return CMD_RET_FAILURE; + } +#ifdef CONFIG_FASTBOOT_USB_DEV + controller_index = CONFIG_FASTBOOT_USB_DEV; +#endif } ret = usb_gadget_initialize(controller_index); diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index ed373a8c4da..247db43bc4c 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -160,6 +160,40 @@ static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len); static int device_del(struct mtd_device *dev); +#ifdef CONFIG_MTDPARTS_SKIP_INVALID +int skip_counter = 0; +/* + * find a seperator to locate the next entry + * @param p pointer of the pointer of input char string + * @param sp seperator charactor + * @param n find the nth seperator + * @param limit the looking scope + * @return 1 on success, otherwise 0 + */ +static int find_seperator(const char **p, char sp, int n, int limit) +{ + int i, j; + + /* n = 0 means do nothing */ + if (!n) + return 1; + + i = j = 0; + + while (*p && (**p != '\0') && (i < limit)) { + if (**p == sp) { + (*p)++; + j++; + if (j == n) + return 1; + } + (*p)++; + i++; + } + + return 0; +} +#endif /** * Parses a string into a number. The number stored at ptr is * potentially suffixed with K (for kilobytes, or 1024 bytes), @@ -1578,6 +1612,12 @@ static int parse_mtdparts(const char *const mtdparts) while (*p != '\0') { err = 1; +#ifdef CONFIG_MTDPARTS_SKIP_INVALID + if (!find_seperator(&p, ';', skip_counter, MTDPARTS_MAXLEN)) { + printf("goes wrong when skip invalid parts\n"); + return 1; + } +#endif if ((device_parse(p, &p, &dev) != 0) || (!dev)) break; @@ -1648,8 +1688,20 @@ static int parse_mtdids(const char *const ids) p++; /* check if requested device exists */ - if (mtd_device_validate(type, num, &size) != 0) + if (mtd_device_validate(type, num, &size) != 0) { +#ifdef CONFIG_MTDPARTS_SKIP_INVALID + if (find_seperator(&p, ',', 1, MTDIDS_MAXLEN)) { + printf("current device is invalid, skip it and check the next one\n"); + skip_counter++; + continue; + } else { + printf("the only deivce is invalid\n"); + return 1; + } +#else return 1; +#endif + } /* locate */ mtd_id = p; diff --git a/cmd/read.c b/cmd/read.c index 34f53f9a292..daea30a4784 100644 --- a/cmd/read.c +++ b/cmd/read.c @@ -12,7 +12,7 @@ #include #include -int do_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +int do_raw_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { char *ep; struct blk_desc *dev_desc = NULL; @@ -75,7 +75,7 @@ int do_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } U_BOOT_CMD( - read, 6, 0, do_read, + read, 6, 0, do_raw_read, "Load binary data from a partition", " addr blk# cnt" ); diff --git a/cmd/sata.c b/cmd/sata.c index aa396c1bbdf..e0106f871a6 100644 --- a/cmd/sata.c +++ b/cmd/sata.c @@ -89,8 +89,10 @@ static int do_sata(struct cmd_tbl *cmdtp, int flag, int argc, if (argc == 3) devnum = (int)simple_strtoul(argv[2], NULL, 10); - if (!strcmp(argv[1], "stop")) + if (!strcmp(argv[1], "stop")) { + sata_curr_device = -1; return sata_remove(devnum); + } if (!strcmp(argv[1], "init")) { if (sata_curr_device != -1) { @@ -99,7 +101,11 @@ static int do_sata(struct cmd_tbl *cmdtp, int flag, int argc, return rc; } - return sata_probe(devnum); + rc = sata_probe(devnum); + if (rc < 0) + return CMD_RET_FAILURE; + sata_curr_device = rc; + return CMD_RET_SUCCESS; } } diff --git a/common/autoboot.c b/common/autoboot.c index 0bb08e7a4cf..2802e381ad5 100644 --- a/common/autoboot.c +++ b/common/autoboot.c @@ -23,6 +23,9 @@ #include #include #include +#ifdef is_boot_from_usb +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -345,6 +348,21 @@ const char *bootdelay_process(void) bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay", bootdelay); +#if defined(is_boot_from_usb) + if (is_boot_from_usb() && env_get("bootcmd_mfg")) { + disconnect_from_pc(); + printf("Boot from USB for mfgtools\n"); + bootdelay = 0; + env_set_default("Use default environment for \ + mfgtools\n", 0); + } else if (is_boot_from_usb()) { + printf("Boot from USB for uuu\n"); + env_set("bootcmd", "fastboot 0"); + } else { + printf("Normal Boot\n"); + } +#endif + debug("### main_loop entered: bootdelay=%d\n\n", bootdelay); if (IS_ENABLED(CONFIG_AUTOBOOT_MENU_SHOW)) @@ -361,6 +379,13 @@ const char *bootdelay_process(void) else s = env_get("bootcmd"); +#if defined(is_boot_from_usb) + if (is_boot_from_usb() && env_get("bootcmd_mfg")) { + s = env_get("bootcmd_mfg"); + printf("Run bootcmd_mfg: %s\n", s); + } +#endif + if (IS_ENABLED(CONFIG_OF_CONTROL)) process_fdt_options(gd->fdt_blob); stored_bootdelay = bootdelay; diff --git a/common/board_f.c b/common/board_f.c index 0cddf0359dc..1216ba8e0aa 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -847,7 +847,9 @@ static const init_fnc_t init_sequence_f[] = { #endif env_init, /* initialize environment */ init_baud_rate, /* initialze baudrate settings */ +#ifndef CONFIG_ANDROID_AUTO_SUPPORT serial_init, /* serial communications setup */ +#endif console_init_f, /* stage 1 init of console */ display_options, /* say that we are here */ display_text_info, /* show debugging info if required */ diff --git a/common/board_r.c b/common/board_r.c index c835ff8e260..aa0fe6b57d0 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -77,6 +77,9 @@ #ifdef CONFIG_EFI_SETUP_EARLY #include #endif +#ifdef CONFIG_FSL_FASTBOOT +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -578,6 +581,46 @@ int initr_mem(void) } #endif +#if defined(AVB_RPMB) && !defined(CONFIG_SPL) +extern int init_avbkey(void); +static int initr_avbkey(void) +{ + return init_avbkey(); +} +#endif + +#ifdef CONFIG_FSL_FASTBOOT +static int initr_fastboot_setup(void) +{ + fastboot_setup(); + return 0; +} + +static int initr_check_fastboot(void) +{ + fastboot_run_bootmode(); + return 0; +} +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +extern void tee_setup(void); +static int initr_tee_setup(void) +{ + tee_setup(); + return 0; +} +#endif + +#ifdef CONFIG_DUAL_BOOTLOADER +extern void check_spl_recovery(void); +static int initr_check_spl_recovery(void) +{ + check_spl_recovery(); + return 0; +} +#endif + static int run_main_loop(void) { #ifdef CONFIG_SANDBOX @@ -759,6 +802,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_BOARD_LATE_INIT board_late_init, #endif +#ifdef CONFIG_FSL_FASTBOOT + initr_fastboot_setup, +#endif #if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI) INIT_FUNC_WATCHDOG_RESET initr_scsi, @@ -797,6 +843,18 @@ static init_fnc_t init_sequence_r[] = { #endif #ifdef CONFIG_EFI_SETUP_EARLY (init_fnc_t)efi_init_obj_list, +#endif +#if defined(AVB_RPMB) && !defined(CONFIG_SPL) + initr_avbkey, +#endif +#ifdef CONFIG_IMX_TRUSTY_OS + initr_tee_setup, +#endif +#ifdef CONFIG_FSL_FASTBOOT + initr_check_fastboot, +#endif +#ifdef CONFIG_DUAL_BOOTLOADER + initr_check_spl_recovery, #endif run_main_loop, }; diff --git a/common/eeprom/eeprom_field.c b/common/eeprom/eeprom_field.c index f56eebe679f..814dc4eb7a2 100644 --- a/common/eeprom/eeprom_field.c +++ b/common/eeprom/eeprom_field.c @@ -11,7 +11,7 @@ #include static void __eeprom_field_print_bin(const struct eeprom_field *field, - char *delimiter, bool reverse) + uchar *fbuf, char *delimiter, bool reverse) { int i; int from = reverse ? field->size - 1 : 0; @@ -19,12 +19,12 @@ static void __eeprom_field_print_bin(const struct eeprom_field *field, printf(PRINT_FIELD_SEGMENT, field->name); for (i = from; i != to; reverse ? i-- : i++) - printf("%02x%s", field->buf[i], delimiter); + printf("%02x%s", fbuf[i], delimiter); - printf("%02x\n", field->buf[i]); + printf("%02x\n", fbuf[i]); } -static int __eeprom_field_update_bin(struct eeprom_field *field, +static int __eeprom_field_update_bin(struct eeprom_field *field, uchar *fbuf, const char *value, bool reverse) { int len = strlen(value); @@ -36,7 +36,7 @@ static int __eeprom_field_update_bin(struct eeprom_field *field, if (len > field->size * 2) return -1; - memset(field->buf, 0, field->size); + memset(fbuf, 0, field->size); /* i - string iterator, j - buf iterator */ for (j = 0; j < field->size; j++) { @@ -59,7 +59,7 @@ static int __eeprom_field_update_bin(struct eeprom_field *field, if (*endptr != '\0' || byte < 0) return -1; - field->buf[j] = byte; + fbuf[j] = byte; i = reverse ? i - 2 : i + 2; } @@ -67,7 +67,8 @@ static int __eeprom_field_update_bin(struct eeprom_field *field, } static int __eeprom_field_update_bin_delim(struct eeprom_field *field, - char *value, char *delimiter) + uchar *fbuf, char *value, + char *delimiter) { int count = 0; int i, val; @@ -92,7 +93,7 @@ static int __eeprom_field_update_bin_delim(struct eeprom_field *field, return -1; /* here we assume that each tok is no more than byte long */ - field->buf[i] = (unsigned char)val; + fbuf[i] = (unsigned char)val; tok = strtok(NULL, delimiter); } @@ -108,21 +109,46 @@ static int __eeprom_field_update_bin_delim(struct eeprom_field *field, * Field Name 0102030405060708090a * * @field: an initialized field to print + * @fbuf: field buffer */ -void eeprom_field_print_bin(const struct eeprom_field *field) +void eeprom_field_print_bin(const struct eeprom_field *field, uchar *fbuf) { - __eeprom_field_print_bin(field, "", false); + __eeprom_field_print_bin(field, fbuf, "", false); } /** * eeprom_field_update_bin() - Update field with new data in binary form * * @field: an initialized field + * @fbuf: field buffer * @value: a string of values (i.e. "10b234a") */ -int eeprom_field_update_bin(struct eeprom_field *field, char *value) +int eeprom_field_update_bin(struct eeprom_field *field, uchar *fbuf, + char *value) { - return __eeprom_field_update_bin(field, value, false); + return __eeprom_field_update_bin(field, fbuf, value, false); +} + +/** + * eeprom_field_read_bin() - Read field data in binary form + * + * @field: an initialized field + * @fbuf: field buffer + * @buf: read buffer + * @buf_size: read buffer size + */ +int eeprom_field_read_bin(const struct eeprom_field *field, uchar *fbuf, + uchar *buf, int buf_size) +{ + memset(buf, 0, buf_size); + if (field->size <= 0) + return 0; + if (field->size > buf_size) + memcpy(buf, fbuf, buf_size); + else + memcpy(buf, fbuf, field->size); + + return 0; } /** @@ -130,11 +156,13 @@ int eeprom_field_update_bin(struct eeprom_field *field, char *value) * binary form * * @field: an initialized field + * @fbuf: field buffer * @value: a space delimited string of byte values (i.e. "1 02 3 0x4") */ -int eeprom_field_update_reserved(struct eeprom_field *field, char *value) +int eeprom_field_update_reserved(struct eeprom_field *field, uchar *fbuf, + char *value) { - return __eeprom_field_update_bin_delim(field, value, " "); + return __eeprom_field_update_bin_delim(field, fbuf, value, " "); } /** @@ -150,10 +178,11 @@ int eeprom_field_update_reserved(struct eeprom_field *field, char *value) * Field Name 0a090807060504030201 * * @field: an initialized field to print + * @fbuf: field buffer */ -void eeprom_field_print_bin_rev(const struct eeprom_field *field) +void eeprom_field_print_bin_rev(const struct eeprom_field *field, uchar *fbuf) { - __eeprom_field_print_bin(field, "", true); + __eeprom_field_print_bin(field, fbuf, "", true); } /** @@ -165,11 +194,34 @@ void eeprom_field_print_bin_rev(const struct eeprom_field *field) * "3412" will be written to the field. * * @field: an initialized field + * @fbuf: field buffer * @value: a string of byte values */ -int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value) +int eeprom_field_update_bin_rev(struct eeprom_field *field, uchar *fbuf, + char *value) +{ + return __eeprom_field_update_bin(field, fbuf, value, true); +} + +/** + * eeprom_field_read_rev() - Read reversed binary data + * + * @field: an initialized field + * @fbuf: field buffer + * @buf: read buffer + * @buf_size: read buffer size + */ +int eeprom_field_read_rev(const struct eeprom_field *field, uchar *fbuf, + uchar *buf, int buf_size) { - return __eeprom_field_update_bin(field, value, true); + int i; + + memset(buf, 0, buf_size); + + for (i = field->size - 1; i >= 0; i--, buf++) + *buf = fbuf[i]; + + return 0; } /** @@ -181,10 +233,12 @@ int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value) * Field Name 01:02:03:04:05:06 * * @field: an initialized field to print + * @fbuf: field buffer */ -void eeprom_field_print_mac(const struct eeprom_field *field) +void eeprom_field_print_mac(const struct eeprom_field *field, uchar *fbuf) + { - __eeprom_field_print_bin(field, ":", false); + __eeprom_field_print_bin(field, fbuf, ":", false); } /** @@ -192,42 +246,47 @@ void eeprom_field_print_mac(const struct eeprom_field *field) * data * * @field: an initialized field + * @fbuf: field buffer * @value: a colon delimited string of byte values (i.e. "1:02:3:ff") */ -int eeprom_field_update_mac(struct eeprom_field *field, char *value) +int eeprom_field_update_mac(struct eeprom_field *field, uchar *fbuf, + char *value) { - return __eeprom_field_update_bin_delim(field, value, ":"); + return __eeprom_field_update_bin_delim(field, fbuf, value, ":"); } /** * eeprom_field_print_ascii() - print a field which contains ASCII data * @field: an initialized field to print + * @fbuf: field buffer */ -void eeprom_field_print_ascii(const struct eeprom_field *field) +void eeprom_field_print_ascii(const struct eeprom_field *field, uchar *fbuf) { char format[8]; sprintf(format, "%%.%ds\n", field->size); printf(PRINT_FIELD_SEGMENT, field->name); - printf(format, field->buf); + printf(format, fbuf); } /** * eeprom_field_update_ascii() - Update field with new data in ASCII form * @field: an initialized field + * @fbuf: field buffer * @value: the new string data * * Returns 0 on success, -1 of failure (new string too long). */ -int eeprom_field_update_ascii(struct eeprom_field *field, char *value) +int eeprom_field_update_ascii(struct eeprom_field *field, uchar *fbuf, + char *value) { if (strlen(value) >= field->size) { printf("%s: new data too long\n", field->name); return -1; } - strncpy((char *)field->buf, value, field->size - 1); - field->buf[field->size - 1] = '\0'; + strncpy((char *)fbuf, value, field->size - 1); + fbuf[field->size - 1] = '\0'; return 0; } @@ -241,8 +300,9 @@ int eeprom_field_update_ascii(struct eeprom_field *field, char *value) * Reserved fields (64 bytes) * * @field: an initialized field to print + * @fbuf: field buffer */ -void eeprom_field_print_reserved(const struct eeprom_field *field) +void eeprom_field_print_reserved(const struct eeprom_field *field, uchar *fbuf) { printf(PRINT_FIELD_SEGMENT, "Reserved fields\t"); printf("(%d bytes)\n", field->size); diff --git a/common/eeprom/eeprom_layout.c b/common/eeprom/eeprom_layout.c index 5a9be1da061..cc6dd39e016 100644 --- a/common/eeprom/eeprom_layout.c +++ b/common/eeprom/eeprom_layout.c @@ -14,8 +14,8 @@ #define NO_LAYOUT_FIELDS "Unknown layout. Dumping raw data\n" struct eeprom_field layout_unknown[1] = { - { NO_LAYOUT_FIELDS, 256, NULL, eeprom_field_print_bin, - eeprom_field_update_bin }, + { NO_LAYOUT_FIELDS, 256, eeprom_field_print_bin, + eeprom_field_update_bin }, }; /* @@ -51,9 +51,10 @@ static void eeprom_layout_print(const struct eeprom_layout *layout) { int i; struct eeprom_field *fields = layout->fields; + uchar *fbuf = layout->data; - for (i = 0; i < layout->num_of_fields; i++) - fields[i].print(&fields[i]); + for (i = 0; i < layout->num_of_fields; fbuf += fields[i++].size) + fields[i].print(&fields[i], fbuf); } /* @@ -69,6 +70,7 @@ static int eeprom_layout_update_field(struct eeprom_layout *layout, { int i, err; struct eeprom_field *fields = layout->fields; + uchar *fbuf = layout->data; if (new_data == NULL) return 0; @@ -76,12 +78,12 @@ static int eeprom_layout_update_field(struct eeprom_layout *layout, if (field_name == NULL) return -1; - for (i = 0; i < layout->num_of_fields; i++) { + for (i = 0; i < layout->num_of_fields; fbuf += fields[i++].size) { if (fields[i].name == RESERVED_FIELDS || strcmp(fields[i].name, field_name)) continue; - err = fields[i].update(&fields[i], new_data); + err = fields[i].update(&fields[i], fbuf, new_data); if (err) printf("Invalid data for field %s\n", field_name); @@ -93,6 +95,42 @@ static int eeprom_layout_update_field(struct eeprom_layout *layout, return -1; } +/* + * eeprom_layout_read_field() - read a single field from the layout data + * @layout: A pointer to an existing struct layout. + * @field_name: The name of the field to update. + * @buf: Read data buffer. + * @buf_size: Read data buffer size. + * + * Returns: 0 on success, negative error value on failure. + */ +static int eeprom_layout_read_field(struct eeprom_layout *layout, + char *field_name, uchar *buf, int buf_size) +{ + int i, err; + struct eeprom_field *fields = layout->fields; + uchar *fbuf = layout->data; + + if ((field_name == NULL) || (buf == NULL) || (buf_size <= 0)) + return -1; + + for (i = 0; i < layout->num_of_fields; fbuf += fields[i++].size) { + if (fields[i].name == RESERVED_FIELDS || + strcmp(fields[i].name, field_name)) + continue; + + err = fields[i].read(&fields[i], fbuf, buf, buf_size); + if (err) + printf("Field %s, read error\n", field_name); + + return err; + } + + printf("No such field '%s'\n", field_name); + + return -1; +} + /* * eeprom_layout_setup() - setup layout struct with the layout data and * metadata as dictated by layout_version @@ -104,8 +142,6 @@ static int eeprom_layout_update_field(struct eeprom_layout *layout, void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf, unsigned int buf_size, int layout_version) { - int i; - if (layout_version == LAYOUT_VERSION_AUTODETECT) layout->layout_version = eeprom_layout_detect(buf); else @@ -113,12 +149,8 @@ void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf, eeprom_layout_assign(layout, layout_version); layout->data = buf; - for (i = 0; i < layout->num_of_fields; i++) { - layout->fields[i].buf = buf; - buf += layout->fields[i].size; - } - layout->data_size = buf_size; layout->print = eeprom_layout_print; layout->update = eeprom_layout_update_field; + layout->read = eeprom_layout_read_field; } diff --git a/common/image-android.c b/common/image-android.c index d07b0e0f09b..fb32c9482c5 100644 --- a/common/image-android.c +++ b/common/image-android.c @@ -1,6 +1,9 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (c) 2011 Sebastian Andrzej Siewior + * + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP */ #include @@ -13,8 +16,17 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include +#include #define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000 +#define COMMANDLINE_LENGTH 2048 static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1]; @@ -44,6 +56,151 @@ static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr) return hdr->kernel_addr; } +static void append_kernel_cmdline(char *commandline) +{ + char newbootargs[512] = {0}; + extern boot_metric metrics; + + /* Add 'bootargs_ram_capacity' to hold the parameters based on different ram capacity */ + char *bootargs_ram_capacity = env_get("bootargs_ram_capacity"); + if (bootargs_ram_capacity) { + strncat(commandline, " ", COMMANDLINE_LENGTH - strlen(commandline)); + strncat(commandline, bootargs_ram_capacity, + COMMANDLINE_LENGTH - strlen(commandline)); + } + +#ifdef CONFIG_SERIAL_TAG + struct tag_serialnr serialnr; + get_board_serial(&serialnr); + + sprintf(newbootargs, + " androidboot.serialno=%08x%08x", + serialnr.high, + serialnr.low); + strncat(commandline, newbootargs, COMMANDLINE_LENGTH - strlen(commandline)); + + if (serialnr.high + serialnr.low != 0) { + char bd_addr[16]={0}; + sprintf(bd_addr, + "%08x%08x", + serialnr.high, + serialnr.low); + sprintf(newbootargs, + " androidboot.btmacaddr=%c%c:%c%c:%c%c:%c%c:%c%c:%c%c", + bd_addr[0],bd_addr[1],bd_addr[2],bd_addr[3],bd_addr[4],bd_addr[5], + bd_addr[6],bd_addr[7],bd_addr[8],bd_addr[9],bd_addr[10],bd_addr[11]); + } else { + /* Some boards have serial number as all zeros (imx8mp), + * hard code the bt mac address for such case. */ + sprintf(newbootargs, " androidboot.btmacaddr=22:22:67:C6:69:73"); + } + + strncat(commandline, newbootargs, COMMANDLINE_LENGTH - strlen(commandline)); +#endif + + /* append soc type into bootargs */ + char *soc_type = env_get("soc_type"); + if (soc_type) { + sprintf(newbootargs, + " androidboot.soc_type=%s", + soc_type); + strncat(commandline, newbootargs, COMMANDLINE_LENGTH - strlen(commandline)); + } + /* append soc rev into bootargs */ + char *soc_rev = env_get("soc_rev"); + if (soc_rev) { + sprintf(newbootargs, + " androidboot.soc_rev=%s", + soc_rev); + strncat(commandline, newbootargs, COMMANDLINE_LENGTH - strlen(commandline)); + } + + sprintf(newbootargs, + " androidboot.boot_device_root=mmcblk%d", mmc_map_to_kernel_blk(mmc_get_env_dev())); + strncat(commandline, newbootargs, COMMANDLINE_LENGTH - strlen(commandline)); + + /* boot metric variables */ + metrics.ble_1 = get_timer(0); + sprintf(newbootargs, + " androidboot.boottime=1BLL:%d,1BLE:%d,KL:%d,KD:%d,AVB:%d,ODT:%d,SW:%d", + metrics.bll_1, metrics.ble_1, metrics.kl, metrics.kd, metrics.avb, + metrics.odt, metrics.sw); + strncat(commandline, newbootargs, COMMANDLINE_LENGTH - strlen(commandline)); + +#if defined(CONFIG_ARCH_MX6) || defined(CONFIG_ARCH_MX7) || \ + defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8M) + char cause[18]; + + memset(cause, '\0', sizeof(cause)); + get_reboot_reason(cause); + if (strstr(cause, "POR")) + sprintf(newbootargs," androidboot.bootreason=cold,powerkey"); + else if (strstr(cause, "WDOG") || strstr(cause, "WDG")) + sprintf(newbootargs," androidboot.bootreason=watchdog"); + else + sprintf(newbootargs," androidboot.bootreason=reboot"); +#else + sprintf(newbootargs," androidboot.bootreason=reboot"); +#endif + strncat(commandline, newbootargs, COMMANDLINE_LENGTH - strlen(commandline)); + +#ifdef CONFIG_AVB_SUPPORT + /* secondary cmdline added by avb */ + char *bootargs_sec = env_get("bootargs_sec"); + if (bootargs_sec) { + strncat(commandline, " ", COMMANDLINE_LENGTH - strlen(commandline)); + strncat(commandline, bootargs_sec, COMMANDLINE_LENGTH - strlen(commandline)); + } +#endif +#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT + /* Normal boot: + * cmdline to bypass ramdisk in boot.img, but use the system.img + * Recovery boot: + * Use the ramdisk in boot.img + */ + char *bootargs_3rd = env_get("bootargs_3rd"); + if (bootargs_3rd) { + strncat(commandline, " ", COMMANDLINE_LENGTH - strlen(commandline)); + strncat(commandline, bootargs_3rd, COMMANDLINE_LENGTH - strlen(commandline)); + } +#endif + + /* VTS need this commandline to verify fdt overlay. Pass the + * dtb index as "0" here since we only have one dtb in dtbo + * partition and haven't enabled the dtb overlay. + */ +#if defined(CONFIG_ANDROID_SUPPORT) || defined(CONFIG_ANDROID_AUTO_SUPPORT) + sprintf(newbootargs," androidboot.dtbo_idx=0"); + strncat(commandline, newbootargs, COMMANDLINE_LENGTH - strlen(commandline)); +#endif + + char *keystore = env_get("keystore"); + if ((keystore == NULL) || strncmp(keystore, "trusty", sizeof("trusty"))) { + char *bootargs_trusty = "androidboot.keystore=software"; + strncat(commandline, " ", COMMANDLINE_LENGTH - strlen(commandline)); + strncat(commandline, bootargs_trusty, COMMANDLINE_LENGTH - strlen(commandline)); + } else { + char *bootargs_trusty = "androidboot.keystore=trusty"; + strncat(commandline, " ", COMMANDLINE_LENGTH - strlen(commandline)); + strncat(commandline, bootargs_trusty, COMMANDLINE_LENGTH - strlen(commandline)); + } + +#ifdef CONFIG_APPEND_BOOTARGS + /* Add 'append_bootargs' to hold some paramemters which need to be appended + * to bootargs */ + char *append_bootargs = env_get("append_bootargs"); + if (append_bootargs) { + if (strlen(append_bootargs) + 2 > + (COMMANDLINE_LENGTH - strlen(commandline))) { + printf("The 'append_bootargs' is too long to be appended to bootargs\n"); + } else { + strncat(commandline, " ", COMMANDLINE_LENGTH - strlen(commandline)); + strncat(commandline, append_bootargs, COMMANDLINE_LENGTH - strlen(commandline)); + } + } +#endif +} + /** * android_image_get_kernel() - processes kernel part of Android boot images * @hdr: Pointer to image header, which is at the start @@ -79,31 +236,41 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, printf("Kernel load addr 0x%08x size %u KiB\n", kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024)); - int len = 0; - if (*hdr->cmdline) { - printf("Kernel command line: %s\n", hdr->cmdline); - len += strlen(hdr->cmdline); - } - + char commandline[COMMANDLINE_LENGTH] = {0}; + int offset; char *bootargs = env_get("bootargs"); - if (bootargs) - len += strlen(bootargs); - - char *newbootargs = malloc(len + 2); - if (!newbootargs) { - puts("Error: malloc in android_image_get_kernel failed!\n"); - return -ENOMEM; - } - *newbootargs = '\0'; if (bootargs) { - strcpy(newbootargs, bootargs); - strcat(newbootargs, " "); + if (strlen(bootargs) + 1 > sizeof(commandline)) { + printf("bootargs is too long!\n"); + return -1; + } + else + strncpy(commandline, bootargs, sizeof(commandline) - 1); + } else { + offset = fdt_path_offset(gd->fdt_blob, "/chosen"); + if (offset > 0) { + bootargs = (char *)fdt_getprop(gd->fdt_blob, offset, + "bootargs", NULL); + if (bootargs) + sprintf(commandline, "%s ", bootargs); + } + + if (*hdr->cmdline) { + if (strlen(hdr->cmdline) + 1 > + COMMANDLINE_LENGTH - strlen(commandline)) { + printf("cmdline in bootimg is too long!\n"); + return -1; + } + else + strncat(commandline, hdr->cmdline, COMMANDLINE_LENGTH - strlen(commandline)); + } } - if (*hdr->cmdline) - strcat(newbootargs, hdr->cmdline); - env_set("bootargs", newbootargs); + append_kernel_cmdline(commandline); + + debug("Kernel command line: %s\n", commandline); + env_set("bootargs", commandline); if (os_data) { if (image_get_magic(ihdr) == IH_MAGIC) { @@ -119,6 +286,84 @@ int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, else *os_len = hdr->kernel_size; } + + return 0; +} + +/** + * android_image_get_kernel() - processes kernel part of Android boot images + * @hdr: Pointer to boot image header, which is at the start + * of the image. + * @vendor_hdr: Pointer to vendor_boot image header, which is at the start + * of the image. + * This function appends the kernel command line to the bootargs env variable. + * + * Return: Zero on success, otherwise on failure. + */ +int android_image_get_kernel_v3(const struct boot_img_hdr_v3 *hdr, + const struct vendor_boot_img_hdr_v3 *vendor_hdr) +{ + u32 kernel_addr = vendor_hdr->kernel_addr; + + /* + * Not all Android tools use the id field for signing the image with + * sha1 (or anything) so we don't check it. It is not obvious that the + * string is null terminated so we take care of this. + */ + strncpy(andr_tmp_str, (char *)(vendor_hdr->name), ANDR_VENDOR_BOOT_NAME_SIZE); + andr_tmp_str[ANDR_VENDOR_BOOT_NAME_SIZE] = '\0'; + if (strlen(andr_tmp_str)) + printf("Android's image name: %s\n", andr_tmp_str); + + printf("Kernel load addr 0x%08x size %u KiB\n", + kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024)); + + char commandline[COMMANDLINE_LENGTH] = {0}; + int offset; + char *bootargs = env_get("bootargs"); + + if (bootargs) { + if (strlen(bootargs) + 1 > sizeof(commandline)) { + printf("bootargs is too long!\n"); + return -1; + } + else + strncpy(commandline, bootargs, sizeof(commandline) - 1); + } else { + offset = fdt_path_offset(gd->fdt_blob, "/chosen"); + if (offset > 0) { + bootargs = (char *)fdt_getprop(gd->fdt_blob, offset, + "bootargs", NULL); + if (bootargs) + sprintf(commandline, "%s ", bootargs); + } + + if (*vendor_hdr->cmdline) { + if (strlen((char *)vendor_hdr->cmdline) + 1 > + COMMANDLINE_LENGTH - strlen(commandline)) { + printf("cmdline in bootimg is too long!\n"); + return -1; + } + else + strncat(commandline, (char *)(vendor_hdr->cmdline), COMMANDLINE_LENGTH - strlen(commandline)); + } + + if (*hdr->cmdline) { + if (strlen((char *)hdr->cmdline) + 1 > + COMMANDLINE_LENGTH - strlen(commandline)) { + printf("cmdline in bootimg is too long!\n"); + return -1; + } + else + strncat(commandline, (char *)hdr->cmdline, COMMANDLINE_LENGTH - strlen(commandline)); + } + } + + append_kernel_cmdline(commandline); + + debug("Kernel command line: %s\n", commandline); + env_set("bootargs", commandline); + return 0; } @@ -127,6 +372,13 @@ int android_image_check_header(const struct andr_img_hdr *hdr) return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE); } +int android_image_check_header_v3(const struct boot_img_hdr_v3 *hdr, + const struct vendor_boot_img_hdr_v3 *vendor_hdr) +{ + return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE) || + memcmp(ANDR_VENDOR_BOOT_MAGIC, vendor_hdr->magic, ANDR_VENDOR_BOOT_MAGIC_SIZE); +} + ulong android_image_get_end(const struct andr_img_hdr *hdr) { ulong end; @@ -537,3 +789,44 @@ bool android_image_print_dtb_contents(ulong hdr_addr) return true; } #endif + +#define ARM64_IMAGE_MAGIC 0x644d5241 +bool image_arm64(void *images) +{ + struct header_image *ih; + + ih = (struct header_image *)images; + debug("image magic: %x\n", ih->magic); + if (ih->magic == le32_to_cpu(ARM64_IMAGE_MAGIC)) + return true; + return false; +} + +uint32_t kernel_size(void *images) +{ + struct header_image *ih; + uint32_t image_size; + + ih = (struct header_image *)images; + image_size = le64_to_cpu(ih->image_size); + + return image_size; +} + +ulong kernel_relocate_addr(ulong images) +{ + struct header_image *ih; + ulong relocated_addr, text_offset; + + ih = (struct header_image *)images; + text_offset = le64_to_cpu(ih->text_offset); + + if (le64_to_cpu(ih->res1) & BIT(3)) + relocated_addr = images - text_offset; + else + relocated_addr = gd->bd->bi_dram[0].start; + + relocated_addr = ALIGN(relocated_addr, SZ_2M) + text_offset; + + return relocated_addr; +} diff --git a/common/image-fdt.c b/common/image-fdt.c index a287b663925..6bd3c3930d1 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -79,7 +79,7 @@ static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr, { long ret; - ret = lmb_reserve(lmb, addr, size); + ret = lmb_reserve_overlap(lmb, addr, size); if (ret >= 0) { debug(" reserving fdt memory region: addr=%llx size=%llx\n", (unsigned long long)addr, (unsigned long long)size); diff --git a/common/image-fit.c b/common/image-fit.c index 94501b10716..445d5adbfe4 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1371,19 +1371,10 @@ int fit_image_verify_with_data(const void *fit, int image_noffset, */ int fit_image_verify(const void *fit, int image_noffset) { - const char *name = fit_get_name(fit, image_noffset, NULL); const void *data; size_t size; char *err_msg = ""; - if (strchr(name, '@')) { - /* - * We don't support this since libfdt considers names with the - * name root but different @ suffix to be equal - */ - err_msg = "Node name contains @"; - goto err; - } /* Get image data and data length */ if (fit_image_get_data_and_size(fit, image_noffset, &data, &size)) { err_msg = "Can't get image data/size"; diff --git a/common/lcd.c b/common/lcd.c index ab5614ad0e3..4b17a23903e 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -39,11 +39,6 @@ #define CONFIG_LCD_ALIGNMENT PAGE_SIZE #endif -#if (LCD_BPP != LCD_COLOR8) && (LCD_BPP != LCD_COLOR16) && \ - (LCD_BPP != LCD_COLOR32) -#error Unsupported LCD BPP. -#endif - DECLARE_GLOBAL_DATA_PTR; static int lcd_init(void *lcdbase); @@ -175,10 +170,13 @@ int drv_lcd_init(void) void lcd_clear(void) { - int bg_color; __maybe_unused ulong addr; static int do_splash = 1; -#if LCD_BPP == LCD_COLOR8 +#if LCD_BPP == LCD_MONOCHROME + /* Setting the palette */ + lcd_initcolregs(); + +#elif LCD_BPP == LCD_COLOR8 /* Setting the palette */ lcd_setcolreg(CONSOLE_COLOR_BLACK, 0, 0, 0); lcd_setcolreg(CONSOLE_COLOR_RED, 0xFF, 0, 0); @@ -194,11 +192,9 @@ void lcd_clear(void) #ifndef CONFIG_SYS_WHITE_ON_BLACK lcd_setfgcolor(CONSOLE_COLOR_BLACK); lcd_setbgcolor(CONSOLE_COLOR_WHITE); - bg_color = CONSOLE_COLOR_WHITE; #else lcd_setfgcolor(CONSOLE_COLOR_WHITE); lcd_setbgcolor(CONSOLE_COLOR_BLACK); - bg_color = CONSOLE_COLOR_BLACK; #endif /* CONFIG_SYS_WHITE_ON_BLACK */ #ifdef LCD_TEST_PATTERN @@ -206,14 +202,15 @@ void lcd_clear(void) #else /* set framebuffer to background color */ #if (LCD_BPP != LCD_COLOR32) - memset((char *)lcd_base, bg_color, lcd_line_length * panel_info.vl_row); + memset((char *)lcd_base, COLOR_MASK(lcd_getbgcolor()), + lcd_line_length * panel_info.vl_row); #else u32 *ppix = lcd_base; u32 i; for (i = 0; i < (lcd_line_length * panel_info.vl_row)/NBYTES(panel_info.vl_bpix); i++) { - *ppix++ = bg_color; + *ppix++ = COLOR_MASK(lcd_getbgcolor()); } #endif #endif @@ -286,7 +283,7 @@ ulong lcd_setmem(ulong addr) ulong size; int line_length; - debug("LCD panel info: %d x %d, %d bit/pix\n", panel_info.vl_col, + debug("LCD panel info: %lu x %lu, %d bit/pix\n", panel_info.vl_col, panel_info.vl_row, NBITS(panel_info.vl_bpix)); size = lcd_get_size(&line_length); diff --git a/common/lcd_console.c b/common/lcd_console.c index 1a246c492ce..a70d44d2539 100644 --- a/common/lcd_console.c +++ b/common/lcd_console.c @@ -48,17 +48,34 @@ static void lcd_putc_xy0(struct console_t *pcons, ushort x, ushort y, char c) { int fg_color = lcd_getfgcolor(); int bg_color = lcd_getbgcolor(); - int i, row; + int row; +#if LCD_BPP == LCD_MONOCHROME + ushort off = x * (1 << LCD_BPP) % 8; +#else + int i; +#endif + fbptr_t *dst = (fbptr_t *)pcons->fbbase + y * pcons->lcdsizex + x; for (row = 0; row < VIDEO_FONT_HEIGHT; row++) { uchar bits = video_fontdata[c * VIDEO_FONT_HEIGHT + row]; +#if LCD_BPP == LCD_MONOCHROME + uchar rest = *dst & -(1 << (8 - off)); + uchar sym; + + sym = (COLOR_MASK(fg_color) & bits) | + (COLOR_MASK(bg_color) & ~bits); + *dst++ = rest | (sym >> off); + rest = sym << (8 - off); + *dst = rest | (*dst & ((1 << (8 - off)) - 1)); +#else /* LCD_BPP == LCD_COLOR8 or LCD_COLOR16 or LCD_COLOR32 */ for (i = 0; i < VIDEO_FONT_WIDTH; ++i) { *dst++ = (bits & 0x80) ? fg_color : bg_color; bits <<= 1; } +#endif dst += (pcons->lcdsizex - VIDEO_FONT_WIDTH); } } @@ -116,7 +133,7 @@ static inline void console_newline(void) for (i = 0; i < cons.rows-rows; i++) cons.fp_console_moverow(&cons, i, i+rows); for (i = 0; i < rows; i++) - cons.fp_console_setrow(&cons, cons.rows-i-1, bg_color); + cons.fp_console_setrow(&cons, cons.rows-i-1, COLOR_MASK(bg_color)); cons.curr_row -= rows; } lcd_sync(); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 774541c02bc..6c8bbcbe4cf 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -195,7 +195,7 @@ config SPL_BOOTCOUNT_LIMIT config SPL_RAW_IMAGE_SUPPORT bool "Support SPL loading and booting of RAW images" - default n if (ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT)) + default n if ((ARCH_MX6 && (SPL_MMC_SUPPORT || SPL_SATA_SUPPORT)) || ARCH_IMX8 || ARCH_IMX8M) default y if !TI_SECURE_DEVICE help SPL will support loading and booting a RAW image when this option diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 75c8ff065bb..1442e0e35da 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -66,6 +66,10 @@ static int find_node_from_desc(const void *fit, int node, const char *str) return -ENOENT; } +#ifdef CONFIG_DUAL_BOOTLOADER +extern int spl_fit_get_rbindex(const void *fit); +#endif + /** * spl_fit_get_image_name(): By using the matching configuration subnode, * retrieve the name of an image, specified by a property name and an index @@ -213,6 +217,15 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, return (data_size + info->bl_len - 1) / info->bl_len; } +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_IMX_TRUSTY_OS) +__weak int get_tee_load(ulong *load) +{ + /* default return ok */ + return 0; +} + +#endif + /** * spl_load_fit_image(): load the image described in a certain FIT node * @info: points to information about the device to load data from @@ -261,6 +274,21 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, if (fit_image_get_load(fit, node, &load_addr)) load_addr = image_info->load_addr; +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_IMX_TRUSTY_OS) + char *desc = NULL; + + if (fit_get_desc(fit, node, &desc)) { + printf("can't found node description!\n"); + return -ENOENT; + } else if (!strncmp(desc, "TEE firmware", + strlen("TEE firmware"))) { + if (get_tee_load(&load_addr)) { + printf("Failed to get TEE load address!\n"); + return -ENOENT; + } + } +#endif + if (!fit_image_get_data_position(fit, node, &offset)) { external_data = true; } else if (!fit_image_get_data_offset(fit, node, &offset)) { @@ -510,6 +538,11 @@ static void *spl_get_fit_load_buffer(size_t size) return buf; } +__weak void* board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) +{ + return spl_get_fit_load_buffer(sectors * bl_len); +} + /* * Weak default function to allow customizing SPL fit loading for load-only * use cases by allowing to skip the parsing/processing of the FIT contents @@ -545,7 +578,7 @@ static int spl_simple_fit_read(struct spl_fit_info *ctx, * For FIT with external data, data is not loaded in this step. */ sectors = get_aligned_image_size(info, size, 0); - buf = spl_get_fit_load_buffer(sectors * info->bl_len); + buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len); count = info->read(info, sector, sectors, buf); ctx->fit = buf; @@ -603,6 +636,16 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, if (ret < 0) return ret; +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_IMX_TRUSTY_OS) + int rbindex; + rbindex = spl_fit_get_rbindex(ctx.fit); + if (rbindex < 0) { + printf("Error! Can't get rollback index!\n"); + return -1; + } else + spl_image->rbindex = rbindex; +#endif + #ifdef CONFIG_SPL_FPGA node = spl_fit_get_image_node(&ctx, "fpga", 0); if (node >= 0) { @@ -737,7 +780,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, spl_image->flags |= SPL_FIT_FOUND; - if (IS_ENABLED(CONFIG_IMX_HAB)) + if (IS_ENABLED(CONFIG_IMX_HAB) && !(spl_image->flags & SPL_FIT_BYPASS_POST_LOAD)) board_spl_fit_post_load(ctx.fit); return 0; diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index add2785b4e3..d3ce1efc5f8 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -43,7 +43,7 @@ static int mmc_load_legacy(struct spl_image_info *spl_image, struct mmc *mmc, return 0; } -static ulong h_spl_load_read(struct spl_load_info *load, ulong sector, +ulong h_spl_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { struct mmc *mmc = load->dev; @@ -61,6 +61,16 @@ static __maybe_unused unsigned long spl_mmc_raw_uboot_offset(int part) return 0; } +#if defined(CONFIG_DUAL_BOOTLOADER) +int mmc_load_image_raw_sector_dual_uboot(struct spl_image_info *spl_image, + struct mmc *mmc); +#endif + +int __weak mmc_image_load_late(struct mmc *mmc) +{ + return 0; +} + static __maybe_unused int mmc_load_image_raw_sector(struct spl_image_info *spl_image, struct mmc *mmc, unsigned long sector) @@ -113,7 +123,8 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, return -1; } - return 0; + ret = mmc_image_load_late(mmc); + return ret; } static int spl_mmc_get_device_index(u32 boot_device) @@ -180,7 +191,7 @@ static int mmc_load_image_raw_partition(struct spl_image_info *spl_image, err = part_get_info(mmc_get_blk_desc(mmc), type_part, &info); if (err) continue; - if (info.sys_ind == + if (info.sys_ind == CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE) { partition = type_part; break; @@ -324,6 +335,34 @@ unsigned long __weak spl_mmc_get_uboot_raw_sector(struct mmc *mmc, return raw_sect; } +int __weak spl_mmc_emmc_boot_partition(struct mmc *mmc) +{ + int part = 0; + +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION + part = CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION; +#else + /* + * We need to check what the partition is configured to. + * 1 and 2 match up to boot0 / boot1 and 7 is user data + * which is the first physical partition (0). + */ +#ifdef CONFIG_DUAL_BOOTLOADER + /* Bootloader is stored in eMMC user partition for + * dual bootloader. + */ + part = 0; +#else + part = (mmc->part_config >> 3) & PART_ACCESS_MASK; + + if (part == 7) + part = 0; +#endif +#endif + + return part; +} + int spl_mmc_load(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, const char *filename, @@ -355,19 +394,7 @@ int spl_mmc_load(struct spl_image_info *spl_image, err = -EINVAL; switch (boot_mode) { case MMCSD_MODE_EMMCBOOT: -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION - part = CONFIG_SYS_MMCSD_RAW_MODE_EMMC_BOOT_PARTITION; -#else - /* - * We need to check what the partition is configured to. - * 1 and 2 match up to boot0 / boot1 and 7 is user data - * which is the first physical partition (0). - */ - part = (mmc->part_config >> 3) & PART_ACCESS_MASK; - - if (part == 7) - part = 0; -#endif + part = spl_mmc_emmc_boot_partition(mmc); if (CONFIG_IS_ENABLED(MMC_TINY)) err = mmc_switch_part(mmc, part); @@ -390,7 +417,9 @@ int spl_mmc_load(struct spl_image_info *spl_image, return err; } +#ifndef CONFIG_DUAL_BOOTLOADER raw_sect = spl_mmc_get_uboot_raw_sector(mmc, raw_sect); +#endif #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION err = mmc_load_image_raw_partition(spl_image, mmc, raw_part, @@ -399,8 +428,12 @@ int spl_mmc_load(struct spl_image_info *spl_image, return err; #endif #ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#ifdef CONFIG_DUAL_BOOTLOADER + err = mmc_load_image_raw_sector_dual_uboot(spl_image, mmc); +#else err = mmc_load_image_raw_sector(spl_image, mmc, raw_sect + spl_mmc_raw_uboot_offset(part)); +#endif if (!err) return err; #endif diff --git a/common/spl/spl_sdp.c b/common/spl/spl_sdp.c index ae9c09883a4..3493ae674d9 100644 --- a/common/spl/spl_sdp.c +++ b/common/spl/spl_sdp.c @@ -15,11 +15,14 @@ static int spl_sdp_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { int ret; - const int controller_index = CONFIG_SPL_SDP_USB_DEV; + int index; + int controller_index = CONFIG_SPL_SDP_USB_DEV; - usb_gadget_initialize(controller_index); + index = board_usb_gadget_port_auto(); + if (index >= 0) + controller_index = index; - board_usb_init(0, USB_INIT_DEVICE); + usb_gadget_initialize(controller_index); g_dnl_clear_detach(); ret = g_dnl_register("usb_dnl_sdp"); diff --git a/common/stdio.c b/common/stdio.c index d4acc5256c1..9575e99e0df 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -18,6 +18,8 @@ #include #include #include +#include + #include #include #include @@ -340,6 +342,9 @@ int stdio_add_devices(void) i2c_init_all(); #endif if (IS_ENABLED(CONFIG_DM_VIDEO)) { +#ifdef CONFIG_VIDEO_LINK + video_link_init(); +#endif /* * If the console setting is not in environment variables then * console_init_r() will not be calling iomux_doenv() (which diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index bdfd0ef71b7..54bcc2f0821 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -66,6 +67,8 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 9094327edea..853a3d65ae1 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -63,6 +64,8 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig index ef097bab897..bca800f5ae8 100644 --- a/configs/T1042D4RDB_SECURE_BOOT_defconfig +++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig @@ -2,8 +2,10 @@ CONFIG_PPC=y CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_NXP_ESBC=y +CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_MPC85xx=y CONFIG_TARGET_T1042D4RDB=y +CONFIG_MPC85XX_HAVE_RESET_VECTOR=y # CONFIG_SYS_MALLOC_F is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y @@ -17,6 +19,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SF=y @@ -29,6 +32,7 @@ CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)" +CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_DM=y CONFIG_FSL_ESDHC=y @@ -45,8 +49,9 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y -CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y @@ -60,4 +65,3 @@ CONFIG_SYS_NUM_ADDR_MAP=64 CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index bc59866b551..cef5295748a 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -33,6 +33,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -65,6 +66,8 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index f968a448e92..85e2beab020 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -18,6 +18,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -51,6 +52,8 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 543d34e2498..3bb74335bb4 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -70,6 +71,8 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_SYS_CORTINA_FW_IN_NAND=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index d947846e645..bcd67a05764 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -31,6 +31,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -67,6 +68,8 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_SYS_CORTINA_FW_IN_MMC=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 6f7b083bc62..198e926c32f 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -33,6 +33,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -69,6 +70,8 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 9dd01bbe50a..12aaccd1d50 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -18,6 +18,7 @@ CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -54,6 +55,8 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_MII=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 61670fa3d14..2def90140f2 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -28,6 +28,7 @@ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -59,6 +60,8 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_CORTINA=y CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 2c8a2f0ef27..8a0c122833f 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -15,6 +15,7 @@ CONFIG_BOARD_EARLY_INIT_R=y CONFIG_HUSH_PARSER=y CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y @@ -47,6 +48,8 @@ CONFIG_PHYLIB_10G=y CONFIG_PHY_CORTINA=y CONFIG_PHY_TERANETICS=y CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y diff --git a/configs/imx8dx_17x17_val_defconfig b/configs/imx8dx_17x17_val_defconfig new file mode 100644 index 00000000000..6d45bf9091c --- /dev/null +++ b/configs/imx8dx_17x17_val_defconfig @@ -0,0 +1,153 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg" +CONFIG_TARGET_IMX8X_17X17_VAL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-17x17-val" +CONFIG_DEFAULT_FDT_FILE="imx8dx-17x17-val.dtb" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_USB_CDNS3=y +# CONFIG_USB_CDNS3_GADGET=y +# CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_USB_PORT_AUTO=y diff --git a/configs/imx8dx_mek_android_defconfig b/configs/imx8dx_mek_android_defconfig new file mode 100644 index 00000000000..6cde1517ddb --- /dev/null +++ b/configs/imx8dx_mek_android_defconfig @@ -0,0 +1,183 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8DX_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y diff --git a/configs/imx8dx_mek_android_uuu_defconfig b/configs/imx8dx_mek_android_uuu_defconfig new file mode 100644 index 00000000000..dae6b83a2fc --- /dev/null +++ b/configs/imx8dx_mek_android_uuu_defconfig @@ -0,0 +1,180 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8DX_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n diff --git a/configs/imx8dx_mek_defconfig b/configs/imx8dx_mek_defconfig new file mode 100644 index 00000000000..354b9b23c6f --- /dev/null +++ b/configs/imx8dx_mek_defconfig @@ -0,0 +1,176 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8DX_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8dx_mek_fspi_defconfig b/configs/imx8dx_mek_fspi_defconfig new file mode 100644 index 00000000000..2b32268e413 --- /dev/null +++ b/configs/imx8dx_mek_fspi_defconfig @@ -0,0 +1,181 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8DX_MEK=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_SPI_FLASH_TINY=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000 +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8dxl_ddr3_evk_defconfig b/configs/imx8dxl_ddr3_evk_defconfig new file mode 100644 index 00000000000..0ae61f24a13 --- /dev/null +++ b/configs/imx8dxl_ddr3_evk_defconfig @@ -0,0 +1,163 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg" +CONFIG_TARGET_IMX8DXL_DDR3_EVK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-ddr3-evk" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8dxl_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_EHCI_HCD=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_DM_USB=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 +CONFIG_USB_PORT_AUTO=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8dxl_ddr3_evk_nand_defconfig b/configs/imx8dxl_ddr3_evk_nand_defconfig new file mode 100644 index 00000000000..956ad0cc34b --- /dev/null +++ b/configs/imx8dxl_ddr3_evk_nand_defconfig @@ -0,0 +1,172 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x7800000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg" +CONFIG_TARGET_IMX8DXL_DDR3_EVK=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-ddr3-evk" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8dxl_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_NAND=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_EHCI_HCD=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_NAND_BOOT=y +CONFIG_CMD_UBI=y + +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_DM_USB=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 +CONFIG_USB_PORT_AUTO=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8dxl_evk_defconfig b/configs/imx8dxl_evk_defconfig new file mode 100644 index 00000000000..c25a56238af --- /dev/null +++ b/configs/imx8dxl_evk_defconfig @@ -0,0 +1,166 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg" +CONFIG_TARGET_IMX8DXL_EVK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-evk" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8dxl_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_FSL_LPSPI=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_EHCI_HCD=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_DM_USB=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 +CONFIG_USB_PORT_AUTO=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8dxl_evk_fspi_defconfig b/configs/imx8dxl_evk_fspi_defconfig new file mode 100644 index 00000000000..14ce5bbf55a --- /dev/null +++ b/configs/imx8dxl_evk_fspi_defconfig @@ -0,0 +1,170 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg" +CONFIG_TARGET_IMX8DXL_EVK=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_SPI_FLASH_TINY=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000 +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-evk" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8dxl_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_MII=y + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_EHCI_HCD=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_DM_USB=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 +CONFIG_USB_PORT_AUTO=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8dxl_evk_lcd_defconfig b/configs/imx8dxl_evk_lcd_defconfig new file mode 100644 index 00000000000..525a05734de --- /dev/null +++ b/configs/imx8dxl_evk_lcd_defconfig @@ -0,0 +1,169 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_evk/uboot-container.cfg" +CONFIG_TARGET_IMX8DXL_EVK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-evk-lcdif" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8dxl_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_EHCI_HCD=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_DM_USB=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 +CONFIG_USB_PORT_AUTO=y + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y \ No newline at end of file diff --git a/configs/imx8dxl_phantom_mek_defconfig b/configs/imx8dxl_phantom_mek_defconfig new file mode 100644 index 00000000000..e084844cc14 --- /dev/null +++ b/configs/imx8dxl_phantom_mek_defconfig @@ -0,0 +1,165 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_phantom_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8DXL_PHANTOM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-phantom-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8dxl_phantom_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_EHCI_HCD=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_USB_CDNS3=y +# CONFIG_USB_CDNS3_GADGET=y +# CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_DM_USB=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8dxl_phantom_mek_fspi_defconfig b/configs/imx8dxl_phantom_mek_fspi_defconfig new file mode 100644 index 00000000000..0bece368452 --- /dev/null +++ b/configs/imx8dxl_phantom_mek_fspi_defconfig @@ -0,0 +1,171 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8dxl_phantom_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8DXL_PHANTOM_MEK=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_SPI_FLASH_TINY=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000 +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dxl-phantom-mek" +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8dxl_phantom_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_EHCI_HCD=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_USB_CDNS3=y +# CONFIG_USB_CDNS3_GADGET=y +# CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_DM_USB=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8mm_ddr3l_val_defconfig b/configs/imx8mm_ddr3l_val_defconfig new file mode 100644 index 00000000000..fe1bd9c3d87 --- /dev/null +++ b/configs/imx8mm_ddr3l_val_defconfig @@ -0,0 +1,132 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_DDR3L_VAL=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr3l-val" +CONFIG_CSF_SIZE=0x2000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-ddr3l.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr3l-val.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_MXC_SPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=8000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y diff --git a/configs/imx8mm_ddr4_evk_android_defconfig b/configs/imx8mm_ddr4_evk_android_defconfig new file mode 100644 index 00000000000..2facbe3f522 --- /dev/null +++ b/configs/imx8mm_ddr4_evk_android_defconfig @@ -0,0 +1,158 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-ddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y diff --git a/configs/imx8mm_ddr4_evk_android_uuu_defconfig b/configs/imx8mm_ddr4_evk_android_uuu_defconfig new file mode 100644 index 00000000000..c1dc414b692 --- /dev/null +++ b/configs/imx8mm_ddr4_evk_android_uuu_defconfig @@ -0,0 +1,153 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-ddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n diff --git a/configs/imx8mm_ddr4_evk_defconfig b/configs/imx8mm_ddr4_evk_defconfig new file mode 100644 index 00000000000..6971c047e4f --- /dev/null +++ b/configs/imx8mm_ddr4_evk_defconfig @@ -0,0 +1,148 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-ddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mm_ddr4_evk_nand_defconfig b/configs/imx8mm_ddr4_evk_nand_defconfig new file mode 100644 index 00000000000..e7463764965 --- /dev/null +++ b/configs/imx8mm_ddr4_evk_nand_defconfig @@ -0,0 +1,150 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_BOOTCOMMAND="run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-ddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-evk.dtb" +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mm_ddr4_val_defconfig b/configs/imx8mm_ddr4_val_defconfig new file mode 100644 index 00000000000..12f3b8203bd --- /dev/null +++ b/configs/imx8mm_ddr4_val_defconfig @@ -0,0 +1,128 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_DDR4_VAL=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-ddr4-val" +CONFIG_CSF_SIZE=0x2000 +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-ddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-ddr4-val.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 diff --git a/configs/imx8mm_evk_1g_ddr_android_defconfig b/configs/imx8mm_evk_1g_ddr_android_defconfig new file mode 100644 index 00000000000..fd28cbfeabd --- /dev/null +++ b/configs/imx8mm_evk_1g_ddr_android_defconfig @@ -0,0 +1,189 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_LZ4=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_IMX8M_1G_MEMORY=y diff --git a/configs/imx8mm_evk_4g_android_defconfig b/configs/imx8mm_evk_4g_android_defconfig new file mode 100644 index 00000000000..72b00c37c18 --- /dev/null +++ b/configs/imx8mm_evk_4g_android_defconfig @@ -0,0 +1,189 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_LZ4=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_IMX8M_4G_LPDDR4=y diff --git a/configs/imx8mm_evk_4g_android_trusty_defconfig b/configs/imx8mm_evk_4g_android_trusty_defconfig new file mode 100644 index 00000000000..39bb921fd9b --- /dev/null +++ b/configs/imx8mm_evk_4g_android_trusty_defconfig @@ -0,0 +1,190 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_LZ4=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_IMX8M_4G_LPDDR4=y +CONFIG_IMX_TRUSTY_OS=y diff --git a/configs/imx8mm_evk_4g_android_uuu_defconfig b/configs/imx8mm_evk_4g_android_uuu_defconfig new file mode 100644 index 00000000000..a768cd0d9dd --- /dev/null +++ b/configs/imx8mm_evk_4g_android_uuu_defconfig @@ -0,0 +1,184 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n +CONFIG_IMX8M_4G_LPDDR4=y diff --git a/configs/imx8mm_evk_android_defconfig b/configs/imx8mm_evk_android_defconfig new file mode 100644 index 00000000000..1a43c9de471 --- /dev/null +++ b/configs/imx8mm_evk_android_defconfig @@ -0,0 +1,188 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_LZ4=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y diff --git a/configs/imx8mm_evk_android_dual_defconfig b/configs/imx8mm_evk_android_dual_defconfig new file mode 100644 index 00000000000..1ea678549e5 --- /dev/null +++ b/configs/imx8mm_evk_android_dual_defconfig @@ -0,0 +1,189 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_LZ4=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_DUAL_BOOTLOADER=y diff --git a/configs/imx8mm_evk_android_trusty_defconfig b/configs/imx8mm_evk_android_trusty_defconfig new file mode 100644 index 00000000000..3967a222bdb --- /dev/null +++ b/configs/imx8mm_evk_android_trusty_defconfig @@ -0,0 +1,189 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_LZ4=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y diff --git a/configs/imx8mm_evk_android_trusty_dual_defconfig b/configs/imx8mm_evk_android_trusty_dual_defconfig new file mode 100644 index 00000000000..8a0cdf07019 --- /dev/null +++ b/configs/imx8mm_evk_android_trusty_dual_defconfig @@ -0,0 +1,190 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_LZ4=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_DUAL_BOOTLOADER=y diff --git a/configs/imx8mm_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mm_evk_android_trusty_secure_unlock_defconfig new file mode 100644 index 00000000000..339ee8dbf9b --- /dev/null +++ b/configs/imx8mm_evk_android_trusty_secure_unlock_defconfig @@ -0,0 +1,191 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_LZ4=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SECURE_UNLOCK=y +CONFIG_IMX_HAB=y diff --git a/configs/imx8mm_evk_android_uuu_defconfig b/configs/imx8mm_evk_android_uuu_defconfig new file mode 100644 index 00000000000..2bbb0e3cba1 --- /dev/null +++ b/configs/imx8mm_evk_android_uuu_defconfig @@ -0,0 +1,183 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y + +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index e22b7de56fb..1b78d0ed299 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -4,20 +4,26 @@ CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x10000 -CONFIG_ENV_SIZE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y @@ -25,54 +31,95 @@ CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y -CONFIG_HUSH_PARSER=y +CONFIG_NR_DRAM_BANKS=2 CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_NVEDIT_EFI=y CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y CONFIG_CMD_PART=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y +CONFIG_CMD_SNTP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y +CONFIG_CMD_HASH=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -CONFIG_SPL_DM=y -CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK_COMPOSITE_CCF=y -CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_UDP_FUNCTION_FASTBOOT=y CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y @@ -80,17 +127,53 @@ CONFIG_PHY_GIGE=y CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y -CONFIG_DM_PMIC=y -CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y -CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y -CONFIG_IMX_WATCHDOG=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZO=y +CONFIG_BZIP2=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig new file mode 100644 index 00000000000..38bf8d3734c --- /dev/null +++ b/configs/imx8mm_evk_fspi_defconfig @@ -0,0 +1,155 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E2000 +CONFIG_TARGET_IMX8MM_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4-fspi.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk.dtb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mm_evk_qca_defconfig b/configs/imx8mm_evk_qca_defconfig new file mode 100644 index 00000000000..a1e3954d0d5 --- /dev/null +++ b/configs/imx8mm_evk_qca_defconfig @@ -0,0 +1,153 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MM_EVK_QCA=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk-qca-wifi" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk-qca-wifi.dtb" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mm_evk_qca_fspi_defconfig b/configs/imx8mm_evk_qca_fspi_defconfig new file mode 100644 index 00000000000..a864721e202 --- /dev/null +++ b/configs/imx8mm_evk_qca_fspi_defconfig @@ -0,0 +1,154 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E2000 +CONFIG_TARGET_IMX8MM_EVK_QCA=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk-qca-wifi" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4-fspi.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_DEFAULT_FDT_FILE="imx8mm-evk-qca-wifi.dtb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SDP_LOADADDR=0x40400000 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mn_ddr3l_evk_defconfig b/configs/imx8mn_ddr3l_evk_defconfig new file mode 100644 index 00000000000..e80d182c984 --- /dev/null +++ b/configs/imx8mn_ddr3l_evk_defconfig @@ -0,0 +1,145 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x70000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_DDR3_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr3l-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr3l.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr3l-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/imx8mn_ddr4_evk_android_defconfig b/configs/imx8mn_ddr4_evk_android_defconfig new file mode 100644 index 00000000000..c8c30730ba7 --- /dev/null +++ b/configs/imx8mn_ddr4_evk_android_defconfig @@ -0,0 +1,168 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y diff --git a/configs/imx8mn_ddr4_evk_android_uuu_defconfig b/configs/imx8mn_ddr4_evk_android_uuu_defconfig new file mode 100644 index 00000000000..9cbec2509bd --- /dev/null +++ b/configs/imx8mn_ddr4_evk_android_uuu_defconfig @@ -0,0 +1,163 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +ONFIG_CMD_BOOTA=n diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 2c12bdabe0a..1c1d1cb2440 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -5,20 +5,26 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 -CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0x912000 CONFIG_TARGET_IMX8MN_DDR4_EVK=y -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y @@ -27,32 +33,44 @@ CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg" CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set CONFIG_CMD_ERASEENV=y # CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y @@ -62,27 +80,79 @@ CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MN=y CONFIG_CLK_IMX8MN=y CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_BD71837=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y -CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y -CONFIG_IMX_WATCHDOG=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mn_ddr4_evk_ld_defconfig b/configs/imx8mn_ddr4_evk_ld_defconfig new file mode 100644 index 00000000000..97d2e87bcf6 --- /dev/null +++ b/configs/imx8mn_ddr4_evk_ld_defconfig @@ -0,0 +1,160 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-ddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-ddr4-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_BD71837=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_IMX8MN_LOW_DRIVE_MODE=y diff --git a/configs/imx8mn_evk_android_defconfig b/configs/imx8mn_evk_android_defconfig new file mode 100644 index 00000000000..015c189eb62 --- /dev/null +++ b/configs/imx8mn_evk_android_defconfig @@ -0,0 +1,168 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y diff --git a/configs/imx8mn_evk_android_dual_defconfig b/configs/imx8mn_evk_android_dual_defconfig new file mode 100644 index 00000000000..861edca059d --- /dev/null +++ b/configs/imx8mn_evk_android_dual_defconfig @@ -0,0 +1,169 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_DUAL_BOOTLOADER=y diff --git a/configs/imx8mn_evk_android_trusty_defconfig b/configs/imx8mn_evk_android_trusty_defconfig new file mode 100644 index 00000000000..58b2d2d61b9 --- /dev/null +++ b/configs/imx8mn_evk_android_trusty_defconfig @@ -0,0 +1,169 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y diff --git a/configs/imx8mn_evk_android_trusty_dual_defconfig b/configs/imx8mn_evk_android_trusty_dual_defconfig new file mode 100644 index 00000000000..76487ee1c21 --- /dev/null +++ b/configs/imx8mn_evk_android_trusty_dual_defconfig @@ -0,0 +1,170 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_DUAL_BOOTLOADER=y diff --git a/configs/imx8mn_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mn_evk_android_trusty_secure_unlock_defconfig new file mode 100644 index 00000000000..23054287836 --- /dev/null +++ b/configs/imx8mn_evk_android_trusty_secure_unlock_defconfig @@ -0,0 +1,171 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SECURE_UNLOCK=y +CONFIG_IMX_HAB=y diff --git a/configs/imx8mn_evk_android_uuu_defconfig b/configs/imx8mn_evk_android_uuu_defconfig new file mode 100644 index 00000000000..8370ab6ea9d --- /dev/null +++ b/configs/imx8mn_evk_android_uuu_defconfig @@ -0,0 +1,163 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig new file mode 100644 index 00000000000..ef5647eadb1 --- /dev/null +++ b/configs/imx8mn_evk_defconfig @@ -0,0 +1,158 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mn_evk_ld_defconfig b/configs/imx8mn_evk_ld_defconfig new file mode 100644 index 00000000000..730ee15653e --- /dev/null +++ b/configs/imx8mn_evk_ld_defconfig @@ -0,0 +1,160 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x912000 +CONFIG_TARGET_IMX8MN_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mn-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mn-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MN=y +CONFIG_CLK_IMX8MN=y +CONFIG_MXC_GPIO=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y + +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y +CONFIG_CI_UDC=y +CONFIG_USB_EHCI_HCD=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_DM_RESET=y +CONFIG_RESET_DISPMIX=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_IMX8MN_LOW_DRIVE_MODE=y diff --git a/configs/imx8mp_ddr4_evk_defconfig b/configs/imx8mp_ddr4_evk_defconfig new file mode 100644 index 00000000000..57214b39a23 --- /dev/null +++ b/configs/imx8mp_ddr4_evk_defconfig @@ -0,0 +1,170 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-ddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-ddr4-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y diff --git a/configs/imx8mp_ddr4_evk_inline_ecc_defconfig b/configs/imx8mp_ddr4_evk_inline_ecc_defconfig new file mode 100644 index 00000000000..4882a79f707 --- /dev/null +++ b/configs/imx8mp_ddr4_evk_inline_ecc_defconfig @@ -0,0 +1,172 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-ddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-ddr4-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y + +CONFIG_IMX8M_DRAM_INLINE_ECC=y diff --git a/configs/imx8mp_ddr4_evk_nand_defconfig b/configs/imx8mp_ddr4_evk_nand_defconfig new file mode 100644 index 00000000000..945406265cc --- /dev/null +++ b/configs/imx8mp_ddr4_evk_nand_defconfig @@ -0,0 +1,171 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_DDR4_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-ddr4-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_BOOTCOMMAND="run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-ddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-ddr4-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y + +CONFIG_NAND_BOOT=y diff --git a/configs/imx8mp_evk_android_defconfig b/configs/imx8mp_evk_android_defconfig new file mode 100644 index 00000000000..94e2053a733 --- /dev/null +++ b/configs/imx8mp_evk_android_defconfig @@ -0,0 +1,180 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y diff --git a/configs/imx8mp_evk_android_dual_defconfig b/configs/imx8mp_evk_android_dual_defconfig new file mode 100644 index 00000000000..d8f0d54a5d1 --- /dev/null +++ b/configs/imx8mp_evk_android_dual_defconfig @@ -0,0 +1,181 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_DUAL_BOOTLOADER=y diff --git a/configs/imx8mp_evk_android_powersave_defconfig b/configs/imx8mp_evk_android_powersave_defconfig new file mode 100644 index 00000000000..a492ee410be --- /dev/null +++ b/configs/imx8mp_evk_android_powersave_defconfig @@ -0,0 +1,182 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX8M_VDD_SOC_850MV=y +CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS=y diff --git a/configs/imx8mp_evk_android_trusty_defconfig b/configs/imx8mp_evk_android_trusty_defconfig new file mode 100644 index 00000000000..8aff30b4f47 --- /dev/null +++ b/configs/imx8mp_evk_android_trusty_defconfig @@ -0,0 +1,181 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y diff --git a/configs/imx8mp_evk_android_trusty_dual_defconfig b/configs/imx8mp_evk_android_trusty_dual_defconfig new file mode 100644 index 00000000000..2e4b3640f40 --- /dev/null +++ b/configs/imx8mp_evk_android_trusty_dual_defconfig @@ -0,0 +1,182 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_IMX_TRUSTY_OS=y diff --git a/configs/imx8mp_evk_android_trusty_powersave_defconfig b/configs/imx8mp_evk_android_trusty_powersave_defconfig new file mode 100644 index 00000000000..94b295162e5 --- /dev/null +++ b/configs/imx8mp_evk_android_trusty_powersave_defconfig @@ -0,0 +1,183 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_IMX8M_VDD_SOC_850MV=y +CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS=y diff --git a/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig new file mode 100644 index 00000000000..0a56b90444a --- /dev/null +++ b/configs/imx8mp_evk_android_trusty_secure_unlock_defconfig @@ -0,0 +1,183 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x320 +CONFIG_AVB_WARNING_LOGO_ROWS=0xc0 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SECURE_UNLOCK=y +CONFIG_IMX_HAB=y diff --git a/configs/imx8mp_evk_android_uuu_defconfig b/configs/imx8mp_evk_android_uuu_defconfig new file mode 100644 index 00000000000..ccf18db4ce3 --- /dev/null +++ b/configs/imx8mp_evk_android_uuu_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0xc800000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 47a52eedb99..8c7ede824c4 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -5,20 +5,26 @@ CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x10000 -CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 CONFIG_SYS_I2C_MXC_I2C1=y CONFIG_SYS_I2C_MXC_I2C2=y CONFIG_SYS_I2C_MXC_I2C3=y CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0x920000 CONFIG_TARGET_IMX8MP_EVK=y -CONFIG_SPL_MMC_SUPPORT=y +CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y @@ -33,13 +39,16 @@ CONFIG_SPL_BOOTROM_SUPPORT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y # CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_CLK=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y @@ -51,29 +60,45 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y CONFIG_CLK_IMX8MP=y CONFIG_MXC_GPIO=y CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y CONFIG_DM_I2C=y -# CONFIG_SPL_DM_I2C is not set CONFIG_SYS_I2C_MXC=y CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y @@ -81,20 +106,65 @@ CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_FSL_ESDHC_IMX=y CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y CONFIG_DM_ETH=y CONFIG_PHY_GIGE=y CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y CONFIG_FEC_MXC=y CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_SYSRESET=y -CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_IMX_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mp_evk_inline_ecc_defconfig b/configs/imx8mp_evk_inline_ecc_defconfig new file mode 100644 index 00000000000..9116c4f8c5e --- /dev/null +++ b/configs/imx8mp_evk_inline_ecc_defconfig @@ -0,0 +1,172 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0xC0000000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IMX8MP_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mp-evk" +CONFIG_CSF_SIZE=0x2000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mp-evk.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_LED=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_PHY_REALTEK=y +CONFIG_PHYLIB=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_USB_STORAGE=y +CONFIG_DM_USB=y + +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_OF_BOARD_SETUP=y +CONFIG_IMX8M_DRAM_INLINE_ECC=y + +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM67191=y +CONFIG_VIDEO_ADV7535=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8mq_ddr3l_val_defconfig b/configs/imx8mq_ddr3l_val_defconfig new file mode 100644 index 00000000000..97d72b38f93 --- /dev/null +++ b/configs/imx8mq_ddr3l_val_defconfig @@ -0,0 +1,129 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_DDR3L_VAL=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_DEFAULT_FDT_FILE="imx8mq-ddr3l-val.dtb" +CONFIG_NR_DRAM_BANKS=2 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-ddr3l-val" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y + +CONFIG_PHYLIB=y +CONFIG_PHY_REALTEK=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_FSL_QSPI=y +CONFIG_CMD_SF=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=1 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 diff --git a/configs/imx8mq_ddr4_val_defconfig b/configs/imx8mq_ddr4_val_defconfig new file mode 100644 index 00000000000..cb38c52ff77 --- /dev/null +++ b/configs/imx8mq_ddr4_val_defconfig @@ -0,0 +1,128 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_DDR4_VAL=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_DEFAULT_FDT_FILE="imx8mq-ddr4-val.dtb" +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-ddr4-val" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y diff --git a/configs/imx8mq_ddr4_val_nand_defconfig b/configs/imx8mq_ddr4_val_nand_defconfig new file mode 100644 index 00000000000..b6ffae60485 --- /dev/null +++ b/configs/imx8mq_ddr4_val_nand_defconfig @@ -0,0 +1,128 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_DDR4_VAL=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_DEFAULT_FDT_FILE="imx8mq-ddr4-val.dtb" +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-ddr4-val" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y + +CONFIG_CMD_NAND=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y diff --git a/configs/imx8mq_evk_android_defconfig b/configs/imx8mq_evk_android_defconfig new file mode 100644 index 00000000000..0c3d625aaa8 --- /dev/null +++ b/configs/imx8mq_evk_android_defconfig @@ -0,0 +1,152 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMX8M_DCSS=y +CONFIG_VIDEO_IMX8M_HDMI=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y diff --git a/configs/imx8mq_evk_android_dual_defconfig b/configs/imx8mq_evk_android_dual_defconfig new file mode 100644 index 00000000000..d43e34b1cc9 --- /dev/null +++ b/configs/imx8mq_evk_android_dual_defconfig @@ -0,0 +1,153 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMX8M_DCSS=y +CONFIG_VIDEO_IMX8M_HDMI=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_DUAL_BOOTLOADER=y diff --git a/configs/imx8mq_evk_android_trusty_defconfig b/configs/imx8mq_evk_android_trusty_defconfig new file mode 100644 index 00000000000..c6003adc05c --- /dev/null +++ b/configs/imx8mq_evk_android_trusty_defconfig @@ -0,0 +1,153 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMX8M_DCSS=y +CONFIG_VIDEO_IMX8M_HDMI=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y diff --git a/configs/imx8mq_evk_android_trusty_dual_defconfig b/configs/imx8mq_evk_android_trusty_dual_defconfig new file mode 100644 index 00000000000..d69c4f92c6d --- /dev/null +++ b/configs/imx8mq_evk_android_trusty_dual_defconfig @@ -0,0 +1,152 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMX8M_DCSS=y +CONFIG_VIDEO_IMX8M_HDMI=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_DUAL_BOOTLOADER=y diff --git a/configs/imx8mq_evk_android_trusty_secure_unlock_defconfig b/configs/imx8mq_evk_android_trusty_secure_unlock_defconfig new file mode 100644 index 00000000000..85aedf824f5 --- /dev/null +++ b/configs/imx8mq_evk_android_trusty_secure_unlock_defconfig @@ -0,0 +1,155 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMX8M_DCSS=y +CONFIG_VIDEO_IMX8M_HDMI=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SECURE_UNLOCK=y +CONFIG_IMX_HAB=y diff --git a/configs/imx8mq_evk_android_uuu_defconfig b/configs/imx8mq_evk_android_uuu_defconfig new file mode 100644 index 00000000000..8fccf6fac23 --- /dev/null +++ b/configs/imx8mq_evk_android_uuu_defconfig @@ -0,0 +1,147 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x44800000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMX8M_DCSS=y +CONFIG_VIDEO_IMX8M_HDMI=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_FLASH_MCUFIRMWARE_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index a149c1a7709..02dab99ec02 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -1,49 +1,97 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 -CONFIG_ENV_SIZE=0x1000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_OFFSET=0x400000 +CONFIG_SYS_MEMTEST_START=0x40000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_IMX8MQ_EVK=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="imx8mq-evk" CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" -CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y -# CONFIG_BOOTM_NETBSD is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set # CONFIG_CMD_CRC32 is not set +# CONFIG_BOOTM_NETBSD is not set CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -# CONFIG_CMD_MDIO is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MXC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX8M=y CONFIG_POWER_DOMAIN=y @@ -53,4 +101,42 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB_TCPC=y +CONFIG_USB_STORAGE=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_GADGET=y +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8M=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMX8M_DCSS=y +CONFIG_VIDEO_IMX8M_HDMI=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8qm_ddr4_val_defconfig b/configs/imx8qm_ddr4_val_defconfig new file mode 100644 index 00000000000..db653c14c38 --- /dev/null +++ b/configs/imx8qm_ddr4_val_defconfig @@ -0,0 +1,163 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_val/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_DDR4_VAL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-ddr4-val" +CONFIG_DEFAULT_FDT_FILE="imx8qm-ddr4-val.dtb" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y diff --git a/configs/imx8qm_lpddr4_val_defconfig b/configs/imx8qm_lpddr4_val_defconfig new file mode 100644 index 00000000000..4c38e4587ef --- /dev/null +++ b/configs/imx8qm_lpddr4_val_defconfig @@ -0,0 +1,166 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_val/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_LPDDR4_VAL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-val" +CONFIG_DEFAULT_FDT_FILE="imx8qm-lpddr4-val.dtb" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y diff --git a/configs/imx8qm_lpddr4_val_fspi_defconfig b/configs/imx8qm_lpddr4_val_fspi_defconfig new file mode 100644 index 00000000000..a18611fe2cb --- /dev/null +++ b/configs/imx8qm_lpddr4_val_fspi_defconfig @@ -0,0 +1,172 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_val/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_LPDDR4_VAL=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_SPI_FLASH_TINY=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000 +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-lpddr4-val" +CONFIG_DEFAULT_FDT_FILE="imx8qm-lpddr4-val.dtb" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_QSPI_BOOT=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y diff --git a/configs/imx8qm_mek_android_defconfig b/configs/imx8qm_mek_android_defconfig new file mode 100644 index 00000000000..f195f9c4da0 --- /dev/null +++ b/configs/imx8qm_mek_android_defconfig @@ -0,0 +1,197 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y diff --git a/configs/imx8qm_mek_android_hdmi_defconfig b/configs/imx8qm_mek_android_hdmi_defconfig new file mode 100644 index 00000000000..fccd6f711c2 --- /dev/null +++ b/configs/imx8qm_mek_android_hdmi_defconfig @@ -0,0 +1,199 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX=y +CONFIG_IMX_LOAD_HDMI_FIMRWARE_RX=y diff --git a/configs/imx8qm_mek_android_trusty_defconfig b/configs/imx8qm_mek_android_trusty_defconfig new file mode 100644 index 00000000000..672776463dd --- /dev/null +++ b/configs/imx8qm_mek_android_trusty_defconfig @@ -0,0 +1,199 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SHA256=y diff --git a/configs/imx8qm_mek_android_trusty_secure_unlock_defconfig b/configs/imx8qm_mek_android_trusty_secure_unlock_defconfig new file mode 100644 index 00000000000..5dba8c48cd4 --- /dev/null +++ b/configs/imx8qm_mek_android_trusty_secure_unlock_defconfig @@ -0,0 +1,201 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SHA256=y +CONFIG_SECURE_UNLOCK=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8qm_mek_android_uuu_defconfig b/configs/imx8qm_mek_android_uuu_defconfig new file mode 100644 index 00000000000..92674d365b3 --- /dev/null +++ b/configs/imx8qm_mek_android_uuu_defconfig @@ -0,0 +1,191 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n diff --git a/configs/imx8qm_mek_androidauto2_trusty_defconfig b/configs/imx8qm_mek_androidauto2_trusty_defconfig new file mode 100644 index 00000000000..f95b4f67777 --- /dev/null +++ b/configs/imx8qm_mek_androidauto2_trusty_defconfig @@ -0,0 +1,198 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=y +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SHA256=y +CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2" +CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_LOAD_KEY_FROM_RPMB=n diff --git a/configs/imx8qm_mek_androidauto2_trusty_md_defconfig b/configs/imx8qm_mek_androidauto2_trusty_md_defconfig new file mode 100644 index 00000000000..f555b1d3919 --- /dev/null +++ b/configs/imx8qm_mek_androidauto2_trusty_md_defconfig @@ -0,0 +1,199 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=y +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SHA256=y +CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2" +CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_LOAD_KEY_FROM_RPMB=n +CONFIG_IMX_LOAD_HDMI_FIMRWARE_TX=y diff --git a/configs/imx8qm_mek_androidauto_trusty_defconfig b/configs/imx8qm_mek_androidauto_trusty_defconfig new file mode 100644 index 00000000000..f609f005031 --- /dev/null +++ b/configs/imx8qm_mek_androidauto_trusty_defconfig @@ -0,0 +1,197 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=y +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88800000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_SHA256=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car" +CONFIG_ANDROID_AUTO_SUPPORT=y diff --git a/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig b/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig new file mode 100644 index 00000000000..49c89819c46 --- /dev/null +++ b/configs/imx8qm_mek_androidauto_trusty_secure_unlock_defconfig @@ -0,0 +1,199 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=y +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88800000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x02000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_SHA256=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car" +CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_SECURE_UNLOCK=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8qm_mek_androidauto_xen_defconfig b/configs/imx8qm_mek_androidauto_xen_defconfig new file mode 100644 index 00000000000..f95b4f67777 --- /dev/null +++ b/configs/imx8qm_mek_androidauto_xen_defconfig @@ -0,0 +1,198 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=y +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SHA256=y +CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2" +CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_LOAD_KEY_FROM_RPMB=n diff --git a/configs/imx8qm_mek_cockpit_a53_defconfig b/configs/imx8qm_mek_cockpit_a53_defconfig new file mode 100644 index 00000000000..e85e9223015 --- /dev/null +++ b/configs/imx8qm_mek_cockpit_a53_defconfig @@ -0,0 +1,161 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_TARGET_IMX8QM_MEK_A53_ONLY=y +CONFIG_DM_GPIO=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_FIT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-cockpit-a53" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_DM_VIDEO=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8qm_mek_cockpit_a72_android_defconfig b/configs/imx8qm_mek_cockpit_a72_android_defconfig new file mode 100644 index 00000000000..aa82a9312b3 --- /dev/null +++ b/configs/imx8qm_mek_cockpit_a72_android_defconfig @@ -0,0 +1,146 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0xC0020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_MU_BASE_SPL=0x5d1e0000 +CONFIG_TARGET_IMX8QM_MEK_A72_ONLY=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg,ANDROID_SUPPORT" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-cockpit-a72" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_DM_GPIO=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SC_THERMAL=y + +CONFIG_VIDEO=n +CONFIG_VIDEO_IMX_HDP_LOAD=n + +CONFIG_SPI=y +CONFIG_FSL_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0xC0400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FSL_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xD8000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0xC8000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_LIBAVB=y +CONFIG_CMD_MMC_RPMB=y +CONFIG_SUPPORT_EMMC_RPMB=y diff --git a/configs/imx8qm_mek_cockpit_a72_defconfig b/configs/imx8qm_mek_cockpit_a72_defconfig new file mode 100644 index 00000000000..41edba861b9 --- /dev/null +++ b/configs/imx8qm_mek_cockpit_a72_defconfig @@ -0,0 +1,165 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0xC0020000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_MU_BASE_SPL=0x5d1e0000 +CONFIG_TARGET_IMX8QM_MEK_A72_ONLY=y +CONFIG_DM_GPIO=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_ENV_IS_NOWHERE=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_NR_DRAM_BANKS=4 +CONFIG_SPL=y +CONFIG_PANIC_HANG=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek-cockpit-a72" +CONFIG_ENV_IS_NOWHERE=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_DM_VIDEO=y +CONFIG_VIDEO=y +CONFIG_VIDEO_IMX_HDP_LOAD=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=n +CONFIG_USB_XHCI_IMX8=n +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=n +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=n +CONFIG_USB_CDNS3_GADGET=n +CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0xC0400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0xC2800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0xC8000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index 0dc7f4bec39..f8fa8ee0e51 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -1,12 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SIZE=0x1000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0x100000 @@ -14,21 +16,25 @@ CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" CONFIG_TARGET_IMX8QM_MEK=y CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y -CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_CPU=y # CONFIG_BOOTM_NETBSD is not set @@ -44,12 +50,16 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_CLK=y CONFIG_CLK_IMX8=y @@ -62,7 +72,12 @@ CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y @@ -81,8 +96,92 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y CONFIG_SPL_TINY_MEMSET=y # CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y \ No newline at end of file diff --git a/configs/imx8qm_mek_fspi_defconfig b/configs/imx8qm_mek_fspi_defconfig new file mode 100644 index 00000000000..912ed586fce --- /dev/null +++ b/configs/imx8qm_mek_fspi_defconfig @@ -0,0 +1,186 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_SPI_FLASH_TINY=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000 +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y \ No newline at end of file diff --git a/configs/imx8qm_mek_trusty_xen_defconfig b/configs/imx8qm_mek_trusty_xen_defconfig new file mode 100644 index 00000000000..f95b4f67777 --- /dev/null +++ b/configs/imx8qm_mek_trusty_xen_defconfig @@ -0,0 +1,198 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qm_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QM_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=y +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x01000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y + +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y + +CONFIG_VIDEO_IMX_HDP_LOAD=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SHA256=y +CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2" +CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_LOAD_KEY_FROM_RPMB=n diff --git a/configs/imx8qxp_17x17_val_defconfig b/configs/imx8qxp_17x17_val_defconfig new file mode 100644 index 00000000000..6656477ec2f --- /dev/null +++ b/configs/imx8qxp_17x17_val_defconfig @@ -0,0 +1,153 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg" +CONFIG_TARGET_IMX8X_17X17_VAL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-17x17-val" +CONFIG_DEFAULT_FDT_FILE="imx8qxp-17x17-val.dtb" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_USB_CDNS3=y +# CONFIG_USB_CDNS3_GADGET=y +# CONFIG_USB_GADGET_DUALSPEED=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=0 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=0 + +CONFIG_USB_PORT_AUTO=y diff --git a/configs/imx8qxp_ddr3_val_defconfig b/configs/imx8qxp_ddr3_val_defconfig new file mode 100644 index 00000000000..0cef999f399 --- /dev/null +++ b/configs/imx8qxp_ddr3_val_defconfig @@ -0,0 +1,165 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_DDR3_VAL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val" +CONFIG_DEFAULT_FDT_FILE="imx8qxp-ddr3l-val.dtb" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8qxp_lpddr4_val_defconfig b/configs/imx8qxp_lpddr4_val_defconfig new file mode 100644 index 00000000000..328f108b71b --- /dev/null +++ b/configs/imx8qxp_lpddr4_val_defconfig @@ -0,0 +1,167 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_LPDDR4_VAL=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val" +CONFIG_DEFAULT_FDT_FILE="imx8qxp-lpddr4-val.dtb" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_FSL_LPSPI=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8qxp_lpddr4_val_fspi_defconfig b/configs/imx8qxp_lpddr4_val_fspi_defconfig new file mode 100644 index 00000000000..87fccaa6df5 --- /dev/null +++ b/configs/imx8qxp_lpddr4_val_fspi_defconfig @@ -0,0 +1,171 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_LPDDR4_VAL=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_SPI_FLASH_TINY=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000 +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val" +CONFIG_DEFAULT_FDT_FILE="imx8qxp-lpddr4-val.dtb" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_QSPI_BOOT=y +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8qxp_lpddr4_val_nand_defconfig b/configs/imx8qxp_lpddr4_val_nand_defconfig new file mode 100644 index 00000000000..49fed5ff7d4 --- /dev/null +++ b/configs/imx8qxp_lpddr4_val_nand_defconfig @@ -0,0 +1,165 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x7800000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_val/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_LPDDR4_VAL=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_DMA=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-lpddr4-val-gpmi-nand" +CONFIG_DEFAULT_FDT_FILE="imx8qxp-lpddr4-val-gpmi-nand.dtb" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_NAND=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_NAND_BOOT=y +CONFIG_CMD_UBI=y + +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y diff --git a/configs/imx8qxp_mek_android_defconfig b/configs/imx8qxp_mek_android_defconfig new file mode 100644 index 00000000000..2862f273c81 --- /dev/null +++ b/configs/imx8qxp_mek_android_defconfig @@ -0,0 +1,195 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y diff --git a/configs/imx8qxp_mek_android_trusty_defconfig b/configs/imx8qxp_mek_android_trusty_defconfig new file mode 100644 index 00000000000..ebf9651df97 --- /dev/null +++ b/configs/imx8qxp_mek_android_trusty_defconfig @@ -0,0 +1,198 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y + +CONFIG_SHA256=y +CONFIG_IMX_TRUSTY_OS=y diff --git a/configs/imx8qxp_mek_android_trusty_secure_unlock_defconfig b/configs/imx8qxp_mek_android_trusty_secure_unlock_defconfig new file mode 100644 index 00000000000..d4003ec2644 --- /dev/null +++ b/configs/imx8qxp_mek_android_trusty_secure_unlock_defconfig @@ -0,0 +1,200 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_AVB_WARNING_LOGO=y +CONFIG_AVB_WARNING_LOGO_COLS=0x1E0 +CONFIG_AVB_WARNING_LOGO_ROWS=0x60 +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y + +CONFIG_SHA256=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_SECURE_UNLOCK=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8qxp_mek_android_uuu_defconfig b/configs/imx8qxp_mek_android_uuu_defconfig new file mode 100644 index 00000000000..4ab7632e3ee --- /dev/null +++ b/configs/imx8qxp_mek_android_uuu_defconfig @@ -0,0 +1,189 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_ANDROID_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y +CONFIG_CMD_BOOTA=n diff --git a/configs/imx8qxp_mek_androidauto2_trusty_defconfig b/configs/imx8qxp_mek_androidauto2_trusty_defconfig new file mode 100644 index 00000000000..dca283f4f84 --- /dev/null +++ b/configs/imx8qxp_mek_androidauto2_trusty_defconfig @@ -0,0 +1,197 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=y +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_VIRTUAL_AB_SUPPORT=y +CONFIG_ANDROID_AB_SUPPORT=y + +CONFIG_SHA256=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car2" +CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_LOAD_KEY_FROM_RPMB=n diff --git a/configs/imx8qxp_mek_androidauto_trusty_defconfig b/configs/imx8qxp_mek_androidauto_trusty_defconfig new file mode 100644 index 00000000000..5e78a67ccf1 --- /dev/null +++ b/configs/imx8qxp_mek_androidauto_trusty_defconfig @@ -0,0 +1,196 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=y +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_ANDROID_AB_SUPPORT=y + +CONFIG_SHA256=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car" +CONFIG_ANDROID_AUTO_SUPPORT=y diff --git a/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig b/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig new file mode 100644 index 00000000000..8c3a2225a1f --- /dev/null +++ b/configs/imx8qxp_mek_androidauto_trusty_secure_unlock_defconfig @@ -0,0 +1,198 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=y +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=n +CONFIG_FASTBOOT_BUF_ADDR=0x98000000 +CONFIG_FASTBOOT_BUF_SIZE=0x19000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x00800000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_LZ4=y +CONFIG_APPEND_BOOTARGS=y +CONFIG_PSCI_BOARD_REBOOT=y +CONFIG_ANDROID_AB_SUPPORT=y + +CONFIG_SHA256=y +CONFIG_IMX_TRUSTY_OS=y +CONFIG_DUAL_BOOTLOADER=y +CONFIG_ATTESTATION_ID_PRODUCT="mek_8q_car" +CONFIG_ANDROID_AUTO_SUPPORT=y +CONFIG_SECURE_UNLOCK=y +CONFIG_AHAB_BOOT=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index e60eb8047d0..56d3fe45215 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -1,12 +1,14 @@ CONFIG_ARM=y CONFIG_ARCH_IMX8=y CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 CONFIG_SPL_GPIO_SUPPORT=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x4000 -CONFIG_NR_DRAM_BANKS=3 -CONFIG_ENV_SIZE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x400000 CONFIG_DM_GPIO=y CONFIG_SPL_TEXT_BASE=0x100000 @@ -14,17 +16,22 @@ CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" CONFIG_TARGET_IMX8QXP_MEK=y CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_SERIAL_SUPPORT=y CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_SPL=y CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" CONFIG_BOOTDELAY=3 CONFIG_LOG=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SPL_BOARD_INIT=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_POWER_SUPPORT=y CONFIG_SPL_POWER_DOMAIN=y @@ -36,7 +43,6 @@ CONFIG_CMD_CPU=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_CLK=y CONFIG_CMD_DM=y -CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -44,6 +50,9 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y @@ -65,6 +74,10 @@ CONFIG_MISC=y CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y CONFIG_PHYLIB=y CONFIG_PHY_ADDR_ENABLE=y CONFIG_PHY_ATHEROS=y @@ -83,10 +96,90 @@ CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y -CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y -CONFIG_DM_THERMAL=y -CONFIG_IMX_SCU_THERMAL=y CONFIG_SPL_TINY_MEMSET=y # CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/imx8qxp_mek_fspi_defconfig b/configs/imx8qxp_mek_fspi_defconfig new file mode 100644 index 00000000000..36afea38783 --- /dev/null +++ b/configs/imx8qxp_mek_fspi_defconfig @@ -0,0 +1,190 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MEMTEST_START=0xA0000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_NR_DRAM_BANKS=4 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x100000 +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="board/freescale/imx8qxp_mek/uboot-container.cfg" +CONFIG_TARGET_IMX8QXP_MEK=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_SPL_SPI_FLASH_TINY=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x200000 +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_SPL_EFI_PARTITION=n +CONFIG_SPL_DOS_PARTITION=n +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek" +CONFIG_USE_TINY_PRINTF=y +CONFIG_PANIC_HANG=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qxp_mek/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_LOG=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_CLK=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_EFI_PARTITION=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPL_TINY_MEMSET=y +# CONFIG_EFI_LOADER is not set + +CONFIG_CMD_FUSE=y +CONFIG_SMC_FUSE=y +CONFIG_CMD_MEMTEST=y + +CONFIG_IMX_BOOTAUX=y + +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y + +CONFIG_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_CMD_SF=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 + +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_IMX8=y +CONFIG_DM_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB=y +CONFIG_USB_TCPC=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_CDNS3=y +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_CDNS3_USB_PHY=y +CONFIG_PHY=y +CONFIG_SPL_PHY=y + +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_SDP_USB_DEV=1 +CONFIG_SDP_LOADADDR=0x80400000 + +CONFIG_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_CMD_FASTBOOT=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_USB_DEV=1 + +CONFIG_SYS_I2C_IMX_VIRT_I2C=y +CONFIG_I2C_MUX_IMX_VIRT=y +CONFIG_IMX_VSERVICE_SHARED_BUFFER=0x90400000 + +CONFIG_BOOTAUX_RESERVED_MEM_BASE=0x88000000 +CONFIG_BOOTAUX_RESERVED_MEM_SIZE=0x08000000 + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_USB_PORT_AUTO=y + +CONFIG_IMX_SNVS_SEC_SC=y +CONFIG_OF_LIBFDT_OVERLAY=y + +CONFIG_VIDEO_IMXDPUV1=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_IMX8_LVDS=y +CONFIG_VIDEO_IT6263_BRIDGE=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y diff --git a/configs/iot-gate-imx8_defconfig b/configs/iot-gate-imx8_defconfig new file mode 100644 index 00000000000..39c448eca05 --- /dev/null +++ b/configs/iot-gate-imx8_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DM_GPIO=y +CONFIG_TARGET_IOT_GATE_IMX8=y +CONFIG_DEFAULT_DTB="sb-iotgimx8-can.dtb" +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_LOCALVERSION="-iot-gate-imx8-1.0" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_CONSOLE_MUX=y +CONFIG_DEFAULT_FDT_FILE="sb-iotgimx8-can.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="iot-gate-imx8" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_NXP_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_EXT4_WRITE=y +CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/iot-gate-imx8plus_defconfig b/configs/iot-gate-imx8plus_defconfig new file mode 100644 index 00000000000..3cdf5e0826b --- /dev/null +++ b/configs/iot-gate-imx8plus_defconfig @@ -0,0 +1,154 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x3F0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IOT_GATE_IMX8PLUS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_BOOTCOMMAND="run bsp_bootcmd" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +# CONFIG_CMD_DATE is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_PWM=y +CONFIG_DM_RTC=y +CONFIG_RTC_ABX80X=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_LCD_STARTEK_ILI9881C=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_VIDEO_IMX_LCDIFV3=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_HEXDUMP is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/iotdin-imx8p_defconfig b/configs/iotdin-imx8p_defconfig new file mode 100644 index 00000000000..5a27397f578 --- /dev/null +++ b/configs/iotdin-imx8p_defconfig @@ -0,0 +1,158 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x3F0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_IOTDIN_IMX8P=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_BOOTCOMMAND="run bsp_bootcmd" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +# CONFIG_CMD_DATE is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_PWM=y +CONFIG_DM_RTC=y +CONFIG_RTC_ABX80X=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_LCD_STARTEK_ILI9881C=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_HEXDUMP is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index 31209e4feb3..e2b0e01de4f 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -29,7 +29,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig index e0e34e75b55..8e6837e9c70 100644 --- a/configs/ls1021aqds_nor_defconfig +++ b/configs/ls1021aqds_nor_defconfig @@ -41,7 +41,6 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index 80d5ef8411e..2cd5bf0393b 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -42,7 +42,6 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_SYS_FSL_DDR3=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 17f7eea0880..a7a2b88934b 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -30,7 +30,6 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 1a9b3e15740..bc4840d0142 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -36,7 +36,6 @@ CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_ADDR=0x60300000 CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index d7217298198..fe60d0a1725 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -51,6 +51,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SPL_DM=y +CONFIG_SPL_OF_CONTROL=y CONFIG_DM_I2C=y # CONFIG_SPL_DM_I2C is not set CONFIG_FSL_ESDHC=y diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig index 17daef8d74f..f033b185205 100644 --- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig @@ -89,3 +89,5 @@ CONFIG_WDT_SP805=y CONFIG_RSA=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LS_HDP_LOAD=y diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig index cc38bd89570..1f70fe34cc4 100644 --- a/configs/ls1028aqds_tfa_defconfig +++ b/configs/ls1028aqds_tfa_defconfig @@ -94,3 +94,5 @@ CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LS_HDP_LOAD=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 794632a6c93..de82f5b210e 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -84,3 +84,5 @@ CONFIG_WDT_SP805=y CONFIG_RSA=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LS_HDP_LOAD=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index 2ee57de839a..87357d30c0a 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -44,7 +44,6 @@ CONFIG_NETCONSOLE=y CONFIG_DM=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0 @@ -93,3 +92,5 @@ CONFIG_WDT=y CONFIG_WDT_SP805=y CONFIG_OF_LIBFDT_OVERLAY=y CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_VIDEO=y +CONFIG_VIDEO_LS_HDP_LOAD=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index de3db3e2c41..73910cb40a0 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -35,7 +35,6 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_ADDR=0x60500000 CONFIG_DM=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 5647fd52f92..0a0c7ec36fc 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -61,3 +61,4 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_ASIX88179=y CONFIG_USB_ETHER_RTL8152=y CONFIG_RSA=y +CONFIG_NXP_ESBC=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index add30016156..2e01985ffbd 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -36,7 +36,6 @@ CONFIG_ENV_ADDR=0x40500000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 9d5c941fb64..f5c2ef63cf5 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -47,7 +47,6 @@ CONFIG_ENV_SPI_BUS=0 CONFIG_ENV_ADDR=0x40500000 CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 2fbfa342829..7d5d63e1f68 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -38,7 +38,6 @@ CONFIG_ENV_ADDR=0x40500000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_ESDHC=y diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig index cf8fb314405..2d4e8967edf 100644 --- a/configs/ls1088aqds_tfa_defconfig +++ b/configs/ls1088aqds_tfa_defconfig @@ -48,6 +48,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig index 283c192b210..2e99e337c8e 100644 --- a/configs/ls1088ardb_tfa_defconfig +++ b/configs/ls1088ardb_tfa_defconfig @@ -45,6 +45,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_ADDR=0x20500000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SCSI_AHCI=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 29296995577..c6e107d6302 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -42,12 +42,11 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_ADDR=0x20500000 +CONFIG_ENV_ADDR=0x580500000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0 diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index de57235284f..f567de6e222 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -45,7 +45,6 @@ CONFIG_ENV_ADDR=0x580500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0 diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 5a7ffe9c4a1..eb1aa453fe8 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -57,6 +57,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_INPHI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index ed6f78b0993..421f531d055 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -46,7 +46,6 @@ CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0 @@ -64,6 +63,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_INPHI=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index bb92fcb6c57..8c915b516ba 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -53,6 +53,7 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_INPHI=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 1d3b59c849c..9d4a4c0816e 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -45,7 +45,6 @@ CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_DEFAULT_BUS_NUMBER=0 @@ -62,6 +61,7 @@ CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_INPHI=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index d0d33840478..9666a8be794 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -47,7 +47,6 @@ CONFIG_ENV_ADDR=0x20500000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y CONFIG_SATA_CEVA=y -CONFIG_FSL_CAAM=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/mcm-imx8m-mini_defconfig b/configs/mcm-imx8m-mini_defconfig new file mode 100644 index 00000000000..cf388e99a5a --- /dev/null +++ b/configs/mcm-imx8m-mini_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MCM_IMX8M_MINI=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_LOCALVERSION="-mcm-imx8m-mini-1.0" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_CONSOLE_MUX=y +CONFIG_DEFAULT_FDT_FILE="mcm-imx8m-mini.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="mcm-imx8m-mini" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_NXP_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_EXT4_WRITE=y +CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER is not set +CONFIG_LED=y +CONFIG_LED_GPIO=y diff --git a/configs/mcm-imx8m-plus_defconfig b/configs/mcm-imx8m-plus_defconfig new file mode 100644 index 00000000000..88f2e44554d --- /dev/null +++ b/configs/mcm-imx8m-plus_defconfig @@ -0,0 +1,155 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x3F0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_MCM_IMX8M_PLUS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +# CONFIG_CMD_DATE is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_PWM=y +CONFIG_DM_RTC=y +CONFIG_RTC_ABX80X=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_LCD_STARTEK_ILI9881C=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_VIDEO_IMX_LCDIFV3=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_HEXDUMP is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig index 57da844e8d3..17a7a124a69 100644 --- a/configs/mx6dlarm2_defconfig +++ b/configs/mx6dlarm2_defconfig @@ -1,11 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6DL=y -CONFIG_TARGET_MX6QARM2=y +CONFIG_TARGET_MX6DLARM2=y # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,DDR_MB=2048" @@ -13,9 +12,12 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -29,13 +31,26 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_DEV=3 CONFIG_BOUNCE_BUFFER=y CONFIG_FSL_USDHC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6dl-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig index c1f4fed2cbe..5fc6e983e96 100644 --- a/configs/mx6dlarm2_lpddr2_defconfig +++ b/configs/mx6dlarm2_lpddr2_defconfig @@ -1,11 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6DL=y -CONFIG_TARGET_MX6QARM2=y +CONFIG_TARGET_MX6DLARM2=y # CONFIG_CMD_BMODE is not set CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL_LPDDR2,DDR_MB=512" @@ -13,9 +12,12 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -29,13 +31,26 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_DEV=3 CONFIG_BOUNCE_BUFFER=y CONFIG_FSL_USDHC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6dl-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_lpddr2_plugin_defconfig b/configs/mx6dlarm2_lpddr2_plugin_defconfig new file mode 100644 index 00000000000..a72cf775b61 --- /dev/null +++ b/configs/mx6dlarm2_lpddr2_plugin_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,MX6DL_LPDDR2,DDR_MB=512" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_BOUNCE_BUFFER=y +CONFIG_FSL_USDHC=y +CONFIG_MII=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6dl-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlarm2_plugin_defconfig b/configs/mx6dlarm2_plugin_defconfig new file mode 100644 index 00000000000..a73562670c4 --- /dev/null +++ b/configs/mx6dlarm2_plugin_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLARM2=y +CONFIG_USE_IMXIMG_PLUGIN=y +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage_mx6dl.cfg,DDR_MB=2048" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_BOUNCE_BUFFER=y +CONFIG_FSL_USDHC=y +CONFIG_MII=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6dl-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig new file mode 100644 index 00000000000..b55be27bec6 --- /dev/null +++ b/configs/mx6dlsabreauto_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_eimnor_defconfig b/configs/mx6dlsabreauto_eimnor_defconfig new file mode 100644 index 00000000000..add6d35a2ba --- /dev/null +++ b/configs/mx6dlsabreauto_eimnor_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_ADDR=0x080E0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CMD_FLASH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_nand_defconfig b/configs/mx6dlsabreauto_nand_defconfig new file mode 100644 index 00000000000..64cddcdbb0c --- /dev/null +++ b/configs/mx6dlsabreauto_nand_defconfig @@ -0,0 +1,95 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor,nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_optee_defconfig b/configs/mx6dlsabreauto_optee_defconfig new file mode 100644 index 00000000000..fb888c645d7 --- /dev/null +++ b/configs/mx6dlsabreauto_optee_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_plugin_defconfig b/configs/mx6dlsabreauto_plugin_defconfig new file mode 100644 index 00000000000..474dd2b022e --- /dev/null +++ b/configs/mx6dlsabreauto_plugin_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabreauto_spinor_defconfig b/configs/mx6dlsabreauto_spinor_defconfig new file mode 100644 index 00000000000..13594844614 --- /dev/null +++ b/configs/mx6dlsabreauto_spinor_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6dl.cfg" +CONFIG_SPI_BOOT=y +CONFIG_CMD_SF=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_MXC_SPI=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-ecspi" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig new file mode 100644 index 00000000000..a9c1a0ad7d8 --- /dev/null +++ b/configs/mx6dlsabresd_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABRESD=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabresd_epdc_defconfig b/configs/mx6dlsabresd_epdc_defconfig new file mode 100644 index 00000000000..5cee9e2466b --- /dev/null +++ b/configs/mx6dlsabresd_epdc_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABRESD=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_MXC_EPDC=y +CONFIG_LCD=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabresd_optee_defconfig b/configs/mx6dlsabresd_optee_defconfig new file mode 100644 index 00000000000..8f053690644 --- /dev/null +++ b/configs/mx6dlsabresd_optee_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABRESD=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6dlsabresd_plugin_defconfig b/configs/mx6dlsabresd_plugin_defconfig new file mode 100644 index 00000000000..791d73452ad --- /dev/null +++ b/configs/mx6dlsabresd_plugin_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6DL=y +CONFIG_TARGET_MX6DLSABRESD=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig index 180d5f9baa6..5c261f76c0c 100644 --- a/configs/mx6qarm2_defconfig +++ b/configs/mx6qarm2_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6Q=y CONFIG_TARGET_MX6QARM2=y # CONFIG_CMD_BMODE is not set @@ -13,9 +12,12 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -29,13 +31,26 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_DEV=3 CONFIG_BOUNCE_BUFFER=y CONFIG_FSL_USDHC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig index d481f686be0..1d48341b072 100644 --- a/configs/mx6qarm2_lpddr2_defconfig +++ b/configs/mx6qarm2_lpddr2_defconfig @@ -1,9 +1,8 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x60000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6Q=y CONFIG_TARGET_MX6QARM2=y # CONFIG_CMD_BMODE is not set @@ -13,9 +12,12 @@ CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y -CONFIG_CMD_GPIO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -29,13 +31,26 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_MMC_ENV_DEV=3 CONFIG_BOUNCE_BUFFER=y CONFIG_FSL_USDHC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_USB=y CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_lpddr2_plugin_defconfig b/configs/mx6qarm2_lpddr2_plugin_defconfig new file mode 100644 index 00000000000..0d05fa34658 --- /dev/null +++ b/configs/mx6qarm2_lpddr2_plugin_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QARM2=y +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6DQ_LPDDR2,DDR_MB=512" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_BOUNCE_BUFFER=y +CONFIG_FSL_USDHC=y +CONFIG_MII=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_plugin_defconfig b/configs/mx6qarm2_plugin_defconfig new file mode 100644 index 00000000000..8644947413a --- /dev/null +++ b/configs/mx6qarm2_plugin_defconfig @@ -0,0 +1,57 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QARM2=y +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,DDR_MB=2048" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_BOUNCE_BUFFER=y +CONFIG_FSL_USDHC=y +CONFIG_MII=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_pop_lpddr2_defconfig b/configs/mx6qarm2_pop_lpddr2_defconfig new file mode 100644 index 00000000000..a54d4691757 --- /dev/null +++ b/configs/mx6qarm2_pop_lpddr2_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QARM2=y +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg,MX6DQ_POP_LPDDR2,DDR_MB=256" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_BOUNCE_BUFFER=y +CONFIG_FSL_USDHC=y +CONFIG_MII=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-pop-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-pop-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qarm2_pop_lpddr2_revb_defconfig b/configs/mx6qarm2_pop_lpddr2_revb_defconfig new file mode 100644 index 00000000000..8c9212d9dde --- /dev/null +++ b/configs/mx6qarm2_pop_lpddr2_revb_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QARM2=y +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qarm2/mt128x64mx32.cfg,MX6DQ_POP_LPDDR2,DDR_MB=512" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_BOUNCE_BUFFER=y +CONFIG_FSL_USDHC=y +CONFIG_MII=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DEFAULT_DEVICE_TREE="imx6q-pop-arm2" +CONFIG_DEFAULT_FDT_FILE="imx6q-pop-arm2.dtb" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_OF_LIBFDT=y diff --git a/configs/mx6qpsabreauto_defconfig b/configs/mx6qpsabreauto_defconfig new file mode 100644 index 00000000000..20ebda46ab3 --- /dev/null +++ b/configs/mx6qpsabreauto_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_eimnor_defconfig b/configs/mx6qpsabreauto_eimnor_defconfig new file mode 100644 index 00000000000..c34f065f74e --- /dev/null +++ b/configs/mx6qpsabreauto_eimnor_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_ADDR=0x080E0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CMD_FLASH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_nand_defconfig b/configs/mx6qpsabreauto_nand_defconfig new file mode 100644 index 00000000000..ef0ea44f04a --- /dev/null +++ b/configs/mx6qpsabreauto_nand_defconfig @@ -0,0 +1,96 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor,nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_optee_defconfig b/configs/mx6qpsabreauto_optee_defconfig new file mode 100644 index 00000000000..f642bc760e2 --- /dev/null +++ b/configs/mx6qpsabreauto_optee_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_plugin_defconfig b/configs/mx6qpsabreauto_plugin_defconfig new file mode 100644 index 00000000000..5ce6cf0ecb5 --- /dev/null +++ b/configs/mx6qpsabreauto_plugin_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabreauto_sata_defconfig b/configs/mx6qpsabreauto_sata_defconfig new file mode 100644 index 00000000000..d3cdcc224dd --- /dev/null +++ b/configs/mx6qpsabreauto_sata_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_SATA_BOOT=y +CONFIG_ENV_IS_IN_SATA=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y diff --git a/configs/mx6qpsabreauto_spinor_defconfig b/configs/mx6qpsabreauto_spinor_defconfig new file mode 100644 index 00000000000..9116ad8bb9e --- /dev/null +++ b/configs/mx6qpsabreauto_spinor_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6qp.cfg" +CONFIG_SPI_BOOT=y +CONFIG_CMD_SF=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_MXC_SPI=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabreauto-ecspi" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabresd_defconfig b/configs/mx6qpsabresd_defconfig new file mode 100644 index 00000000000..d4d09c4cef3 --- /dev/null +++ b/configs/mx6qpsabresd_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABRESD=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6qp.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabresd_optee_defconfig b/configs/mx6qpsabresd_optee_defconfig new file mode 100644 index 00000000000..b56a69c68b1 --- /dev/null +++ b/configs/mx6qpsabresd_optee_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABRESD=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6qp.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qpsabresd_sata_defconfig b/configs/mx6qpsabresd_sata_defconfig new file mode 100644 index 00000000000..161fa92a657 --- /dev/null +++ b/configs/mx6qpsabresd_sata_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6QP=y +CONFIG_TARGET_MX6QPSABRESD=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6qp.cfg" +CONFIG_SATA_BOOT=y +CONFIG_ENV_IS_IN_SATA=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6qp-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig new file mode 100644 index 00000000000..89b3cee6560 --- /dev/null +++ b/configs/mx6qsabreauto_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_eimnor_defconfig b/configs/mx6qsabreauto_eimnor_defconfig new file mode 100644 index 00000000000..2f0cd03486d --- /dev/null +++ b/configs/mx6qsabreauto_eimnor_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_ADDR=0x080E0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CMD_FLASH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_nand_defconfig b/configs/mx6qsabreauto_nand_defconfig new file mode 100644 index 00000000000..db6371e5a86 --- /dev/null +++ b/configs/mx6qsabreauto_nand_defconfig @@ -0,0 +1,96 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor,nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_optee_defconfig b/configs/mx6qsabreauto_optee_defconfig new file mode 100644 index 00000000000..73b4559a018 --- /dev/null +++ b/configs/mx6qsabreauto_optee_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_plugin_defconfig b/configs/mx6qsabreauto_plugin_defconfig new file mode 100644 index 00000000000..41de6d0b667 --- /dev/null +++ b/configs/mx6qsabreauto_plugin_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabreauto_sata_defconfig b/configs/mx6qsabreauto_sata_defconfig new file mode 100644 index 00000000000..a8552139b11 --- /dev/null +++ b/configs/mx6qsabreauto_sata_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_SATA_BOOT=y +CONFIG_ENV_IS_IN_SATA=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y diff --git a/configs/mx6qsabreauto_spinor_defconfig b/configs/mx6qsabreauto_spinor_defconfig new file mode 100644 index 00000000000..d649f76b345 --- /dev/null +++ b/configs/mx6qsabreauto_spinor_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6Q=y +CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/imximage.cfg" +CONFIG_SPI_BOOT=y +CONFIG_CMD_SF=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_MXC_SPI=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabreauto-ecspi" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig new file mode 100644 index 00000000000..862723df0a7 --- /dev/null +++ b/configs/mx6qsabresd_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABRESD=y +CONFIG_MX6Q=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabresd_optee_defconfig b/configs/mx6qsabresd_optee_defconfig new file mode 100644 index 00000000000..8306762ec09 --- /dev/null +++ b/configs/mx6qsabresd_optee_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABRESD=y +CONFIG_MX6Q=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabresd_plugin_defconfig b/configs/mx6qsabresd_plugin_defconfig new file mode 100644 index 00000000000..af387fb71b5 --- /dev/null +++ b/configs/mx6qsabresd_plugin_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABRESD=y +CONFIG_MX6Q=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6qsabresd_sata_defconfig b/configs/mx6qsabresd_sata_defconfig new file mode 100644 index 00000000000..270f398ee5d --- /dev/null +++ b/configs/mx6qsabresd_sata_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6QSABRESD=y +CONFIG_MX6Q=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg" +CONFIG_SATA_BOOT=y +CONFIG_ENV_IS_IN_SATA=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6q-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_AHCI=y +CONFIG_IMX_AHCI=y +CONFIG_DM_SCSI=y +CONFIG_SCSI=y +CONFIG_CMD_SCSI=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 5fd78c3629a..1689e154614 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -1,20 +1,21 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x80000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6SL=y CONFIG_TARGET_MX6SLEVK=y CONFIG_DM_GPIO=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -67,5 +68,22 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6slevk_epdc_defconfig b/configs/mx6slevk_epdc_defconfig new file mode 100644 index 00000000000..9f72176c71a --- /dev/null +++ b/configs/mx6slevk_epdc_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SL=y +CONFIG_TARGET_MX6SLEVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_DM=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_LCD=y +CONFIG_MXC_EPDC=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6slevk_optee_defconfig b/configs/mx6slevk_optee_defconfig new file mode 100644 index 00000000000..9075f0d2c6a --- /dev/null +++ b/configs/mx6slevk_optee_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SL=y +CONFIG_TARGET_MX6SLEVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_DM=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6slevk_plugin_defconfig b/configs/mx6slevk_plugin_defconfig new file mode 100644 index 00000000000..808bc88aeac --- /dev/null +++ b/configs/mx6slevk_plugin_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SL=y +CONFIG_TARGET_MX6SLEVK=y +CONFIG_DM_GPIO=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_DM=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 9777166727e..6da00a293af 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -1,25 +1,27 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_MX6SL=y CONFIG_TARGET_MX6SLEVK=y CONFIG_DM_GPIO=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6sl-evk" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg" CONFIG_SPI_BOOT=y CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -35,6 +37,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y @@ -69,3 +72,19 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sll_lpddr2_val_defconfig b/configs/mx6sll_lpddr2_val_defconfig new file mode 100644 index 00000000000..18ee4f04c51 --- /dev/null +++ b/configs/mx6sll_lpddr2_val_defconfig @@ -0,0 +1,63 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_val/imximage_lpddr2.cfg" +CONFIG_LPDDR2_BOARD=y +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SLL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr2-val" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr2-val.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y diff --git a/configs/mx6sll_lpddr3_val_defconfig b/configs/mx6sll_lpddr3_val_defconfig new file mode 100644 index 00000000000..9c661f8db20 --- /dev/null +++ b/configs/mx6sll_lpddr3_val_defconfig @@ -0,0 +1,62 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SLL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y diff --git a/configs/mx6sll_lpddr3_val_epdc_defconfig b/configs/mx6sll_lpddr3_val_epdc_defconfig new file mode 100644 index 00000000000..c239846b203 --- /dev/null +++ b/configs/mx6sll_lpddr3_val_epdc_defconfig @@ -0,0 +1,64 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SLL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VIDEO=y +CONFIG_MXC_EPDC=y +CONFIG_LCD=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y diff --git a/configs/mx6sll_lpddr3_val_plugin_defconfig b/configs/mx6sll_lpddr3_val_plugin_defconfig new file mode 100644 index 00000000000..61aca5057ad --- /dev/null +++ b/configs/mx6sll_lpddr3_val_plugin_defconfig @@ -0,0 +1,63 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SLL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y diff --git a/configs/mx6sll_lpddr3_val_spinor_defconfig b/configs/mx6sll_lpddr3_val_spinor_defconfig new file mode 100644 index 00000000000..50ad708076d --- /dev/null +++ b/configs/mx6sll_lpddr3_val_spinor_defconfig @@ -0,0 +1,74 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sll_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6SLL_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SLL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_CMD_BMODE is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SPI_BOOT=y +CONFIG_MXC_SPI=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-lpddr3-val-ecspi" +CONFIG_DEFAULT_FDT_FILE="imx6sll-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index 1e446a3e439..7c1068e55d4 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -1,21 +1,21 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6SLL=y CONFIG_TARGET_MX6SLLEVK=y CONFIG_DM_GPIO=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" +CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -23,6 +23,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y @@ -52,6 +53,30 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y + +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sllevk_epdc_defconfig b/configs/mx6sllevk_epdc_defconfig new file mode 100644 index 00000000000..6ecd35138b7 --- /dev/null +++ b/configs/mx6sllevk_epdc_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SLL=y +CONFIG_TARGET_MX6SLLEVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" +CONFIG_MXC_EPDC=y +CONFIG_LCD=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sllevk_optee_defconfig b/configs/mx6sllevk_optee_defconfig new file mode 100644 index 00000000000..2c9f04d0ebb --- /dev/null +++ b/configs/mx6sllevk_optee_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SLL=y +CONFIG_TARGET_MX6SLLEVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y + +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 3e0e1006b96..16fae55e978 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -1,22 +1,22 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6SLL=y CONFIG_TARGET_MX6SLLEVK=y CONFIG_DM_GPIO=y CONFIG_USE_IMXIMG_PLUGIN=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6sll-evk" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sllevk/imximage.cfg" +CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -24,6 +24,7 @@ CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y @@ -56,3 +57,26 @@ CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y + +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_defconfig b/configs/mx6solosabreauto_defconfig new file mode 100644 index 00000000000..59c790a796d --- /dev/null +++ b/configs/mx6solosabreauto_defconfig @@ -0,0 +1,89 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6S=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_eimnor_defconfig b/configs/mx6solosabreauto_eimnor_defconfig new file mode 100644 index 00000000000..22b941715eb --- /dev/null +++ b/configs/mx6solosabreauto_eimnor_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6S=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_ADDR=0x080E0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_FLASH_CFI_DRIVER=y +CONFIG_CMD_FLASH=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_nand_defconfig b/configs/mx6solosabreauto_nand_defconfig new file mode 100644 index 00000000000..092657afd04 --- /dev/null +++ b/configs/mx6solosabreauto_nand_defconfig @@ -0,0 +1,96 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6S=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor,nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-gpmi-weim" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_optee_defconfig b/configs/mx6solosabreauto_optee_defconfig new file mode 100644 index 00000000000..6b987b4cf99 --- /dev/null +++ b/configs/mx6solosabreauto_optee_defconfig @@ -0,0 +1,90 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6S=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabreauto_spinor_defconfig b/configs/mx6solosabreauto_spinor_defconfig new file mode 100644 index 00000000000..781b1e46988 --- /dev/null +++ b/configs/mx6solosabreauto_spinor_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6S=y +CONFIG_TARGET_MX6SOLOSABREAUTO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabreauto/mx6solo.cfg" +CONFIG_SPI_BOOT=y +CONFIG_CMD_SF=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_MXC_SPI=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabreauto-ecspi" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabresd_defconfig b/configs/mx6solosabresd_defconfig new file mode 100644 index 00000000000..b56dc278328 --- /dev/null +++ b/configs/mx6solosabresd_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6S=y +CONFIG_TARGET_MX6SOLOSABRESD=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6solosabresd_optee_defconfig b/configs/mx6solosabresd_optee_defconfig new file mode 100644 index 00000000000..3add8470adf --- /dev/null +++ b/configs/mx6solosabresd_optee_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_MX6S=y +CONFIG_TARGET_MX6SOLOSABRESD=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP32 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MXC_UART=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +# CONFIG_VIDEO_SW_CURSOR is not set +# CONFIG_OF_LIBFDT=y + +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-sabresd" +CONFIG_OF_CONTROL=y +CONFIG_DM_GPIO=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x12C00000 +CONFIG_FASTBOOT_BUF_SIZE=0x10000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sx_14x14_lpddr2_val_defconfig b/configs/mx6sx_14x14_lpddr2_val_defconfig new file mode 100644 index 00000000000..56fe7cee70a --- /dev/null +++ b/configs/mx6sx_14x14_lpddr2_val_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_14X14_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-val.dtb" +CONFIG_LPDDR2_BOARD=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_14x14_lpddr2_val_nand_defconfig b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig new file mode 100644 index 00000000000..a6507e6e0fc --- /dev/null +++ b/configs/mx6sx_14x14_lpddr2_val_nand_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_14X14_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_NAND_BOOT=y +CONFIG_LPDDR2_BOARD=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig new file mode 100644 index 00000000000..f7a8461b903 --- /dev/null +++ b/configs/mx6sx_14x14_lpddr2_val_plugin_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_14X14_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-14x14-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/mx6sx_14x14_lpddr2_val.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-14x14-val.dtb" +CONFIG_LPDDR2_BOARD=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_defconfig b/configs/mx6sx_17x17_val_defconfig new file mode 100644 index 00000000000..e4050198229 --- /dev/null +++ b/configs/mx6sx_17x17_val_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_eimnor_defconfig b/configs/mx6sx_17x17_val_eimnor_defconfig new file mode 100644 index 00000000000..0c213b53a09 --- /dev/null +++ b/configs/mx6sx_17x17_val_eimnor_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_ADDR=0x501C0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_nand_defconfig b/configs/mx6sx_17x17_val_nand_defconfig new file mode 100644 index 00000000000..b0e50a12c40 --- /dev/null +++ b/configs/mx6sx_17x17_val_nand_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_plugin_defconfig b/configs/mx6sx_17x17_val_plugin_defconfig new file mode 100644 index 00000000000..e866b7b0c13 --- /dev/null +++ b/configs/mx6sx_17x17_val_plugin_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_qspi2_defconfig b/configs/mx6sx_17x17_val_qspi2_defconfig new file mode 100644 index 00000000000..b2fcf68f477 --- /dev/null +++ b/configs/mx6sx_17x17_val_qspi2_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17_val_spinor_defconfig b/configs/mx6sx_17x17_val_spinor_defconfig new file mode 100644 index 00000000000..40f0454e5c1 --- /dev/null +++ b/configs/mx6sx_17x17_val_spinor_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val-ecspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_17x17wp_val_defconfig b/configs/mx6sx_17x17wp_val_defconfig new file mode 100644 index 00000000000..b808df0bdc1 --- /dev/null +++ b/configs/mx6sx_17x17wp_val_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_17X17_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-17x17-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_17x17_val/imximage_wp.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-17x17-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_defconfig b/configs/mx6sx_19x19_ddr3_val_defconfig new file mode 100644 index 00000000000..83b2519f1f6 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig new file mode 100644 index 00000000000..555303df736 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_eimnor_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_ADDR=0x500E0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_nand_defconfig b/configs/mx6sx_19x19_ddr3_val_nand_defconfig new file mode 100644 index 00000000000..5f65772900e --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_nand_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val-gpmi-weim" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_ETH=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_plugin_defconfig b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig new file mode 100644 index 00000000000..19f1464d243 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_plugin_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig new file mode 100644 index 00000000000..e09a4bd06fa --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_qspi2_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_ddr3_val_spinor_defconfig b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig new file mode 100644 index 00000000000..ef149839775 --- /dev/null +++ b/configs/mx6sx_19x19_ddr3_val_spinor_defconfig @@ -0,0 +1,81 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val-ecspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=5 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_lpddr2_val_defconfig b/configs/mx6sx_19x19_lpddr2_val_defconfig new file mode 100644 index 00000000000..ae93be649b5 --- /dev/null +++ b/configs/mx6sx_19x19_lpddr2_val_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg" +CONFIG_LPDDR2_BOARD=y +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig new file mode 100644 index 00000000000..f1b9c65a220 --- /dev/null +++ b/configs/mx6sx_19x19_lpddr2_val_plugin_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg" +CONFIG_LPDDR2_BOARD=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig new file mode 100644 index 00000000000..f75f59393ce --- /dev/null +++ b/configs/mx6sx_19x19_lpddr2_val_qspi2_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x81000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SX_19X19_VAL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-19x19-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sx_19x19_val/imximage_lpddr2.cfg" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_QSPI_BOOT=y +CONFIG_LPDDR2_BOARD=y +CONFIG_DEFAULT_FDT_FILE="imx6sx-19x19-val.dtb" +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_VIDEO=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_SF=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_ETH=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index 0d8c07b57d8..94902530309 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -1,23 +1,28 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x80000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_MX6SX=y CONFIG_TARGET_MX6SXSABREAUTO=y CONFIG_DM_GPIO=y -# CONFIG_CMD_BMODE is not set CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" +CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y @@ -42,13 +47,11 @@ CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_PHY_ATHEROS=y -CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y @@ -67,3 +70,32 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y + + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabreauto_nand_defconfig b/configs/mx6sxsabreauto_nand_defconfig new file mode 100644 index 00000000000..35d1f32a8fa --- /dev/null +++ b/configs/mx6sxsabreauto_nand_defconfig @@ -0,0 +1,109 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y + + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabreauto_optee_defconfig b/configs/mx6sxsabreauto_optee_defconfig new file mode 100644 index 00000000000..5cee3b15b43 --- /dev/null +++ b/configs/mx6sxsabreauto_optee_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_IMX_OPTEE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabreauto_plugin_defconfig b/configs/mx6sxsabreauto_plugin_defconfig new file mode 100644 index 00000000000..b3ad2b6c0ce --- /dev/null +++ b/configs/mx6sxsabreauto_plugin_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_DM_GPIO=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y + + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabreauto_qspi1_defconfig b/configs/mx6sxsabreauto_qspi1_defconfig new file mode 100644 index 00000000000..ee1d8e07f5b --- /dev/null +++ b/configs/mx6sxsabreauto_qspi1_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SXSABREAUTO=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sabreauto" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabreauto/imximage.cfg" +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_VIDEO=y +CONFIG_SYS_CONSOLE_IS_IN_ENV=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index af5acc178f2..607e98e1280 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -1,21 +1,23 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6SX=y CONFIG_TARGET_MX6SXSABRESD=y CONFIG_DM_GPIO=y -# CONFIG_CMD_BMODE is not set CONFIG_NXP_BOARD_REVISION=y CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -28,6 +30,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -36,7 +39,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_SYS_MMC_ENV_DEV=3 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y @@ -49,11 +52,10 @@ CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y -CONFIG_PHYLIB=y -CONFIG_PHY_ATHEROS=y -CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y @@ -72,5 +74,32 @@ CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabresd_emmc_defconfig b/configs/mx6sxsabresd_emmc_defconfig new file mode 100644 index 00000000000..16e8c1b0b98 --- /dev/null +++ b/configs/mx6sxsabresd_emmc_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_DM_GPIO=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb-emmc" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_MX6SXSABRESD_EMMC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabresd_m4fastup_defconfig b/configs/mx6sxsabresd_m4fastup_defconfig new file mode 100644 index 00000000000..254c332b90e --- /dev/null +++ b/configs/mx6sxsabresd_m4fastup_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_DM_GPIO=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,SYS_AUXCORE_FASTUP" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y diff --git a/configs/mx6sxsabresd_optee_defconfig b/configs/mx6sxsabresd_optee_defconfig new file mode 100644 index 00000000000..411e65ef887 --- /dev/null +++ b/configs/mx6sxsabresd_optee_defconfig @@ -0,0 +1,106 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_DM_GPIO=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_IMX_OPTEE=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabresd_plugin_defconfig b/configs/mx6sxsabresd_plugin_defconfig new file mode 100644 index 00000000000..9bdf409b849 --- /dev/null +++ b/configs/mx6sxsabresd_plugin_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_DM_GPIO=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6sxsabresd_qspi2_defconfig b/configs/mx6sxsabresd_qspi2_defconfig new file mode 100644 index 00000000000..b1368cdaf84 --- /dev/null +++ b/configs/mx6sxsabresd_qspi2_defconfig @@ -0,0 +1,109 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6SX=y +CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_DM_GPIO=y +CONFIG_NXP_BOARD_REVISION=y +CONFIG_DEFAULT_DEVICE_TREE="imx6sx-sdb" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=3 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO=y + +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_IMX_BOOTAUX=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_ddr3_val_defconfig b/configs/mx6ul_14x14_ddr3_val_defconfig new file mode 100644 index 00000000000..bb97f951a0d --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig new file mode 100644 index 00000000000..58bd8fb80e2 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_eimnor_defconfig @@ -0,0 +1,62 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_ADDR=0x501C0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_NET=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_STORAGE=y +CONFIG_MMC=n diff --git a/configs/mx6ul_14x14_ddr3_val_emmc_defconfig b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig new file mode 100644 index 00000000000..2e33849ce21 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_emmc_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val-emmc" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_MX6UL_DDR3_VAL_EMMC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_nand_defconfig b/configs/mx6ul_14x14_ddr3_val_nand_defconfig new file mode 100644 index 00000000000..5269f33b9f7 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_nand_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3c00000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val-gpmi-weim" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_plugin_defconfig b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig new file mode 100644 index 00000000000..f4b80019b27 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_plugin_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig new file mode 100644 index 00000000000..74a3cfe7bb4 --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_qspi1_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_ddr3_val_spinor_defconfig b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig new file mode 100644 index 00000000000..3bc6c44cc0f --- /dev/null +++ b/configs/mx6ul_14x14_ddr3_val_spinor_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-ddr3-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_ddr3_val/imximage.cfg" +CONFIG_SPI_BOOT=y +CONFIG_MXC_SPI=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index f4a3a4a8f84..38f606ad21e 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -1,40 +1,28 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6UL=y CONFIG_TARGET_MX6UL_14X14_EVK=y CONFIG_DM_GPIO=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_USB_HOST_SUPPORT=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -42,6 +30,7 @@ CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -54,7 +43,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y -CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y @@ -85,14 +73,27 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="FSL" -CONFIG_USB_GADGET_VENDOR_NUM=0x0525 -CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 -CONFIG_CI_UDC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_emmc_defconfig b/configs/mx6ul_14x14_evk_emmc_defconfig new file mode 100644 index 00000000000..87b2c54274d --- /dev/null +++ b/configs/mx6ul_14x14_evk_emmc_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk-emmc" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_nand_defconfig b/configs/mx6ul_14x14_evk_nand_defconfig new file mode 100644 index 00000000000..ecc6e263381 --- /dev/null +++ b/configs/mx6ul_14x14_evk_nand_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3c00000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk-gpmi-weim" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_optee_defconfig b/configs/mx6ul_14x14_evk_optee_defconfig new file mode 100644 index 00000000000..a12cf788797 --- /dev/null +++ b/configs/mx6ul_14x14_evk_optee_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_plugin_defconfig b/configs/mx6ul_14x14_evk_plugin_defconfig new file mode 100644 index 00000000000..91a821ca055 --- /dev/null +++ b/configs/mx6ul_14x14_evk_plugin_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_qspi1_defconfig b/configs/mx6ul_14x14_evk_qspi1_defconfig new file mode 100644 index 00000000000..02cd1214634 --- /dev/null +++ b/configs/mx6ul_14x14_evk_qspi1_defconfig @@ -0,0 +1,102 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_14x14_evk_spl_defconfig b/configs/mx6ul_14x14_evk_spl_defconfig new file mode 100644 index 00000000000..f4a3a4a8f84 --- /dev/null +++ b/configs/mx6ul_14x14_evk_spl_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xC0000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_USB_HOST_SUPPORT=y +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y diff --git a/configs/mx6ul_14x14_lpddr2_val_defconfig b/configs/mx6ul_14x14_lpddr2_val_defconfig new file mode 100644 index 00000000000..f052176d1b5 --- /dev/null +++ b/configs/mx6ul_14x14_lpddr2_val_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_LPDDR2_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-lpddr2-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-lpddr2-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig new file mode 100644 index 00000000000..92da102b94b --- /dev/null +++ b/configs/mx6ul_14x14_lpddr2_val_eimnor_defconfig @@ -0,0 +1,66 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6UL_14X14_LPDDR2_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_ADDR=0x501C0000 +CONFIG_MX6UL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-14x14-lpddr2-val" +CONFIG_DEFAULT_FDT_FILE="imx6ul-14x14-lpddr2-val.dtb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_lpddr2_val/imximage.cfg" +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_SYS_FLASH_PROTECTION=y +CONFIG_ENV_IS_IN_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_I2C=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 28a0806fb2b..e697abe2e10 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -1,42 +1,34 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 -CONFIG_SPL_GPIO_SUPPORT=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x80000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6UL=y CONFIG_TARGET_MX6UL_9X9_EVK=y CONFIG_DM_GPIO=y -CONFIG_SPL_TEXT_BASE=0x00908000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg" +CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_SPL_FS_EXT4=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_WATCHDOG_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -49,6 +41,7 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y @@ -62,6 +55,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_DM_ETH=y CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y @@ -80,9 +74,27 @@ CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y CONFIG_DM_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_VIDEO_BMP_RLE8=y CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_9x9_evk_optee_defconfig b/configs/mx6ul_9x9_evk_optee_defconfig new file mode 100644 index 00000000000..06c2f5982b2 --- /dev/null +++ b/configs/mx6ul_9x9_evk_optee_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_9x9_evk_plugin_defconfig b/configs/mx6ul_9x9_evk_plugin_defconfig new file mode 100644 index 00000000000..e8892159822 --- /dev/null +++ b/configs/mx6ul_9x9_evk_plugin_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_9x9_evk_qspi1_defconfig b/configs/mx6ul_9x9_evk_qspi1_defconfig new file mode 100644 index 00000000000..8bd671d1fc1 --- /dev/null +++ b/configs/mx6ul_9x9_evk_qspi1_defconfig @@ -0,0 +1,103 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ul_14x14_evk/imximage_lpddr2.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ul_9x9_evk_spl_defconfig b/configs/mx6ul_9x9_evk_spl_defconfig new file mode 100644 index 00000000000..28a0806fb2b --- /dev/null +++ b/configs/mx6ul_9x9_evk_spl_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x87800000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x80000 +CONFIG_MX6UL=y +CONFIG_TARGET_MX6UL_9X9_EVK=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x00908000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ul-9x9-evk" +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_FS_EXT4=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y diff --git a/configs/mx6ull_14x14_ddr3_val_defconfig b/configs/mx6ull_14x14_ddr3_val_defconfig new file mode 100644 index 00000000000..8b09f465516 --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_val_defconfig @@ -0,0 +1,75 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ull_14x14_ddr3_val_emmc_defconfig b/configs/mx6ull_14x14_ddr3_val_emmc_defconfig new file mode 100644 index 00000000000..ec1f325a3ee --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_val_emmc_defconfig @@ -0,0 +1,67 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-emmc" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb" +CONFIG_MX6ULL_DDR3_VAL_EMMC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ull_14x14_ddr3_val_epdc_defconfig b/configs/mx6ull_14x14_ddr3_val_epdc_defconfig new file mode 100644 index 00000000000..c0da6c73854 --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_val_epdc_defconfig @@ -0,0 +1,77 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_DM_GPIO=y +CONFIG_VIDEO=y +CONFIG_LCD=y +CONFIG_MXC_EPDC=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-epdc" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6ull_14x14_ddr3_val_nand_defconfig b/configs/mx6ull_14x14_ddr3_val_nand_defconfig new file mode 100644 index 00000000000..a6fa6843cb5 --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_val_nand_defconfig @@ -0,0 +1,75 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3c00000 +CONFIG_MX6ULL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-gpmi-weim" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ull_14x14_ddr3_val_plugin_defconfig b/configs/mx6ull_14x14_ddr3_val_plugin_defconfig new file mode 100644 index 00000000000..89f556daf4a --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_val_plugin_defconfig @@ -0,0 +1,76 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig b/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig new file mode 100644 index 00000000000..1fe4f1f6da8 --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_val_qspi1_defconfig @@ -0,0 +1,77 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6ULL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb" +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ull_14x14_ddr3_val_spinor_defconfig b/configs/mx6ull_14x14_ddr3_val_spinor_defconfig new file mode 100644 index 00000000000..ae600bf9a9c --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_val_spinor_defconfig @@ -0,0 +1,78 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6ULL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb" +CONFIG_SPI_BOOT=y +CONFIG_MXC_SPI=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=1 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ull_14x14_ddr3_val_tsc_defconfig b/configs/mx6ull_14x14_ddr3_val_tsc_defconfig new file mode 100644 index 00000000000..838231c2627 --- /dev/null +++ b/configs/mx6ull_14x14_ddr3_val_tsc_defconfig @@ -0,0 +1,76 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ull_ddr3_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6ULL_DDR3_VAL=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_DM_GPIO=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-ddr3-val-tsc" +CONFIG_DEFAULT_FDT_FILE="imx6ull-14x14-ddr3-val.dtb" +CONFIG_MX6ULL_DDR3_VAL_TSC_REWORK=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_VIDEO=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 2696bd8811b..a57618f230f 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -1,27 +1,32 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6ULL=y CONFIG_TARGET_MX6ULL_14X14_EVK=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" +CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -58,5 +63,32 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y CONFIG_FSL_QSPI=y CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_14x14_evk_emmc_defconfig b/configs/mx6ull_14x14_evk_emmc_defconfig new file mode 100644 index 00000000000..2c84f54cc6d --- /dev/null +++ b/configs/mx6ull_14x14_evk_emmc_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk-emmc" +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_14x14_evk_nand_defconfig b/configs/mx6ull_14x14_evk_nand_defconfig new file mode 100644 index 00000000000..6e97f562867 --- /dev/null +++ b/configs/mx6ull_14x14_evk_nand_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3c00000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk-gpmi-weim" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_14x14_evk_optee_defconfig b/configs/mx6ull_14x14_evk_optee_defconfig new file mode 100644 index 00000000000..fccb277e13d --- /dev/null +++ b/configs/mx6ull_14x14_evk_optee_defconfig @@ -0,0 +1,95 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 2e08c99a3ca..a55ebd30b53 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -1,28 +1,33 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6ULL=y CONFIG_TARGET_MX6ULL_14X14_EVK=y CONFIG_DM_GPIO=y CONFIG_USE_IMXIMG_PLUGIN=y CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" +CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -54,8 +59,36 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y CONFIG_FSL_QSPI=y CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_14x14_evk_qspi1_defconfig b/configs/mx6ull_14x14_evk_qspi1_defconfig new file mode 100644 index 00000000000..89e05407617 --- /dev/null +++ b/configs/mx6ull_14x14_evk_qspi1_defconfig @@ -0,0 +1,96 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_9x9_evk_defconfig b/configs/mx6ull_9x9_evk_defconfig new file mode 100644 index 00000000000..d338c0fa657 --- /dev/null +++ b/configs/mx6ull_9x9_evk_defconfig @@ -0,0 +1,96 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_9X9_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-9x9-evk" +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage_lpddr2.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_9x9_evk_plugin_defconfig b/configs/mx6ull_9x9_evk_plugin_defconfig new file mode 100644 index 00000000000..e2183a9d488 --- /dev/null +++ b/configs/mx6ull_9x9_evk_plugin_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_9X9_EVK=y +CONFIG_DM_GPIO=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-9x9-evk" +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage_lpddr2.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ull_9x9_evk_qspi1_defconfig b/configs/mx6ull_9x9_evk_qspi1_defconfig new file mode 100644 index 00000000000..300a197a395 --- /dev/null +++ b/configs/mx6ull_9x9_evk_qspi1_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_9X9_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ull-9x9-evk" +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage_lpddr2.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ8XXX=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index 71801208adb..0ae649f6157 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -1,25 +1,32 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x87800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_MX6ULL=y CONFIG_TARGET_MX6ULL_14X14_EVK=y CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" +CONFIG_BOOTDELAY=3 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -31,22 +38,49 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y -# CONFIG_NET is not set CONFIG_BOUNCE_BUFFER=y CONFIG_DM_74X164=y CONFIG_DM_I2C=y CONFIG_DM_MMC=y -CONFIG_FSL_ESDHC_IMX=y +CONFIG_FSL_USDHC=y CONFIG_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_MODE=0 CONFIG_SF_DEFAULT_SPEED=40000000 CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y CONFIG_FSL_QSPI=y CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y \ No newline at end of file diff --git a/configs/mx6ulz_14x14_evk_emmc_defconfig b/configs/mx6ulz_14x14_evk_emmc_defconfig new file mode 100644 index 00000000000..28f3a8659ef --- /dev/null +++ b/configs/mx6ulz_14x14_evk_emmc_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk-emmc" +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y \ No newline at end of file diff --git a/configs/mx6ulz_14x14_evk_nand_defconfig b/configs/mx6ulz_14x14_evk_nand_defconfig new file mode 100644 index 00000000000..61d8e1f204d --- /dev/null +++ b/configs/mx6ulz_14x14_evk_nand_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3c00000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk-gpmi-weim" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y \ No newline at end of file diff --git a/configs/mx6ulz_14x14_evk_optee_defconfig b/configs/mx6ulz_14x14_evk_optee_defconfig new file mode 100644 index 00000000000..14e77c76a3b --- /dev/null +++ b/configs/mx6ulz_14x14_evk_optee_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y \ No newline at end of file diff --git a/configs/mx6ulz_14x14_evk_qspi1_defconfig b/configs/mx6ulz_14x14_evk_qspi1_defconfig new file mode 100644 index 00000000000..199affd221a --- /dev/null +++ b/configs/mx6ulz_14x14_evk_qspi1_defconfig @@ -0,0 +1,88 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_MX6ULL=y +CONFIG_TARGET_MX6ULL_14X14_EVK=y +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx6ulz-14x14-evk" +CONFIG_BOOTDELAY=3 +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_NET=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_PHYLIB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7d_12x12_ddr3_val_defconfig b/configs/mx7d_12x12_ddr3_val_defconfig new file mode 100644 index 00000000000..0a02496aa2e --- /dev/null +++ b/configs/mx7d_12x12_ddr3_val_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7D_12X12_DDR3_VAL=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-ddr3-val" +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_ddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-ddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y diff --git a/configs/mx7d_12x12_lpddr3_val_defconfig b/configs/mx7d_12x12_lpddr3_val_defconfig new file mode 100644 index 00000000000..d40ff94edf5 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_val_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_val_epdc_defconfig b/configs/mx7d_12x12_lpddr3_val_epdc_defconfig new file mode 100644 index 00000000000..5809826ff5d --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_val_epdc_defconfig @@ -0,0 +1,84 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb" +CONFIG_LCD=y +CONFIG_MXC_EPDC=y +CONFIG_CMD_BMP=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_val_optee_defconfig b/configs/mx7d_12x12_lpddr3_val_optee_defconfig new file mode 100644 index 00000000000..cae0ef53a4c --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_val_optee_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +CONFIG_IMX_OPTEE=y +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_val_qspi1_defconfig b/configs/mx7d_12x12_lpddr3_val_qspi1_defconfig new file mode 100644 index 00000000000..2a60a664b1e --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_val_qspi1_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val-qspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_FSL_QSPI=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y +CONFIG_QSPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_DM_ETH=y diff --git a/configs/mx7d_12x12_lpddr3_val_spinor_defconfig b/configs/mx7d_12x12_lpddr3_val_spinor_defconfig new file mode 100644 index 00000000000..04a6fc623d1 --- /dev/null +++ b/configs/mx7d_12x12_lpddr3_val_spinor_defconfig @@ -0,0 +1,97 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7D_12X12_LPDDR3_VAL=y +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-12x12-lpddr3-val-ecspi" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_lpddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-12x12-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_MXC_SPI=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y +CONFIG_DM_ETH=y +CONFIG_SPI_BOOT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set diff --git a/configs/mx7d_19x19_ddr3_val_defconfig b/configs/mx7d_19x19_ddr3_val_defconfig new file mode 100644 index 00000000000..b03a6d6a64b --- /dev/null +++ b/configs/mx7d_19x19_ddr3_val_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7D_19X19_DDR3_VAL=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_VIDEO=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-ddr3-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_ddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-ddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_FSL_QSPI=y +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y diff --git a/configs/mx7d_19x19_lpddr2_val_defconfig b/configs/mx7d_19x19_lpddr2_val_defconfig new file mode 100644 index 00000000000..fe1534170bb --- /dev/null +++ b/configs/mx7d_19x19_lpddr2_val_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR2_VAL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr2-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_val/imximage_lpddr2.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr2-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y diff --git a/configs/mx7d_19x19_lpddr3_val_defconfig b/configs/mx7d_19x19_lpddr3_val_defconfig new file mode 100644 index 00000000000..c7ace91e9c5 --- /dev/null +++ b/configs/mx7d_19x19_lpddr3_val_defconfig @@ -0,0 +1,80 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR3_VAL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CMD_FLASH=y diff --git a/configs/mx7d_19x19_lpddr3_val_eimnor_defconfig b/configs/mx7d_19x19_lpddr3_val_eimnor_defconfig new file mode 100644 index 00000000000..9a11d4436d4 --- /dev/null +++ b/configs/mx7d_19x19_lpddr3_val_eimnor_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_ENV_ADDR=0x281C0000 +CONFIG_DM_GPIO=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR3_VAL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y +CONFIG_NOR=y +CONFIG_NOR_BOOT=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_ENV_IS_IN_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_CMD_FLASH=y diff --git a/configs/mx7d_19x19_lpddr3_val_nand_defconfig b/configs/mx7d_19x19_lpddr3_val_nand_defconfig new file mode 100644 index 00000000000..7c69dfbf977 --- /dev/null +++ b/configs/mx7d_19x19_lpddr3_val_nand_defconfig @@ -0,0 +1,93 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_GPIO=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_TARGET_MX7D_19X19_LPDDR3_VAL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx7d-19x19-lpddr3-val" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_19x19_lpddr3_val/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx7d-19x19-lpddr3-val.dtb" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_ERRNO_STR=y +CONFIG_NAND_BOOT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index 3687a65283f..0c3421b435e 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -4,22 +4,24 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_DM_GPIO=y CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" -CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" -CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_CMD_BOOTD is not set +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set -# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set @@ -28,18 +30,24 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set +CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DM_74X164=y @@ -53,8 +61,7 @@ CONFIG_FSL_USDHC=y CONFIG_PHYLIB=y CONFIG_PHY_BROADCOM=y CONFIG_DM_ETH=y -CONFIG_DM_MDIO=y -CONFIG_DM_MDIO_MUX=y +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y @@ -75,6 +82,7 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 @@ -85,4 +93,15 @@ CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_ERRNO_STR=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_epdc_defconfig similarity index 73% rename from configs/mx7dsabresd_qspi_defconfig rename to configs/mx7dsabresd_epdc_defconfig index c216b8c5be6..4f8ab50235a 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_epdc_defconfig @@ -4,22 +4,27 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_DM_GPIO=y CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y # CONFIG_ARMV7_VIRT is not set CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y -CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi" -CONFIG_DISTRO_DEFAULTS=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" -CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" +CONFIG_MXC_EPDC=y +CONFIG_LCD=y +CONFIG_CMD_BMP=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y -# CONFIG_CMD_BOOTD is not set +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set -# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set # CONFIG_CMD_XIMG is not set # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set @@ -28,18 +33,23 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set +CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-epdc" CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DM_74X164=y @@ -50,17 +60,10 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=40000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_MACRONIX=y CONFIG_PHYLIB=y CONFIG_PHY_BROADCOM=y CONFIG_DM_ETH=y -CONFIG_DM_MDIO=y -CONFIG_DM_MDIO_MUX=y +CONFIG_DM_ETH_PHY=y CONFIG_FEC_MXC=y CONFIG_RGMII=y CONFIG_MII=y @@ -75,13 +78,13 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y -CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 @@ -93,3 +96,12 @@ CONFIG_USB_ETHER_ASIX=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y CONFIG_ERRNO_STR=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_nand_defconfig b/configs/mx7dsabresd_nand_defconfig new file mode 100644 index 00000000000..976bc879a83 --- /dev/null +++ b/configs/mx7dsabresd_nand_defconfig @@ -0,0 +1,118 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x3C00000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_NAND_BOOT=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_UBI=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand" +CONFIG_MTDPARTS_SKIP_INVALID=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_NAND_MXS_DT=y +CONFIG_ENV_IS_IN_NAND=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-gpmi-weim" +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_ERRNO_STR=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_optee_defconfig b/configs/mx7dsabresd_optee_defconfig new file mode 100644 index 00000000000..5b326b5880a --- /dev/null +++ b/configs/mx7dsabresd_optee_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_ERRNO_STR=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_plugin_defconfig b/configs/mx7dsabresd_plugin_defconfig new file mode 100644 index 00000000000..0be5a6707e2 --- /dev/null +++ b/configs/mx7dsabresd_plugin_defconfig @@ -0,0 +1,108 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_ERRNO_STR=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_qspi1_defconfig b/configs/mx7dsabresd_qspi1_defconfig new file mode 100644 index 00000000000..2214cc86d52 --- /dev/null +++ b/configs/mx7dsabresd_qspi1_defconfig @@ -0,0 +1,119 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_QSPI_BOOT=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_ENV_IS_IN_SPI_FLASH=y +# CONFIG_ENV_IS_IN_MMC is not set +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-qspi" +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_PHYLIB=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_QSPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_ERRNO_STR=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_reva_defconfig b/configs/mx7dsabresd_reva_defconfig new file mode 100644 index 00000000000..af1d128e421 --- /dev/null +++ b/configs/mx7dsabresd_reva_defconfig @@ -0,0 +1,107 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb-reva" +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_ERRNO_STR=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7dsabresd_revb_defconfig b/configs/mx7dsabresd_revb_defconfig new file mode 100644 index 00000000000..c24f91b9375 --- /dev/null +++ b/configs/mx7dsabresd_revb_defconfig @@ -0,0 +1,107 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xa0000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7DSABRESD=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +# CONFIG_ARMV7_VIRT is not set +CONFIG_IMX_RDC=y +CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage_TO_1_1.cfg" +CONFIG_BOOTDELAY=3 +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb" +CONFIG_ENV_OVERWRITE=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_DM_74X164=y +CONFIG_DM_I2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_BROADCOM=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_FEC_MXC=y +CONFIG_RGMII=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PFUZE100=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PFUZE100=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_ERRNO_STR=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x83800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y diff --git a/configs/mx7ulp_10x10_val_defconfig b/configs/mx7ulp_10x10_val_defconfig new file mode 100644 index 00000000000..00dee779a0f --- /dev/null +++ b/configs/mx7ulp_10x10_val_defconfig @@ -0,0 +1,78 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_val/imximage_lpddr2.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x9E000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7ULP_10X10_VAL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-10x10-val" +CONFIG_DEFAULT_FDT_FILE="imx7ulp-10x10-val.dtb" +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y diff --git a/configs/mx7ulp_14x14_val_defconfig b/configs/mx7ulp_14x14_val_defconfig new file mode 100644 index 00000000000..7c59e0d3444 --- /dev/null +++ b/configs/mx7ulp_14x14_val_defconfig @@ -0,0 +1,78 @@ +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_val/imximage.cfg" +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x7E000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7ULP_14X14_VAL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-14x14-val" +CONFIG_DEFAULT_FDT_FILE="imx7ulp-14x14-val.dtb" +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig index e918634a014..b607d3e1123 100644 --- a/configs/mx7ulp_evk_defconfig +++ b/configs/mx7ulp_evk_defconfig @@ -3,14 +3,16 @@ CONFIG_ARCH_MX7ULP=y CONFIG_SYS_TEXT_BASE=0x67800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x60000000 -CONFIG_SYS_MEMTEST_END=0x9e000000 +CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_DM_GPIO=y CONFIG_TARGET_MX7ULP_EVK=y -CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -21,11 +23,12 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_IMX_RGPIO2P=y @@ -43,3 +46,55 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_FSL_LPSPI=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_NW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_CMD_DM=y diff --git a/configs/mx7ulp_evk_emmc_defconfig b/configs/mx7ulp_evk_emmc_defconfig new file mode 100644 index 00000000000..168308f9b3f --- /dev/null +++ b/configs/mx7ulp_evk_emmc_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-emmc" +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb-emmc" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_NW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_CMD_DM=y diff --git a/configs/mx7ulp_evk_m4boot_defconfig b/configs/mx7ulp_evk_m4boot_defconfig new file mode 100644 index 00000000000..bce3d1fe079 --- /dev/null +++ b/configs/mx7ulp_evk_m4boot_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y +CONFIG_IMX_M4_BIND=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_NW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_CMD_DM=y diff --git a/configs/mx7ulp_evk_optee_defconfig b/configs/mx7ulp_evk_optee_defconfig new file mode 100644 index 00000000000..48e22c87547 --- /dev/null +++ b/configs/mx7ulp_evk_optee_defconfig @@ -0,0 +1,100 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX7ULP=y +CONFIG_SYS_TEXT_BASE=0x67800000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SYS_MEMTEST_START=0x60000000 +CONFIG_SYS_MEMTEST_END=0x80000000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xE0000 +CONFIG_DM_GPIO=y +CONFIG_TARGET_MX7ULP_EVK=y +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_IMX_OPTEE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_IMX_RGPIO2P=y +# CONFIG_MXC_GPIO is not set +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX7ULP=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_NW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_CMD_DM=y diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig index 8a80f898c7a..05541775391 100644 --- a/configs/mx7ulp_evk_plugin_defconfig +++ b/configs/mx7ulp_evk_plugin_defconfig @@ -3,15 +3,19 @@ CONFIG_ARCH_MX7ULP=y CONFIG_SYS_TEXT_BASE=0x67800000 CONFIG_NR_DRAM_BANKS=1 CONFIG_SYS_MEMTEST_START=0x60000000 -CONFIG_SYS_MEMTEST_END=0x9e000000 +CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xC0000 +CONFIG_ENV_OFFSET=0xE0000 CONFIG_DM_GPIO=y CONFIG_TARGET_MX7ULP_EVK=y -CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk" +CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi" +CONFIG_USE_IMXIMG_PLUGIN=y +CONFIG_DEFAULT_FDT_FILE="imx7ulp-evkb" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg" +CONFIG_BOARD_LATE_INIT=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y @@ -19,11 +23,12 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_CACHE=y CONFIG_CMD_FAT=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -# CONFIG_NET is not set CONFIG_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_IMX_RGPIO2P=y @@ -41,3 +46,53 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_FSL_LPUART=y +CONFIG_CMD_SF=y +CONFIG_FSL_QSPI=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SF_DEFAULT_BUS=0 +CONFIG_SF_DEFAULT_CS=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_ULP_WATCHDOG=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_MXC_USB_OTG_HACTIVE=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_DM_ETH=y + +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y + +CONFIG_CMD_FASTBOOT=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x60800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_EFI_PARTITION=y + +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_VIDEO_IMX_NW_DSI=y +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_LCD_RAYDIUM_RM68200=y +CONFIG_BACKLIGHT_GPIO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_CMD_BMP=y +CONFIG_CMD_DM=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 536fe7d6e1d..a1b9ea56cad 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -27,15 +27,20 @@ CONFIG_OF_CONTROL=y CONFIG_OF_BOARD=y CONFIG_ENV_OVERWRITE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM=y +CONFIG_SIMPLE_BUS_CORRECT_RANGE=y CONFIG_BLK=y CONFIG_HAVE_BLOCK_DEVICE=y CONFIG_MPC8XXX_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_FSL=y # CONFIG_MMC is not set +CONFIG_PHY_FIXED=y CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y CONFIG_E1000=y +CONFIG_TSEC_ENET=y CONFIG_DM_PCI=y CONFIG_PCI_MPC85XX=y CONFIG_DM_RTC=y diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig index cfda83474b6..1cea3401ee1 100644 --- a/configs/sandbox64_defconfig +++ b/configs/sandbox64_defconfig @@ -137,7 +137,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 5bc90d09a8f..dff3cd73b42 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -165,7 +165,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig index 4401f33f0ba..4623accbd24 100644 --- a/configs/sandbox_flattree_defconfig +++ b/configs/sandbox_flattree_defconfig @@ -115,7 +115,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig index c0118702a81..3fc9457c1c8 100644 --- a/configs/sandbox_spl_defconfig +++ b/configs/sandbox_spl_defconfig @@ -135,7 +135,6 @@ CONFIG_CROS_EC_I2C=y CONFIG_CROS_EC_LPC=y CONFIG_CROS_EC_SANDBOX=y CONFIG_CROS_EC_SPI=y -CONFIG_IRQ=y CONFIG_P2SB=y CONFIG_PWRSEQ=y CONFIG_SPL_PWRSEQ=y diff --git a/configs/som-imx8m-plus_defconfig b/configs/som-imx8m-plus_defconfig new file mode 100644 index 00000000000..2ff11c091b1 --- /dev/null +++ b/configs/som-imx8m-plus_defconfig @@ -0,0 +1,154 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x3F0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_SOM_IMX8M_PLUS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +CONFIG_FSL_MFGPROT=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_GREPENV=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_PWM=y +CONFIG_DM_RTC=y +CONFIG_RTC_ABX80X=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_LCD_STARTEK_ILI9881C=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_VIDEO_IMX_LCDIFV3=y +CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/configs/ucm-imx8m-mini_defconfig b/configs/ucm-imx8m-mini_defconfig new file mode 100644 index 00000000000..9fe7268870a --- /dev/null +++ b/configs/ucm-imx8m-mini_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_ICACHE_OFF=y +CONFIG_SPL_SYS_DCACHE_OFF=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DM_GPIO=y +CONFIG_TARGET_UCM_IMX8M_MINI=y +CONFIG_DEFAULT_DTB="ucm-imx8m-mini.dtb" +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_CSF_SIZE=0x2000 +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_LOCALVERSION="-ucm-imx8m-mini-2.0" +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg" +CONFIG_CONSOLE_MUX=y +CONFIG_DEFAULT_FDT_FILE="ucm-imx8m-mini.dtb" +CONFIG_BOARD_LATE_INIT=y +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_EEPROM_LAYOUT=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR= +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="ucm-imx8m-mini" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_IMX8MM=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_NXP_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_CI_UDC=y +CONFIG_SDP_LOADADDR=0x40400000 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_EXT4_WRITE=y +CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER is not set +CONFIG_LED=y +CONFIG_LED_GPIO=y diff --git a/configs/ucm-imx8m-plus_defconfig b/configs/ucm-imx8m-plus_defconfig new file mode 100644 index 00000000000..c4c78d4339f --- /dev/null +++ b/configs/ucm-imx8m-plus_defconfig @@ -0,0 +1,161 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x3F0000 +CONFIG_SYS_I2C_MXC_I2C1=y +CONFIG_SYS_I2C_MXC_I2C2=y +CONFIG_SYS_I2C_MXC_I2C3=y +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0x920000 +CONFIG_TARGET_UCM_IMX8M_PLUS=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +CONFIG_FSL_MFGPROT=y +CONFIG_IMX_CAAM_MFG_PROT=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mp-lpddr4.cfg" +CONFIG_BOOTCOMMAND="run distro_bootcmd;run bsp_bootcmd" +CONFIG_ARCH_MISC_INIT=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_POWER_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_GREPENV=y +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +# CONFIG_CMD_DATE is not set +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_CLK_COMPOSITE_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_SPL_CLK_IMX8MP=y +CONFIG_CLK_IMX8MP=y +CONFIG_DFU_MMC=y +CONFIG_DFU_SF=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_GPIO_HOG=y +CONFIG_MXC_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_ESDHC_IMX=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PHY_GIGE=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_PWM=y +CONFIG_DM_RTC=y +CONFIG_RTC_ABX80X=y +CONFIG_MXC_UART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_NXP_FSPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_TMU=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_LCD_STARTEK_ILI9881C=y +CONFIG_VIDEO_IMX_SEC_DSI=y +CONFIG_VIDEO_IMX_LCDIFV3=y +# CONFIG_WATCHDOG is not set +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_IMX_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_HEXDUMP is not set +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_EFI_SET_TIME=y +CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y +CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y diff --git a/disk/part_efi.c b/disk/part_efi.c index e5636ea7e69..42cb38f44f1 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -151,6 +151,25 @@ static int validate_gpt_header(gpt_header *gpt_h, lbaint_t lba, return 0; } +static void prepare_last_lba_gpt_header(struct blk_desc *dev_desc, gpt_header *gpt_h) +{ + uint32_t calc_crc32; + uint64_t val; + + /* recalculate the values for the Backup GPT Header */ + val = le64_to_cpu(gpt_h->my_lba); + gpt_h->my_lba = cpu_to_le64(dev_desc->lba - 1);; + gpt_h->alternate_lba = cpu_to_le64(val); + gpt_h->last_usable_lba = cpu_to_le64(dev_desc->lba - 34); + gpt_h->partition_entry_lba = + cpu_to_le64(le64_to_cpu(gpt_h->last_usable_lba) + 1); + gpt_h->header_crc32 = 0; + + calc_crc32 = efi_crc32((const unsigned char *)gpt_h, + le32_to_cpu(gpt_h->header_size)); + gpt_h->header_crc32 = cpu_to_le32(calc_crc32); +} + static int validate_gpt_entries(gpt_header *gpt_h, gpt_entry *gpt_e) { uint32_t calc_crc32; @@ -161,7 +180,7 @@ static int validate_gpt_entries(gpt_header *gpt_h, gpt_entry *gpt_e) le32_to_cpu(gpt_h->sizeof_partition_entry)); if (calc_crc32 != le32_to_cpu(gpt_h->partition_entry_array_crc32)) { - printf("%s: 0x%x != 0x%x\n", + debug("%s: 0x%x != 0x%x\n", "GUID Partition Table Entry Array CRC is wrong", le32_to_cpu(gpt_h->partition_entry_array_crc32), calc_crc32); @@ -258,8 +277,10 @@ void part_print_efi(struct blk_desc *dev_desc) printf("\tguid:\t%s\n", uuid); } +#if !defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) /* Remember to free pte */ free(gpt_pte); +#endif return; } @@ -283,7 +304,9 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part, !is_pte_valid(&gpt_pte[part - 1])) { debug("%s: *** ERROR: Invalid partition number %d ***\n", __func__, part); +#if !defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) free(gpt_pte); +#endif return -1; } @@ -310,11 +333,73 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part, debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__, info->start, info->size, info->name); - /* Remember to free pte */ +#if !defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) + /* Heap memory is very limited in SPL, if the dual bootloader is + * enabled, just load pte to dram instead of oc-ram. In such case, + * this part of memory shouldn't be freed. But in common routine, + * don't forget to free the memory after use. + */ free(gpt_pte); +#endif return 0; } +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_SPL_BUILD) +int part_get_info_efi_by_name(struct blk_desc *dev_desc, const char *name, + struct disk_partition *info) +{ + ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz); + /* We don't free gpt_pte because the memory is allocated at + * CONFIG_SYS_SPL_PTE_RAM_BASE due to the limited memory at + * SPL stage. + */ + gpt_entry *gpt_pte = NULL; + int i = 0; + + if (name == NULL) { + printf("%s: Invalid Argument(s)\n", __func__); + return -1; + } + + /* This function validates AND fills in the GPT header and PTE */ + if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1) + return -1; + + /* Search PTE to find matched partition. */ + for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) { + if (is_pte_valid(&gpt_pte[i]) && + strcmp(name, print_efiname(&gpt_pte[i])) == 0) { + /* Matched partition found, copy it. */ + /* The 'lbaint_t' casting may limit the maximum disk size to 2 TB */ + info->start = (lbaint_t)le64_to_cpu(gpt_pte[i].starting_lba); + /* The ending LBA is inclusive, to calculate size, add 1 to it */ + info->size = (lbaint_t)le64_to_cpu(gpt_pte[i].ending_lba) + 1 + - info->start; + info->blksz = dev_desc->blksz; + + snprintf((char *)info->name, sizeof(info->name), "%s", name); + strcpy((char *)info->type, "U-Boot"); + info->bootable = get_bootable(&gpt_pte[i]); +#if CONFIG_IS_ENABLED(PARTITION_UUIDS) + uuid_bin_to_str(gpt_pte[i].unique_partition_guid.b, info->uuid, + UUID_STR_FORMAT_GUID); +#endif +#ifdef CONFIG_PARTITION_TYPE_GUID + uuid_bin_to_str(gpt_pte[i].partition_type_guid.b, + info->type_guid, UUID_STR_FORMAT_GUID); +#endif + + debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__, + info->start, info->size, info->name); + + return i; + } + } + + return -1; +} +#endif /* CONFIG_DUAL_BOOTLOADER && CONFIG_SPL_BUILD */ + static int part_test_efi(struct blk_desc *dev_desc) { ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz); @@ -873,6 +958,58 @@ int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf) return 0; } +int write_backup_gpt_partitions(struct blk_desc *dev_desc, void *buf) +{ + gpt_header *gpt_h; + gpt_entry *gpt_e; + int gpt_e_blk_cnt; + lbaint_t lba; + int cnt; + + if (is_valid_gpt_buf(dev_desc, buf)) + return -1; + + /* determine start of GPT Header in the buffer */ + gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA * + dev_desc->blksz); + + /* determine start of GPT Entries in the buffer */ + gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) * + dev_desc->blksz); + gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) * + le32_to_cpu(gpt_h->sizeof_partition_entry)), + dev_desc); + + /* write MBR */ + lba = 0; /* MBR is always at 0 */ + cnt = 1; /* MBR (1 block) */ + if (blk_dwrite(dev_desc, lba, cnt, buf) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "MBR", cnt, lba); + return 1; + } + + prepare_last_lba_gpt_header(dev_desc, gpt_h); + + /* write Backup GPT */ + lba = le64_to_cpu(gpt_h->partition_entry_lba); + cnt = gpt_e_blk_cnt; + if (blk_dwrite(dev_desc, lba, cnt, gpt_e) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Backup GPT Entries", cnt, lba); + return 1; + } + + lba = le64_to_cpu(gpt_h->my_lba); + cnt = 1; /* GPT Header (1 block) */ + if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) { + printf("%s: failed writing '%s' (%d blks at 0x" LBAF ")\n", + __func__, "Backup GPT Header", cnt, lba); + return 1; + } + + return 0; +} #endif /* @@ -1005,7 +1142,7 @@ static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head, if (r != 1) { if (r != 2) - printf("%s: *** ERROR: Invalid GPT ***\n", __func__); + debug("%s: *** ERROR: Invalid GPT ***\n", __func__); if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head, pgpt_pte) != 1) { @@ -1014,7 +1151,7 @@ static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head, return 0; } if (r != 2) - printf("%s: *** Using Backup GPT ***\n", + debug("%s: *** Using Backup GPT ***\n", __func__); } return 1; @@ -1049,10 +1186,19 @@ static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc, (u32) le32_to_cpu(pgpt_head->sizeof_partition_entry), (ulong)count); - /* Allocate memory for PTE, remember to FREE */ + /* Allocate memory for PTE. + * Heap memory is very limited in SPL, if the dual bootloader is + * enabled, just load pte to dram instead of oc-ram. In such case, + * this part of memory shouldn't be freed. But in common routine, + * don't forget to free the memory after use. + */ if (count != 0) { +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_SPL_BUILD) + pte = (gpt_entry *)CONFIG_SYS_SPL_PTE_RAM_BASE; +#else pte = memalign(ARCH_DMA_MINALIGN, PAD_TO_BLOCKSIZE(count, dev_desc)); +#endif } if (count == 0 || pte == NULL) { @@ -1066,7 +1212,9 @@ static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc, blk_cnt = BLOCK_CNT(count, dev_desc); if (blk_dread(dev_desc, blk, (lbaint_t)blk_cnt, pte) != blk_cnt) { printf("*** ERROR: Can't read GPT Entries ***\n"); +#if !defined(CONFIG_DUAL_BOOTLOADER) || !defined(CONFIG_SPL_BUILD) free(pte); +#endif return NULL; } return pte; diff --git a/doc/board/emulation/qemu-ppce500.rst b/doc/board/emulation/qemu-ppce500.rst index 0a5c86c61ae..5de0aaf55de 100644 --- a/doc/board/emulation/qemu-ppce500.rst +++ b/doc/board/emulation/qemu-ppce500.rst @@ -70,6 +70,11 @@ interface at PCI address 0.1.0, but we can switch that to an e1000 NIC by:: $ qemu-system-ppc -nographic -machine ppce500 -bios u-boot \ -nic tap,ifname=tap0,script=no,downscript=no,model=e1000 +The QEMU ppce500 machine can also dynamically instantiate an eTSEC device if +"-device eTSEC" is given to QEMU:: + + -netdev tap,ifname=tap0,script=no,downscript=no,id=net0 -device eTSEC,netdev=net0 + VirtIO BLK driver is also enabled to support booting from a disk image where a kernel image is stored. Append the following to QEMU:: diff --git a/doc/device-tree-bindings/net/fixed-link.txt b/doc/device-tree-bindings/net/fixed-link.txt index 5829bd81a22..5efeeb6fc5e 100644 --- a/doc/device-tree-bindings/net/fixed-link.txt +++ b/doc/device-tree-bindings/net/fixed-link.txt @@ -5,21 +5,37 @@ Some Ethernet MACs have a "fixed link", and are not connected to a normal MDIO-managed PHY device. For those situations, a Device Tree binding allows to describe a "fixed link". -Such a fixed link situation is described by creating a 'fixed-link' -sub-node of the Ethernet MAC device node, with the following -properties: - -* 'speed' (integer, mandatory), to indicate the link speed. Accepted - values are 10, 100 and 1000 -* 'full-duplex' (boolean, optional), to indicate that full duplex is - used. When absent, half duplex is assumed. -* 'pause' (boolean, optional), to indicate that pause should be - enabled. -* 'asym-pause' (boolean, optional), to indicate that asym_pause should - be enabled. +Note there are two ways to describe a fixed PHY attached to an +Ethernet device: + +- The new DT binding, where 'fixed-link' is a sub-node of the Ethernet + MAC device node, with the following properties: + + * 'speed' (integer, mandatory), to indicate the link speed. Accepted + values are 10, 100 and 1000 + * 'full-duplex' (boolean, optional), to indicate that full duplex is + used. When absent, half duplex is assumed. + * 'pause' (boolean, optional), to indicate that pause should be + enabled. + * 'asym-pause' (boolean, optional), to indicate that asym_pause should + be enabled. + +- The old DT binding, where 'fixed-link' is a property with 5 cells + encoding various information about the fixed PHY, in the form of + . + + * 'phy_id', emulated PHY ID, choose any but unique to the all specified + fixed-links. Note U-Boot deliberately ignores the 'phy_id' and + unconditionally uses PHY_FIXED_ID. + * 'full-duplex', 0 for half duplex or 1 for full duplex + * 'speed', link speed in Mbits/sec, accepts only 10, 100 and 1000 + * 'pause', 0 for no pause, 1 for pause + * 'asym-pause', 0 for no asymmetric pause, 1 for asymmetric pause Examples: +The new binding: + ethernet@0 { ... fixed-link { @@ -28,3 +44,11 @@ ethernet@0 { }; ... }; + +The old binding: + +ethernet@0 { + ... + fixed-link = <0 1 1000 0 0>; + ... +}; diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt index a44c5fd9d9c..f68980352bc 100644 --- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt +++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt @@ -3,12 +3,17 @@ Properties: - compatible : Should be "fsl,etsec2" or "gianfar" - - reg : Offset and length of the register set for the device + - reg : Offset and length of the register set for the device. If this is + missing, a subnode with a name prefix "queue-group" must be provided to + provide the property. - phy-handle : See ethernet.txt file in the same directory. - phy-connection-type : See ethernet.txt file in the same directory. This property is only really needed if the connection is of type "rgmii-id", "rgmii-rxid" and "rgmii-txid" as all other connection types are detected by hardware. + - ranges : an value if subnode "queue-group" is present, specifying + that no address translation is required between them TSEC parent node and + the child "queue-group" node. Example: ethernet@24000 { @@ -18,6 +23,18 @@ Example: phy-connection-type = "sgmii"; }; +An alternate description with "queue-group" subnode example: + ethernet@24000 { + compatible = "fsl,etsec2"; + phy-handle = <&phy0>; + phy-connection-type = "sgmii"; + ranges; + + queue-group { + reg = <0x24000 0x1000>; + }; + }; + Child nodes of the TSEC controller are typically the individual PHY devices connected via the MDIO bus (sometimes the MDIO bus controller is separate). diff --git a/doc/device-tree-bindings/usb/cdns-usb3.txt b/doc/device-tree-bindings/usb/cdns-usb3.txt new file mode 100644 index 00000000000..8aba13b88ad --- /dev/null +++ b/doc/device-tree-bindings/usb/cdns-usb3.txt @@ -0,0 +1,53 @@ +* Cadence USB3 Controller + +Required properties: +- compatible: should contain: "cdns,usb3-1.0.0" +- reg: physical base address and size of the controller's register areas + Controller has 5 different regions: + region 1 - NONE-CORE registers area + region 2 - HOST registers area + region 3 - DEVICE registers area + region 4 - PHY registers area + region 5 - OTG registers area +- reg-names - register memory area names: + "none-core" - for NONE-CORE registers space + "xhci" - for HOST registers space + "dev" - for DEVICE registers space + "phy" - for PHY registers space + "otg" - for OTG registers space +- interrupts: interrupts used by cdns3 controller +- interrupt-parent: the interrupt parent for this module +- clocks: reference to the USB clock +- clock-names: the name of clocks +- phys: reference to the USB PHY + +Optional properties: +- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" +- extcon: extcon phandler for cdns3 device +- power-domains: the power domain for cdns3 controller and phy + +Examples: + +usbotg3: cdns3@5b110000 { + compatible = "cdns,usb3-1.0.0"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>, + <0x0 0x5B120000 0x0 0x10000>; + reg-names = "none-core", "xhci", "dev", "phy", "otg"; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&clk IMX8QM_USB3_LPM_CLK>, + <&clk IMX8QM_USB3_BUS_CLK>, + <&clk IMX8QM_USB3_ACLK>, + <&clk IMX8QM_USB3_IPG_CLK>, + <&clk IMX8QM_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + power-domains = <&pd_conn_usb2>; + phys = <&usbphy1>; + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "disabled"; +}; diff --git a/doc/imx/ahab/csf_examples/csf_boot_image.txt b/doc/imx/ahab/csf_examples/csf_boot_image.txt new file mode 100644 index 00000000000..1f296f09007 --- /dev/null +++ b/doc/imx/ahab/csf_examples/csf_boot_image.txt @@ -0,0 +1,21 @@ +[Header] +Target = AHAB +Version = 1.0 + +[Install SRK] +# SRK table generated by srktool +File = "./release/crts/SRK_1_2_3_4_table.bin" +# Public key certificate in PEM format +Source = "./release/crts/SRK1_sha384_secp384r1_v3_usr_crt.pem" +# Index of the public key certificate within the SRK table (0 .. 3) +Source index = 0 +# Type of SRK set (NXP or OEM) +Source set = OEM +# bitmask of the revoked SRKs +Revocations = 0x0 + +[Authenticate Data] +# Binary to be signed generated by mkimage +File = "flash.bin" +# Offsets = Container header Signature block (printed out by mkimage) +Offsets = 0x400 0x590 diff --git a/doc/imx/ahab/csf_examples/csf_boot_image_sgk.txt b/doc/imx/ahab/csf_examples/csf_boot_image_sgk.txt new file mode 100644 index 00000000000..ec42f4f09ea --- /dev/null +++ b/doc/imx/ahab/csf_examples/csf_boot_image_sgk.txt @@ -0,0 +1,28 @@ +[Header] +Target = AHAB +Version = 1.0 + +[Install SRK] +# SRK table generated by srktool +File = "./release/crts/SRK_1_2_3_4_table.bin" +# Public key certificate in PEM format +Source = "./release/crts/SRK1_sha384_secp384r1_v3_ca_crt.pem" +# Index of the public key certificate within the SRK table (0 .. 3) +Source index = 0 +# Type of SRK set (NXP or OEM) +Source set = OEM +# bitmask of the revoked SRKs +Revocations = 0x0 + +# Optional subordinate SGK key +[Install Certificate] +# Public key certificate in PEM format +File = "./release/crts/SGK1_sha384_secp384r1_v3_usr_crt.pem" +# bitmask of the permissions +Permissions = 0x1 + +[Authenticate Data] +# Binary to be signed generated by mkimage +File = "flash.bin" +# Offsets = Container header Signature block (printed out by mkimage) +Offsets = 0x400 0x590 diff --git a/doc/imx/ahab/csf_examples/csf_linux_img.txt b/doc/imx/ahab/csf_examples/csf_linux_img.txt new file mode 100644 index 00000000000..b5aa5238023 --- /dev/null +++ b/doc/imx/ahab/csf_examples/csf_linux_img.txt @@ -0,0 +1,21 @@ +[Header] +Target = AHAB +Version = 1.0 + +[Install SRK] +# SRK table generated by srktool +File = "./release/crts/SRK_1_2_3_4_table.bin" +# Public key certificate in PEM format +Source = "./release/crts/SRK1_sha384_secp384r1_v3_usr_crt.pem" +# Index of the public key certificate within the SRK table (0 .. 3) +Source index = 0 +# Type of SRK set (NXP or OEM) +Source set = OEM +# bitmask of the revoked SRKs +Revocations = 0x0 + +[Authenticate Data] +# Binary to be signed generated by mkimage +File = "flash_os.bin" +# Offsets = Container header Signature block (printed out by mkimage) +Offsets = 0x0 0x110 diff --git a/doc/imx/ahab/csf_examples/csf_uboot_atf.txt b/doc/imx/ahab/csf_examples/csf_uboot_atf.txt new file mode 100644 index 00000000000..c4d23bcce4b --- /dev/null +++ b/doc/imx/ahab/csf_examples/csf_uboot_atf.txt @@ -0,0 +1,21 @@ +[Header] +Target = AHAB +Version = 1.0 + +[Install SRK] +# SRK table generated by srktool +File = "../crts/SRK_1_2_3_4_table.bin" +# Public key certificate in PEM format on this example only using SRK key +Source = "../crts/SRK1_sha384_secp384r1_v3_usr_crt.pem" +# Index of the public key certificate within the SRK table (0 .. 3) +Source index = 0 +# Type of SRK set (NXP or OEM) +Source set = OEM +# bitmask of the revoked SRKs +Revocations = 0x0 + +[Authenticate Data] +# Binary to be signed generated by mkimage +File = "u-boot-atf-container.img" +# Offsets = Container header Signature block (printed out by mkimage) +Offsets = 0x0 0x110 diff --git a/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt b/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt index dfea4c8277c..23a78a1b529 100644 --- a/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt +++ b/doc/imx/ahab/guides/mx8_mx8x_encrypted_boot.txt @@ -290,4 +290,4 @@ os_cntr_signed.bin. $ sudo cp enc_flash_os.bin /media/UserID/Boot\ imx8/os_cntr_signed.bin References: -[1] SCFW API guide: "System Controller Firmware API Reference Guide - Rev 1.5" +[1] SCFW API guide: "System Controller Firmware API Reference Guide" diff --git a/doc/imx/ahab/guides/mx8_mx8x_secure_boot.txt b/doc/imx/ahab/guides/mx8_mx8x_secure_boot.txt new file mode 100644 index 00000000000..4d4d6833c81 --- /dev/null +++ b/doc/imx/ahab/guides/mx8_mx8x_secure_boot.txt @@ -0,0 +1,397 @@ + +=========================================================+ + + i.MX 8, i.MX 8X Secure Boot guide using AHAB + + +=========================================================+ + +1. AHAB secure boot process +---------------------------- + +This document describes a step-by-step procedure on how to sign and +securely boot a flash.bin image. It is assumed that the reader is +familiar with basic AHAB concepts and with the PKI tree generation. + +It is also assumed that the reader is familiar with all pieces of +software needed. The procedure to built SCFW, ATF and download the +firmwares are out of scope of this document, please refer to the Linux +BSP Release Notes and AN12212[1] for further details. + +Details about AHAB can be found in the introduction_ahab.txt document +and in processors Security Reference Manual Document (SRM). + +1.1 Preparing the environment to build a secure boot image +----------------------------------------------------------- + +Before continuing, be sure to have already downloaded and built the +following: + +- imx-mkimage downloaded and built with i.MX 8 container support. +- SECO firmware downloaded. +- U-Boot downloaded and built. Please check section 1.2. +- ARM Trusted Firmware (ATF) downloaded and built for your target. +- System Controller Firmware (SCFW). +- Kernel image. + +You should also have downloaded the Code Signing Tool, available on NXP +website. + +In the following sections, designates the repository where all +parts have been downloaded and built. + +1.2 Preparing U-Boot to support AHAB secure boot features +---------------------------------------------------------- + +The U-Boot provides extra functions for AHAB, such as the ability to +authenticate additional container images by calling the SCU API +sc_misc_seco_authenticate() function. + +The support is enabled by adding CONFIG_AHAB_BOOT to the defconfig file used +for your target: + + - Defconfig: + CONFIG_AHAB_BOOT=y + - Kconfig: + ARM architecture -> Support i.MX 8 AHAB features + +1.3 Building an image supporting secure boot +--------------------------------------------- + +The boot image is composed of different layers: + + +---------------------------+ <-- *start + | 1st Container header | + | and signature | + +---------------------------+ + | Padding for 1kB alignment | + +---------------------------+ <-- *start + 0x400 + | 2nd Container header | + | and signature | + +---------------------------+ + | Padding | + +---------------------------+ + | SECO FW | + +---------------------------+ + | Padding | + +---------------------------+ + | SCU FW with DDR | + | initialization Image | + | embedded | + +---------------------------+ + | Cortex-M4 Image | + +---------------------------+ + | Cortex-A bootloader | + +---------------------------+ + +It contains two containers, one for the SECO firmware (AHAB), and one for +the SCFW, the ATF, U-Boot and M4 Image. They are preceded by their headers. +The first one, containing the SECO firmware image, is padded to 0x1000 to +fix the start address of the second one, which can contain one or multiple +images. + +If you are familiar with secure boot process with HABv4, you will notice +there is no need for CSF in this architecture. The CST is responsible to +handle the Signature block: + + +----------------------------+ ^ + | | | + | | | + | Container header | | + | | | + | | | + +---+------------------------+ | + | S | Signature block header | | Signed + | i +------------------------+ | + | g | | | + | n | | | + | a | SRK table | | + | t | | | + | u | | | + | r +------------------------+ v + | e | Signature | + | +------------------------+ + | b | | + | l | SGK Key | + | o | Certificate (optional) | + | c | | + | k | | + +---+------------------------+ + +The certificate block is divided into: + + +---------------+ ^ + | Public key | | Signed + | Permission | | + +---------------+ v + | Signature | + +---------------+ + +The first block (public key permission) verify the Signature block +preceding (between SRK table and Certificate blocks), while the second +block (signature) is verified by the SRK table block. + +1.4 Prepare the boot image layout +---------------------------------- + +To generate the flash.bin file: + +- On i.MX 8 QXP: + + $ cd /imx-mkimage + $ make SOC=iMX8QX flash + +- On i.MX 8 QM: + + $ cd /imx-mkimage + $ make SOC=iMX8QM flash + +If the command ends successfully, the end of the result should look +like: + + CST: CONTAINER 0 offset: 0x400 + CST: CONTAINER 0: Signature Block: offset is at 0x590 + DONE. + Note: Please copy image to offset: IVT_OFFSET + IMAGE_OFFSET + +Keep in mind the offsets above to be used with CST/CSF. + +Please note that on this example we not including an Cortex-M4 Image, on +i.MX8/8x MEK boards the SCU console may be replaced by the M4 console not +being possible to run the steps documented in section "1.5.5 Verify SECO +events". + +1.5 Secure boot setup with the CST +----------------------------------- + +1.5.1 Creating the CSF description file for the second container +----------------------------------------------------------------- + +The CSF contains all the commands that the AHAB executes during the secure +boot. These commands instruct the AHAB on which memory areas of the image +to authenticate, which keys to install, use and etc. + +CSF examples are available under doc/imx/hab/ahab/csf_examples/ +directory. + +This csf_boot_image.txt file example should be updated with the offset values +of the 1.4 section and the path to your flash.bin file. It is the last part +of the file: + + [Authenticate Data] + # Binary to be signed generated by mkimage + File = "flash.bin" + # Offsets = Container header Signature block (printed out by mkimage) + Offsets = 0x400 0x590 + +1.5.2 Signing the boot image +----------------------------- + +Now you use the CST to generate the signed boot image from the previously +created csf_boot_image.txt Commands Sequence File: + + $ cd + $ ./release/linux64/bin/cst -i csf_boot_image.txt -o flash.signed.bin + +1.5.3 Flash the signed image +----------------------------- + +Write the signed U-Boot image: + + $ sudo dd if=flash.signed.bin of=/dev/sdX bs=1k seek=32 ; sync + +Then insert the SD Card into the board and plug your device to your computer +with an USB serial cable. + +1.5.4 Programming SRK Hash +--------------------------- + +As explained in introduction_ahab.txt document the SRK Hash fuse values are +generated by the srktool and should be programmed in the SoC SRK_HASH[511:0] +fuses. + +Be careful when programming these values, as this data is the basis for the +root of trust. An error in SRK Hash results in a part that does not boot. + +The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs. + +- Dump SRK Hash fuses values in host machine: + + $ od -t x4 SRK_1_2_3_4_fuse.bin + 0000000 d436cc46 8ecccda9 b89e1601 5fada3db + 0000020 d454114a b6cd51f4 77384870 c50ee4b2 + 0000040 a27e5132 eba887cf 592c1e2b bb501799 + 0000060 ee702e07 cf8ce73e fb55e2d5 eba6bbd2 + +- Program SRK_HASH[511:0] fuses: + + * On i.MX 8 QXP: + + => fuse prog 0 730 0xd436cc46 + => fuse prog 0 731 0x8ecccda9 + => fuse prog 0 732 0xb89e1601 + => fuse prog 0 733 0x5fada3db + => fuse prog 0 734 0xd454114a + => fuse prog 0 735 0xb6cd51f4 + => fuse prog 0 736 0x77384870 + => fuse prog 0 737 0xc50ee4b2 + => fuse prog 0 738 0xa27e5132 + => fuse prog 0 739 0xeba887cf + => fuse prog 0 740 0x592c1e2b + => fuse prog 0 741 0xbb501799 + => fuse prog 0 742 0xee702e07 + => fuse prog 0 743 0xcf8ce73e + => fuse prog 0 744 0xfb55e2d5 + => fuse prog 0 745 0xeba6bbd2 + + * On i.MX 8 QM: + + => fuse prog 0 722 0xd436cc46 + => fuse prog 0 723 0x8ecccda9 + => fuse prog 0 724 0xb89e1601 + => fuse prog 0 725 0x5fada3db + => fuse prog 0 726 0xd454114a + => fuse prog 0 727 0xb6cd51f4 + => fuse prog 0 728 0x77384870 + => fuse prog 0 729 0xc50ee4b2 + => fuse prog 0 730 0xa27e5132 + => fuse prog 0 731 0xeba887cf + => fuse prog 0 732 0x592c1e2b + => fuse prog 0 733 0xbb501799 + => fuse prog 0 734 0xee702e07 + => fuse prog 0 735 0xcf8ce73e + => fuse prog 0 736 0xfb55e2d5 + => fuse prog 0 737 0xeba6bbd2 + +1.5.5 Verify SECO events +------------------------- + +If the fuses have been written properly, there should be no SECO events after +boot. To validate this, power on the board, and run ahab_status command on +U-Boot terminal. + +No events should be returned after this command: + + => ahab_status + Lifecycle: 0x0020, NXP closed + + No SECO Events Found! + +U-Boot will decode the SECO events and provide more details on the failure, +for example in case container is not signed (signature is missing), but the +device is not OEM closed: + + => ahab_status + Lifecycle: 0x0020, NXP closed + + SECO Event[0] = 0x0087EE00 + CMD = AHAB_AUTH_CONTAINER_REQ (0x87) + IND = AHAB_NO_AUTHENTICATION_IND (0xEE) + +Note: In case the signature is incorrect (signed with wrong keys which are not +matching the OTP SRK hashes) the event 0x0087FA00 is also displayed. + +1.5.6 Close the device +----------------------- + +After the device successfully boots a signed image without generating any +SECO security events, it is safe to close the device. The SECO lifecycle +should be changed from 0x20 NXP closed to 0x80 OEM closed. Be aware this +step can damage your board if a previous step failed. It is also +irreversible. Run on the U-Boot terminal: + + => ahab_close + +Now reboot the target, and run: + + => ahab_status + +The lifecycle value should now be 0x80 OEM closed. + +2. Authenticating the OS container +----------------------------------- + +Note that the following section is not mandatory. If you do not plan to +authenticate the kernel image, you can disable this behavior by setting +sec_boot=no in U-Boot environment variable. + +Note, you can also authenticate the OS image by running a U-Boot command: + + => auth_cntr + +2.1 Prepare the OS container image +----------------------------------- + +You need to generate the OS container image. First, copy the binary previously +generated to the directory to save it for later: + +- On i.MX 8 QXP + + $ cd /imx-mkimage + $ cp iMX8QX/flash.bin .. + $ make SOC=iMX8QX flash_kernel + $ mv iMX8QX/flash.bin iMX8QX/flash_os.bin + $ cp iMX8QX/flash_os.bin .. + +- On i.MX 8 QM + + $ cd /imx-mkimage + $ cp iMX8QM/flash.bin .. + $ make SOC=iMX8QM flash_kernel + $ mv iMX8QM/flash.bin iMX8QM/flash_os.bin + $ cp iMX8QM/flash_os.bin .. + +If the make command ends successfully, the end of the result should look +like: + + CST: CONTAINER 0 offset: 0x0 + CST: CONTAINER 0: Signature Block: offset is at 0x110 + DONE. + Note: Please copy image to offset: IVT_OFFSET + IMAGE_OFFSET + +Keep in mind the offsets above to be used with CST/CSF + +2.2 Creating the CSF description file for OS container image +------------------------------------------------------------- + +CSF examples are available under doc/imx/hab/ahab/csf_examples/ +directory. + +This csf_linux_img.txt file example should be updated with the offset values +of the 2.1 chapter and the path to your flash_os.bin file. It it the last +part of the file: + + [Authenticate Data] + # Binary to be signed generated by mkimage + File = "flash_os.bin" + # Offsets = Container header Signature block (printed out by mkimage) + Offsets = 0x0 0x110 + +2.3 Authenticating container image +----------------------------------- + +Now you use the CST to signed the OS image using the previously +created csf_linux_img.txt Commands Sequence File: + + $ cd + $ ./release/linux64/bin/cst -i csf_linux_img.txt -o os_cntr_signed.bin + +2.4 Copy OS container +---------------------- + +Mount the SD Card: + + $ sudo mount /dev/sdX1 partition + +Copy the OS signed image on the SD Card: + +- For i.MX 8 QXP + + $ sudo cp os_cntr_signed.bin /media/UserID/Boot\ imx8qx + +- For i.MX 8 QM + + $ sudo cp os_cntr_signed.bin /media/UserID/Boot\ imx8qm + +Finally: + + $ sudo umount partition + +References: +[1] AN12212: "Software Solutions for Migration Guide from Aarch32 to Aarch64" diff --git a/doc/imx/ahab/guides/mx8_mx8x_spl_secure_boot.txt b/doc/imx/ahab/guides/mx8_mx8x_spl_secure_boot.txt new file mode 100644 index 00000000000..6699ebfecd3 --- /dev/null +++ b/doc/imx/ahab/guides/mx8_mx8x_spl_secure_boot.txt @@ -0,0 +1,357 @@ + +=========================================================+ + + i.MX 8, i.MX 8X AHAB guide on SPL targets + + +=========================================================+ + +1. AHAB secure boot process +---------------------------- + +This document provides a step-by-step guide on how securely boot a flash.bin +image generated by Secondary Program Loader (SPL) targets. It is assumed that +the reader is familiar with basic AHAB concepts and with the PKI tree +generation. + +Details about AHAB can be found in the introduction_ahab.txt document and in +processors Security Reference Manual Document (SRM). + +1.1 Preparing the environment to build a secure boot image +----------------------------------------------------------- + +The following files and projects are used to prepare a secure boot image +for i.MX8/8x device: + +- imx-mkimage. +- SECO Firmware. +- U-Boot proper and SPL. (Please refer to section 1.2) +- ARM Trusted Firmware (ATF). +- System Controller Firmware (SCFW). +- Cortex M binary. (Optional) +- Kernel image. (Optional) +- Code signing tools (CST). + +The procedure to download the SECO firmware and build U-Boot, SCFW and ATF are +out of the scope of this document, please refer to the Linux BSP Release Notes +and AN12212[1] for further details. + +1.2 Preparing U-Boot to support AHAB secure boot features +---------------------------------------------------------- + +The U-Boot provides an alternative SPL target for i.MX8 and i.MX8x devices. The +SPL is intended to be used by applications that requires a initial bootloader +prior to initialize the ARM Trusted Firmware (ATF) and the U-Boot proper. + +The U-Boot support AHAB functions that are essential to completely authenticate +the flash.bin image. On SPL targets only the SCFW, SPL and M4 IMG are +authenticated at SCU ROM level, in order to authenticate the ATF and U-Boot +proper it's necessary to call the SCU API sc_misc_seco_authenticate() function +at SPL level. + +The support is enabled by adding CONFIG_AHAB_BOOT to the defconfig file used +by your target: + + - Defconfig: + CONFIG_AHAB_BOOT=y + - Kconfig: + ARM architecture -> Support i.MX 8 AHAB features + +1.3 Building a SPL image supporting secure boot +------------------------------------------------ + +The boot image generated by SPL targets has three containers: + + +---------------------------+ --------- + | 1st Container header | ^ + | and signature | | + +---------------------------+ | + | Padding for 1kB alignment | | + +---------------------------+ | + | 2nd Container header | | + | and signature | | + +---------------------------+ | + | Padding | | Authenticated at + +---------------------------+ | SCU ROM Level + | SECO FW | | + +---------------------------+ | + | Padding | | + +---------------------------+ | + | SCU FW + DCD Table | | + +---------------------------+ | + | Cortex-M Image | | + +---------------------------+ | + | SPL Image | v + +---------------------------+ --------- + | 3rd Container header | ^ + | and signature | | + +---------------------------+ | + | Padding | | Authenticated + +---------------------------+ | at SPL Level + | U-Boot Proper IMG | | + +---------------------------+ | + | ARM Trusted FW (ATF) | v + +---------------------------+ --------- + +The first container includes the SECO firmware which is signed using NXP keys, +this container is authenticated by SECO ROM at SCU ROM level. + +The second container includes the SCFW, SPL and Cortex M SW images which are +signed using OEM keys, this container is authenticated by SECO FW at SCU ROM +level. + +The third container includes the U-Boot proper and the ATF. The SPL is in +charge to load this container and also to interface with SCU requesting +SECO FW to authenticate the additional container. + +The signing procedure is slightly different when compared with HABv4 series. On +AHAB the signature is directly included in the container, the CST is +responsible to sign and handle the "Signature Block": + + +----------------------------+ --------- + | | ^ + | | | + | Container header | | + | | | + | | | + +---+----------------------- + | + | S | Signature block header | | Signed + | i +------------------------+ | + | g | | | + | n | | | + | a | SRK table | | + | t | | | + | u | | v + | r +------------------------+ --------- + | e | Signature | + | +------------------------+ + | B | | + | l | SGK Key | + | o | Certificate (optional) | + | c | | + | k | | + +---+------------------------+ + +In case using the optional subordinate SGK key, the container signature is +verified against the SGK key certificate. This certificate is verified +against the SRK table. + +In case not using the subordinate key, the container signature is verified +against the SRK keys directly. + +1.4 Preparing the boot image +----------------------------- + +1.4.1 Preparing the 3rd container +---------------------------------- + +The first step is to generate the third container including the U-Boot proper +and ATF images. + +The imx-mkimage project includes a target which only generates this third +container: + +- Generating the U-Boot proper + ATF container: + + $ make SOC= u-boot-atf-container.img + +The mkimage log provides the container and signature block offsets used by the +CSF description file: + + CST: CONTAINER 0 offset: 0x0 + CST: CONTAINER 0: Signature Block: offset is at 0x110 + +The u-boot-atf-container.img file is the third container which have to be +signed using the Code Signing Tool (CST). + +1.4.2 Signing the 3rd container +-------------------------------- + +The CSF description file contains all the commands that the SECO executes +during the secure boot procedure. These commands instruct the AHAB code on +which memory areas of the image to authenticate, which keys to install, use +and etc. + +CSF examples are available under doc/imx/hab/ahab/csf_examples/ directory. + +As explained in section above the mkimage log provides the container and +signature block offsets used by the CSF description file: + +- "Authenticate Data" command in cst_uboot_atf.txt file: + + [Authenticate Data] + # Binary to be signed generated by mkimage + File = "u-boot-atf-container.img" + # Offsets = Container header Signature block + Offsets = 0x0 0x110 + +- Sign the third container: + + $ ./cst -i cst_uboot_atf.txt -o signed-u-boot-atf-container.img + +The signed-u-boot-atf-container.img have to be copied to imx-mkimage directory +and renamed to u-boot-atf-container.img. + +1.4.3 Preparing the flash.bin image +------------------------------------ + +The signed 3rd container can be now used to create the final flash.bin image, +be sure that your signed container were successfully replaced and is named +as u-boot-atf-container.img. + +- Generating the flash.bin image: + + $ make SOC= flash_spl + +The mkimage log provides the container and signature block offsets used by the +CSF description file: + + CST: CONTAINER 0 offset: 0x400 + CST: CONTAINER 0: Signature Block: offset is at 0x510 + +The flash.bin file include three containers and the second container have to be +signed using the Code Signing Tool (CST). + +1.4.4 Signing the flash.bin image +---------------------------------- + +As mentioned above the CSF description file contains all the commands that +the SECO executes during the secure boot procedure. + +The procedure for signing the flash.bin image is similar as documented in +mx8_mx8x_secure_boot.txt guide. + +- "Authenticate Data" command in csf_boot_image.txt file: + + [Authenticate Data] + # Binary to be signed generated by mkimage + File = "flash.bin" + # Offsets = Container header Signature block + Offsets = 0x400 0x510 + +- Sign the flash.bin container: + + $ ./cst -i csf_boot_image.txt -o signed-flash.bin + +The signed-flash.bin image contains all the signatures and can be flashed in +the device. + +1.5 Flashing the signed image +------------------------------ + +After completing all steps in section "1.4 Preparing the boot image" the +signed flash.bin image can be flashed in the device: + + $ sudo dd if=signed-flash.bin of=/dev/sd bs=1k seek=32 && sync + +1.6 Programming SRK Hash +------------------------- + +As explained in introduction_ahab.txt document the SRK Hash fuse values are +generated by the srktool and should be programmed in the SoC SRK_HASH[511:0] +fuses. + +Be careful when programming these values, as this data is the basis +for the root of trust. An error in SRK Hash results in a part that +does not boot. + +The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs. + +- Dump SRK Hash fuses values in host machine: + + $ od -t x4 SRK_1_2_3_4_fuse.bin + 0000000 d436cc46 8ecccda9 b89e1601 5fada3db + 0000020 d454114a b6cd51f4 77384870 c50ee4b2 + 0000040 a27e5132 eba887cf 592c1e2b bb501799 + 0000060 ee702e07 cf8ce73e fb55e2d5 eba6bbd2 + +- Program SRK_HASH[511:0] fuses: + + * On i.MX 8 QXP: + + => fuse prog 0 730 0xd436cc46 + => fuse prog 0 731 0x8ecccda9 + => fuse prog 0 732 0xb89e1601 + => fuse prog 0 733 0x5fada3db + => fuse prog 0 734 0xd454114a + => fuse prog 0 735 0xb6cd51f4 + => fuse prog 0 736 0x77384870 + => fuse prog 0 737 0xc50ee4b2 + => fuse prog 0 738 0xa27e5132 + => fuse prog 0 739 0xeba887cf + => fuse prog 0 740 0x592c1e2b + => fuse prog 0 741 0xbb501799 + => fuse prog 0 742 0xee702e07 + => fuse prog 0 743 0xcf8ce73e + => fuse prog 0 744 0xfb55e2d5 + => fuse prog 0 745 0xeba6bbd2 + + * On i.MX 8 QM: + + => fuse prog 0 722 0xd436cc46 + => fuse prog 0 723 0x8ecccda9 + => fuse prog 0 724 0xb89e1601 + => fuse prog 0 725 0x5fada3db + => fuse prog 0 726 0xd454114a + => fuse prog 0 727 0xb6cd51f4 + => fuse prog 0 728 0x77384870 + => fuse prog 0 729 0xc50ee4b2 + => fuse prog 0 730 0xa27e5132 + => fuse prog 0 731 0xeba887cf + => fuse prog 0 732 0x592c1e2b + => fuse prog 0 733 0xbb501799 + => fuse prog 0 734 0xee702e07 + => fuse prog 0 735 0xcf8ce73e + => fuse prog 0 736 0xfb55e2d5 + => fuse prog 0 737 0xeba6bbd2 + +1.7 Verify SECO events +----------------------- + +If the fuses have been written properly, there should be no SECO events after +boot. To validate this, power on the board, and run ahab_status command on +U-Boot terminal. + +No events should be returned after this command: + + => ahab_status + Lifecycle: 0x0020, NXP closed + + No SECO Events Found! + +U-Boot will decode the SECO events and provide more details on the failure, +for example in case container image was signed with wrong keys and are not +matching the OTP SRK hashes: + + => ahab_status + Lifecycle: 0x0020, NXP closed + + SECO Event[0] = 0x0087EE00 + CMD = AHAB_AUTH_CONTAINER_REQ (0x87) + IND = AHAB_NO_AUTHENTICATION_IND (0xEE) + +Note: In case your SRK fuses are not programmed yet the event 0x0087FA00 may +also be displayed. + +1.8 Close the device +--------------------- + +After the device successfully boots a signed image without generating any +SECO security events, it is safe to close the device. The SECO lifecycle +should be changed from 0x20 NXP closed to 0x80 OEM closed. Be aware this +step can damage your board if a previous step failed. It is also +irreversible. Run on the U-Boot terminal: + + => ahab_close + +Now reboot the target, and run: + + => ahab_status + +The lifecycle value should now be 0x80 OEM closed. + +2. Authenticating the OS container +----------------------------------- + +The procedure for authenticating the OS container is similar as in Non-SPL +targets, for a complete procedure please refer to mx8_mx8x_secure_boot.txt +document available under doc/imx/hab/ahab/guides/ directory. + +References: +[1] AN12212: "Software Solutions for Migration Guide from Aarch32 to Aarch64" diff --git a/doc/imx/ahab/introduction_ahab.txt b/doc/imx/ahab/introduction_ahab.txt new file mode 100644 index 00000000000..6a4e4e4004c --- /dev/null +++ b/doc/imx/ahab/introduction_ahab.txt @@ -0,0 +1,305 @@ + +=======================================================+ + + i.MX8/8x AHAB Secure Boot introduction + + +=======================================================+ + +1. Introduction +---------------- + +The i.MX8 and i.MX8x family of applications processors introduce a new +secure boot concept. Due to the multi-core architecture the Security +Controller (SECO) and System Control Unit (SCU) are heavily involved in +the secure boot process. + +Step-by-step guides are available under doc/imx/hab/ahab/guides/ directory, +users familiar with AHAB architecture and CST PKI tree generation should +refer to this directory instead. + +1.1 The AHAB Secure Boot Architecture +-------------------------------------- + +The Advanced High Assurance Boot (AHAB) feature relies in digital signatures to +prevent unauthorized software execution during the device boot sequence. In +case a malware takes control of the boot sequence, sensitive data, services and +network can be impacted. + +The AHAB authentication is based on public key cryptography in which image +data is signed offline using one or more private keys. The resulting signed +image data is then verified on the i.MX processor using the corresponding +public keys. The public keys are included in the final binary and the SRK +Hash is programmed in the SoC fuses for establishing the root of trust. + +In i.MX8 and i.MX8x families the SCU is responsible to interface with the boot +media, managing the process of loading the firmware and software images in +different partitions of the SoC. The SECO is responsible to authenticate the +images and authorize the execution of them. + +1.1.1 The System Control Unit (SCU) +------------------------------------ + +The System Control Unit SCU is a subsystem equipped with a programmable M4 +core, which is responsible to handle the resource allocation, power, clocking, +IO configuration and muxing. + +The SCU is also responsible to interface between the rest of the system. In the +secure boot flow the SCU interfaces with the Security Controller (SECO), +requesting the image authentication. + +The System Control Unit FW (SCFW) is responsible to control all the +functionalities of the SCU. This firmware is distributed in a porting kit form. +Instructions to download the SCFW Porting Kit are available in the Linux BSP +Release Notes. + +Details about SCU can be found in the processors Reference Manual (RM). + +1.1.2 The Security Controller (SECO) +------------------------------------- + +The SECO is a M0+ core dedicated to handle the SoC security subsystem. The +controller communicates with SCU domain through a dedicate message unit (MU). + +The SECO has a dedicate ROM which is responsible to initialize low level +security features and to authenticate the SECO firmware previously loaded by +the SCU ROM. + +The SECO firmware provides security services at run-time to different domains +of the SoC, one of these being the capability of authenticate images. + +The SECO firmware is signed and distributed by NXP and is always authenticated +in OEM open and closed configuration, instructions to download the SECO FW are +available in the Linux BSP Release Notes. + +Details about SECO can be found in the processors Security Reference Manual +(SRM). + +1.2 The image container +------------------------ + +Due to the new the architecture, multiple firmwares and softwares are required +to boot i.MX8 and i.MX8x family devices. In order to store all the images in a +single binary the container image structure is used. + +At least two containers are needed for the boot process, the first container +must include only the SECO FW (provided by NXP). Additional containers can +contain one or multiple images, depending on the users specific application. + +The final binary is generated by the imx-mkimage tool. The tool can generate +additional containers and also combine all containers in a single binary. + +1.3 The i.MX8/8x secure boot flow +---------------------------------- + +As mentioned in the introduction, due to the multiple cores architecture the +i.MX8 boot sequence involves SCU ROM, SCFW, SECO ROM, and SECO FW. + +The diagram below illustrate the secure boot flow overview: + +System Controller │ Security Controller │ Cortex-M │ Cortex-A + (SCU) │ (SECO) │ │ + │ │ │ + ╔═════════════╗ │ ╔═════════════╗ ┌───────────┐ ┌─────────┐ + ║ SCU INIT ║ │ ║ SECO INIT ║ │ │ │ │ │ │ + ╚══════╤══════╝ │ ╚══════╤══════╝ │ │ v │ │ v + │ │ │ │ │ ┌──────────┐ │ │ ┌────────────┐ + ╔══════╧══════╗ │ │ │ │ │ Start M4 │ │ │ │ Start AP │ + ║Load SECO FW ║ │ │ │ │ │ IMG │ │ │ │ IMG │ + ╚══════╤══════╝ │ ╔══════╧══════╗ │ │ └──────────┘ │ │ └─────┬──────┘ + ├──────────────>║Auth SECO FW ║ │ │ │ │ │ + ╔══════╧══════╗ │ ╚══════╤══════╝ │ │ ┌────────────┘ │ │ + ║ Load SCU FW ║ │ │ │ │ │ │ │ + ║ and DCD ║ │ │ │ │ │ │ ┌─────┴──────┐ + ╚══════╤══════╝ │ ┌──────┴──────┐ │ │ │ │ │ Load │ + ├──────────────>│ Auth SCU FW │ │ │ │ │ │ Add AP IMG │ + │ │ │ and DCD │ │ │ │ │ └─────┬──────┘ + ╔══════╧══════╗ │ └──────┬──────┘ │ │ │ │ │ + ║ Run DCD ║<──────────────┤ │ │ │ │ │ + ╚══════╤══════╝ │ │ │ │ │ ┌───────────────┤ + │ │ │ │ │ │ │ │ │ + ╔══════╧══════╗ │ │ │ │ │ │ │ │ + ║ Load M4 IMG ║ │ │ │ │ │ │ │ │ + ╚══════╤══════╝ │ ┌──────┴──────┐ │ │ │ │ │ │ + ├──────────────>│ Auth M4 IMG │ │ │ │ │ │ │ + ╔══════╧══════╗ │ └──────┬──────┘ │ │ │ │ │ ┌─────┴──────┐ + ║ Load AP IMG ║ │ │ │ │ │ │ │ │ Run │ + ╚══════╤══════╝ │ ┌──────┴──────┐ │ │ │ │ │ │ Add AP IMG │ + ├──────────────>│ Auth AP IMG │ │ │ │ │ │ └────────────┘ + ╔══════╧══════╗ │ └─────────────┘ │ │ │ │ │ + ║Start SCU FW ║ │ ┌──────────────────┘ │ │ │ │ + ╚══════╤══════╝ │ │ │ │ │ │ + │ │ │ ┌─────────────────────┘ │ │ + ┌──────┴──────┐ │ │ │ │ │ │ + │ Start M4 ├──────┘ │ ┌──────────────────────┘ │ + └──────┬──────┘ │ │ │ │ │ + │ │ │ │ │ │ + ┌──────┴──────┐ │ │ │ │ │ + │ Start AP ├──────────┘ │ │ │ + └─────────────┘ │ │ │ │ + ┌───────────────────────┘ │ │ + │ │ │ │ + v │ │ │ + ┌─────────────┐ │ ┌─────────────┐ │ │ + │Request SECO ├───────>│ Auth AP IMG │ │ │ + └─────────────┘ │ └─────────────┘ │ │ + │ │ │ + +Notes: +All boxes enclosed by double dash (═) are performed at SCU/SECO ROM level. + +The sequence below explains the i.MX8 and i.MX8x boot flow: + +1 - At reset, the SCU ROM and SECO ROM both start execution. +2 - The SCU ROM reads the boot configuration and loads the SECO FW (First + container) from the boot media to the SECO TCM. +3 - A message is sent by the SCU ROM via MU requesting the SECO ROM to + authenticate the SECO FW which is signed using NXP key. +4 - The SCU ROM loads the second container from the boot media, this container + must contain at least the SCFW which is signed using the OEM keys. +5 - The SCU ROM loads the SCFW to the SCU TCM, a message is sent via MU + requesting the SECO FW to authenticate the SCFW and DCD table. +6 - The SCU ROM configures the DDR and loads the M4 and AP images included in + the second container to their respective load addresses. +7 - The SCU ROM request the SECO FW to authenticate the M4 image. +8 - The SCU ROM request the SECO FW to authenticate the AP image. This image + is the initial AP core software, depending in the U-Boot target it can + be the U-Boot and ATF or only SPL. +9 - The SCFW is initialized and starts the ARM Cortex-M and Cortex-A cores. +10 - From this point additional containers can be loaded by Cortex-M and + Cortex-A cores and authenticated by SECO, the AP SW must interface with + SCU by calling the sc_misc_seco_authenticate() API function. In current + U-Boot implementation the additional image can be the Linux Kernel binary + or the U-Boot proper and ATF. Details about current U-Boot implementation + can be found in AHAB guides included in doc/imx/hab/ahab/guides/ directory. + +2. Generating a PKI tree +------------------------- + +The first step is to generate the private keys and public keys certificates. +The AHAB architecture is based on a Public Key Infrastructure (PKI) tree. + +The Code Signing Tools package contains an OpenSSL based key generation script +under keys/ directory. The ahab_pki_tree.sh script generates a PKI tree +containing 4 Super Root Keys (SRK), possible to also include a subordinate +SGK key. + +The AHAB supports both RSA and ECC keys, a new PKI tree can be generated by +following the example below: + +- Generating a P384 ECC PKI tree on CST (starting from v3.1.0): + + $ ./ahab_pki_tree.sh + ... + Do you want to use an existing CA key (y/n)?: n + Do you want to use Elliptic Curve Cryptography (y/n)?: y + Enter length for elliptic curve to be used for PKI tree: + Possible values p256, p384, p521: p384 + Enter the digest algorithm to use: sha384 + Enter PKI tree duration (years): 5 + Do you want the SRK certificates to have the CA flag set? (y/n)?: n + +The diagram below illustrate the PKI tree generated: + + ┌─────────┐ + │ CA │ + └────┬────┘ + │ + │ + ┌───────────────┬────────┴────────┬───────────────┐ + │ │ │ │ + │ │ │ │ + v v v v + ┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ + │ SRK1 │ │ SRK2 │ │ SRK3 │ │ SRK4 │ + └────────┘ └────────┘ └────────┘ └────────┘ + +2.1 Generating a PKI tree including a subordinate SGK key +---------------------------------------------------------- + +The ahab_pki_tree.sh script is also able to generate a PKI tree containing a +subordinate key of the SRK, this key can be used to verify the signature +included in the final signed image. + +Users should set the CA flag when generating the SRK certificates. + +- Generating a P384 ECC PKI tree with a subordinate SGK key on CST (starting +from v3.1.0): + + $ ./ahab_pki_tree.sh + ... + Do you want to use an existing CA key (y/n)?: n + Do you want to use Elliptic Curve Cryptography (y/n)?: y + Enter length for elliptic curve to be used for PKI tree: + Possible values p256, p384, p521: p384 + Enter the digest algorithm to use: sha384 + Enter PKI tree duration (years): 5 + Do you want the SRK certificates to have the CA flag set? (y/n)?: y + +The diagram below illustrate the PKI tree generated: + + ┌─────────┐ + │ CA │ + └────┬────┘ + │ + │ + ┌───────────────┬────────┴────────┬───────────────┐ + │ │ │ │ + v v v v + ┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ + │ SRK1 │ │ SRK2 │ │ SRK3 │ │ SRK4 │ + └────┬───┘ └───┬────┘ └────┬───┘ └───┬────┘ + │ │ │ │ + v v v v + ┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ + │ SGK1 │ │ SGK2 │ │ SGK3 │ │ SGK4 │ + └────────┘ └────────┘ └────────┘ └────────┘ + +Note: Due to a limitation in i.MX8QXP B0 silicon it's not possible to use RSA +4096-bit SRK keys with an additional subordinate SGK key. + +2.2 Generating a SRK Table and SRK Hash +---------------------------------------- + +The next step is to generated the SRK Table and its respective SRK Table Hash +from the SRK public key certificates created in one of the steps above. + +In the AHAB architecture, the SRK Table is included in the signed image and the +SRK Hash is programmed in the SoC SRK_HASH[511:0] fuses. + +On the target device during the authentication process the AHAB code verify the +SRK Table against the SoC SRK_HASH fuses, in case the verification is successful +the root of trust is established and the AHAB code can progress with the image +authentication. + +The srktool can be used for generating the SRK Table and its respective SRK +Table Hash. + +- Generating SRK Table and SRK Hash in Linux 64-bit machines: + + $ cd ../crts/ + $ ../linux64/bin/srktool -a -s sha384 -t SRK_1_2_3_4_table.bin \ + -e SRK_1_2_3_4_fuse.bin -f 1 -c \ + SRK1_sha384_secp384r1_v3_usr_crt.pem,\ + SRK2_sha384_secp384r1_v3_usr_crt.pem,\ + SRK3_sha384_secp384r1_v3_usr_crt.pem,\ + SRK4_sha384_secp384r1_v3_usr_crt.pem + +- Optionally users can check if the sha512sum of SRK_1_2_3_4_table matches with + the SRK_1_2_3_4_fuse.bin: + + $ od -t x4 --endian=big SRK_1_2_3_4_fuse.bin + 0000000 01b04697 0253376b 2066fe56 aaef9a91 + 0000020 e62e09d8 14fb7e36 d5b38d05 0982edab + 0000040 7ada6576 2f6b4f59 1fd9347e 46e7305d + 0000060 46e34bf0 89780bd1 c809e714 a17e2f4e + + $ sha512sum SRK_1_2_3_4_table.bin + 01b046970253376b2066fe56aaef9a91\ + e62e09d814fb7e36d5b38d050982edab\ + 7ada65762f6b4f591fd9347e46e7305d\ + 46e34bf089780bd1c809e714a17e2f4e\ + SRK_1_2_3_4_table.bin + +NOTE: The commands above cannot be used as reference to program the SoC + SRK_HASH fuses. + +The SRK_1_2_3_4_table.bin and SRK_1_2_3_4_fuse.bin files can be used in further +steps as explained in AHAB guides available under doc/imx/hab/ahab/guides/ +directory. diff --git a/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt b/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt index bbe489714bc..589fd56f068 100644 --- a/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt +++ b/doc/imx/habv4/csf_examples/additional_images/csf_additional_images.txt @@ -29,6 +29,6 @@ # Key slot index used to authenticate the image data Verification index = 2 # Authenticate Start Address, Offset, Length and file - Blocks = 0x80800000 0x00000000 0x80EEA020 "zImage", \ - 0x83800000 0x00000000 0x8380B927 "imx7d-sdb.dtb", \ - 0x84000000 0x00000000 0x840425B8 "uTee-7dsdb" + Blocks = 0x80800000 0x00000000 0x006EA000 "zImage", \ + 0x83800000 0x00000000 0x0000B927 "imx7d-sdb.dtb", \ + 0x84000000 0x00000000 0x000425B8 "uTee-7dsdb" diff --git a/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_enc.txt b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_enc.txt new file mode 100644 index 00000000000..96083a6a589 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_enc.txt @@ -0,0 +1,50 @@ +[Header] + Version = 4.2 + Hash Algorithm = sha256 + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + Engine = CAAM + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target Index = 2 + # Key to install + File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # Key slot index used to authenticate the image data + Verification index = 2 + # This Authenticate Data command covers the IVT and DCD Data + # The image file referenced will remain unmodified by CST + Blocks = 0x877ff400 0x000 0xc00 "u-boot-dtb.imx" + +[Install Secret Key] + # Install the blob + Verification Index = 0 + Target Index = 0 + Key = "dek.bin" + Key Length = 128 + # Start address + padding 0x2000 + length + Blob Address = 0x878a0000 + +[Decrypt Data] + # The decrypt data command below causes CST to modify the input + # file and encrypt the specified block of data. This image file + # is a copy of the file used for the authentication command above + Verification Index = 0 + Mac Bytes = 16 + Blocks = 0x87800000 0x00000c00 0x9e000 "u-boot-dtb.imx-enc" diff --git a/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_sign_enc.txt b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_sign_enc.txt new file mode 100644 index 00000000000..7e508020af3 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx6_mx7/csf_u-boot_sign_enc.txt @@ -0,0 +1,53 @@ +[Header] + Version = 4.2 + Hash Algorithm = sha256 + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + Engine = CAAM + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target Index = 2 + # Key to install + File= "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # This Authenticate Data commandcovers both clear and encrypted data. + # The image file referenced will remain unmodified by CST. + # Key slot index used to authenticate the image data + Verification index = 2 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x877ff400 0x000 0x0009ec00 "u-boot-dtb.imx-enc" + +[Install Secret Key] + # Install the blob - This will manage a new key that will not be used in + # the final image, so the file name has to be different + Verification Index = 0 + Target Index = 0 + Key = "dek-dummy.bin" + Key Length = 128 + # Start address + padding 0x2000 + length + Blob Address = 0x878a000 + +[Decrypt Data] + # The decrypt Data command is a place holder to ensure the + # CSF includes the decrypt data command from the first pass. + # The file that CST will encrypt will not be used, so the file + # name has to be different. + Verification Index = 0 + Mac Bytes = 16 + Blocks = 0x87800000 0x00000c00 0x9e000 "u-boot-dtb.imx-dummy" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt new file mode 100644 index 00000000000..d9218ab4311 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit.txt @@ -0,0 +1,36 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target index = 2 + # Key to install + File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # Key slot index used to authenticate the image data + Verification index = 2 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x401fcdc0 0x057c00 0x01020 "flash.bin", \ + 0x40200000 0x05AC00 0x9AAC8 "flash.bin", \ + 0x00910000 0x0F56C8 0x09139 "flash.bin", \ + 0xFE000000 0x0FE804 0x4D268 "flash.bin", \ + 0x4029AAC8 0x14BA6C 0x06DCF "flash.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt new file mode 100644 index 00000000000..be0b353084d --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit_enc.txt @@ -0,0 +1,49 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Unlock] + Engine = CAAM + Features = MID + +[Install Key] + Verification index = 0 + Target index = 2 + File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + Verification index = 2 + Blocks = 0x401fcdc0 0x57c00 0x1020 "flash-spl-enc.bin" + +[Install Secret Key] + # Install the blob + Verification Index = 0 + Target Index = 0 + Key = "dek_fit.bin" + Key Length = 128 + # Fixed address defined in imx-mkimage project in iMX8M/soc.mak file + # DEK_BLOB_LOAD_ADDR = 0x40400000 + Blob Address = 0x40400000 + +[Decrypt Data] + # The decrypt data command below causes CST to modify the input + # file and encrypt the specified block of data. This image file + # is a copy of the file used for the authentication command above + Verification Index = 0 + Mac Bytes = 16 + Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \ + 0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \ + 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt new file mode 100644 index 00000000000..9a41c8bb400 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf_fit_sign_enc.txt @@ -0,0 +1,53 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Unlock] + Engine = CAAM + Features = MID + +[Install Key] + Verification index = 0 + Target index = 2 + File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + Verification index = 2 + Blocks = 0x401fcdc0 0x57c00 0x1020 "flash-spl-fit-enc.bin", \ + 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \ + 0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \ + 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin" + +[Install Secret Key] + # Install the blob + Verification Index = 0 + Target Index = 0 + Key = "dek_fit_dummy.bin" + Key Length = 128 + # Fixed address defined in imx-mkimage project in iMX8M/soc.mak file + # DEK_BLOB_LOAD_ADDR = 0x40400000 + Blob Address = 0x40400000 + +[Decrypt Data] + # The decrypt data command below causes CST to modify the input + # file and encrypt the specified block of data. This image file + # is a copy of the file used for the authentication command above + Verification Index = 0 + Mac Bytes = 16 + Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc-dummy.bin", \ + 0x920000 0x113540 0xA160 "flash-spl-fit-enc-dummy.bin", \ + 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc-dummy.bin" + diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt new file mode 100644 index 00000000000..39adf7a3eb8 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl.txt @@ -0,0 +1,37 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + # Index of the key location in the SRK table to be installed + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + # Key used to authenticate the CSF data + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Unlock] + # Leave Job Ring and DECO master ID registers Unlocked + Engine = CAAM + Features = MID + +[Install Key] + # Key slot index used to authenticate the key to be installed + Verification index = 0 + # Target key slot in HAB key store where key will be installed + Target index = 2 + # Key to install + File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + # Key slot index used to authenticate the image data + Verification index = 2 + # Authenticate Start Address, Offset, Length and file + Blocks = 0x7e0fc0 0x1a000 0x2a600 "flash.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl_enc.txt new file mode 100644 index 00000000000..de71710e6c1 --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl_enc.txt @@ -0,0 +1,50 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Unlock] + Engine = CAAM + Features = MID + +[Install Key] + Verification index = 0 + Target index = 2 + File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + Verification index = 2 + Blocks = 0x7e0fc0 0x0 0x40 "flash.bin" + +[Install Secret Key] + # Install the blob + Verification Index = 0 + Target Index = 0 + Key = "dek_spl.bin" + Key Length = 128 + # Authenticate Start Address + SPL & DDR FW image length + CSF Padding + # 0x7E0FC0 + 0x2c400 + 0x2000 + Blob Address = 0x80F3C0 + +[Decrypt Data] + # The decrypt data command below causes CST to modify the input + # file and encrypt the specified block of data. This image file + # is a copy of the file used for the authentication command above + Verification Index = 0 + Mac Bytes = 16 + # Start Address = Start Address + SPL header = 0x7E0FC0 + 0x40 = 0x7E1000 + # Offset = Image offset (image_off) = 0x40 + # Decrypt size = Image length - SPL header = 0x2c400 - 0x40 = 0x2C3C0 + Blocks = 0x7E1000 0x40 0x2C3C0 "flash-spl-enc.bin" diff --git a/doc/imx/habv4/csf_examples/mx8m/csf_spl_sign_enc.txt b/doc/imx/habv4/csf_examples/mx8m/csf_spl_sign_enc.txt new file mode 100644 index 00000000000..b1b8db1a62f --- /dev/null +++ b/doc/imx/habv4/csf_examples/mx8m/csf_spl_sign_enc.txt @@ -0,0 +1,47 @@ +[Header] + Version = 4.3 + Hash Algorithm = sha256 + Engine = CAAM + Engine Configuration = 0 + Certificate Format = X509 + Signature Format = CMS + +[Install SRK] + File = "../crts/SRK_1_2_3_4_table.bin" + Source index = 0 + +[Install CSFK] + File = "../crts/CSF1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate CSF] + +[Unlock] + Engine = CAAM + Features = MID + +[Install Key] + Verification index = 0 + Target index = 2 + File = "../crts/IMG1_1_sha256_2048_65537_v3_usr_crt.pem" + +[Authenticate Data] + Verification index = 2 + Blocks = 0x7E0FC0 0x0 0x2C400 "flash-spl-enc.bin" + +[Install Secret Key] + # Install the blob + Verification Index = 0 + Target Index = 0 + Key = "dek_spl_dummy.bin" + Key Length = 128 + # Authenticate Start Address + Image length + CSF Padding + # 0x7E0FC0 + 0x2c400 + 0x2000 + Blob Address = 0x80F3C0 + +[Decrypt Data] + # The decrypt data command below causes CST to modify the input + # file and encrypt the specified block of data. This image file + # is a copy of the file used for the authentication command above + Verification Index = 0 + Mac Bytes = 16 + Blocks = 0x7E1000 0x40 0x2C3C0 "flash-spl-enc-dummy.bin" diff --git a/doc/imx/habv4/guides/mx6_mx7_encrypted_boot.txt b/doc/imx/habv4/guides/mx6_mx7_encrypted_boot.txt new file mode 100644 index 00000000000..53cd9bbc831 --- /dev/null +++ b/doc/imx/habv4/guides/mx6_mx7_encrypted_boot.txt @@ -0,0 +1,277 @@ ++==========================================================+ ++ i.MX6, i.MX7 U-Boot Encrypted Boot guide using HABv4 + ++==========================================================+ + +1. HABv4 Encrypted Boot process +------------------------------- + +This document describes a step-by-step procedure on how to encrypt and +sign an U-Boot image. It is assumed that the reader is familiar +with basic HAB concepts and has already followed the mx6_mx7_secure_boot.txt +guide and got a working closed device. + +Details about HAB and encrypted boot process can be found in application +notes AN4581[1] and AN12056[2] and in the introduction_habv4.txt document. + +Before continuing, be sure to have fatwrite and dek_blob commands +available in U-Boot. If not, enable them in Kconfig and rebuild +U-Boot: + +- Defconfig + + CONFIG_FAT_WRITE=y + CONFIG_CMD_DEKBLOB=y + CONFIG_CMD_PRIBLOB=y + +- Kconfig + + File systems -> Enable FAT filesystem support-> Enable FAT filesystem + write support + ARM architecture -> Support the 'dek_blob' command + ARM architecture -> Support the set_priblob_bitfield command + +1.1 Building an encrypted U-Boot image +-------------------------------------- + +This U-Boot is built the same way the one from the secure document is, +so it provides the same access the the HAB APIs, extra functions +for HAB, etc... + +However, the layout of the new image is different, as a part of it is +encrypted, and a DEK blob is appended at the end. The diagram below +illustrates an encrypted u-boot-dtb.imx image layout: + + ----------------------- +-----------------------------+ <--- *start + ^ ^ | Image Vector Table | + | | +-----------------------------+ <--- *boot_data + | | | Boot Data | + | Plain | +-----------------------------+ <--- *dcd + | text | | DCD Table | + | | +-----------------------------+ + Signed | v | Padding | + data | ------- +-----------------------------+ <--- *entry + | ^ | | + | | | | + | Encrypted | | u-boot-dtb.bin | + | data | | | + | | | | + | | +-----------------------------+ + v v | Padding | + ----------------------- +-----------------------------+ <--- *csf + ^ | Command Sequence File | + 0x2000 | | (commands + SRK table + | + (in bytes) | | signatures + certificates + | + v | Nonce + MAC) | + ------- +-----------------------------+ + | Padding | + +-----------------------------+ <--- *csf + 0x2000 + | DEK Blob | + +-----------------------------+ + | Padding | + +-----------------------------+ + +1.2 Get a secure boot working +----------------------------- + +You need to go through all the steps described into the +mx6_mx7_secure_boot.txt guide, and get a signed U-Boot which can +boot successfully on a closed target. Otherwise, the following +steps will not work. + +1.3 Compile the CST to enable the encrypting feature +---------------------------------------------------- + +The encrypting feature is not enabled by default. You need to +execute the following commands to enable it: + + $ sudo apt-get install libssl-dev openssl + $ cd /code/back_end/src + $ gcc -o cst_encrypted -I ../hdr -L ../../../linux64/lib *.c + -lfrontend -lcrypto + $ cp cst_encrypted ../../../ + +1.4 Creating the CSF description files +-------------------------------------- + +The CSF contains all the commands that the ROM executes during the +secure boot. These commands instruct the HAB on which memory areas +of the image to authenticate, which keys to install, use, etc... + +CSF examples for encrypted boot are available under +doc/imx/hab/habv4/csf_examples/ directory. + +For both CSF, first part is same compared to the CSF used for +the secure boot step. +Here we describe how to encrypt the U-Boot image and then sign it. + +1.4.1 csf_u-boot_enc.txt +------------------------- + +This first CSF is used to encrypt the U-Boot image and generate the +dek.bin file. The Authenticate Data command has to be modified, and +two new commands have to be added: + +- Modify the Authenticate Data command to only cover IVT and DCD: + + Blocks = 0x877ff400 0x00000000 0x00000c00 "u-boot-dtb.imx" + +- Add the new Install Secret Key command to generate the dek.bin + file and install the blob. The parameter which depends of your + configuration is the Blob Address. Padding of 0x2000 is + recommended. Following the csf_uboot.txt data for instance: + + Blob Address = Authenticate Start Address + Padding + length + = 0x877ff400 + 0x2000 + 0x9ec00 = 0x878a0000 + +- Add the new Decrypt Data command to encrypt the file. As the file + specified in parameter will be modified, we suggest to copy it. + Then modify the Blocks command depending of your U-Boot image. + In our example: + + $ cp u-boot-dtb.imx u-boot-dtb.imx-enc + Block = (Authenticate start addr + 0xc00) 0xc00 (length - 0xc00) + u-boot-dtb.imx-enc + = (0x877ff400 + 0xc00) 0xc00 (0x9ec00 - 0xc00) + u-boot-dtb.imx-enc + = 0x87800000 0xc00 0x9e000 u-boot-dtb.imx-enc + +1.4.2 csf_u-boot_sign_enc.txt +----------------------------- + +This second CSF is used to sign the encrypted U-Boot image previously +generated (u-boot-dtb.imx-enc). The Authenticate Data part has also +to be changed, the modifications are the following: + +- The Authenticate Data command is same compared to the one in + csf_uboot.txt file, except that this time, the file parameter + is the file previously encrypted: u-boot-dtb.imx-enc. + + Blocks = 0x877ff400 0x000 0x0009ec00 "u-boot-dtb.imx-enc" + +- For the two new commands, we do not want to they modify our previously + signed/generated files. Therefore, for the Key parameter of the + Install Secret Key command, the value is now dek-dummy.bin, which + will generate a new dek file instead of erasing the previous one. + About the decrypt data command, you need to copy the u-boot-dtb.imx + file again in a u-boot-dtb.imx-dummy file, to not replace the + original encrypted file with an encrypted one: + + Key = "dek-dummy.bin" + Blocks = 0x87800000 0x00000c00 0x9e000 "u-boot-dtb.imx-dummy" + +1.5 Encrypt the U-Boot image +---------------------------- + +The image is encrypted using the Code Signing Tool. It generates also +a CSF binary and a dek.bin file, which will be used on the future +steps below. + +- Create the CSF binary file and encrypt the U-Boot image + + $ ./cst_encrypted -i csf_u-boot_enc.txt -o csf_u-boot_enc.bin + +1.6 Sign the encrypted U-Boot image +----------------------------------- + +The image is then signed using the Code Signing Tool. It also +generate a CSF binary, which will be used on the future steps below. + +- Create the CSF binary file and sign the encrypted U-Boot image + + $ ./cst_encrypted -i csf_u-boot_sign_enc.txt -o csf_u-boot_sign_enc.bin + +1.7 Swap Nonce/MAC from csf_u-boot_enc.bin to csf_u-boot_sign_enc.bin +--------------------------------------------------------------------- + +First, calculate Nonce/MAC size based on MAC bytes value +in CSF. As Mac bytes is 16: + + Nonce/MAC size = Nonce size + MAC bytes + CSF header for Nonce/Mac + = 12 + 16 + 8 = 36 bytes + +Then, calculate Nonce/MAC offset in CSF: + + MAC offset = csf_u-boot-enc.bin size - Nonce/MAC size + = 3972 - 36 = 3936 Bytes + +In the next step, extract Nonce/NAC from the first CSF: + + $ dd if=csf_u-boot_enc.bin of=noncemac.bin bs=1 skip=3936 count=36 + +Finally, replace the MAC of csf_u-boot_sign_enc.bin with the extracted +one: + + $ dd if=noncemac.bin of=csf_u-boot_sign_enc.bin bs=1 seek=3936 count=36 + +1.8 Generate encryptedu-boot with no dek +---------------------------------------- + +As described in the layout in the first part of this document, the +final image is composed of these different parts padded to known +values, to make it compliant with the CSF. + +First, pad the CSF to 0x2000: + + $ objcopy -I binary -O binary --pad-to 0x2000 --gap-fill=0xff + csf_u-boot_sign_enc.bin csf_u-boot_sign_enc_padded.bin + +Then, append this file to the encrypted U-Boot image: + + $ cat u-boot-dtb.imx-enc csf_u-boot_sign_enc_padded.bin > + u-boot_encrypted_no_dek.bin + +Pad this new file to width+offset (0x9ec00 + 0x2000 = 0xa0c00): + + $ objcopy -I binary -O binary --pad-to 0xa0c00 --gap-fill=0x00 + u-boot_encrypted_no_dek.bin u-boot_encrypted_no_dek_padded.bin + +1.9 Generate the DEK Blob +------------------------- +The missing part to get our final U-Boot encrypted image is a DEK +blob. To generate it, copy the dek.bin file generated at step 1.5 +on the Boot partition of your SD Card. Then interrupt the boot +and your chip. You need the fatwrite and dek_blob command, which +should be enabled by the secure boot. If not, you have to enable +them in Kconfig and recompile U-Boot + +Run the following commands: + + => mmc list + FSL_SDHC: 0 (SD) #index to use for mmc in following commands + => fatload mmc 0 0x80800000 dek.bin + => dek_blob 0x80800000 0x80801000 128 + => fatwrite mmc 0 0x80801000 dek_blob.bin 0x48 + +1.10 Finalize the encrypted U-Boot image +---------------------------------------- + +Finally, copy the generated dek_blob.bin file from your SDCard to +your CST repository. Append it with the last padded file to get your +final image: + + $ cat u-boot_encrypted_no_dek_padded.bin dek_blob.bin > + u-boot_encrypted.bin + +If the image does not boot, please verify the size of your +U-Boot image, the length specified into CSF and the padding values. + +2. About the PRIBLOB bitfield from CAAM SCFGR register +------------------------------------------------------ + +It is highly recommended to set the PRIBLOB bitfield from the CAAM +SCFGR register to 0x3 once your encrypted U-Boot image is completed. +To do so, a command has been implemented in u-boot: + + => set_priblob_bitfield + +Once this bitfield is set to 0x3, it ensures cryptographic separation +of private blob types avoiding any modification or replacement of +DEK blobs. Newly created blobs will be incompatible with blobs +required to decrypt an encrypted boot image. When the HAB later +executes the command to decrypt the DEK, an incompatible DEK blob +will be detected and cause an error. A substitute encrypted boot image +will not be decrypted, and will not be executed. + +References: +[1] AN4581: "i.MX Secure Boot on HABv4 Supported Devices" +[2] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices" diff --git a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt index 20fff937b66..d0e7c70e7cc 100644 --- a/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt +++ b/doc/imx/habv4/guides/mx6_mx7_secure_boot.txt @@ -110,6 +110,23 @@ the U-Boot build, the example below is a log for mx7dsabresd_defconfig target: Block = 0x877ff400 0x00000000 0x0009ec00 "u-boot-dtb.imx" +1.3.1 Avoiding Kernel crash when OP-TEE is enabled +--------------------------------------------------- + +For devices prior to HAB v4.4.0, the HAB code locks the Job Ring and DECO +master ID registers in HAB closed configuration. In case the user specific +application requires any changes in CAAM MID registers it's necessary to +add the "Unlock CAAM MID" command in CSF file. + +The current NXP OP-TEE implementation expects the CAAM registers to be unlocked +when configuring CAAM to operate in non-secure TrustZone world. + +- Add Unlock MID command in CSF: + + [Unlock] + Engine = CAAM + Features = MID + 1.4 Signing the U-Boot binary ------------------------------ @@ -213,6 +230,30 @@ the example below: HAB Configuration: 0xf0, HAB State: 0x66 No HAB Events Found! +1.6.1 Verifying HAB events in i.MX7ULP +--------------------------------------- + +When booting i.MX7ULP in low power or dual boot modes the M4 binary is +authenticated by an independent HAB in M4 ROM code using a +different SRK key set. + +The U-Boot provides a M4 option in hab_status command so users can retrieve +M4 HAB failure and warning events. + +- Verify HAB M4 events: + + => hab_status m4 + + Secure boot disabled + + HAB Configuration: 0xf0, HAB State: 0x66 + No HAB Events Found! + +As HAB M4 API cannot be called from A7 core the command is parsing the M4 HAB +persistent memory region, M4 software should not modify this reserved region. + +Details about HAB persistent memory region can be found in AN12263[2]. + 1.7 Closing the device ----------------------- @@ -301,7 +342,13 @@ and word according to the i.MX device: | i.MX7ULP | bank 1 word 1 | 0x000000C0 | +--------------+---------------+------------+ -2. Extending the root of trust +2. Secure boot in SDP mode +--------------------------- + +For secure boot in SDP mode, please refer to the "HABv4 closed chip support" +chapter in the UUU documentation[3]. + +3. Extending the root of trust ------------------------------- The High Assurance Boot (HAB) code located in the on-chip ROM provides an @@ -335,7 +382,7 @@ The diagram below illustrate the zImage layout: | Padding (optional) | +-----------------------------+ -2.1 Padding the image +3.1 Padding the image ---------------------- The zImage must be padded to the next boundary address (0x1000), for instance @@ -348,7 +395,7 @@ The tool objcopy can be used for padding the image. $ objcopy -I binary -O binary --pad-to 0x64A000 --gap-fill=0x00 \ zImage zImage_pad.bin -2.2 Generating Image Vector Table +3.2 Generating Image Vector Table ---------------------------------- The HAB code requires an Image Vector Table (IVT) for determining the image @@ -366,7 +413,7 @@ Note: The load Address may change depending on the device. $ cat zImage_pad.bin ivt.bin > zImage_pad_ivt.bin -2.3 Signing the image +3.3 Signing the image ---------------------- A CSF file has to be created to sign the image. HAB does not allow to change @@ -384,7 +431,7 @@ directory. $ cat zImage_pad_ivt.bin csf_zImage.bin > zImage_signed.bin -2.4 Verifying HAB events +3.4 Verifying HAB events ------------------------- The U-Boot includes the hab_auth_img command which can be used for @@ -398,5 +445,6 @@ loaded at the load address specified in the IVT. If no HAB events were found the zImage is successfully signed. References: -[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using - HABv4" - Rev 2. +[1] AN4581: "i.MX Secure Boot on HABv4 Supported Devices" +[2] AN12263: "HABv4 RVT Guidelines and Recommendations" +[3] https://github.com/NXPmicro/mfgtools/releases/ diff --git a/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt b/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt index fde0f27efdc..3be971f0311 100644 --- a/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt +++ b/doc/imx/habv4/guides/mx6_mx7_spl_secure_boot.txt @@ -176,6 +176,12 @@ complete procedure please refer to section "1.5 Programming SRK Hash" in mx6_mx7_secure_boot.txt document available under doc/imx/habv4/guides/ directory. +2. Secure boot in SDP mode +--------------------------- + +For secure boot in SDP mode, please refer to the "HABv4 closed chip support" +chapter in the UUU documentation[2]. + References: -[1] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using - HABv4" - Rev 2. +[1] AN4581: "i.MX Secure Boot on HABv4 Supported Devices" +[2] https://github.com/NXPmicro/mfgtools/releases/ diff --git a/doc/imx/habv4/guides/mx8m_encrypted_boot.txt b/doc/imx/habv4/guides/mx8m_encrypted_boot.txt new file mode 100644 index 00000000000..14dc65ed44d --- /dev/null +++ b/doc/imx/habv4/guides/mx8m_encrypted_boot.txt @@ -0,0 +1,500 @@ + +======================================================+ + + i.MX8M family Encrypted Boot guide using HABv4 + + +======================================================+ + +1. HABv4 Encrypted Boot process +------------------------------- + +This document describes a step-by-step procedure on how to encrypt and sign a +bootloader image for i.MX8M family devices. It is assumed that the reader is +familiar with basic HAB concepts and has already closed the device, step-by-step +procedure can be found in mx8m_secure_boot.txt guide. + +Details about encrypted boot can be found in application note AN12056[1] and +in the introduction_habv4.txt document. + +The steps described in this document were based in i.MX8MM device, the same +concept can be applied to other i.MX8M family devices. + +1.1 Understanding the encrypted flash.bin image layout +------------------------------------------------------ + +As described in mx8m_secure_boot.txt guide a single binary is used to boot the +device, the imx-mkimage tool combines all the input images in a FIT structure, +generating a flash.bin binary. + +The encrypted boot image requires a DEK (Data Encryption Key) blob on each time +HABv4 is used to decrypt an image. The DEK blob is used as a security layer to +wrap and store the DEK off-chip using the OTPMK which is unique per device. +More details can be found in AN12056 application note. + +The diagram below illustrates an encrypted flash.bin image layout: + + +-----------------------------+ + | | + | *Signed HDMI/DP FW | + | | + +-----------------------------+ + | Padding | + ------------------ +-----------------------------+ -------- + ^ | IVT - SPL | ^ + Signed | ------- +-----------------------------+ | + Data | Enc ^ | u-boot-spl.bin | | + | Data | | + | | SPL + v v | DDR FW | | Image + ------------------ +-----------------------------+ | + | CSF - SPL + DDR FW | v + +-----------------------------+ -------- + | DEK Blob | + +-----------------------------+ + | Padding | + ------- +-----------------------------+ -------- + Signed ^ | FDT - FIT | ^ + Data | +-----------------------------+ | + v | IVT - FIT | | + ------- +-----------------------------+ | + | CSF - FIT | | + ------------------ +-----------------------------+ | + ^ | u-boot-nodtb.bin | | FIT + | +-----------------------------+ | Image + Signed and | | u-boot.dtb | | + Encrypted | +-----------------------------+ | + Data | | bl31.bin (ATF) | | + | +-----------------------------+ | + v | OP-TEE | | + ------------------ +-----------------------------+ | + | DEK Blob | v + +-----------------------------+ -------- + * Only supported on i.MX8M series + +1.2 Enabling the encrypted boot support in U-Boot +-------------------------------------------------- + +For deploying an encrypted boot image additional U-Boot tools are needed, +please be sure to have the following features enabled, this can be achieved +by following one of the methods below: + +- Defconfig + + CONFIG_IMX_HAB=y + CONFIG_FAT_WRITE=y + CONFIG_CMD_DEKBLOB=y + CONFIG_IMX_OPTEE_DEK_ENCAP=y + CONFIG_CMD_PRIBLOB=y + +- Kconfig + + ARM architecture -> Support i.MX HAB features + ARM architecture -> Support the 'dek_blob' command + ARM architecture -> Support the set_priblob_bitfield command + File systems -> Enable FAT filesystem support-> Enable FAT filesystem + write support + +1.3 Enabling the encrypted boot support in CST +----------------------------------------------- + +The encryption feature is not enabled by default in Code Signing tools (CST). +The CST backend must be recompiled, execute the following commands to enable +encryption support in CST: + + $ sudo apt-get install libssl-dev openssl + $ cd /code/back_end/src + $ gcc -o cst_encrypted -I ../hdr -L ../../../linux64/lib *.c + -lfrontend -lcrypto + $ cp cst_encrypted ../../../linux64/bin/ + +1.4 Building OP-TEE and ATF to support DEK blob tool +----------------------------------------------------- + +The DEK blob must be created by a software running in Arm TrustZone Secure +World, the CAAM block takes into consideration the TrustZone configuration +when encapsulating the DEK and the resulting blob can be only decapsulated +by a SW running in the same configuration. As ROM code is running in ARM +TrustZone secure world we must encapsulate the blobs using OP-TEE. + +- Building ATF to support OP-TEE: + + $ make PLAT= SPD=opteed bl31 + +- Building OP-TEE to support DEK blob encapsulation: + + $ CFG_NXPCRYPT=y CFG_GEN_DEK_BLOB=y source ./scripts/nxp_build.sh + +* OP-TEE debug logs can be enabled by adding CFG_TEE_CORE_LOG_LEVEL=4 in + command line above. + +1.5 Preparing the fit image +---------------------------- + +As explained in mx8m_secure_boot.txt document the imx-mkimage project is used to +combine all the images in a single flash.bin binary. + +Copy all the binaries generated (U-Boot images, bl31.bin, tee.bin and Firmware) +into iMX8M directory and run the following commands according to the target +device: + +- Create a dummy DEK blob: + + $ dd if=/dev/zero of=iMX8M/dek_blob_fit_dummy.bin bs=96 count=1 && sync + +- Assembly flash.bin binary: + + $ make SOC= flash_spl_uboot + +The mkimage log will be used during the encrypted boot procedure to create the +Command Sequence File (CSF): + +- imx-mkimage build log: + + Loader IMAGE: + header_image_off 0x0 + dcd_off 0x0 + image_off 0x40 + csf_off 0x2c400 + spl hab block: 0x7e0fc0 0x0 0x2c400 + + Second Loader IMAGE: + sld_header_off 0x57c00 + sld_csf_off 0x58c20 + sld hab block: 0x401fcdc0 0x57c00 0x1020 + +- Additional HAB information is provided by running the following command: + + $ make SOC= print_fit_hab + + ./../scripts/pad_image.sh bl31.bin + ./../scripts/pad_image.sh u-boot-nodtb.bin fsl-imx8mm-evk.dtb + TEE_LOAD_ADDR=0xbe000000 ATF_LOAD_ADDR=0x00920000 VERSION=v1 \ + ./print_fit_hab.sh 0x60000 fsl-imx8mm-evk.dtb + 0x40200000 0x5AC00 0xB0318 + 0x402B0318 0x10AF18 0x8628 + 0x920000 0x113540 0xA160 + 0xBE000000 0x11D6A0 0x48520 + +1.6 Creating the CSF description file for SPL + DDR FW image +------------------------------------------------------------- + +The CSF contains all the commands that the ROM executes during the secure boot. +These commands instruct the HAB on which memory areas of the image to +authenticate and/or decrypt, which keys to install, use, etc... + +CSF examples for encrypted boot are available under +doc/imx/hab/habv4/csf_examples/ directory. + +With current CST implementation is not possible to encrypt and sign an image +at the same time, hence two CSF files are required on each time HAB is used. + +1.6.1 csf_spl_enc.txt +---------------------- + +The first CSF is used to encrypt the SPL and DDR FW images and generate the +dek_spl.bin file. The Authenticate Data command has to cover only the image +header and two commands have to be added to encrypt the image. + +- Add the Authenticate Data command to only cover SPL IVT and boot data: + + Blocks = 0x7E0FC0 0x0 0x40 "flash.bin" + +- Add the Install Secret Key command to generate the dek_spl.bin file and + install the blob. The Blob Address depends on your image layout and can + be calculated as following: + + Key = "dek_spl.bin" + Blob Address = Authenticate Start Address + Image length + CSF Padding + = 0x7E0FC0 + 0x2c400 + 0x2000 = 0x80F3C0 + +- Add the Decrypt Data command to encrypt the file. As SPL image header + cannot be encrypted we need to calculate the Block as following: + + Start Address = Start Address + SPL header = 0x7E0FC0 + 0x40 = 0x7E1000 + Offset = Image offset (image_off) = 0x40 + Decrypt size = Image length - SPL header = 0x2C400 - 0x40 = 0x2C3C0 + + Blocks = 0x7E1000 0x40 0x2C3C0 "flash-spl-enc.bin" + +1.6.2 csf_spl_sign_enc.txt +--------------------------- + +The second CSF is used to sign the encrypted SPL image previously generated +(flash-spl-enc.bin). + +- The Authenticate Data command should cover the entire SPL and DDR FW image, + the file parameter is the encrypted image flash-spl-enc.bin: + + Blocks = 0x7E0FC0 0x0 0x2C400 "flash-spl-enc.bin" + +- Add the Install Secret Key command to generate a dummy DEK blob file, + the blob address should be the same as used in csf_spl_enc.txt: + + Key = "dek_spl_dummy.bin" + +- Add the Decrypt Data command to encrypt the file. As image was encrypted + in CSF above we need to encrypt a dummy file, the block addresses should be + the same as used in csf_spl_enc.txt: + + Blocks = 0x7E1000 0x40 0x2C3C0 "flash-spl-enc-dummy.bin" + +1.7 Encrypting and signing the SPL + DDR FW image +-------------------------------------------------- + +The CST is used to encrypt the image and regenerate a random DEK. During this +step two CSF binaries are generated but only one will be included in final +image. + +- Encrypt the SPL + DDR FW image: + + $ cp flash.bin flash-spl-enc.bin + $ ./cst_encrypted -i csf_spl_enc.txt -o csf_spl_enc.bin + +- Sign the encrypted SPL + DDR FW image: + + $ cp flash-spl-enc.bin flash-spl-enc-dummy.bin + $ ./cst_encrypted -i csf_spl_sign_enc.txt -o csf_spl_sign_enc.bin + +1.7.1 Create final CSF binary for SPL + DDR FW image +----------------------------------------------------- + +As only one CSF binary will be included in final image it's necessary to +swap Nonce/MAC from csf_spl_enc.bin to csf_spl_sign_enc.bin. + +- Calculate Nonce/MAC size based on MAC bytes value in CSF: + + Nonce/MAC size = Nonce size + MAC bytes + CSF header for Nonce/Mac + = 12 + 16 + 8 = 36 bytes + +- Calculate Nonce/MAC offset in CSF: + + MAC offset = csf_spl_enc.bin size - Nonce/MAC size + = 3980 - 36 = 3944 Bytes + +- Extract Nonce/MAC from csf_spl_enc.bin: + + $ dd if=csf_spl_enc.bin of=noncemac.bin bs=1 skip=3944 count=36 + +- Replace the MAC of csf_spl_sign_enc with the one extracted above: + + $ dd if=noncemac.bin of=csf_spl_sign_enc.bin bs=1 seek=3944 count=36 + +1.8 Creating the CSF description file for FIT image +---------------------------------------------------- + +Similar to SPL image two CSF files are required encrypt and sign the FIT +image. + +Please note that the steps below are using the flash-spl-enc.bin image created +in steps above. + +1.8.1 csf_fit_enc.txt +---------------------- + +The first CSF is used to encrypt the FIT image and generate the dek_fit.bin +file. + +- Modify the Authenticate Data command to only cover FIT image FDT header: + + Blocks = 0x401FCDC0 0x57C00 0x1020 "flash-spl-enc.bin" + +- Add the Install Secret Key command to generate the dek_fit.bin file and + install the blob. The Blob Address is a fixed address defined in imx-mkimage + project in iMX8M/soc.mak file: + + iMX8M/soc.mak: + DEK_BLOB_LOAD_ADDR = 0x40400000 + + Key = "dek_fit.bin" + Blob Address = 0x40400000 + +- Add the Decrypt Data command to encrypt the file. + + The CST can only encrypt images that are 16 bytes aligned, as u-boot-nodtb.bin + and u-boot.dtb are together 16 bytes aligned we should consider the first two + lines provided in print_fit_hab as a single block. + + imx-mkimage output: + + 0x40200000 0x5AC00 0xB0318 ──┬── Total length = 0xB0318 + 0x8628 = 0xB8940 + 0x402B0318 0x10AF18 0x8628 ──┘ + 0x920000 0x113540 0xA160 + 0xBE000000 0x11D6A0 0x48520 + + Decrypt data in csf_fit_enc.txt: + + Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \ + 0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \ + 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin" + +1.8.2 csf_fit_sign_enc.txt +--------------------------- + +The second CSF is used to sign the encrypted FIT image previously generated +(flash-spl-fit-enc.bin). + +- The Authenticate Data command should cover the entire FIT image, + the file parameter is the encrypted FIT image flash-spl-fit-enc.bin: + + Blocks = 0x401fcdc0 0x57c00 0x1020 "flash-spl-fit-enc.bin" + 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc.bin", \ + 0x920000 0x113540 0xA160 "flash-spl-fit-enc.bin", \ + 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc.bin" + + +- Add the Install Secret Key command to generate a dummy DEK blob file, + the blob address should be the same as used in csf_spl_enc.txt: + + Key = "dek_fit_dummy.bin" + +- Add the Decrypt Data command to encrypt the file. As image was encrypted + in CSF above we need to encrypt a dummy file, the block address should be + the same as used in csf_spl_enc.txt: + + Blocks = 0x40200000 0x5AC00 0xB8940 "flash-spl-fit-enc-dummy.bin", \ + 0x920000 0x113540 0xA160"flash-spl-fit-enc-dummy.bin", \ + 0xBE000000 0x11D6A0 0x48520 "flash-spl-fit-enc-dummy.bin" + +1.9 Encrypting and signing the FIT image +----------------------------------------- + +The CST is used to encrypt the image and regenerate a random DEK. During this +step two CSF binaries are generated but only one will be included in final +image. + +- Encrypt the FIT image: + + $ cp flash-spl-enc.bin flash-spl-fit-enc.bin + $ ./cst_encrypted -i csf_fit_enc.txt -o csf_fit_enc.bin + +- Sign the encrypted FIT image: + + $ cp flash-spl-fit-enc.bin flash-spl-fit-enc-dummy.bin + $ ./cst_encrypted -i csf_fit_sign_enc.txt -o csf_fit_sign_enc.bin + +1.9.1 Create final CSF binary for FIT image +----------------------------------------------------- + +As only one CSF binary will be included in final image it's necessary to swap +Nonce/MAC from csf_fit_enc.bin to csf_fit_sign_enc.bin. + +- Calculate Nonce/MAC size based on MAC bytes value in CSF: + + Nonce/MAC size = Nonce size + MAC bytes + CSF header for Nonce/Mac + = 12 + 16 + 8 = 36 bytes + +- Calculate Nonce/MAC offset in csf_fit_enc.bin: + + MAC offset = csf_fit_enc.bin size - Nonce/MAC size + = 3996 - 36 = 3960 Bytes + +- Extract Nonce/MAC from csf_fit_enc.bin: + + $ dd if=csf_fit_enc.bin of=noncemac.bin bs=1 skip=3960 count=36 + +- Calculate Nonce/MAC offset in csf_fit_sign_enc.bin: + + MAC offset = csf_fit_enc.bin size - Nonce/MAC size + = 4020 - 36 = 3984 Bytes + +- Replace the MAC of csf_fit_sign_enc.bin with the one extracted above: + + $ dd if=noncemac.bin of=csf_fit_sign_enc.bin bs=1 seek=3984 count=36 + +1.10 Generate the DEK Blob +--------------------------- + +The DEK must be encapsulated into a CAAM blob so it can be included into +the final encrypted binary. The U-Boot provides a tool called dek_blob +which is calling the CAAM implementation included in OP-TEE. + +Copy the dek_spl.bin and dek_fit.bin in SDCard FAT partition and run +the following commands from U-Boot prompt: + + => mmc list + FSL_SDHC: 1 (SD) + FSL_SDHC: 2 + => fatload mmc 1:1 0x40400000 dek_spl.bin + => dek_blob 0x40400000 0x40401000 128 + => fatwrite mmc 1:1 0x40401000 dek_spl_blob.bin 0x48 + => fatload mmc 1:1 0x40402000 dek_fit.bin + => dek_blob 0x40402000 0x40403000 128 + => fatwrite mmc 1:1 0x40403000 dek_fit_blob.bin 0x48 + +In host PC copy the generated dek_spl_blob.bin and dek_fit_blob.bin to the +CST directory. + +1.11 Assembly the encrypted image +---------------------------------- + +The CSF binaries generated in the steps above have to be inserted into the +encrypted image. + +The CSF offsets can be obtained from the flash.bin build log: + +- SPL CSF offset: + + csf_off 0x2c400 + +- FIT CSF offset: + + sld_csf_off 0x58c20 + +The encrypted flash.bin image can be then assembled: + +- Create a flash-spl-fit-enc.bin copy: + + $ cp flash-spl-fit-enc.bin encrypted-flash.bin + +1.11.1 Insert SPL CSF and DEK blob +----------------------------------- + +- Insert csf_spl_sign_enc.bin in encrypted-flash.bin at 0x2c400 offset: + + $ dd if=csf_spl_sign_enc.bin of=encrypted-flash.bin seek=$((0x2c400)) bs=1 conv=notrunc + +- Insert dek_spl_blob.bin in encrypted-flash.bin at 0x2c400 + 0x2000 offset: + + $ dd if=dek_spl_blob.bin of=encrypted-flash.bin seek=$((0x2e400)) bs=1 conv=notrunc + +1.11.2 Insert FIT CSF and DEK blob +----------------------------------- + +- Insert csf_fit_sign_enc.bin in encrypted-flash.bin at 0x58c20 offset: + + $ dd if=csf_fit_sign_enc.bin of=encrypted-flash.bin seek=$((0x58c20)) bs=1 conv=notrunc + +- The DEK blob must be inserted in last image entry on FIT image, the last line + provided by print_fit_hab taget log target can be used: + + 0x40200000 0x5AC00 0xB0318 + 0x402B0318 0x10AF18 0x8628 + 0x920000 0x113540 0xA160 + 0xBE000000 0x11D6A0 0x48520 -> Last line in print_fit_hab log + +- Insert dek_fit_blob.bin encrypted-flash.bin at 0x11D6A0 + 0x48520 offset: + + $ dd if=dek_fit_blob.bin of=encrypted-flash.bin seek=$((0x165BC0)) bs=1 conv=notrunc + +1.11.3 Flash encrypted boot image +----------------------------------- + +- Flash encrypted image in SDCard: + + $ sudo dd if=encrypted-flash.bin of=/dev/sd bs=1K seek=33* && sync + * Offset in i.MX8MN device is 32K. + +2.0 Setting the PRIBLOB in CAAM SCFGR register +----------------------------------------------- + +It is highly recommended to advance the PRIBLOB field in CAAM SCFGR register to +0x3, a command is available in U-Boot that should be called after all images in +boot flow has been decrypted by HAB: + + => set_priblob_bitfield + +The PRIBLOB configuration ensures cryptographic separation of private blob +types avoiding any modification or replacement of DEK blobs. Newly created +blobs will be incompatible with blobs required to decrypt an encrypted boot +image. When the HAB later executes the command to decrypt the DEK, an +incompatible DEK blob will be detected and cause an error. A substitute +encrypted boot image will not be decrypted, and will not be executed. + +References: +[1] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices" diff --git a/doc/imx/habv4/guides/mx8m_secure_boot.txt b/doc/imx/habv4/guides/mx8m_secure_boot.txt new file mode 100644 index 00000000000..4835d006756 --- /dev/null +++ b/doc/imx/habv4/guides/mx8m_secure_boot.txt @@ -0,0 +1,524 @@ + +=====================================================+ + + i.MX8M family Secure Boot guide using HABv4 + + +=====================================================+ + +1. HABv4 secure boot process +----------------------------- + +This document describes a step-by-step procedure on how to sign and securely +boot a bootloader image on i.MX8M family devices. It is assumed that the reader +is familiar with basic HAB concepts and with the PKI tree generation. + +Details about HAB can be found in the application note AN4581[1] and in the +introduction_habv4.txt document. + +1.1 Understanding the i.MX8M family flash.bin image layout +---------------------------------------------------------- + +Due to the new the architecture, multiple firmwares and softwares are required +to boot i.MX8M family devices. In order to store all the images in a single +binary the FIT (Flattened Image Tree) image structure is used. + +The final image is generated by the imx-mkimage project, the tool combines all +the input images in a FIT structure, generating a flash.bin image with an +appropriate IVT set. + +For a secure boot process users should ensure all images included in flash.bin +file are covered by a digital signature. + +- The diagram below illustrate a signed flash.bin image layout: + + +-----------------------------+ + | | + | *Signed HDMI/DP FW | + | | + +-----------------------------+ + | Padding | + ------- +-----------------------------+ -------- + ^ | IVT - SPL | ^ + Signed | +-----------------------------+ | + Data | | u-boot-spl.bin | | + | | + | | SPL + v | DDR FW | | Image + ------- +-----------------------------+ | + | CSF - SPL + DDR FW | v + +-----------------------------+ -------- + | Padding | + ------- +-----------------------------+ -------- + Signed ^ | FDT - FIT | ^ + Data | +-----------------------------+ | + v | IVT - FIT | | + ------- +-----------------------------+ | + | CSF - FIT | | + ------- +-----------------------------+ | FIT + ^ | u-boot-nodtb.bin | | Image + | +-----------------------------+ | + Signed | | OP-TEE (Optional) | | + Data | +-----------------------------+ | + | | bl31.bin (ATF) | | + | +-----------------------------+ | + v | u-boot.dtb | v + ------- +-----------------------------+ -------- + * Only supported on i.MX8M series + +The boot flow on i.MX8M devices are slightly different when compared with i.MX6 +and i.MX7 series, the diagram below illustrate the boot sequence overview: + +- i.MX8M boot flow: + + Secure World Non-Secure World + | + | + +------------+ +------------+ | + | SPL | | i.MX 8M | | + | + | ---> | ROM | | + | DDR FW | | + HAB | | + +------------+ +------------+ | + | | + v | + +------------+ | + | *Signed | | + | HDMI/DP FW | | + +------------+ | + | | + v | + +------------+ +------------+ | + | FIT Image: | | SPL | | + | ATF + TEE | ---> | + | | + | + U-Boot | | DDR FW | | +-----------+ + +------------+ +------------+ | | Linux | + | | +-----------+ + v | ^ + +------------+ | | +-------+ + | ARM | | +-----------+ | Linux | + | Trusted | ----+---> | U-Boot | <--- | + | + | Firmware | | +-----------+ | DTB | + +------------+ | +-------+ + | | + v | + +----------+ | + | **OP-TEE | | + +----------+ | + * Only supported on i.MX8M series + ** Optional + +Particularly on the i.MX8M, the HDMI firmware or DisplayPort firmware are the +first image to boot on the device. These firmwares are signed and distributed by +NXP, and are always authenticated regardless of security configuration. In case +not required by the application the HDMI or DisplayPort controllers can be +disabled by eFuses and the firmwares are not required anymore. + +The next images are not signed by NXP and users should follow the signing +procedure as described in this document. + +The Second Program Loader (SPL) and DDR firmware are loaded and authenticated +by the ROM code, these images are executed in the internal RAM and responsible +for initializing essential features such as DDR, UART, PMIC and clock +enablement. + +Once the DDR is available, the SPL code loads all the images included in the +FIT structure to their specific execution addresses, the HAB APIs are called +to extend the root of trust, authenticating the U-Boot, ARM trusted firmware +(ATF) and OP-TEE (If included). + +The root of trust can be extended again at U-Boot level to authenticate Kernel +and M4 images. + +1.2 Enabling the secure boot support in U-Boot +----------------------------------------------- + +The first step is to generate an U-Boot image supporting the HAB features, +similar to i.MX6 and i.MX7 series the U-Boot provides extra functions for +HAB, such as the HAB status logs retrievement through the hab_status command +and support to extend the root of trust. + +The support is enabled by adding the CONFIG_IMX_HAB to the build +configuration: + +- Defconfig: + + CONFIG_IMX_HAB=y + +- Kconfig: + + ARM architecture -> Support i.MX HAB features + +1.3 Preparing the fit image +---------------------------- + +The imx-mkimage project is used to combines all the images in a single +flash.bin binary, the following files are required: + +- U-Boot: + u-boot-nodtb.bin + u-boot-spl.bin + U-Boot DTB file (e.g. fsl-imx8mq-evk.dtb) + +- ATF image: + bl31.bin + +- DDR firmware: + lpddr4_pmu_train_1d_dmem.bin + lpddr4_pmu_train_1d_imem.bin + lpddr4_pmu_train_2d_dmem.bin + lpddr4_pmu_train_2d_imem.bin + +- HDMI firmware (Only in i.MX8M): + signed_hdmi_imx8m.bin + +- DisplayPort firmware (Only in i.MX8M): + signed_dp_imx8m.bin + +- OP-TEE (Optional): + tee.bin + +The procedure to build ATF and download the firmwares are out of the scope +of this document, please refer to the Linux BSP Release Notes and AN12212[2] +for further details. + +Copy all files to iMX8M directory and run the following command according to +the target device, on this example we are building a HDMI target and also +including the OP-TEE binary: + +- Assembly flash.bin binary: + + $ make SOC= flash_hdmi_spl_uboot + +The mkimage log can be used to calculate the authenticate image command +parameters and CSF offsets: + +- imx-mkimage build log: + + Loader IMAGE: + header_image_off 0x1a000 + dcd_off 0x0 + image_off 0x1a040 + csf_off 0x44600 + spl hab block: 0x7e0fd0 0x1a000 0x2e600 + + Second Loader IMAGE: + sld_header_off 0x57c00 + sld_csf_off 0x58c20 + sld hab block: 0x401fcdc0 0x57c00 0x1020 + +Additional HAB information is provided by running the following command: + +- Printing HAB FIT information: + + $ make SOC= print_fit_hab + + TEE_LOAD_ADDR=0xfe000000 ATF_LOAD_ADDR=0x00910000 ./print_fit_hab.sh \ + 0x60000 fsl-imx8mq-evk.dtb + 0x40200000 0x5AC00 0x9AAC8 + 0x910000 0xF56C8 0x9139 + 0xFE000000 0xFE804 0x4D268 + 0x4029AAC8 0x14BA6C 0x6DCF + +1.4 Creating the CSF description file +-------------------------------------- + +The CSF contains all the commands that the ROM executes during the secure +boot. These commands instruct the HAB code on which memory areas of the image +to authenticate, which keys to install, use and etc. + +CSF examples are available under doc/imx/hab/habv4/csf_examples/ directory. + +As explained in sections above the SPL is first authenticated by the ROM code +and the root of trust is extended to the FIT image, hence two CSF files are +necessary to completely sign an flash.bin image. + +The build log provided by imx-mkimage can be used to define the "Authenticate +Data" parameter in CSF. + +- SPL "Authenticate Data" addresses in flash.bin build log: + + spl hab block: 0x7e0fd0 0x1a000 0x2e600 + +- "Authenticate Data" command in csf_spl.txt file: + + Blocks = 0x7e0fd0 0x1a000 0x2e600 "flash.bin" + +- FIT image "Authenticate Data" addresses in flash.bin build log: + + sld hab block: 0x401fcdc0 0x57c00 0x1020 + +- FIT image "Authenticate Data" addresses in print_fit_hab build log: + + 0x40200000 0x5AC00 0x9AAC8 + 0x910000 0xF56C8 0x9139 + 0xFE000000 0xFE804 0x4D268 + 0x4029AAC8 0x14BA6C 0x6DCF + +- "Authenticate Data" command in csf_fit.txt file: + + Blocks = 0x401fcdc0 0x057c00 0x01020 "flash.bin", \ + 0x40200000 0x05AC00 0x9AAC8 "flash.bin", \ + 0x00910000 0x0F56C8 0x09139 "flash.bin", \ + 0xFE000000 0x0FE804 0x4D268 "flash.bin", \ + 0x4029AAC8 0x14BA6C 0x06DCF "flash.bin" + +1.4.1 Avoiding Kernel crash in closed devices +---------------------------------------------- + +For devices prior to HAB v4.4.0, the HAB code locks the Job Ring and DECO +master ID registers in closed configuration. In case the user specific +application requires any changes in CAAM MID registers it's necessary to +add the "Unlock CAAM MID" command in CSF file. + +The current NXP BSP implementation expects the CAAM registers to be unlocked +when configuring CAAM to operate in non-secure TrustZone world. + +The Unlock command is already included by default in the signed HDMI and +DisplayPort firmwares. On i.MX8MM, i.MX8MN and i.MX8MP devices or in case the +HDMI or DisplayPort controllers are disabled in i.MX8M, users must ensure this +command is included in SPL CSF. + +- Add Unlock MID command in csf_spl.txt: + + [Unlock] + Engine = CAAM + Features = MID + +1.5 Signing the flash.bin binary +--------------------------------- + +The CST tool is used for singing the flash.bin image and generating the CSF +binary. Users should input the CSF description file created in the step above +and receive a CSF binary, which contains the CSF commands, SRK table, +signatures and certificates. + +- Create SPL CSF binary file: + + $ ./cst -i csf_spl.txt -o csf_spl.bin + +- Create FIT CSF binary file: + + $ ./cst -i csf_fit.txt -o csf_fit.bin + +1.6 Assembling the CSF in flash.bin binary +------------------------------------------- + +The CSF binaries generated in the step above have to be inserted into the +flash.bin image. + +The CSF offsets can be obtained from the flash.bin build log: + +- SPL CSF offset: + + csf_off 0x44600 + +- FIT CSF offset: + + sld_csf_off 0x58c20 + +The signed flash.bin image can be then assembled: + +- Create a flash.bin copy: + + $ cp flash.bin signed_flash.bin + +- Insert csf_spl.bin in signed_flash.bin at 0x44600 offset: + + $ dd if=csf_spl.bin of=signed_flash.bin seek=$((0x44600)) bs=1 conv=notrunc + +- Insert csf_fit.bin in signed_flash.bin at 0x58c20 offset: + + $ dd if=csf_fit.bin of=signed_flash.bin seek=$((0x58c20)) bs=1 conv=notrunc + +- Flash signed flash.bin image: + + $ sudo dd if=signed_flash.bin of=/dev/sd bs=1K seek=33 && sync + +1.7 Programming SRK Hash +------------------------- + +As explained in AN4581[1] and in introduction_habv4.txt document the SRK Hash +fuse values are generated by the srktool and should be programmed in the +SoC SRK_HASH[255:0] fuses. + +Be careful when programming these values, as this data is the basis for the +root of trust. An error in SRK Hash results in a part that does not boot. + +The U-Boot fuse tool can be used for programming eFuses on i.MX SoCs. + +- Dump SRK Hash fuses values in host machine: + + $ hexdump -e '/4 "0x"' -e '/4 "%X""\n"' SRK_1_2_3_4_fuse.bin + 0x20593752 + 0x6ACE6962 + 0x26E0D06C + 0xFC600661 + 0x1240E88F + 0x1209F144 + 0x831C8117 + 0x1190FD4D + +- Program SRK_HASH[255:0] fuses on i.MX8M family devices: + + => fuse prog 6 0 0x20593752 + => fuse prog 6 1 0x6ACE6962 + => fuse prog 6 2 0x26E0D06C + => fuse prog 6 3 0xFC600661 + => fuse prog 7 0 0x1240E88F + => fuse prog 7 1 0x1209F144 + => fuse prog 7 2 0x831C8117 + => fuse prog 7 3 0x1190FD4D + + +1.8 Verifying HAB events +------------------------- + +The next step is to verify that the signatures included in flash.bin image is +successfully processed without errors. HAB generates events when processing +the commands if it encounters issues. + +The hab_status U-Boot command call the hab_report_event() and hab_status() +HAB API functions to verify the processor security configuration and status. +This command displays any events that were generated during the process. + +Prior to closing the device users should ensure no HAB events were found, as +the example below: + +- Verify HAB events: + + => hab_status + + Secure boot disabled + + HAB Configuration: 0xf0, HAB State: 0x66 + +1.9 Closing the device +----------------------- + +After the device successfully boots a signed image without generating any HAB +events, it is safe to close the device. This is the last step in the HAB +process, and is achieved by programming the SEC_CONFIG[1] fuse bit. + +Once the fuse is programmed, the chip does not load an image that has not been +signed using the correct PKI tree. + +- Program SEC_CONFIG[1] fuse on i.MX8M family devices: + + => fuse prog 1 3 0x2000000 + +1.10 Completely secure the device +---------------------------------- + +Additional fuses can be programmed for completely secure the device, more +details about these fuses and their possible impact can be found at AN4581[1]. + +2. Secure boot in SDP mode +--------------------------- + +For secure boot in SDP mode, please refer to the "HABv4 closed chip support" +chapter in the UUU documentation[3]. + +3. Authenticating additional boot images +----------------------------------------- + +The High Assurance Boot (HAB) code located in the on-chip ROM provides an +Application Programming Interface (API) making it possible to call back +into the HAB code for authenticating additional boot images. + +The U-Boot is running in non-secure TrustZone world and to make use of this +feature it's necessary to use a SIP call to the ATF, this is already +implemented in hab.c code and it's transparent to the user. + +The process of signing an additional image is similar as in i.MX6 and i.MX7 +series devices, the steps below are using the Linux Kernel image as example. + +The diagram below illustrate the Image layout: + + ------- +-----------------------------+ <-- *load_address + ^ | | + | | | + | | | + | | | + | | Image | + Signed | | | + Data | | | + | | | + | +-----------------------------+ + | | Padding to Image size | + | | in header | + | +-----------------------------+ <-- *ivt + v | Image Vector Table | + ------- +-----------------------------+ <-- *csf + | | + | Command Sequence File (CSF) | + | | + +-----------------------------+ + | Padding (optional) | + +-----------------------------+ + +3.1 Padding the image +---------------------- + +The Image must be padded to the size specified in the Image header, this can be +achieved by using the od command. + +- Read Image size: + + $ od -x -j 0x10 -N 0x4 --endian=little Image + 0000020 5000 0145 + 0000024 + +The tool objcopy can be used for padding the image. + +- Pad the Image: + + $ objcopy -I binary -O binary --pad-to 0x1455000 --gap-fill=0x00 \ + Image Image_pad.bin + +3.2 Generating Image Vector Table +---------------------------------- + +The HAB code requires an Image Vector Table (IVT) for determining the image +length and the CSF location. Since Image does not include an IVT this has +to be manually created and appended to the end of the padded Image, the +script genIVT.pl in script_examples directory can be used as reference. + +- Generate IVT: + + $ genIVT.pl + +Note: The load Address may change depending on the device. + +- Append the ivt.bin at the end of the padded Image: + + $ cat Image_pad.bin ivt.bin > Image_pad_ivt.bin + +3.3 Signing the image +---------------------- + +A CSF file has to be created to sign the image. HAB does not allow to change +the SRK once the first image is authenticated, so the same SRK key used in +the initial image must be used when extending the root of trust. + +CSF examples are available in ../csf_examples/additional_images/ directory. + +- Create CSF binary file: + + $ ./cst --i csf_additional_images.txt --o csf_Image.bin + +- Attach the CSF binary to the end of the image: + + $ cat Image_pad_ivt.bin csf_Image.bin > Image_signed.bin + +3.4 Verifying HAB events +------------------------- + +The U-Boot includes the hab_auth_img command which can be used for +authenticating and troubleshooting the signed image, the Image must be +loaded at the load address specified in the IVT. + +- Authenticate additional image: + + => hab_auth_img + +If no HAB events were found the Image is successfully signed. + +References: +[1] AN4581: "i.MX Secure Boot on HABv4 Supported Devices" +[2] AN12212: "Software Solutions for Migration Guide from Aarch32 to Aarch64" +[3] https://github.com/NXPmicro/mfgtools/releases/ diff --git a/doc/imx/habv4/introduction_habv4.txt b/doc/imx/habv4/introduction_habv4.txt index 25711bbe95a..9d934d19bd5 100644 --- a/doc/imx/habv4/introduction_habv4.txt +++ b/doc/imx/habv4/introduction_habv4.txt @@ -12,7 +12,7 @@ to authenticate and/or decrypt the program image by using cryptography operations. This feature is supported in i.MX 50, i.MX 53, i.MX 6, i.MX 7 series and - i.MX 8M, i.MX 8MM devices. +i.MX 8M family (i.MX 8M, i.MX 8MM, i.MX 8MN, i.MX 8MP devices). Step-by-step guides are available under doc/imx/habv4/guides/ directory, users familiar with HAB and CST PKI tree generation should refer to these @@ -153,7 +153,7 @@ IMG and CSF keys. A new PKI tree can be generated by following the example below: -- Generating 2048-bit PKI tree on CST v3.1.0: +- Generating 2048-bit PKI tree on CST (starting from v3.1.0): $ ./hab4_pki_tree.sh ... @@ -199,7 +199,8 @@ The script hab4_pki_tree.sh is also able to generate a Public Key Infrastructure (PKI) tree which only contains SRK Keys, users should not set the CA flag when generating the SRK certificates. -- Generating 2048-bit fast authentication PKI tree on CST v3.1.0: +- Generating 2048-bit fast authentication PKI tree on CST (starting from +v3.1.0): $ ./hab4_pki_tree.sh ... @@ -257,6 +258,5 @@ directory. References: [1] CST: i.MX High Assurance Boot Reference Code Signing Tool. -[2] AN4581: "Secure Boot on i.MX 50, i.MX 53, i.MX 6 and i.MX 7 Series using - HABv4" - Rev 2. -[3] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices" - Rev. 1 +[2] AN4581: "i.MX Secure Boot on HABv4 Supported Devices" +[3] AN12056: "Encrypted Boot on HABv4 and CAAM Enabled Devices" diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index f2f8275aeca..16cc0ef30b5 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -59,6 +59,15 @@ config DWC_AHCI Enable this driver to support Sata devices through Synopsys DWC AHCI module. +config IMX_AHCI + bool "Enable IMX AHCI driver support" + select SCSI_AHCI + depends on AHCI + depends on DM_SCSI + help + Enable this driver to support Sata devices through + i.MX AHCI module. + config DWC_AHSATA bool "Enable DWC AHSATA driver support" select LIBATA diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 98fb4807008..f06d8ec3036 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_LIBATA) += libata.o obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o obj-$(CONFIG_SATA) += sata.o obj-$(CONFIG_SATA_CEVA) += sata_ceva.o +obj-$(CONFIG_IMX_AHCI) += imx_ahci.o obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o obj-$(CONFIG_SATA_SIL) += sata_sil.o diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index 2ef21ec508a..ba0ab0f6f20 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -644,8 +644,8 @@ static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis, debug("Enter %s: for port %d\n", __func__, port); - if (port > uc_priv->n_ports) { - printf("Invalid port number %d\n", port); + if (port >= uc_priv->n_ports) { + debug("Invalid port number %d\n", port); return -1; } diff --git a/drivers/ata/imx_ahci.c b/drivers/ata/imx_ahci.c new file mode 100644 index 00000000000..9d9da96e850 --- /dev/null +++ b/drivers/ata/imx_ahci.c @@ -0,0 +1,857 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#if CONFIG_IS_ENABLED(CLK) +#include +#else +#include +#include +#endif +#include +#include +#include +#include +#include + +enum { + /* Timer 1-ms Register */ + IMX_TIMER1MS = 0x00e0, + /* Port0 PHY Control Register */ + IMX_P0PHYCR = 0x0178, + IMX_P0PHYCR_TEST_PDDQ = 1 << 20, + IMX_P0PHYCR_CR_READ = 1 << 19, + IMX_P0PHYCR_CR_WRITE = 1 << 18, + IMX_P0PHYCR_CR_CAP_DATA = 1 << 17, + IMX_P0PHYCR_CR_CAP_ADDR = 1 << 16, + /* Port0 PHY Status Register */ + IMX_P0PHYSR = 0x017c, + IMX_P0PHYSR_CR_ACK = 1 << 18, + IMX_P0PHYSR_CR_DATA_OUT = 0xffff << 0, + /* Lane0 Output Status Register */ + IMX_LANE0_OUT_STAT = 0x2003, + IMX_LANE0_OUT_STAT_RX_PLL_STATE = 1 << 1, + /* Clock Reset Register */ + IMX_CLOCK_RESET = 0x7f3f, + IMX_CLOCK_RESET_RESET = 1 << 0, + /* IMX8QM HSIO AHCI definitions */ + IMX8QM_SATA_PHY_REG03_RX_IMPED_RATIO = 0x03, + IMX8QM_SATA_PHY_REG09_TX_IMPED_RATIO = 0x09, + IMX8QM_SATA_PHY_REG10_TX_POST_CURSOR_RATIO = 0x0a, + IMX8QM_SATA_PHY_GEN1_TX_POST_CURSOR_RATIO = 0x15, + IMX8QM_SATA_PHY_IMPED_RATIO_85OHM = 0x6c, + IMX8QM_SATA_PHY_REG22_TX_POST_CURSOR_RATIO = 0x16, + IMX8QM_SATA_PHY_GEN2_TX_POST_CURSOR_RATIO = 0x00, + IMX8QM_SATA_PHY_REG24_TX_AMP_RATIO_MARGIN0 = 0x18, + IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN0 = 0x64, + IMX8QM_SATA_PHY_REG25_TX_AMP_RATIO_MARGIN1 = 0x19, + IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN1 = 0x70, + IMX8QM_SATA_PHY_REG26_TX_AMP_RATIO_MARGIN2 = 0x1a, + IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN2 = 0x69, + IMX8QM_SATA_PHY_REG48_PMA_STATUS = 0x30, + IMX8QM_SATA_PHY_REG48_PMA_RDY = BIT(7), + IMX8QM_SATA_PHY_REG128_UPDATE_SETTING = 0x80, + IMX8QM_SATA_PHY_UPDATE_SETTING = 0x01, + IMX8QM_LPCG_PHYX2_OFFSET = 0x00000, + IMX8QM_CSR_PHYX2_OFFSET = 0x90000, + IMX8QM_CSR_PHYX1_OFFSET = 0xa0000, + IMX8QM_CSR_PHYX_STTS0_OFFSET = 0x4, + IMX8QM_CSR_PCIEA_OFFSET = 0xb0000, + IMX8QM_CSR_PCIEB_OFFSET = 0xc0000, + IMX8QM_CSR_SATA_OFFSET = 0xd0000, + IMX8QM_CSR_PCIE_CTRL2_OFFSET = 0x8, + IMX8QM_CSR_MISC_OFFSET = 0xe0000, + /* IMX8QM SATA specific control registers */ + IMX8QM_SATA_PPCFG_OFFSET = 0xa8, + IMX8QM_SATA_PPCFG_FORCE_PHY_RDY = BIT(20), + IMX8QM_SATA_PPCFG_BIST_PATTERN_MASK = 0x7 << 21, + IMX8QM_SATA_PPCFG_BIST_PATTERN_OFFSET = 21, + IMX8QM_SATA_PPCFG_BIST_PATTERN_EN = BIT(24), + IMX8QM_SATA_PPCFG_BIST_PATTERN_NOALIGNS = BIT(26), + IMX8QM_SATA_PP2CFG_OFFSET = 0xac, + IMX8QM_SATA_PP2CFG_COMINIT_NEGATE_MIN = 0x28 << 24, + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP = 0x18 << 16, + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MAX = 0x2b << 8, + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MIN = 0x1b << 0, + IMX8QM_SATA_PP3CFG_OFFSET = 0xb0, + IMX8QM_SATA_PP3CFG_COMWAKE_NEGATE_MIN = 0x0e << 24, + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP = 0x08 << 16, + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MAX = 0x0f << 8, + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MIN = 0x01 << 0, + + IMX8QM_LPCG_PHYX2_PCLK0_MASK = (0x3 << 16), + IMX8QM_LPCG_PHYX2_PCLK1_MASK = (0x3 << 20), + IMX8QM_PHY_APB_RSTN_0 = BIT(0), + IMX8QM_PHY_MODE_SATA = BIT(19), + IMX8QM_PHY_MODE_MASK = (0xf << 17), + IMX8QM_PHY_PIPE_RSTN_0 = BIT(24), + IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0 = BIT(25), + IMX8QM_PHY_PIPE_RSTN_1 = BIT(26), + IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1 = BIT(27), + IMX8QM_STTS0_LANE0_TX_PLL_LOCK = BIT(4), + IMX8QM_MISC_IOB_RXENA = BIT(0), + IMX8QM_MISC_IOB_TXENA = BIT(1), + IMX8QM_MISC_PHYX1_EPCS_SEL = BIT(12), + IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 = BIT(24), + IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 = BIT(25), + IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 = BIT(28), + IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0 = BIT(29), + IMX8QM_SATA_CTRL_RESET_N = BIT(12), + IMX8QM_SATA_CTRL_EPCS_PHYRESET_N = BIT(7), + IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL = BIT(6), + IMX8QM_SATA_CTRL_EPCS_TXDEEMP = BIT(5), + IMX8QM_CTRL_BUTTON_RST_N = BIT(21), + IMX8QM_CTRL_POWER_UP_RST_N = BIT(23), + IMX8QM_CTRL_LTSSM_ENABLE = BIT(4), +}; + +enum ahci_imx_type { + AHCI_IMX6Q, + AHCI_IMX6QP, + AHCI_IMX8QM, +}; + +struct imx_ahci_priv { +#if CONFIG_IS_ENABLED(CLK) + struct clk sata_clk; + struct clk sata_ref_clk; + struct clk ahb_clk; + struct clk epcs_tx_clk; + struct clk epcs_rx_clk; + struct clk phy_apbclk; + struct clk phy_pclk0; + struct clk phy_pclk1; +#endif + enum ahci_imx_type type; + void __iomem *phy_base; + void __iomem *mmio; + struct regmap *gpr; + struct gpio_desc clkreq_gpio; + u32 phy_params; + u32 imped_ratio; + u32 ext_osc; +}; + +static int imx_phy_crbit_assert(void __iomem *mmio, u32 bit, bool assert) +{ + int timeout = 10; + u32 crval; + u32 srval; + + /* Assert or deassert the bit */ + crval = readl(mmio + IMX_P0PHYCR); + if (assert) + crval |= bit; + else + crval &= ~bit; + writel(crval, mmio + IMX_P0PHYCR); + + /* Wait for the cr_ack signal */ + do { + srval = readl(mmio + IMX_P0PHYSR); + if ((assert ? srval : ~srval) & IMX_P0PHYSR_CR_ACK) + break; + udelay(100); + } while (--timeout); + + return timeout ? 0 : -ETIMEDOUT; +} + +static int imx_phy_reg_addressing(u16 addr, void __iomem *mmio) +{ + u32 crval = addr; + int ret; + + /* Supply the address on cr_data_in */ + writel(crval, mmio + IMX_P0PHYCR); + + /* Assert the cr_cap_addr signal */ + ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, true); + if (ret) + return ret; + + /* Deassert cr_cap_addr */ + ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_ADDR, false); + if (ret) + return ret; + + return 0; +} + +static int imx_phy_reg_write(u16 val, void __iomem *mmio) +{ + u32 crval = val; + int ret; + + /* Supply the data on cr_data_in */ + writel(crval, mmio + IMX_P0PHYCR); + + /* Assert the cr_cap_data signal */ + ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, true); + if (ret) + return ret; + + /* Deassert cr_cap_data */ + ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_CAP_DATA, false); + if (ret) + return ret; + + if (val & IMX_CLOCK_RESET_RESET) { + /* + * In case we're resetting the phy, it's unable to acknowledge, + * so we return immediately here. + */ + crval |= IMX_P0PHYCR_CR_WRITE; + writel(crval, mmio + IMX_P0PHYCR); + goto out; + } + + /* Assert the cr_write signal */ + ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, true); + if (ret) + return ret; + + /* Deassert cr_write */ + ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_WRITE, false); + if (ret) + return ret; + +out: + return 0; +} + +static int imx_phy_reg_read(u16 *val, void __iomem *mmio) +{ + int ret; + + /* Assert the cr_read signal */ + ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, true); + if (ret) + return ret; + + /* Capture the data from cr_data_out[] */ + *val = readl(mmio + IMX_P0PHYSR) & IMX_P0PHYSR_CR_DATA_OUT; + + /* Deassert cr_read */ + ret = imx_phy_crbit_assert(mmio, IMX_P0PHYCR_CR_READ, false); + if (ret) + return ret; + + return 0; +} + +static int imx_sata_phy_reset(struct imx_ahci_priv *priv) +{ + void __iomem *mmio = priv->mmio; + int timeout = 10; + u16 val; + int ret; + + /* Reset SATA PHY by setting RESET bit of PHY register CLOCK_RESET */ + ret = imx_phy_reg_addressing(IMX_CLOCK_RESET, mmio); + if (ret) + return ret; + ret = imx_phy_reg_write(IMX_CLOCK_RESET_RESET, mmio); + if (ret) + return ret; + + /* Wait for PHY RX_PLL to be stable */ + do { + udelay(100); + ret = imx_phy_reg_addressing(IMX_LANE0_OUT_STAT, mmio); + if (ret) + return ret; + ret = imx_phy_reg_read(&val, mmio); + if (ret) + return ret; + if (val & IMX_LANE0_OUT_STAT_RX_PLL_STATE) + break; + } while (--timeout); + + return timeout ? 0 : -ETIMEDOUT; +} + +static int imx8_sata_enable(struct udevice *dev) +{ + u32 val, reg; + int i, ret; + struct imx_ahci_priv *imxpriv = dev_get_priv(dev); + +#if CONFIG_IS_ENABLED(CLK) + /* configure the hsio for sata */ + ret = clk_enable(&imxpriv->phy_pclk0); + if (ret < 0) { + dev_err(dev, "can't enable phy pclk0.\n"); + return ret; + } + ret = clk_enable(&imxpriv->phy_pclk1); + if (ret < 0) { + dev_err(dev, "can't enable phy pclk1.\n"); + goto disable_phy_pclk0; + } + ret = clk_enable(&imxpriv->epcs_tx_clk); + if (ret < 0) { + dev_err(dev, "can't enable epcs tx clk.\n"); + goto disable_phy_pclk1; + } + ret = clk_enable(&imxpriv->epcs_rx_clk); + if (ret < 0) { + dev_err(dev, "can't enable epcs rx clk.\n"); + goto disable_epcs_tx_clk; + } + ret = clk_enable(&imxpriv->phy_apbclk); + if (ret < 0) { + dev_err(dev, "can't enable phy pclk1.\n"); + goto disable_epcs_rx_clk; + } +#endif + + /* Configure PHYx2 PIPE_RSTN */ + regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEA_OFFSET + + IMX8QM_CSR_PCIE_CTRL2_OFFSET, &val); + if ((val & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { + /* PCIEA of HSIO is down too */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_PHYX2_OFFSET, + IMX8QM_PHY_PIPE_RSTN_0 + | IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0, + IMX8QM_PHY_PIPE_RSTN_0 + | IMX8QM_PHY_PIPE_RSTN_OVERRIDE_0); + } + regmap_read(imxpriv->gpr, IMX8QM_CSR_PCIEB_OFFSET + + IMX8QM_CSR_PCIE_CTRL2_OFFSET, ®); + if ((reg & IMX8QM_CTRL_LTSSM_ENABLE) == 0) { + /* PCIEB of HSIO is down */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_PHYX2_OFFSET, + IMX8QM_PHY_PIPE_RSTN_1 + | IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1, + IMX8QM_PHY_PIPE_RSTN_1 + | IMX8QM_PHY_PIPE_RSTN_OVERRIDE_1); + } + + /* set PWR_RST and BT_RST of csr_pciea */ + val = IMX8QM_CSR_PCIEA_OFFSET + IMX8QM_CSR_PCIE_CTRL2_OFFSET; + regmap_update_bits(imxpriv->gpr, + val, + IMX8QM_CTRL_BUTTON_RST_N, + IMX8QM_CTRL_BUTTON_RST_N); + regmap_update_bits(imxpriv->gpr, + val, + IMX8QM_CTRL_POWER_UP_RST_N, + IMX8QM_CTRL_POWER_UP_RST_N); + + /* PHYX1_MODE to SATA */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_PHYX1_OFFSET, + IMX8QM_PHY_MODE_MASK, + IMX8QM_PHY_MODE_SATA); + + if (imxpriv->ext_osc) { + dev_info(dev, "external osc is used.\n"); + /* + * bit0 rx ena 1, bit1 tx ena 0 + * bit12 PHY_X1_EPCS_SEL 1. + */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + IMX8QM_MISC_IOB_RXENA); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + 0); + } else { + dev_info(dev, "internal pll is used.\n"); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + 0); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + IMX8QM_MISC_IOB_TXENA); + + } + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PHYX1_EPCS_SEL, + IMX8QM_MISC_PHYX1_EPCS_SEL); + /* + * It is possible, for PCIe and SATA are sharing + * the same clock source, HPLL or external oscillator. + * When PCIe is in low power modes (L1.X or L2 etc), + * the clock source can be turned off. In this case, + * if this clock source is required to be toggling by + * SATA, then SATA functions will be abnormal. + */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 + | IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 + | IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 + | IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0, + IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_1 + | IMX8QM_MISC_CLKREQN_OUT_OVERRIDE_0 + | IMX8QM_MISC_CLKREQN_IN_OVERRIDE_1 + | IMX8QM_MISC_CLKREQN_IN_OVERRIDE_0); + + /* clear PHY RST, then set it */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_SATA_OFFSET, + IMX8QM_SATA_CTRL_EPCS_PHYRESET_N, + 0); + + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_SATA_OFFSET, + IMX8QM_SATA_CTRL_EPCS_PHYRESET_N, + IMX8QM_SATA_CTRL_EPCS_PHYRESET_N); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_SATA_OFFSET, + IMX8QM_SATA_CTRL_EPCS_TXDEEMP, + IMX8QM_SATA_CTRL_EPCS_TXDEEMP); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_SATA_OFFSET, + IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL, + IMX8QM_SATA_CTRL_EPCS_TXDEEMP_SEL); + + /* CTRL RST: SET -> delay 1 us -> CLEAR -> SET */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_SATA_OFFSET, + IMX8QM_SATA_CTRL_RESET_N, + IMX8QM_SATA_CTRL_RESET_N); + udelay(1); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_SATA_OFFSET, + IMX8QM_SATA_CTRL_RESET_N, + 0); + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_SATA_OFFSET, + IMX8QM_SATA_CTRL_RESET_N, + IMX8QM_SATA_CTRL_RESET_N); + + /* APB reset */ + regmap_update_bits(imxpriv->gpr, + IMX8QM_CSR_PHYX1_OFFSET, + IMX8QM_PHY_APB_RSTN_0, + IMX8QM_PHY_APB_RSTN_0); + + for (i = 0; i < 100; i++) { + reg = IMX8QM_CSR_PHYX1_OFFSET + + IMX8QM_CSR_PHYX_STTS0_OFFSET; + regmap_read(imxpriv->gpr, reg, &val); + val &= IMX8QM_STTS0_LANE0_TX_PLL_LOCK; + if (val == IMX8QM_STTS0_LANE0_TX_PLL_LOCK) + break; + udelay(1); + } + + if (val != IMX8QM_STTS0_LANE0_TX_PLL_LOCK) { + dev_err(dev, "TX PLL of the PHY is not locked\n"); + ret = -ENODEV; + } else { + for (i = 0; i < 1000; i++) { + reg = readb(imxpriv->phy_base + + IMX8QM_SATA_PHY_REG48_PMA_STATUS); + if (reg & IMX8QM_SATA_PHY_REG48_PMA_RDY) + break; + udelay(10); + } + if ((reg & IMX8QM_SATA_PHY_REG48_PMA_RDY) == 0) { + dev_err(dev, "Calibration is NOT finished.\n"); + ret = -ENODEV; + goto err_out; + } + + writeb(imxpriv->imped_ratio, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG03_RX_IMPED_RATIO); + writeb(imxpriv->imped_ratio, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG09_TX_IMPED_RATIO); + reg = readb(imxpriv->phy_base + + IMX8QM_SATA_PHY_REG03_RX_IMPED_RATIO); + if (unlikely(reg != imxpriv->imped_ratio)) + dev_info(dev, "Can't set PHY RX impedance ratio.\n"); + reg = readb(imxpriv->phy_base + + IMX8QM_SATA_PHY_REG09_TX_IMPED_RATIO); + if (unlikely(reg != imxpriv->imped_ratio)) + dev_info(dev, "Can't set PHY TX impedance ratio.\n"); + + /* Configure the tx_amplitude to pass the tests. */ + writeb(IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN0, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG24_TX_AMP_RATIO_MARGIN0); + writeb(IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN1, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG25_TX_AMP_RATIO_MARGIN1); + writeb(IMX8QM_SATA_PHY_TX_AMP_RATIO_MARGIN2, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG26_TX_AMP_RATIO_MARGIN2); + + /* Adjust the OOB COMINIT/COMWAKE to pass the tests. */ + writeb(IMX8QM_SATA_PHY_GEN1_TX_POST_CURSOR_RATIO, + imxpriv->phy_base + + IMX8QM_SATA_PHY_REG10_TX_POST_CURSOR_RATIO); + writeb(IMX8QM_SATA_PHY_GEN2_TX_POST_CURSOR_RATIO, + imxpriv->phy_base + + IMX8QM_SATA_PHY_REG22_TX_POST_CURSOR_RATIO); + + writeb(IMX8QM_SATA_PHY_UPDATE_SETTING, imxpriv->phy_base + + IMX8QM_SATA_PHY_REG128_UPDATE_SETTING); + + reg = IMX8QM_SATA_PP2CFG_COMINIT_NEGATE_MIN | + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP | + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MAX | + IMX8QM_SATA_PP2CFG_COMINT_BURST_GAP_MIN; + writel(reg, imxpriv->mmio + IMX8QM_SATA_PP2CFG_OFFSET); + reg = IMX8QM_SATA_PP3CFG_COMWAKE_NEGATE_MIN | + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP | + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MAX | + IMX8QM_SATA_PP3CFG_COMWAKE_BURST_GAP_MIN; + writel(reg, imxpriv->mmio + IMX8QM_SATA_PP3CFG_OFFSET); + + udelay(100); + + /* + * To reduce the power consumption, gate off + * the PHY clks + */ +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&imxpriv->phy_apbclk); + clk_disable(&imxpriv->phy_pclk1); + clk_disable(&imxpriv->phy_pclk0); +#endif + return ret; + } + +err_out: +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&imxpriv->phy_apbclk); +disable_epcs_rx_clk: + clk_disable(&imxpriv->epcs_rx_clk); +disable_epcs_tx_clk: + clk_disable(&imxpriv->epcs_tx_clk); +disable_phy_pclk1: + clk_disable(&imxpriv->phy_pclk1); +disable_phy_pclk0: + clk_disable(&imxpriv->phy_pclk0); +#endif + return ret; +} + +static int imx8_sata_probe(struct udevice *dev, struct imx_ahci_priv *imxpriv) +{ + int ret = 0; + fdt_addr_t addr; + + if (dev_read_u32u(dev, "ext_osc", &imxpriv->ext_osc)) { + dev_info(dev, "ext_osc is not specified.\n"); + /* Use the external osc as ref clk defaultly. */ + imxpriv->ext_osc = 1; + } + + if (dev_read_u32u(dev, "fsl,phy-imp", &imxpriv->imped_ratio)) { + /* + * Regarding to the differnet Hw designs, + * Set the impedance ratio to 0x6c when 85OHM is used. + * Keep it to default value 0x80, when 100OHM is used. + */ + dev_info(dev, "phy impedance ratio is not specified.\n"); + imxpriv->imped_ratio = IMX8QM_SATA_PHY_IMPED_RATIO_85OHM; + } + + addr = dev_read_addr_name(dev, "phy"); + if (addr == FDT_ADDR_T_NONE){ + dev_err(dev, "no phy space\n"); + return -ENOMEM; + } + + imxpriv->phy_base = (void __iomem *)addr; + + imxpriv->gpr = + syscon_regmap_lookup_by_phandle(dev, "hsio"); + if (IS_ERR(imxpriv->gpr)) { + dev_err(dev, "unable to find gpr registers\n"); + return PTR_ERR(imxpriv->gpr); + } + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_name(dev, "epcs_tx", &imxpriv->epcs_tx_clk); + if (ret) { + dev_err(dev, "can't get sata_epcs tx clock.\n"); + return ret; + } + + ret = clk_get_by_name(dev, "epcs_rx", &imxpriv->epcs_rx_clk); + if (ret) { + dev_err(dev, "can't get sata_epcs rx clock.\n"); + return ret; + } + + ret = clk_get_by_name(dev, "phy_pclk0", &imxpriv->phy_pclk0); + if (ret) { + dev_err(dev, "can't get sata_phy_pclk0 clock.\n"); + return ret; + } + + ret = clk_get_by_name(dev, "phy_pclk1", &imxpriv->phy_pclk1); + if (ret) { + dev_err(dev, "can't get sata_phy_pclk1 clock.\n"); + return ret; + } + + ret = clk_get_by_name(dev, "phy_apbclk", &imxpriv->phy_apbclk); + if (ret) { + dev_err(dev, "can't get sata_phy_apbclk clock.\n"); + return ret; + } +#endif + + /* Fetch GPIO, then enable the external OSC */ + ret = gpio_request_by_name(dev, "clkreq-gpio", 0, &imxpriv->clkreq_gpio, + (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)); + if (ret) { + dev_err(dev, "%d unable to get clkreq.\n", ret); + return ret; + } + + return 0; +} + + +static int imx_sata_enable(struct udevice *dev) +{ + struct imx_ahci_priv *imxpriv = dev_get_priv(dev); + int ret = 0; + + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { + /* + * set PHY Paremeters, two steps to configure the GPR13, + * one write for rest of parameters, mask of first write + * is 0x07ffffff, and the other one write for setting + * the mpll_clk_en. + */ + regmap_update_bits(imxpriv->gpr, 0x34, + IOMUXC_GPR13_SATA_MASK, + imxpriv->phy_params); + regmap_update_bits(imxpriv->gpr, 0x34, + IOMUXC_GPR13_SATA_PHY_1_MASK, + IOMUXC_GPR13_SATA_PHY_1_SLOW); + + udelay(200); + } + + if (imxpriv->type == AHCI_IMX6Q) { + ret = imx_sata_phy_reset(imxpriv); + } else if (imxpriv->type == AHCI_IMX6QP) { + /* 6qp adds the sata reset mechanism, use it for 6qp sata */ + regmap_update_bits(imxpriv->gpr, 0x14, + BIT(10), 0); + + regmap_update_bits(imxpriv->gpr, 0x14, + BIT(11), 0); + udelay(50); + regmap_update_bits(imxpriv->gpr, 0x14, + BIT(11), BIT(11)); + } else if (imxpriv->type == AHCI_IMX8QM) { + ret = imx8_sata_enable(dev); + } + + if (ret) { + dev_err(dev, "failed to reset phy: %d\n", ret); + return ret; + } + + udelay(2000); + + return 0; +} + +static void imx_sata_disable(struct udevice *dev) +{ + struct imx_ahci_priv *imxpriv = dev_get_priv(dev); + + if (imxpriv->type == AHCI_IMX6QP) + regmap_update_bits(imxpriv->gpr, 0x14, + BIT(10), BIT(10)); + + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { + regmap_update_bits(imxpriv->gpr, 0x34, + IOMUXC_GPR13_SATA_PHY_1_MASK, + 0); + } + + if (imxpriv->type == AHCI_IMX8QM) { +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&imxpriv->epcs_rx_clk); + clk_disable(&imxpriv->epcs_tx_clk); +#endif + } +} + + +static int imx_ahci_bind(struct udevice *dev) +{ + struct udevice *scsi_dev; + + return ahci_bind_scsi(dev, &scsi_dev); +} + +static int imx_ahci_probe(struct udevice *dev) +{ + int ret = 0; + struct imx_ahci_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + unsigned int reg_val; + + priv->type = (enum ahci_imx_type)dev_get_driver_data(dev); + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_name(dev, "sata", &priv->sata_clk); + if (ret) { + printf("Failed to get sata clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "sata_ref", &priv->sata_ref_clk); + if (ret) { + printf("Failed to get sata_ref clk\n"); + return ret; + } +#endif + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) { + dev_err(dev, "no mmio space\n"); + return -EINVAL; + } + + priv->mmio = (void __iomem *)addr; + + if (priv->type == AHCI_IMX6Q || priv->type == AHCI_IMX6QP) { + priv->gpr = syscon_regmap_lookup_by_phandle(dev, "gpr"); + if (IS_ERR(priv->gpr)) { + dev_err(dev, + "failed to find fsl,imx6q-iomux-gpr regmap\n"); + return PTR_ERR(priv->gpr); + } + + priv->phy_params = + IOMUXC_GPR13_SATA_PHY_7_SATA2M | + (3 << IOMUXC_GPR13_SATA_PHY_6_SHIFT) | + IOMUXC_GPR13_SATA_SPEED_3G | + IOMUXC_GPR13_SATA_PHY_2_TX_1P025V | + IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB | + IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16 | + IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB | + IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED; + } else if (priv->type == AHCI_IMX8QM) { + ret = imx8_sata_probe(dev, priv); + if (ret) + return ret; + } + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_enable(&priv->sata_clk); + if (ret) + return ret; + + ret = clk_enable(&priv->sata_ref_clk); + if (ret) + return ret; +#else + enable_sata_clock(); +#endif + + ret = imx_sata_enable(dev); + if (ret) + goto disable_clk; + + /* + * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL, + * and IP vendor specific register IMX_TIMER1MS. + * Configure CAP_SSS (support stagered spin up). + * Implement the port0. + * Get the ahb clock rate, and configure the TIMER1MS register. + */ + reg_val = readl(priv->mmio + HOST_CAP); + if (!(reg_val & (1 << 27))) { + reg_val |= (1 << 27); + writel(reg_val, priv->mmio + HOST_CAP); + } + reg_val = readl(priv->mmio + HOST_PORTS_IMPL); + if (!(reg_val & 0x1)) { + reg_val |= 0x1; + writel(reg_val, priv->mmio + HOST_PORTS_IMPL); + } + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk); + if (ret) { + dev_info(dev, "no ahb clock.\n"); + } else { + /* + * AHB clock is only used to configure the vendor specified + * TIMER1MS register. Set it if the AHB clock is defined. + */ + reg_val = clk_get_rate(&priv->ahb_clk) / 1000; + writel(reg_val, priv->mmio + IMX_TIMER1MS); + } +#else + reg_val = mxc_get_clock(MXC_AHB_CLK) / 1000; + writel(reg_val, priv->mmio + IMX_TIMER1MS); +#endif + + ret = ahci_probe_scsi(dev, (ulong)priv->mmio); + if (ret) + goto disable_sata; + + return ret; + +disable_sata: + imx_sata_disable(dev); +disable_clk: +#if CONFIG_IS_ENABLED(CLK) + clk_disable(&priv->sata_ref_clk); + clk_disable(&priv->sata_clk); +#else + disable_sata_clock(); +#endif + return ret; +} + +static int imx_ahci_remove(struct udevice *dev) +{ + imx_sata_disable(dev); + +#if CONFIG_IS_ENABLED(CLK) + struct imx_ahci_priv *priv = dev_get_priv(dev); + clk_disable(&priv->sata_ref_clk); + clk_disable(&priv->sata_clk); +#else + disable_sata_clock(); +#endif + + return 0; +} + + +static const struct udevice_id imx_ahci_ids[] = { + { .compatible = "fsl,imx6q-ahci", .data = (ulong)AHCI_IMX6Q }, + { .compatible = "fsl,imx6qp-ahci", .data = (ulong)AHCI_IMX6QP }, + { .compatible = "fsl,imx8qm-ahci", .data = (ulong)AHCI_IMX8QM }, + { } +}; + +U_BOOT_DRIVER(imx_ahci) = { + .name = "imx_ahci", + .id = UCLASS_AHCI, + .of_match = imx_ahci_ids, + .bind = imx_ahci_bind, + .probe = imx_ahci_probe, + .remove = imx_ahci_remove, + .priv_auto = sizeof(struct imx_ahci_priv), +}; diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index 01bbbdf3aea..5f07207cce8 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_CLK_IMX8) += clk-imx8.o ifdef CONFIG_CLK_IMX8 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o +obj-$(CONFIG_IMX8DXL) += clk-imx8qxp.o obj-$(CONFIG_IMX8QM) += clk-imx8qm.o endif obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \ diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c index 8484613eed5..2f5c5e5ed1b 100644 --- a/drivers/clk/imx/clk-imx8.c +++ b/drivers/clk/imx/clk-imx8.c @@ -14,32 +14,294 @@ #include #include #include +#include #include "clk-imx8.h" -__weak ulong imx8_clk_get_rate(struct clk *clk) +struct imx8_clks_collect *soc_data[] = { +#if defined(CONFIG_IMX8QXP) || defined(CONFIG_IMX8DXL) + &imx8qxp_clk_collect, +#endif +#ifdef CONFIG_IMX8QM + &imx8qm_clk_collect, +#endif +}; + +static ulong __imx8_clk_get_rate(struct udevice *dev, ulong id); +static int __imx8_clk_enable(struct udevice *dev, ulong id, bool enable); +static ulong __imx8_clk_set_rate(struct udevice *dev, ulong id, unsigned long rate); + +static struct imx8_clks_collect * find_clks_collect(struct udevice *dev) +{ + ulong data = (ulong)dev_get_driver_data(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(soc_data); i++) { + if (soc_data[i]->match_flag == data) + return soc_data[i]; + } + + return NULL; +} + +static void * check_imx8_clk(struct udevice *dev, enum imx8_clk_type type, ulong id, u32 size_of_clk) +{ + u32 i, size; + struct imx8_clks_collect *clks_col = find_clks_collect(dev); + struct imx8_clk_header *hdr; + ulong clks; + + if (!clks_col || !(clks_col->clks[type].type_clks)) { + printf("%s fails to get clks for type %d\n", + __func__, type); + return NULL; + } + + clks = (ulong)(clks_col->clks[type].type_clks); + size = clks_col->clks[type].num; + + for (i = 0; i < size; i++) { + hdr = (struct imx8_clk_header *)clks; + if (id == hdr->id) + return (void *)hdr; + + clks += size_of_clk; + } + + return NULL; +} + +static ulong imx8_get_rate_lpcg(struct udevice *dev, struct imx8_lpcg_clks *lpcg_clk) +{ + if (lpcg_clk->parent_id != 0) { + if (lpcg_is_clock_on(lpcg_clk->lpcg, lpcg_clk->bit_idx >> 2)) { + return __imx8_clk_get_rate(dev, lpcg_clk->parent_id); + } else { + return 0; + } + } else { + return -ENOSYS; + } +} + +static ulong imx8_get_rate_slice(struct udevice *dev, struct imx8_clks *slice_clk) +{ + int ret; + u32 rate; + + ret = sc_pm_get_clock_rate(-1, slice_clk->rsrc, slice_clk->pm_clk, + (sc_pm_clock_rate_t *)&rate); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + + return rate; +} + +static ulong imx8_get_rate_fixed(struct udevice *dev, struct imx8_fixed_clks *fixed_clk) +{ + return fixed_clk->rate; +} + +static ulong __imx8_clk_get_rate(struct udevice *dev, ulong id) +{ + void* clkdata; + + clkdata = check_imx8_clk(dev, IMX8_CLK_LPCG, id, sizeof(struct imx8_lpcg_clks)); + if (clkdata) { + return imx8_get_rate_lpcg(dev, (struct imx8_lpcg_clks *)clkdata); + } + + clkdata = check_imx8_clk(dev, IMX8_CLK_SLICE, id, sizeof(struct imx8_clks)); + if (clkdata) { + return imx8_get_rate_slice(dev, (struct imx8_clks *)clkdata); + } + + clkdata = check_imx8_clk(dev, IMX8_CLK_FIXED, id, sizeof(struct imx8_fixed_clks)); + if (clkdata) { + return imx8_get_rate_fixed(dev, (struct imx8_fixed_clks *)clkdata); + } + + return -ENOSYS; +} + +static ulong imx8_clk_get_rate(struct clk *clk) +{ + return __imx8_clk_get_rate(clk->dev, clk->id); +} + +static ulong imx8_set_rate_lpcg(struct udevice *dev, struct imx8_lpcg_clks *lpcg_clk, unsigned long rate) +{ + if (lpcg_clk->parent_id != 0) { + return __imx8_clk_set_rate(dev, lpcg_clk->parent_id, rate); + } else { + return -ENOSYS; + } +} + +static ulong imx8_set_rate_slice(struct udevice *dev, struct imx8_clks *slice_clk, unsigned long rate) +{ + int ret; + u32 new_rate = rate; + + ret = sc_pm_set_clock_rate(-1, slice_clk->rsrc, slice_clk->pm_clk, &new_rate); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + + return new_rate; +} + +static ulong imx8_set_rate_gpr(struct udevice *dev, struct imx8_gpr_clks *gpr_clk, unsigned long rate) { + ulong parent_rate; + u32 val; + int ret; + + if (gpr_clk->parent_id == 0) + return -ENOSYS; + + parent_rate = __imx8_clk_get_rate(dev, gpr_clk->parent_id); + if (parent_rate > 0) { + val = (rate < parent_rate) ? 1 : 0; + + ret = sc_misc_set_control(-1, gpr_clk->rsrc, + gpr_clk->gpr_id, val); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + + return rate; + } + + return -ENOSYS; +} + +static ulong __imx8_clk_set_rate(struct udevice *dev, ulong id, unsigned long rate) +{ + void* clkdata; + + clkdata = check_imx8_clk(dev, IMX8_CLK_SLICE, id, sizeof(struct imx8_clks)); + if (clkdata) { + return imx8_set_rate_slice(dev, (struct imx8_clks *)clkdata, rate); + } + + clkdata = check_imx8_clk(dev, IMX8_CLK_LPCG, id, sizeof(struct imx8_lpcg_clks)); + if (clkdata) { + return imx8_set_rate_lpcg(dev, (struct imx8_lpcg_clks *)clkdata, rate); + } + + clkdata = check_imx8_clk(dev, IMX8_CLK_GPR, id, sizeof(struct imx8_gpr_clks)); + if (clkdata) { + return imx8_set_rate_gpr(dev, (struct imx8_gpr_clks *)clkdata, rate); + } + + return -ENOSYS; +} + +static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) +{ + return __imx8_clk_set_rate(clk->dev, clk->id, rate); + +} + +static int imx8_enable_slice(struct udevice *dev, struct imx8_clks *slice_clk, bool enable) +{ + int ret; + + ret = sc_pm_clock_enable(-1, slice_clk->rsrc, slice_clk->pm_clk, enable, 0); + if (ret) { + printf("%s err %d\n", __func__, ret); + return ret; + } + return 0; } -__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) +static int imx8_enable_lpcg(struct udevice *dev, struct imx8_lpcg_clks *lpcg_clk, bool enable) { + if (enable) { + if (lpcg_clk->parent_id != 0) { + __imx8_clk_enable(dev, lpcg_clk->parent_id, enable); + } + + lpcg_clock_on(lpcg_clk->lpcg, lpcg_clk->bit_idx >> 2); + } else { + lpcg_clock_off(lpcg_clk->lpcg, lpcg_clk->bit_idx >> 2); + + if (lpcg_clk->parent_id != 0) { + __imx8_clk_enable(dev, lpcg_clk->parent_id, enable); + } + } + return 0; } -__weak int __imx8_clk_enable(struct clk *clk, bool enable) +static int __imx8_clk_enable(struct udevice *dev, ulong id, bool enable) { - return -ENOTSUPP; + void* clkdata; + + clkdata = check_imx8_clk(dev, IMX8_CLK_LPCG, id, sizeof(struct imx8_lpcg_clks)); + if (clkdata) { + return imx8_enable_lpcg(dev, (struct imx8_lpcg_clks *)clkdata, enable); + } + + clkdata = check_imx8_clk(dev, IMX8_CLK_SLICE, id, sizeof(struct imx8_clks)); + if (clkdata) { + return imx8_enable_slice(dev, (struct imx8_clks *)clkdata, enable); + } + + return -ENOSYS; } static int imx8_clk_disable(struct clk *clk) { - return __imx8_clk_enable(clk, 0); + return __imx8_clk_enable(clk->dev, clk->id, 0); } static int imx8_clk_enable(struct clk *clk) { - return __imx8_clk_enable(clk, 1); + return __imx8_clk_enable(clk->dev, clk->id, 1); +} + +static int imx8_set_parent_mux(struct udevice *dev, struct imx8_mux_clks *mux_clk, ulong pid) +{ + u32 i; + int ret; + struct imx8_clks *slice_clkdata; + + slice_clkdata = check_imx8_clk(dev, IMX8_CLK_SLICE, mux_clk->slice_clk_id, sizeof(struct imx8_clks)); + if (!slice_clkdata) { + printf("Error: fail to find slice clk %lu for this mux %lu\n", mux_clk->slice_clk_id, mux_clk->hdr.id); + return -EINVAL; + } + + for (i = 0; i< CLK_IMX8_MAX_MUX_SEL; i++) { + if (pid == mux_clk->parent_clks[i]) { + ret = sc_pm_set_clock_parent(-1, slice_clkdata->rsrc, slice_clkdata->pm_clk, i); + if (ret) + printf("Error: fail to set clock parent rsrc %d, pm_clk %d, parent clk %d\n", + slice_clkdata->rsrc, slice_clkdata->pm_clk, i); + return ret; + } + } + + return -ENOSYS; +} + +static int imx8_clk_set_parent(struct clk *clk, struct clk *parent) +{ + void* clkdata; + + clkdata = check_imx8_clk(clk->dev, IMX8_CLK_MUX, clk->id, sizeof(struct imx8_mux_clks)); + if (clkdata) { + return imx8_set_parent_mux(clk->dev, (struct imx8_mux_clks *)clkdata, parent->id); + } + + return -ENOSYS; } #if CONFIG_IS_ENABLED(CMD_CLK) @@ -49,6 +311,9 @@ int soc_clk_dump(void) struct clk clk; unsigned long rate; int i, ret; + u32 size; + struct imx8_clks *clks; + struct imx8_clks_collect *clks_col; ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(imx8_clk), &dev); @@ -57,8 +322,19 @@ int soc_clk_dump(void) printf("Clk\t\tHz\n"); - for (i = 0; i < num_clks; i++) { - clk.id = imx8_clk_names[i].id; + clks_col = find_clks_collect(dev); + + if (!clks_col || !(clks_col->clks[IMX8_CLK_SLICE].type_clks)) { + printf("%s fails to get clks for type %d\n", + __func__, IMX8_CLK_SLICE); + return -ENODEV; + } + + clks = (struct imx8_clks *)(clks_col->clks[IMX8_CLK_SLICE].type_clks); + size = clks_col->clks[IMX8_CLK_SLICE].num; + + for (i = 0; i < size; i++) { + clk.id = clks[i].hdr.id; ret = clk_request(dev, &clk); if (ret < 0) { debug("%s clk_request() failed: %d\n", __func__, ret); @@ -72,21 +348,22 @@ int soc_clk_dump(void) if (ret == -ENOTSUPP) { printf("clk ID %lu not supported yet\n", - imx8_clk_names[i].id); + clks[i].hdr.id); continue; } if (ret < 0) { printf("%s %lu: get_rate err: %d\n", - __func__, imx8_clk_names[i].id, ret); + __func__, clks[i].hdr.id, ret); continue; } printf("%s(%3lu):\t%lu\n", - imx8_clk_names[i].name, imx8_clk_names[i].id, rate); + clks[i].hdr.name, clks[i].hdr.id, rate); } return 0; } + #endif static struct clk_ops imx8_clk_ops = { @@ -94,6 +371,7 @@ static struct clk_ops imx8_clk_ops = { .get_rate = imx8_clk_get_rate, .enable = imx8_clk_enable, .disable = imx8_clk_disable, + .set_parent = imx8_clk_set_parent, }; static int imx8_clk_probe(struct udevice *dev) @@ -102,8 +380,8 @@ static int imx8_clk_probe(struct udevice *dev) } static const struct udevice_id imx8_clk_ids[] = { - { .compatible = "fsl,imx8qxp-clk" }, - { .compatible = "fsl,imx8qm-clk" }, + { .compatible = "fsl,imx8qxp-clk", .data = FLAG_CLK_IMX8_IMX8QXP, }, + { .compatible = "fsl,imx8qm-clk", .data = FLAG_CLK_IMX8_IMX8QM, }, { }, }; diff --git a/drivers/clk/imx/clk-imx8.h b/drivers/clk/imx/clk-imx8.h index 68ad6755e80..c0566f81171 100644 --- a/drivers/clk/imx/clk-imx8.h +++ b/drivers/clk/imx/clk-imx8.h @@ -4,16 +4,87 @@ * Peng Fan */ -struct imx8_clks { +#define CLK_IMX8_MAX_MUX_SEL 5 + +#define FLAG_CLK_IMX8_IMX8QM BIT(0) +#define FLAG_CLK_IMX8_IMX8QXP BIT(1) + +struct imx8_clk_header { ulong id; +#if CONFIG_IS_ENABLED(CMD_CLK) const char *name; +#endif +}; + +struct imx8_clks { + struct imx8_clk_header hdr; + u16 rsrc; + sc_pm_clk_t pm_clk; +}; + +struct imx8_fixed_clks { + struct imx8_clk_header hdr; + ulong rate; +}; + +struct imx8_gpr_clks { + struct imx8_clk_header hdr; + u16 rsrc; + sc_ctrl_t gpr_id; + ulong parent_id; +}; + +struct imx8_lpcg_clks { + struct imx8_clk_header hdr; + u8 bit_idx; + u32 lpcg; + ulong parent_id; +}; + +struct imx8_mux_clks { + struct imx8_clk_header hdr; + ulong slice_clk_id; + ulong parent_clks[CLK_IMX8_MAX_MUX_SEL]; +}; + +enum imx8_clk_type { + IMX8_CLK_SLICE = 0, + IMX8_CLK_FIXED = 1, + IMX8_CLK_GPR = 2, + IMX8_CLK_LPCG = 3, + IMX8_CLK_MUX = 4, + IMX8_CLK_END = 5, +}; + +struct imx8_clk_pair { + void *type_clks; + u32 num; +}; + +struct imx8_clks_collect { + struct imx8_clk_pair clks[IMX8_CLK_END]; + ulong match_flag; }; #if CONFIG_IS_ENABLED(CMD_CLK) -extern struct imx8_clks imx8_clk_names[]; -extern int num_clks; +#define CLK_3(ID, NAME, MEM2) \ + { { ID, NAME, }, MEM2, } +#define CLK_4(ID, NAME, MEM2, MEM3) \ + { { ID, NAME, }, MEM2, MEM3, } +#define CLK_5(ID, NAME, MEM2, MEM3, MEM4) \ + { { ID, NAME, }, MEM2, MEM3, MEM4, } +#define CLK_MUX(ID, NAME, MEM2, MUX0, MUX1, MUX2, MUX3, MUX4) \ + { { ID, NAME, }, MEM2, { MUX0, MUX1, MUX2, MUX3, MUX4} } +#else +#define CLK_3(ID, NAME, MEM2) \ + { { ID, }, MEM2, } +#define CLK_4(ID, NAME, MEM2, MEM3) \ + { { ID, }, MEM2, MEM3, } +#define CLK_5(ID, NAME, MEM2, MEM3, MEM4) \ + { { ID, }, MEM2, MEM3, MEM4, } +#define CLK_MUX(ID, NAME, MEM2, MUX0, MUX1, MUX2, MUX3, MUX4) \ + { { ID, }, MEM2, { MUX0, MUX1, MUX2, MUX3, MUX4} } #endif -ulong imx8_clk_get_rate(struct clk *clk); -ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate); -int __imx8_clk_enable(struct clk *clk, bool enable); +extern struct imx8_clks_collect imx8qxp_clk_collect; +extern struct imx8_clks_collect imx8qm_clk_collect; diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 7e466d630a0..848b8aff737 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -13,338 +13,217 @@ #include #include #include +#include #include "clk-imx8.h" -#if CONFIG_IS_ENABLED(CMD_CLK) -struct imx8_clks imx8_clk_names[] = { - { IMX8QM_A53_DIV, "A53_DIV" }, - { IMX8QM_UART0_CLK, "UART0" }, - { IMX8QM_UART1_CLK, "UART1" }, - { IMX8QM_UART2_CLK, "UART2" }, - { IMX8QM_UART3_CLK, "UART3" }, - { IMX8QM_SDHC0_CLK, "SDHC0" }, - { IMX8QM_SDHC1_CLK, "SDHC1" }, - { IMX8QM_SDHC2_CLK, "SDHC2" }, - { IMX8QM_ENET0_AHB_CLK, "ENET0_AHB" }, - { IMX8QM_ENET0_IPG_CLK, "ENET0_IPG" }, - { IMX8QM_ENET0_REF_DIV, "ENET0_REF" }, - { IMX8QM_ENET0_PTP_CLK, "ENET0_PTP" }, - { IMX8QM_ENET1_AHB_CLK, "ENET1_AHB" }, - { IMX8QM_ENET1_IPG_CLK, "ENET1_IPG" }, - { IMX8QM_ENET1_REF_DIV, "ENET1_REF" }, - { IMX8QM_ENET1_PTP_CLK, "ENET1_PTP" }, +static struct imx8_clks imx8qm_clks[] = { + CLK_4( IMX8QM_A53_DIV, "A53_DIV", SC_R_A53, SC_PM_CLK_CPU ), + CLK_4( IMX8QM_A72_DIV, "A72_DIV", SC_R_A72, SC_PM_CLK_CPU ), + CLK_4( IMX8QM_I2C0_DIV, "I2C0_DIV", SC_R_I2C_0, SC_PM_CLK_PER ), + CLK_4( IMX8QM_I2C1_DIV, "I2C1_DIV", SC_R_I2C_1, SC_PM_CLK_PER ), + CLK_4( IMX8QM_I2C2_DIV, "I2C2_DIV", SC_R_I2C_2, SC_PM_CLK_PER ), + CLK_4( IMX8QM_I2C3_DIV, "I2C3_DIV", SC_R_I2C_3, SC_PM_CLK_PER ), + CLK_4( IMX8QM_LVDS0_I2C0_DIV, "LVDS0 I2C0 DIV", SC_R_LVDS_0_I2C_0, SC_PM_CLK_PER ), + CLK_4( IMX8QM_LVDS0_I2C1_DIV, "LVDS0 I2C1 DIV", SC_R_LVDS_0_I2C_1, SC_PM_CLK_PER ), + CLK_4( IMX8QM_LVDS1_I2C0_DIV, "LVDS1 I2C0 DIV", SC_R_LVDS_1_I2C_0, SC_PM_CLK_PER ), + CLK_4( IMX8QM_LVDS1_I2C1_DIV, "LVDS1 I2C1 DIV", SC_R_LVDS_1_I2C_1, SC_PM_CLK_PER ), + CLK_4( IMX8QM_MIPI0_I2C0_DIV, "MIPI0 I2C0_DIV", SC_R_MIPI_0_I2C_0, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QM_MIPI0_I2C1_DIV, "MIPI0 I2C1_DIV", SC_R_MIPI_0_I2C_1, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QM_MIPI1_I2C0_DIV, "MIPI1 I2C0_DIV", SC_R_MIPI_1_I2C_0, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QM_MIPI1_I2C1_DIV, "MIPI1 I2C1_DIV", SC_R_MIPI_1_I2C_1, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QM_CSI0_I2C0_DIV, "CSI0 I2C0_DIV", SC_R_CSI_0_I2C_0, SC_PM_CLK_PER ), + CLK_4( IMX8QM_CSI1_I2C0_DIV, "CSI1 I2C0_DIV", SC_R_CSI_1_I2C_0, SC_PM_CLK_PER ), + CLK_4( IMX8QM_HDMI_I2C0_DIV, "HDMI I2C0_DIV", SC_R_HDMI_I2C_0, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QM_HDMI_IPG_CLK, "HDMI IPG_CLK", SC_R_HDMI, SC_PM_CLK_MISC ), + CLK_4( IMX8QM_HDMI_RX_I2C0_DIV, "HDMI RX I2C_DIV", SC_R_HDMI_RX_I2C_0, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QM_UART0_DIV, "UART0_DIV", SC_R_UART_0, SC_PM_CLK_PER ), + CLK_4( IMX8QM_UART1_DIV, "UART1_DIV", SC_R_UART_1, SC_PM_CLK_PER ), + CLK_4( IMX8QM_UART2_DIV, "UART2_DIV", SC_R_UART_2, SC_PM_CLK_PER ), + CLK_4( IMX8QM_UART3_DIV, "UART3_DIV", SC_R_UART_3, SC_PM_CLK_PER ), + CLK_4( IMX8QM_SDHC0_DIV, "SDHC0_DIV", SC_R_SDHC_0, SC_PM_CLK_PER ), + CLK_4( IMX8QM_SDHC1_DIV, "SDHC1_DIV", SC_R_SDHC_1, SC_PM_CLK_PER ), + CLK_4( IMX8QM_SDHC2_DIV, "SDHC2_DIV", SC_R_SDHC_2, SC_PM_CLK_PER ), + CLK_4( IMX8QM_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_R_ENET_0, SC_PM_CLK_PER ), + CLK_4( IMX8QM_ENET0_RGMII_DIV, "ENET0_RGMII_DIV", SC_R_ENET_0, SC_PM_CLK_MISC0 ), + CLK_4( IMX8QM_ENET1_ROOT_DIV, "ENET1_ROOT_DIV", SC_R_ENET_1, SC_PM_CLK_PER ), + CLK_4( IMX8QM_ENET1_RGMII_DIV, "ENET1_RGMII_DIV", SC_R_ENET_1, SC_PM_CLK_MISC0 ), + + CLK_4( IMX8QM_USB3_ACLK_DIV, "USB3_ACLK_DIV", SC_R_USB_2, SC_PM_CLK_PER ), + CLK_4( IMX8QM_USB3_BUS_DIV, "USB3_BUS_DIV", SC_R_USB_2, SC_PM_CLK_MST_BUS ), + CLK_4( IMX8QM_USB3_LPM_DIV, "USB3_LPM_DIV", SC_R_USB_2, SC_PM_CLK_MISC ), + + CLK_4( IMX8QM_FSPI0_DIV, "FSPI0_DIV", SC_R_FSPI_0, SC_PM_CLK_PER ), + + CLK_4( IMX8QM_GPMI_BCH_IO_DIV, "GPMI_IO_DIV", SC_R_NAND, SC_PM_CLK_MST_BUS ), + CLK_4( IMX8QM_GPMI_BCH_DIV, "GPMI_BCH_DIV", SC_R_NAND, SC_PM_CLK_PER ), }; -int num_clks = ARRAY_SIZE(imx8_clk_names); -#endif - -ulong imx8_clk_get_rate(struct clk *clk) -{ - sc_pm_clk_t pm_clk; - ulong rate; - u16 resource; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - switch (clk->id) { - case IMX8QM_A53_DIV: - resource = SC_R_A53; - pm_clk = SC_PM_CLK_CPU; - break; - case IMX8QM_I2C0_IPG_CLK: - case IMX8QM_I2C0_CLK: - case IMX8QM_I2C0_DIV: - resource = SC_R_I2C_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_I2C1_IPG_CLK: - case IMX8QM_I2C1_CLK: - case IMX8QM_I2C1_DIV: - resource = SC_R_I2C_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_I2C2_IPG_CLK: - case IMX8QM_I2C2_CLK: - case IMX8QM_I2C2_DIV: - resource = SC_R_I2C_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_I2C3_IPG_CLK: - case IMX8QM_I2C3_CLK: - case IMX8QM_I2C3_DIV: - resource = SC_R_I2C_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_SDHC0_IPG_CLK: - case IMX8QM_SDHC0_CLK: - case IMX8QM_SDHC0_DIV: - resource = SC_R_SDHC_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_SDHC1_IPG_CLK: - case IMX8QM_SDHC1_CLK: - case IMX8QM_SDHC1_DIV: - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_SDHC2_IPG_CLK: - case IMX8QM_SDHC2_CLK: - case IMX8QM_SDHC2_DIV: - resource = SC_R_SDHC_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART0_IPG_CLK: - case IMX8QM_UART0_CLK: - resource = SC_R_UART_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART1_CLK: - resource = SC_R_UART_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART2_CLK: - resource = SC_R_UART_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART3_CLK: - resource = SC_R_UART_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_ENET0_IPG_CLK: - case IMX8QM_ENET0_AHB_CLK: - case IMX8QM_ENET0_REF_DIV: - case IMX8QM_ENET0_PTP_CLK: - resource = SC_R_ENET_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_ENET1_IPG_CLK: - case IMX8QM_ENET1_AHB_CLK: - case IMX8QM_ENET1_REF_DIV: - case IMX8QM_ENET1_PTP_CLK: - resource = SC_R_ENET_1; - pm_clk = SC_PM_CLK_PER; - break; - default: - if (clk->id < IMX8QM_UART0_IPG_CLK || - clk->id >= IMX8QM_CLK_END) { - printf("%s(Invalid clk ID #%lu)\n", - __func__, clk->id); - return -EINVAL; - } - return -ENOTSUPP; - }; - - ret = sc_pm_get_clock_rate(-1, resource, pm_clk, - (sc_pm_clock_rate_t *)&rate); - if (ret) { - printf("%s err %d\n", __func__, ret); - return ret; - } - - return rate; -} - -ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) -{ - sc_pm_clk_t pm_clk; - u32 new_rate = rate; - u16 resource; - int ret; - - debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); - - switch (clk->id) { - case IMX8QM_I2C0_IPG_CLK: - case IMX8QM_I2C0_CLK: - case IMX8QM_I2C0_DIV: - resource = SC_R_I2C_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_I2C1_IPG_CLK: - case IMX8QM_I2C1_CLK: - case IMX8QM_I2C1_DIV: - resource = SC_R_I2C_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_I2C2_IPG_CLK: - case IMX8QM_I2C2_CLK: - case IMX8QM_I2C2_DIV: - resource = SC_R_I2C_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_I2C3_IPG_CLK: - case IMX8QM_I2C3_CLK: - case IMX8QM_I2C3_DIV: - resource = SC_R_I2C_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART0_CLK: - resource = SC_R_UART_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART1_CLK: - resource = SC_R_UART_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART2_CLK: - resource = SC_R_UART_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART3_CLK: - resource = SC_R_UART_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_SDHC0_IPG_CLK: - case IMX8QM_SDHC0_CLK: - case IMX8QM_SDHC0_DIV: - resource = SC_R_SDHC_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_SDHC1_IPG_CLK: - case IMX8QM_SDHC1_CLK: - case IMX8QM_SDHC1_DIV: - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_SDHC2_IPG_CLK: - case IMX8QM_SDHC2_CLK: - case IMX8QM_SDHC2_DIV: - resource = SC_R_SDHC_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_ENET0_IPG_CLK: - case IMX8QM_ENET0_AHB_CLK: - case IMX8QM_ENET0_REF_DIV: - case IMX8QM_ENET0_PTP_CLK: - case IMX8QM_ENET0_ROOT_DIV: - resource = SC_R_ENET_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_ENET1_IPG_CLK: - case IMX8QM_ENET1_AHB_CLK: - case IMX8QM_ENET1_REF_DIV: - case IMX8QM_ENET1_PTP_CLK: - case IMX8QM_ENET1_ROOT_DIV: - resource = SC_R_ENET_1; - pm_clk = SC_PM_CLK_PER; - break; - default: - if (clk->id < IMX8QM_UART0_IPG_CLK || - clk->id >= IMX8QM_CLK_END) { - printf("%s(Invalid clk ID #%lu)\n", - __func__, clk->id); - return -EINVAL; - } - return -ENOTSUPP; - }; - - ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate); - if (ret) { - printf("%s err %d\n", __func__, ret); - return ret; - } - - return new_rate; -} - -int __imx8_clk_enable(struct clk *clk, bool enable) -{ - sc_pm_clk_t pm_clk; - u16 resource; - int ret; +static struct imx8_fixed_clks imx8qm_fixed_clks[] = { + CLK_3( IMX8QM_IPG_CONN_CLK_ROOT, "IPG_CONN_CLK", SC_83MHZ ), + CLK_3( IMX8QM_AHB_CONN_CLK_ROOT, "AHB_CONN_CLK", SC_166MHZ ), + CLK_3( IMX8QM_AXI_CONN_CLK_ROOT, "AXI_CONN_CLK", SC_333MHZ ), + CLK_3( IMX8QM_IPG_DMA_CLK_ROOT, "IPG_DMA_CLK", SC_120MHZ ), + CLK_3( IMX8QM_IPG_MIPI_CSI_CLK_ROOT, "IPG_MIPI_CLK", SC_120MHZ ), + CLK_3( IMX8QM_LVDS_IPG_CLK, "IPG_LVDS_CLK", SC_24MHZ ), + CLK_3( IMX8QM_LSIO_BUS_CLK, "LSIO_BUS_CLK", SC_100MHZ ), + CLK_3( IMX8QM_LSIO_MEM_CLK, "LSIO_MEM_CLK", SC_200MHZ ), + CLK_3( IMX8QM_MIPI0_CLK_ROOT, "MIPI0_CLK", SC_120MHZ ), + CLK_3( IMX8QM_MIPI1_CLK_ROOT, "MIPI1_CLK", SC_120MHZ ), + CLK_3( IMX8QM_HDMI_RX_IPG_CLK, "HDMI_RX_IPG_CLK", SC_200MHZ ), + CLK_3( IMX8QM_HSIO_PER_CLK, "HSIO_CLK", SC_133MHZ ), + CLK_3( IMX8QM_HSIO_AXI_CLK, "HSIO_AXI", SC_400MHZ ), +}; - debug("%s(#%lu)\n", __func__, clk->id); +static struct imx8_gpr_clks imx8qm_gpr_clks[] = { + CLK_5( IMX8QM_ENET0_REF_DIV, "ENET0_REF_DIV", SC_R_ENET_0, SC_C_CLKDIV, IMX8QM_ENET0_ROOT_DIV ), + CLK_4( IMX8QM_ENET0_REF_25MHZ_125MHZ_SEL, "ENET0_REF_25_125", SC_R_ENET_0, SC_C_SEL_125 ), + CLK_4( IMX8QM_ENET0_RMII_TX_SEL, "ENET0_RMII_TX", SC_R_ENET_0, SC_C_TXCLK ), + CLK_4( IMX8QM_ENET0_REF_25MHZ_125MHZ_CLK, "ENET0_REF_25_125_CLK", SC_R_ENET_0, SC_C_DISABLE_125 ), + CLK_4( IMX8QM_ENET0_REF_50MHZ_CLK, "ENET0_REF_50", SC_R_ENET_0, SC_C_DISABLE_50 ), + + CLK_5( IMX8QM_ENET1_REF_DIV, "ENET1_REF_DIV", SC_R_ENET_1, SC_C_CLKDIV, IMX8QM_ENET1_ROOT_DIV ), + CLK_4( IMX8QM_ENET1_REF_25MHZ_125MHZ_SEL, "ENET1_REF_25_125", SC_R_ENET_1, SC_C_SEL_125 ), + CLK_4( IMX8QM_ENET1_RMII_TX_SEL, "ENET1_RMII_TX", SC_R_ENET_1, SC_C_TXCLK ), + CLK_4( IMX8QM_ENET1_REF_25MHZ_125MHZ_CLK, "ENET1_REF_25_125_CLK", SC_R_ENET_1, SC_C_DISABLE_125 ), + CLK_4( IMX8QM_ENET1_REF_50MHZ_CLK, "ENET1_REF_50", SC_R_ENET_1, SC_C_DISABLE_50 ), +}; - switch (clk->id) { - case IMX8QM_I2C0_IPG_CLK: - case IMX8QM_I2C0_CLK: - case IMX8QM_I2C0_DIV: - resource = SC_R_I2C_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_I2C1_IPG_CLK: - case IMX8QM_I2C1_CLK: - case IMX8QM_I2C1_DIV: - resource = SC_R_I2C_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_I2C2_IPG_CLK: - case IMX8QM_I2C2_CLK: - case IMX8QM_I2C2_DIV: - resource = SC_R_I2C_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_I2C3_IPG_CLK: - case IMX8QM_I2C3_CLK: - case IMX8QM_I2C3_DIV: - resource = SC_R_I2C_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART0_CLK: - resource = SC_R_UART_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART1_CLK: - resource = SC_R_UART_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART2_CLK: - resource = SC_R_UART_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_UART3_CLK: - resource = SC_R_UART_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_SDHC0_IPG_CLK: - case IMX8QM_SDHC0_CLK: - case IMX8QM_SDHC0_DIV: - resource = SC_R_SDHC_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_SDHC1_IPG_CLK: - case IMX8QM_SDHC1_CLK: - case IMX8QM_SDHC1_DIV: - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_SDHC2_IPG_CLK: - case IMX8QM_SDHC2_CLK: - case IMX8QM_SDHC2_DIV: - resource = SC_R_SDHC_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_ENET0_IPG_CLK: - case IMX8QM_ENET0_AHB_CLK: - case IMX8QM_ENET0_REF_DIV: - case IMX8QM_ENET0_PTP_CLK: - resource = SC_R_ENET_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QM_ENET1_IPG_CLK: - case IMX8QM_ENET1_AHB_CLK: - case IMX8QM_ENET1_REF_DIV: - case IMX8QM_ENET1_PTP_CLK: - resource = SC_R_ENET_1; - pm_clk = SC_PM_CLK_PER; - break; - default: - if (clk->id < IMX8QM_UART0_IPG_CLK || - clk->id >= IMX8QM_CLK_END) { - printf("%s(Invalid clk ID #%lu)\n", - __func__, clk->id); - return -EINVAL; - } - return -ENOTSUPP; - } +static struct imx8_lpcg_clks imx8qm_lpcg_clks[] = { + CLK_5( IMX8QM_I2C0_CLK, "I2C0_CLK", 0, LPI2C_0_LPCG, IMX8QM_I2C0_DIV ), + CLK_5( IMX8QM_I2C0_IPG_CLK, "I2C0_IPG", 16, LPI2C_0_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QM_I2C1_CLK, "I2C1_CLK", 0, LPI2C_1_LPCG, IMX8QM_I2C1_DIV ), + CLK_5( IMX8QM_I2C1_IPG_CLK, "I2C1_IPG", 16, LPI2C_1_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QM_I2C2_CLK, "I2C2_CLK", 0, LPI2C_2_LPCG, IMX8QM_I2C2_DIV ), + CLK_5( IMX8QM_I2C2_IPG_CLK, "I2C2_IPG", 16, LPI2C_2_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QM_I2C3_CLK, "I2C3_CLK", 0, LPI2C_3_LPCG, IMX8QM_I2C3_DIV ), + CLK_5( IMX8QM_I2C3_IPG_CLK, "I2C3_IPG", 16, LPI2C_3_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), + + CLK_5( IMX8QM_LVDS0_I2C0_CLK, "LVDS0_I2C0_CLK", 0, DI_LVDS_0_LPCG + 0x10, IMX8QM_LVDS0_I2C0_DIV ), + CLK_5( IMX8QM_LVDS0_I2C0_IPG_CLK, "LVDS0_I2C0_IPG", 16, DI_LVDS_0_LPCG + 0x10, IMX8QM_LVDS_IPG_CLK ), + CLK_5( IMX8QM_LVDS0_I2C1_CLK, "LVDS0_I2C1_CLK", 0, DI_LVDS_0_LPCG + 0x14, IMX8QM_LVDS0_I2C1_DIV ), + CLK_5( IMX8QM_LVDS0_I2C1_IPG_CLK, "LVDS0_I2C1_IPG", 16, DI_LVDS_0_LPCG + 0x14, IMX8QM_LVDS_IPG_CLK ), + CLK_5( IMX8QM_LVDS1_I2C0_CLK, "LVDS1_I2C0_CLK", 0, DI_LVDS_1_LPCG + 0x10, IMX8QM_LVDS1_I2C0_DIV ), + CLK_5( IMX8QM_LVDS1_I2C0_IPG_CLK, "LVDS1_I2C0_IPG", 16, DI_LVDS_1_LPCG + 0x10, IMX8QM_LVDS_IPG_CLK ), + CLK_5( IMX8QM_LVDS1_I2C1_CLK, "LVDS1_I2C1_CLK", 0, DI_LVDS_1_LPCG + 0x14, IMX8QM_LVDS1_I2C1_DIV ), + CLK_5( IMX8QM_LVDS1_I2C1_IPG_CLK, "LVDS1_I2C1_IPG", 16, DI_LVDS_1_LPCG + 0x14, IMX8QM_LVDS_IPG_CLK ), + + CLK_5( IMX8QM_MIPI0_I2C0_CLK, "MIPI0_I2C0_CLK", 0, MIPI_DSI_0_LPCG + 0x1c, IMX8QM_MIPI0_I2C0_DIV ), + CLK_5( IMX8QM_MIPI0_I2C0_IPG_CLK, "MIPI0_I2C0_IPG", 0, MIPI_DSI_0_LPCG + 0x14, IMX8QM_MIPI0_I2C0_IPG_S_CLK), + CLK_5( IMX8QM_MIPI0_I2C0_IPG_S_CLK, "MIPI0_I2C0_IPG_S", 0, MIPI_DSI_0_LPCG + 0x18, IMX8QM_MIPI0_CLK_ROOT ), + CLK_5( IMX8QM_MIPI0_I2C1_CLK, "MIPI0_I2C1_CLK", 0, MIPI_DSI_0_LPCG + 0x2c, IMX8QM_MIPI0_I2C1_DIV ), + CLK_5( IMX8QM_MIPI0_I2C1_IPG_CLK, "MIPI0_I2C1_IPG", 0, MIPI_DSI_0_LPCG + 0x24, IMX8QM_MIPI0_I2C1_IPG_S_CLK), + CLK_5( IMX8QM_MIPI0_I2C1_IPG_S_CLK, "MIPI0_I2C1_IPG_S", 0, MIPI_DSI_0_LPCG + 0x28, IMX8QM_MIPI0_CLK_ROOT ), + CLK_5( IMX8QM_MIPI1_I2C0_CLK, "MIPI1_I2C0_CLK", 0, MIPI_DSI_1_LPCG + 0x1c, IMX8QM_MIPI1_I2C0_DIV ), + CLK_5( IMX8QM_MIPI1_I2C0_IPG_CLK, "MIPI1_I2C0_IPG", 0, MIPI_DSI_1_LPCG + 0x14, IMX8QM_MIPI1_I2C0_IPG_S_CLK), + CLK_5( IMX8QM_MIPI1_I2C0_IPG_S_CLK, "MIPI1_I2C0_IPG_S", 0, MIPI_DSI_1_LPCG + 0x18, IMX8QM_MIPI1_CLK_ROOT ), + CLK_5( IMX8QM_MIPI1_I2C1_CLK, "MIPI1_I2C1_CLK", 0, MIPI_DSI_1_LPCG + 0x2c, IMX8QM_MIPI1_I2C1_DIV ), + CLK_5( IMX8QM_MIPI1_I2C1_IPG_CLK, "MIPI1_I2C1_IPG", 0, MIPI_DSI_1_LPCG + 0x24, IMX8QM_MIPI1_I2C1_IPG_S_CLK), + CLK_5( IMX8QM_MIPI1_I2C1_IPG_S_CLK, "MIPI1_I2C1_IPG_S", 0, MIPI_DSI_1_LPCG + 0x28, IMX8QM_MIPI1_CLK_ROOT ), + + CLK_5( IMX8QM_CSI0_I2C0_CLK, "CSI0_I2C0_CLK", 0, MIPI_CSI_0_LPCG + 0x14, IMX8QM_CSI0_I2C0_DIV ), + CLK_5( IMX8QM_CSI0_I2C0_IPG_CLK, "CSI0_I2C0_IPG", 16, MIPI_CSI_0_LPCG + 0x14, IMX8QM_IPG_MIPI_CSI_CLK_ROOT ), + CLK_5( IMX8QM_CSI1_I2C0_CLK, "CSI1_I2C0_CLK", 0, MIPI_CSI_1_LPCG + 0x14, IMX8QM_CSI1_I2C0_DIV ), + CLK_5( IMX8QM_CSI1_I2C0_IPG_CLK, "CSI1_I2C0_IPG", 16, MIPI_CSI_1_LPCG + 0x14, IMX8QM_IPG_MIPI_CSI_CLK_ROOT ), + CLK_5( IMX8QM_HDMI_I2C0_CLK, "HDMI_I2C0_CLK", 0, DI_HDMI_LPCG, IMX8QM_HDMI_I2C0_DIV ), + CLK_5( IMX8QM_HDMI_I2C_IPG_CLK, "HDMI_I2C0_IPG", 16, DI_HDMI_LPCG, IMX8QM_HDMI_IPG_CLK ), + CLK_5( IMX8QM_HDMI_RX_I2C_DIV_CLK, "HDMI RX_I2C_DIV_CLK", 0, MIPI_DSI_0_LPCG + 0x14, IMX8QM_MIPI0_I2C0_DIV ), + CLK_5( IMX8QM_HDMI_RX_I2C0_CLK, "HDMI RX_I2C_CLK", 0, MIPI_DSI_0_LPCG + 0x10, IMX8QM_HDMI_RX_I2C_DIV_CLK ), + CLK_5( IMX8QM_HDMI_RX_I2C_IPG_CLK, "HDMI_RX_I2C_IPG", 0, RX_HDMI_LPCG + 0x18, IMX8QM_HDMI_RX_I2C_IPG_S_CLK), + CLK_5( IMX8QM_HDMI_RX_I2C_IPG_S_CLK, "HDMI_I2C_IPG_S", 0, RX_HDMI_LPCG + 0x1c, IMX8QM_HDMI_RX_IPG_CLK ), + + CLK_5( IMX8QM_UART0_CLK, "UART0_CLK", 0, LPUART_0_LPCG, IMX8QM_UART0_DIV ), + CLK_5( IMX8QM_UART0_IPG_CLK, "UART0_IPG", 16, LPUART_0_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QM_UART1_CLK, "UART1_CLK", 0, LPUART_1_LPCG, IMX8QM_UART1_DIV ), + CLK_5( IMX8QM_UART1_IPG_CLK, "UART1_IPG", 16, LPUART_1_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QM_UART2_CLK, "UART2_CLK", 0, LPUART_2_LPCG, IMX8QM_UART2_DIV ), + CLK_5( IMX8QM_UART2_IPG_CLK, "UART2_IPG", 16, LPUART_2_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QM_UART3_CLK, "UART3_CLK", 0, LPUART_3_LPCG, IMX8QM_UART3_DIV ), + CLK_5( IMX8QM_UART3_IPG_CLK, "UART3_IPG", 16, LPUART_3_LPCG, IMX8QM_IPG_DMA_CLK_ROOT ), + + CLK_5( IMX8QM_SDHC0_CLK, "SDHC0_CLK", 0, USDHC_0_LPCG, IMX8QM_SDHC0_DIV ), + CLK_5( IMX8QM_SDHC0_IPG_CLK, "SDHC0_IPG", 16, USDHC_0_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QM_SDHC0_AHB_CLK, "SDHC0_AHB", 20, USDHC_0_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ), + CLK_5( IMX8QM_SDHC1_CLK, "SDHC1_CLK", 0, USDHC_1_LPCG, IMX8QM_SDHC1_DIV ), + CLK_5( IMX8QM_SDHC1_IPG_CLK, "SDHC1_IPG", 16, USDHC_1_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QM_SDHC1_AHB_CLK, "SDHC1_AHB", 20, USDHC_1_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ), + CLK_5( IMX8QM_SDHC2_CLK, "SDHC2_CLK", 0, USDHC_2_LPCG, IMX8QM_SDHC2_DIV ), + CLK_5( IMX8QM_SDHC2_IPG_CLK, "SDHC2_IPG", 16, USDHC_2_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QM_SDHC2_AHB_CLK, "SDHC2_AHB", 20, USDHC_2_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ), + + CLK_5( IMX8QM_ENET0_IPG_S_CLK, "ENET0_IPG_S", 20, ENET_0_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QM_ENET0_IPG_CLK, "ENET0_IPG", 16, ENET_0_LPCG, IMX8QM_ENET0_IPG_S_CLK ), + CLK_5( IMX8QM_ENET0_AHB_CLK, "ENET0_AHB", 8, ENET_0_LPCG, IMX8QM_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8QM_ENET0_TX_CLK, "ENET0_TX", 4, ENET_0_LPCG, IMX8QM_ENET0_ROOT_DIV ), + CLK_5( IMX8QM_ENET0_PTP_CLK, "ENET0_PTP", 0, ENET_0_LPCG, IMX8QM_ENET0_ROOT_DIV ), + CLK_5( IMX8QM_ENET0_RGMII_TX_CLK, "ENET0_RGMII_TX", 12, ENET_0_LPCG, IMX8QM_ENET0_RMII_TX_SEL ), + CLK_5( IMX8QM_ENET0_RMII_RX_CLK, "ENET0_RMII_RX", 0, ENET_0_LPCG + 0x4, IMX8QM_ENET0_RGMII_DIV ), + + CLK_5( IMX8QM_ENET1_IPG_S_CLK, "ENET1_IPG_S", 20, ENET_1_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QM_ENET1_IPG_CLK, "ENET1_IPG", 16, ENET_1_LPCG, IMX8QM_ENET1_IPG_S_CLK ), + CLK_5( IMX8QM_ENET1_AHB_CLK, "ENET1_AHB", 8, ENET_1_LPCG, IMX8QM_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8QM_ENET1_TX_CLK, "ENET1_TX", 4, ENET_1_LPCG, IMX8QM_ENET1_ROOT_DIV ), + CLK_5( IMX8QM_ENET1_PTP_CLK, "ENET1_PTP", 0, ENET_1_LPCG, IMX8QM_ENET1_ROOT_DIV ), + CLK_5( IMX8QM_ENET1_RGMII_TX_CLK, "ENET1_RGMII_TX", 12, ENET_1_LPCG, IMX8QM_ENET1_RMII_TX_SEL ), + CLK_5( IMX8QM_ENET1_RMII_RX_CLK, "ENET1_RMII_RX", 0, ENET_1_LPCG + 0x4, IMX8QM_ENET1_RGMII_DIV ), + + CLK_5( IMX8QM_FSPI0_IPG_S_CLK, "FSPI0_IPG_S", 0x18, FSPI_0_LPCG, IMX8QM_LSIO_BUS_CLK ), + CLK_5( IMX8QM_FSPI0_IPG_CLK, "FSPI0_IPG", 0x14, FSPI_0_LPCG, IMX8QM_FSPI0_IPG_S_CLK ), + CLK_5( IMX8QM_FSPI0_HCLK, "FSPI0_HCLK", 0x10, FSPI_0_LPCG, IMX8QM_LSIO_MEM_CLK ), + CLK_5( IMX8QM_FSPI0_CLK, "FSPI0_CLK", 0, FSPI_0_LPCG, IMX8QM_FSPI0_DIV ), + + CLK_5( IMX8QM_USB2_OH_AHB_CLK, "USB2_OH_AHB", 24, USB_2_LPCG, IMX8QM_AHB_CONN_CLK_ROOT ), + CLK_5( IMX8QM_USB2_OH_IPG_S_CLK, "USB2_OH_IPG_S", 16, USB_2_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QM_USB2_OH_IPG_S_PL301_CLK, "USB2_OH_IPG_S_PL301", 20, USB_2_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QM_USB2_PHY_IPG_CLK, "USB2_PHY_IPG", 28, USB_2_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + + CLK_5( IMX8QM_USB3_IPG_CLK, "USB3_IPG", 16, USB_3_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QM_USB3_CORE_PCLK, "USB3_CORE", 20, USB_3_LPCG, IMX8QM_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QM_USB3_PHY_CLK, "USB3_PHY", 24, USB_3_LPCG, IMX8QM_USB3_IPG_CLK ), + CLK_5( IMX8QM_USB3_ACLK, "USB3_ACLK", 28, USB_3_LPCG, IMX8QM_USB3_ACLK_DIV ), + CLK_5( IMX8QM_USB3_BUS_CLK, "USB3_BUS", 0, USB_3_LPCG, IMX8QM_USB3_BUS_DIV ), + CLK_5( IMX8QM_USB3_LPM_CLK, "USB3_LPM", 4, USB_3_LPCG, IMX8QM_USB3_LPM_DIV ), + + CLK_5( IMX8QM_GPMI_APB_CLK, "GPMI_APB", 16, NAND_LPCG, IMX8QM_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8QM_GPMI_APB_BCH_CLK, "GPMI_APB_BCH", 20, NAND_LPCG, IMX8QM_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8QM_GPMI_BCH_IO_CLK, "GPMI_IO_CLK", 4, NAND_LPCG, IMX8QM_GPMI_BCH_IO_DIV ), + CLK_5( IMX8QM_GPMI_BCH_CLK, "GPMI_BCH_CLK", 0, NAND_LPCG, IMX8QM_GPMI_BCH_DIV ), + CLK_5( IMX8QM_APBHDMA_CLK, "GPMI_CLK", 16, NAND_LPCG + 0x4, IMX8QM_AXI_CONN_CLK_ROOT ), + + CLK_5( IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK, "HSIO_PCIE_A_MSTR_AXI_CLK", 16, HSIO_PCIE_X2_LPCG, IMX8QM_HSIO_AXI_CLK ), + CLK_5( IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK, "HSIO_PCIE_A_SLV_AXI_CLK", 20, HSIO_PCIE_X2_LPCG, IMX8QM_HSIO_AXI_CLK ), + CLK_5( IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK, "HSIO_PCIE_A_DBI_AXI_CLK", 24, HSIO_PCIE_X2_LPCG, IMX8QM_HSIO_AXI_CLK ), + CLK_5( IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK, "HSIO_PCIE_B_MSTR_AXI_CLK", 16, HSIO_PCIE_X1_LPCG, IMX8QM_HSIO_AXI_CLK ), + CLK_5( IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK, "HSIO_PCIE_B_SLV_AXI_CLK", 20, HSIO_PCIE_X1_LPCG, IMX8QM_HSIO_AXI_CLK ), + CLK_5( IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK, "HSIO_PCIE_B_DBI_AXI_CLK", 24, HSIO_PCIE_X1_LPCG, IMX8QM_HSIO_AXI_CLK ), + CLK_5( IMX8QM_HSIO_PCIE_X1_PER_CLK, "HSIO_PCIE_X1_PER_CLK", 16, HSIO_PCIE_X1_CRR3_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_PCIE_X2_PER_CLK, "HSIO_PCIE_X2_PER_CLK", 16, HSIO_PCIE_X2_CRR2_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_SATA_PER_CLK, "HSIO_SATA_PER_CLK", 16, HSIO_SATA_CRR4_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_PHY_X1_PER_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_PHY_X1_CRR1_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_PHY_X2_PER_CLK, "HSIO_PHY_X2_PER_CLK", 16, HSIO_PHY_X2_CRR0_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_MISC_PER_CLK, "HSIO_MISC_PER_CLK", 16, HSIO_MISC_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_PHY_X1_APB_CLK, "HSIO_PHY_X1_APB_CLK", 16, HSIO_PHY_X1_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_PHY_X2_APB_0_CLK, "HSIO_PHY_X2_APB_0_CLK", 16, HSIO_PHY_X2_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_PHY_X2_APB_1_CLK, "HSIO_PHY_X2_APB_1_CLK", 20, HSIO_PHY_X2_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_SATA_CLK, "HSIO_SATA_CLK", 16, HSIO_SATA_LPCG, IMX8QM_HSIO_AXI_CLK ), + CLK_5( IMX8QM_HSIO_GPIO_CLK, "HSIO_GPIO_CLK", 16, HSIO_GPIO_LPCG, IMX8QM_HSIO_PER_CLK ), + CLK_5( IMX8QM_HSIO_PHY_X1_PCLK, "HSIO_PHY_X1_PCLK", 0, HSIO_PHY_X1_LPCG, 0 ), + CLK_5( IMX8QM_HSIO_PHY_X2_PCLK_0, "HSIO_PHY_X2_PCLK_0", 0, HSIO_PHY_X2_LPCG, 0 ), + CLK_5( IMX8QM_HSIO_PHY_X2_PCLK_1, "HSIO_PHY_X2_PCLK_1", 4, HSIO_PHY_X2_LPCG, 0 ), + CLK_5( IMX8QM_HSIO_SATA_EPCS_RX_CLK, "HSIO_SATA_EPCS_RX_CLK", 8, HSIO_PHY_X1_LPCG, 0 ), + CLK_5( IMX8QM_HSIO_SATA_EPCS_TX_CLK, "HSIO_SATA_EPCS_TX_CLK", 4, HSIO_PHY_X1_LPCG, 0 ), +}; - ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0); - if (ret) { - printf("%s err %d\n", __func__, ret); - return ret; - } +struct imx8_mux_clks imx8qm_mux_clks[] = { +}; - return 0; -} +struct imx8_clks_collect imx8qm_clk_collect = { + { + {&imx8qm_clks, ARRAY_SIZE(imx8qm_clks)}, + {&imx8qm_fixed_clks, ARRAY_SIZE(imx8qm_fixed_clks)}, + {&imx8qm_gpr_clks, ARRAY_SIZE(imx8qm_gpr_clks)}, + {&imx8qm_lpcg_clks, ARRAY_SIZE(imx8qm_lpcg_clks)}, + {&imx8qm_mux_clks, ARRAY_SIZE(imx8qm_mux_clks)}, + }, + FLAG_CLK_IMX8_IMX8QM, +}; diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c index e6b2fb40da2..8319658abf7 100644 --- a/drivers/clk/imx/clk-imx8qxp.c +++ b/drivers/clk/imx/clk-imx8qxp.c @@ -13,312 +13,215 @@ #include #include #include +#include #include "clk-imx8.h" -#if CONFIG_IS_ENABLED(CMD_CLK) -struct imx8_clks imx8_clk_names[] = { - { IMX8QXP_A35_DIV, "A35_DIV" }, - { IMX8QXP_I2C0_CLK, "I2C0" }, - { IMX8QXP_I2C1_CLK, "I2C1" }, - { IMX8QXP_I2C2_CLK, "I2C2" }, - { IMX8QXP_I2C3_CLK, "I2C3" }, - { IMX8QXP_UART0_CLK, "UART0" }, - { IMX8QXP_UART1_CLK, "UART1" }, - { IMX8QXP_UART2_CLK, "UART2" }, - { IMX8QXP_UART3_CLK, "UART3" }, - { IMX8QXP_SDHC0_CLK, "SDHC0" }, - { IMX8QXP_SDHC1_CLK, "SDHC1" }, - { IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" }, - { IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" }, - { IMX8QXP_ENET0_REF_DIV, "ENET0_REF" }, - { IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" }, - { IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" }, - { IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" }, - { IMX8QXP_ENET1_REF_DIV, "ENET1_REF" }, - { IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" }, +static struct imx8_clks imx8qxp_clks[] = { + CLK_4( IMX8QXP_A35_DIV, "A35_DIV", SC_R_A35, SC_PM_CLK_CPU ), + CLK_4( IMX8QXP_I2C0_DIV, "I2C0_DIV", SC_R_I2C_0, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_I2C1_DIV, "I2C1_DIV", SC_R_I2C_1, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_I2C2_DIV, "I2C2_DIV", SC_R_I2C_2, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_I2C3_DIV, "I2C3_DIV", SC_R_I2C_3, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_MIPI0_I2C0_DIV, "MIPI0 I2C0_DIV", SC_R_MIPI_0_I2C_0, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QXP_MIPI0_I2C1_DIV, "MIPI0 I2C1_DIV", SC_R_MIPI_0_I2C_1, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QXP_MIPI1_I2C0_DIV, "MIPI1 I2C0_DIV", SC_R_MIPI_1_I2C_0, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QXP_MIPI1_I2C1_DIV, "MIPI1 I2C1_DIV", SC_R_MIPI_1_I2C_1, SC_PM_CLK_MISC2 ), + CLK_4( IMX8QXP_CSI0_I2C0_DIV, "CSI0 I2C0_DIV", SC_R_CSI_0_I2C_0, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_SPI0_DIV, "SPI0_DIV", SC_R_SPI_0, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_SPI1_DIV, "SPI1_DIV", SC_R_SPI_1, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_SPI2_DIV, "SPI2_DIV", SC_R_SPI_2, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_SPI3_DIV, "SPI3_DIV", SC_R_SPI_3, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_UART0_DIV, "UART0_DIV", SC_R_UART_0, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_UART1_DIV, "UART1_DIV", SC_R_UART_1, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_UART2_DIV, "UART2_DIV", SC_R_UART_2, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_UART3_DIV, "UART3_DIV", SC_R_UART_3, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_SDHC0_DIV, "SDHC0_DIV", SC_R_SDHC_0, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_SDHC1_DIV, "SDHC1_DIV", SC_R_SDHC_1, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_SDHC2_DIV, "SDHC2_DIV", SC_R_SDHC_2, SC_PM_CLK_PER ), +#if !defined(CONFIG_IMX8DXL) + CLK_4( IMX8QXP_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_R_ENET_0, SC_PM_CLK_PER ), +#endif + CLK_4( IMX8QXP_ENET0_RGMII_DIV, "ENET0_RGMII_DIV", SC_R_ENET_0, SC_PM_CLK_MISC0 ), + CLK_4( IMX8QXP_ENET1_ROOT_DIV, "ENET1_ROOT_DIV", SC_R_ENET_1, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_ENET1_RGMII_DIV, "ENET1_RGMII_DIV", SC_R_ENET_1, SC_PM_CLK_MISC0 ), + CLK_4( IMX8QXP_USB3_ACLK_DIV, "USB3_ACLK_DIV", SC_R_USB_2, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_USB3_BUS_DIV, "USB3_BUS_DIV", SC_R_USB_2, SC_PM_CLK_MST_BUS ), + CLK_4( IMX8QXP_USB3_LPM_DIV, "USB3_LPM_DIV", SC_R_USB_2, SC_PM_CLK_MISC ), + CLK_4( IMX8QXP_LSIO_FSPI0_DIV, "FSPI0_DIV", SC_R_FSPI_0, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_GPMI_BCH_IO_DIV, "GPMI_IO_DIV", SC_R_NAND, SC_PM_CLK_MST_BUS ), + CLK_4( IMX8QXP_GPMI_BCH_DIV, "GPMI_BCH_DIV", SC_R_NAND, SC_PM_CLK_PER ), + + CLK_4( IMX8QXP_ELCDIF_PLL_DIV, "ELCDIF_PLL_DIV", SC_R_ELCDIF_PLL, SC_PM_CLK_PLL ), + CLK_4( IMX8QXP_LCD_PXL_DIV, "LCD_PXL_DIV", SC_R_LCD_0, SC_PM_CLK_MISC0 ), + CLK_4( IMX8QXP_LCD_DIV, "LCD_DIV", SC_R_LCD_0, SC_PM_CLK_PER ), + CLK_4( IMX8QXP_LCD_PXL_BYPASS_DIV, "LCD_PXL_BYPASS_DIV", SC_R_LCD_0, SC_PM_CLK_BYPASS ), }; -int num_clks = ARRAY_SIZE(imx8_clk_names); +static struct imx8_fixed_clks imx8qxp_fixed_clks[] = { + CLK_3( IMX8QXP_IPG_CONN_CLK_ROOT, "IPG_CONN_CLK", SC_83MHZ ), + CLK_3( IMX8QXP_AHB_CONN_CLK_ROOT, "AHB_CONN_CLK", SC_166MHZ ), + CLK_3( IMX8QXP_AXI_CONN_CLK_ROOT, "AXI_CONN_CLK", SC_333MHZ ), + CLK_3( IMX8QXP_IPG_DMA_CLK_ROOT, "IPG_DMA_CLK", SC_120MHZ ), + CLK_3( IMX8QXP_MIPI_IPG_CLK, "IPG_MIPI_CLK", SC_120MHZ ), + CLK_3( IMX8QXP_LSIO_BUS_CLK, "LSIO_BUS_CLK", SC_100MHZ ), + CLK_3( IMX8QXP_LSIO_MEM_CLK, "LSIO_MEM_CLK", SC_200MHZ ), + CLK_3( IMX8QXP_HSIO_PER_CLK, "HSIO_CLK", SC_133MHZ ), + CLK_3( IMX8QXP_HSIO_AXI_CLK, "HSIO_AXI", SC_400MHZ ), +#if defined(CONFIG_IMX8DXL) + CLK_3( IMX8QXP_ENET0_ROOT_DIV, "ENET0_ROOT_DIV", SC_250MHZ ), #endif +}; -ulong imx8_clk_get_rate(struct clk *clk) -{ - sc_pm_clk_t pm_clk; - ulong rate; - u16 resource; - int ret; - - debug("%s(#%lu)\n", __func__, clk->id); - - switch (clk->id) { - case IMX8QXP_A35_DIV: - resource = SC_R_A35; - pm_clk = SC_PM_CLK_CPU; - break; - case IMX8QXP_I2C0_CLK: - case IMX8QXP_I2C0_IPG_CLK: - resource = SC_R_I2C_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C1_CLK: - case IMX8QXP_I2C1_IPG_CLK: - resource = SC_R_I2C_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C2_CLK: - case IMX8QXP_I2C2_IPG_CLK: - resource = SC_R_I2C_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C3_CLK: - case IMX8QXP_I2C3_IPG_CLK: - resource = SC_R_I2C_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC0_IPG_CLK: - case IMX8QXP_SDHC0_CLK: - case IMX8QXP_SDHC0_DIV: - resource = SC_R_SDHC_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC1_IPG_CLK: - case IMX8QXP_SDHC1_CLK: - case IMX8QXP_SDHC1_DIV: - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART0_IPG_CLK: - case IMX8QXP_UART0_CLK: - resource = SC_R_UART_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART1_CLK: - resource = SC_R_UART_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART2_CLK: - resource = SC_R_UART_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART3_CLK: - resource = SC_R_UART_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET0_IPG_CLK: - case IMX8QXP_ENET0_AHB_CLK: - case IMX8QXP_ENET0_REF_DIV: - case IMX8QXP_ENET0_PTP_CLK: - resource = SC_R_ENET_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET1_IPG_CLK: - case IMX8QXP_ENET1_AHB_CLK: - case IMX8QXP_ENET1_REF_DIV: - case IMX8QXP_ENET1_PTP_CLK: - resource = SC_R_ENET_1; - pm_clk = SC_PM_CLK_PER; - break; - default: - if (clk->id < IMX8QXP_UART0_IPG_CLK || - clk->id >= IMX8QXP_CLK_END) { - printf("%s(Invalid clk ID #%lu)\n", - __func__, clk->id); - return -EINVAL; - } - return -ENOTSUPP; - }; - - ret = sc_pm_get_clock_rate(-1, resource, pm_clk, - (sc_pm_clock_rate_t *)&rate); - if (ret) { - printf("%s err %d\n", __func__, ret); - return ret; - } - - return rate; -} - -ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) -{ - sc_pm_clk_t pm_clk; - u32 new_rate = rate; - u16 resource; - int ret; - - debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate); - - switch (clk->id) { - case IMX8QXP_I2C0_CLK: - case IMX8QXP_I2C0_IPG_CLK: - resource = SC_R_I2C_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C1_CLK: - case IMX8QXP_I2C1_IPG_CLK: - resource = SC_R_I2C_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C2_CLK: - case IMX8QXP_I2C2_IPG_CLK: - resource = SC_R_I2C_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C3_CLK: - case IMX8QXP_I2C3_IPG_CLK: - resource = SC_R_I2C_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART0_CLK: - resource = SC_R_UART_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART1_CLK: - resource = SC_R_UART_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART2_CLK: - resource = SC_R_UART_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART3_CLK: - resource = SC_R_UART_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC0_IPG_CLK: - case IMX8QXP_SDHC0_CLK: - case IMX8QXP_SDHC0_DIV: - resource = SC_R_SDHC_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC1_SEL: - case IMX8QXP_SDHC0_SEL: - return 0; - case IMX8QXP_SDHC1_IPG_CLK: - case IMX8QXP_SDHC1_CLK: - case IMX8QXP_SDHC1_DIV: - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET0_IPG_CLK: - case IMX8QXP_ENET0_AHB_CLK: - case IMX8QXP_ENET0_REF_DIV: - case IMX8QXP_ENET0_PTP_CLK: - resource = SC_R_ENET_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET1_IPG_CLK: - case IMX8QXP_ENET1_AHB_CLK: - case IMX8QXP_ENET1_REF_DIV: - case IMX8QXP_ENET1_PTP_CLK: - resource = SC_R_ENET_1; - pm_clk = SC_PM_CLK_PER; - break; - default: - if (clk->id < IMX8QXP_UART0_IPG_CLK || - clk->id >= IMX8QXP_CLK_END) { - printf("%s(Invalid clk ID #%lu)\n", - __func__, clk->id); - return -EINVAL; - } - return -ENOTSUPP; - }; +static struct imx8_gpr_clks imx8qxp_gpr_clks[] = { + CLK_5( IMX8QXP_ENET0_REF_DIV, "ENET0_REF_DIV", SC_R_ENET_0, SC_C_CLKDIV, IMX8QXP_ENET0_ROOT_DIV ), + CLK_4( IMX8QXP_ENET0_REF_25MHZ_125MHZ_SEL, "ENET0_REF_25_125", SC_R_ENET_0, SC_C_SEL_125 ), + CLK_4( IMX8QXP_ENET0_RMII_TX_SEL, "ENET0_RMII_TX", SC_R_ENET_0, SC_C_TXCLK ), + CLK_4( IMX8QXP_ENET0_REF_25MHZ_125MHZ_CLK, "ENET0_REF_25_125_CLK", SC_R_ENET_0, SC_C_DISABLE_125 ), + CLK_4( IMX8QXP_ENET0_REF_50MHZ_CLK, "ENET0_REF_50", SC_R_ENET_0, SC_C_DISABLE_50 ), + + CLK_5( IMX8QXP_ENET1_REF_DIV, "ENET1_REF_DIV", SC_R_ENET_1, SC_C_CLKDIV, IMX8QXP_ENET1_ROOT_DIV ), + CLK_4( IMX8QXP_ENET1_REF_25MHZ_125MHZ_SEL, "ENET1_REF_25_125", SC_R_ENET_1, SC_C_SEL_125 ), + CLK_4( IMX8QXP_ENET1_RMII_TX_SEL, "ENET1_RMII_TX", SC_R_ENET_1, SC_C_TXCLK ), + CLK_4( IMX8QXP_ENET1_REF_25MHZ_125MHZ_CLK, "ENET1_REF_25_125_CLK", SC_R_ENET_1, SC_C_DISABLE_125 ), + CLK_4( IMX8QXP_ENET1_REF_50MHZ_CLK, "ENET1_REF_50", SC_R_ENET_1, SC_C_DISABLE_50 ), +}; - ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate); - if (ret) { - printf("%s err %d\n", __func__, ret); - return ret; - } +static struct imx8_lpcg_clks imx8qxp_lpcg_clks[] = { + CLK_5( IMX8QXP_I2C0_CLK, "I2C0_CLK", 0, LPI2C_0_LPCG, IMX8QXP_I2C0_DIV ), + CLK_5( IMX8QXP_I2C0_IPG_CLK, "I2C0_IPG", 16, LPI2C_0_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_I2C1_CLK, "I2C1_CLK", 0, LPI2C_1_LPCG, IMX8QXP_I2C1_DIV ), + CLK_5( IMX8QXP_I2C1_IPG_CLK, "I2C1_IPG", 16, LPI2C_1_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_I2C2_CLK, "I2C2_CLK", 0, LPI2C_2_LPCG, IMX8QXP_I2C2_DIV ), + CLK_5( IMX8QXP_I2C2_IPG_CLK, "I2C2_IPG", 16, LPI2C_2_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_I2C3_CLK, "I2C3_CLK", 0, LPI2C_3_LPCG, IMX8QXP_I2C3_DIV ), + CLK_5( IMX8QXP_I2C3_IPG_CLK, "I2C3_IPG", 16, LPI2C_3_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_MIPI0_I2C0_CLK, "MIPI0_I2C0_CLK", 0, DI_MIPI0_LPCG + 0x10, IMX8QXP_MIPI0_I2C0_DIV ), + CLK_5( IMX8QXP_MIPI0_I2C0_IPG_CLK, "MIPI0_I2C0_IPG", 16, DI_MIPI0_LPCG + 0x10, IMX8QXP_MIPI_IPG_CLK ), + CLK_5( IMX8QXP_MIPI0_I2C1_CLK, "MIPI0_I2C1_CLK", 0, DI_MIPI0_LPCG + 0x14, IMX8QXP_MIPI0_I2C1_DIV ), + CLK_5( IMX8QXP_MIPI0_I2C1_IPG_CLK, "MIPI0_I2C1_IPG", 16, DI_MIPI0_LPCG + 0x14, IMX8QXP_MIPI_IPG_CLK ), + CLK_5( IMX8QXP_MIPI1_I2C0_CLK, "MIPI1_I2C0_CLK", 0, DI_MIPI1_LPCG + 0x10, IMX8QXP_MIPI1_I2C0_DIV ), + CLK_5( IMX8QXP_MIPI1_I2C0_IPG_CLK, "MIPI1_I2C0_IPG", 16, DI_MIPI1_LPCG + 0x10, IMX8QXP_MIPI_IPG_CLK ), + CLK_5( IMX8QXP_MIPI1_I2C1_CLK, "MIPI1_I2C1_CLK", 0, DI_MIPI1_LPCG + 0x14, IMX8QXP_MIPI1_I2C1_DIV ), + CLK_5( IMX8QXP_MIPI1_I2C1_IPG_CLK, "MIPI1_I2C1_IPG", 16, DI_MIPI1_LPCG + 0x14, IMX8QXP_MIPI_IPG_CLK ), + CLK_5( IMX8QXP_CSI0_I2C0_CLK, "CSI0_I2C0_CLK", 0, MIPI_CSI_0_LPCG + 0x14, IMX8QXP_CSI0_I2C0_DIV ), + CLK_5( IMX8QXP_CSI0_I2C0_IPG_CLK, "CSI0_I2C0_IPG", 16, MIPI_CSI_0_LPCG + 0x14, IMX8QXP_MIPI_IPG_CLK ), + + CLK_5( IMX8QXP_SPI0_CLK, "SPI0_CLK", 0, LPSPI_0_LPCG, IMX8QXP_SPI0_DIV ), + CLK_5( IMX8QXP_SPI0_IPG_CLK, "SPI0_IPG", 16, LPSPI_0_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_SPI1_CLK, "SPI1_CLK", 0, LPSPI_1_LPCG, IMX8QXP_SPI1_DIV ), + CLK_5( IMX8QXP_SPI1_IPG_CLK, "SPI1_IPG", 16, LPSPI_1_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_SPI2_CLK, "SPI2_CLK", 0, LPSPI_2_LPCG, IMX8QXP_SPI2_DIV ), + CLK_5( IMX8QXP_SPI2_IPG_CLK, "SPI2_IPG", 16, LPSPI_2_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_SPI3_CLK, "SPI3_CLK", 0, LPSPI_3_LPCG, IMX8QXP_SPI3_DIV ), + CLK_5( IMX8QXP_SPI3_IPG_CLK, "SPI3_IPG", 16, LPSPI_3_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + + CLK_5( IMX8QXP_UART0_CLK, "UART0_CLK", 0, LPUART_0_LPCG, IMX8QXP_UART0_DIV ), + CLK_5( IMX8QXP_UART0_IPG_CLK, "UART0_IPG", 16, LPUART_0_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_UART1_CLK, "UART1_CLK", 0, LPUART_1_LPCG, IMX8QXP_UART1_DIV ), + CLK_5( IMX8QXP_UART1_IPG_CLK, "UART1_IPG", 16, LPUART_1_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_UART2_CLK, "UART2_CLK", 0, LPUART_2_LPCG, IMX8QXP_UART2_DIV ), + CLK_5( IMX8QXP_UART2_IPG_CLK, "UART2_IPG", 16, LPUART_2_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + CLK_5( IMX8QXP_UART3_CLK, "UART3_CLK", 0, LPUART_3_LPCG, IMX8QXP_UART3_DIV ), + CLK_5( IMX8QXP_UART3_IPG_CLK, "UART3_IPG", 16, LPUART_3_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), + + CLK_5( IMX8QXP_SDHC0_CLK, "SDHC0_CLK", 0, USDHC_0_LPCG, IMX8QXP_SDHC0_DIV ), + CLK_5( IMX8QXP_SDHC0_IPG_CLK, "SDHC0_IPG", 16, USDHC_0_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_SDHC0_AHB_CLK, "SDHC0_AHB", 20, USDHC_0_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_SDHC1_CLK, "SDHC1_CLK", 0, USDHC_1_LPCG, IMX8QXP_SDHC1_DIV ), + CLK_5( IMX8QXP_SDHC1_IPG_CLK, "SDHC1_IPG", 16, USDHC_1_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_SDHC1_AHB_CLK, "SDHC1_AHB", 20, USDHC_1_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_SDHC2_CLK, "SDHC2_CLK", 0, USDHC_2_LPCG, IMX8QXP_SDHC2_DIV ), + CLK_5( IMX8QXP_SDHC2_IPG_CLK, "SDHC2_IPG", 16, USDHC_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_SDHC2_AHB_CLK, "SDHC2_AHB", 20, USDHC_2_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ), + + CLK_5( IMX8QXP_ENET0_IPG_S_CLK, "ENET0_IPG_S", 20, ENET_0_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG", 16, ENET_0_LPCG, IMX8QXP_ENET0_IPG_S_CLK ), + CLK_5( IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB", 8, ENET_0_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_ENET0_TX_CLK, "ENET0_TX", 4, ENET_0_LPCG, IMX8QXP_ENET0_ROOT_DIV ), + CLK_5( IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP", 0, ENET_0_LPCG, IMX8QXP_ENET0_ROOT_DIV ), + CLK_5( IMX8QXP_ENET0_RGMII_TX_CLK, "ENET0_RGMII_TX", 12, ENET_0_LPCG, IMX8QXP_ENET0_RMII_TX_SEL ), + CLK_5( IMX8QXP_ENET0_RMII_RX_CLK, "ENET0_RMII_RX", 0, ENET_0_LPCG + 0x4, IMX8QXP_ENET0_RGMII_DIV ), + + CLK_5( IMX8QXP_ENET1_IPG_S_CLK, "ENET1_IPG_S", 20, ENET_1_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG", 16, ENET_1_LPCG, IMX8QXP_ENET1_IPG_S_CLK ), + CLK_5( IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB", 8, ENET_1_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_ENET1_TX_CLK, "ENET1_TX", 4, ENET_1_LPCG, IMX8QXP_ENET1_ROOT_DIV ), + CLK_5( IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP", 0, ENET_1_LPCG, IMX8QXP_ENET1_ROOT_DIV ), + CLK_5( IMX8QXP_ENET1_RGMII_TX_CLK, "ENET1_RGMII_TX", 12, ENET_1_LPCG, IMX8QXP_ENET1_RMII_TX_SEL ), + CLK_5( IMX8QXP_ENET1_RMII_RX_CLK, "ENET1_RMII_RX", 0, ENET_1_LPCG + 0x4, IMX8QXP_ENET1_RGMII_DIV ), + +#if defined(CONFIG_IMX8DXL) + CLK_5( IMX8DXL_EQOS_MEM_CLK, "EQOS_MEM_CLK", 8, ENET_1_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8DXL_EQOS_ACLK, "EQOS_ACLK", 16, ENET_1_LPCG, IMX8DXL_EQOS_MEM_CLK ), + CLK_5( IMX8DXL_EQOS_CSR_CLK, "EQOS_CSR_CLK", 24, ENET_1_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8DXL_EQOS_CLK, "EQOS_CLK", 20, ENET_1_LPCG, IMX8QXP_ENET1_ROOT_DIV ), + CLK_5( IMX8DXL_EQOS_PTP_CLK_S, "EQOS_PTP_S", 8, ENET_1_LPCG, IMX8QXP_ENET0_ROOT_DIV ), + CLK_5( IMX8DXL_EQOS_PTP_CLK, "EQOS_PTP", 0, ENET_1_LPCG, IMX8DXL_EQOS_PTP_CLK_S ), +#endif - return new_rate; -} + CLK_5( IMX8QXP_LSIO_FSPI0_IPG_S_CLK, "FSPI0_IPG_S", 0x18, FSPI_0_LPCG, IMX8QXP_LSIO_BUS_CLK ), + CLK_5( IMX8QXP_LSIO_FSPI0_IPG_CLK, "FSPI0_IPG", 0x14, FSPI_0_LPCG, IMX8QXP_LSIO_FSPI0_IPG_S_CLK ), + CLK_5( IMX8QXP_LSIO_FSPI0_HCLK, "FSPI0_HCLK", 0x10, FSPI_0_LPCG, IMX8QXP_LSIO_MEM_CLK ), + CLK_5( IMX8QXP_LSIO_FSPI0_CLK, "FSPI0_CLK", 0, FSPI_0_LPCG, IMX8QXP_LSIO_FSPI0_DIV ), -int __imx8_clk_enable(struct clk *clk, bool enable) -{ - sc_pm_clk_t pm_clk; - u16 resource; - int ret; +#if !defined(CONFIG_IMX8DXL) + CLK_5( IMX8QXP_USB2_OH_AHB_CLK, "USB2_OH_AHB", 24, USB_2_LPCG, IMX8QXP_AHB_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_USB2_OH_IPG_S_CLK, "USB2_OH_IPG_S", 16, USB_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_USB2_OH_IPG_S_PL301_CLK, "USB2_OH_IPG_S_PL301", 20, USB_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), +#endif + CLK_5( IMX8QXP_USB2_PHY_IPG_CLK, "USB2_PHY_IPG", 28, USB_2_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), - debug("%s(#%lu)\n", __func__, clk->id); + CLK_5( IMX8QXP_USB3_IPG_CLK, "USB3_IPG", 16, USB_3_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_USB3_CORE_PCLK, "USB3_CORE", 20, USB_3_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_USB3_PHY_CLK, "USB3_PHY", 24, USB_3_LPCG, IMX8QXP_USB3_IPG_CLK ), - switch (clk->id) { - case IMX8QXP_I2C0_CLK: - case IMX8QXP_I2C0_IPG_CLK: - resource = SC_R_I2C_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C1_CLK: - case IMX8QXP_I2C1_IPG_CLK: - resource = SC_R_I2C_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C2_CLK: - case IMX8QXP_I2C2_IPG_CLK: - resource = SC_R_I2C_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_I2C3_CLK: - case IMX8QXP_I2C3_IPG_CLK: - resource = SC_R_I2C_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART0_CLK: - resource = SC_R_UART_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART1_CLK: - resource = SC_R_UART_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART2_CLK: - resource = SC_R_UART_2; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_UART3_CLK: - resource = SC_R_UART_3; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC0_IPG_CLK: - case IMX8QXP_SDHC0_CLK: - case IMX8QXP_SDHC0_DIV: - resource = SC_R_SDHC_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_SDHC1_IPG_CLK: - case IMX8QXP_SDHC1_CLK: - case IMX8QXP_SDHC1_DIV: - resource = SC_R_SDHC_1; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET0_IPG_CLK: - case IMX8QXP_ENET0_AHB_CLK: - case IMX8QXP_ENET0_REF_DIV: - case IMX8QXP_ENET0_PTP_CLK: - resource = SC_R_ENET_0; - pm_clk = SC_PM_CLK_PER; - break; - case IMX8QXP_ENET1_IPG_CLK: - case IMX8QXP_ENET1_AHB_CLK: - case IMX8QXP_ENET1_REF_DIV: - case IMX8QXP_ENET1_PTP_CLK: - resource = SC_R_ENET_1; - pm_clk = SC_PM_CLK_PER; - break; - default: - if (clk->id < IMX8QXP_UART0_IPG_CLK || - clk->id >= IMX8QXP_CLK_END) { - printf("%s(Invalid clk ID #%lu)\n", - __func__, clk->id); - return -EINVAL; - } - return -ENOTSUPP; - } +#if defined(CONFIG_IMX8DXL) + CLK_5( IMX8DXL_USB2_PHY2_IPG_CLK, "USB3_ACLK", 28, USB_3_LPCG, IMX8QXP_IPG_CONN_CLK_ROOT ), +#endif + CLK_5( IMX8QXP_USB3_ACLK, "USB3_ACLK", 28, USB_3_LPCG, IMX8QXP_USB3_ACLK_DIV ), + CLK_5( IMX8QXP_USB3_BUS_CLK, "USB3_BUS", 0, USB_3_LPCG, IMX8QXP_USB3_BUS_DIV ), + CLK_5( IMX8QXP_USB3_LPM_CLK, "USB3_LPM", 4, USB_3_LPCG, IMX8QXP_USB3_LPM_DIV ), + + CLK_5( IMX8QXP_GPMI_APB_CLK, "GPMI_APB", 16, NAND_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_GPMI_APB_BCH_CLK, "GPMI_APB_BCH", 20, NAND_LPCG, IMX8QXP_AXI_CONN_CLK_ROOT ), + CLK_5( IMX8QXP_GPMI_BCH_IO_CLK, "GPMI_IO_CLK", 4, NAND_LPCG, IMX8QXP_GPMI_BCH_IO_DIV ), + CLK_5( IMX8QXP_GPMI_BCH_CLK, "GPMI_BCH_CLK", 0, NAND_LPCG, IMX8QXP_GPMI_BCH_DIV ), + CLK_5( IMX8QXP_APBHDMA_CLK, "GPMI_CLK", 16, NAND_LPCG + 0x4, IMX8QXP_AXI_CONN_CLK_ROOT ), + + CLK_5( IMX8QXP_HSIO_PCIE_MSTR_AXI_CLK, "HSIO_PCIE_A_MSTR_AXI_CLK", 16, HSIO_PCIE_X1_LPCG, IMX8QXP_HSIO_AXI_CLK ), + CLK_5( IMX8QXP_HSIO_PCIE_SLV_AXI_CLK, "HSIO_PCIE_A_SLV_AXI_CLK", 20, HSIO_PCIE_X1_LPCG, IMX8QXP_HSIO_AXI_CLK ), + CLK_5( IMX8QXP_HSIO_PCIE_DBI_AXI_CLK, "HSIO_PCIE_A_DBI_AXI_CLK", 24, HSIO_PCIE_X1_LPCG, IMX8QXP_HSIO_AXI_CLK ), + CLK_5( IMX8QXP_HSIO_PCIE_X1_PER_CLK, "HSIO_PCIE_X1_PER_CLK", 16, HSIO_PCIE_X1_CRR3_LPCG, IMX8QXP_HSIO_PER_CLK ), + CLK_5( IMX8QXP_HSIO_PHY_X1_PER_CLK, "HSIO_PHY_X1_PER_CLK", 16, HSIO_PHY_X1_CRR1_LPCG, IMX8QXP_HSIO_PER_CLK ), + CLK_5( IMX8QXP_HSIO_MISC_PER_CLK, "HSIO_MISC_PER_CLK", 16, HSIO_MISC_LPCG, IMX8QXP_HSIO_PER_CLK ), + CLK_5( IMX8QXP_HSIO_PHY_X1_APB_CLK, "HSIO_PHY_X1_APB_CLK", 16, HSIO_PHY_X1_LPCG, IMX8QXP_HSIO_PER_CLK ), + CLK_5( IMX8QXP_HSIO_GPIO_CLK, "HSIO_GPIO_CLK", 16, HSIO_GPIO_LPCG, IMX8QXP_HSIO_PER_CLK ), + CLK_5( IMX8QXP_HSIO_PHY_X1_PCLK, "HSIO_PHY_X1_PCLK", 0, HSIO_PHY_X1_LPCG, 0 ), + CLK_5( IMX8QXP_LCD_IPG_CLK, "LCD_IPG_CLK", 16, LCD_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ), +}; - ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0); - if (ret) { - printf("%s err %d\n", __func__, ret); - return ret; - } +struct imx8_mux_clks imx8qxp_mux_clks[] = { + CLK_MUX( IMX8QXP_SDHC0_SEL, "SDHC0_SEL", IMX8QXP_SDHC0_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CONN_PLL0_CLK, + IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ), + CLK_MUX( IMX8QXP_SDHC1_SEL, "SDHC1_SEL", IMX8QXP_SDHC1_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CONN_PLL0_CLK, + IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ), + CLK_MUX( IMX8QXP_SDHC2_SEL, "SDHC2_SEL", IMX8QXP_SDHC2_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CONN_PLL0_CLK, + IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ), + + CLK_MUX( IMX8QXP_LCD_PXL_SEL, "LCD_PXL_SEL", IMX8QXP_LCD_PXL_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, + IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, IMX8QXP_LCD_PXL_BYPASS_DIV ), + CLK_MUX( IMX8QXP_LCD_SEL, "LCD_SEL", IMX8QXP_LCD_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, + IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, IMX8QXP_ELCDIF_PLL_DIV ), +}; - return 0; -} +struct imx8_clks_collect imx8qxp_clk_collect = { + { + {&imx8qxp_clks, ARRAY_SIZE(imx8qxp_clks)}, + {&imx8qxp_fixed_clks, ARRAY_SIZE(imx8qxp_fixed_clks)}, + {&imx8qxp_gpr_clks, ARRAY_SIZE(imx8qxp_gpr_clks)}, + {&imx8qxp_lpcg_clks, ARRAY_SIZE(imx8qxp_lpcg_clks)}, + {&imx8qxp_mux_clks, ARRAY_SIZE(imx8qxp_mux_clks)}, + }, + FLAG_CLK_IMX8_IMX8QXP, +}; diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 1eccac28c62..a7c31208604 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -235,6 +235,20 @@ config SPL_SIMPLE_BUS Supports the 'simple-bus' driver, which is used on some systems in SPL. +config SIMPLE_BUS_CORRECT_RANGE + bool "Decode the 'simple-bus' by honoring the #address-cells and #size-cells" + depends on SIMPLE_BUS + default y if SANDBOX + help + Decoding the 'simple-bus' by honoring the #address-cells + and #size-cells of parent/child bus. If unset, #address-cells of + parent bus is assumed to be 1, #address-cells and #size-cells of + child bus is also assumed to be 1, to save some spaces of using + an advanced API to decode the , which benefits SPL image + builds that have size limits. + + If you are unsure about this, Say N here. + config SIMPLE_PM_BUS bool "Support simple-pm-bus driver" depends on DM && OF_CONTROL && CLK && POWER_DOMAIN diff --git a/drivers/core/device.c b/drivers/core/device.c index 81f6880eac4..0d2b8f872e5 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -548,7 +548,7 @@ int device_probe(struct udevice *dev) } /* Only handle devices that have a valid ofnode */ - if (dev_has_ofnode(dev)) { + if (dev_has_ofnode(dev) && !(dev->driver->flags & DM_FLAG_IGNORE_DEFAULT_CLKS)) { /* * Process 'assigned-{clocks/clock-parents/clock-rates}' * properties diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c index 653344529e6..7702beff97b 100644 --- a/drivers/core/of_extra.c +++ b/drivers/core/of_extra.c @@ -130,3 +130,26 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type, return 0; } + +bool ofnode_phy_is_fixed_link(ofnode eth_node, ofnode *phy_node) +{ + ofnode node, subnode; + int len; + + subnode = ofnode_find_subnode(eth_node, "fixed-link"); + if (ofnode_valid(subnode)) { + /* new binding */ + node = subnode; + } else if (ofnode_get_property(eth_node, "fixed-link", &len) && + len == (5 * sizeof(__be32))) { + /* old binding */ + node = eth_node; + } else { + return false; + } + + if (phy_node) + *phy_node = node; + + return true; +} diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c index b0c2c209587..18f52d26df2 100644 --- a/drivers/core/simple-bus.c +++ b/drivers/core/simple-bus.c @@ -4,8 +4,12 @@ */ #include +#include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; fdt_addr_t simple_bus_translate(struct udevice *dev, fdt_addr_t addr) { @@ -22,16 +26,30 @@ static int simple_bus_post_bind(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_PLATDATA) return 0; #else - u32 cell[3]; + struct simple_bus_plat *plat = dev_get_uclass_plat(dev); int ret; - ret = dev_read_u32_array(dev, "ranges", cell, ARRAY_SIZE(cell)); - if (!ret) { - struct simple_bus_plat *plat = dev_get_uclass_plat(dev); + if (CONFIG_IS_ENABLED(SIMPLE_BUS_CORRECT_RANGE)) { + uint64_t caddr, paddr, len; + + /* only read range index 0 */ + ret = fdt_read_range((void *)gd->fdt_blob, dev_of_offset(dev), + 0, &caddr, &paddr, &len); + if (!ret) { + plat->base = caddr; + plat->target = paddr; + plat->size = len; + } + } else { + u32 cell[3]; - plat->base = cell[0]; - plat->target = cell[1]; - plat->size = cell[2]; + ret = dev_read_u32_array(dev, "ranges", cell, + ARRAY_SIZE(cell)); + if (!ret) { + plat->base = cell[0]; + plat->target = cell[1]; + plat->size = cell[2]; + } } return dm_scan_fdt_dev(dev); diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index abddbef57b8..de1c876e8ad 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -35,6 +35,8 @@ const char *get_imx8_type(u32 imxtype) return "QXP"; case MXC_CPU_IMX8QM: return "QM"; + case MXC_CPU_IMX8DXL: + return "DXL"; default: return "??"; } @@ -49,6 +51,10 @@ const char *get_imx8_rev(u32 rev) return "B"; case CHIP_REV_C: return "C"; + case CHIP_REV_A1: + return "A1"; + case CHIP_REV_A2: + return "A2"; default: return "?"; } diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index efbd1d3fca0..6069dd5b29c 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -4,5 +4,6 @@ # http://www.samsung.com obj-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o +obj-$(CONFIG_FSL_CAAM_KB) += fsl_caam.o obj-y += rsa_mod_exp/ obj-y += fsl/ diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index 5ed6140da35..cb9fc425207 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -7,6 +7,12 @@ config FSL_CAAM Module (CAAM), also known as the SEC version 4 (SEC4). The driver uses Job Ring as interface to communicate with CAAM. +config CAAM_64BIT + bool + default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 + help + Select Crypto driver for 64 bits CAAM version + config SYS_FSL_HAS_SEC bool help @@ -58,4 +64,6 @@ config FSL_CAAM_RNG using the prediction resistance flag which means the DRGB is reseeded from the TRNG every time random data is generated. +config FSL_BLOB + bool "Enable Blob Encap/Decap, Blob KEK support" endif diff --git a/drivers/crypto/fsl/Makefile b/drivers/crypto/fsl/Makefile index a5e8d38e381..7c3da9bc363 100644 --- a/drivers/crypto/fsl/Makefile +++ b/drivers/crypto/fsl/Makefile @@ -4,7 +4,8 @@ obj-y += sec.o obj-$(CONFIG_FSL_CAAM) += jr.o fsl_hash.o jobdesc.o error.o -obj-$(CONFIG_CMD_BLOB) += fsl_blob.o -obj-$(CONFIG_CMD_DEKBLOB) += fsl_blob.o +obj-$(CONFIG_CMD_BLOB)$(CONFIG_IMX_CAAM_DEK_ENCAP) += fsl_blob.o +obj-$(CONFIG_FSL_BLOB) += fsl_blob.o obj-$(CONFIG_RSA_FREESCALE_EXP) += fsl_rsa.o obj-$(CONFIG_FSL_CAAM_RNG) += rng.o +obj-$(CONFIG_IMX_CAAM_MFG_PROT) += fsl_mfgprot.o diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 3589e6ea024..4d53911b340 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -11,8 +11,11 @@ #ifndef DESC_H #define DESC_H +#include "type.h" + #define KEY_BLOB_SIZE 32 #define MAC_SIZE 16 +#define BKEK_SIZE 32 /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */ #define MAX_CAAM_DESCSIZE 64 @@ -461,6 +464,9 @@ #define OP_PROTINFO_HASH_SHA384 0x00000200 #define OP_PROTINFO_HASH_SHA512 0x00000280 +/* PROTINFO fields for Blob Operations */ +#define OP_PROTINFO_MKVB 0x00000002 + /* For non-protocol/alg-only op commands */ #define OP_ALG_TYPE_SHIFT 24 #define OP_ALG_TYPE_MASK (0x7 << OP_ALG_TYPE_SHIFT) @@ -693,29 +699,29 @@ /* Structures for Protocol Data Blocks */ struct __packed pdb_ecdsa_verify { uint32_t pdb_hdr; - dma_addr_t dma_q; /* Pointer to q (elliptic curve) */ - dma_addr_t dma_r; /* Pointer to r (elliptic curve) */ - dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */ - dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */ - dma_addr_t dma_hash; /* Pointer to hash input */ - dma_addr_t dma_c; /* Pointer to C_signature */ - dma_addr_t dma_d; /* Pointer to D_signature */ - dma_addr_t dma_buf; /* Pointer to 64-byte temp buffer */ - dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */ + caam_dma_addr_t dma_q; /* Pointer to q (elliptic curve) */ + caam_dma_addr_t dma_r; /* Pointer to r (elliptic curve) */ + caam_dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */ + caam_dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */ + caam_dma_addr_t dma_hash; /* Pointer to hash input */ + caam_dma_addr_t dma_c; /* Pointer to C_signature */ + caam_dma_addr_t dma_d; /* Pointer to D_signature */ + caam_dma_addr_t dma_buf; /* Pointer to 64-byte temp buffer */ + caam_dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */ uint32_t img_size; /* Length of Message */ }; struct __packed pdb_ecdsa_sign { uint32_t pdb_hdr; - dma_addr_t dma_q; /* Pointer to q (elliptic curve) */ - dma_addr_t dma_r; /* Pointer to r (elliptic curve) */ - dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */ - dma_addr_t dma_pri_key; /* Pointer to S (Private key) */ - dma_addr_t dma_hash; /* Pointer to hash input */ - dma_addr_t dma_c; /* Pointer to C_signature */ - dma_addr_t dma_d; /* Pointer to D_signature */ - dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */ - dma_addr_t dma_u; /* Pointer to Per Message Random */ + caam_dma_addr_t dma_q; /* Pointer to q (elliptic curve) */ + caam_dma_addr_t dma_r; /* Pointer to r (elliptic curve) */ + caam_dma_addr_t dma_g_xy; /* Pointer to Gx,y (elliptic curve) */ + caam_dma_addr_t dma_pri_key; /* Pointer to S (Private key) */ + caam_dma_addr_t dma_hash; /* Pointer to hash input */ + caam_dma_addr_t dma_c; /* Pointer to C_signature */ + caam_dma_addr_t dma_d; /* Pointer to D_signature */ + caam_dma_addr_t dma_ab; /* Pointer to a,b (elliptic curve ) */ + caam_dma_addr_t dma_u; /* Pointer to Per Message Random */ uint32_t img_size; /* Length of Message */ }; @@ -726,20 +732,21 @@ struct __packed pdb_ecdsa_sign { struct __packed pdb_mp_pub_k { uint32_t pdb_hdr; #define PDB_MP_PUB_K_SGF_SHIFT 31 - dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */ + caam_dma_addr_t dma_pkey; /* Pointer to Wx,y (public key) */ }; struct __packed pdb_mp_sign { uint32_t pdb_hdr; #define PDB_MP_SIGN_SGF_SHIFT 28 - dma_addr_t dma_addr_msg; /* Pointer to Message */ - dma_addr_t dma_addr_hash; /* Pointer to hash output */ - dma_addr_t dma_addr_c_sig; /* Pointer to C_signature */ - dma_addr_t dma_addr_d_sig; /* Pointer to D_signature */ + caam_dma_addr_t dma_addr_msg; /* Pointer to Message */ + caam_dma_addr_t dma_addr_hash; /* Pointer to hash output */ + caam_dma_addr_t dma_addr_c_sig; /* Pointer to C_signature */ + caam_dma_addr_t dma_addr_d_sig; /* Pointer to D_signature */ uint32_t img_size; /* Length of Message */ }; #define PDB_MP_CSEL_SHIFT 17 +#define PDB_MP_CSEL_WIDTH 4 #define PDB_MP_CSEL_P256 0x3 << PDB_MP_CSEL_SHIFT /* P-256 */ #define PDB_MP_CSEL_P384 0x4 << PDB_MP_CSEL_SHIFT /* P-384 */ #define PDB_MP_CSEL_P521 0x5 << PDB_MP_CSEL_SHIFT /* P-521 */ diff --git a/drivers/crypto/fsl/desc_constr.h b/drivers/crypto/fsl/desc_constr.h index b82ba83e73a..209557c4ffa 100644 --- a/drivers/crypto/fsl/desc_constr.h +++ b/drivers/crypto/fsl/desc_constr.h @@ -12,7 +12,7 @@ #define IMMEDIATE (1 << 23) #define CAAM_CMD_SZ sizeof(u32) -#define CAAM_PTR_SZ sizeof(dma_addr_t) +#define CAAM_PTR_SZ sizeof(caam_dma_addr_t) #define CAAM_DESC_BYTES_MAX (CAAM_CMD_SZ * MAX_CAAM_DESCSIZE) #define DESC_JOB_IO_LEN (CAAM_CMD_SZ * 5 + CAAM_PTR_SZ * 3) @@ -35,7 +35,7 @@ LDST_SRCDST_WORD_DECOCTRL | \ (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT)) -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT struct ptr_addr_t { #ifdef CONFIG_SYS_FSL_SEC_LE u32 low; @@ -49,9 +49,9 @@ struct ptr_addr_t { }; #endif -static inline void pdb_add_ptr(dma_addr_t *offset, dma_addr_t ptr) +static inline void pdb_add_ptr(caam_dma_addr_t *offset, caam_dma_addr_t ptr) { -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset; @@ -102,11 +102,11 @@ static inline void init_job_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes) options); } -static inline void append_ptr(u32 *desc, dma_addr_t ptr) +static inline void append_ptr(u32 *desc, caam_dma_addr_t ptr) { - dma_addr_t *offset = (dma_addr_t *)desc_end(desc); + caam_dma_addr_t *offset = (caam_dma_addr_t *)desc_end(desc); -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT /* The Position of low and high part of 64 bit address * will depend on the endianness of CAAM Block */ struct ptr_addr_t *ptr_addr = (struct ptr_addr_t *)offset; @@ -159,7 +159,7 @@ static inline u32 *write_cmd(u32 *desc, u32 command) return desc + 1; } -static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, +static inline void append_cmd_ptr(u32 *desc, caam_dma_addr_t ptr, int len, u32 command) { append_cmd(desc, command | len); @@ -167,7 +167,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len, } /* Write length after pointer, rather than inside command */ -static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr, +static inline void append_cmd_ptr_extlen(u32 *desc, caam_dma_addr_t ptr, unsigned int len, u32 command) { append_cmd(desc, command); @@ -225,7 +225,7 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD) APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE) #define APPEND_CMD_PTR(cmd, op) \ -static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \ +static inline void append_##cmd(u32 *desc, caam_dma_addr_t ptr, unsigned int len, \ u32 options) \ { \ PRINT_POS; \ @@ -236,7 +236,7 @@ APPEND_CMD_PTR(load, LOAD) APPEND_CMD_PTR(fifo_load, FIFO_LOAD) APPEND_CMD_PTR(fifo_store, FIFO_STORE) -static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, +static inline void append_store(u32 *desc, caam_dma_addr_t ptr, unsigned int len, u32 options) { u32 cmd_src; @@ -254,7 +254,7 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len, } #define APPEND_SEQ_PTR_INTLEN(cmd, op) \ -static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \ +static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, caam_dma_addr_t ptr, \ unsigned int len, \ u32 options) \ { \ @@ -278,7 +278,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD); APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD); #define APPEND_CMD_PTR_EXTLEN(cmd, op) \ -static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \ +static inline void append_##cmd##_extlen(u32 *desc, caam_dma_addr_t ptr, \ unsigned int len, u32 options) \ { \ PRINT_POS; \ @@ -292,7 +292,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR) * the size of its type */ #define APPEND_CMD_PTR_LEN(cmd, op, type) \ -static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \ +static inline void append_##cmd(u32 *desc, caam_dma_addr_t ptr, \ type len, u32 options) \ { \ PRINT_POS; \ diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index d6bd861251e..154a48cfed9 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -40,7 +40,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) return -EINVAL; } - printf("\nDecapsulating blob to get data\n"); + debug("\nDecapsulating blob to get data\n"); desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); @@ -65,6 +65,9 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + ret = run_descriptor_jr(desc); if (ret) { @@ -74,7 +77,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size); - puts("Blob decapsulation successful.\n"); + debug("Blob decapsulation successful.\n"); } free(desc); @@ -105,7 +108,7 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) return -EINVAL; } - printf("\nEncapsulating data to form blob\n"); + debug("\nEncapsulating data to form blob\n"); desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); @@ -130,6 +133,9 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + flush_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + ret = run_descriptor_jr(desc); if (ret) { @@ -139,7 +145,88 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size); - puts("Blob encapsulation successful.\n"); + debug("Blob encapsulation successful.\n"); + } + + free(desc); + return ret; +} + +int derive_blob_kek(u8 *bkek_buf, u8 *key_mod, u32 key_sz) +{ + int ret, size; + u32 *desc; + + if (!IS_ALIGNED((uintptr_t)bkek_buf, ARCH_DMA_MINALIGN) || + !IS_ALIGNED((uintptr_t)key_mod, ARCH_DMA_MINALIGN)) { + puts("Error: derive_bkek: Address arguments are not aligned!\n"); + return -EINVAL; + } + + debug("\nBlob key encryption key(bkek)\n"); + desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); + if (!desc) { + printf("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + size = ALIGN(key_sz, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)key_mod, (unsigned long)key_mod + size); + + /* construct blob key encryption key(bkek) derive descriptor */ + inline_cnstr_jobdesc_derive_bkek(desc, bkek_buf, key_mod, key_sz); + + size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + size = ALIGN(BKEK_SIZE, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)bkek_buf, + (unsigned long)bkek_buf + size); + + /* run descriptor */ + ret = run_descriptor_jr(desc); + if (ret < 0) { + printf("Error: derive_blob_kek failed 0x%x\n", ret); + } else { + invalidate_dcache_range((unsigned long)bkek_buf, + (unsigned long)bkek_buf + size); + debug("derive bkek successful.\n"); + } + + free(desc); + return ret; +} + +int hwrng_generate(u8 *dst, u32 len) +{ + int ret, size; + u32 *desc; + + if (!IS_ALIGNED((uintptr_t)dst, ARCH_DMA_MINALIGN)) { + puts("Error: caam_hwrng: Address arguments are not aligned!\n"); + return -EINVAL; + } + + debug("\nRNG generate\n"); + desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); + if (!desc) { + printf("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + inline_cnstr_jobdesc_rng(desc, dst ,len); + + size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); + size = ALIGN(len, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dst, (unsigned long)dst + size); + + ret = run_descriptor_jr(desc); + if (ret < 0) { + printf("Error: RNG generate failed 0x%x\n", ret); + } else { + invalidate_dcache_range((unsigned long)dst, + (unsigned long)dst + size); + debug("RNG generation successful.\n"); } free(desc); diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index 61f953e8a6d..8b5c26db070 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -87,7 +87,7 @@ static int caam_hash_update(void *hash_ctx, const void *buf, enum caam_hash_algos caam_algo) { uint32_t final; - phys_addr_t addr = virt_to_phys((void *)buf); + caam_dma_addr_t addr = virt_to_phys((void *)buf); struct sha_ctx *ctx = hash_ctx; if (ctx->sg_num >= MAX_SG_32) { @@ -95,12 +95,12 @@ static int caam_hash_update(void *hash_ctx, const void *buf, return -EINVAL; } -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, (uint32_t)(addr >> 32)); #else sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_hi, 0x0); #endif - sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (uint32_t)addr); + sec_out32(&ctx->sg_tbl[ctx->sg_num].addr_lo, (caam_dma_addr_t)addr); sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, (size & SG_ENTRY_LENGTH_MASK)); diff --git a/drivers/crypto/fsl/fsl_mfgprot.c b/drivers/crypto/fsl/fsl_mfgprot.c new file mode 100644 index 00000000000..0e3ecc524fb --- /dev/null +++ b/drivers/crypto/fsl/fsl_mfgprot.c @@ -0,0 +1,163 @@ +/* + * Copyright 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#include +#include +#include +#include +#include +#include "desc.h" +#include "desc_constr.h" +#include "jobdesc.h" +#include "jr.h" + +/* Size of MFG descriptor */ +#define MFG_PUBK_DSC_WORDS 4 +#define MFG_SIGN_DSC_WORDS 8 + +static void mfg_build_sign_dsc(u32 *dsc_ptr, const u8 *m, int size, + u8 *dgst, u8 *c, u8 *d) +{ + u32 *dsc = dsc_ptr; + struct pdb_mp_sign *pdb; + + init_job_desc_pdb(dsc, 0, sizeof(struct pdb_mp_sign)); + + pdb = (struct pdb_mp_sign *)desc_pdb(dsc); + + /* Curve */ + pdb->pdb_hdr = (PDB_MP_CSEL_P256); + + /* Message Pointer */ + pdb_add_ptr(&pdb->dma_addr_msg, virt_to_phys((void *)m)); + + /* mes-resp Pointer */ + pdb_add_ptr(&pdb->dma_addr_hash, virt_to_phys((void *)dgst)); + + /* C Pointer */ + pdb_add_ptr(&pdb->dma_addr_c_sig, virt_to_phys((void *)c)); + + /* d Pointer */ + pdb_add_ptr(&pdb->dma_addr_d_sig, virt_to_phys((void *)d)); + + /* Message Size */ + pdb->img_size = size; + + /* MP PubK generate key command */ + append_cmd(dsc, (CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | + OP_PCLID_MP_SIGN)); +} + +static void mfg_build_pubk_dsc(u32 *dsc_ptr, u8 *dst) +{ + u32 *dsc = dsc_ptr; + struct pdb_mp_pub_k *pdb; + + init_job_desc_pdb(dsc, 0, sizeof(struct pdb_mp_pub_k)); + + pdb = (struct pdb_mp_pub_k *)desc_pdb(dsc); + + /* Curve */ + pdb->pdb_hdr = (PDB_MP_CSEL_P256); + + /* Message Pointer */ + pdb_add_ptr(&pdb->dma_pkey, virt_to_phys((void *)dst)); + + /* MP Sign key command */ + append_cmd(dsc, (CMD_OPERATION | OP_TYPE_DECAP_PROTOCOL | + OP_PCLID_MP_PUB_KEY)); +} + +int gen_mppubk(u8 *dst) +{ + int size, ret; + u32 *dsc; + + /* Job Descriptor initialization */ + dsc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * MFG_PUBK_DSC_WORDS); + if (!dsc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + mfg_build_pubk_dsc(dsc, dst); + + size = roundup(sizeof(uint32_t) * MFG_PUBK_DSC_WORDS, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dsc, (unsigned long)dsc + size); + + size = roundup(FSL_CAAM_MP_PUBK_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dst, (unsigned long)dst + size); + + /* Execute Job Descriptor */ + debug("\nGenerating Manufacturing Protection Public Key\n"); + + ret = run_descriptor_jr(dsc); + if (ret) { + debug("Error in public key generation %d\n", ret); + goto err; + } + + size = roundup(FSL_CAAM_MP_PUBK_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dst, (unsigned long)dst + size); +err: + free(dsc); + return ret; +} + +int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d) +{ + int size, ret; + u32 *dsc; + + /* Job Descriptor initialization */ + dsc = memalign(ARCH_DMA_MINALIGN, + sizeof(uint32_t) * MFG_SIGN_DSC_WORDS); + if (!dsc) { + debug("Not enough memory for descriptor allocation\n"); + return -ENOMEM; + } + + mfg_build_sign_dsc(dsc, m, data_size, dgst, c, d); + + size = roundup(sizeof(uint32_t) * MFG_SIGN_DSC_WORDS, + ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dsc, (unsigned long)dsc + size); + + size = roundup(data_size, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)m, (unsigned long)m + size); + + size = roundup(FSL_CAAM_MP_MES_DGST_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)dgst, (unsigned long)dgst + size); + + size = roundup(FSL_CAAM_MP_PRVK_BYTES, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)c, (unsigned long)c + size); + flush_dcache_range((unsigned long)d, (unsigned long)d + size); + + /* Execute Job Descriptor */ + puts("\nSigning message with Manufacturing Protection Private Key\n"); + + ret = run_descriptor_jr(dsc); + if (ret) { + debug("Error in public key generation %d\n", ret); + goto err; + } + + size = roundup(FSL_CAAM_MP_MES_DGST_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)dgst, + (unsigned long)dgst + size); + + size = roundup(FSL_CAAM_MP_PRVK_BYTES, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)c, (unsigned long)c + size); + invalidate_dcache_range((unsigned long)d, (unsigned long)d + size); + +err: + free(dsc); + return ret; +} diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index fbc1aeddeeb..77ef2e12ab5 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -4,6 +4,7 @@ * Basic job descriptor construction * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * */ @@ -15,7 +16,8 @@ #include "rsa_caam.h" #include -#if defined(CONFIG_MX6) || defined(CONFIG_MX7) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \ + defined(CONFIG_IMX8M) /*! * Secure memory run command * @@ -163,9 +165,9 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt, append_u32(desc, aad_w2); - append_cmd_ptr(desc, (dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); + append_cmd_ptr(desc, (caam_dma_addr_t)SEC_MEM_PAGE1, in_sz, CMD_SEQ_IN_PTR); - append_cmd_ptr(desc, (dma_addr_t)dek_blob + 8, out_sz, CMD_SEQ_OUT_PTR); + append_cmd_ptr(desc, (caam_dma_addr_t)(ulong)(dek_blob + 8), out_sz, CMD_SEQ_OUT_PTR); append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB | OP_PCLID_SECMEM); @@ -181,7 +183,7 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, /* SHA 256 , output is of length 32 words */ uint32_t storelen = alg_size; u32 options; - dma_addr_t dma_addr_in, dma_addr_out; + caam_dma_addr_t dma_addr_in, dma_addr_out; dma_addr_in = virt_to_phys((void *)msg); dma_addr_out = virt_to_phys((void *)digest); @@ -205,12 +207,12 @@ void inline_cnstr_jobdesc_hash(uint32_t *desc, append_store(desc, dma_addr_out, storelen, LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_CONTEXT); } -#ifndef CONFIG_SPL_BUILD + void inline_cnstr_jobdesc_blob_encap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *plain_txt, uint8_t *enc_blob, uint32_t in_sz) { - dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; /* output blob will have 32 bytes key blob in beginning and * 16 byte HMAC identifier at end of data blob */ @@ -235,7 +237,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *enc_blob, uint8_t *plain_txt, uint32_t out_sz) { - dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; + caam_dma_addr_t dma_addr_key_idnfr, dma_addr_in, dma_addr_out; uint32_t key_sz = KEY_IDNFR_SZ_BYTES; uint32_t in_sz = out_sz + KEY_BLOB_SIZE + MAC_SIZE; @@ -253,7 +255,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, append_operation(desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB); } -#endif + /* * Descriptor to instantiate RNG State Handle 0 in normal mode and * load the JDKEK, TDKEK and TDSK registers @@ -298,7 +300,7 @@ void inline_cnstr_jobdesc_rng_deinstantiation(u32 *desc, int handle) void inline_cnstr_jobdesc_rng(u32 *desc, void *data_out, u32 size) { - dma_addr_t dma_data_out = virt_to_phys(data_out); + caam_dma_addr_t dma_data_out = virt_to_phys(data_out); init_job_desc(desc, 0); append_operation(desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG | @@ -311,7 +313,7 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, uint32_t out_siz) { - dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; + caam_dma_addr_t dma_addr_e, dma_addr_a, dma_addr_n, dma_addr_out; dma_addr_e = virt_to_phys((void *)pkin->e); dma_addr_a = virt_to_phys((void *)pkin->a); @@ -332,3 +334,16 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, append_fifo_store(desc, dma_addr_out, out_siz, LDST_CLASS_1_CCB | FIFOST_TYPE_PKHA_B); } + +void inline_cnstr_jobdesc_derive_bkek(uint32_t *desc, void *bkek_out, void *key_mod, uint32_t key_sz) +{ + dma_addr_t dma_key_mod = virt_to_phys(key_mod); + dma_addr_t dma_bkek_out = virt_to_phys(bkek_out); + + init_job_desc(desc, 0); + append_load(desc, dma_key_mod, key_sz, LDST_CLASS_2_CCB | + LDST_SRCDST_BYTE_KEY); + append_seq_out_ptr_intlen(desc, dma_bkek_out, BKEK_SIZE, 0); + append_operation(desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB | + OP_PROTINFO_MKVB); +} diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h index c4501abd26b..f7bd6991f46 100644 --- a/drivers/crypto/fsl/jobdesc.h +++ b/drivers/crypto/fsl/jobdesc.h @@ -49,4 +49,7 @@ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, uint32_t out_siz); +void inline_cnstr_jobdesc_derive_bkek(uint32_t *desc, void *bkek_out, + void *key_mod, uint32_t key_sz); + #endif diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 44273c345f9..84301834481 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -1,16 +1,17 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2008-2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Based on CAAM driver in drivers/crypto/caam in Linux */ #include #include +#include #include #include #include -#include "fsl_sec.h" #include "jr.h" #include "jobdesc.h" #include "desc_constr.h" @@ -20,7 +21,11 @@ #include #include #endif +#include #include +#include +#include +#include #define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1)) #define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size)) @@ -33,20 +38,30 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { #endif }; +#if CONFIG_IS_ENABLED(DM) +struct udevice *caam_dev; +#else #define SEC_ADDR(idx) \ - ((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) + (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) #define SEC_JR0_ADDR(idx) \ - (SEC_ADDR(idx) + \ + (ulong)(SEC_ADDR(idx) + \ (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) +struct caam_regs caam_st; +#endif -struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; +static inline u32 jr_start_reg(u8 jrid) +{ + return (1 << jrid); +} -static inline void start_jr0(uint8_t sec_idx) +#ifndef CONFIG_ARCH_IMX8 +static inline void start_jr(struct caam_regs *caam) { - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); + ccsr_sec_t *sec = caam->sec; u32 ctpr_ms = sec_in32(&sec->ctpr_ms); u32 scfgr = sec_in32(&sec->scfgr); + u32 jrstart = jr_start_reg(caam->jrid); if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) { /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or @@ -54,23 +69,17 @@ static inline void start_jr0(uint8_t sec_idx) */ if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) || (scfgr & SEC_SCFGR_VIRT_EN)) - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); + sec_out32(&sec->jrstartr, jrstart); } else { /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */ if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) - sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0); + sec_out32(&sec->jrstartr, jrstart); } } +#endif -static inline void jr_reset_liodn(uint8_t sec_idx) -{ - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); - sec_out32(&sec->jrliodnr[0].ls, 0); -} - -static inline void jr_disable_irq(uint8_t sec_idx) +static inline void jr_disable_irq(struct jr_regs *regs) { - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); uint32_t jrcfg = sec_in32(®s->jrcfg1); jrcfg = jrcfg | JR_INTMASK; @@ -78,20 +87,20 @@ static inline void jr_disable_irq(uint8_t sec_idx) sec_out32(®s->jrcfg1, jrcfg); } -static void jr_initregs(uint8_t sec_idx) +static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam) { - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); - struct jobring *jr = &jr0[sec_idx]; - phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); - phys_addr_t op_base = virt_to_phys((void *)jr->output_ring); + struct jr_regs *regs = caam->regs; + struct jobring *jr = &caam->jr[sec_idx]; + caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring); + caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring); -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT sec_out32(®s->irba_h, ip_base >> 32); #else sec_out32(®s->irba_h, 0x0); #endif sec_out32(®s->irba_l, (uint32_t)ip_base); -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT sec_out32(®s->orba_h, op_base >> 32); #else sec_out32(®s->orba_h, 0x0); @@ -101,24 +110,24 @@ static void jr_initregs(uint8_t sec_idx) sec_out32(®s->irs, JR_SIZE); if (!jr->irq) - jr_disable_irq(sec_idx); + jr_disable_irq(regs); } -static int jr_init(uint8_t sec_idx) +static int jr_init(uint8_t sec_idx, struct caam_regs *caam) { - struct jobring *jr = &jr0[sec_idx]; + struct jobring *jr = &caam->jr[sec_idx]; memset(jr, 0, sizeof(struct jobring)); - jr->jq_id = DEFAULT_JR_ID; + jr->jq_id = caam->jrid; jr->irq = DEFAULT_IRQ; #ifdef CONFIG_FSL_CORENET jr->liodn = DEFAULT_JR_LIODN; #endif jr->size = JR_SIZE; - jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, - JR_SIZE * sizeof(dma_addr_t)); + jr->input_ring = (caam_dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + JR_SIZE * sizeof(caam_dma_addr_t)); if (!jr->input_ring) return -1; @@ -129,56 +138,13 @@ static int jr_init(uint8_t sec_idx) if (!jr->output_ring) return -1; - memset(jr->input_ring, 0, JR_SIZE * sizeof(dma_addr_t)); + memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t)); memset(jr->output_ring, 0, jr->op_size); - start_jr0(sec_idx); - - jr_initregs(sec_idx); - - return 0; -} - -static int jr_sw_cleanup(uint8_t sec_idx) -{ - struct jobring *jr = &jr0[sec_idx]; - - jr->head = 0; - jr->tail = 0; - jr->read_idx = 0; - jr->write_idx = 0; - memset(jr->info, 0, sizeof(jr->info)); - memset(jr->input_ring, 0, jr->size * sizeof(dma_addr_t)); - memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring)); - - return 0; -} - -static int jr_hw_reset(uint8_t sec_idx) -{ - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); - uint32_t timeout = 100000; - uint32_t jrint, jrcr; - - sec_out32(®s->jrcr, JRCR_RESET); - do { - jrint = sec_in32(®s->jrint); - } while (((jrint & JRINT_ERR_HALT_MASK) == - JRINT_ERR_HALT_INPROGRESS) && --timeout); - - jrint = sec_in32(®s->jrint); - if (((jrint & JRINT_ERR_HALT_MASK) != - JRINT_ERR_HALT_INPROGRESS) && timeout == 0) - return -1; - - timeout = 100000; - sec_out32(®s->jrcr, JRCR_RESET); - do { - jrcr = sec_in32(®s->jrcr); - } while ((jrcr & JRCR_RESET) && --timeout); - - if (timeout == 0) - return -1; +#ifndef CONFIG_ARCH_IMX8 + start_jr(caam); +#endif + jr_initregs(sec_idx, caam); return 0; } @@ -186,15 +152,15 @@ static int jr_hw_reset(uint8_t sec_idx) /* -1 --- error, can't enqueue -- no space available */ static int jr_enqueue(uint32_t *desc_addr, void (*callback)(uint32_t status, void *arg), - void *arg, uint8_t sec_idx) + void *arg, uint8_t sec_idx, struct caam_regs *caam) { - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); - struct jobring *jr = &jr0[sec_idx]; + struct jr_regs *regs = caam->regs; + struct jobring *jr = &caam->jr[sec_idx]; int head = jr->head; uint32_t desc_word; int length = desc_len(desc_addr); int i; -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT uint32_t *addr_hi, *addr_lo; #endif @@ -208,7 +174,7 @@ static int jr_enqueue(uint32_t *desc_addr, sec_out32((uint32_t *)&desc_addr[i], desc_word); } - phys_addr_t desc_phys_addr = virt_to_phys(desc_addr); + caam_dma_addr_t desc_phys_addr = virt_to_phys(desc_addr); jr->info[head].desc_phys_addr = desc_phys_addr; jr->info[head].callback = (void *)callback; @@ -221,7 +187,7 @@ static int jr_enqueue(uint32_t *desc_addr, sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT /* Write the 64 bit Descriptor address on Input Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -240,11 +206,11 @@ static int jr_enqueue(uint32_t *desc_addr, #else /* Write the 32 bit Descriptor address on Input Ring. */ sec_out32(&jr->input_ring[head], desc_phys_addr); -#endif /* ifdef CONFIG_PHYS_64BIT */ +#endif /* ifdef CONFIG_CAAM_64BIT */ start = (unsigned long)&jr->input_ring[head] & ~(ARCH_DMA_MINALIGN - 1); end = ALIGN((unsigned long)&jr->input_ring[head] + - sizeof(dma_addr_t), ARCH_DMA_MINALIGN); + sizeof(caam_dma_addr_t), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); jr->head = (head + 1) & (jr->size - 1); @@ -261,16 +227,16 @@ static int jr_enqueue(uint32_t *desc_addr, return 0; } -static int jr_dequeue(int sec_idx) +static int jr_dequeue(int sec_idx, struct caam_regs *caam) { - struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); - struct jobring *jr = &jr0[sec_idx]; + struct jr_regs *regs = caam->regs; + struct jobring *jr = &caam->jr[sec_idx]; int head = jr->head; int tail = jr->tail; int idx, i, found; void (*callback)(uint32_t status, void *arg); void *arg = NULL; -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT uint32_t *addr_hi, *addr_lo; #else uint32_t *addr; @@ -281,8 +247,8 @@ static int jr_dequeue(int sec_idx) found = 0; - phys_addr_t op_desc; - #ifdef CONFIG_PHYS_64BIT + caam_dma_addr_t op_desc; + #ifdef CONFIG_CAAM_64BIT /* Read the 64 bit Descriptor address from Output Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -302,7 +268,7 @@ static int jr_dequeue(int sec_idx) /* Read the 32 bit Descriptor address from Output Ring. */ addr = (uint32_t *)&jr->output_ring[jr->tail].desc; op_desc = sec_in32(addr); - #endif /* ifdef CONFIG_PHYS_64BIT */ + #endif /* ifdef CONFIG_CAAM_64BIT */ uint32_t status = sec_in32(&jr->output_ring[jr->tail].status); @@ -347,39 +313,44 @@ static void desc_done(uint32_t status, void *arg) { struct result *x = arg; x->status = status; -#ifndef CONFIG_SPL_BUILD caam_jr_strstatus(status); -#endif x->done = 1; } static inline int run_descriptor_jr_idx(uint32_t *desc, uint8_t sec_idx) { - unsigned long long timeval = get_ticks(); - unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); + struct caam_regs *caam; +#if CONFIG_IS_ENABLED(DM) + caam = dev_get_priv(caam_dev); +#else + caam = &caam_st; +#endif + unsigned long long timeval = 0; + unsigned long long timeout = CONFIG_USEC_DEQ_TIMEOUT; struct result op; int ret = 0; memset(&op, 0, sizeof(op)); - ret = jr_enqueue(desc, desc_done, &op, sec_idx); + ret = jr_enqueue(desc, desc_done, &op, sec_idx, caam); if (ret) { debug("Error in SEC enq\n"); ret = JQ_ENQ_ERR; goto out; } - timeval = get_ticks(); - timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT); while (op.done != 1) { - ret = jr_dequeue(sec_idx); + udelay(1); + timeval += 1; + + ret = jr_dequeue(sec_idx, caam); if (ret) { debug("Error in SEC deq\n"); ret = JQ_DEQ_ERR; goto out; } - if ((get_ticks() - timeval) > timeout) { + if (timeval > timeout) { debug("SEC Dequeue timed out\n"); ret = JQ_DEQ_TO_ERR; goto out; @@ -399,13 +370,63 @@ int run_descriptor_jr(uint32_t *desc) return run_descriptor_jr_idx(desc, 0); } +#ifndef CONFIG_ARCH_IMX8 +static int jr_sw_cleanup(uint8_t sec_idx, struct caam_regs *caam) +{ + struct jobring *jr = &caam->jr[sec_idx]; + + jr->head = 0; + jr->tail = 0; + jr->read_idx = 0; + jr->write_idx = 0; + memset(jr->info, 0, sizeof(jr->info)); + memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t)); + memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring)); + + return 0; +} + +static int jr_hw_reset(struct jr_regs *regs) +{ + uint32_t timeout = 100000; + uint32_t jrint, jrcr; + + sec_out32(®s->jrcr, JRCR_RESET); + do { + jrint = sec_in32(®s->jrint); + } while (((jrint & JRINT_ERR_HALT_MASK) == + JRINT_ERR_HALT_INPROGRESS) && --timeout); + + jrint = sec_in32(®s->jrint); + if (((jrint & JRINT_ERR_HALT_MASK) != + JRINT_ERR_HALT_INPROGRESS) && timeout == 0) + return -1; + + timeout = 100000; + sec_out32(®s->jrcr, JRCR_RESET); + do { + jrcr = sec_in32(®s->jrcr); + } while ((jrcr & JRCR_RESET) && --timeout); + + if (timeout == 0) + return -1; + + return 0; +} + static inline int jr_reset_sec(uint8_t sec_idx) { - if (jr_hw_reset(sec_idx) < 0) + struct caam_regs *caam; +#if CONFIG_IS_ENABLED(DM) + caam = dev_get_priv(caam_dev); +#else + caam = &caam_st; +#endif + if (jr_hw_reset(caam->regs) < 0) return -1; /* Clean up the jobring structure maintained by software */ - jr_sw_cleanup(sec_idx); + jr_sw_cleanup(sec_idx, caam); return 0; } @@ -415,9 +436,15 @@ int jr_reset(void) return jr_reset_sec(0); } -static inline int sec_reset_idx(uint8_t sec_idx) +int sec_reset(void) { - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); + struct caam_regs *caam; +#if CONFIG_IS_ENABLED(DM) + caam = dev_get_priv(caam_dev); +#else + caam = &caam_st; +#endif + ccsr_sec_t *sec = caam->sec; uint32_t mcfgr = sec_in32(&sec->mcfgr); uint32_t timeout = 100000; @@ -443,11 +470,7 @@ static inline int sec_reset_idx(uint8_t sec_idx) return 0; } -int sec_reset(void) -{ - return sec_reset_idx(0); -} -#ifndef CONFIG_SPL_BUILD + static int deinstantiate_rng(u8 sec_idx, int state_handle_mask) { u32 *desc; @@ -493,12 +516,11 @@ static int deinstantiate_rng(u8 sec_idx, int state_handle_mask) return ret; } -static int instantiate_rng(u8 sec_idx, int gen_sk) +static int instantiate_rng(uint8_t sec_idx, ccsr_sec_t *sec, int gen_sk) { u32 *desc; u32 rdsta_val; int ret = 0, sh_idx, size; - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; @@ -551,9 +573,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk) return ret; } -static u8 get_rng_vid(uint8_t sec_idx) +static u8 get_rng_vid(ccsr_sec_t *sec) { - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); u8 vid; if (caam_get_era() < 10) { @@ -567,13 +588,121 @@ static u8 get_rng_vid(uint8_t sec_idx) return vid; } +#if defined(CONFIG_ARCH_IMX8M) || defined(CONFIG_ARCH_MX7ULP) || \ + defined(CONFIG_ARCH_MX6) || defined (CONFIG_ARCH_MX7) + +static void kick_trng(u32 ent_delay, ccsr_sec_t *sec) +{ + u32 samples = 512; /* number of bits to generate and test */ + u32 mono_min = 195; + u32 mono_max = 317; + u32 mono_range = mono_max - mono_min; + u32 poker_min = 1031; + u32 poker_max = 1600; + u32 poker_range = poker_max - poker_min + 1; + u32 retries = 2; + u32 lrun_max = 32; + s32 run_1_min = 27; + s32 run_1_max = 107; + s32 run_1_range = run_1_max - run_1_min; + s32 run_2_min = 7; + s32 run_2_max = 62; + s32 run_2_range = run_2_max - run_2_min; + s32 run_3_min = 0; + s32 run_3_max = 39; + s32 run_3_range = run_3_max - run_3_min; + s32 run_4_min = -1; + s32 run_4_max = 26; + s32 run_4_range = run_4_max - run_4_min; + s32 run_5_min = -1; + s32 run_5_max = 18; + s32 run_5_range = run_5_max - run_5_min; + s32 run_6_min = -1; + s32 run_6_max = 17; + s32 run_6_range = run_6_max - run_6_min; + u32 val; + + struct rng4tst __iomem *rng = + (struct rng4tst __iomem *)&sec->rng; + + /* Put RNG in program mode */ + /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to + * properly invalidate the entropy in the entropy register and + * force re-generation. + */ + sec_setbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC); + + /* Configure the RNG Entropy Delay + * Performance-wise, it does not make sense to + * set the delay to a value that is lower + * than the last one that worked (i.e. the state handles + * were instantiated properly. Thus, instead of wasting + * time trying to set the values controlling the sample + * frequency, the function simply returns. + */ + val = sec_in32(&rng->rtsdctl); + val &= RTSDCTL_ENT_DLY_MASK; + val >>= RTSDCTL_ENT_DLY_SHIFT; + if (ent_delay < val) { + /* Put RNG4 into run mode */ + sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC); + return; + } + + val = (ent_delay << RTSDCTL_ENT_DLY_SHIFT) | samples; + sec_out32(&rng->rtsdctl, val); + + /* + * Recommended margins (min,max) for freq. count: + * freq_mul = RO_freq / TRNG_clk_freq + * rtfrqmin = (ent_delay x freq_mul) >> 1; + * rtfrqmax = (ent_delay x freq_mul) << 3; + * Given current deployments of CAAM in i.MX SoCs, and to simplify + * the configuration, we consider [1,16] to be a safe interval + * for the freq_mul and the limits of the interval are used to compute + * rtfrqmin, rtfrqmax + */ + sec_out32(&rng->rtfreqmin, ent_delay >> 1); + sec_out32(&rng->rtfreqmax, ent_delay << 7); + + sec_out32(&rng->rtscmisc, (retries << 16) | lrun_max); + sec_out32(&rng->rtpkrmax, poker_max); + sec_out32(&rng->rtpkrrng, poker_range); + sec_out32(&rng->rsvd1[0], (mono_range << 16) | mono_max); + sec_out32(&rng->rsvd1[1], (run_1_range << 16) | run_1_max); + sec_out32(&rng->rsvd1[2], (run_2_range << 16) | run_2_max); + sec_out32(&rng->rsvd1[3], (run_3_range << 16) | run_3_max); + sec_out32(&rng->rsvd1[4], (run_4_range << 16) | run_4_max); + sec_out32(&rng->rsvd1[5], (run_5_range << 16) | run_5_max); + sec_out32(&rng->rsvd1[6], (run_6_range << 16) | run_6_max); + + val = sec_in32(&rng->rtmctl); + /* + * Select raw sampling in both entropy shifter + * and statistical checker + */ + val &= ~RTMCTL_SAMP_MODE_INVALID; + val |= RTMCTL_SAMP_MODE_RAW_ES_SC; + /* Put RNG4 into run mode */ + val &= ~(RTMCTL_PRGM | RTMCTL_ACC); + /*test with sample mode only */ + sec_out32(&rng->rtmctl, val); + + /* Clear the ERR bit in RTMCTL if set. The TRNG error can occur when the + * RNG clock is not within 1/2x to 8x the system clock. + * This error is possible if ROM code does not initialize the system PLLs + * immediately after PoR. + */ + /* setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); */ +} + +#else /* * By default, the TRNG runs for 200 clocks per sample; * 1200 clocks per sample generates better entropy. */ -static void kick_trng(int ent_delay, uint8_t sec_idx) +static void kick_trng(int ent_delay, ccsr_sec_t *sec) { - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; u32 val; @@ -599,11 +728,11 @@ static void kick_trng(int ent_delay, uint8_t sec_idx) /* put RNG4 into run mode */ sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM); } +#endif -static int rng_init(uint8_t sec_idx) +static int rng_init(uint8_t sec_idx, ccsr_sec_t *sec) { int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; - ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; u32 inst_handles; @@ -621,7 +750,7 @@ static int rng_init(uint8_t sec_idx) * the TRNG parameters. */ if (!inst_handles) { - kick_trng(ent_delay, sec_idx); + kick_trng(ent_delay, sec); ent_delay += 400; } /* @@ -631,7 +760,7 @@ static int rng_init(uint8_t sec_idx) * interval, leading to a sucessful initialization of * the RNG. */ - ret = instantiate_rng(sec_idx, gen_sk); + ret = instantiate_rng(sec_idx, sec, gen_sk); } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); if (ret) { printf("SEC%u: Failed to instantiate RNG\n", sec_idx); @@ -644,12 +773,25 @@ static int rng_init(uint8_t sec_idx) return ret; } #endif + int sec_init_idx(uint8_t sec_idx) { - ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); - uint32_t mcr = sec_in32(&sec->mcfgr); int ret = 0; - + struct caam_regs *caam; +#if CONFIG_IS_ENABLED(DM) + caam = dev_get_priv(caam_dev); +#else + caam_st.sec = (void *)SEC_ADDR(sec_idx); + caam_st.regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx); + caam_st.jrid = 0; + caam = &caam_st; +#endif +#ifndef CONFIG_ARCH_IMX8 + ccsr_sec_t *sec = caam->sec; + uint32_t mcr = sec_in32(&sec->mcfgr); +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M) + uint32_t jrdid_ms = 0; +#endif #ifdef CONFIG_FSL_CORENET uint32_t liodnr; uint32_t liodn_ns; @@ -675,10 +817,15 @@ int sec_init_idx(uint8_t sec_idx) mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); #endif -#ifdef CONFIG_PHYS_64BIT +#ifdef CONFIG_CAAM_64BIT mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); + jr_reset(); +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_IMX8M) + jrdid_ms = JRDID_MS_TZ_OWN | JRDID_MS_PRIM_TZ | JRDID_MS_PRIM_DID; + sec_out32(&sec->jrliodnr[caam->jrid].ms, jrdid_ms); +#endif #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SPL_BUILD @@ -690,25 +837,26 @@ int sec_init_idx(uint8_t sec_idx) liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK; liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK; - liodnr = sec_in32(&sec->jrliodnr[0].ls) & + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls) & ~(JRNSLIODN_MASK | JRSLIODN_MASK); liodnr = liodnr | (liodn_ns << JRNSLIODN_SHIFT) | (liodn_s << JRSLIODN_SHIFT); - sec_out32(&sec->jrliodnr[0].ls, liodnr); + sec_out32(&sec->jrliodnr[caam->jrid].ls, liodnr); #else - liodnr = sec_in32(&sec->jrliodnr[0].ls); + liodnr = sec_in32(&sec->jrliodnr[caam->jrid].ls); liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif #endif - - ret = jr_init(sec_idx); +#endif + ret = jr_init(sec_idx, caam); if (ret < 0) { printf("SEC%u: initialization failed\n", sec_idx); return -1; } +#ifndef CONFIG_ARCH_IMX8 #ifdef CONFIG_FSL_CORENET ret = sec_config_pamu_table(liodn_ns, liodn_s); if (ret < 0) @@ -716,9 +864,9 @@ int sec_init_idx(uint8_t sec_idx) pamu_enable(); #endif -#ifndef CONFIG_SPL_BUILD - if (get_rng_vid(sec_idx) >= 4) { - if (rng_init(sec_idx) < 0) { + + if (get_rng_vid(caam->sec) >= 4) { + if (rng_init(sec_idx, caam->sec) < 0) { printf("SEC%u: RNG instantiation failed\n", sec_idx); return -1; } @@ -740,3 +888,90 @@ int sec_init(void) { return sec_init_idx(0); } + +#ifdef CONFIG_ARCH_IMX8 +static int jr_power_on(int subnode) +{ +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + struct udevice __maybe_unused jr_dev; + struct power_domain pd; + + dev_set_ofnode(&jr_dev, offset_to_ofnode(subnode)); + + /* Need to power on Job Ring before access it */ + if (!power_domain_get(&jr_dev, &pd)) { + if (power_domain_on(&pd)) + return -EINVAL; + } +#endif + return 0; +} +#endif + +#if CONFIG_IS_ENABLED(DM) +static int caam_jr_probe(struct udevice *dev) +{ + struct caam_regs *caam = dev_get_priv(dev); + const void *fdt = gd->fdt_blob; + int node = dev_of_offset(dev); + struct fdt_resource res; + int subnode, ret; + unsigned int jr_node = 0; + + caam_dev = dev; + + ret = fdt_get_resource(fdt, node, "reg", 0, &res); + if (ret) { + printf("caam_jr: resource not found\n"); + return ret; + } + caam->sec = (ccsr_sec_t *)res.start; + caam->regs = (struct jr_regs *)caam->sec; + + /* Check for enabled job ring subnode */ + fdt_for_each_subnode(subnode, fdt, node) { + if (!fdtdec_get_is_enabled(fdt, subnode)) { + continue; + } + jr_node = fdtdec_get_uint(fdt, subnode, "reg", -1); + if (jr_node > 0) { + caam->regs = (struct jr_regs *)((ulong)caam->sec + jr_node); + while (!(jr_node & 0x0F)) { + jr_node = jr_node >> 4; + } + caam->jrid = jr_node - 1; +#ifdef CONFIG_ARCH_IMX8 + ret = jr_power_on(subnode); + if (ret) + return ret; +#endif + break; + } + } + + if (sec_init()) { + printf("\nsec_init failed!\n"); + } + + return 0; +} + +static int caam_jr_bind(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id caam_jr_match[] = { + { .compatible = "fsl,sec-v4.0" }, + { } +}; + +U_BOOT_DRIVER(caam_jr) = { + .name = "caam_jr", + .id = UCLASS_MISC, + .of_match = caam_jr_match, + .bind = caam_jr_bind, + .probe = caam_jr_probe, + .priv_auto = sizeof(struct caam_regs), +}; +#endif diff --git a/drivers/crypto/fsl/jr.h b/drivers/crypto/fsl/jr.h index ffd3a192738..d6d5698ea4b 100644 --- a/drivers/crypto/fsl/jr.h +++ b/drivers/crypto/fsl/jr.h @@ -8,10 +8,13 @@ #define __JR_H #include +#include "fsl_sec.h" +#include "type.h" +#include #define JR_SIZE 4 -/* Timeout currently defined as 90 sec */ -#define CONFIG_SEC_DEQ_TIMEOUT 90000000U +/* Timeout currently defined as 10 sec */ +#define CONFIG_USEC_DEQ_TIMEOUT 10000000U #define DEFAULT_JR_ID 0 #define DEFAULT_JR_LIODN 0 @@ -34,6 +37,10 @@ #define JRSLIODN_SHIFT 0 #define JRSLIODN_MASK 0x00000fff +#define JRDID_MS_PRIM_DID 1 +#define JRDID_MS_PRIM_TZ (1 << 4) +#define JRDID_MS_TZ_OWN (1 << 15) + #define JQ_DEQ_ERR -1 #define JQ_DEQ_TO_ERR -2 #define JQ_ENQ_ERR -3 @@ -41,13 +48,13 @@ #define RNG4_MAX_HANDLES 2 struct op_ring { - phys_addr_t desc; + caam_dma_addr_t desc; uint32_t status; } __packed; struct jr_info { void (*callback)(uint32_t status, void *arg); - phys_addr_t desc_phys_addr; + caam_dma_addr_t desc_phys_addr; uint32_t desc_len; uint32_t op_done; void *arg; @@ -83,7 +90,7 @@ struct jobring { * by SEC */ /*Circular Ring of i/p descriptors */ - dma_addr_t *input_ring; + caam_dma_addr_t *input_ring; /* Circular Ring of o/p descriptors */ /* Circula Ring containing info regarding descriptors in i/p * and o/p ring @@ -101,6 +108,13 @@ struct result { uint32_t status; }; +struct caam_regs { + ccsr_sec_t *sec; + struct jr_regs *regs; + u8 jrid; + struct jobring jr[CONFIG_SYS_FSL_MAX_NUM_OF_SEC]; +}; + void caam_jr_strstatus(u32 status); int run_descriptor_jr(uint32_t *desc); diff --git a/drivers/crypto/fsl/type.h b/drivers/crypto/fsl/type.h new file mode 100644 index 00000000000..b7031a60fdd --- /dev/null +++ b/drivers/crypto/fsl/type.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + * + */ + +#ifndef CRYPTO_FSL_TYPE_H +#define CRYPTO_FSL_TYPE_H + +#ifdef CONFIG_CAAM_64BIT +typedef unsigned long long caam_dma_addr_t; +#else +typedef u32 caam_dma_addr_t; +#endif + +#endif diff --git a/drivers/crypto/fsl_caam.c b/drivers/crypto/fsl_caam.c new file mode 100644 index 00000000000..02cc82bf79f --- /dev/null +++ b/drivers/crypto/fsl_caam.c @@ -0,0 +1,763 @@ +/* + * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * Copyright 2018 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#ifndef CONFIG_ARCH_MX7ULP +#include +#else +#include +#endif /* CONFIG_ARCH_MX7ULP */ +#include "fsl_caam_internal.h" +#include "fsl/desc_constr.h" +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void rng_init(void); +static void caam_clock_enable(void); +static int do_cfg_jrqueue(void); +static int do_job(u32 *desc); +static int jr_reset(void); + +/* + * Structures + */ +/* Definition of input ring object */ +struct inring_entry { + u32 desc; /* Pointer to input descriptor */ +}; + +/* Definition of output ring object */ +struct outring_entry { + u32 desc; /* Pointer to output descriptor */ + u32 status; /* Status of the Job Ring */ +}; + +/* Main job ring data structure */ +struct jr_data_st { + struct inring_entry *inrings; + struct outring_entry *outrings; + u32 status; /* Ring buffers init status */ + u32 *desc; /* Pointer to output descriptor */ + u32 raw_addr[DESC_MAX_SIZE * 2]; +}; + +/* + * Global variables + */ +#if defined(CONFIG_SPL_BUILD) +static struct jr_data_st g_jrdata = {0}; +#else +static struct jr_data_st g_jrdata = {0, 0, 0xFFFFFFFF}; +#endif + +static u8 skeymod[] = { + 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 +}; + +/* + * Local functions + */ +static void dump_error(void) +{ + int i; + + debug("Dump CAAM Error\n"); + debug("MCFGR 0x%08X\n", __raw_readl(CAAM_MCFGR)); + debug("FAR 0x%08X\n", __raw_readl(CAAM_FAR)); + debug("FAMR 0x%08X\n", __raw_readl(CAAM_FAMR)); + debug("FADR 0x%08X\n", __raw_readl(CAAM_FADR)); + debug("CSTA 0x%08X\n", __raw_readl(CAAM_STA)); + debug("RTMCTL 0x%X\n", __raw_readl(CAAM_RTMCTL)); + debug("RTSTATUS 0x%X\n", __raw_readl(CAAM_RTSTATUS)); + debug("RDSTA 0x%X\n", __raw_readl(CAAM_RDSTA)); + + for (i = 0; i < desc_len(g_jrdata.desc); i++) + debug("desc[%d]: 0x%08x\n", i, g_jrdata.desc[i]); +} + +/*! + * Secure memory run command. + * + * @param sec_mem_cmd Secure memory command register + * @return cmd_status Secure memory command status register + */ +u32 secmem_set_cmd_1(u32 sec_mem_cmd) +{ + u32 temp_reg; + __raw_writel(sec_mem_cmd, CAAM_SMCJR0); + do { + temp_reg = __raw_readl(CAAM_SMCSJR0); + } while (temp_reg & CMD_COMPLETE); + + return temp_reg; +} + + +/*! + * Use CAAM to decapsulate a blob to secure memory. + * Such blob of secret key cannot be read once decrypted, + * but can still be used for enc/dec operation of user's data. + * + * @param blob_addr Location address of the blob. + * + * @return SUCCESS or ERROR_XXX + */ +u32 caam_decap_blob(u32 plain_text, u32 blob_addr, u32 size) +{ + u32 ret = SUCCESS; + u32 key_sz = sizeof(skeymod); + u32 *decap_desc = g_jrdata.desc; + + /* prepare job descriptor */ + init_job_desc(decap_desc, 0); + append_load(decap_desc, PTR2CAAMDMA(skeymod), key_sz, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); + append_seq_in_ptr_intlen(decap_desc, blob_addr, size + 48, 0); + append_seq_out_ptr_intlen(decap_desc, plain_text, size, 0); + append_operation(decap_desc, OP_TYPE_DECAP_PROTOCOL | OP_PCLID_BLOB); + + flush_dcache_range((uintptr_t)blob_addr & ALIGN_MASK, + ((uintptr_t)blob_addr & ALIGN_MASK) + + ROUND(2 * size, ARCH_DMA_MINALIGN)); + flush_dcache_range((uintptr_t)plain_text & ALIGN_MASK, + (plain_text & ALIGN_MASK) + + ROUND(2 * size, ARCH_DMA_MINALIGN)); + + /* Run descriptor with result written to blob buffer */ + ret = do_job(decap_desc); + + if (ret != SUCCESS) { + printf("Error: blob decap job failed 0x%x\n", ret); + } + + return ret; +} + +/*! + * Use CAAM to generate a blob. + * + * @param plain_data_addr Location address of the plain data. + * @param blob_addr Location address of the blob. + * + * @return SUCCESS or ERROR_XXX + */ +u32 caam_gen_blob(u32 plain_data_addr, u32 blob_addr, u32 size) +{ + u32 ret = SUCCESS; + u32 key_sz = sizeof(skeymod); + u32 *encap_desc = g_jrdata.desc; + /* Buffer to hold the resulting blob */ + u8 *blob = (u8 *)CAAMDMA2PTR(blob_addr); + + /* initialize the blob array */ + memset(blob,0,size); + + /* prepare job descriptor */ + init_job_desc(encap_desc, 0); + append_load(encap_desc, PTR2CAAMDMA(skeymod), key_sz, + LDST_CLASS_2_CCB | LDST_SRCDST_BYTE_KEY); + append_seq_in_ptr_intlen(encap_desc, plain_data_addr, size, 0); + append_seq_out_ptr_intlen(encap_desc, PTR2CAAMDMA(blob), size + 48, 0); + append_operation(encap_desc, OP_TYPE_ENCAP_PROTOCOL | OP_PCLID_BLOB); + + flush_dcache_range((uintptr_t)plain_data_addr & ALIGN_MASK, + (plain_data_addr & ALIGN_MASK) + + ROUND(2 * size, ARCH_DMA_MINALIGN)); + flush_dcache_range((uintptr_t)blob & ALIGN_MASK, + ((uintptr_t)blob & ALIGN_MASK) + + ROUND(2 * size, ARCH_DMA_MINALIGN)); + + ret = do_job(encap_desc); + + if (ret != SUCCESS) { + printf("Error: blob encap job failed 0x%x\n", ret); + } + + return ret; +} + +u32 caam_hwrng(u8 *output_ptr, u32 output_len) +{ + u32 ret = SUCCESS; + u32 *hwrng_desc = g_jrdata.desc; + /* Buffer to hold the resulting output*/ + u8 *output = (u8 *)output_ptr; + + /* initialize the output array */ + memset(output,0,output_len); + + /* prepare job descriptor */ + init_job_desc(hwrng_desc, 0); + append_operation(hwrng_desc, OP_ALG_ALGSEL_RNG | OP_TYPE_CLASS1_ALG); + append_fifo_store(hwrng_desc, PTR2CAAMDMA(output), + output_len, FIFOST_TYPE_RNGSTORE); + + /* flush cache */ + flush_dcache_range((uintptr_t)hwrng_desc & ALIGN_MASK, + ((uintptr_t)hwrng_desc & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + + ret = do_job(hwrng_desc); + + flush_dcache_range((uintptr_t)output & ALIGN_MASK, + ((uintptr_t)output & ALIGN_MASK) + + ROUND(2 * output_len, ARCH_DMA_MINALIGN)); + + if (ret != SUCCESS) { + printf("Error: RNG generate failed 0x%x\n", ret); + } + + return ret; +} + +/*! + * Initialize the CAAM. + * + */ +void caam_open(void) +{ + u32 temp_reg; + int ret; + + /* switch on the clock */ +#ifndef CONFIG_ARCH_IMX8 + u32 init_mask; + + caam_clock_enable(); +#endif + + /* reset the CAAM */ + temp_reg = __raw_readl(CAAM_MCFGR) | + CAAM_MCFGR_DMARST | CAAM_MCFGR_SWRST; + __raw_writel(temp_reg, CAAM_MCFGR); + while (__raw_readl(CAAM_MCFGR) & CAAM_MCFGR_DMARST) + ; + + jr_reset(); + ret = do_cfg_jrqueue(); + + if (ret != SUCCESS) { + printf("Error CAAM JR initialization\n"); + return; + } + + /* Check if the RNG is already instantiated */ + temp_reg = __raw_readl(CAAM_RDSTA); + init_mask = RDSTA_IF0 | RDSTA_IF1 | RDSTA_SKVN; + if ((temp_reg & init_mask) == init_mask) { + printf("RNG already instantiated 0x%X\n", temp_reg); + return; + } + + rng_init(); +} + +static void caam_clock_enable(void) +{ +#if defined(CONFIG_ARCH_MX6) + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + u32 reg; + + reg = __raw_readl(&mxc_ccm->CCGR0); + + reg |= (MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK | + MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK); + + __raw_writel(reg, &mxc_ccm->CCGR0); + +#ifndef CONFIG_MX6UL + /* EMI slow clk */ + reg = __raw_readl(&mxc_ccm->CCGR6); + reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK; + + __raw_writel(reg, &mxc_ccm->CCGR6); +#endif + +#elif defined(CONFIG_ARCH_MX7) + HW_CCM_CCGR_SET(36, MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK); +#elif defined(CONFIG_ARCH_MX7ULP) + pcc_clock_enable(PER_CLK_CAAM, true); +#endif +} + +static void kick_trng(u32 ent_delay) +{ + u32 samples = 512; /* number of bits to generate and test */ + u32 mono_min = 195; + u32 mono_max = 317; + u32 mono_range = mono_max - mono_min; + u32 poker_min = 1031; + u32 poker_max = 1600; + u32 poker_range = poker_max - poker_min + 1; + u32 retries = 2; + u32 lrun_max = 32; + s32 run_1_min = 27; + s32 run_1_max = 107; + s32 run_1_range = run_1_max - run_1_min; + s32 run_2_min = 7; + s32 run_2_max = 62; + s32 run_2_range = run_2_max - run_2_min; + s32 run_3_min = 0; + s32 run_3_max = 39; + s32 run_3_range = run_3_max - run_3_min; + s32 run_4_min = -1; + s32 run_4_max = 26; + s32 run_4_range = run_4_max - run_4_min; + s32 run_5_min = -1; + s32 run_5_max = 18; + s32 run_5_range = run_5_max - run_5_min; + s32 run_6_min = -1; + s32 run_6_max = 17; + s32 run_6_range = run_6_max - run_6_min; + u32 val; + + /* Put RNG in program mode */ + /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to + * properly invalidate the entropy in the entropy register and + * force re-generation. + */ + setbits_le32(CAAM_RTMCTL, RTMCTL_PGM | RTMCTL_ACC); + + /* Configure the RNG Entropy Delay + * Performance-wise, it does not make sense to + * set the delay to a value that is lower + * than the last one that worked (i.e. the state handles + * were instantiated properly. Thus, instead of wasting + * time trying to set the values controlling the sample + * frequency, the function simply returns. + */ + val = __raw_readl(CAAM_RTSDCTL); + val &= BM_TRNG_ENT_DLY; + val >>= BS_TRNG_ENT_DLY; + if (ent_delay < val) { + /* Put RNG4 into run mode */ + clrbits_le32(CAAM_RTMCTL, RTMCTL_PGM | RTMCTL_ACC); + return; + } + + val = (ent_delay << BS_TRNG_ENT_DLY) | samples; + __raw_writel(val, CAAM_RTSDCTL); + + /* + * Recommended margins (min,max) for freq. count: + * freq_mul = RO_freq / TRNG_clk_freq + * rtfrqmin = (ent_delay x freq_mul) >> 1; + * rtfrqmax = (ent_delay x freq_mul) << 3; + * Given current deployments of CAAM in i.MX SoCs, and to simplify + * the configuration, we consider [1,16] to be a safe interval + * for the freq_mul and the limits of the interval are used to compute + * rtfrqmin, rtfrqmax + */ + __raw_writel(ent_delay >> 1, CAAM_RTFRQMIN); + __raw_writel(ent_delay << 7, CAAM_RTFRQMAX); + + __raw_writel((retries << 16) | lrun_max, CAAM_RTSCMISC); + __raw_writel(poker_max, CAAM_RTPKRMAX); + __raw_writel(poker_range, CAAM_RTPKRRNG); + __raw_writel((mono_range << 16) | mono_max, CAAM_RTSCML); + __raw_writel((run_1_range << 16) | run_1_max, CAAM_RTSCR1L); + __raw_writel((run_2_range << 16) | run_2_max, CAAM_RTSCR2L); + __raw_writel((run_3_range << 16) | run_3_max, CAAM_RTSCR3L); + __raw_writel((run_4_range << 16) | run_4_max, CAAM_RTSCR4L); + __raw_writel((run_5_range << 16) | run_5_max, CAAM_RTSCR5L); + __raw_writel((run_6_range << 16) | run_6_max, CAAM_RTSCR6PL); + + val = __raw_readl(CAAM_RTMCTL); + /* + * Select raw sampling in both entropy shifter + * and statistical checker + */ + val &= ~BM_TRNG_SAMP_MODE; + val |= TRNG_SAMP_MODE_RAW_ES_SC; + /* Put RNG4 into run mode */ + val &= ~(RTMCTL_PGM | RTMCTL_ACC); +/*test with sample mode only */ + __raw_writel(val, CAAM_RTMCTL); + + /* Clear the ERR bit in RTMCTL if set. The TRNG error can occur when the + * RNG clock is not within 1/2x to 8x the system clock. + * This error is possible if ROM code does not initialize the system PLLs + * immediately after PoR. + */ + /* setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); */ +} + +/* + * Descriptors to instantiate SH0, SH1, load the keys + */ +#ifndef CONFIG_ARCH_IMX8 +static const u32 rng_inst_sh0_desc[] = { + /* Header, don't setup the size */ + CAAM_HDR_CTYPE | CAAM_HDR_ONE | CAAM_HDR_START_INDEX(0), + /* Operation instantiation (sh0) */ + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | ALGO_RNG_SH(0) | ALGO_RNG_PR | + ALGO_RNG_INSTANTIATE, +}; + +static const u32 rng_inst_sh1_desc[] = { + /* wait for done - Jump to next entry */ + CAAM_C1_JUMP | CAAM_JUMP_LOCAL | CAAM_JUMP_TST_ALL_COND_TRUE + | CAAM_JUMP_OFFSET(1), + /* Clear written register (write 1) */ + CAAM_C0_LOAD_IMM | CAAM_DST_CLEAR_WRITTEN | sizeof(u32), + 0x00000001, + /* Operation instantiation (sh1) */ + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | ALGO_RNG_SH(1) | ALGO_RNG_PR + | ALGO_RNG_INSTANTIATE, +}; + +static const u32 rng_inst_load_keys[] = { + /* wait for done - Jump to next entry */ + CAAM_C1_JUMP | CAAM_JUMP_LOCAL | CAAM_JUMP_TST_ALL_COND_TRUE + | CAAM_JUMP_OFFSET(1), + /* Clear written register (write 1) */ + CAAM_C0_LOAD_IMM | CAAM_DST_CLEAR_WRITTEN | sizeof(u32), + 0x00000001, + /* Generate the Key */ + CAAM_PROTOP_CTYPE | CAAM_C1_RNG | BM_ALGO_RNG_SK | ALGO_RNG_GENERATE, +}; +#endif + +static void do_inst_desc(u32 *desc, u32 status) +{ + u32 *pdesc = desc; + u8 desc_len; + bool add_sh0 = false; + bool add_sh1 = false; + bool load_keys = false; + + /* + * Modify the the descriptor to remove if necessary: + * - The key loading + * - One of the SH already instantiated + */ + desc_len = RNG_DESC_SH0_SIZE; + if ((status & RDSTA_IF0) != RDSTA_IF0) + add_sh0 = true; + + if ((status & RDSTA_IF1) != RDSTA_IF1) { + add_sh1 = true; + if (add_sh0) + desc_len += RNG_DESC_SH1_SIZE; + } + + if ((status & RDSTA_SKVN) != RDSTA_SKVN) { + load_keys = true; + desc_len += RNG_DESC_KEYS_SIZE; + } + + /* Copy the SH0 descriptor anyway */ + memcpy(pdesc, rng_inst_sh0_desc, sizeof(rng_inst_sh0_desc)); + pdesc += RNG_DESC_SH0_SIZE; + + if (load_keys) { + debug("RNG - Load keys\n"); + memcpy(pdesc, rng_inst_load_keys, sizeof(rng_inst_load_keys)); + pdesc += RNG_DESC_KEYS_SIZE; + } + + if (add_sh1) { + if (add_sh0) { + debug("RNG - Instantiation of SH0 and SH1\n"); + /* Add the sh1 descriptor */ + memcpy(pdesc, rng_inst_sh1_desc, + sizeof(rng_inst_sh1_desc)); + } else { + debug("RNG - Instantiation of SH1 only\n"); + /* Modify the SH0 descriptor to instantiate only SH1 */ + desc[1] &= ~BM_ALGO_RNG_SH; + desc[1] |= ALGO_RNG_SH(1); + } + } + + /* Setup the descriptor size */ + desc[0] &= ~(0x3F); + desc[0] |= CAAM_HDR_DESCLEN(desc_len); +} + +static int jr_reset(void) +{ + /* + * Function reset the Job Ring HW + * Reset is done in 2 steps: + * - Flush all pending jobs (Set RESET bit) + * - Reset the Job Ring (Set RESET bit second time) + */ + u16 timeout = 10000; + u32 reg_val; + + /* Mask interrupts to poll for reset completion status */ + setbits_le32(CAAM_JRCFGR0_LS, BM_JRCFGR_LS_IMSK); + + /* Initiate flush (required prior to reset) */ + __raw_writel(JRCR_RESET, CAAM_JRCR0); + do { + reg_val = __raw_readl(CAAM_JRINTR0); + reg_val &= BM_JRINTR_HALT; + } while ((reg_val == JRINTR_HALT_ONGOING) && --timeout); + + if (!timeout || reg_val != JRINTR_HALT_DONE) { + printf("Failed to flush job ring\n"); + return ERROR_ANY; + } + + /* Initiate reset */ + timeout = 100; + __raw_writel(JRCR_RESET, CAAM_JRCR0); + do { + reg_val = __raw_readl(CAAM_JRCR0); + } while ((reg_val & JRCR_RESET) && --timeout); + + if (!timeout) { + printf("Failed to reset job ring\n"); + return ERROR_ANY; + } + + return 0; +} + +static int do_job(u32 *desc) +{ + int ret; + phys_addr_t p_desc = virt_to_phys(desc); + + if (__raw_readl(CAAM_IRSAR0) == 0) + return ERROR_ANY; + g_jrdata.inrings[0].desc = p_desc; + + flush_dcache_range((uintptr_t)g_jrdata.inrings & ALIGN_MASK, + ((uintptr_t)g_jrdata.inrings & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + flush_dcache_range((uintptr_t)desc & ALIGN_MASK, + ((uintptr_t)desc & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + + /* Inform HW that a new JR is available */ + __raw_writel(1, CAAM_IRJAR0); + while (__raw_readl(CAAM_ORSFR0) == 0) + ; + + flush_dcache_range((uintptr_t)g_jrdata.outrings & ALIGN_MASK, + ((uintptr_t)g_jrdata.outrings & ALIGN_MASK) + + ROUND(DESC_MAX_SIZE, ARCH_DMA_MINALIGN)); + + if (PTR2CAAMDMA(desc) == g_jrdata.outrings[0].desc) { + ret = g_jrdata.outrings[0].status; + } else { + dump_error(); + ret = ERROR_ANY; + } + + /* Acknowledge interrupt */ + setbits_le32(CAAM_JRINTR0, JRINTR_JRI); + + /* Remove the JR from the output list even if no JR caller found */ + __raw_writel(1, CAAM_ORJRR0); + + return ret; +} + +static int do_cfg_jrqueue(void) +{ + u32 value = 0; + phys_addr_t ip_base; + phys_addr_t op_base; + + /* check if already configured after relocation */ + if (g_jrdata.status == RING_RELOC_INIT) + return 0; + + /* + * jr configuration needs to be updated once, after relocation to ensure + * using the right buffers. + * When buffers are updated after relocation the flag RING_RELOC_INIT + * is used to prevent extra updates + */ + if (gd->flags & GD_FLG_RELOC) { + g_jrdata.inrings = (struct inring_entry *) + memalign(ARCH_DMA_MINALIGN, + ARCH_DMA_MINALIGN); + g_jrdata.outrings = (struct outring_entry *) + memalign(ARCH_DMA_MINALIGN, + ARCH_DMA_MINALIGN); + g_jrdata.desc = (u32 *) + memalign(ARCH_DMA_MINALIGN, ARCH_DMA_MINALIGN); + g_jrdata.status = RING_RELOC_INIT; + } else { + u32 align_idx = 0; + + /* Ensure 64bits buffers addresses alignment */ + if ((uintptr_t)g_jrdata.raw_addr & 0x7) + align_idx = 1; + g_jrdata.inrings = (struct inring_entry *) + (&g_jrdata.raw_addr[align_idx]); + g_jrdata.outrings = (struct outring_entry *) + (&g_jrdata.raw_addr[align_idx + 2]); + g_jrdata.desc = (u32 *)(&g_jrdata.raw_addr[align_idx + 4]); + g_jrdata.status = RING_EARLY_INIT; + } + + if (!g_jrdata.inrings || !g_jrdata.outrings) + return ERROR_ANY; + + /* Configure the HW Job Rings */ + ip_base = virt_to_phys((void *)g_jrdata.inrings); + op_base = virt_to_phys((void *)g_jrdata.outrings); + __raw_writel(ip_base, CAAM_IRBAR0); + __raw_writel(1, CAAM_IRSR0); + + __raw_writel(op_base, CAAM_ORBAR0); + __raw_writel(1, CAAM_ORSR0); + + setbits_le32(CAAM_JRINTR0, JRINTR_JRI); + + /* + * Configure interrupts but disable it: + * Optimization to generate an interrupt either when there are + * half of the job done or when there is a job done and + * 10 clock cycles elapse without new job complete + */ + value = 10 << BS_JRCFGR_LS_ICTT; + value |= (1 << BS_JRCFGR_LS_ICDCT) & BM_JRCFGR_LS_ICDCT; + value |= BM_JRCFGR_LS_ICEN; + value |= BM_JRCFGR_LS_IMSK; + __raw_writel(value, CAAM_JRCFGR0_LS); + + /* Enable deco watchdog */ + setbits_le32(CAAM_MCFGR, BM_MCFGR_WDE); + + return 0; +} + +static void do_clear_rng_error(void) +{ + u32 val; + + val = __raw_readl(CAAM_RTMCTL); + + if (val & (RTMCTL_ERR | RTMCTL_FCT_FAIL)) { + setbits_le32(CAAM_RTMCTL, RTMCTL_ERR); + val = __raw_readl(CAAM_RTMCTL); + } +} + +static int do_instantiation(void) +{ + int ret = ERROR_ANY; + u32 cha_vid_ls; + u32 ent_delay; + u32 status; + + if (!g_jrdata.desc) { + printf("%d: CAAM Descriptor allocation error\n", __LINE__); + return ERROR_ANY; + } + + cha_vid_ls = __raw_readl(CAAM_CHAVID_LS); + + /* + * If SEC has RNG version >= 4 and RNG state handle has not been + * already instantiated, do RNG instantiation + */ + if (((cha_vid_ls & BM_CHAVID_LS_RNGVID) >> BS_CHAVID_LS_RNGVID) < 4) { + printf("%d: RNG already instantiated\n", __LINE__); + return 0; + } + + ent_delay = TRNG_SDCTL_ENT_DLY_MIN; + + do { + /* Read the CAAM RNG status */ + status = __raw_readl(CAAM_RDSTA); + + if ((status & RDSTA_IF0) != RDSTA_IF0) { + /* Configure the RNG entropy delay */ + kick_trng(ent_delay); + ent_delay += 400; + } + + do_clear_rng_error(); + + if ((status & (RDSTA_IF0 | RDSTA_IF1)) != + (RDSTA_IF0 | RDSTA_IF1)) { + /* Prepare the instantiation descriptor */ + do_inst_desc(g_jrdata.desc, status); + + /* Run Job */ + ret = do_job(g_jrdata.desc); + + if (ret == ERROR_ANY) { + /* CAAM JR failure ends here */ + printf("RNG Instantiation error\n"); + goto end_instantation; + } + } else { + ret = SUCCESS; + printf("RNG instantiation done (%d)\n", ent_delay); + goto end_instantation; + } + } while (ent_delay < TRNG_SDCTL_ENT_DLY_MAX); + + printf("RNG Instantation Failure - Entropy delay (%d)\n", ent_delay); + ret = ERROR_ANY; + +end_instantation: + return ret; +} + +static void rng_init(void) +{ + int ret; + + ret = jr_reset(); + if (ret != SUCCESS) { + printf("Error CAAM JR reset\n"); + return; + } + + ret = do_instantiation(); + + if (ret != SUCCESS) + printf("Error do_instantiation\n"); + + jr_reset(); + + return; +} + diff --git a/drivers/crypto/fsl_caam_internal.h b/drivers/crypto/fsl_caam_internal.h new file mode 100644 index 00000000000..a59f13a25c8 --- /dev/null +++ b/drivers/crypto/fsl_caam_internal.h @@ -0,0 +1,259 @@ +/* + * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * Copyright 2018 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CAAM_INTERNAL_H__ +#define __CAAM_INTERNAL_H__ + +/* 4kbyte pages */ +#define CAAM_SEC_RAM_START_ADDR CAAM_ARB_BASE_ADDR + +#define SEC_MEM_PAGE0 CAAM_SEC_RAM_START_ADDR +#define SEC_MEM_PAGE1 (CAAM_SEC_RAM_START_ADDR + 0x1000) +#define SEC_MEM_PAGE2 (CAAM_SEC_RAM_START_ADDR + 0x2000) +#define SEC_MEM_PAGE3 (CAAM_SEC_RAM_START_ADDR + 0x3000) + +/* Configuration and special key registers */ +#define CAAM_MCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x0004) +#define CAAM_SCFGR (CONFIG_SYS_FSL_SEC_ADDR + 0x000c) +#define CAAM_JR0MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0010) +#define CAAM_JR1MIDR (CONFIG_SYS_FSL_SEC_ADDR + 0x0018) +#define CAAM_DECORR (CONFIG_SYS_FSL_SEC_ADDR + 0x009c) +#define CAAM_DECO0MID (CONFIG_SYS_FSL_SEC_ADDR + 0x00a0) +#define CAAM_DAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0120) +#define CAAM_DRR (CONFIG_SYS_FSL_SEC_ADDR + 0x0124) +#define CAAM_JDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0400) +#define CAAM_TDKEKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0420) +#define CAAM_TDSKR (CONFIG_SYS_FSL_SEC_ADDR + 0x0440) +#define CAAM_SKNR (CONFIG_SYS_FSL_SEC_ADDR + 0x04e0) +#define CAAM_SMSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FB4) +#define CAAM_STA (CONFIG_SYS_FSL_SEC_ADDR + 0x0FD4) +#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) +#define CAAM_CHAVID_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x0FEC) +#define CAAM_FAR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC0) +#define CAAM_FAMR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FC8) +#define CAAM_FADR (CONFIG_SYS_FSL_SEC_ADDR + 0x0FCC) + +/* RNG registers */ +#define CAAM_RTMCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0600) +#define CAAM_RTSCMISC (CONFIG_SYS_FSL_SEC_ADDR + 0x0604) +#define CAAM_RTPKRRNG (CONFIG_SYS_FSL_SEC_ADDR + 0x0608) +#define CAAM_RTPKRMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x060C) +#define CAAM_RTSDCTL (CONFIG_SYS_FSL_SEC_ADDR + 0x0610) +#define CAAM_RTFRQMIN (CONFIG_SYS_FSL_SEC_ADDR + 0x0618) +#define CAAM_RTFRQMAX (CONFIG_SYS_FSL_SEC_ADDR + 0x061C) +#define CAAM_RTSCML (CONFIG_SYS_FSL_SEC_ADDR + 0x0620) +#define CAAM_RTSCR1L (CONFIG_SYS_FSL_SEC_ADDR + 0x0624) +#define CAAM_RTSCR2L (CONFIG_SYS_FSL_SEC_ADDR + 0x0628) +#define CAAM_RTSCR3L (CONFIG_SYS_FSL_SEC_ADDR + 0x062C) +#define CAAM_RTSCR4L (CONFIG_SYS_FSL_SEC_ADDR + 0x0630) +#define CAAM_RTSCR5L (CONFIG_SYS_FSL_SEC_ADDR + 0x0634) +#define CAAM_RTSCR6PL (CONFIG_SYS_FSL_SEC_ADDR + 0x0638) +#define CAAM_RTSTATUS (CONFIG_SYS_FSL_SEC_ADDR + 0x063C) +#define CAAM_RDSTA (CONFIG_SYS_FSL_SEC_ADDR + 0x06C0) + +/* Job Ring 0 registers */ +#define CAAM_IRBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1004) +#define CAAM_IRSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x100c) +#define CAAM_IRSAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1014) +#define CAAM_IRJAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x101c) +#define CAAM_ORBAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1024) +#define CAAM_ORSR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x102c) +#define CAAM_ORJRR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1034) +#define CAAM_ORSFR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x103c) +#define CAAM_JRSTAR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1044) +#define CAAM_JRINTR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x104c) +#define CAAM_JRCFGR0_MS (CONFIG_SYS_FSL_SEC_ADDR + 0x1050) +#define CAAM_JRCFGR0_LS (CONFIG_SYS_FSL_SEC_ADDR + 0x1054) +#define CAAM_IRRIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x105c) +#define CAAM_ORWIR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1064) +#define CAAM_JRCR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x106c) +#define CAAM_SMCJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10f4) +#define CAAM_SMCSJR0 (CONFIG_SYS_FSL_SEC_ADDR + 0x10fc) +#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16) +#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16) +#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16) +#define CAAM_SMAPJR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1114) +#define CAAM_SMAG2JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x1118) +#define CAAM_SMAG1JR0_PRTN1 (CONFIG_SYS_FSL_SEC_ADDR + 0x111c) +#define CAAM_SMPO (CONFIG_SYS_FSL_SEC_ADDR + 0x1fbc) + +#define DESC_MAX_SIZE (0x40) /* Descriptor max size */ +#define JRCFG_LS_IMSK (0x01) /* Interrupt Mask */ +#define JR_MID (0x02) /* Matches ROM configuration */ +#define KS_G1 BIT(JR_MID) /* CAAM only */ +#define PERM (0x0000B008) /* Clear on release, lock SMAP, + * lock SMAG and group 1 Blob + */ + +#define CMD_PAGE_ALLOC (0x1) +#define CMD_PAGE_DEALLOC (0x2) +#define CMD_PART_DEALLOC (0x3) +#define CMD_INQUIRY (0x5) +#define PAGE(x) (x << 16) +#define PARTITION(x) (x << 8) + +#define SMCSJR_AERR (3 << 12) +#define SMCSJR_CERR (3 << 14) +#define CMD_COMPLETE (3 << 14) + +#define SMCSJR_PO (3 << 6) +#define PAGE_AVAILABLE (0) +#define PAGE_OWNED (3 << 6) + +#define PARTITION_OWNER(x) (0x3 << (x*2)) + +#define CAAM_BUSY_MASK (0x00000001) /* BUSY from status reg */ +#define CAAM_IDLE_MASK (0x00000002) /* IDLE from status reg */ +#define CAAM_MCFGR_SWRST BIT(31) /* CAAM SW reset */ +#define CAAM_MCFGR_DMARST BIT(28) /* CAAM DMA reset */ + +#define JOB_RING_ENTRIES (1) +#define JOB_RING_STS (0xF << 28) + +/** OSC_DIV in RNG trim fuses */ +#define RNG_TRIM_OSC_DIV (0) +/** ENT_DLY multiplier in RNG trim fuses */ +#define TRNG_SDCTL_ENT_DLY_MIN (3200) +#define TRNG_SDCTL_ENT_DLY_MAX (4800) + +#define RTMCTL_PGM BIT(16) +#define RTMCTL_ERR BIT(12) +#define RTMCTL_RST BIT(6) +#define RTMCTL_ACC BIT(5) +#define RDSTA_IF0 (1) +#define RDSTA_IF1 (2) +#define RDSTA_SKVN BIT(30) +#define JRCR_RESET (1) +#define RTMCTL_FCT_FAIL BIT(8) + +#define BS_TRNG_ENT_DLY (16) +#define BM_TRNG_ENT_DLY (0xffff << BS_TRNG_ENT_DLY) +#define BM_TRNG_SAMP_MODE (3) +#define TRNG_SAMP_MODE_RAW_ES_SC (1) +#define BS_JRINTR_HALT (2) +#define BM_JRINTR_HALT (0x3 << BS_JRINTR_HALT) +#define JRINTR_HALT_ONGOING (0x1 << BS_JRINTR_HALT) +#define JRINTR_HALT_DONE (0x2 << BS_JRINTR_HALT) +#define JRINTR_JRI (0x1) +#define BS_JRCFGR_LS_ICTT (16) +#define BM_JRCFGR_LS_ICTT (0xFFFF << BS_JRCFGR_LS_ICTT) +#define BS_JRCFGR_LS_ICDCT (8) +#define BM_JRCFGR_LS_ICDCT (0xFF << BS_JRCFGR_LS_ICDCT) +#define BS_JRCFGR_LS_ICEN (1) +#define BM_JRCFGR_LS_ICEN (0x1 << BS_JRCFGR_LS_ICEN) +#define BS_JRCFGR_LS_IMSK (0) +#define BM_JRCFGR_LS_IMSK (0x1 << BS_JRCFGR_LS_IMSK) +#define BS_CHAVID_LS_RNGVID (16) +#define BM_CHAVID_LS_RNGVID (0xF << BS_CHAVID_LS_RNGVID) +#define BS_MCFGR_WDE (30) +#define BM_MCFGR_WDE (0x1 << BS_MCFGR_WDE) + +typedef enum { + PAGE_0, + PAGE_1, + PAGE_2, + PAGE_3, +} page_num_e; + +typedef enum { + PARTITION_0, + PARTITION_1, + PARTITION_2, + PARTITION_3, + PARTITION_4, + PARTITION_5, + PARTITION_6, + PARTITION_7, +} partition_num_e; + + +/* + * Local defines + */ +/* arm v7 need 64 align */ +#define ALIGN_MASK ~(ARCH_DMA_MINALIGN - 1) +/* caam dma and pointer conversion for arm and arm64 architectures */ +#ifdef CONFIG_IMX_CONFIG + #define PTR2CAAMDMA(x) (u32)((uintptr_t)(x) & 0xffffffff) + #define CAAMDMA2PTR(x) (uintptr_t)((x) & 0xffffffff) +#else + #define PTR2CAAMDMA(x) (uintptr_t)(x) + #define CAAMDMA2PTR(x) (uintptr_t)(x) +#endif +#define RING_EARLY_INIT (0x01) +#define RING_RELOC_INIT (0x02) + +#define CAAM_HDR_CTYPE (0x16u << 27) +#define CAAM_HDR_ONE BIT(23) +#define CAAM_HDR_START_INDEX(x) (((x) & 0x3F) << 16) +#define CAAM_HDR_DESCLEN(x) ((x) & 0x3F) +#define CAAM_PROTOP_CTYPE (0x10u << 27) + +/* State Handle */ +#define BS_ALGO_RNG_SH (4) +#define BM_ALGO_RNG_SH (0x3 << BS_ALGO_RNG_SH) +#define ALGO_RNG_SH(id) (((id) << BS_ALGO_RNG_SH) & BM_ALGO_RNG_SH) + +/* Secure Key */ +#define BS_ALGO_RNG_SK (12) +#define BM_ALGO_RNG_SK BIT(BS_ALGO_RNG_SK) + +/* State */ +#define BS_ALGO_RNG_AS (2) +#define BM_ALGO_RNG_AS (0x3 << BS_ALGO_RNG_AS) +#define ALGO_RNG_GENERATE (0x0 << BS_ALGO_RNG_AS) +#define ALGO_RNG_INSTANTIATE BIT(BS_ALGO_RNG_AS) + +/* Prediction Resistance */ +#define ALGO_RNG_PR BIT(1) + +#define CAAM_C1_RNG ((0x50 << 16) | (2 << 24)) + +#define BS_JUMP_LOCAL_OFFSET (0) +#define BM_JUMP_LOCAL_OFFSET (0xFF << BS_JUMP_LOCAL_OFFSET) + +#define CAAM_C1_JUMP ((0x14u << 27) | (1 << 25)) +#define CAAM_JUMP_LOCAL (0 << 20) +#define CAAM_JUMP_TST_ALL_COND_TRUE (0 << 16) +#define CAAM_JUMP_OFFSET(off) (((off) << BS_JUMP_LOCAL_OFFSET) \ + & BM_JUMP_LOCAL_OFFSET) + +#define CAAM_C0_LOAD_IMM ((0x2 << 27) | (1 << 23)) +#define CAAM_DST_CLEAR_WRITTEN (0x8 << 16) + +#define RNG_DESC_SH0_SIZE (ARRAY_SIZE(rng_inst_sh0_desc)) +#define RNG_DESC_SH1_SIZE (ARRAY_SIZE(rng_inst_sh1_desc)) +#define RNG_DESC_KEYS_SIZE (ARRAY_SIZE(rng_inst_load_keys)) +#define RNG_DESC_MAX_SIZE (RNG_DESC_SH0_SIZE + \ + RNG_DESC_SH1_SIZE + \ + RNG_DESC_KEYS_SIZE) + +#endif /* __CAAM_INTERNAL_H__ */ diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig index a5f5524fbec..64c1323c829 100644 --- a/drivers/ddr/imx/imx8m/Kconfig +++ b/drivers/ddr/imx/imx8m/Kconfig @@ -32,8 +32,19 @@ config SAVED_DRAM_TIMING_BASE config IMX8M_DRAM_INLINE_ECC bool "imx8mp inline ECC" - depends on IMX8MP && IMX8M_LPDDR4 + depends on IMX8MP help Select this config if you want to use inline ecc feature for imx8mp-evk board. + +config IMX8M_VDD_SOC_850MV + bool "imx8mp change the vdd_soc voltage to 850mv" + depends on IMX8MP + +config IMX8M_LPDDR4_FREQ0_2400MTS + bool "imx8m PDDR4 freq0 change from 4000MTS to 2400MTS" + +config IMX8M_4G_LPDDR4 + bool "imx8m 4GB LPDDR4" + endmenu diff --git a/drivers/ddr/imx/imx8m/ddr_init.c b/drivers/ddr/imx/imx8m/ddr_init.c index b70bcc383fa..57331649ac2 100644 --- a/drivers/ddr/imx/imx8m/ddr_init.c +++ b/drivers/ddr/imx/imx8m/ddr_init.c @@ -96,7 +96,7 @@ int ddr_init(struct dram_timing_info *dram_timing) unsigned int tmp, initial_drate, target_freq; int ret; - debug("DDRINFO: start DRAM init\n"); + printf("DDRINFO: start DRAM init\n"); /* Step1: Follow the power up procedure */ if (is_imx8mq()) { @@ -119,6 +119,7 @@ int ddr_init(struct dram_timing_info *dram_timing) initial_drate = dram_timing->fsp_msg[0].drate; /* default to the frequency point 0 clock */ + printf("DDRINFO: DRAM rate %dMTS\n", initial_drate); ddrphy_init_set_dfi_clk(initial_drate); /* D-aasert the presetn */ @@ -185,7 +186,7 @@ int ddr_init(struct dram_timing_info *dram_timing) tmp = reg32_read(DDRPHY_CalBusy(0)); } while ((tmp & 0x1)); - debug("DDRINFO:ddrphy calibration done\n"); + printf("DDRINFO:ddrphy calibration done\n"); /* Step15: Set SWCTL.sw_done to 0 */ reg32_write(DDRC_SWCTL(0), 0x00000000); @@ -238,7 +239,7 @@ int ddr_init(struct dram_timing_info *dram_timing) /* enable port 0 */ reg32_write(DDRC_PCTRL_0(0), 0x00000001); - debug("DDRINFO: ddrmix config done\n"); + printf("DDRINFO: ddrmix config done\n"); board_dram_ecc_scrub(); diff --git a/drivers/ddr/imx/imx8m/ddrphy_utils.c b/drivers/ddr/imx/imx8m/ddrphy_utils.c index 0f8baefb1f8..326b92d784a 100644 --- a/drivers/ddr/imx/imx8m/ddrphy_utils.c +++ b/drivers/ddr/imx/imx8m/ddrphy_utils.c @@ -104,7 +104,7 @@ int wait_ddrphy_training_complete(void) debug("Training PASS\n"); return 0; } else if (mail == 0xff) { - debug("Training FAILED\n"); + printf("Training FAILED\n"); return -1; } } diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index da988f6bb66..bccb501d84b 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -129,10 +129,10 @@ static int mxs_dma_enable(int channel) return 0; } - pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); - if (pdesc == NULL) + if (list_empty(&pchan->active)) return -EFAULT; + pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node); if (pchan->flags & MXS_DMA_FLAGS_BUSY) { if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN)) return 0; @@ -578,6 +578,14 @@ void mxs_dma_init(void) struct mxs_apbh_regs *apbh_regs = (struct mxs_apbh_regs *)MXS_APBH_BASE; + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_APBHDMA)) { + printf("NAND APBH-DMA@0x%x is fused, disable it\n", + MXS_APBH_BASE); + return; + } + } + mxs_reset_block(&apbh_regs->hw_apbh_ctrl0_reg); #ifdef CONFIG_APBH_DMA_BURST8 diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig index 2d1836a80e0..588d3741142 100644 --- a/drivers/fastboot/Kconfig +++ b/drivers/fastboot/Kconfig @@ -11,6 +11,7 @@ config USB_FUNCTION_FASTBOOT default y if ARCH_SUNXI && USB_MUSB_GADGET select FASTBOOT select USB_GADGET_DOWNLOAD + select USB_GADGET_OS_DESCRIPTORS help This enables the USB part of the fastboot gadget. @@ -74,16 +75,63 @@ config FASTBOOT_FLASH config FASTBOOT_UUU_SUPPORT bool "Enable FASTBOOT i.MX UUU special command" - default n + default y if ARCH_MX7 || ARCH_MX6 || ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7ULP + select FSL_FASTBOOT + select FAT_WRITE + select CMD_GPT + select RANDOM_UUID + select CMD_GPT_RENAME + select CONSOLE_MUX + select SYS_STDIO_DEREGISTER help The fastboot protocol includes "UCmd" and "ACmd" command. Be aware that you provide full access to any U-Boot command, including working with memory and may open a huge backdoor, when enabling this option. +config FSL_FASTBOOT + bool "Enable FSL fastboot support" + depends on FASTBOOT_FLASH + help + This enables FSL implementation for Android fastboot. + +config ANDROID_RECOVERY + bool "Enable the recovery boot function" + depends on FSL_FASTBOOT + help + This enables the Android Recovery boot function. + +config CMD_BOOTA + bool "Enable the boota command" + default y + depends on FSL_FASTBOOT + depends on ANDROID_SUPPORT || ANDROID_AUTO_SUPPORT || ANDROID_THINGS_SUPPORT + help + This enables the boota command for booting android images. + +config BCB_SUPPORT + bool "Enable the boot control block support" + depends on FSL_FASTBOOT + help + This enables the boot control block support for android reboot command + +config FASTBOOT_LOCK + bool "Enable the lock and unlock feature to the partitions" + depends on FSL_FASTBOOT + help + This enables the lock support for android flashing command + +config FASTBOOT_USB_DEV + int "USB controller number" + default 0 + help + Some boards have USB OTG controller other than 0. Define this + option so it can be used in compiled environment (e.g. in + CONFIG_BOOTCOMMAND). + choice prompt "Flash provider for FASTBOOT" - depends on FASTBOOT_FLASH + depends on FASTBOOT_FLASH && !FSL_FASTBOOT config FASTBOOT_FLASH_MMC bool "FASTBOOT on MMC" diff --git a/drivers/fastboot/Makefile b/drivers/fastboot/Makefile index 048af5aa823..902da22e67e 100644 --- a/drivers/fastboot/Makefile +++ b/drivers/fastboot/Makefile @@ -1,7 +1,11 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += fb_common.o -obj-y += fb_getvar.o +ifndef CONFIG_FSL_FASTBOOT obj-y += fb_command.o +obj-y += fb_getvar.o obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fb_mmc.o obj-$(CONFIG_FASTBOOT_FLASH_NAND) += fb_nand.o +else +obj-y += fb_fsl/ +endif diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index cbcc3683c47..140f9498377 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -16,6 +16,7 @@ #include #include #include +#include /** * fastboot_buf_addr - base address of the fastboot download buffer @@ -136,12 +137,22 @@ void fastboot_boot(void) run_command(s, CMD_FLAG_ENV); } else { static char boot_addr_start[20]; +#ifdef CONFIG_FSL_FASTBOOT + static char *const bootm_args[] = { + "boota", boot_addr_start, NULL + }; + + snprintf(boot_addr_start, sizeof(boot_addr_start) - 1, + "0x%p", (void *)image_load_addr); +#else static char *const bootm_args[] = { "bootm", boot_addr_start, NULL }; snprintf(boot_addr_start, sizeof(boot_addr_start) - 1, "0x%p", fastboot_buf_addr); +#endif + printf("Booting kernel at %s...\n\n\n", boot_addr_start); do_bootm(NULL, 0, 2, bootm_args); @@ -178,8 +189,13 @@ void fastboot_set_progress_callback(void (*progress)(const char *msg)) */ void fastboot_init(void *buf_addr, u32 buf_size) { +#ifdef CONFIG_FSL_FASTBOOT + fastboot_buf_addr = buf_addr ? buf_addr : + (void *)env_get_ulong("fastboot_buffer", 16, CONFIG_FASTBOOT_BUF_ADDR); +#else fastboot_buf_addr = buf_addr ? buf_addr : (void *)CONFIG_FASTBOOT_BUF_ADDR; +#endif fastboot_buf_size = buf_size ? buf_size : CONFIG_FASTBOOT_BUF_SIZE; fastboot_set_progress_callback(NULL); } diff --git a/drivers/fastboot/fb_fsl/Makefile b/drivers/fastboot/fb_fsl/Makefile new file mode 100644 index 00000000000..6a88aee1809 --- /dev/null +++ b/drivers/fastboot/fb_fsl/Makefile @@ -0,0 +1,14 @@ +# +# Copyright 2019 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ccflags-y += -I./lib + +ifndef CONFIG_SPL_BUILD +obj-y += fb_fsl_dev.o fb_fsl_boot.o fb_fsl_command.o fb_fsl_common.o fb_fsl_getvar.o fb_fsl_partitions.o +obj-$(CONFIG_FASTBOOT_LOCK) += fastboot_lock_unlock.o +obj-$(CONFIG_BCB_SUPPORT) += command.o bcb.o +obj-$(CONFIG_VIRTUAL_AB_SUPPORT) += fb_fsl_virtual_ab.o +endif diff --git a/drivers/fastboot/fb_fsl/bcb.c b/drivers/fastboot/fb_fsl/bcb.c new file mode 100644 index 00000000000..7226790ad72 --- /dev/null +++ b/drivers/fastboot/fb_fsl/bcb.c @@ -0,0 +1,169 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + */ + +#include +#include +#include +#include +#include +#include +#include "bcb.h" +#include "command.h" +#define ALIGN_BYTES 64 /*armv7 cache line need 64 bytes aligned */ + +static ulong get_block_size(char *ifname, int dev) +{ + struct blk_desc *dev_desc = NULL; + + dev_desc = blk_get_dev(ifname, dev); + if (dev_desc == NULL) { + printf("Block device %s %d not supported\n", ifname, dev); + return 0; + } + + return dev_desc->blksz; +} + +static int do_write(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + char *ep; + struct blk_desc *dev_desc = NULL; + int dev; + int part = 0; + struct disk_partition part_info; + ulong offset = 0u; + ulong limit = 0u; + void *addr; + uint blk; + uint cnt; + + if (argc != 6) { + cmd_usage(cmdtp); + return 1; + } + + dev = (int)simple_strtoul(argv[2], &ep, 16); + if (*ep) { + if (*ep != ':') { + printf("Invalid block device %s\n", argv[2]); + return 1; + } + part = (int)simple_strtoul(++ep, NULL, 16); + } + + dev_desc = blk_get_dev(argv[1], dev); + if (dev_desc == NULL) { + printf("Block device %s %d not supported\n", argv[1], dev); + return 1; + } + + addr = (void *)simple_strtoul(argv[3], NULL, 16); + blk = simple_strtoul(argv[4], NULL, 16); + cnt = simple_strtoul(argv[5], NULL, 16); + + if (part != 0) { + if (part_get_info(dev_desc, part, &part_info)) { + printf("Cannot find partition %d\n", part); + return 1; + } + offset = part_info.start; + limit = part_info.size; + } else { + /* Largest address not available in block_dev_desc_t. */ + limit = ~0; + } + + if (cnt + blk > limit) { + printf("Write out of range\n"); + return 1; + } + + if (blk_dwrite(dev_desc, offset + blk, cnt, addr) != cnt) { + printf("Error writing blocks\n"); + return 1; + } + + return 0; +} + +U_BOOT_CMD( + write, 6, 0, do_write, + "write binary data to a partition", + " addr blk# cnt" +); + +int bcb_rw_block(bool bread, char **ppblock, + uint *pblksize, char *pblock_write, uint offset, uint size) +{ + int ret; + char *argv[6]; + char addr_str[20]; + char cnt_str[8]; + char devpart_str[8]; + char block_begin_str[8]; + ulong blk_size = 0; + uint blk_begin = 0; + uint blk_end = 0; + uint block_cnt = 0; + char *p_block = NULL; + unsigned int mmc_id; + + if (bread && ((ppblock == NULL) || (pblksize == NULL))) + return -1; + + if (!bread && (pblock_write == NULL)) + return -1; + + mmc_id = mmc_get_env_dev(); + blk_size = get_block_size("mmc", mmc_id); + if (blk_size == 0) { + printf("bcb_rw_block, get_block_size return 0\n"); + return -1; + } + + blk_begin = offset/blk_size; + blk_end = (offset + size)/blk_size; + block_cnt = 1 + (blk_end - blk_begin); + + sprintf(devpart_str, "0x%x:0x%x", mmc_id, + fastboot_flash_find_index(FASTBOOT_PARTITION_MISC)); + sprintf(block_begin_str, "0x%x", blk_begin); + sprintf(cnt_str, "0x%x", block_cnt); + + argv[0] = "rw"; /* not care */ + argv[1] = "mmc"; + argv[2] = devpart_str; + argv[3] = addr_str; + argv[4] = block_begin_str; + argv[5] = cnt_str; + + if (bread) { + p_block = (char *)memalign(ALIGN_BYTES, blk_size * block_cnt); + if (NULL == p_block) { + printf("bcb_rw_block, memalign %d bytes failed\n", + (int)(blk_size * block_cnt)); + return -1; + } + sprintf(addr_str, "0x%x", (unsigned int)(uintptr_t)p_block); + ret = do_raw_read(NULL, 0, 6, argv); + if (ret) { + free(p_block); + printf("do_raw_read failed, ret %d\n", ret); + return -1; + } + + *ppblock = p_block; + *pblksize = (uint)blk_size; + } else { + sprintf(addr_str, "0x%x", (unsigned int)(uintptr_t)pblock_write); + ret = do_write(NULL, 0, 6, argv); + if (ret) { + printf("do_write failed, ret %d\n", ret); + return -1; + } + } + return 0; +} diff --git a/drivers/fastboot/fb_fsl/bcb.h b/drivers/fastboot/fb_fsl/bcb.h new file mode 100644 index 00000000000..3b72eb15d14 --- /dev/null +++ b/drivers/fastboot/fb_fsl/bcb.h @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + */ + +#ifndef BCB_H +#define BCB_H +#include +#include +#include + +#define FASTBOOT_BCB_CMD "bootonce-bootloader" +#ifdef CONFIG_ANDROID_RECOVERY +#define RECOVERY_BCB_CMD "boot-recovery" +#define RECOVERY_FASTBOOT_ARG "recovery\n--fastboot" +#endif + +/* bcb struct is defined in include/android_bootloader_message.h */ + +/* start from bootloader_message_ab.slot_suffix[BOOTCTRL_IDX] */ +#define BOOTCTRL_IDX 0 +#define MISC_COMMAND_IDX 0 +#define BOOTCTRL_OFFSET \ + (u32)(&(((struct bootloader_message_ab *)0)->slot_suffix[BOOTCTRL_IDX])) +#define MISC_COMMAND \ + (u32)(uintptr_t)(&(((struct bootloader_message *)0)->command[MISC_COMMAND_IDX])) + +#ifdef CONFIG_ANDROID_RECOVERY +#define RECOVERY_OPTIONS\ + (u32)(uintptr_t)(&(((struct bootloader_message *)0)->recovery[0])) +#endif +int bcb_rw_block(bool bread, char **ppblock, + uint *pblksize, char *pblock_write, uint offset, uint size); + +int bcb_write_command(char *bcb_command); +int bcb_read_command(char *command); + +#ifdef CONFIG_ANDROID_RECOVERY +int bcb_write_recovery_opt(char *opts); +#endif +#endif diff --git a/drivers/fastboot/fb_fsl/command.c b/drivers/fastboot/fb_fsl/command.c new file mode 100644 index 00000000000..d3fb9f03dfc --- /dev/null +++ b/drivers/fastboot/fb_fsl/command.c @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + */ + +#include +#include +#include "bcb.h" + +int bcb_read_command(char *command) +{ + int ret = 0; + char *p_block = NULL; + uint offset_in_block = 0; + uint blk_size = 0; + + if (command == NULL) + return -1; + + ret = bcb_rw_block(true, &p_block, &blk_size, NULL, MISC_COMMAND, 32); + if (ret) { + printf("read_bootctl, bcb_rw_block read failed\n"); + return -1; + } + + offset_in_block = MISC_COMMAND%blk_size; + memcpy(command, p_block + offset_in_block, 32); + free(p_block); + + return 0; +} +int bcb_write_command(char *bcb_command) +{ + int ret = 0; + char *p_block = NULL; + uint offset_in_block = 0; + uint blk_size = 0; + + if (bcb_command == NULL) + return -1; + + + ret = bcb_rw_block(true, &p_block, &blk_size, NULL, MISC_COMMAND, 32); + if (ret) { + printf("write_bootctl, bcb_rw_block read failed\n"); + return -1; + } + + offset_in_block = MISC_COMMAND%blk_size; + memcpy(p_block + offset_in_block, bcb_command, 32); + + ret = bcb_rw_block(false, NULL, NULL, p_block, MISC_COMMAND, 32); + if (ret) { + free(p_block); + printf("write_bootctl, bcb_rw_block write failed\n"); + return -1; + } + + free(p_block); + return 0; +} + +#ifdef CONFIG_ANDROID_RECOVERY +int bcb_write_recovery_opt(char *opts) +{ + int ret = 0; + char *p_block = NULL; + uint offset_in_block = 0; + uint blk_size = 0; + + if (opts == NULL) + return -1; + + + ret = bcb_rw_block(true, &p_block, &blk_size, NULL, RECOVERY_OPTIONS, 32); + if (ret) { + printf("write_bootctl, bcb_rw_block read failed\n"); + return -1; + } + + offset_in_block = RECOVERY_OPTIONS%blk_size; + memcpy(p_block + offset_in_block, opts, 32); + + ret = bcb_rw_block(false, NULL, NULL, p_block, RECOVERY_OPTIONS, 32); + if (ret) { + free(p_block); + printf("write_bootctl, bcb_rw_block write failed\n"); + return -1; + } + + free(p_block); + return 0; +} +#endif diff --git a/drivers/fastboot/fb_fsl/fastboot_lock_unlock.c b/drivers/fastboot/fb_fsl/fastboot_lock_unlock.c new file mode 100644 index 00000000000..afe9302344d --- /dev/null +++ b/drivers/fastboot/fb_fsl/fastboot_lock_unlock.c @@ -0,0 +1,671 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fastboot_lock_unlock.h" +#include +#include +#include +#ifdef CONFIG_IMX_TRUSTY_OS +#include +#include +#endif + +#include + +#ifdef FASTBOOT_ENCRYPT_LOCK + +#include +#include + +//Encrypted data is 80bytes length. +#define ENDATA_LEN 80 + +#endif + +#ifdef CONFIG_AVB_WARNING_LOGO +#include "lcd.h" +#include "video.h" +#include "dm/uclass.h" +#include "fsl_avb_logo.h" +#include "video_link.h" +#include "video_console.h" +#include "video_font_data.h" +#endif + +int fastboot_flash_find_index(const char *name); + +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_ARM64) +#define IVT_HEADER_MAGIC 0xD1 +#define IVT_HDR_LEN 0x20 +#define HAB_MAJ_VER 0x40 +#define HAB_MAJ_MASK 0xF0 + +bool tos_flashed; + +static bool tos_ivt_check(ulong start_addr, int ivt_offset) { + const struct ivt *ivt_initial = NULL; + const uint8_t *start = (const uint8_t *)start_addr; + + if (start_addr & 0x3) { + puts("Error: tos's start address is not 4 byte aligned\n"); + return false; + } + + ivt_initial = (const struct ivt *)(start + ivt_offset); + + const struct ivt_header *ivt_hdr = &ivt_initial->hdr; + + if ((ivt_hdr->magic == IVT_HEADER_MAGIC && \ + (be16_to_cpu(ivt_hdr->length) == IVT_HDR_LEN) && \ + (ivt_hdr->version & HAB_MAJ_MASK) == HAB_MAJ_VER) && \ + (ivt_initial->entry != 0x0) && \ + (ivt_initial->reserved1 == 0x0) && \ + (ivt_initial->self == (uint32_t)ivt_initial) && \ + (ivt_initial->csf != 0x0) && \ + (ivt_initial->reserved2 == 0x0)) { + if (ivt_initial->dcd != 0x0) + return false; + else + return true; + } + + return false; +} + +bool valid_tos() { + /* + * If enabled SECURE_BOOT then use HAB to verify tos. + * Or check the IVT only. + */ + bool valid = false; +#ifdef CONFIG_IMX_HAB + if (is_hab_enabled()) { + valid = authenticate_image(TRUSTY_OS_ENTRY, TRUSTY_OS_PADDED_SZ); + } else +#endif + valid = tos_ivt_check(TRUSTY_OS_ENTRY, TRUSTY_OS_PADDED_SZ); + + if (valid) { + tos_flashed = true; + return true; + } else { + tos_flashed = false; + return false; + } +} + +#endif + +#if !defined(FASTBOOT_ENCRYPT_LOCK) || defined(NON_SECURE_FASTBOOT) + +/* + * This will return FASTBOOT_LOCK, FASTBOOT_UNLOCK or FASTBOOT_ERROR + */ +#ifndef CONFIG_IMX_TRUSTY_OS +static FbLockState decrypt_lock_store(unsigned char* bdata) { + if (!strncmp((const char *)bdata, "locked", strlen("locked"))) + return FASTBOOT_LOCK; + else if (!strncmp((const char *)bdata, "unlocked", strlen("unlocked"))) + return FASTBOOT_UNLOCK; + else + return FASTBOOT_LOCK_ERROR; +} +static inline int encrypt_lock_store(FbLockState lock, unsigned char* bdata) { + if (FASTBOOT_LOCK == lock) + strncpy((char *)bdata, "locked", strlen("locked") + 1); + else if (FASTBOOT_UNLOCK == lock) + strncpy((char *)bdata, "unlocked", strlen("unlocked") + 1); + else + return -1; + return 0; +} +#endif +#else +static u8 skeymod[] = { + 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 +}; + +static int sha1sum(unsigned char* data, int len, unsigned char* output) { + struct hash_algo *algo; + void *buf; + if (hash_lookup_algo("sha1", &algo)) { + printf("error in lookup sha1 algo!\n"); + return -1; + } + buf = map_sysmem((ulong)data, len); + algo->hash_func_ws(buf, len, output, algo->chunk_size); + unmap_sysmem(buf); + + return algo->digest_size; + +} + +static int generate_salt(unsigned char* salt) { + unsigned long time = get_timer(0); + return sha1sum((unsigned char *)&time, sizeof(unsigned long), salt); + +} + +static __maybe_unused FbLockState decrypt_lock_store(unsigned char *bdata) { + int p = 0, ret; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, plain_data, ENDATA_LEN); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, keymod, 16); + + memcpy(keymod, skeymod, sizeof(skeymod)); + ret = blob_decap(keymod, plain_data, bdata + ROUND(ENDATA_LEN, ARCH_DMA_MINALIGN), ENDATA_LEN); + if (ret != 0) { + printf("Error during blob decap operation: 0x%x\n",ret); + return FASTBOOT_LOCK_ERROR; + } +#ifdef FASTBOOT_LOCK_DEBUG + FB_DEBUG("Decrypt data block are:\n \t=======\t\n"); + for (p = 0; p < ENDATA_LEN; p++) { + FB_DEBUG("0x%2x ", *(bdata + p)); + if (p % 16 == 0) + FB_DEBUG("\n"); + } + FB_DEBUG("\n \t========\t\n"); + for (p = ENDATA_LEN; p < (ENDATA_LEN + ENDATA_LEN + 48 ); p++) { + FB_DEBUG("0x%2x ", *(bdata + p)); + if (p % 16 == 0) + FB_DEBUG("\n"); + } + + FB_DEBUG("\n plain text are:\n"); + for (p = 0; p < ENDATA_LEN; p++) { + FB_DEBUG("0x%2x ", plain_data[p]); + if (p % 16 == 0) + FB_DEBUG("\n"); + } + FB_DEBUG("\n"); +#endif + + for (p = 0; p < ENDATA_LEN-1; p++) { + if (*(bdata+p) != plain_data[p]) { + FB_DEBUG("Verify salt in decrypt error on pointer %d\n", p); + return FASTBOOT_LOCK_ERROR; + } + } + + if (plain_data[ENDATA_LEN - 1] >= FASTBOOT_LOCK_NUM) + return FASTBOOT_LOCK_ERROR; + else + return plain_data[ENDATA_LEN-1]; +} + +static __maybe_unused int encrypt_lock_store(FbLockState lock, unsigned char* bdata) { + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, keymod, 16); + unsigned int p = 0; + int ret; + int salt_len = generate_salt(bdata); + if (salt_len < 0) + return -1; + + //salt_len cannot be longer than endata block size. + if (salt_len >= ENDATA_LEN) + salt_len = ENDATA_LEN - 1; + + p = ENDATA_LEN - 1; + + //Set lock value + *(bdata + p) = lock; + + memcpy(keymod, skeymod, sizeof(skeymod)); + ret = blob_encap(keymod, bdata, bdata + ROUND(ENDATA_LEN, ARCH_DMA_MINALIGN), ENDATA_LEN); + if (ret != 0) { + printf("error in blob_encap:0x%x\n", ret); + return -1; + } + + +#ifdef FASTBOOT_LOCK_DEBUG + int i = 0; + FB_DEBUG("encrypt plain_text:\n"); + for (i = 0; i < ENDATA_LEN; i++) { + FB_DEBUG("0x%2x\t", *(bdata+i)); + if (i % 16 == 0) + printf("\n"); + } + printf("\nto:\n"); + for (i=0; i < ENDATA_LEN + 48; i++) { + FB_DEBUG("0x%2x\t", *(bdata + ENDATA_LEN + i)); + if (i % 16 == 0) + printf("\n"); + } + printf("\n"); + +#endif + //protect value + *(bdata + p) = 0xff; + return 0; +} + +#endif + +static char mmc_dev_part[16]; +static char* get_mmc_part(int part) { + u32 dev_no = mmc_get_env_dev(); + sprintf(mmc_dev_part,"%x:%x",dev_no, part); + return mmc_dev_part; +} + +static inline void set_lock_disable_data(unsigned char* bdata) { + *(bdata + SECTOR_SIZE -1) = 0; +} + +/* + * The enabling value is stored in the last byte of target partition. + */ +static inline unsigned char lock_enable_parse(unsigned char* bdata) { + FB_DEBUG("lock_enable_parse: 0x%x\n", *(bdata + SECTOR_SIZE -1)); + if (*(bdata + SECTOR_SIZE -1) >= FASTBOOT_UL_NUM) + return FASTBOOT_UL_ERROR; + else + return *(bdata + SECTOR_SIZE -1); +} + +static FbLockState g_lockstat = FASTBOOT_UNLOCK; + +#ifdef CONFIG_IMX_TRUSTY_OS +FbLockState fastboot_get_lock_stat(void) { + uint8_t l_status; + int ret; + /* + * If Trusty OS not flashed, then must return + * unlock status to make device been able + * to flash Trusty OS binary. + */ +#ifndef CONFIG_ARM64 + if (!tos_flashed) + return FASTBOOT_UNLOCK; +#endif + ret = trusty_read_lock_state(&l_status); + if (ret < 0) + return g_lockstat; + else + return l_status; + +} + +int fastboot_set_lock_stat(FbLockState lock) { + int ret; + /* + * If Trusty OS not flashed, we must prevent set lock + * status. Due the Trusty IPC won't work here. + */ +#ifndef CONFIG_ARM64 + if (!tos_flashed) + return 0; +#endif + ret = trusty_write_lock_state(lock); + if (ret < 0) { + printf("cannot set lock status due Trusty return %d\n", ret); + return ret; + } + return 0; +} +#else + +/* + * Set status of the lock&unlock to FSL_FASTBOOT_FB_PART + * Currently use the very first Byte of FSL_FASTBOOT_FB_PART + * to store the fastboot lock&unlock status + */ +int fastboot_set_lock_stat(FbLockState lock) { + struct blk_desc *fs_dev_desc; + struct disk_partition fs_partition; + unsigned char *bdata; + int mmc_id; + int status, ret; + + bdata = (unsigned char *)memalign(ARCH_DMA_MINALIGN, SECTOR_SIZE); + if (bdata == NULL) + goto fail2; + memset(bdata, 0, SECTOR_SIZE); + + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_FBMISC); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + ret = -1; + goto fail; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), + &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("%s:error in getdevice partition.\n", __FUNCTION__); + ret = -1; + goto fail; + } + + status = encrypt_lock_store(lock, bdata); + if (status < 0) { + ret = -1; + goto fail; + } + status = blk_dwrite(fs_dev_desc, fs_partition.start, 1, bdata); + if (!status) { + printf("%s:error in block write.\n", __FUNCTION__); + ret = -1; + goto fail; + } + ret = 0; +fail: + free(bdata); + return ret; +fail2: + g_lockstat = lock; + return 0; +} + +FbLockState fastboot_get_lock_stat(void) { + struct blk_desc *fs_dev_desc; + struct disk_partition fs_partition; + unsigned char *bdata; + int mmc_id; + FbLockState ret; + /* uboot used by uuu will boot from USB, always return UNLOCK state */ + if (is_boot_from_usb()) + return g_lockstat; + + bdata = (unsigned char *)memalign(ARCH_DMA_MINALIGN, SECTOR_SIZE); + if (bdata == NULL) + return g_lockstat; + + int status; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_FBMISC); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + ret = g_lockstat; + goto fail; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), + &fs_dev_desc, &fs_partition, 1); + + if (status < 0) { + printf("%s:error in getdevice partition.\n", __FUNCTION__); + ret = g_lockstat; + goto fail; + } + + status = blk_dread(fs_dev_desc, fs_partition.start, 1, bdata); + if (!status) { + printf("%s:error in block read.\n", __FUNCTION__); + ret = FASTBOOT_LOCK_ERROR; + goto fail; + } + + ret = decrypt_lock_store(bdata); +fail: + free(bdata); + return ret; +} +#endif + + +/* Return the last byte of of FSL_FASTBOOT_PR_DATA + * which is managed by PresistDataService + */ + +#ifdef CONFIG_ENABLE_LOCKSTATUS_SUPPORT +//Brillo has no presist data partition +FbLockEnableResult fastboot_lock_enable(void) { + return FASTBOOT_UL_ENABLE; +} +void set_fastboot_lock_disable(void) { +} +#else +void set_fastboot_lock_disable(void) { + struct blk_desc *fs_dev_desc; + struct disk_partition fs_partition; + unsigned char *bdata; + int mmc_id; + + bdata = (unsigned char *)memalign(ALIGN_BYTES, SECTOR_SIZE); + if (bdata == NULL) + return; + set_lock_disable_data(bdata); + int status; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_PRDATA); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + goto fail; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), + &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("%s:error in getdevice partition.\n", __FUNCTION__); + goto fail; + } + + lbaint_t target_block = fs_partition.start + fs_partition.size - 1; + status = blk_dwrite(fs_dev_desc, target_block, 1, bdata); + if (!status) { + printf("%s: error in block read\n", __FUNCTION__); + goto fail; + } + +fail: + free(bdata); + return; + +} +FbLockEnableResult fastboot_lock_enable() { +#ifdef CONFIG_DUAL_BOOTLOADER + /* Always allow unlock device in spl recovery mode. */ + if (is_spl_recovery()) + return FASTBOOT_UL_ENABLE; +#endif + +#if defined(CONFIG_IMX_TRUSTY_OS) || defined(CONFIG_TRUSTY_UNLOCK_PERMISSION) + int ret; + uint8_t oem_device_unlock; + + ret = trusty_read_oem_unlock_device_permission(&oem_device_unlock); + if (ret < 0) + return FASTBOOT_UL_ERROR; + else + return oem_device_unlock; +#else /* CONFIG_IMX_TRUSTY_OS */ + FbLockEnableResult ret; + struct blk_desc *fs_dev_desc; + struct disk_partition fs_partition; + unsigned char *bdata; + int mmc_id; + + bdata = (unsigned char *)memalign(ALIGN_BYTES, SECTOR_SIZE); + if (bdata == NULL) + return FASTBOOT_UL_ERROR; + int status; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_PRDATA); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + ret = FASTBOOT_UL_ERROR; + goto fail; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), + &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("%s:error in getdevice partition.\n", __FUNCTION__); + ret = FASTBOOT_UL_ERROR; + goto fail; + } + + //The data is stored in the last blcok of this partition. + lbaint_t target_block = fs_partition.start + fs_partition.size - 1; + status = blk_dread(fs_dev_desc, target_block, 1, bdata); + if (!status) { + printf("%s: error in block read\n", __FUNCTION__); + ret = FASTBOOT_UL_ERROR; + goto fail; + } + int i = 0; + FB_DEBUG("\n PRIST last sector is:\n"); + for (i = 0; i < SECTOR_SIZE; i++) { + FB_DEBUG("0x%x ", *(bdata + i)); + if (i % 32 == 0) + FB_DEBUG("\n"); + } + FB_DEBUG("\n"); + ret = lock_enable_parse(bdata); +fail: + free(bdata); + return ret; +#endif /* CONFIG_IMX_TRUSTY_OS */ + +} +#endif + +int display_lock(FbLockState lock, int verify) { + struct stdio_dev *disp; + disp = stdio_get_by_name("vga"); + if (disp != NULL) { + if (lock == FASTBOOT_UNLOCK) { + disp->puts(disp, "\n============= NOTICE ============\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "| Your device is NOT locked. |\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "=================================\n"); + } else { + if (verify == -1) { + disp->puts(disp, "\n============= NOTICE ============\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "| Your device is NOT protected. |\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "=================================\n"); + } else if (verify == 1) { + disp->puts(disp, "\n============= NOTICE ============\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "| Boot verify failed! |\n"); + disp->puts(disp, "| |\n"); + disp->puts(disp, "=================================\n"); + } + } + return 0; + } else + printf("not found VGA disp console.\n"); + + return -1; + +} + +#ifdef CONFIG_AVB_WARNING_LOGO +int display_unlock_warning(void) { + int ret; + struct udevice *dev; + + ret = uclass_first_device_err(UCLASS_VIDEO, &dev); + if (!ret) { + /* clear screen first */ + video_clear(dev); + /* Draw the orange warning bmp logo */ + ret = bmp_display((ulong)orange_warning_bmp_bitmap, + CONFIG_AVB_WARNING_LOGO_COLS, CONFIG_AVB_WARNING_LOGO_ROWS); + + /* Show warning text. */ + if (uclass_first_device_err(UCLASS_VIDEO_CONSOLE, &dev)) { + printf("no text console device found!\n"); + return -1; + } + /* Adjust the cursor postion, the (x, y) are hard-coded here. */ + vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH, + CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 6); + vidconsole_put_string(dev, "The bootloader is unlocked and software"); + vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH, + CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 7); + vidconsole_put_string(dev, "integrity cannot be guaranteed. Any data"); + vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH, + CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 8); + vidconsole_put_string(dev, "stored on the device may be available to"); + vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH, + CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 9); + vidconsole_put_string(dev, "attackers. Do not store any sensitive data"); + vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH, + CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 10); + vidconsole_put_string(dev, "on the device."); + /* Jump one line to show the link */ + vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH, + CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 13); + vidconsole_put_string(dev, "Visit this link on another device:"); + vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH, + CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 14); + vidconsole_put_string(dev, "g.co/ABH"); + + vidconsole_position_cursor(dev, CONFIG_AVB_WARNING_LOGO_COLS/VIDEO_FONT_WIDTH, + CONFIG_AVB_WARNING_LOGO_ROWS/VIDEO_FONT_HEIGHT + 20); + vidconsole_put_string(dev, "PRESS POWER BUTTON TO CONTINUE..."); + /* sync frame buffer */ + video_sync_all(); + + return 0; + } else { + printf("no video device found!\n"); + return -1; + } +} +#endif + +int fastboot_wipe_data_partition(void) +{ + struct blk_desc *fs_dev_desc; + struct disk_partition fs_partition; + int status; + int mmc_id; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_DATA); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + return -1; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("error in get device partition for wipe /data\n"); + return -1; + } + status = blk_derase(fs_dev_desc, fs_partition.start , fs_partition.size ); + if (status != fs_partition.size ) { + printf("erase not complete\n"); + return -1; + } + mdelay(2000); + + return 0; +} + +void fastboot_wipe_all(void) { + struct blk_desc *fs_dev_desc; + struct disk_partition fs_partition; + int status; + int mmc_id; + mmc_id = fastboot_flash_find_index(FASTBOOT_PARTITION_GPT); + if (mmc_id < 0) { + printf("%s: error in get mmc part\n", __FUNCTION__); + return; + } + status = blk_get_device_part_str(FSL_FASTBOOT_FB_DEV, + get_mmc_part(mmc_id), &fs_dev_desc, &fs_partition, 1); + if (status < 0) { + printf("error in get device partition for wipe user partition\n"); + return; + } + status = blk_derase(fs_dev_desc, fs_partition.start , fs_partition.size ); + if (status != fs_partition.size ) { + printf("erase not complete\n"); + return; + } + printf("fastboot wiped all.\n"); +} diff --git a/drivers/fastboot/fb_fsl/fastboot_lock_unlock.h b/drivers/fastboot/fb_fsl/fastboot_lock_unlock.h new file mode 100644 index 00000000000..890b0de00b5 --- /dev/null +++ b/drivers/fastboot/fb_fsl/fastboot_lock_unlock.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FASTBOOT_LOCK_UNLOCK_H +#define FASTBOOT_LOCK_UNLOCK_H + +#define ALIGN_BYTES 64 /*armv7 cache line need 64 bytes aligned */ + +//#define FASTBOOT_LOCK_DEBUG + +#ifdef FASTBOOT_LOCK_DEBUG +#define FB_DEBUG(format, ...) printf(format, ##__VA_ARGS__) +#else +#define FB_DEBUG(format, ...) +#endif + +typedef enum { + FASTBOOT_UNLOCK, + FASTBOOT_LOCK, + FASTBOOT_LOCK_ERROR, + FASTBOOT_LOCK_NUM +}FbLockState; + +typedef enum { + FASTBOOT_UL_DISABLE, + FASTBOOT_UL_ENABLE, + FASTBOOT_UL_ERROR, + FASTBOOT_UL_NUM +}FbLockEnableResult; + +FbLockState fastboot_get_lock_stat(void); + +int fastboot_set_lock_stat(FbLockState lock); + +int fastboot_wipe_data_partition(void); +void fastboot_wipe_all(void); + +FbLockEnableResult fastboot_lock_enable(void); +void set_fastboot_lock_disable(void); + +int display_lock(FbLockState lock, int verify); + +int display_unlock_warning(void); + +bool valid_tos(void); +#endif diff --git a/drivers/fastboot/fb_fsl/fb_fsl_boot.c b/drivers/fastboot/fb_fsl/fb_fsl_boot.c new file mode 100644 index 00000000000..b73a7aa8f68 --- /dev/null +++ b/drivers/fastboot/fb_fsl/fb_fsl_boot.c @@ -0,0 +1,1164 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../lib/avb/fsl/utils.h" + +#ifdef CONFIG_AVB_SUPPORT +#include +#include +#endif + +#ifdef CONFIG_ANDROID_THINGS_SUPPORT +#include +#include +#include "../lib/avb/fsl/fsl_avbkey.h" +#include "../arch/arm/include/asm/mach-imx/hab.h" +#endif + +#if defined(CONFIG_FASTBOOT_LOCK) +#include "fastboot_lock_unlock.h" +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#include "u-boot/sha256.h" +#include +#include + +#ifndef CONFIG_LOAD_KEY_FROM_RPMB +#include "../lib/avb/fsl/fsl_public_key.h" +#endif + +#endif + +#include "fb_fsl_common.h" + +/* max kernel image size, used for compressed kernel image */ +#define MAX_KERNEL_LEN (96 * 1024 * 1024) + +/* Offset (in u32's) of start and end fields in the zImage header. */ +#define ZIMAGE_START_ADDR 10 +#define ZIMAGE_END_ADDR 11 + +/* Boot metric variables */ +boot_metric metrics = { + .bll_1 = 0, + .ble_1 = 0, + .kl = 0, + .kd = 0, + .avb = 0, + .odt = 0, + .sw = 0 +}; + +int read_from_partition_multi(const char* partition, + int64_t offset, size_t num_bytes, void* buffer, size_t* out_num_read) +{ + struct fastboot_ptentry *pte; + unsigned char *bdata; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned char *dst, *dst64 = NULL; + unsigned long blksz; + unsigned long s, cnt; + size_t num_read = 0; + lbaint_t part_start, part_end, bs, be, bm, blk_num; + margin_pos_t margin; + struct blk_desc *fs_dev_desc = NULL; + int dev_no; + int ret; + + assert(buffer != NULL && out_num_read != NULL); + + dev_no = mmc_get_env_dev(); + if ((fs_dev_desc = blk_get_dev("mmc", dev_no)) == NULL) { + printf("mmc device not found\n"); + return -1; + } + + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + printf("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return -1; + } + + blksz = fs_dev_desc->blksz; + part_start = pte->start; + part_end = pte->start + pte->length - 1; + + if (get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, true)) + return -1; + + bs = (lbaint_t)margin.blk_start; + be = (lbaint_t)margin.blk_end; + s = margin.start; + bm = margin.multi; + + /* alloc a blksz mem */ + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) { + printf("Failed to allocate memory!\n"); + return -1; + } + + /* support multi blk read */ + while (bs <= be) { + if (!s && bm > 1) { + dst = out_buf; + dst64 = PTR_ALIGN(out_buf, 64); /* for mmc blk read alignment */ + if (dst64 != dst) { + dst = dst64; + bm--; + } + blk_num = bm; + cnt = bm * blksz; + bm = 0; /* no more multi blk */ + } else { + blk_num = 1; + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + dst = bdata; + } + if (blk_dread(fs_dev_desc, bs, blk_num, dst) != blk_num) { + ret = -1; + goto fail; + } + + if (dst == bdata) + memcpy(out_buf, bdata + s, cnt); + else if (dst == dst64) + memcpy(out_buf, dst, cnt); /* internal copy */ + + s = 0; + bs += blk_num; + num_read += cnt; + out_buf += cnt; + } + *out_num_read = num_read; + ret = 0; + +fail: + free(bdata); + return ret; +} + + +#if defined(CONFIG_FASTBOOT_LOCK) +int do_lock_status(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { + FbLockState status = fastboot_get_lock_stat(); + if (status != FASTBOOT_LOCK_ERROR) { + if (status == FASTBOOT_LOCK) + printf("fastboot lock status: locked.\n"); + else + printf("fastboot lock status: unlocked.\n"); + } else + printf("fastboot lock status error!\n"); + + display_lock(status, -1); + + return 0; + +} + +U_BOOT_CMD( + lock_status, 2, 1, do_lock_status, + "lock_status", + "lock_status"); +#endif + +#if defined(CONFIG_FLASH_MCUFIRMWARE_SUPPORT) && defined(CONFIG_ARCH_IMX8M) +static int do_bootmcu(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + int ret; + size_t out_num_read; + void *mcu_base_addr = (void *)MCU_BOOTROM_BASE_ADDR; + char command[32]; + + ret = read_from_partition_multi(FASTBOOT_MCU_FIRMWARE_PARTITION, + 0, ANDROID_MCU_FIRMWARE_SIZE, (void *)mcu_base_addr, &out_num_read); + if ((ret != 0) || (out_num_read != ANDROID_MCU_FIRMWARE_SIZE)) { + printf("Read MCU images failed!\n"); + return 1; + } else { + printf("run command: 'bootaux 0x%x'\n",(unsigned int)(ulong)mcu_base_addr); + + sprintf(command, "bootaux 0x%x", (unsigned int)(ulong)mcu_base_addr); + ret = run_command(command, 0); + if (ret) { + printf("run 'bootaux' command failed!\n"); + return 1; + } + } + return 0; +} + +U_BOOT_CMD( + bootmcu, 1, 0, do_bootmcu, + "boot mcu images\n", + "boot mcu images from 'mcu_os' partition, only support images run from TCM" +); +#endif + +#ifdef CONFIG_CMD_BOOTA + +/* Section for Android bootimage format support */ + +#if !defined(CONFIG_ANDROID_DYNAMIC_PARTITION) && defined(CONFIG_SYSTEM_RAMDISK_SUPPORT) +/* Setup booargs for taking the system parition as ramdisk */ +static void fastboot_setup_system_boot_args(const char *slot, bool append_root) +{ + const char *system_part_name = NULL; +#ifdef CONFIG_ANDROID_AB_SUPPORT + if(slot == NULL) + return; + if(!strncmp(slot, "_a", strlen("_a")) || !strncmp(slot, "boot_a", strlen("boot_a"))) { + system_part_name = FASTBOOT_PARTITION_SYSTEM_A; + } + else if(!strncmp(slot, "_b", strlen("_b")) || !strncmp(slot, "boot_b", strlen("boot_b"))) { + system_part_name = FASTBOOT_PARTITION_SYSTEM_B; + } else { + printf("slot invalid!\n"); + return; + } +#else + system_part_name = FASTBOOT_PARTITION_SYSTEM; +#endif + + struct fastboot_ptentry *ptentry = fastboot_flash_find_ptn(system_part_name); + if(ptentry != NULL) { + char bootargs_3rd[ANDR_BOOT_ARGS_SIZE] = {'\0'}; + if (append_root) { + u32 dev_no = mmc_map_to_kernel_blk(mmc_get_env_dev()); + sprintf(bootargs_3rd, "root=/dev/mmcblk%dp%d ", + dev_no, + ptentry->partition_index); + } + strcat(bootargs_3rd, "rootwait"); + + env_set("bootargs_3rd", bootargs_3rd); + } else { + printf("Can't find partition: %s\n", system_part_name); + fastboot_flash_dump_ptn(); + } +} +#endif + +void +bootimg_print_image_hdr(struct andr_img_hdr *hdr) +{ +#ifdef DEBUG + int i; + printf(" Image magic: %s\n", hdr->magic); + + printf(" kernel_size: 0x%x\n", hdr->kernel_size); + printf(" kernel_addr: 0x%x\n", hdr->kernel_addr); + + printf(" rdisk_size: 0x%x\n", hdr->ramdisk_size); + printf(" rdisk_addr: 0x%x\n", hdr->ramdisk_addr); + + printf(" second_size: 0x%x\n", hdr->second_size); + printf(" second_addr: 0x%x\n", hdr->second_addr); + + printf(" tags_addr: 0x%x\n", hdr->tags_addr); + printf(" page_size: 0x%x\n", hdr->page_size); + + printf(" name: %s\n", hdr->name); + printf(" cmdline: %s\n", hdr->cmdline); + + for (i = 0; i < 8; i++) + printf(" id[%d]: 0x%x\n", i, hdr->id[i]); +#endif +} + +#if !defined(CONFIG_AVB_SUPPORT) || !defined(CONFIG_MMC) +static struct andr_img_hdr boothdr __aligned(ARCH_DMA_MINALIGN); +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_AVB_ATX) +static int sha256_concatenation(uint8_t *hash_buf, uint8_t *vbh, uint8_t *image_hash) +{ + if ((hash_buf == NULL) || (vbh == NULL) || (image_hash == NULL)) { + printf("sha256_concatenation: null buffer found!\n"); + return -1; + } + + memcpy(hash_buf, vbh, AVB_SHA256_DIGEST_SIZE); + memcpy(hash_buf + AVB_SHA256_DIGEST_SIZE, + image_hash, AVB_SHA256_DIGEST_SIZE); + sha256_csum_wd((unsigned char *)hash_buf, 2 * AVB_SHA256_DIGEST_SIZE, + (unsigned char *)vbh, CHUNKSZ_SHA256); + + return 0; +} + +/* Since we use fit format to organize the atf, tee, u-boot and u-boot dtb, + * so calculate the hash of fit is enough. + */ +static int vbh_bootloader(uint8_t *image_hash) +{ + char* slot_suffixes[2] = {"_a", "_b"}; + char partition_name[20]; + AvbABData ab_data; + uint8_t *image_buf = NULL; + uint32_t image_size; + size_t image_num_read; + int target_slot; + int ret = 0; + + /* Load A/B metadata and decide which slot we are going to load */ + if (fsl_avb_ab_ops.read_ab_metadata(&fsl_avb_ab_ops, &ab_data) != + AVB_IO_RESULT_OK) { + ret = -1; + goto fail ; + } + target_slot = get_curr_slot(&ab_data); + sprintf(partition_name, "bootloader%s", slot_suffixes[target_slot]); + + /* Read image header to find the image size */ + image_buf = (uint8_t *)malloc(MMC_SATA_BLOCK_SIZE); + if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, partition_name, + 0, MMC_SATA_BLOCK_SIZE, + image_buf, &image_num_read)) { + printf("bootloader image load error!\n"); + ret = -1; + goto fail; + } + image_size = fdt_totalsize((struct image_header *)image_buf); + image_size = (image_size + 3) & ~3; + free(image_buf); + + /* Load full fit image */ + image_buf = (uint8_t *)malloc(image_size); + if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, partition_name, + 0, image_size, + image_buf, &image_num_read)) { + printf("bootloader image load error!\n"); + ret = -1; + goto fail; + } + /* Calculate hash */ + sha256_csum_wd((unsigned char *)image_buf, image_size, + (unsigned char *)image_hash, CHUNKSZ_SHA256); + +fail: + if (image_buf != NULL) + free(image_buf); + return ret; +} + +int vbh_calculate(uint8_t *vbh, AvbSlotVerifyData *avb_out_data) +{ + uint8_t image_hash[AVB_SHA256_DIGEST_SIZE]; + uint8_t hash_buf[2 * AVB_SHA256_DIGEST_SIZE]; + uint8_t* image_buf = NULL; + uint32_t image_size; + size_t image_num_read; + int ret = 0; + + if (vbh == NULL) + return -1; + + /* Initial VBH (VBH0) should be 32 bytes 0 */ + memset(vbh, 0, AVB_SHA256_DIGEST_SIZE); + /* Load and calculate the sha256 hash of spl.bin */ + image_size = (ANDROID_SPL_SIZE + MMC_SATA_BLOCK_SIZE -1) / + MMC_SATA_BLOCK_SIZE; + image_buf = (uint8_t *)malloc(image_size); + if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, + FASTBOOT_PARTITION_BOOTLOADER, + 0, image_size, + image_buf, &image_num_read)) { + printf("spl image load error!\n"); + ret = -1; + goto fail; + } + sha256_csum_wd((unsigned char *)image_buf, image_size, + (unsigned char *)image_hash, CHUNKSZ_SHA256); + /* Calculate VBH1 */ + if (sha256_concatenation(hash_buf, vbh, image_hash)) { + ret = -1; + goto fail; + } + free(image_buf); + + /* Load and calculate hash of bootloader.img */ + if (vbh_bootloader(image_hash)) { + ret = -1; + goto fail; + } + + /* Calculate VBH2 */ + if (sha256_concatenation(hash_buf, vbh, image_hash)) { + ret = -1; + goto fail; + } + + /* Calculate the hash of vbmeta.img */ + avb_slot_verify_data_calculate_vbmeta_digest(avb_out_data, + AVB_DIGEST_TYPE_SHA256, + image_hash); + /* Calculate VBH3 */ + if (sha256_concatenation(hash_buf, vbh, image_hash)) { + ret = -1; + goto fail; + } + +fail: + if (image_buf != NULL) + free(image_buf); + return ret; +} +#endif /* CONFIG_DUAL_BOOTLOADER && CONFIG_AVB_ATX */ + +int trusty_setbootparameter(uint32_t os_version, + AvbABFlowResult avb_result, AvbSlotVerifyData *avb_out_data) { + int ret = 0; + uint8_t vbh[AVB_SHA256_DIGEST_SIZE]; + u32 os_ver = os_version >> 11; + u32 os_ver_km = (((os_ver >> 14) & 0x7F) * 100 + ((os_ver >> 7) & 0x7F)) * 100 + + (os_ver & 0x7F); + u32 os_lvl = os_version & ((1U << 11) - 1); + u32 os_lvl_km = ((os_lvl >> 4) + 2000) * 100 + (os_lvl & 0x0F); + keymaster_verified_boot_t vbstatus; + FbLockState lock_status = fastboot_get_lock_stat(); + uint8_t boot_key_hash[AVB_SHA256_DIGEST_SIZE]; + + bool lock = (lock_status == FASTBOOT_LOCK)? true: false; + if ((avb_result == AVB_AB_FLOW_RESULT_OK) && lock) + vbstatus = KM_VERIFIED_BOOT_VERIFIED; + else + vbstatus = KM_VERIFIED_BOOT_UNVERIFIED; + +#ifdef CONFIG_AVB_ATX + if (fsl_read_permanent_attributes_hash(&fsl_avb_atx_ops, boot_key_hash)) { + printf("ERROR - failed to read permanent attributes hash for keymaster\n"); + memset(boot_key_hash, '\0', AVB_SHA256_DIGEST_SIZE); + } +#else + uint8_t public_key_buf[AVB_MAX_BUFFER_LENGTH]; +#ifdef CONFIG_LOAD_KEY_FROM_RPMB + if (trusty_read_vbmeta_public_key(public_key_buf, + AVB_MAX_BUFFER_LENGTH) != 0) { + printf("ERROR - failed to read public key for keymaster\n"); + memset(boot_key_hash, '\0', AVB_SHA256_DIGEST_SIZE); + } else +#else + memcpy(public_key_buf, fsl_public_key, AVB_SHA256_DIGEST_SIZE); +#endif + sha256_csum_wd((unsigned char *)public_key_buf, AVB_SHA256_DIGEST_SIZE, + (unsigned char *)boot_key_hash, CHUNKSZ_SHA256); +#endif + + /* All '\0' boot key should be passed if the device is unlocked. */ + if (!lock) + memset(boot_key_hash, '\0', AVB_SHA256_DIGEST_SIZE); + + /* Calculate VBH */ +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_AVB_ATX) + if (vbh_calculate(vbh, avb_out_data)) { + ret = -1; + goto fail; + } +#else + avb_slot_verify_data_calculate_vbmeta_digest(avb_out_data, + AVB_DIGEST_TYPE_SHA256, + vbh); +#endif + trusty_set_boot_params(os_ver_km, os_lvl_km, vbstatus, lock, + boot_key_hash, AVB_SHA256_DIGEST_SIZE, + vbh, AVB_SHA256_DIGEST_SIZE); + +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_AVB_ATX) +fail: +#endif + return ret; +} +#endif + +#if defined(CONFIG_AVB_SUPPORT) && defined(CONFIG_MMC) +/* we can use avb to verify Trusty if we want */ +const char *requested_partitions_boot[] = {"boot", "dtbo", "vendor_boot", NULL}; +const char *requested_partitions_recovery[] = {"recovery", NULL}; + +static bool gki_is_enabled(void) +{ + size_t size; + struct andr_img_hdr hdr; + char partition_name[20]; + +#ifdef CONFIG_ANDROID_AB_SUPPORT + int target_slot; + struct bootloader_control ab_data; + char* slot_suffixes[2] = {"_a", "_b"}; + + if (fsl_avb_ab_ops.read_ab_metadata(&fsl_avb_ab_ops, &ab_data) != + AVB_IO_RESULT_OK) { + printf("Read A/B metadata fail!\n"); + return false; + } + target_slot = get_curr_slot(&ab_data); + sprintf(partition_name, "boot%s", slot_suffixes[target_slot]); +#else + sprintf(partition_name, "boot"); +#endif + + /* Read boot header to find the version */ + if (fsl_avb_ops.read_from_partition(&fsl_avb_ops, partition_name, + 0, sizeof(struct andr_img_hdr), + (void *)&hdr, &size)) { + printf("%s load error!\n", partition_name); + return false; + } + + if (hdr.header_version >= 3) + return true; + else + return false; +} + +static int find_partition_data_by_name(char* part_name, + AvbSlotVerifyData* avb_out_data, AvbPartitionData** avb_loadpart) +{ + int num = 0; + AvbPartitionData* loadpart = NULL; + + for (num = 0; num < avb_out_data->num_loaded_partitions; num++) { + loadpart = &(avb_out_data->loaded_partitions[num]); + if (!(strncmp(loadpart->partition_name, + part_name, strlen(part_name)))) { + *avb_loadpart = loadpart; + break; + } + } + if (num == avb_out_data->num_loaded_partitions) { + printf("Error! Can't find %s partition from avb partition data!\n", + part_name); + return -1; + } + else + return 0; +} + +bool __weak is_power_key_pressed(void) { + return false; +} + +int do_boota(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { + + ulong addr = 0; + u32 avb_metric; + u32 kernel_image_size = 0; + bool check_image_arm64 = false; + bool is_recovery_mode = false; + bool gki_is_supported = false; + + /* 'hdr' should point to boot.img */ + struct andr_img_hdr *hdr = NULL; + struct boot_img_hdr_v3 *hdr_v3 = NULL; + struct vendor_boot_img_hdr_v3 *vendor_boot_hdr = NULL; + + AvbABFlowResult avb_result; + AvbSlotVerifyData *avb_out_data = NULL; + AvbPartitionData *avb_loadpart = NULL; + AvbPartitionData *avb_vendorboot = NULL; + + /* get bootmode, default to boot "boot" */ + if (argc > 1) { + is_recovery_mode = + (strncmp(argv[1], "recovery", sizeof("recovery")) != 0) ? false: true; + if (is_recovery_mode) + printf("Will boot from recovery!\n"); + } + + /* check lock state */ + FbLockState lock_status = fastboot_get_lock_stat(); + if (lock_status == FASTBOOT_LOCK_ERROR) { + printf("In boota get fastboot lock status error. Set lock status\n"); + fastboot_set_lock_stat(FASTBOOT_LOCK); + lock_status = FASTBOOT_LOCK; + } + + bool allow_fail = (lock_status == FASTBOOT_UNLOCK ? true : false); + avb_metric = get_timer(0); + + if (gki_is_enabled()) + /* set flag when GKI is enabled, vendor_boot partition will be supported. */ + gki_is_supported = true; + else { + requested_partitions_boot[2] = NULL; + } + + /* For imx6 on Android, we don't have a/b slot and we want to verify boot/recovery with AVB. + * For imx8 and Android Things we don't have recovery and support a/b slot for boot */ +#ifdef CONFIG_DUAL_BOOTLOADER + /* We will only verify single one slot which has been selected in SPL */ + avb_result = avb_flow_dual_uboot(&fsl_avb_ab_ops, requested_partitions_boot, allow_fail, + AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, &avb_out_data); + + /* Reboot if current slot is not bootable. */ + if (avb_result == AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS) { + printf("boota: slot verify fail!\n"); + do_reset(NULL, 0, 0, NULL); + } +#else /* CONFIG_DUAL_BOOTLOADER */ +#ifdef CONFIG_ANDROID_AB_SUPPORT + /* we can use avb to verify Trusty if we want */ + avb_result = avb_ab_flow_fast(&fsl_avb_ab_ops, requested_partitions_boot, allow_fail, + AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, &avb_out_data); +#else /* CONFIG_ANDROID_AB_SUPPORT */ + /* For imx6/7 devices. */ + if (is_recovery_mode) { + avb_result = avb_single_flow(&fsl_avb_ab_ops, requested_partitions_recovery, allow_fail, + AVB_HASHTREE_ERROR_MODE_RESTART, &avb_out_data); + } else { + avb_result = avb_single_flow(&fsl_avb_ab_ops, requested_partitions_boot, allow_fail, + AVB_HASHTREE_ERROR_MODE_RESTART, &avb_out_data); + } +#endif /* CONFIG_ANDROID_AB_SUPPORT */ +#endif /* CONFIG_DUAL_BOOTLOADER */ + + /* get the duration of avb */ + metrics.avb = get_timer(avb_metric); + + /* Parse the avb data */ + if ((avb_result == AVB_AB_FLOW_RESULT_OK) || + (avb_result == AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR)) { + if (avb_out_data == NULL) + goto fail; + /* We may have more than one partition loaded by AVB, find the boot partition first.*/ +#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT + if (find_partition_data_by_name("boot", avb_out_data, &avb_loadpart)) + goto fail; + if (gki_is_supported && find_partition_data_by_name("vendor_boot", avb_out_data, &avb_vendorboot)) + goto fail; +#else + if (is_recovery_mode) { + if (find_partition_data_by_name("recovery", avb_out_data, &avb_loadpart)) + goto fail; + } else { + if (find_partition_data_by_name("boot", avb_out_data, &avb_loadpart)) + goto fail; + } +#endif + + assert(avb_loadpart != NULL); + + /* boot image is already read by avb */ + if (gki_is_supported) { + assert(avb_vendorboot != NULL); + hdr_v3 = (struct boot_img_hdr_v3 *)avb_loadpart->data; + vendor_boot_hdr = (struct vendor_boot_img_hdr_v3 *)avb_vendorboot->data; + if (android_image_check_header_v3(hdr_v3, vendor_boot_hdr)) { + printf("boota: bad boot/vendor_boot image magic\n"); + goto fail; + } + } else { + hdr = (struct andr_img_hdr *)avb_loadpart->data; + if (android_image_check_header(hdr)) { + printf("boota: bad boot image magic\n"); + goto fail; + } + } + + if (avb_result == AVB_AB_FLOW_RESULT_OK) + printf(" verify OK, boot '%s%s'\n", + avb_loadpart->partition_name, avb_out_data->ab_suffix); + else { + printf(" verify FAIL, state: UNLOCK\n"); + printf(" boot '%s%s' still\n", + avb_loadpart->partition_name, avb_out_data->ab_suffix); + } + char bootargs_sec[ANDR_BOOT_EXTRA_ARGS_SIZE]; + if (lock_status == FASTBOOT_LOCK) { + snprintf(bootargs_sec, sizeof(bootargs_sec), + "androidboot.verifiedbootstate=green androidboot.flash.locked=1 androidboot.slot_suffix=%s ", + avb_out_data->ab_suffix); + } else { + snprintf(bootargs_sec, sizeof(bootargs_sec), + "androidboot.verifiedbootstate=orange androidboot.flash.locked=0 androidboot.slot_suffix=%s ", + avb_out_data->ab_suffix); + } + if (avb_out_data->cmdline != NULL) + strcat(bootargs_sec, avb_out_data->cmdline); +#if defined(CONFIG_ANDROID_DYNAMIC_PARTITION) && defined(CONFIG_SYSTEM_RAMDISK_SUPPORT) + /* for the condition dynamic partition is used , recovery ramdisk is used to boot + * up Android, in this condition, "androidboot.force_normal_boot=1" is needed */ + if(!is_recovery_mode) { + strcat(bootargs_sec, " androidboot.force_normal_boot=1"); + } +#endif + env_set("bootargs_sec", bootargs_sec); +#if !defined(CONFIG_ANDROID_DYNAMIC_PARTITION) && defined(CONFIG_SYSTEM_RAMDISK_SUPPORT) + if(!is_recovery_mode) { + if(avb_out_data->cmdline != NULL && strstr(avb_out_data->cmdline, "root=")) + fastboot_setup_system_boot_args(avb_out_data->ab_suffix, false); + else + fastboot_setup_system_boot_args(avb_out_data->ab_suffix, true); + } +#endif /* CONFIG_ANDROID_AUTO_SUPPORT */ + } else { + /* Fall into fastboot mode if get unacceptable error from avb + * or verify fail in lock state. + */ + if (lock_status == FASTBOOT_LOCK) + printf(" verify FAIL, state: LOCK\n"); + + goto fail; + } + + /* + * Start decompress & load kernel image. If we are using uncompressed kernel image, + * copy it directly to physical dram address. If we are using compressed lz4 kernel + * image, we need to decompress the kernel image first. + */ + if (gki_is_supported) { + if (image_arm64((void *)((ulong)hdr_v3 + 4096))) { + memcpy((void *)(long)vendor_boot_hdr->kernel_addr, + (void *)((ulong)hdr_v3 + 4096), hdr_v3->kernel_size); + } else if (IS_ENABLED(CONFIG_LZ4)) { + size_t lz4_len = MAX_KERNEL_LEN; + if (ulz4fn((void *)((ulong)hdr_v3 + 4096), + hdr_v3->kernel_size, (void *)(ulong)vendor_boot_hdr->kernel_addr, &lz4_len) != 0) { + printf("Decompress kernel fail!\n"); + goto fail; + } + } else { + printf("Wrong kernel image! Please check if you need to enable 'CONFIG_LZ4'\n"); + goto fail; + } + + kernel_image_size = kernel_size((void *)((ulong)hdr_v3 + 4096)); + } else { +#if defined (CONFIG_ARCH_IMX8) || defined (CONFIG_ARCH_IMX8M) + if (image_arm64((void *)((ulong)hdr + hdr->page_size))) { + memcpy((void *)(long)hdr->kernel_addr, + (void *)((ulong)hdr + hdr->page_size), hdr->kernel_size); + } else if (IS_ENABLED(CONFIG_LZ4)) { + size_t lz4_len = MAX_KERNEL_LEN; + if (ulz4fn((void *)((ulong)hdr + hdr->page_size), + hdr->kernel_size, (void *)(ulong)hdr->kernel_addr, &lz4_len) != 0) { + printf("Decompress kernel fail!\n"); + goto fail; + } + } else { + printf("Wrong kernel image! Please check if you need to enable 'CONFIG_LZ4'\n"); + goto fail; + } + + kernel_image_size = kernel_size((void *)(long)hdr->kernel_addr); +#else /* CONFIG_ARCH_IMX8 || CONFIG_ARCH_IMX8M */ + /* copy kernel image and boot header to hdr->kernel_addr - hdr->page_size */ + memcpy((void *)(ulong)(hdr->kernel_addr - hdr->page_size), (void *)hdr, + hdr->page_size + ALIGN(hdr->kernel_size, hdr->page_size)); +#endif /* CONFIG_ARCH_IMX8 || CONFIG_ARCH_IMX8M */ + } + + /* + * Start loading ramdisk. */ + /* Load ramdisk except for Android Auto which doesn't support dynamic partition, it will only + * load ramdisk in recovery mode. + */ + if (gki_is_supported) { + /* Need to concatenate vendor_boot ramdisk and boot ramdisk, check + * "include/android_image.h" for boot/vendor_boot image overlay. + */ + memcpy((void *)(ulong)vendor_boot_hdr->ramdisk_addr, + (void *)(ulong)vendor_boot_hdr + ALIGN(sizeof(struct vendor_boot_img_hdr_v3), vendor_boot_hdr->page_size), + vendor_boot_hdr->vendor_ramdisk_size); + memcpy((void *)(ulong)vendor_boot_hdr->ramdisk_addr + vendor_boot_hdr->vendor_ramdisk_size, + (void *)(ulong)hdr_v3 + 4096 + ALIGN(hdr_v3->kernel_size, 4096), hdr_v3->ramdisk_size); + } else { +#if !defined(CONFIG_SYSTEM_RAMDISK_SUPPORT) || defined(CONFIG_ANDROID_DYNAMIC_PARTITION) + memcpy((void *)(ulong)hdr->ramdisk_addr, (void *)(ulong)hdr + hdr->page_size + + ALIGN(hdr->kernel_size, hdr->page_size), hdr->ramdisk_size); +#else + if (is_recovery_mode) + memcpy((void *)(ulong)hdr->ramdisk_addr, (void *)(ulong)hdr + hdr->page_size + + ALIGN(hdr->kernel_size, hdr->page_size), hdr->ramdisk_size); +#endif + } + + /* Check arm64 image */ + if (gki_is_supported) + check_image_arm64 = image_arm64((void *)(ulong)vendor_boot_hdr->kernel_addr); + else + check_image_arm64 = image_arm64((void *)(ulong)hdr->kernel_addr); + + /* Start loading the dtb file */ + u32 fdt_addr = 0; + u32 fdt_size = 0; + struct dt_table_header *dt_img = NULL; + + /* Kernel addr may need relocatition, put the dtb right after the kernel image. */ + if (check_image_arm64) { + ulong relocated_addr; + + if (gki_is_supported) + relocated_addr = kernel_relocate_addr((ulong)(vendor_boot_hdr->kernel_addr)); + else + relocated_addr = kernel_relocate_addr((ulong)(hdr->kernel_addr)); + + fdt_addr = relocated_addr + kernel_image_size + 1024; /* 1K gap */ + } else { + /* Let's reserve 64 MB for arm32 case */ + fdt_addr = (ulong)((ulong)(hdr->kernel_addr) + 64 * 1024 * 1024); + } + +#ifdef CONFIG_SYSTEM_RAMDISK_SUPPORT + /* It means boot.img(recovery) do not include dtb, it need load dtb from partition */ + if (find_partition_data_by_name("dtbo", + avb_out_data, &avb_loadpart)) { + goto fail; + } else + dt_img = (struct dt_table_header *)avb_loadpart->data; +#else + /* recovery.img include dts while boot.img use dtbo */ + if (is_recovery_mode) { + if (hdr->header_version != 1) { + printf("boota: boot image header version error!\n"); + goto fail; + } + + dt_img = (struct dt_table_header *)((void *)(ulong)hdr + + hdr->page_size + + ALIGN(hdr->kernel_size, hdr->page_size) + + ALIGN(hdr->ramdisk_size, hdr->page_size) + + ALIGN(hdr->second_size, hdr->page_size)); + } else if (find_partition_data_by_name("dtbo", + avb_out_data, &avb_loadpart)) { + goto fail; + } else + dt_img = (struct dt_table_header *)avb_loadpart->data; +#endif + + if (be32_to_cpu(dt_img->magic) != DT_TABLE_MAGIC) { + printf("boota: bad dt table magic %08x\n", + be32_to_cpu(dt_img->magic)); + goto fail; + } else if (!be32_to_cpu(dt_img->dt_entry_count)) { + printf("boota: no dt entries\n"); + goto fail; + } + + struct dt_table_entry *dt_entry; + dt_entry = (struct dt_table_entry *)((ulong)dt_img + + be32_to_cpu(dt_img->dt_entries_offset)); + fdt_size = be32_to_cpu(dt_entry->dt_size); + memcpy((void *)(ulong)fdt_addr, (void *)((ulong)dt_img + + be32_to_cpu(dt_entry->dt_offset)), fdt_size); + + /* Combine cmdline and Print image info */ + if (gki_is_supported) { + android_image_get_kernel_v3(hdr_v3, vendor_boot_hdr); + addr = vendor_boot_hdr->kernel_addr; + printf("kernel @ %08x (%d)\n", vendor_boot_hdr->kernel_addr, kernel_image_size); + printf("ramdisk @ %08x (%d)\n", vendor_boot_hdr->ramdisk_addr, + vendor_boot_hdr->vendor_ramdisk_size + hdr_v3->ramdisk_size); + } else { + if (check_image_arm64) { + android_image_get_kernel(hdr, 0, NULL, NULL); + addr = hdr->kernel_addr; + } else { + addr = (ulong)(hdr->kernel_addr - hdr->page_size); + } + printf("kernel @ %08x (%d)\n", hdr->kernel_addr, kernel_image_size); + printf("ramdisk @ %08x (%d)\n", hdr->ramdisk_addr, hdr->ramdisk_size); + } + if (fdt_size) + printf("fdt @ %08x (%d)\n", fdt_addr, fdt_size); + + /* Set boot parameters */ + char boot_addr_start[12]; + char ramdisk_addr[25]; + char fdt_addr_start[12]; + + char *boot_args[] = { NULL, boot_addr_start, ramdisk_addr, fdt_addr_start}; + if (check_image_arm64) + boot_args[0] = "booti"; + else + boot_args[0] = "bootm"; + + sprintf(boot_addr_start, "0x%lx", addr); + if (gki_is_supported) { + sprintf(ramdisk_addr, "0x%x:0x%x", vendor_boot_hdr->ramdisk_addr, + vendor_boot_hdr->vendor_ramdisk_size + hdr_v3->ramdisk_size); + } else { + sprintf(ramdisk_addr, "0x%x:0x%x", hdr->ramdisk_addr, hdr->ramdisk_size); + } + sprintf(fdt_addr_start, "0x%x", fdt_addr); + + /* Don't pass ramdisk addr for Android Auto if we are not booting from recovery */ +#if !defined(CONFIG_ANDROID_DYNAMIC_PARTITION) && defined(CONFIG_SYSTEM_RAMDISK_SUPPORT) + if (!is_recovery_mode) + boot_args[2] = NULL; +#endif + + /* Show orange warning for unlocked device, press power button to skip. */ +#ifdef CONFIG_AVB_WARNING_LOGO + if (fastboot_get_lock_stat() == FASTBOOT_UNLOCK) { + int count = 0; + + printf("Device is unlocked, press power key to skip warning logo... \n"); + if (display_unlock_warning()) + printf("can't show unlock warning.\n"); + while ( (count < 10 * CONFIG_AVB_WARNING_TIME_LAST) && !is_power_key_pressed()) { + mdelay(100); + count++; + } + } +#endif + + /* Trusty related operations */ +#ifdef CONFIG_IMX_TRUSTY_OS + /* Trusty keymaster needs some parameters before it work */ + uint32_t os_version; + if (gki_is_supported) + os_version = hdr_v3->os_version; + else + os_version = hdr->os_version; + if (trusty_setbootparameter(os_version, avb_result, avb_out_data)) + goto fail; + + /* lock the boot status and rollback_idx preventing Linux modify it */ + trusty_lock_boot_state(); + /* lock the boot state so linux can't use some hwcrypto commands. */ + hwcrypto_lock_boot_state(); + /* put ql-tipc to release resource for Linux */ + trusty_ipc_shutdown(); +#endif + + /* Free AVB data */ + if (avb_out_data != NULL) + avb_slot_verify_data_free(avb_out_data); + + /* Images are loaded, start to boot. */ + if (check_image_arm64) { +#ifdef CONFIG_CMD_BOOTI + do_booti(NULL, 0, 4, boot_args); +#else + debug("please enable CONFIG_CMD_BOOTI when kernel are Image"); +#endif + } else { + do_bootm(NULL, 0, 4, boot_args); + } + + /* This only happens if image is somehow faulty so we start over */ + do_reset(NULL, 0, 0, NULL); + + return 1; + +fail: + /* avb has no recovery */ + if (avb_out_data != NULL) + avb_slot_verify_data_free(avb_out_data); + + return run_command("fastboot 0", 0); +} + +U_BOOT_CMD( + boota, 2, 1, do_boota, + "boota - boot android bootimg \n", + "boot from current mmc with avb verify\n" +); + +#else /* CONFIG_AVB_SUPPORT */ +/* boota [ mmc0 | mmc1 [ ] ] */ +int do_boota(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + ulong addr = 0; + char *ptn = "boot"; + int mmcc = -1; + struct andr_img_hdr *hdr = &boothdr; + ulong image_size; + bool check_image_arm64 = false; + int i = 0; + + for (i = 0; i < argc; i++) + printf("%s ", argv[i]); + printf("\n"); + + if (argc < 2) + return -1; + + mmcc = simple_strtoul(argv[1]+3, NULL, 10); + + if (argc > 2) + ptn = argv[2]; + + if (mmcc != -1) { +#ifdef CONFIG_MMC + struct fastboot_ptentry *pte; + struct mmc *mmc; + struct disk_partition info; + struct blk_desc *dev_desc = NULL; + unsigned bootimg_sectors; + + memset((void *)&info, 0 , sizeof(struct disk_partition)); + /* i.MX use MBR as partition table, so this will have + to find the start block and length for the + partition name and register the fastboot pte we + define the partition number of each partition in + config file + */ + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("boota: cannot find '%d' mmc device\n", mmcc); + goto fail; + } + dev_desc = blk_get_dev("mmc", mmcc); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + printf("** Block device MMC %d not supported\n", mmcc); + goto fail; + } + + /* below was i.MX mmc operation code */ + if (mmc_init(mmc)) { + printf("mmc%d init failed\n", mmcc); + goto fail; + } + + pte = fastboot_flash_find_ptn(ptn); + if (!pte) { + printf("boota: cannot find '%s' partition\n", ptn); + fastboot_flash_dump_ptn(); + goto fail; + } + + if (blk_dread(dev_desc, pte->start, + 1, (void *)hdr) < 0) { + printf("boota: mmc failed to read bootimg header\n"); + goto fail; + } + + if (android_image_check_header(hdr)) { + printf("boota: bad boot image magic\n"); + goto fail; + } + + image_size = android_image_get_end(hdr) - (ulong)hdr; + bootimg_sectors = image_size/512; + + if (blk_dread(dev_desc, pte->start, + bootimg_sectors, + (void *)(hdr->kernel_addr - hdr->page_size)) < 0) { + printf("boota: mmc failed to read bootimage\n"); + goto fail; + } + check_image_arm64 = image_arm64((void *)hdr->kernel_addr); +#if defined(CONFIG_FASTBOOT_LOCK) + int verifyresult = -1; +#endif + +#if defined(CONFIG_FASTBOOT_LOCK) + int lock_status = fastboot_get_lock_stat(); + if (lock_status == FASTBOOT_LOCK_ERROR) { + printf("In boota get fastboot lock status error. Set lock status\n"); + fastboot_set_lock_stat(FASTBOOT_LOCK); + } + display_lock(fastboot_get_lock_stat(), verifyresult); +#endif + /* load the ramdisk file */ + memcpy((void *)hdr->ramdisk_addr, (void *)hdr->kernel_addr + + ALIGN(hdr->kernel_size, hdr->page_size), hdr->ramdisk_size); + +#ifdef CONFIG_OF_LIBFDT + u32 fdt_size = 0; + /* load the dtb file */ + if (hdr->second_addr) { + u32 zimage_size = ((u32 *)hdrload->kernel_addr)[ZIMAGE_END_ADDR] + - ((u32 *)hdrload->kernel_addr)[ZIMAGE_START_ADDR]; + fdt_size = hdrload->kernel_size - zimage_size; + memcpy((void *)(ulong)hdrload->second_addr, + (void*)(ulong)hdrload->kernel_addr + zimage_size, fdt_size); + } +#endif /*CONFIG_OF_LIBFDT*/ + +#else /*! CONFIG_MMC*/ + return -1; +#endif /*! CONFIG_MMC*/ + } else { + printf("boota: parameters is invalid. only support mmcX device\n"); + return -1; + } + + printf("kernel @ %08x (%d)\n", hdr->kernel_addr, hdr->kernel_size); + printf("ramdisk @ %08x (%d)\n", hdr->ramdisk_addr, hdr->ramdisk_size); +#ifdef CONFIG_OF_LIBFDT + if (fdt_size) + printf("fdt @ %08x (%d)\n", hdr->second_addr, fdt_size); +#endif /*CONFIG_OF_LIBFDT*/ + + + char boot_addr_start[12]; + char ramdisk_addr[25]; + char fdt_addr[12]; + char *boot_args[] = { NULL, boot_addr_start, ramdisk_addr, fdt_addr}; + if (check_image_arm64 ) { + addr = hdr->kernel_addr; + boot_args[0] = "booti"; + } else { + addr = hdr->kernel_addr - hdr->page_size; + boot_args[0] = "bootm"; + } + + sprintf(boot_addr_start, "0x%lx", addr); + sprintf(ramdisk_addr, "0x%x:0x%x", hdr->ramdisk_addr, hdr->ramdisk_size); + sprintf(fdt_addr, "0x%x", hdr->second_addr); + if (check_image_arm64) { + android_image_get_kernel(hdr, 0, NULL, NULL); +#ifdef CONFIG_CMD_BOOTI + do_booti(NULL, 0, 4, boot_args); +#else + debug("please enable CONFIG_CMD_BOOTI when kernel are Image"); +#endif + } else { + do_bootm(NULL, 0, 4, boot_args); + } + /* This only happens if image is somehow faulty so we start over */ + do_reset(NULL, 0, 0, NULL); + + return 1; + +fail: +#if defined(CONFIG_FSL_FASTBOOT) + return run_command("fastboot 0", 0); +#else /*! CONFIG_FSL_FASTBOOT*/ + return -1; +#endif /*! CONFIG_FSL_FASTBOOT*/ +} + +U_BOOT_CMD( + boota, 3, 1, do_boota, + "boota - boot android bootimg from memory\n", + "[ | mmc0 | mmc1 | mmc2 | mmcX] []\n " + "- boot application image stored in memory or mmc\n" + "\t'addr' should be the address of boot image " + "which is zImage+ramdisk.img\n" + "\t'mmcX' is the mmc device you store your boot.img, " + "which will read the boot.img from 1M offset('/boot' partition)\n" + "\t 'partition' (optional) is the partition id of your device, " + "if no partition give, will going to 'boot' partition\n" +); +#endif /* CONFIG_AVB_SUPPORT */ +#endif /* CONFIG_CMD_BOOTA */ diff --git a/drivers/fastboot/fb_fsl/fb_fsl_command.c b/drivers/fastboot/fb_fsl/fb_fsl_command.c new file mode 100644 index 00000000000..104e86e496f --- /dev/null +++ b/drivers/fastboot/fb_fsl/fb_fsl_command.c @@ -0,0 +1,1178 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif + +#ifdef CONFIG_BCB_SUPPORT +#include "bcb.h" +#endif + +#ifdef CONFIG_AVB_SUPPORT +#include +#include +#endif + +#ifdef CONFIG_ANDROID_THINGS_SUPPORT +#include +#include +#include "../lib/avb/fsl/fsl_avbkey.h" +#include "../arch/arm/include/asm/mach-imx/hab.h" +#endif + +#if defined(CONFIG_FASTBOOT_LOCK) +#include "fastboot_lock_unlock.h" +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#include "u-boot/sha256.h" +#include "trusty/rpmb.h" +#include +#endif + +#include "fb_fsl_common.h" +#include "fb_fsl_virtual_ab.h" + +#define EP_BUFFER_SIZE 4096 + +/** + * fastboot_bytes_received - number of bytes received in the current download + */ +static u32 fastboot_bytes_received; + +/** + * fastboot_bytes_expected - number of bytes expected in the current download + */ +static u32 fastboot_bytes_expected; + +/* Write the bcb with fastboot bootloader commands */ +static void enable_fastboot_command(void) +{ +#ifdef CONFIG_BCB_SUPPORT + char fastboot_command[32] = {0}; + strncpy(fastboot_command, FASTBOOT_BCB_CMD, 31); + bcb_write_command(fastboot_command); +#endif +} + +#ifdef CONFIG_ANDROID_RECOVERY +/* Write the recovery options with fastboot bootloader commands */ +static void enable_recovery_fastboot(void) +{ +#ifdef CONFIG_BCB_SUPPORT + char msg[32] = {0}; + strncpy(msg, RECOVERY_BCB_CMD, 31); + bcb_write_command(msg); + strncpy(msg, RECOVERY_FASTBOOT_ARG, 31); + bcb_write_recovery_opt(msg); +#endif +} +#endif + +/* Get the Boot mode from BCB cmd or Key pressed */ +static FbBootMode fastboot_get_bootmode(void) +{ + int boot_mode = BOOTMODE_NORMAL; +#ifdef CONFIG_ANDROID_RECOVERY + if(is_recovery_key_pressing()) { + boot_mode = BOOTMODE_RECOVERY_KEY_PRESSED; + return boot_mode; + } +#endif +#ifdef CONFIG_BCB_SUPPORT + int ret = 0; + char command[32]; + ret = bcb_read_command(command); + if (ret < 0) { + printf("read command failed\n"); + return boot_mode; + } + if (!strcmp(command, FASTBOOT_BCB_CMD)) { + boot_mode = BOOTMODE_FASTBOOT_BCB_CMD; + } +#ifdef CONFIG_ANDROID_RECOVERY + else if (!strcmp(command, RECOVERY_BCB_CMD)) { + boot_mode = BOOTMODE_RECOVERY_BCB_CMD; + } +#endif + + /* Clean the mode once its read out, + no matter what in the mode string */ + memset(command, 0, 32); + bcb_write_command(command); +#endif + return boot_mode; +} + +/* export to lib_arm/board.c */ +void fastboot_run_bootmode(void) +{ + FbBootMode boot_mode = fastboot_get_bootmode(); + switch(boot_mode){ + case BOOTMODE_FASTBOOT_BCB_CMD: + /* Make the boot into fastboot mode*/ + puts("Fastboot: Got bootloader commands!\n"); + run_command("fastboot 0", 0); + break; +#ifdef CONFIG_ANDROID_RECOVERY + case BOOTMODE_RECOVERY_BCB_CMD: + case BOOTMODE_RECOVERY_KEY_PRESSED: + /* Make the boot into recovery mode */ + puts("Fastboot: Got Recovery key pressing or recovery commands!\n"); + board_recovery_setup(); + break; +#endif + default: + /* skip special mode boot*/ + puts("Fastboot: Normal\n"); + break; + } +} + + + +/** + * okay() - Send bare OKAY response + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + * + * Send a bare OKAY fastboot response. This is used where the command is + * valid, but all the work is done after the response has been sent (e.g. + * boot, reboot etc.) + */ +static void okay(char *cmd_parameter, char *response) +{ + fastboot_okay(NULL, response); +} + +/** + * getvar() - Read a config/version variable + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + */ +static void getvar(char *cmd_parameter, char *response) +{ + fastboot_getvar(cmd_parameter, response); +} + +/** + * reboot_bootloader() - Sets reboot bootloader flag. + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + */ +static void reboot_bootloader(char *cmd_parameter, char *response) +{ + enable_fastboot_command(); + + if (fastboot_set_reboot_flag(FASTBOOT_REBOOT_REASON_BOOTLOADER)) + fastboot_fail("Cannot set reboot flag", response); + else + fastboot_okay(NULL, response); +} + +#ifdef CONFIG_ANDROID_RECOVERY +/** + * reboot_fastboot() - Sets reboot fastboot flag. + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + */ +static void reboot_fastboot(char *cmd_parameter, char *response) +{ + enable_recovery_fastboot(); + + if (fastboot_set_reboot_flag(FASTBOOT_REBOOT_REASON_FASTBOOTD)) + fastboot_fail("Cannot set reboot flag", response); + else + fastboot_okay(NULL, response); +} +#endif + +static void upload(char *cmd_parameter, char *response) +{ + if (!fastboot_bytes_received || fastboot_bytes_received > (EP_BUFFER_SIZE * 32)) { + fastboot_fail("", response); + return; + } + + printf("Will upload %d bytes.\n", fastboot_bytes_received); + snprintf(response, FASTBOOT_RESPONSE_LEN, "DATA%08x", fastboot_bytes_received); + fastboot_tx_write_more(response); + + fastboot_tx_write((const char *)(fastboot_buf_addr), fastboot_bytes_received); + + snprintf(response,FASTBOOT_RESPONSE_LEN, "OKAY"); + fastboot_tx_write_more(response); + + fastboot_none_resp(response); +} + +/** + * fastboot_download() - Start a download transfer from the client + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + */ +static void download(char *cmd_parameter, char *response) +{ + char *tmp; + + if (!cmd_parameter) { + fastboot_fail("Expected command parameter", response); + return; + } + fastboot_bytes_received = 0; + fastboot_bytes_expected = simple_strtoul(cmd_parameter, &tmp, 16); + if (fastboot_bytes_expected == 0) { + fastboot_fail("Expected nonzero image size", response); + return; + } + /* + * Nothing to download yet. Response is of the form: + * [DATA|FAIL]$cmd_parameter + * + * where cmd_parameter is an 8 digit hexadecimal number + */ + if (fastboot_bytes_expected > fastboot_buf_size) { + fastboot_fail(cmd_parameter, response); + } else { + printf("Starting download of %d bytes\n", + fastboot_bytes_expected); + fastboot_response("DATA", response, "%s", cmd_parameter); + } +} + +/** + * fastboot_data_remaining() - return bytes remaining in current transfer + * + * Return: Number of bytes left in the current download + */ +u32 fastboot_data_remaining(void) +{ + if (fastboot_bytes_received >= fastboot_bytes_expected) + return 0; + + return fastboot_bytes_expected - fastboot_bytes_received; +} + +/** + * fastboot_data_download() - Copy image data to fastboot_buf_addr. + * + * @fastboot_data: Pointer to received fastboot data + * @fastboot_data_len: Length of received fastboot data + * @response: Pointer to fastboot response buffer + * + * Copies image data from fastboot_data to fastboot_buf_addr. Writes to + * response. fastboot_bytes_received is updated to indicate the number + * of bytes that have been transferred. + * + * On completion sets image_size and ${filesize} to the total size of the + * downloaded image. + */ +void fastboot_data_download(const void *fastboot_data, + unsigned int fastboot_data_len, + char *response) +{ +#define BYTES_PER_DOT 0x20000 + u32 pre_dot_num, now_dot_num; + + if (fastboot_data_len == 0 || + (fastboot_bytes_received + fastboot_data_len) > + fastboot_bytes_expected) { + fastboot_fail("Received invalid data length", + response); + return; + } + /* Download data to fastboot_buf_addr */ + memcpy(fastboot_buf_addr + fastboot_bytes_received, + fastboot_data, fastboot_data_len); + + pre_dot_num = fastboot_bytes_received / BYTES_PER_DOT; + fastboot_bytes_received += fastboot_data_len; + now_dot_num = fastboot_bytes_received / BYTES_PER_DOT; + + if (pre_dot_num != now_dot_num) { + putc('.'); + if (!(now_dot_num % 74)) + putc('\n'); + } + *response = '\0'; +} + +/** + * fastboot_data_complete() - Mark current transfer complete + * + * @response: Pointer to fastboot response buffer + * + * Set image_size and ${filesize} to the total size of the downloaded image. + */ +void fastboot_data_complete(char *response) +{ + /* Download complete. Respond with "OKAY" */ + fastboot_okay(NULL, response); + printf("\ndownloading of %d bytes finished\n", fastboot_bytes_received); + env_set_hex("filesize", fastboot_bytes_received); + env_set_hex("fastboot_bytes", fastboot_bytes_received); + fastboot_bytes_expected = 0; +} + +#if defined(CONFIG_FASTBOOT_LOCK) +static int partition_table_valid(void) +{ + int status, mmc_no; + struct blk_desc *dev_desc; +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_ARM64) + /* Prevent other partition accessing when no TOS flashed. */ + if (!tos_flashed) + return 0; +#endif + struct disk_partition info; + mmc_no = fastboot_devinfo.dev_id; + dev_desc = blk_get_dev("mmc", mmc_no); + if (dev_desc) + status = part_get_info(dev_desc, 1, &info); + else + status = -1; + return (status == 0); +} + +static void wipe_all_userdata(void) +{ + char response[FASTBOOT_RESPONSE_LEN]; + + /* Erase all user data */ + printf("Start userdata wipe process....\n"); + /* Erase /data partition */ + fastboot_wipe_data_partition(); + +#if defined (CONFIG_ANDROID_SUPPORT) || defined (CONFIG_ANDROID_AUTO_SUPPORT) + /* Erase the misc partition. */ + process_erase_mmc(FASTBOOT_PARTITION_MISC, response); +#endif + +#ifndef CONFIG_ANDROID_AB_SUPPORT + /* Erase the cache partition for legacy imx6/7 */ + process_erase_mmc(FASTBOOT_PARTITION_CACHE, response); +#endif + +#if defined(AVB_RPMB) && !defined(CONFIG_IMX_TRUSTY_OS) + printf("Start stored_rollback_index wipe process....\n"); + rbkidx_erase(); + printf("Wipe stored_rollback_index completed.\n"); +#endif + process_erase_mmc(FASTBOOT_PARTITION_METADATA, response); + printf("Wipe userdata completed.\n"); +} + +static FbLockState do_fastboot_unlock(bool force) +{ + int status; + + if (fastboot_get_lock_stat() == FASTBOOT_UNLOCK) { + printf("The device is already unlocked\n"); + return FASTBOOT_UNLOCK; + } + if ((fastboot_lock_enable() == FASTBOOT_UL_ENABLE) || force) { + printf("It is able to unlock device. %d\n",fastboot_lock_enable()); + +#if defined(CONFIG_SECURE_UNLOCK) && defined(CONFIG_IMX_TRUSTY_OS) + if ((fastboot_bytes_received == 0) || !hab_is_enabled()) { + printf("No unlock credential found or hab is not closed!\n"); + return FASTBOOT_LOCK_ERROR; + } else { + char *serial = get_serial(); + status = trusty_verify_secure_unlock(fastboot_buf_addr, + fastboot_bytes_received, + (uint8_t *)serial, 16); + if (status < 0) { + printf("verify secure unlock credential fail due Trusty return %d\n", status); + return FASTBOOT_LOCK_ERROR; + } + } +#endif + +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + if (virtual_ab_update_is_merging() || + (virtual_ab_update_is_snapshoted() && !virtual_ab_slot_match())) { + printf("Can not erase userdata while a snapshot update is in progress!\n"); + return FASTBOOT_LOCK_ERROR; + } +#endif + + wipe_all_userdata(); + status = fastboot_set_lock_stat(FASTBOOT_UNLOCK); + if (status < 0) + return FASTBOOT_LOCK_ERROR; + } else { + printf("It is not able to unlock device."); + return FASTBOOT_LOCK_ERROR; + } + + return FASTBOOT_UNLOCK; +} + +static FbLockState do_fastboot_lock(void) +{ + int status; + + if (fastboot_get_lock_stat() == FASTBOOT_LOCK) { + printf("The device is already locked\n"); + return FASTBOOT_LOCK; + } + +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + if (virtual_ab_update_is_merging() || + (virtual_ab_update_is_snapshoted() && !virtual_ab_slot_match())) { + printf("Can not erase userdata while a snapshot update is in progress!\n"); + return FASTBOOT_LOCK_ERROR; + } +#endif + + wipe_all_userdata(); + status = fastboot_set_lock_stat(FASTBOOT_LOCK); + if (status < 0) + return FASTBOOT_LOCK_ERROR; + + return FASTBOOT_LOCK; +} + +static bool endswith(char* s, char* subs) { + if (!s || !subs) + return false; + uint32_t len = strlen(s); + uint32_t sublen = strlen(subs); + if (len < sublen) { + return false; + } + if (strncmp(s + len - sublen, subs, sublen)) { + return false; + } + return true; +} + +static void flashing(char *cmd, char *response) +{ + FbLockState status; + FbLockEnableResult result; + if (endswith(cmd, "lock_critical")) { + strcpy(response, "OKAY"); + } +#ifdef CONFIG_AVB_ATX + else if (endswith(cmd, FASTBOOT_AVB_AT_PERM_ATTR)) { + if (avb_atx_fuse_perm_attr(fastboot_buf_addr, fastboot_bytes_received)) + strcpy(response, "FAILInternal error!"); + else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_AT_GET_UNLOCK_CHALLENGE)) { + if (avb_atx_get_unlock_challenge(fsl_avb_ops.atx_ops, + fastboot_buf_addr, &fastboot_bytes_received)) + strcpy(response, "FAILInternal error!"); + else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_AT_UNLOCK_VBOOT)) { + if (at_unlock_vboot_is_disabled()) { + printf("unlock vboot already disabled, can't unlock the device!\n"); + strcpy(response, "FAILunlock vboot already disabled!."); + } else { +#ifdef CONFIG_AT_AUTHENTICATE_UNLOCK + if (avb_atx_verify_unlock_credential(fsl_avb_ops.atx_ops, + fastboot_buf_addr)) + strcpy(response, "FAILIncorrect unlock credential!"); + else { +#endif + status = do_fastboot_unlock(true); + if (status != FASTBOOT_LOCK_ERROR) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILunlock device failed."); +#ifdef CONFIG_AT_AUTHENTICATE_UNLOCK + } +#endif + } + } else if (endswith(cmd, FASTBOOT_AT_LOCK_VBOOT)) { + if (perm_attr_are_fused()) { + status = do_fastboot_lock(); + if (status != FASTBOOT_LOCK_ERROR) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILlock device failed."); + } else + strcpy(response, "FAILpermanent attributes not fused!"); + } else if (endswith(cmd, FASTBOOT_AT_DISABLE_UNLOCK_VBOOT)) { + /* This command can only be called after 'oem at-lock-vboot' */ + status = fastboot_get_lock_stat(); + if (status == FASTBOOT_LOCK) { + if (at_unlock_vboot_is_disabled()) { + printf("unlock vboot already disabled!\n"); + strcpy(response, "OKAY"); + } + else { + if (!at_disable_vboot_unlock()) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILdisable unlock vboot fail!"); + } + } else + strcpy(response, "FAILplease lock the device first!"); + } +#endif /* CONFIG_AVB_ATX */ +#ifdef CONFIG_ANDROID_THINGS_SUPPORT + else if (endswith(cmd, FASTBOOT_BOOTLOADER_VBOOT_KEY)) { + strcpy(response, "OKAY"); + } +#endif /* CONFIG_ANDROID_THINGS_SUPPORT */ +#ifdef CONFIG_IMX_TRUSTY_OS + else if (endswith(cmd, FASTBOOT_GET_CA_REQ)) { + uint8_t *ca_output; + uint32_t ca_length, cp_length; + if (trusty_atap_get_ca_request(fastboot_buf_addr, fastboot_bytes_received, + &(ca_output), &ca_length)) { + printf("ERROR get_ca_request failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + cp_length = min((uint32_t)CONFIG_FASTBOOT_BUF_SIZE, ca_length); + memcpy(fastboot_buf_addr, ca_output, cp_length); + fastboot_bytes_received = ca_length; + strcpy(response, "OKAY"); + } + + } else if (endswith(cmd, FASTBOOT_SET_CA_RESP)) { + if (trusty_atap_set_ca_response(fastboot_buf_addr, fastboot_bytes_received)) { + printf("ERROR set_ca_response failed!\n"); + strcpy(response, "FAILInternal error!"); + } else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_SET_RSA_ATTESTATION_KEY_ENC)) { + if (trusty_set_attestation_key_enc(fastboot_buf_addr, + fastboot_bytes_received, + KM_ALGORITHM_RSA)) { + printf("ERROR set rsa attestation key failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Set rsa attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_SET_EC_ATTESTATION_KEY_ENC)) { + if (trusty_set_attestation_key_enc(fastboot_buf_addr, + fastboot_bytes_received, + KM_ALGORITHM_EC)) { + printf("ERROR set ec attestation key failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Set ec attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_APPEND_RSA_ATTESTATION_CERT_ENC)) { + if (trusty_append_attestation_cert_chain_enc(fastboot_buf_addr, + fastboot_bytes_received, + KM_ALGORITHM_RSA)) { + printf("ERROR append rsa attestation cert chain failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Append rsa attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_APPEND_EC_ATTESTATION_CERT_ENC)) { + if (trusty_append_attestation_cert_chain_enc(fastboot_buf_addr, + fastboot_bytes_received, + KM_ALGORITHM_EC)) { + printf("ERROR append ec attestation cert chain failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Append ec attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_SET_RSA_ATTESTATION_KEY)) { + if (trusty_set_attestation_key(fastboot_buf_addr, + fastboot_bytes_received, + KM_ALGORITHM_RSA)) { + printf("ERROR set rsa attestation key failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Set rsa attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_SET_EC_ATTESTATION_KEY)) { + if (trusty_set_attestation_key(fastboot_buf_addr, + fastboot_bytes_received, + KM_ALGORITHM_EC)) { + printf("ERROR set ec attestation key failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Set ec attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_APPEND_RSA_ATTESTATION_CERT)) { + if (trusty_append_attestation_cert_chain(fastboot_buf_addr, + fastboot_bytes_received, + KM_ALGORITHM_RSA)) { + printf("ERROR append rsa attestation cert chain failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Append rsa attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_APPEND_EC_ATTESTATION_CERT)) { + if (trusty_append_attestation_cert_chain(fastboot_buf_addr, + fastboot_bytes_received, + KM_ALGORITHM_EC)) { + printf("ERROR append ec attestation cert chain failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Append ec attestation key successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_GET_MPPUBK)) { + if (fastboot_get_mppubk(fastboot_buf_addr, &fastboot_bytes_received)) { + printf("ERROR Generate mppubk failed!\n"); + strcpy(response, "FAILGenerate mppubk failed!"); + } else { + printf("mppubk generated!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_GET_SERIAL_NUMBER)) { + char *serial = get_serial(); + + if (!serial) + strcpy(response, "FAILSerial number not support!"); + else { + /* Serial number will not exceed 16 bytes.*/ + strncpy(fastboot_buf_addr, serial, 16); + fastboot_bytes_received = 16; + printf("Serial number generated!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_WV_PROVISION)) { + if (hwcrypto_provision_wv_key(fastboot_buf_addr, fastboot_bytes_received)) { + printf("ERROR provision widevine keybox failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Provision widevine keybox successfully!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_WV_PROVISION_ENC)) { + if (hwcrypto_provision_wv_key_enc(fastboot_buf_addr, fastboot_bytes_received)) { + printf("ERROR provision widevine keybox failed!\n"); + strcpy(response, "FAILInternal error!"); + } else { + printf("Provision widevine keybox successfully!\n"); + strcpy(response, "OKAY"); + } + } +#ifdef CONFIG_ID_ATTESTATION + else if (endswith(cmd, FASTBOOT_APPEND_ATTESTATION_ID)) { + if (trusty_append_attestation_id(ATTESTATION_ID_BRAND, strlen(ATTESTATION_ID_BRAND))) { + printf("Error append ATTESTATION_ID_BRAND failed!\n"); + strcpy(response, "FAILAppend ATTESTATION_ID_BRAND failed!"); + } else if (trusty_append_attestation_id(ATTESTATION_ID_DEVICE, strlen(ATTESTATION_ID_DEVICE))) { + printf("Error append ATTESTATION_ID_DEVICE failed!\n"); + strcpy(response, "FAILAppend ATTESTATION_ID_DEVICE failed!"); + } else if (trusty_append_attestation_id(CONFIG_ATTESTATION_ID_PRODUCT, strlen(CONFIG_ATTESTATION_ID_PRODUCT))) { + printf("Error append ATTESTATION_ID_PRODUCT failed!\n"); + strcpy(response, "FAILAppend ATTESTATION_ID_PRODUCT failed!"); + } else if (trusty_append_attestation_id(ATTESTATION_ID_MANUFACTURER, strlen(ATTESTATION_ID_MANUFACTURER))) { + printf("Error append ATTESTATION_ID_MANUFACTURER failed!\n"); + strcpy(response, "FAILAppend ATTESTATION_ID_MANUFACTURER failed!"); + } else if (trusty_append_attestation_id(ATTESTATION_ID_MODEL, strlen(ATTESTATION_ID_MODEL))) { + printf("Error append ATTESTATION_ID_MODEL failed!\n"); + strcpy(response, "FAILAppend ATTESTATION_ID_MODEL failed!"); + } else { + char *serial = get_serial(); + + if (!serial) { + printf("Error Failed to append the serial number!\n"); + strcpy(response, "FAIL Failed to append the serial number!"); + } else if (trusty_append_attestation_id(serial, 16)) { + printf("Error Failed to append the serial number!\n"); + strcpy(response, "FAILFailed to append the serial number!"); + } else + strcpy(response, "OKAY"); + } + } +#endif +#ifndef CONFIG_AVB_ATX + else if (endswith(cmd, FASTBOOT_SET_RPMB_STAGED_KEY)) { + if (fastboot_set_rpmb_staged_key(fastboot_buf_addr, fastboot_bytes_received)) { + printf("ERROR set rpmb staged key failed!\n"); + strcpy(response, "FAILset rpmb staged key failed!"); + } else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_SET_RPMB_HARDWARE_KEY)) { + if (fastboot_set_rpmb_hardware_key()) { + printf("ERROR set rpmb hardware key failed!\n"); + strcpy(response, "FAILset rpmb hardware key failed!"); + } else + strcpy(response, "OKAY"); + } else if (endswith(cmd, FASTBOOT_ERASE_RPMB)) { + if (storage_erase_rpmb()) { + printf("ERROR erase rpmb storage failed!\n"); + strcpy(response, "FAILerase rpmb storage failed!"); + } else { + printf("erase rpmb storage succeed!\n"); + strcpy(response, "OKAY"); + } + } else if (endswith(cmd, FASTBOOT_SET_VBMETA_PUBLIC_KEY)) { + if (avb_set_public_key(fastboot_buf_addr, + fastboot_bytes_received)) + strcpy(response, "FAILcan't set public key!"); + else + strcpy(response, "OKAY"); + } +#endif /* !CONFIG_AVB_ATX */ +#endif /* CONFIG_IMX_TRUSTY_OS */ + else if (endswith(cmd, "unlock_critical")) { + strcpy(response, "OKAY"); + } else if (endswith(cmd, "unlock")) { + printf("flashing unlock.\n"); +#ifdef CONFIG_AVB_ATX + /* We should do nothing here For Android Things which + * enables the authenticated unlock feature. + */ + strcpy(response, "OKAY"); +#else + status = do_fastboot_unlock(false); + if (status != FASTBOOT_LOCK_ERROR) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILunlock device failed."); +#endif + } else if (endswith(cmd, "lock")) { +#ifdef CONFIG_AVB_ATX + /* We should do nothing here For Android Things which + * enables the at-lock-vboot feature. + */ + strcpy(response, "OKAY"); +#else + printf("flashing lock.\n"); + status = do_fastboot_lock(); + if (status != FASTBOOT_LOCK_ERROR) + strcpy(response, "OKAY"); + else + strcpy(response, "FAILlock device failed."); +#endif + } else if (endswith(cmd, "get_unlock_ability")) { + result = fastboot_lock_enable(); + if (result == FASTBOOT_UL_ENABLE) { + fastboot_tx_write_more("INFO1"); + strcpy(response, "OKAY"); + } else if (result == FASTBOOT_UL_DISABLE) { + fastboot_tx_write_more("INFO0"); + strcpy(response, "OKAY"); + } else { + printf("flashing get_unlock_ability fail!\n"); + strcpy(response, "FAILget unlock ability failed."); + } + } else { + printf("Unknown flashing command:%s\n", cmd); + strcpy(response, "FAILcommand not defined"); + } + fastboot_tx_write_more(response); + + /* Must call fastboot_none_resp before returning from the dispatch function + * which uses fastboot_tx_write_more + */ + fastboot_none_resp(response); +} +#endif /* CONFIG_FASTBOOT_LOCK */ + +#ifdef CONFIG_AVB_SUPPORT +static void set_active_avb(char *cmd, char *response) +{ + AvbIOResult ret; + int slot = 0; + + if (!cmd) { + pr_err("missing slot suffix\n"); + fastboot_fail("missing slot suffix", response); + return; + } + +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + if (virtual_ab_update_is_merging()) { + printf("Can not switch slot while snapshot merge is in progress!\n"); + fastboot_fail("Snapshot merge is in progress!", response); + return; + } + + /* Only output a warning when the image is snapshoted. */ + if (virtual_ab_update_is_snapshoted()) + printf("Warning: changing the active slot with a snapshot applied may cancel the update!\n"); + else + printf("Warning: Virtual A/B is enabled, switch slot may make the system fail to boot. \n"); +#endif + + slot = slotidx_from_suffix(cmd); + + if (slot < 0) { + fastboot_fail("err slot suffix", response); + return; + } + + ret = fsl_avb_ab_mark_slot_active(&fsl_avb_ab_ops, slot); + if (ret != AVB_IO_RESULT_OK) + fastboot_fail("avb IO error", response); + else + fastboot_okay(NULL, response); + + return; +} +#endif /*CONFIG_AVB_SUPPORT*/ + +#if CONFIG_IS_ENABLED(FASTBOOT_FLASH) +static void flash(char *cmd, char *response) +{ + if (!cmd) { + pr_err("missing partition name"); + fastboot_fail("missing partition name", response); + return; + } + + /* Always enable image flash for Android Things. */ +#if defined(CONFIG_FASTBOOT_LOCK) && !defined(CONFIG_AVB_ATX) + int status; + status = fastboot_get_lock_stat(); + + if (status == FASTBOOT_LOCK) { + pr_err("device is LOCKed!\n"); + fastboot_fail("device is locked.", response); + return; + + } else if (status == FASTBOOT_LOCK_ERROR) { + pr_err("write lock status into device!\n"); + fastboot_set_lock_stat(FASTBOOT_LOCK); + fastboot_fail("device is locked.", response); + return; + } +#endif + +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + if (partition_is_protected_during_merge(cmd)) { + printf("Can not flash partition %s while a snapshot update is in progress!\n", cmd); + fastboot_fail("Snapshot update is in progress", response); + return; + } +#endif + + fastboot_process_flash(cmd, fastboot_buf_addr, + fastboot_bytes_received, response); + +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + /* Cancel virtual AB update after image flash */ + if (virtual_ab_update_is_merging() || virtual_ab_update_is_snapshoted()) + virtual_ab_cancel_update(); +#endif + +#if defined(CONFIG_FASTBOOT_LOCK) + if (strncmp(cmd, "gpt", 3) == 0) { + int gpt_valid = 0; + int mmc_no; + struct blk_desc *dev_desc; + mmc_no = fastboot_devinfo.dev_id; + dev_desc = blk_get_dev("mmc", mmc_no); + if (dev_desc) { + if (dev_desc->part_type != PART_TYPE_EFI) + dev_desc->part_type = PART_TYPE_EFI; + } + else { + fastboot_fail("", response); + return; + } + gpt_valid = partition_table_valid(); + /* If gpt is valid, load partitons table into memory. + So if the next command is "fastboot reboot bootloader", + it can find the "misc" partition to r/w. */ + if(gpt_valid) { + fastboot_load_partitions(); + /* Unlock device if the gpt is valid */ + do_fastboot_unlock(true); + } + } + +#endif +} + +static void erase(char *cmd, char *response) +{ + if (!cmd) { + pr_err("missing partition name"); + fastboot_fail("missing partition name", response); + return; + } + +#if defined(CONFIG_FASTBOOT_LOCK) && !defined(CONFIG_AVB_ATX) + FbLockState status; + status = fastboot_get_lock_stat(); + if (status == FASTBOOT_LOCK) { + pr_err("device is LOCKed!\n"); + fastboot_fail("device is locked.", response); + return; + } else if (status == FASTBOOT_LOCK_ERROR) { + pr_err("write lock status into device!\n"); + fastboot_set_lock_stat(FASTBOOT_LOCK); + fastboot_fail("device is locked.", response); + return; + } +#endif + +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + if (partition_is_protected_during_merge(cmd)) { + printf("Can not erase partition %s while a snapshot update is in progress!", cmd); + fastboot_fail("Snapshot update is in progress", response); + return; + } +#endif + + fastboot_process_erase(cmd, response); +} +#endif + +/** + * fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader + * + * This is a redefinition, since BSP dose not need the function of + * "reboot into bootloader", and with BCB support, the flag can be + * set with another way. Redefine this function to override the weak + * definition to avoid error return value. + */ +int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) +{ + return 0; +} + +#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) +/** + * run_ucmd() - Execute the UCmd command + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + */ +static void run_ucmd(char *cmd_parameter, char *response) +{ + if (!cmd_parameter) { + pr_err("missing slot suffix\n"); + fastboot_fail("missing command", response); + return; + } + if(run_command(cmd_parameter, 0)) { + fastboot_fail("", response); + } else { + fastboot_okay(NULL, response); + /* cmd may impact fastboot related environment*/ + fastboot_setup(); + } +} + +static char g_a_cmd_buff[64]; + +void fastboot_acmd_complete(void) +{ + run_command(g_a_cmd_buff, 0); +} + +/** + * run_acmd() - Execute the ACmd command + * + * @cmd_parameter: Pointer to command parameter + * @response: Pointer to fastboot response buffer + */ +static void run_acmd(char *cmd_parameter, char *response) +{ + if (!cmd_parameter) { + pr_err("missing slot suffix\n"); + fastboot_fail("missing command", response); + return; + } + + if (strlen(cmd_parameter) >= sizeof(g_a_cmd_buff)) { + pr_err("input acmd is too long\n"); + fastboot_fail("too long command", response); + return; + } + + strcpy(g_a_cmd_buff, cmd_parameter); + fastboot_okay(NULL, response); +} +#endif + +#ifdef CONFIG_VIRTUAL_AB_SUPPORT +static void snapshot_update(char *cmd_parameter, char *response) +{ + if (endswith(cmd_parameter, "cancel")) { + FbLockState status; + status = fastboot_get_lock_stat(); + if ((status == FASTBOOT_LOCK) || (status == FASTBOOT_LOCK_ERROR)) { + printf("Can not cancel snapshot update when the device is locked!\n"); + fastboot_fail("device is locked!", response); + } else if (virtual_ab_update_is_merging() || virtual_ab_update_is_snapshoted()) { + if (virtual_ab_cancel_update() != -1) + fastboot_okay(NULL, response); + else + fastboot_fail("Can't cancel snapshot update!", response); + } else { + printf("Device is not in 'merging' or 'snapshotted' state, do nothing...\n"); + fastboot_okay(NULL, response); + } + + return; + } else { + printf("Error! Only 'cancel' is supported!"); + strcpy(response, "FAILInternal error!"); + } + + return; +} +#endif + +static const struct { + const char *command; + void (*dispatch)(char *cmd_parameter, char *response); +} commands[FASTBOOT_COMMAND_COUNT] = { + [FASTBOOT_COMMAND_REBOOT_BOOTLOADER] = { + .command = "reboot-bootloader", + .dispatch = reboot_bootloader, + }, + [FASTBOOT_COMMAND_UPLOAD] = { + .command = "upload", + .dispatch = upload, + }, + [FASTBOOT_COMMAND_GETSTAGED] = { + .command = "get_staged", + .dispatch = upload, + }, +#if defined(CONFIG_FASTBOOT_LOCK) + [FASTBOOT_COMMAND_FLASHING] = { + .command = "flashing", + .dispatch = flashing, + }, + [FASTBOOT_COMMAND_OEM] = { + .command = "oem", + .dispatch = flashing, + }, +#endif +#ifdef CONFIG_AVB_SUPPORT + [FASTBOOT_COMMAND_SETACTIVE] = { + .command = "set_active", + .dispatch = set_active_avb, + }, +#endif +#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) + [FASTBOOT_COMMAND_UCMD] = { + .command = "UCmd", + .dispatch = run_ucmd, + }, + [FASTBOOT_COMMAND_ACMD] = { + .command ="ACmd", + .dispatch = run_acmd, + }, +#endif + [FASTBOOT_COMMAND_REBOOT] = { + .command = "reboot", + .dispatch = okay, + }, + [FASTBOOT_COMMAND_GETVAR] = { + .command = "getvar", + .dispatch = getvar, + }, + [FASTBOOT_COMMAND_DOWNLOAD] = { + .command = "download", + .dispatch = download, + }, + [FASTBOOT_COMMAND_BOOT] = { + .command = "boot", + .dispatch = okay, + }, + [FASTBOOT_COMMAND_CONTINUE] = { + .command = "continue", + .dispatch = okay, + }, +#ifdef CONFIG_FASTBOOT_FLASH + [FASTBOOT_COMMAND_FLASH] = { + .command = "flash", + .dispatch = flash, + }, + [FASTBOOT_COMMAND_ERASE] = { + .command = "erase", + .dispatch = erase, + }, +#endif +#ifdef CONFIG_AVB_ATX + [FASTBOOT_COMMAND_STAGE] = { + .command = "stage", + .dispatch = download, + }, +#endif +#ifdef CONFIG_ANDROID_RECOVERY + [FASTBOOT_COMMAND_RECOVERY_FASTBOOT] = { + .command = "reboot-fastboot", + .dispatch = reboot_fastboot, + }, +#endif +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + [FASTBOOT_COMMAND_SNAPSHOT_UPDATE] = { + .command = "snapshot-update", + .dispatch = snapshot_update, + }, +#endif +}; + +/** + * fastboot_handle_command - Handle fastboot command + * + * @cmd_string: Pointer to command string + * @response: Pointer to fastboot response buffer + * + * Return: Executed command, or -1 if not recognized + */ +int fastboot_handle_command(char *cmd_string, char *response) +{ + int i; + char *cmd_parameter; + + cmd_parameter = cmd_string; + strsep(&cmd_parameter, ":"); + /* separate cmdstring for "fastboot oem/flashing" with a blank */ + if(cmd_parameter == NULL) + { + cmd_parameter = cmd_string; + strsep(&cmd_parameter, " "); + } + + for (i = 0; i < ARRAY_SIZE(commands); i++) { + if (commands[i].command != NULL && + !strcmp(commands[i].command, cmd_string)) { + if (commands[i].dispatch) { + commands[i].dispatch(cmd_parameter, + response); + return i; + } else { + break; + } + } + } + + pr_err("command %s not recognized.\n", cmd_string); + fastboot_fail("unrecognized command", response); + return -1; +} diff --git a/drivers/fastboot/fb_fsl/fb_fsl_common.c b/drivers/fastboot/fb_fsl/fb_fsl_common.c new file mode 100644 index 00000000000..bfeecd38b2e --- /dev/null +++ b/drivers/fastboot/fb_fsl/fb_fsl_common.c @@ -0,0 +1,425 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_ANDROID_RECOVERY +#include +#endif + +#ifdef CONFIG_BCB_SUPPORT +#include "bcb.h" +#endif + +#ifdef CONFIG_AVB_SUPPORT +#include +#include +#endif + +#ifdef CONFIG_ANDROID_THINGS_SUPPORT +#include +#include +#include "../lib/avb/fsl/fsl_avbkey.h" +#include "../arch/arm/include/asm/mach-imx/hab.h" +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#include "u-boot/sha256.h" +#include + +extern int armv7_init_nonsec(void); +extern void trusty_os_init(void); +#endif + +#include "fb_fsl_common.h" + +#include +#include + +#if defined(CONFIG_AVB_SUPPORT) && defined(CONFIG_MMC) +AvbABOps fsl_avb_ab_ops = { + .read_ab_metadata = fsl_avb_ab_data_read, + .write_ab_metadata = fsl_avb_ab_data_write, + .ops = NULL +}; +#ifdef CONFIG_AVB_ATX +AvbAtxOps fsl_avb_atx_ops = { + .ops = NULL, + .read_permanent_attributes = fsl_read_permanent_attributes, + .read_permanent_attributes_hash = fsl_read_permanent_attributes_hash, +#ifdef CONFIG_IMX_TRUSTY_OS + .set_key_version = fsl_write_rollback_index_rpmb, +#else + .set_key_version = fsl_set_key_version, +#endif + .get_random = fsl_get_random +}; +#endif +AvbOps fsl_avb_ops = { + .ab_ops = &fsl_avb_ab_ops, +#ifdef CONFIG_AVB_ATX + .atx_ops = &fsl_avb_atx_ops, +#endif + .read_from_partition = fsl_read_from_partition_multi, + .write_to_partition = fsl_write_to_partition, +#ifdef CONFIG_AVB_ATX + .validate_vbmeta_public_key = avb_atx_validate_vbmeta_public_key, +#else + .validate_vbmeta_public_key = fsl_validate_vbmeta_public_key_rpmb, +#endif + .read_rollback_index = fsl_read_rollback_index_rpmb, + .write_rollback_index = fsl_write_rollback_index_rpmb, + .read_is_device_unlocked = fsl_read_is_device_unlocked, + .get_unique_guid_for_partition = fsl_get_unique_guid_for_partition, + .get_size_of_partition = fsl_get_size_of_partition +}; +#endif + +int get_block_size(void) { + int dev_no = 0; + struct blk_desc *dev_desc; + + dev_no = fastboot_devinfo.dev_id; + dev_desc = blk_get_dev(fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc", dev_no); + if (NULL == dev_desc) { + printf("** Block device %s %d not supported\n", + fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc", + dev_no); + return 0; + } + return dev_desc->blksz; +} + +struct fastboot_device_info fastboot_devinfo = {0xff, 0xff}; + +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +struct fastboot_device_info fastboot_firmwareinfo; +#endif + +/** + * fastboot_none() - Skip the common write operation, nothing output. + * + * @response: Pointer to fastboot response buffer + */ +void fastboot_none_resp(char *response) +{ + *response = 0; +} + +void board_fastboot_setup(void) +{ + static char boot_dev_part[32]; + u32 dev_no; + + switch (get_boot_device()) { + case SD1_BOOT: + case SD2_BOOT: + case SD3_BOOT: + case SD4_BOOT: + case MMC1_BOOT: + case MMC2_BOOT: + case MMC3_BOOT: + case MMC4_BOOT: + dev_no = mmc_get_env_dev(); + sprintf(boot_dev_part,"mmc%d",dev_no); + if (!env_get("fastboot_dev")) + env_set("fastboot_dev", boot_dev_part); + sprintf(boot_dev_part, "boota mmc%d", dev_no); + if (!env_get("bootcmd")) + env_set("bootcmd", boot_dev_part); + break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + if (!env_get("bootcmd")) + env_set("bootcmd", "fastboot 0"); + break; + default: + if (!env_get("bootcmd")) + printf("unsupported boot devices\n"); + break; + } + + /* add soc type into bootargs */ + if (is_mx6dqp()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6qp"); + } else if (is_mx6dq()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6q"); + } else if (is_mx6sdl()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6dl"); + } else if (is_mx6sx()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6sx"); + } else if (is_mx6sl()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6sl"); + } else if (is_mx6ul()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx6ul"); + } else if (is_mx7()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx7d"); + } else if (is_mx7ulp()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx7ulp"); + } else if (is_imx8qm()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8qm"); + if (is_soc_rev(CHIP_REV_A)) + env_set("soc_rev", "reva"); + else if (is_soc_rev(CHIP_REV_B)) + env_set("soc_rev", "revb"); + } else if (is_imx8qxp()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8qxp"); + if (is_soc_rev(CHIP_REV_A)) + env_set("soc_rev", "reva"); + else if (is_soc_rev(CHIP_REV_B)) + env_set("soc_rev", "revb"); + else if (is_soc_rev(CHIP_REV_C)) + env_set("soc_rev", "revc"); + } else if (is_imx8mq()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8mq"); + } else if (is_imx8mm()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8mm"); + } else if (is_imx8mn()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8mn"); + } else if (is_imx8mp()) { + if (!env_get("soc_type")) + env_set("soc_type", "imx8mp"); + } +} + +#ifdef CONFIG_ANDROID_RECOVERY +void board_recovery_setup(void) +{ +/* boot from current mmc with avb verify */ +#ifdef CONFIG_AVB_SUPPORT + if (!env_get("bootcmd_android_recovery")) + env_set("bootcmd_android_recovery", "boota recovery"); +#else + static char boot_dev_part[32]; + u32 dev_no; + + int bootdev = get_boot_device(); + switch (bootdev) { + case SD1_BOOT: + case SD2_BOOT: + case SD3_BOOT: + case SD4_BOOT: + case MMC1_BOOT: + case MMC2_BOOT: + case MMC3_BOOT: + case MMC4_BOOT: + dev_no = mmc_get_env_dev(); + sprintf(boot_dev_part,"boota mmc%d recovery",dev_no); + if (!env_get("bootcmd_android_recovery")) + env_set("bootcmd_android_recovery", boot_dev_part); + break; + default: + printf("Unsupported bootup device for recovery: dev: %d\n", + bootdev); + return; + } +#endif /* CONFIG_AVB_SUPPORT */ + printf("setup env for recovery..\n"); + env_set("bootcmd", env_get("bootcmd_android_recovery")); +} +#endif /*CONFIG_ANDROID_RECOVERY*/ + +#ifdef CONFIG_IMX_TRUSTY_OS +#ifdef CONFIG_ARM64 +void tee_setup(void) +{ + trusty_ipc_init(); +} + +#else +extern bool tos_flashed; + +void tee_setup(void) +{ + /* load tee from boot1 of eMMC. */ + int mmcc = mmc_get_env_dev(); + struct blk_desc *dev_desc = NULL; + + struct mmc *mmc; + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("boota: cannot find '%d' mmc device\n", mmcc); + goto fail; + } + + dev_desc = blk_get_dev("mmc", mmcc); + if (NULL == dev_desc) { + printf("** Block device MMC %d not supported\n", mmcc); + goto fail; + } + + /* below was i.MX mmc operation code */ + if (mmc_init(mmc)) { + printf("mmc%d init failed\n", mmcc); + goto fail; + } + + struct fastboot_ptentry *tee_pte; + char *tee_ptn = FASTBOOT_PARTITION_TEE; + tee_pte = fastboot_flash_find_ptn(tee_ptn); + mmc_switch_part(mmc, TEE_HWPARTITION_ID); + if (!tee_pte) { + printf("boota: cannot find tee partition!\n"); + fastboot_flash_dump_ptn(); + } + + if (blk_dread(dev_desc, tee_pte->start, + tee_pte->length, (void *)TRUSTY_OS_ENTRY) < 0) { + printf("Failed to load tee."); + } + mmc_switch_part(mmc, FASTBOOT_MMC_USER_PARTITION_ID); + + tos_flashed = false; + if(!valid_tos()) { + printf("TOS not flashed! Will enter TOS recovery mode. Everything will be wiped!\n"); + fastboot_wipe_all(); + run_command("fastboot 0", 0); + goto fail; + } +#ifdef NON_SECURE_FASTBOOT + armv7_init_nonsec(); + trusty_os_init(); + trusty_ipc_init(); +#endif + +fail: + return; + +} +#endif /* CONFIG_ARM64 */ +#endif /* CONFIG_IMX_TRUSTY_OS */ + +static int _fastboot_setup_dev(int *switched) +{ + char *fastboot_env; + struct fastboot_device_info devinfo;; + fastboot_env = env_get("fastboot_dev"); + + if (fastboot_env) { + if (!strcmp(fastboot_env, "sata")) { + devinfo.type = DEV_SATA; + devinfo.dev_id = 0; + } else if (!strncmp(fastboot_env, "mmc", 3)) { + devinfo.type = DEV_MMC; + if(env_get("target_ubootdev")) + devinfo.dev_id = simple_strtoul(env_get("target_ubootdev"), NULL, 10); + else + devinfo.dev_id = mmc_get_env_dev(); + } else { + return 1; + } + } else { + return 1; + } +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + /* For imx7ulp, flash m4 images directly to spi nor-flash, M4 will + * run automatically after powered on. For imx8mq, flash m4 images to + * physical partition 'mcu_os', m4 will be kicked off by A core. */ + fastboot_firmwareinfo.type = ANDROID_MCU_FRIMWARE_DEV_TYPE; +#endif + + if (switched) { + if (devinfo.type != fastboot_devinfo.type || devinfo.dev_id != fastboot_devinfo.dev_id) + *switched = 1; + else + *switched = 0; + } + + fastboot_devinfo.type = devinfo.type; + fastboot_devinfo.dev_id = devinfo.dev_id; + + return 0; +} + +void fastboot_setup(void) +{ + int sw, ret; + struct tag_serialnr serialnr; + char serial[17]; + + if (!env_get("serial#")) { + get_board_serial(&serialnr); + sprintf(serial, "%08x%08x", serialnr.high, serialnr.low); + env_set("serial#", serial); + } + + /*execute board relevant initilizations for preparing fastboot */ + board_fastboot_setup(); + + /*get the fastboot dev*/ + ret = _fastboot_setup_dev(&sw); + + /*load partitions information for the fastboot dev*/ + if (!ret && sw) + fastboot_load_partitions(); + + fastboot_init(NULL, 0); +#ifdef CONFIG_AVB_SUPPORT + fsl_avb_ab_ops.ops = &fsl_avb_ops; +#ifdef CONFIG_AVB_ATX + fsl_avb_atx_ops.ops = &fsl_avb_ops; +#endif +#endif +} + +static void fastboot_putc(struct stdio_dev *dev, const char c) +{ + char buff[6] = "INFO"; + buff[4] = c; + buff[5] = 0; + fastboot_tx_write_more(buff); +} + +#define FASTBOOT_MAX_LEN 64 + +static void fastboot_puts(struct stdio_dev *dev, const char *s) +{ + char buff[FASTBOOT_MAX_LEN + 1] = "INFO"; + int len = strlen(s); + int i, left; + + for (i = 0; i < len; i += FASTBOOT_MAX_LEN - 4) { + left = len - i; + if (left > FASTBOOT_MAX_LEN - 4) + left = FASTBOOT_MAX_LEN - 4; + + memcpy(buff + 4, s + i, left); + buff[left + 4] = 0; + fastboot_tx_write_more(buff); + } +} + +struct stdio_dev g_fastboot_stdio = { + .name = "fastboot", + .flags = DEV_FLAGS_OUTPUT, + .putc = fastboot_putc, + .puts = fastboot_puts, +}; diff --git a/drivers/fastboot/fb_fsl/fb_fsl_common.h b/drivers/fastboot/fb_fsl/fb_fsl_common.h new file mode 100644 index 00000000000..6b957c43d5d --- /dev/null +++ b/drivers/fastboot/fb_fsl/fb_fsl_common.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef FB_FSL_COMMON_H +#define FB_FSL_COMMON_H + +#ifdef CONFIG_AVB_SUPPORT +#include +#include +#endif + +#if defined(CONFIG_AVB_SUPPORT) && defined(CONFIG_MMC) +extern AvbABOps fsl_avb_ab_ops; +#ifdef CONFIG_AVB_ATX +extern AvbAtxOps fsl_avb_atx_ops; +#endif +extern AvbOps fsl_avb_ops; +#endif + +#define IMX_SERIAL_LEN 32 + +int get_block_size(void); +void process_erase_mmc(const char *cmdbuf, char *response); +char *get_serial(void); + +#endif // FB_FSL_COMMON_H diff --git a/drivers/fastboot/fb_fsl/fb_fsl_dev.c b/drivers/fastboot/fb_fsl/fb_fsl_dev.c new file mode 100644 index 00000000000..0ac2de5d72a --- /dev/null +++ b/drivers/fastboot/fb_fsl/fb_fsl_dev.c @@ -0,0 +1,562 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "fb_fsl_common.h" + +static lbaint_t mmc_sparse_write(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt, const void *buffer) +{ +#define SPARSE_FILL_BUF_SIZE (2 * 1024 * 1024) + + + struct blk_desc *dev_desc = (struct blk_desc *)info->priv; + ulong ret = 0; + void *data; + int fill_buf_num_blks, cnt; + + if ((unsigned long)buffer & (CONFIG_SYS_CACHELINE_SIZE - 1)) { + + fill_buf_num_blks = SPARSE_FILL_BUF_SIZE / info->blksz; + + data = memalign(CONFIG_SYS_CACHELINE_SIZE, fill_buf_num_blks * info->blksz); + + while (blkcnt) { + + if (blkcnt > fill_buf_num_blks) + cnt = fill_buf_num_blks; + else + cnt = blkcnt; + + memcpy(data, buffer, cnt * info->blksz); + + ret += blk_dwrite(dev_desc, blk, cnt, data); + + blk += cnt; + blkcnt -= cnt; + buffer = (void *)((unsigned long)buffer + cnt * info->blksz); + + } + + free(data); + } else { + ret = blk_dwrite(dev_desc, blk, blkcnt, buffer); + } + + return ret; +} + +static lbaint_t mmc_sparse_reserve(struct sparse_storage *info, + lbaint_t blk, lbaint_t blkcnt) +{ + return blkcnt; +} + +int write_backup_gpt(void *download_buffer) +{ + int mmc_no = 0; + struct mmc *mmc; + struct blk_desc *dev_desc; + + mmc_no = fastboot_devinfo.dev_id; + mmc = find_mmc_device(mmc_no); + if (mmc == NULL) { + printf("invalid mmc device\n"); + return -1; + } + dev_desc = blk_get_dev("mmc", mmc_no); + if (dev_desc == NULL) { + printf("Can't get Block device MMC %d\n", + mmc_no); + return -ENODEV; + } + + /* write backup get partition */ + if (write_backup_gpt_partitions(dev_desc, download_buffer)) { + printf("writing GPT image fail\n"); + return -1; + } + + printf("flash backup gpt image successfully\n"); + return 0; +} + +static int get_fastboot_target_dev(char *mmc_dev, struct fastboot_ptentry *ptn) +{ + int dev = 0; + struct mmc *target_mmc; + + /* Support flash bootloader to mmc 'target_ubootdev' devices, if the + * 'target_ubootdev' env is not set just flash bootloader to current + * mmc device. + */ + if ((!strncmp(ptn->name, FASTBOOT_PARTITION_BOOTLOADER, + sizeof(FASTBOOT_PARTITION_BOOTLOADER))) && + (env_get("target_ubootdev"))) { + dev = simple_strtoul(env_get("target_ubootdev"), NULL, 10); + + /* if target_ubootdev is set, it must be that users want to change + * fastboot device, then fastboot environment need to be updated */ + fastboot_setup(); + + target_mmc = find_mmc_device(dev); + if ((target_mmc == NULL) || mmc_init(target_mmc)) { + printf("MMC card init failed!\n"); + return -1; + } else { + printf("Flash target is mmc%d\n", dev); + if (target_mmc->part_config != MMCPART_NOAVAILABLE) + sprintf(mmc_dev, "mmc dev %x %x", dev, /*slot no*/ + FASTBOOT_MMC_BOOT_PARTITION_ID/*part no*/); + else + sprintf(mmc_dev, "mmc dev %x", dev); + } + } else if (ptn->partition_id != FASTBOOT_MMC_NONE_PARTITION_ID) + sprintf(mmc_dev, "mmc dev %x %x", + fastboot_devinfo.dev_id, /*slot no*/ + ptn->partition_id /*part no*/); + else + sprintf(mmc_dev, "mmc dev %x", + fastboot_devinfo.dev_id /*slot no*/); + return 0; +} + +static void process_flash_blkdev(const char *cmdbuf, void *download_buffer, + u32 download_bytes, char *response) +{ + if (download_bytes) { + struct fastboot_ptentry *ptn; + + /* Next is the partition name */ + ptn = fastboot_flash_find_ptn(cmdbuf); + if (ptn == NULL) { + fastboot_fail("partition does not exist", response); + fastboot_flash_dump_ptn(); + } else if ((download_bytes > + ptn->length * MMC_SATA_BLOCK_SIZE) && + !(ptn->flags & FASTBOOT_PTENTRY_FLAGS_WRITE_ENV)) { + printf("Image too large for the partition\n"); + fastboot_fail("image too large for partition", response); + } else { + unsigned int temp; + + char blk_dev[128]; + char blk_write[128]; + int blkret; + + printf("writing to partition '%s'\n", ptn->name); + /* Get target flash device. */ + if (get_fastboot_target_dev(blk_dev, ptn) != 0) + return; + + if (!fastboot_parts_is_raw(ptn) && + is_sparse_image(download_buffer)) { + int dev_no = 0; + struct mmc *mmc; + struct blk_desc *dev_desc; + struct disk_partition info; + struct sparse_storage sparse; + int err; + + dev_no = fastboot_devinfo.dev_id; + + printf("sparse flash target is %s:%d\n", + fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc", + dev_no); + if (fastboot_devinfo.type == DEV_MMC) { + mmc = find_mmc_device(dev_no); + if (mmc && mmc_init(mmc)) + printf("MMC card init failed!\n"); + } + + dev_desc = blk_get_dev(fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc", dev_no); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + printf("** Block device %s %d not supported\n", + fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc", + dev_no); + return; + } + + if( strncmp(ptn->name, FASTBOOT_PARTITION_ALL, + strlen(FASTBOOT_PARTITION_ALL)) == 0) { + info.blksz = dev_desc->blksz; + info.size = dev_desc->lba; + info.start = 0; + } else { + + if (part_get_info(dev_desc, + ptn->partition_index, &info)) { + printf("Bad partition index:%d for partition:%s\n", + ptn->partition_index, ptn->name); + return; + } + } + printf("writing to partition '%s' for sparse, buffer size %d\n", + ptn->name, download_bytes); + + sparse.blksz = info.blksz; + sparse.start = info.start; + sparse.size = info.size; + sparse.write = mmc_sparse_write; + sparse.reserve = mmc_sparse_reserve; + sparse.mssg = fastboot_fail; + printf("Flashing sparse image at offset " LBAFU "\n", + sparse.start); + + sparse.priv = dev_desc; + err = write_sparse_image(&sparse, ptn->name, download_buffer, + response); + + if (!err) + fastboot_okay(NULL, response); + } else { + /* Will flash images in below case: + * 1. Is not gpt partition. + * 2. Is gpt partition but no overlay detected. + * */ + if (strncmp(ptn->name, "gpt", 3) || !bootloader_gpt_overlay()) { + /* block count */ + if (strncmp(ptn->name, "gpt", 3) == 0) { + temp = (ANDROID_GPT_END + + MMC_SATA_BLOCK_SIZE - 1) / + MMC_SATA_BLOCK_SIZE; + } else { + temp = (download_bytes + + MMC_SATA_BLOCK_SIZE - 1) / + MMC_SATA_BLOCK_SIZE; + } + + sprintf(blk_write, "%s write 0x%x 0x%x 0x%x", + fastboot_devinfo.type == DEV_SATA ? "scsi" : "mmc", + (unsigned int)(uintptr_t)download_buffer, /*source*/ + ptn->start, /*dest*/ + temp /*length*/); + + printf("Initializing '%s'\n", ptn->name); + + blkret = run_command(blk_dev, 0); + if (blkret) + fastboot_fail("Init of BLK device failed", response); + else + fastboot_okay(NULL, response); + + printf("Writing '%s'\n", ptn->name); + if (run_command(blk_write, 0)) { + printf("Writing '%s' FAILED!\n", ptn->name); + fastboot_fail("Write partition failed", response); + } else { + printf("Writing '%s' DONE!\n", ptn->name); + fastboot_okay(NULL, response); + } + } + /* Write backup gpt image */ + if (strncmp(ptn->name, "gpt", 3) == 0) { + if (write_backup_gpt(download_buffer)) + fastboot_fail("write backup GPT image fail", response); + else + fastboot_okay(NULL, response); + + /* will force scan the device, + * so dev_desc can be re-inited + * with the latest data */ + run_command(blk_dev, 0); + } + } + } + } else { + fastboot_fail("no image downloaded", response); + } +} + +static void process_erase_blkdev(const char *cmdbuf, char *response) +{ + int mmc_no = 0; + char blk_dev[128]; + lbaint_t blks, blks_start, blks_size, grp_size; + struct mmc *mmc; + struct blk_desc *dev_desc; + struct fastboot_ptentry *ptn; + struct disk_partition info; + + ptn = fastboot_flash_find_ptn(cmdbuf); + if ((ptn == NULL) || (ptn->flags & FASTBOOT_PTENTRY_FLAGS_UNERASEABLE)) { + fastboot_fail("partition does not exist or uneraseable", response); + fastboot_flash_dump_ptn(); + return; + } + + if (fastboot_devinfo.type == DEV_SATA) { + printf("Not support erase on SATA\n"); + return; + } + + mmc_no = fastboot_devinfo.dev_id; + printf("erase target is MMC:%d\n", mmc_no); + + mmc = find_mmc_device(mmc_no); + if ((mmc == NULL) || mmc_init(mmc)) { + printf("MMC card init failed!\n"); + return; + } + + dev_desc = blk_get_dev("mmc", mmc_no); + if (NULL == dev_desc) { + printf("Block device MMC %d not supported\n", + mmc_no); + fastboot_fail("not valid MMC card", response); + return; + } + + /* Get and switch target flash device. */ + if (get_fastboot_target_dev(blk_dev, ptn) != 0) { + printf("failed to get target dev!\n"); + return; + } else if (run_command(blk_dev, 0)) { + printf("Init of BLK device failed\n"); + return; + } + + if (part_get_info(dev_desc, + ptn->partition_index, &info)) { + printf("Bad partition index:%d for partition:%s\n", + ptn->partition_index, ptn->name); + fastboot_fail("erasing of MMC card", response); + return; + } + + /* Align blocks to erase group size to avoid erasing other partitions */ + grp_size = mmc->erase_grp_size; + blks_start = (info.start + grp_size - 1) & ~(grp_size - 1); + if (info.size >= grp_size) + blks_size = (info.size - (blks_start - info.start)) & + (~(grp_size - 1)); + else + blks_size = 0; + + printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n", + blks_start, blks_start + blks_size); + + blks = blk_derase(dev_desc, blks_start, blks_size); + if (blks != blks_size) { + printf("failed erasing from device %d", dev_desc->devnum); + fastboot_fail("erasing of MMC card", response); + return; + } + + printf("........ erased " LBAFU " bytes from '%s'\n", + blks_size * info.blksz, cmdbuf); + fastboot_okay(NULL, response); + + return; +} + +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +static void process_flash_sf(const char *cmdbuf, void *download_buffer, + u32 download_bytes, char *response) +{ + int blksz = 0; + blksz = get_block_size(); + + if (download_bytes) { + struct fastboot_ptentry *ptn; + ptn = fastboot_flash_find_ptn(cmdbuf); + if (ptn == 0) { + fastboot_fail("partition does not exist", response); + fastboot_flash_dump_ptn(); + } else if ((download_bytes > ptn->length * blksz)) { + fastboot_fail("image too large for partition", response); + /* TODO : Improve check for yaffs write */ + } else { + int ret; + char sf_command[128]; + /* Normal case */ + /* Probe device */ + sprintf(sf_command, "sf probe"); + ret = run_command(sf_command, 0); + if (ret){ + fastboot_fail("Probe sf failed", response); + return; + } + /* Erase */ + sprintf(sf_command, "sf erase 0x%x 0x%lx", ptn->start * blksz, /*start*/ + ptn->length * blksz /*size*/); + ret = run_command(sf_command, 0); + if (ret) { + fastboot_fail("Erasing sf failed", response); + return; + } + /* Write image */ + sprintf(sf_command, "sf write 0x%x 0x%x 0x%x", + (unsigned int)(ulong)download_buffer, /* source */ + ptn->start * blksz, /* start */ + download_bytes /*size*/); + printf("sf write '%s'\n", ptn->name); + ret = run_command(sf_command, 0); + if (ret){ + fastboot_fail("Writing sf failed", response); + return; + } + printf("sf write finished '%s'\n", ptn->name); + fastboot_okay(NULL, response); + } + } else { + fastboot_fail("no image downloaded", response); + } +} + +#ifdef CONFIG_ARCH_IMX8M +/* Check if the mcu image is built for running from TCM */ +static bool is_tcm_image(unsigned char *image_addr) +{ + u32 stack; + + stack = *(u32 *)image_addr; + + if ((stack != (u32)ANDROID_MCU_FIRMWARE_HEADER_STACK)) { + printf("Please flash mcu firmware images for running from TCM\n"); + return false; + } else + return true; +} +#endif +#endif + +void fastboot_process_erase(const char *cmdbuf, char *response) +{ + switch (fastboot_devinfo.type) { + case DEV_SATA: + case DEV_MMC: + process_erase_blkdev(cmdbuf, response); + break; + default: + printf("Not support flash command for current device %d\n", + fastboot_devinfo.type); + fastboot_fail("failed to flash device", response); + break; + } +} + +void fastboot_process_flash(const char *cmdbuf, void *download_buffer, + u32 download_bytes, char *response) +{ +/* Check if we need to flash mcu firmware */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + if (!strncmp(cmdbuf, FASTBOOT_MCU_FIRMWARE_PARTITION, + sizeof(FASTBOOT_MCU_FIRMWARE_PARTITION))) { + switch (fastboot_firmwareinfo.type) { + case DEV_SF: + process_flash_sf(cmdbuf, download_buffer, + download_bytes, response); + break; +#ifdef CONFIG_ARCH_IMX8M + case DEV_MMC: + if (is_tcm_image(download_buffer)) + process_flash_blkdev(cmdbuf, download_buffer, + download_bytes, response); + break; +#endif + default: + printf("Don't support flash firmware\n"); + } + return; + } +#endif + /* Normal case */ + switch (fastboot_devinfo.type) { + case DEV_SATA: + case DEV_MMC: + process_flash_blkdev(cmdbuf, download_buffer, + download_bytes, response); + break; + default: + printf("Not support flash command for current device %d\n", + fastboot_devinfo.type); + fastboot_fail("failed to flash device", response); + break; + } +} + +/* erase a partition on mmc */ +void process_erase_mmc(const char *cmdbuf, char *response) +{ + int mmc_no = 0; + lbaint_t blks, blks_start, blks_size, grp_size; + struct mmc *mmc; + struct blk_desc *dev_desc; + struct fastboot_ptentry *ptn; + struct disk_partition info; + + ptn = fastboot_flash_find_ptn(cmdbuf); + if ((ptn == NULL) || (ptn->flags & FASTBOOT_PTENTRY_FLAGS_UNERASEABLE)) { + sprintf(response, "FAILpartition does not exist or uneraseable"); + fastboot_flash_dump_ptn(); + return; + } + + mmc_no = fastboot_devinfo.dev_id; + printf("erase target is MMC:%d\n", mmc_no); + + mmc = find_mmc_device(mmc_no); + if ((mmc == NULL) || mmc_init(mmc)) { + printf("MMC card init failed!\n"); + return; + } + + dev_desc = blk_get_dev("mmc", mmc_no); + if (NULL == dev_desc) { + printf("Block device MMC %d not supported\n", + mmc_no); + sprintf(response, "FAILnot valid MMC card"); + return; + } + + if (part_get_info(dev_desc, + ptn->partition_index, &info)) { + printf("Bad partition index:%d for partition:%s\n", + ptn->partition_index, ptn->name); + sprintf(response, "FAILerasing of MMC card"); + return; + } + + /* Align blocks to erase group size to avoid erasing other partitions */ + grp_size = mmc->erase_grp_size; + blks_start = (info.start + grp_size - 1) & ~(grp_size - 1); + if (info.size >= grp_size) + blks_size = (info.size - (blks_start - info.start)) & + (~(grp_size - 1)); + else + blks_size = 0; + + printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n", + blks_start, blks_start + blks_size); + + blks = blk_derase(dev_desc, blks_start, blks_size); + if (blks != blks_size) { + printf("failed erasing from device %d", dev_desc->devnum); + sprintf(response, "FAILerasing of MMC card"); + return; + } + + printf("........ erased " LBAFU " bytes from '%s'\n", + blks_size * info.blksz, cmdbuf); + sprintf(response, "OKAY"); + + return; +} diff --git a/drivers/fastboot/fb_fsl/fb_fsl_getvar.c b/drivers/fastboot/fb_fsl/fb_fsl_getvar.c new file mode 100644 index 00000000000..457b5ae1238 --- /dev/null +++ b/drivers/fastboot/fb_fsl/fb_fsl_getvar.c @@ -0,0 +1,607 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_AVB_SUPPORT +#include +#include +#endif + +#ifdef CONFIG_ANDROID_THINGS_SUPPORT +#include +#include +#include "../lib/avb/fsl/fsl_avbkey.h" +#include "../arch/arm/include/asm/mach-imx/hab.h" +#endif + +#if defined(CONFIG_FASTBOOT_LOCK) +#include "fastboot_lock_unlock.h" +#endif + +#include "fb_fsl_common.h" + +#ifdef CONFIG_IMX_TRUSTY_OS +#include "u-boot/sha256.h" +#include + +#define ATAP_UUID_SIZE 32 +#define ATAP_UUID_STR_SIZE ((ATAP_UUID_SIZE*2) + 1) +#endif + +#ifdef CONFIG_VIRTUAL_AB_SUPPORT +#include "fb_fsl_virtual_ab.h" +#endif + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) +#define FASTBOOT_COMMON_VAR_NUM 15 +#else +#define FASTBOOT_COMMON_VAR_NUM 14 +#endif + +#define FASTBOOT_VAR_YES "yes" +#define FASTBOOT_VAR_NO "no" + +/* common variables of fastboot getvar command */ +char *fastboot_common_var[FASTBOOT_COMMON_VAR_NUM] = { + "version", + "version-bootloader", + "version-baseband", + "product", + "secure", + "max-download-size", + "erase-block-size", + "logical-block-size", + "unlocked", + "off-mode-charge", + "battery-voltage", + "variant", + "battery-soc-ok", + "is-userspace", +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) + "baseboard_id" +#endif +}; + +/* at-vboot-state variable list */ +#ifdef CONFIG_AVB_ATX +#define AT_VBOOT_STATE_VAR_NUM 6 +extern struct imx_sec_config_fuse_t const imx_sec_config_fuse; +extern int fuse_read(u32 bank, u32 word, u32 *val); + +char *fastboot_at_vboot_state_var[AT_VBOOT_STATE_VAR_NUM] = { + "bootloader-locked", + "bootloader-min-versions", + "avb-perm-attr-set", + "avb-locked", + "avb-unlock-disabled", + "avb-min-versions" +}; +#endif + +static int strcmp_l1(const char *s1, const char *s2) +{ + if (!s1 || !s2) + return -1; + return strncmp(s1, s2, strlen(s1)); +} + +static bool is_slotvar(char *cmd) +{ + assert(cmd != NULL); + if (!strcmp_l1("has-slot:", cmd) || + !strcmp_l1("slot-successful:", cmd) || + !strcmp_l1("slot-count", cmd) || + !strcmp_l1("slot-suffixes", cmd) || + !strcmp_l1("current-slot", cmd) || + !strcmp_l1("slot-unbootable:", cmd) || + !strcmp_l1("slot-retry-count:", cmd)) + return true; + return false; +} + +static char serial[IMX_SERIAL_LEN]; + +char *get_serial(void) +{ +#ifdef CONFIG_SERIAL_TAG + struct tag_serialnr serialnr; + memset(serial, 0, IMX_SERIAL_LEN); + + get_board_serial(&serialnr); + sprintf(serial, "%08x%08x", serialnr.high, serialnr.low); + return serial; +#else + return NULL; +#endif +} + +#if !defined(PRODUCT_NAME) +#define PRODUCT_NAME "NXP i.MX" +#endif + +#if !defined(VARIANT_NAME) +#define VARIANT_NAME "NXP i.MX" +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +static void uuid_hex2string(uint8_t *uuid, char* buf, uint32_t uuid_len, uint32_t uuid_strlen) { + uint32_t i; + if (!uuid || !buf) + return; + char *cp = buf; + char *buf_end = buf + uuid_strlen; + for (i = 0; i < uuid_len; i++) { + cp += snprintf(cp, buf_end - cp, "%02x", uuid[i]); + } +} +#endif + +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) +int get_imx8m_baseboard_id(void); +#endif + +static int get_single_var(char *cmd, char *response) +{ + char *str = cmd; + int chars_left; + const char *s; + struct mmc *mmc; + int mmc_dev_no; + int blksz; + + chars_left = FASTBOOT_RESPONSE_LEN - strlen(response) - 1; + + if ((str = strstr(cmd, "partition-size:"))) { + str +=strlen("partition-size:"); + struct fastboot_ptentry* fb_part; + fb_part = fastboot_flash_find_ptn(str); + if (!fb_part) { + strncat(response, "Wrong partition name.", chars_left); + fastboot_flash_dump_ptn(); + return -1; + } else { + snprintf(response + strlen(response), chars_left, + "0x%llx", + (uint64_t)fb_part->length * get_block_size()); + } + } else if ((str = strstr(cmd, "partition-type:"))) { + str +=strlen("partition-type:"); + struct fastboot_ptentry* fb_part; + fb_part = fastboot_flash_find_ptn(str); + if (!fb_part) { + strncat(response, "Wrong partition name.", chars_left); + fastboot_flash_dump_ptn(); + return -1; + } else { + strncat(response, fb_part->fstype, chars_left); + } + } else if ((str = strstr(cmd, "is-logical:"))) { + str +=strlen("is-logical:"); + struct fastboot_ptentry* fb_part; + fb_part = fastboot_flash_find_ptn(str); + if (!fb_part) { + return -1; + } else { + snprintf(response + strlen(response), chars_left, "no"); + } + } else if (!strcmp_l1("version-baseband", cmd)) { + strncat(response, "N/A", chars_left); + } else if (!strcmp_l1("version-bootloader", cmd) || + !strcmp_l1("bootloader-version", cmd)) { + strncat(response, U_BOOT_VERSION, chars_left); + } else if (!strcmp_l1("version", cmd)) { + strncat(response, FASTBOOT_VERSION, chars_left); + } else if (!strcmp_l1("battery-voltage", cmd)) { + strncat(response, "0mV", chars_left); + } else if (!strcmp_l1("battery-soc-ok", cmd)) { + strncat(response, "yes", chars_left); + } else if (!strcmp_l1("variant", cmd)) { + strncat(response, VARIANT_NAME, chars_left); + } else if (!strcmp_l1("off-mode-charge", cmd)) { + strncat(response, "1", chars_left); + } else if (!strcmp_l1("is-userspace", cmd)) { + strncat(response, FASTBOOT_VAR_NO, chars_left); + } else if (!strcmp_l1("downloadsize", cmd) || + !strcmp_l1("max-download-size", cmd)) { + + snprintf(response + strlen(response), chars_left, "0x%x", CONFIG_FASTBOOT_BUF_SIZE); + } else if (!strcmp_l1("erase-block-size", cmd)) { + mmc_dev_no = mmc_get_env_dev(); + mmc = find_mmc_device(mmc_dev_no); + if (!mmc) { + strncat(response, "FAILCannot get dev", chars_left); + return -1; + } + blksz = get_block_size(); + snprintf(response + strlen(response), chars_left, "0x%x", + (blksz * mmc->erase_grp_size)); + } else if (!strcmp_l1("logical-block-size", cmd)) { + blksz = get_block_size(); + snprintf(response + strlen(response), chars_left, "0x%x", blksz); + } else if (!strcmp_l1("serialno", cmd)) { + s = get_serial(); + if (s) + strncat(response, s, chars_left); + else { + strncat(response, "FAILValue not set", chars_left); + return -1; + } + } else if (!strcmp_l1("product", cmd)) { + strncat(response, PRODUCT_NAME, chars_left); + } +#ifdef CONFIG_IMX_TRUSTY_OS + else if(!strcmp_l1("at-attest-uuid", cmd)) { + char *uuid; + char uuid_str[ATAP_UUID_STR_SIZE]; + if (trusty_atap_read_uuid_str(&uuid)) { + printf("ERROR read uuid failed!\n"); + strncat(response, "FAILCannot get uuid!", chars_left); + return -1; + } else { + uuid_hex2string((uint8_t*)uuid, uuid_str,ATAP_UUID_SIZE, ATAP_UUID_STR_SIZE); + strncat(response, uuid_str, chars_left); + trusty_free(uuid); + } + } + else if(!strcmp_l1("at-attest-dh", cmd)) { + strncat(response, "1:P256,2:curve25519", chars_left); + } +#endif +#if defined(CONFIG_FASTBOOT_LOCK) + else if (!strcmp_l1("secure", cmd)) { + strncat(response, FASTBOOT_VAR_YES, chars_left); + } else if (!strcmp_l1("unlocked",cmd)){ + int status = fastboot_get_lock_stat(); + if (status == FASTBOOT_UNLOCK) { + strncat(response, FASTBOOT_VAR_YES, chars_left); + } else { + strncat(response, FASTBOOT_VAR_NO, chars_left); + } + } +#else + else if (!strcmp_l1("secure", cmd)) { + strncat(response, FASTBOOT_VAR_NO, chars_left); + } else if (!strcmp_l1("unlocked",cmd)) { + strncat(response, FASTBOOT_VAR_NO, chars_left); + } +#endif + else if (is_slotvar(cmd)) { +#ifdef CONFIG_AVB_SUPPORT + if (get_slotvar_avb(&fsl_avb_ab_ops, cmd, + response + strlen(response), chars_left + 1) < 0) + return -1; +#else + strncat(response, FASTBOOT_VAR_NO, chars_left); +#endif + } +#if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) + else if (!strcmp_l1("baseboard_id", cmd)) { + int baseboard_id; + + baseboard_id = get_imx8m_baseboard_id(); + if (baseboard_id < 0) { + printf("Get baseboard id failed!\n"); + strncat(response, "Get baseboard id failed!", chars_left); + return -1; + } else + snprintf(response + strlen(response), chars_left, "0x%x", baseboard_id); + } +#endif +#ifdef CONFIG_AVB_ATX + else if (!strcmp_l1("bootloader-locked", cmd)) { + + /* Below is basically copied from is_hab_enabled() */ + struct imx_sec_config_fuse_t *fuse = + (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse; + uint32_t reg; + int ret; + + /* Read the secure boot status from fuse. */ + ret = fuse_read(fuse->bank, fuse->word, ®); + if (ret) { + printf("\nSecure boot fuse read error!\n"); + strncat(response, "Secure boot fuse read error!", chars_left); + return -1; + } + /* Check if the secure boot bit is enabled */ + if ((reg & 0x2000000) == 0x2000000) + strncat(response, "1", chars_left); + else + strncat(response, "0", chars_left); + } else if (!strcmp_l1("bootloader-min-versions", cmd)) { +#ifndef CONFIG_ARM64 + /* We don't support bootloader rbindex protection for + * ARM32(like imx7d) and the format is: "bootloader,tee". */ + strncat(response, "-1,-1", chars_left); + +#elif defined(CONFIG_DUAL_BOOTLOADER) + /* Rbindex protection for bootloader is supported only when the + * 'dual bootloader' feature is enabled. U-boot will get the rbindx + * from RAM which is passed by spl because we can only get the rbindex + * at spl stage. The format in this case is: "spl,atf,tee,u-boot". + */ + struct bl_rbindex_package *bl_rbindex; + uint32_t rbindex; + + bl_rbindex = (struct bl_rbindex_package *)BL_RBINDEX_LOAD_ADDR; + if (!strncmp(bl_rbindex->magic, BL_RBINDEX_MAGIC, + BL_RBINDEX_MAGIC_LEN)) { + rbindex = bl_rbindex->rbindex; + snprintf(response + strlen(response), chars_left, + "-1,%d,%d,%d",rbindex, rbindex, rbindex); + } else { + printf("Error bootloader rbindex magic!\n"); + strncat(response, "Get bootloader rbindex fail!", chars_left); + return -1; + } +#else + /* Return -1 for all partition if 'dual bootloader' feature + * is not enabled */ + strncat(response, "-1,-1,-1,-1", chars_left); +#endif + } else if (!strcmp_l1("avb-perm-attr-set", cmd)) { + if (perm_attr_are_fused()) + strncat(response, "1", chars_left); + else + strncat(response, "0", chars_left); + } else if (!strcmp_l1("avb-locked", cmd)) { + FbLockState status; + + status = fastboot_get_lock_stat(); + if (status == FASTBOOT_LOCK) + strncat(response, "1", chars_left); + else if (status == FASTBOOT_UNLOCK) + strncat(response, "0", chars_left); + else { + printf("Get lock state error!\n"); + strncat(response, "Get lock state failed!", chars_left); + return -1; + } + } else if (!strcmp_l1("avb-unlock-disabled", cmd)) { + if (at_unlock_vboot_is_disabled()) + strncat(response, "1", chars_left); + else + strncat(response, "0", chars_left); + } else if (!strcmp_l1("avb-min-versions", cmd)) { + int i = 0; + /* rbindex location/value can be very large + * number so we reserve enough space here. + */ + char buffer[35]; + uint32_t rbindex_location[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 2]; + uint32_t location; + uint64_t rbindex; + + memset(buffer, '\0', sizeof(buffer)); + + /* Set rbindex locations. */ + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) + rbindex_location[i] = i; + + /* Set Android Things key version rbindex locations */ + rbindex_location[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS] + = AVB_ATX_PIK_VERSION_LOCATION; + rbindex_location[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 1] + = AVB_ATX_PSK_VERSION_LOCATION; + + /* Read rollback index and set the reponse*/ + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 2; i++) { + location = rbindex_location[i]; + if (fsl_avb_ops.read_rollback_index(&fsl_avb_ops, + location, &rbindex) + != AVB_IO_RESULT_OK) { + printf("Read rollback index error!\n"); + snprintf(response, FASTBOOT_RESPONSE_LEN, + "INFOread rollback index error when get avb-min-versions"); + return -1; + } + /* Generate the "location:value" pair */ + snprintf(buffer, sizeof(buffer), "%d:%lld", location, rbindex); + if (i != AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS + 1) + strncat(buffer, ",", strlen(",")); + + if ((chars_left - (int)strlen(buffer)) >= 0) { + strncat(response, buffer, strlen(buffer)); + chars_left -= strlen(buffer); + } else { + strncat(response, buffer, chars_left); + /* reponse buffer is full, send it first */ + fastboot_tx_write_more(response); + /* reset the reponse buffer for next round */ + memset(response, '\0', FASTBOOT_RESPONSE_LEN); + strncpy(response, "INFO", 5); + /* Copy left strings from 'buffer' to 'response' */ + strncat(response, buffer + chars_left, strlen(buffer)); + chars_left = FASTBOOT_RESPONSE_LEN - + strlen(response) - 1; + } + } + + } +#endif +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + else if (!strcmp_l1("snapshot-update-status", cmd)) { + if (virtual_ab_update_is_merging()) + strncat(response, "merging", chars_left); + else if (virtual_ab_update_is_snapshoted()) + strncat(response, "snapshotted", chars_left); + else + strncat(response, "none", chars_left); + } +#endif + else { + char envstr[32]; + + snprintf(envstr, sizeof(envstr) - 1, "fastboot.%s", cmd); + s = env_get(envstr); + if (s) { + strncat(response, s, chars_left); + } else { + snprintf(response, chars_left, "FAILunknown variable:%s",cmd); + printf("WARNING: unknown variable: %s\n", cmd); + return -1; + } + } + return 0; +} + +void fastboot_getvar(char *cmd, char *response) +{ + int n = 0; + int status = 0; + int count = 0; + char var_name[FASTBOOT_RESPONSE_LEN]; + char partition_base_name[MAX_PTN][20]; + char slot_suffix[2][5] = {"a","b"}; + + if (!cmd) { + pr_err("missing variable"); + fastboot_fail("missing var", response); + return; + } + + if (!strcmp_l1("all", cmd)) { + + memset(response, '\0', FASTBOOT_RESPONSE_LEN); + + + /* get common variables */ + for (n = 0; n < FASTBOOT_COMMON_VAR_NUM; n++) { + snprintf(response, FASTBOOT_RESPONSE_LEN, "INFO%s:", fastboot_common_var[n]); + get_single_var(fastboot_common_var[n], response); + fastboot_tx_write_more(response); + } + + /* get at-vboot-state variables */ +#ifdef CONFIG_AVB_ATX + for (n = 0; n < AT_VBOOT_STATE_VAR_NUM; n++) { + snprintf(response, FASTBOOT_RESPONSE_LEN, "INFO%s:", fastboot_at_vboot_state_var[n]); + get_single_var(fastboot_at_vboot_state_var[n], response); + fastboot_tx_write_more(response); + } +#endif + /* get partition type */ + for (n = 0; n < g_pcount; n++) { + snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOpartition-type:%s:", g_ptable[n].name); + snprintf(var_name, sizeof(var_name), "partition-type:%s", g_ptable[n].name); + get_single_var(var_name, response); + fastboot_tx_write_more(response); + } + /* get partition size */ + for (n = 0; n < g_pcount; n++) { + snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOpartition-size:%s:", g_ptable[n].name); + snprintf(var_name, sizeof(var_name), "partition-size:%s", g_ptable[n].name); + get_single_var(var_name,response); + fastboot_tx_write_more(response); + } + /* slot related variables */ + if (fastboot_parts_is_slot()) { + /* get has-slot variables */ + count = fastboot_parts_get_name(partition_base_name); + for (n = 0; n < count; n++) { + snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOhas-slot:%s:", partition_base_name[n]); + snprintf(var_name, sizeof(var_name), "has-slot:%s", partition_base_name[n]); + get_single_var(var_name,response); + fastboot_tx_write_more(response); + } + /* get current slot */ + strncpy(response, "INFOcurrent-slot:", FASTBOOT_RESPONSE_LEN); + get_single_var("current-slot", response); + fastboot_tx_write_more(response); + /* get slot count */ + strncpy(response, "INFOslot-count:", FASTBOOT_RESPONSE_LEN); + get_single_var("slot-count", response); + fastboot_tx_write_more(response); + /* get slot-successful variable */ + for (n = 0; n < 2; n++) { + snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOslot-successful:%s:", slot_suffix[n]); + snprintf(var_name, sizeof(var_name), "slot-successful:%s", slot_suffix[n]); + get_single_var(var_name, response); + fastboot_tx_write_more(response); + } + /*get slot-unbootable variable*/ + for (n = 0; n < 2; n++) { + snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOslot-unbootable:%s:", slot_suffix[n]); + snprintf(var_name, sizeof(var_name), "slot-unbootable:%s", slot_suffix[n]); + get_single_var(var_name, response); + fastboot_tx_write_more(response); + } + /*get slot-retry-count variable*/ + for (n = 0; n < 2; n++) { + snprintf(response, FASTBOOT_RESPONSE_LEN, "INFOslot-retry-count:%s:", slot_suffix[n]); + snprintf(var_name, sizeof(var_name), "slot-retry-count:%s", slot_suffix[n]); + get_single_var(var_name, response); + fastboot_tx_write_more(response); + } + } + +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + strncpy(response, "INFOsnapshot-update-status:", FASTBOOT_RESPONSE_LEN); + get_single_var("snapshot-update-status", response); + fastboot_tx_write_more(response); +#endif + + strncpy(response, "OKAYDone!", 10); + fastboot_tx_write_more(response); + fastboot_none_resp(response); + + return; + } +#ifdef CONFIG_AVB_ATX + else if (!strcmp_l1("at-vboot-state", cmd)) { + /* get at-vboot-state variables */ + for (n = 0; n < AT_VBOOT_STATE_VAR_NUM; n++) { + snprintf(response, FASTBOOT_RESPONSE_LEN, "INFO%s:", fastboot_at_vboot_state_var[n]); + get_single_var(fastboot_at_vboot_state_var[n], response); + fastboot_tx_write_more(response); + } + + strncpy(response, "OKAY", 5); + fastboot_tx_write_more(response); + fastboot_none_resp(response); + + return; + } else if ((!strcmp_l1("bootloader-locked", cmd)) || + (!strcmp_l1("bootloader-min-versions", cmd)) || + (!strcmp_l1("avb-perm-attr-set", cmd)) || + (!strcmp_l1("avb-locked", cmd)) || + (!strcmp_l1("avb-unlock-disabled", cmd)) || + (!strcmp_l1("avb-min-versions", cmd))) { + + printf("Can't get this variable alone, get 'at-vboot-state' instead!\n"); + fastboot_fail("Can't get this variable alone, get 'at-vboot-state' instead.", response); + return; + } +#endif + else { + char reason[FASTBOOT_RESPONSE_LEN]; + memset(reason, '\0', FASTBOOT_RESPONSE_LEN); + + status = get_single_var(cmd, reason); + if (status != 0) + fastboot_fail(reason, response); + else + fastboot_okay(reason, response); + + return; + } +} diff --git a/drivers/fastboot/fb_fsl/fb_fsl_partitions.c b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c new file mode 100644 index 00000000000..128be79c13d --- /dev/null +++ b/drivers/fastboot/fb_fsl/fb_fsl_partitions.c @@ -0,0 +1,408 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_DM_SCSI +#include +#endif + +#if defined(CONFIG_FASTBOOT_LOCK) +#include "fastboot_lock_unlock.h" +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#include "u-boot/sha256.h" +#include +#endif + + +#ifndef TRUSTY_OS_MMC_BLKS +#define TRUSTY_OS_MMC_BLKS 0x7FF +#endif + +#define MEK_8QM_EMMC 0 + +enum { + PTN_GPT_INDEX = 0, + PTN_TEE_INDEX, +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + PTN_MCU_OS_INDEX, +#endif + PTN_ALL_INDEX, + PTN_BOOTLOADER_INDEX, +}; + +struct fastboot_ptentry g_ptable[MAX_PTN]; +unsigned int g_pcount; + +static ulong bootloader_mmc_offset(void) +{ + if (is_imx8mq() || is_imx8mm() || ((is_imx8qm() || is_imx8qxp()) && is_soc_rev(CHIP_REV_A))) + return 0x8400; + else if (is_imx8qm() || (is_imx8qxp() && !is_soc_rev(CHIP_REV_B))) { + if (MEK_8QM_EMMC == fastboot_devinfo.dev_id) + /* target device is eMMC boot0 partition, bootloader offset is 0x0 */ + return 0x0; + else + /* target device is SD card, bootloader offset is 0x8000 */ + return 0x8000; + } else if (is_imx8mn() || is_imx8mp() || is_imx8dxl()) { + /* target device is eMMC boot0 partition, bootloader offset is 0x0 */ + if (env_get_ulong("emmc_dev", 10, 2) == fastboot_devinfo.dev_id) + return 0; + else + return 0x8000; + } + else if (is_imx8()) + return 0x8000; + else + return 0x400; +} + +bool bootloader_gpt_overlay(void) +{ + return (g_ptable[PTN_GPT_INDEX].partition_id == g_ptable[PTN_BOOTLOADER_INDEX].partition_id && + bootloader_mmc_offset() < ANDROID_GPT_END); +} + +/** + @mmc_dos_partition_index: the partition index in mbr. + @mmc_partition_index: the boot partition or user partition index, + not related to the partition table. + */ +static int _fastboot_parts_add_ptable_entry(int ptable_index, + int mmc_dos_partition_index, + int mmc_partition_index, + const char *name, + const char *fstype, + struct blk_desc *dev_desc, + struct fastboot_ptentry *ptable) +{ + struct disk_partition info; + + if (part_get_info(dev_desc, + mmc_dos_partition_index, &info)) { + debug("Bad partition index:%d for partition:%s\n", + mmc_dos_partition_index, name); + return -1; + } + ptable[ptable_index].start = info.start; + ptable[ptable_index].length = info.size; + ptable[ptable_index].partition_id = mmc_partition_index; + ptable[ptable_index].partition_index = mmc_dos_partition_index; + strncpy(ptable[ptable_index].name, (const char *)info.name, + sizeof(ptable[ptable_index].name) - 1); + +#ifdef CONFIG_PARTITION_UUIDS + strcpy(ptable[ptable_index].uuid, (const char *)info.uuid); +#endif +#ifdef CONFIG_ANDROID_AB_SUPPORT + if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM_A) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM_B) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_A) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_A) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_OEM_B) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_VENDOR_B) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || +#else + if (!strcmp((const char *)info.name, FASTBOOT_PARTITION_SYSTEM) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_DATA) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_DEVICE) || + !strcmp((const char *)info.name, FASTBOOT_PARTITION_CACHE) || +#endif + !strcmp((const char *)info.name, FASTBOOT_PARTITION_METADATA)) + strcpy(ptable[ptable_index].fstype, "ext4"); + else + strcpy(ptable[ptable_index].fstype, "raw"); + return 0; +} + +static int _fastboot_parts_load_from_ptable(void) +{ + int i; + + /* mmc boot partition: -1 means no partition, 0 user part., 1 boot part. + * default is no partition, for emmc default user part, except emmc*/ + int boot_partition = FASTBOOT_MMC_NONE_PARTITION_ID; + int user_partition = FASTBOOT_MMC_NONE_PARTITION_ID; + + struct mmc *mmc; + struct blk_desc *dev_desc; + struct fastboot_ptentry ptable[MAX_PTN]; + + /* sata case in env */ + if (fastboot_devinfo.type == DEV_SATA) { +#ifdef CONFIG_DM_SCSI + int sata_device_no = fastboot_devinfo.dev_id; + puts("flash target is SATA\n"); + scsi_scan(false); + dev_desc = blk_get_dev("scsi", sata_device_no); +#else /*! CONFIG_SATA*/ + puts("SATA isn't buildin\n"); + return -1; +#endif /*! CONFIG_SATA*/ + } else if (fastboot_devinfo.type == DEV_MMC) { + int mmc_no = fastboot_devinfo.dev_id; + + printf("flash target is MMC:%d\n", mmc_no); + mmc = find_mmc_device(mmc_no); + + if (mmc == NULL) { + printf("invalid mmc device %d\n", mmc_no); + return -1; + } + + /* Force to init mmc */ + mmc->has_init = 0; + if (mmc_init(mmc)) + printf("MMC card init failed!\n"); + + dev_desc = blk_get_dev("mmc", mmc_no); + if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) { + printf("** Block device MMC %d not supported\n", + mmc_no); + return -1; + } + + /* multiple boot paritions for eMMC 4.3 later */ + if (mmc->part_config != MMCPART_NOAVAILABLE) { + boot_partition = FASTBOOT_MMC_BOOT_PARTITION_ID; + user_partition = FASTBOOT_MMC_USER_PARTITION_ID; + } + } else { + printf("Can't setup partition table on this device %d\n", + fastboot_devinfo.type); + return -1; + } + + memset((char *)ptable, 0, + sizeof(struct fastboot_ptentry) * (MAX_PTN)); + /* GPT */ + strcpy(ptable[PTN_GPT_INDEX].name, FASTBOOT_PARTITION_GPT); + ptable[PTN_GPT_INDEX].start = ANDROID_GPT_OFFSET / dev_desc->blksz; + ptable[PTN_GPT_INDEX].length = ANDROID_GPT_SIZE / dev_desc->blksz; + ptable[PTN_GPT_INDEX].partition_id = user_partition; + ptable[PTN_GPT_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE; + strcpy(ptable[PTN_GPT_INDEX].fstype, "raw"); + +#ifndef CONFIG_ARM64 + /* Trusty OS */ + strcpy(ptable[PTN_TEE_INDEX].name, FASTBOOT_PARTITION_TEE); + ptable[PTN_TEE_INDEX].start = 0; + ptable[PTN_TEE_INDEX].length = TRUSTY_OS_MMC_BLKS; + ptable[PTN_TEE_INDEX].partition_id = TEE_HWPARTITION_ID; + strcpy(ptable[PTN_TEE_INDEX].fstype, "raw"); +#endif + + /* Add mcu_os partition if we support mcu firmware image flash */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + strcpy(ptable[PTN_MCU_OS_INDEX].name, FASTBOOT_MCU_FIRMWARE_PARTITION); + ptable[PTN_MCU_OS_INDEX].start = ANDROID_MCU_FIRMWARE_START / dev_desc->blksz; + ptable[PTN_MCU_OS_INDEX].length = ANDROID_MCU_FIRMWARE_SIZE / dev_desc->blksz; + ptable[PTN_MCU_OS_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE; + ptable[PTN_MCU_OS_INDEX].partition_id = user_partition; + strcpy(ptable[PTN_MCU_OS_INDEX].fstype, "raw"); +#endif + + strcpy(ptable[PTN_ALL_INDEX].name, FASTBOOT_PARTITION_ALL); + ptable[PTN_ALL_INDEX].start = 0; + ptable[PTN_ALL_INDEX].length = dev_desc->lba; + ptable[PTN_ALL_INDEX].partition_id = user_partition; + strcpy(ptable[PTN_ALL_INDEX].fstype, "device"); + + /* Bootloader */ + strcpy(ptable[PTN_BOOTLOADER_INDEX].name, FASTBOOT_PARTITION_BOOTLOADER); + ptable[PTN_BOOTLOADER_INDEX].start = + bootloader_mmc_offset() / dev_desc->blksz; + ptable[PTN_BOOTLOADER_INDEX].length = + ANDROID_BOOTLOADER_SIZE / dev_desc->blksz; + ptable[PTN_BOOTLOADER_INDEX].partition_id = boot_partition; + ptable[PTN_BOOTLOADER_INDEX].flags = FASTBOOT_PTENTRY_FLAGS_UNERASEABLE; + strcpy(ptable[PTN_BOOTLOADER_INDEX].fstype, "raw"); + + int tbl_idx; + int part_idx = 1; + int ret; + for (tbl_idx = PTN_BOOTLOADER_INDEX + 1; tbl_idx < MAX_PTN; tbl_idx++) { + ret = _fastboot_parts_add_ptable_entry(tbl_idx, + part_idx++, + user_partition, + NULL, + NULL, + dev_desc, ptable); + if (ret) + break; + } + for (i = 0; i < tbl_idx; i++) + fastboot_flash_add_ptn(&ptable[i]); + + return 0; +} + +void fastboot_load_partitions(void) +{ + g_pcount = 0; + _fastboot_parts_load_from_ptable(); +} + +/* + * Android style flash utilties */ +void fastboot_flash_add_ptn(struct fastboot_ptentry *ptn) +{ + if (g_pcount < MAX_PTN) { + memcpy(g_ptable + g_pcount, ptn, sizeof(struct fastboot_ptentry)); + g_pcount++; + } +} + +void fastboot_flash_dump_ptn(void) +{ + unsigned int n; + for (n = 0; n < g_pcount; n++) { + struct fastboot_ptentry *ptn = g_ptable + n; + printf("idx %d, ptn %d name='%s' start=%d len=%ld\n", + n, ptn->partition_index, ptn->name, ptn->start, ptn->length); + } +} + + +struct fastboot_ptentry *fastboot_flash_find_ptn(const char *name) +{ + unsigned int n; + + for (n = 0; n < g_pcount; n++) { + /* Make sure a substring is not accepted */ + if (strlen(name) == strlen(g_ptable[n].name)) { + if (0 == strcmp(g_ptable[n].name, name)) + return g_ptable + n; + } + } + + return 0; +} + +int fastboot_flash_find_index(const char *name) +{ + struct fastboot_ptentry *ptentry = fastboot_flash_find_ptn(name); + if (ptentry == NULL) { + printf("cannot get the partion info for %s\n",name); + fastboot_flash_dump_ptn(); + return -1; + } + return ptentry->partition_index; +} + +struct fastboot_ptentry *fastboot_flash_get_ptn(unsigned int n) +{ + if (n < g_pcount) + return g_ptable + n; + else + return 0; +} + +unsigned int fastboot_flash_get_ptn_count(void) +{ + return g_pcount; +} + +bool fastboot_parts_is_raw(struct fastboot_ptentry *ptn) +{ + if (ptn) { + if (!strncmp(ptn->name, FASTBOOT_PARTITION_BOOTLOADER, + strlen(FASTBOOT_PARTITION_BOOTLOADER))) + return true; +#ifdef CONFIG_ANDROID_AB_SUPPORT + else if (!strncmp(ptn->name, FASTBOOT_PARTITION_GPT, + strlen(FASTBOOT_PARTITION_GPT)) || + !strncmp(ptn->name, FASTBOOT_PARTITION_BOOT_A, + strlen(FASTBOOT_PARTITION_BOOT_A)) || + !strncmp(ptn->name, FASTBOOT_PARTITION_BOOT_B, + strlen(FASTBOOT_PARTITION_BOOT_B))) + return true; +#else + else if (!strncmp(ptn->name, FASTBOOT_PARTITION_BOOT, + strlen(FASTBOOT_PARTITION_BOOT))) + return true; +#endif +#if defined(CONFIG_FASTBOOT_LOCK) + else if (!strncmp(ptn->name, FASTBOOT_PARTITION_FBMISC, + strlen(FASTBOOT_PARTITION_FBMISC))) + return true; +#endif + else if (!strncmp(ptn->name, FASTBOOT_PARTITION_MISC, + strlen(FASTBOOT_PARTITION_MISC))) + return true; + } + + return false; +} + +static bool is_exist(char (*partition_base_name)[20], char *buffer, int count) +{ + int n; + + for (n = 0; n < count; n++) { + if (!strcmp(partition_base_name[n],buffer)) + return true; + } + return false; +} + +/*get partition base name from gpt without "_a/_b"*/ +int fastboot_parts_get_name(char (*partition_base_name)[20]) +{ + int n = 0; + int count = 0; + char *ptr1, *ptr2; + char buffer[20]; + + for (n = 0; n < g_pcount; n++) { + strcpy(buffer,g_ptable[n].name); + ptr1 = strstr(buffer, "_a"); + ptr2 = strstr(buffer, "_b"); + if (ptr1 != NULL) { + *ptr1 = '\0'; + if (!is_exist(partition_base_name,buffer,count)) { + strcpy(partition_base_name[count++],buffer); + } + } else if (ptr2 != NULL) { + *ptr2 = '\0'; + if (!is_exist(partition_base_name,buffer,count)) { + strcpy(partition_base_name[count++],buffer); + } + } else { + strcpy(partition_base_name[count++],buffer); + } + } + return count; +} + +bool fastboot_parts_is_slot(void) +{ + char slot_suffix[2][5] = {"_a","_b"}; + int n; + + for (n = 0; n < g_pcount; n++) { + if (strstr(g_ptable[n].name, slot_suffix[0]) || + strstr(g_ptable[n].name, slot_suffix[1])) + return true; + } + return false; +} + diff --git a/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.c b/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.c new file mode 100644 index 00000000000..11260e6b251 --- /dev/null +++ b/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#include +#include "android_bootloader_message.h" +#include "../lib/avb/fsl/utils.h" +#include "fb_fsl_virtual_ab.h" +#include "fsl_avb.h" +#include "fb_fsl.h" + +static int read_virtual_ab_message(misc_virtual_ab_message *message) +{ + size_t num_bytes; + int source_slot; + + if (fsl_read_from_partition_multi(NULL, FASTBOOT_PARTITION_MISC, + SYSTEM_SPACE_SIZE_IN_MISC, + sizeof(misc_virtual_ab_message), + (void *)message, &num_bytes) || (num_bytes != sizeof(misc_virtual_ab_message))) { + printf("Error reading virtual AB message from misc!\n"); + return -1; + } + + if ((message->magic != MISC_VIRTUAL_AB_MAGIC_HEADER) || + (message->version != MISC_VIRTUAL_AB_MESSAGE_VERSION)) { + printf("Invalid virtual AB status, resetting...\n"); + message->version = MISC_VIRTUAL_AB_MESSAGE_VERSION; + message->magic = MISC_VIRTUAL_AB_MAGIC_HEADER; + message->merge_status = VIRTUAL_AB_NONE; + + /* Reset the source slot as the current slot */ + source_slot = current_slot(); + if (source_slot != -1) + message->source_slot = source_slot; + else + return -1; + + if (fsl_write_to_partition(NULL, FASTBOOT_PARTITION_MISC, + SYSTEM_SPACE_SIZE_IN_MISC, + sizeof(misc_virtual_ab_message), + (void *)message)) { + printf("Error writing virtual AB message to misc!\n"); + return -1; + } + } + + return 0; +} + +/* Flash or erase shall be prohibited to "misc", "userdata" and "metadata" partitions + * when the virtual AB status is VIRTUAL_AB_MERGING or VIRTUAL_AB_SNAPSHOTTED. + * */ +bool partition_is_protected_during_merge(char *part) +{ + if ((!strncmp(part, "misc", sizeof("misc")) || + !strncmp(part, "userdata", sizeof("userdata")) || + !strncmp(part, "metadata", sizeof("metadata"))) && + (virtual_ab_update_is_merging() || + (virtual_ab_update_is_snapshoted() && !virtual_ab_slot_match()))) + return true; + else + return false; +} + +bool virtual_ab_update_is_merging(void) +{ + misc_virtual_ab_message message; + read_virtual_ab_message(&message); + if (message.merge_status == VIRTUAL_AB_MERGING) + return true; + else + return false; +} + +bool virtual_ab_update_is_snapshoted(void) +{ + misc_virtual_ab_message message; + + read_virtual_ab_message(&message); + if (message.merge_status == VIRTUAL_AB_SNAPSHOTTED) + return true; + else + return false; +} + +bool virtual_ab_slot_match(void) +{ + misc_virtual_ab_message message; + read_virtual_ab_message(&message); + + if (message.source_slot == current_slot()) + return true; + else + return false; +} + +int virtual_ab_cancel_update(void) +{ + misc_virtual_ab_message message; + + read_virtual_ab_message(&message); + message.merge_status = VIRTUAL_AB_CANCELLED; + + if (fsl_write_to_partition(NULL, FASTBOOT_PARTITION_MISC, + SYSTEM_SPACE_SIZE_IN_MISC, + sizeof(misc_virtual_ab_message), + (void *)&message)) { + printf("Error writing virtual AB message to misc!\n"); + return -1; + } + + return 0; +} diff --git a/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.h b/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.h new file mode 100644 index 00000000000..13769fdfb04 --- /dev/null +++ b/drivers/fastboot/fb_fsl/fb_fsl_virtual_ab.h @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + */ + +#ifndef __FB_FSL_VIRTUAL_AB_H__ +#define __FB_FSL_VIRTUAL_AB_H__ + +typedef enum { + VIRTUAL_AB_NONE = 0, + VIRTUAL_AB_UNKNOWN, + VIRTUAL_AB_SNAPSHOTTED, + VIRTUAL_AB_MERGING, + VIRTUAL_AB_CANCELLED, +} Virtual_AB_Status; + +bool partition_is_protected_during_merge(char *part); +bool virtual_ab_update_is_merging(void); +bool virtual_ab_update_is_snapshoted(void); +bool virtual_ab_slot_match(void); +int virtual_ab_cancel_update(void); + +#endif diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c index 06e6b2279f6..90deda18a71 100644 --- a/drivers/gpio/mxc_gpio.c +++ b/drivers/gpio/mxc_gpio.c @@ -5,6 +5,9 @@ * * Copyright (C) 2011 * Stefano Babic, DENX Software Engineering, + * + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * */ #include #include @@ -15,6 +18,10 @@ #include #include #include +#ifdef CONFIG_IMX_RDC +#include +#include +#endif enum mxc_gpio_direction { MXC_GPIO_DIRECTION_IN, @@ -70,6 +77,27 @@ static unsigned long gpio_ports[] = { #endif }; +#ifdef CONFIG_IMX_RDC +static unsigned int gpio_rdc[] = { + RDC_PER_GPIO1, + RDC_PER_GPIO2, + RDC_PER_GPIO3, + RDC_PER_GPIO4, + RDC_PER_GPIO5, + RDC_PER_GPIO6, + RDC_PER_GPIO7, +}; + +#define RDC_CHECK(x) imx_rdc_check_permission(gpio_rdc[x], 0) +#define RDC_SPINLOCK_UP(x) imx_rdc_sema_lock(gpio_rdc[x]) +#define RDC_SPINLOCK_DOWN(x) imx_rdc_sema_unlock(gpio_rdc[x]) +#else +#define RDC_CHECK(x) 0 +#define RDC_SPINLOCK_UP(x) +#define RDC_SPINLOCK_DOWN(x) +#endif + + static int mxc_gpio_direction(unsigned int gpio, enum mxc_gpio_direction direction) { @@ -80,6 +108,11 @@ static int mxc_gpio_direction(unsigned int gpio, if (port >= ARRAY_SIZE(gpio_ports)) return -1; + if (RDC_CHECK(port)) + return -1; + + RDC_SPINLOCK_UP(port); + gpio &= 0x1f; regs = (struct gpio_regs *)gpio_ports[port]; @@ -95,6 +128,8 @@ static int mxc_gpio_direction(unsigned int gpio, } writel(l, ®s->gpio_dir); + RDC_SPINLOCK_DOWN(port); + return 0; } @@ -107,6 +142,11 @@ int gpio_set_value(unsigned gpio, int value) if (port >= ARRAY_SIZE(gpio_ports)) return -1; + if (RDC_CHECK(port)) + return -1; + + RDC_SPINLOCK_UP(port); + gpio &= 0x1f; regs = (struct gpio_regs *)gpio_ports[port]; @@ -118,6 +158,8 @@ int gpio_set_value(unsigned gpio, int value) l &= ~(1 << gpio); writel(l, ®s->gpio_dr); + RDC_SPINLOCK_DOWN(port); + return 0; } @@ -130,11 +172,18 @@ int gpio_get_value(unsigned gpio) if (port >= ARRAY_SIZE(gpio_ports)) return -1; + if (RDC_CHECK(port)) + return -1; + + RDC_SPINLOCK_UP(port); + gpio &= 0x1f; regs = (struct gpio_regs *)gpio_ports[port]; - val = (readl(®s->gpio_psr) >> gpio) & 0x01; + val = (readl(®s->gpio_dr) >> gpio) & 0x01; + + RDC_SPINLOCK_DOWN(port); return val; } @@ -144,6 +193,10 @@ int gpio_request(unsigned gpio, const char *label) unsigned int port = GPIO_TO_PORT(gpio); if (port >= ARRAY_SIZE(gpio_ports)) return -1; + + if (RDC_CHECK(port)) + return -1; + return 0; } @@ -211,7 +264,7 @@ static void mxc_gpio_bank_set_value(struct gpio_regs *regs, int offset, static int mxc_gpio_bank_get_value(struct gpio_regs *regs, int offset) { - return (readl(®s->gpio_psr) >> offset) & 0x01; + return (readl(®s->gpio_dr) >> offset) & 0x01; } /* set GPIO pin 'gpio' as an input */ diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 1844941eb21..b990f6fd102 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -169,6 +169,13 @@ config SYS_I2C_IMX_LPI2C help Add support for the NXP i.MX LPI2C driver. +config SYS_I2C_IMX_VIRT_I2C + bool "NXP i.MX Virtual I2C driver" + select IMX_VSERVICE + help + Add support for the NXP i.MX Virtual I2C which needs AMP communtication + to work with remote core to access i2c bus. + config SYS_I2C_MESON bool "Amlogic Meson I2C driver" depends on DM_I2C && ARCH_MESON diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index acd27ac29d2..25c5dd7866f 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o obj-$(CONFIG_SYS_I2C_INTEL) += intel_i2c.o obj-$(CONFIG_SYS_I2C_IMX_LPI2C) += imx_lpi2c.o +obj-$(CONFIG_SYS_I2C_IMX_VIRT_I2C) += imx_virt_i2c.o obj-$(CONFIG_SYS_I2C_IPROC) += iproc_i2c.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o diff --git a/drivers/i2c/imx_lpi2c.c b/drivers/i2c/imx_lpi2c.c index 92c500327b4..961a6b567df 100644 --- a/drivers/i2c/imx_lpi2c.c +++ b/drivers/i2c/imx_lpi2c.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2016 Freescale Semiconductors, Inc. + * Copyright 2019 NXP */ #include @@ -502,6 +503,18 @@ static int imx_lpi2c_probe(struct udevice *bus) return 0; } +int __weak board_imx_lpi2c_bind(struct udevice *dev) +{ + return 0; +} + +static int imx_lpi2c_bind(struct udevice *dev) +{ + debug("imx_lpi2c_bind, %s, seq %d\n", dev->name, dev_seq(dev)); + + return board_imx_lpi2c_bind(dev); +} + static const struct dm_i2c_ops imx_lpi2c_ops = { .xfer = imx_lpi2c_xfer, .probe_chip = imx_lpi2c_probe_chip, @@ -518,6 +531,7 @@ U_BOOT_DRIVER(imx_lpi2c) = { .name = "imx_lpi2c", .id = UCLASS_I2C, .of_match = imx_lpi2c_ids, + .bind = imx_lpi2c_bind, .probe = imx_lpi2c_probe, .priv_auto = sizeof(struct imx_lpi2c_bus), .ops = &imx_lpi2c_ops, diff --git a/drivers/i2c/imx_virt_i2c.c b/drivers/i2c/imx_virt_i2c.c new file mode 100644 index 00000000000..5e0fc78d510 --- /dev/null +++ b/drivers/i2c/imx_virt_i2c.c @@ -0,0 +1,309 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_SRTM_I2C_BUF_SIZE 16 +#define SRTM_I2C_CATEGORY 0x09 +#define SRTM_VERSION 0x0001 +#define SRTM_TYPE_REQ 0x0 +#define SRTM_TYPE_RESP 0x1 +#define SRTM_CMD_READ 0x0 +#define SRTM_CMD_WRITE 0x1 + +#define I2C_M_SELECT_MUX_BUS 0x010000 +#define I2C_M_SRTM_STOP 0x0200 + +struct imx_virt_i2c_bus { + int index; + ulong base; + struct imx_vservice_channel *vservice; +}; + +struct imx_srtm_i2c_msg { + u8 categary; + u8 version[2]; + u8 type; + u8 command; + u8 priority; + u8 reserved[4]; + + u8 i2c_bus; + u8 return_val; + u16 slave_addr; + u16 flag; + u16 data_length; + u8 data_buf[MAX_SRTM_I2C_BUF_SIZE]; +}; + +static void imx_virt_i2c_msg_dump(struct imx_srtm_i2c_msg *msg) +{ + u32 i = 0; + u32 size = sizeof(struct imx_srtm_i2c_msg); + u8 *buf = (u8 *)msg; + + for (; i < size; i++) { + debug("%02x ", buf[i]); + if (i % 16 == 15) + debug("\n"); + } +} + +static int imx_virt_i2c_read(struct udevice *bus, u32 chip, u8 *buf, int len, uint flag) +{ + struct imx_srtm_i2c_msg *msg; + u32 size; + int ret = 0; + struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus); + + debug("imx_virt_i2c_read, bus %d\n", i2c_bus->index); + + if (len > MAX_SRTM_I2C_BUF_SIZE) { + printf("virt_i2c_read exceed the buf length, len=%d\n", len); + return -EINVAL; + } + + size = sizeof(struct imx_srtm_i2c_msg); + msg = imx_vservice_get_buffer(i2c_bus->vservice, size); + if (msg == NULL) + return -ENOMEM; + + /* Fill buf with SRTM i2c format */ + msg->categary = SRTM_I2C_CATEGORY; + msg->version[0] = SRTM_VERSION & 0xff; + msg->version[1] = (SRTM_VERSION >> 8) & 0xff; + msg->type = SRTM_TYPE_REQ; + msg->command = SRTM_CMD_READ; + msg->priority = 1; + + msg->i2c_bus = i2c_bus->index; + msg->return_val = 0; + msg->slave_addr = (u16)chip; + msg->flag = (u16)flag; + msg->data_length = len; + + imx_virt_i2c_msg_dump(msg); + + /* Send request and get return data */ + ret = imx_vservice_blocking_request(i2c_bus->vservice, (u8 *)msg, &size); + if (ret) { + printf("Vservice request is failed, ret %d\n", ret); + return ret; + } + + if (msg->type != SRTM_TYPE_RESP || msg->categary != SRTM_I2C_CATEGORY + || msg->command !=SRTM_CMD_READ) { + printf("Error read response message\n"); + return -EIO; + } + + if (msg->return_val != 0) + return msg->return_val; + + if (len != 0) + memcpy(buf, msg->data_buf, msg->data_length); + + return ret; +} + +static int imx_virt_i2c_write(struct udevice *bus, u32 chip, u8 *buf, int len, uint flag) +{ + struct imx_srtm_i2c_msg *msg; + u32 size; + int ret = 0; + struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus); + + debug("imx_virt_i2c_write, bus %d\n", i2c_bus->index); + + if (len > MAX_SRTM_I2C_BUF_SIZE) { + printf("virt_i2c_read exceed the buf length, len=%d\n", len); + return -EINVAL; + } + + size = sizeof(struct imx_srtm_i2c_msg); + msg = imx_vservice_get_buffer(i2c_bus->vservice, size); + if (msg == NULL) + return -ENOMEM; + + /* Fill buf with SRTM i2c format */ + msg->categary = SRTM_I2C_CATEGORY; + msg->version[0] = SRTM_VERSION & 0xff; + msg->version[1] = (SRTM_VERSION >> 8) & 0xff; + msg->type = SRTM_TYPE_REQ; + msg->command = SRTM_CMD_WRITE; + msg->priority = 1; + + msg->i2c_bus = i2c_bus->index; + msg->return_val = 0; + msg->slave_addr = (u16)chip; + msg->flag = (u16)flag; + msg->data_length = len; + + imx_virt_i2c_msg_dump(msg); + + if (buf) /* probe chip does not have data buffer */ + memcpy(msg->data_buf, buf, msg->data_length); + + /* Send request and get return data */ + ret = imx_vservice_blocking_request(i2c_bus->vservice, (u8 *)msg, &size); + if (ret) { + printf("Vservice request is failed, ret %d\n", ret); + return ret; + } + + if (msg->type != SRTM_TYPE_RESP || msg->categary != SRTM_I2C_CATEGORY + || msg->command !=SRTM_CMD_WRITE) { + printf("Error write response message\n"); + return -EIO; + } + + if (msg->return_val != 0) { + debug("Peer process message, ret %d\n", msg->return_val); + return -EACCES; + } + + debug("imx_vservice_blocking_request get size = %d\n", size); + + return ret; + +} + +static int imx_virt_i2c_probe_chip(struct udevice *bus, u32 chip, + u32 chip_flags) +{ + debug("imx_virt_i2c_probe_chip\n"); + + return imx_virt_i2c_write(bus, chip, NULL, 0, I2C_M_SRTM_STOP); +} + +static int imx_virt_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + int ret = 0; + uint flag = 0; + + for (; nmsgs > 0; nmsgs--, msg++) { + debug("virt_i2c_xfer: chip=0x%x, len=0x%x, buf=0x%08x\n", msg->addr, msg->len, *msg->buf); + + flag = msg->flags; + if (nmsgs == 1) + flag |= I2C_M_SRTM_STOP; + + if (flag & I2C_M_RD) + ret = imx_virt_i2c_read(bus, msg->addr, msg->buf, msg->len, flag); + else { + ret = imx_virt_i2c_write(bus, msg->addr, msg->buf, + msg->len, flag); + if (ret) + break; + } + } + + if (ret) + printf("i2c_xfer: error %d\n", ret); + + return ret; +} + +static int imx_virt_i2c_probe(struct udevice *bus) +{ + struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus); + fdt_addr_t addr; + + addr = dev_read_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + i2c_bus->base = addr; + i2c_bus->index = dev_seq(bus); + + debug("virt_i2c : controller bus %d at 0x%lx, bus udev 0x%lx\n", + dev_seq(bus), i2c_bus->base, (ulong)bus); + + i2c_bus->vservice = imx_vservice_setup(bus); + if (i2c_bus->vservice == NULL) { + printf("virt_i2c: Faild to setup vservice\n"); + return -ENODEV; + } + + return 0; +} + +static int imx_virt_i2c_set_flags(struct udevice *child_dev, uint flags) +{ +#ifdef CONFIG_I2C_MUX_IMX_VIRT + if (child_dev->uclass->uc_drv->id == UCLASS_I2C_MUX) { + struct udevice *bus = child_dev->parent; + struct imx_virt_i2c_bus *i2c_bus = dev_get_priv(bus); + + if (flags == 0) { + i2c_bus->index = dev_seq(bus); + } else if (flags & I2C_M_SELECT_MUX_BUS) { + i2c_bus->index = (flags >> 24) & 0xff; + } + + debug("virt_i2c_set_flags bus %d\n", i2c_bus->index); + } +#endif + return 0; +} + +int __weak board_imx_virt_i2c_bind(struct udevice *dev) +{ + return 0; +} + +static int imx_virt_i2c_bind(struct udevice *dev) +{ + debug("imx_virt_i2c_bind, %s, seq %d\n", dev->name, dev_seq(dev)); + + return board_imx_virt_i2c_bind(dev); +} + +static int imx_virt_i2c_child_post_bind(struct udevice *child_dev) +{ +#ifdef CONFIG_I2C_MUX_IMX_VIRT + if (child_dev->uclass->uc_drv->id == UCLASS_I2C_MUX) { + if (!strcmp(child_dev->driver->name, "imx_virt_i2c_mux")) + return 0; + else + return -ENODEV; + } +#endif + + return 0; +} + +static const struct dm_i2c_ops imx_virt_i2c_ops = { + .xfer = imx_virt_i2c_xfer, + .probe_chip = imx_virt_i2c_probe_chip, + .set_flags = imx_virt_i2c_set_flags, +}; + +static const struct udevice_id imx_virt_i2c_ids[] = { + { .compatible = "fsl,imx-virt-i2c", }, + {} +}; + +U_BOOT_DRIVER(imx_virt_i2c) = { + .name = "imx_virt_i2c", + .id = UCLASS_I2C, + .of_match = imx_virt_i2c_ids, + .bind = imx_virt_i2c_bind, + .probe = imx_virt_i2c_probe, + .child_post_bind = imx_virt_i2c_child_post_bind, + .priv_auto = sizeof(struct imx_virt_i2c_bus), + .ops = &imx_virt_i2c_ops, + .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF | DM_FLAG_IGNORE_DEFAULT_CLKS, +}; diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 39683fc43b4..be8eed17b82 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -36,6 +36,12 @@ config I2C_MUX_PCA954x device. Supported chips are PCA9543, PCA9544, PCA9546, PCA9547, PCA9548 and PCA9646. +config I2C_MUX_IMX_VIRT + bool "i.MX Virtual I2C Mux/switches" + depends on I2C_MUX && SYS_I2C_IMX_VIRT_I2C + help + If you say yes here you get support for the i.MX Virtual I2C mux + config I2C_MUX_GPIO tristate "GPIO-based I2C multiplexer" depends on I2C_MUX && DM_GPIO diff --git a/drivers/i2c/muxes/Makefile b/drivers/i2c/muxes/Makefile index b690821199f..795c292cd28 100644 --- a/drivers/i2c/muxes/Makefile +++ b/drivers/i2c/muxes/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o obj-$(CONFIG_I2C_MUX) += i2c-mux-uclass.o obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o +obj-$(CONFIG_I2C_MUX_IMX_VIRT) += imx_virt_i2c_mux.o diff --git a/drivers/i2c/muxes/imx_virt_i2c_mux.c b/drivers/i2c/muxes/imx_virt_i2c_mux.c new file mode 100644 index 00000000000..fb54550333e --- /dev/null +++ b/drivers/i2c/muxes/imx_virt_i2c_mux.c @@ -0,0 +1,73 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include + +#include + +#define I2C_M_SELECT_MUX_BUS 0x010000 + +struct imx_virt_i2c_mux_priv { + u32 addr; /* I2C mux address */ + u32 i2c_bus_alias_off; +}; + +static int imx_virt_i2c_mux_deselect(struct udevice *mux, struct udevice *bus, + uint channel) +{ + return i2c_set_chip_flags(mux, 0); +} + +static int imx_virt_i2c_mux_select(struct udevice *mux, struct udevice *bus, + uint channel) +{ + struct imx_virt_i2c_mux_priv *priv = dev_get_priv(mux); + uint flags = I2C_M_SELECT_MUX_BUS; + + flags |= ((priv->i2c_bus_alias_off + channel) << 24); + + return i2c_set_chip_flags(mux, flags); +} + +static const struct i2c_mux_ops imx_virt_i2c_mux_ops = { + .select = imx_virt_i2c_mux_select, + .deselect = imx_virt_i2c_mux_deselect, +}; + +static const struct udevice_id imx_virt_i2c_mux_ids[] = { + { .compatible = "fsl,imx-virt-i2c-mux", }, + { } +}; + +static int imx_virt_i2c_mux_probe(struct udevice *dev) +{ + struct imx_virt_i2c_mux_priv *priv = dev_get_priv(dev); + + priv->addr = dev_read_u32_default(dev, "reg", 0); + if (!priv->addr) { + debug("MUX not found\n"); + return -ENODEV; + } + + priv->i2c_bus_alias_off = dev_read_u32_default(dev, "virtual-bus-seq", 0); + + debug("Device %s at 0x%x with i2c_bus_alias_off %d\n", + dev->name, priv->addr, priv->i2c_bus_alias_off); + return 0; +} + +U_BOOT_DRIVER(imx_virt_i2c_mux) = { + .name = "imx_virt_i2c_mux", + .id = UCLASS_I2C_MUX, + .of_match = imx_virt_i2c_mux_ids, + .probe = imx_virt_i2c_mux_probe, + .ops = &imx_virt_i2c_mux_ops, + .priv_auto = sizeof(struct imx_virt_i2c_mux_priv), +}; diff --git a/drivers/input/Makefile b/drivers/input/Makefile index e440c921e4e..e45b6d1ec53 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -14,4 +14,5 @@ obj-$(CONFIG_I8042_KEYB) += i8042.o obj-$(CONFIG_TEGRA_KEYBOARD) += input.o tegra-kbc.o obj-$(CONFIG_TWL4030_INPUT) += twl4030.o obj-$(CONFIG_TWL6030_INPUT) += twl6030.o +obj-$(CONFIG_MXC_KPD) += mxc_keyb.o endif diff --git a/drivers/input/mxc_keyb.c b/drivers/input/mxc_keyb.c new file mode 100644 index 00000000000..09b8ec12bee --- /dev/null +++ b/drivers/input/mxc_keyb.c @@ -0,0 +1,592 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +/*! + * @file mxc_keyb.c + * + * @brief Driver for the Freescale Semiconductor MXC keypad port. + * + * The keypad driver is designed as a standard Input driver which interacts + * with low level keypad port hardware. Upon opening, the Keypad driver + * initializes the keypad port. When the keypad interrupt happens the driver + * calles keypad polling timer and scans the keypad matrix for key + * press/release. If all key press/release happened it comes out of timer and + * waits for key press interrupt. The scancode for key press and release events + * are passed to Input subsytem. + * + * @ingroup keypad + */ + +#include +#include +#include +#include +#include +#include + +/* + * * Module header file + * */ +#include + +/*! + * Comment KPP_DEBUG to disable debug messages + */ + +#undef KPP_DEBUG + +#ifdef KPP_DEBUG +#define KPP_PRINTF(fmt, args...) printf(fmt , ##args) + +static void mxc_kpp_dump_regs() +{ + unsigned short t1, t2, t3; + + t1 = __raw_readw(KPCR); + t2 = __raw_readw(KPSR); + t3 = __raw_readw(KDDR); + /* + KPP_PRINTF("KPCR=0x%04x, KPSR=0x%04x, KDDR=0x%04x\n", + t1, t2, t3); + */ +} +#else +#define KPP_PRINTF(fmt, args...) +#endif + +static u16 mxc_key_mapping[] = CONFIG_MXC_KEYMAPPING; + +/*! + * This structure holds the keypad private data structure. + */ +static struct keypad_priv kpp_dev; + +/*! Indicates if the key pad device is enabled. */ + +/*! This static variable indicates whether a key event is pressed/released. */ +static unsigned short KPress; + +/*! cur_rcmap and prev_rcmap array is used to detect key press and release. */ +static unsigned short *cur_rcmap; /* max 64 bits (8x8 matrix) */ +static unsigned short *prev_rcmap; + +/*! + * Debounce polling period(10ms) in system ticks. + */ +/*static unsigned short KScanRate = (10 * CONFIG_SYS_HZ) / 1000;*/ + +/*! + * These arrays are used to store press and release scancodes. + */ +static short **press_scancode; +static short **release_scancode; + +static const unsigned short *mxckpd_keycodes; +static unsigned short mxckpd_keycodes_size; + +/*! + * This function is called to scan the keypad matrix to find out the key press + * and key release events. Make scancode and break scancode are generated for + * key press and key release events. + * + * The following scanning sequence are done for + * keypad row and column scanning, + * -# Write 1's to KPDR[15:8], setting column data to 1's + * -# Configure columns as totem pole outputs(for quick discharging of keypad + * capacitance) + * -# Configure columns as open-drain + * -# Write a single column to 0, others to 1. + * -# Sample row inputs and save data. Multiple key presses can be detected on + * a single column. + * -# Repeat steps the above steps for remaining columns. + * -# Return all columns to 0 in preparation for standby mode. + * -# Clear KPKD and KPKR status bit(s) by writing to a 1, + * Set the KPKR synchronizer chain by writing "1" to KRSS register, + * Clear the KPKD synchronizer chain by writing "1" to KDSC register + * + * @result Number of key pressed/released. + */ +static int mxc_kpp_scan_matrix(void) +{ + unsigned short reg_val; + int col, row; + short scancode = 0; + int keycnt = 0; /* How many keys are still pressed */ + + /* + * wmb() linux kernel function which guarantees orderings in write + * operations + */ + /* wmb(); */ + + /* save cur keypad matrix to prev */ + memcpy(prev_rcmap, cur_rcmap, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + + /*1. Disable both (depress and release) keypad interrupts.*/ + + /* KDIE has been disabled in mxc_kpp_getc before calling scan matrix. + * KRIE is always disabled in this driver. + */ + + for (col = 0; col < kpp_dev.kpp_cols; col++) { /* Col */ + /* 2. Write 1.s to KPDR[15:8] setting column data to 1.s */ + reg_val = __raw_readw(KPDR); + reg_val |= 0xff00; + __raw_writew(reg_val, KPDR); + + /* + * 3. Configure columns as totem pole outputs(for quick + * discharging of keypad capacitance) + */ + reg_val = __raw_readw(KPCR); + reg_val &= 0x00ff; + __raw_writew(reg_val, KPCR); + + udelay(2); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* + * 4. Configure columns as open-drain + */ + reg_val = __raw_readw(KPCR); + reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8; + __raw_writew(reg_val, KPCR); + + /* + * 5. Write a single column to 0, others to 1. + * 6. Sample row inputs and save data. Multiple key presses + * can be detected on a single column. + * 7. Repeat steps 2 - 6 for remaining columns. + */ + + /* Col bit starts at 8th bit in KPDR */ + reg_val = __raw_readw(KPDR); + reg_val &= ~(1 << (8 + col)); + __raw_writew(reg_val, KPDR); + + /* Delay added to avoid propagating the 0 from column to row + * when scanning. */ + + udelay(5); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* Read row input */ + reg_val = __raw_readw(KPDR); + for (row = 0; row < kpp_dev.kpp_rows; row++) { /* sample row */ + if (TEST_BIT(reg_val, row) == 0) { + cur_rcmap[row] = BITSET(cur_rcmap[row], col); + keycnt++; + } + } + } + + /* + * 8. Return all columns to 0 in preparation for standby mode. + * 9. Clear KPKD and KPKR status bit(s) by writing to a .1., + * set the KPKR synchronizer chain by writing "1" to KRSS register, + * clear the KPKD synchronizer chain by writing "1" to KDSC register + */ + reg_val = 0x00; + __raw_writew(reg_val, KPDR); + reg_val = __raw_readw(KPDR); + reg_val = __raw_readw(KPSR); + reg_val |= KBD_STAT_KPKD | KBD_STAT_KPKR | KBD_STAT_KRSS | + KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* Check key press status change */ + + /* + * prev_rcmap array will contain the previous status of the keypad + * matrix. cur_rcmap array will contains the present status of the + * keypad matrix. If a bit is set in the array, that (row, col) bit is + * pressed, else it is not pressed. + * + * XORing these two variables will give us the change in bit for + * particular row and column. If a bit is set in XOR output, then that + * (row, col) has a change of status from the previous state. From + * the diff variable the key press and key release of row and column + * are found out. + * + * If the key press is determined then scancode for key pressed + * can be generated using the following statement: + * scancode = ((row * 8) + col); + * + * If the key release is determined then scancode for key release + * can be generated using the following statement: + * scancode = ((row * 8) + col) + MXC_KEYRELEASE; + */ + for (row = 0; row < kpp_dev.kpp_rows; row++) { + unsigned char diff; + + /* + * Calculate the change in the keypad row status + */ + diff = prev_rcmap[row] ^ cur_rcmap[row]; + + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((diff >> col) & 0x1) { + /* There is a status change on col */ + if ((prev_rcmap[row] & BITSET(0, col)) == 0) { + /* + * Previous state is 0, so now + * a key is pressed + */ + scancode = + ((row * kpp_dev.kpp_cols) + + col); + KPress = 1; + kpp_dev.iKeyState = KStateUp; + + KPP_PRINTF("Press (%d, %d) scan=%d " + "Kpress=%d\n", + row, col, scancode, KPress); + press_scancode[row][col] = + (short)scancode; + } else { + /* + * Previous state is not 0, so + * now a key is released + */ + scancode = + (row * kpp_dev.kpp_cols) + + col + MXC_KEYRELEASE; + KPress = 0; + kpp_dev.iKeyState = KStateDown; + + KPP_PRINTF + ("Release (%d, %d) scan=%d Kpress=%d\n", + row, col, scancode, KPress); + release_scancode[row][col] = + (short)scancode; + keycnt++; + } + } + } + } + + return keycnt; +} + +static int mxc_kpp_reset(void) +{ + unsigned short reg_val; + int i; + + /* + * Stop scanning and wait for interrupt. + * Enable press interrupt and disable release interrupt. + */ + __raw_writew(0x00FF, KPDR); + reg_val = __raw_readw(KPSR); + reg_val |= (KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + /* + * No more keys pressed... make sure unwanted key codes are + * not given upstairs + */ + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * + kpp_dev.kpp_cols); + } + + return 0; +} + +int mxc_kpp_getc(struct kpp_key_info **key_info) +{ + int col, row; + int key_cnt; + unsigned short reg_val; + short scancode = 0; + int index = 0; + struct kpp_key_info *keyi; + + reg_val = __raw_readw(KPSR); + + if (reg_val & KBD_STAT_KPKD) { + /* + * Disable key press(KDIE status bit) interrupt + */ + reg_val &= ~KBD_STAT_KDIE; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + key_cnt = mxc_kpp_scan_matrix(); + } else { + return 0; + } + + if (key_cnt <= 0) + return 0; + + *key_info = keyi = + (struct kpp_key_info *)malloc + (sizeof(struct kpp_key_info) * key_cnt); + + /* + * This switch case statement is the + * implementation of state machine of debounc + * logic for key press/release. + * The explaination of state machine is as + * follows: + * + * KStateUp State: + * This is in intial state of the state machine + * this state it checks for any key presses. + * The key press can be checked using the + * variable KPress. If KPress is set, then key + * press is identified and switches the to + * KStateFirstDown state for key press to + * debounce. + * + * KStateFirstDown: + * After debounce delay(10ms), if the KPress is + * still set then pass scancode generated to + * input device and change the state to + * KStateDown, else key press debounce is not + * satisfied so change the state to KStateUp. + * + * KStateDown: + * In this state it checks for any key release. + * If KPress variable is cleared, then key + * release is indicated and so, switch the + * state to KStateFirstUp else to state + * KStateDown. + * + * KStateFirstUp: + * After debounce delay(10ms), if the KPress is + * still reset then pass the key release + * scancode to input device and change + * the state to KStateUp else key release is + * not satisfied so change the state to + * KStateDown. + */ + + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((press_scancode[row][col] != -1)) { + /* Still Down, so add scancode */ + scancode = + press_scancode[row][col]; + + keyi[index].val = mxckpd_keycodes[scancode]; + keyi[index++].evt = KDepress; + + KPP_PRINTF("KStateFirstDown: scan=%d val=%d\n", + scancode, mxckpd_keycodes[scancode]); + if (index >= key_cnt) + goto key_detect; + + kpp_dev.iKeyState = KStateDown; + press_scancode[row][col] = -1; + } + } + } + + for (row = 0; row < kpp_dev.kpp_rows; row++) { + for (col = 0; col < kpp_dev.kpp_cols; col++) { + if ((release_scancode[row][col] != -1)) { + scancode = + release_scancode[row][col]; + scancode = + scancode - MXC_KEYRELEASE; + + keyi[index].val = mxckpd_keycodes[scancode]; + keyi[index++].evt = KRelease; + + KPP_PRINTF("KStateFirstUp: scan=%d val=%d\n", + scancode, mxckpd_keycodes[scancode]); + if (index >= key_cnt) + goto key_detect; + + kpp_dev.iKeyState = KStateUp; + release_scancode[row][col] = -1; + } + } + } + +key_detect: + mxc_kpp_reset(); + return key_cnt; +} + +/*! + * This function is called to free the allocated memory for local arrays + */ +static void mxc_kpp_free_allocated(void) +{ + int i; + + if (press_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (press_scancode[i]) + free(press_scancode[i]); + } + free(press_scancode); + } + + if (release_scancode) { + for (i = 0; i < kpp_dev.kpp_rows; i++) { + if (release_scancode[i]) + free(release_scancode[i]); + } + free(release_scancode); + } + + if (cur_rcmap) + free(cur_rcmap); + + if (prev_rcmap) + free(prev_rcmap); +} + +/*! + * This function is called during the driver binding process. + * + * @param pdev the device structure used to store device specific + * information that is used by the suspend, resume and remove + * functions. + * + * @return The function returns 0 on successful registration. Otherwise returns + * specific error code. + */ +int mxc_kpp_init(void) +{ + int i; + int retval; + unsigned int reg_val; + + kpp_dev.kpp_cols = CONFIG_MXC_KPD_COLMAX; + kpp_dev.kpp_rows = CONFIG_MXC_KPD_ROWMAX; + + /* clock and IOMUX configuration for keypad */ + setup_mxc_kpd(); + + /* Configure keypad */ + + /* Enable number of rows in keypad (KPCR[7:0]) + * Configure keypad columns as open-drain (KPCR[15:8]) + * + * Configure the rows/cols in KPP + * LSB nibble in KPP is for 8 rows + * MSB nibble in KPP is for 8 cols + */ + reg_val = __raw_readw(KPCR); + reg_val |= (1 << kpp_dev.kpp_rows) - 1; /* LSB */ + reg_val |= ((1 << kpp_dev.kpp_cols) - 1) << 8; /* MSB */ + __raw_writew(reg_val, KPCR); + + /* Write 0's to KPDR[15:8] */ + reg_val = __raw_readw(KPDR); + reg_val &= 0x00ff; + __raw_writew(reg_val, KPDR); + + /* Configure columns as output, + * rows as input (KDDR[15:0]) */ + reg_val = __raw_readw(KDDR); + reg_val |= 0xff00; + reg_val &= 0xff00; + __raw_writew(reg_val, KDDR); + + /* Clear the KPKD Status Flag + * and Synchronizer chain. */ + reg_val = __raw_readw(KPSR); + reg_val &= ~(KBD_STAT_KPKR | KBD_STAT_KPKD); + reg_val |= KBD_STAT_KPKD; + reg_val |= KBD_STAT_KRSS | KBD_STAT_KDSC; + __raw_writew(reg_val, KPSR); + /* Set the KDIE control bit, and clear the KRIE + * control bit (avoid false release events). */ + reg_val |= KBD_STAT_KDIE; + reg_val &= ~KBD_STAT_KRIE; + __raw_writew(reg_val, KPSR); + +#ifdef KPP_DEBUG + mxc_kpp_dump_regs(); +#endif + + mxckpd_keycodes = mxc_key_mapping; + mxckpd_keycodes_size = kpp_dev.kpp_cols * kpp_dev.kpp_rows; + + if ((mxckpd_keycodes == (void *)0) + || (mxckpd_keycodes_size == 0)) { + retval = -ENODEV; + goto err; + } + + /* allocate required memory */ + press_scancode = (short **)malloc(kpp_dev.kpp_rows * sizeof(press_scancode[0])); + release_scancode = (short **)malloc(kpp_dev.kpp_rows * sizeof(release_scancode[0])); + + if (!press_scancode || !release_scancode) { + retval = -ENOMEM; + goto err; + } + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + press_scancode[i] = (short *)malloc(kpp_dev.kpp_cols + * sizeof(press_scancode[0][0])); + release_scancode[i] = + (short *)malloc(kpp_dev.kpp_cols * sizeof(release_scancode[0][0])); + + if (!press_scancode[i] || !release_scancode[i]) { + retval = -ENOMEM; + goto err; + } + } + + cur_rcmap = + (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + prev_rcmap = + (unsigned short *)malloc(kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + + if (!cur_rcmap || !prev_rcmap) { + retval = -ENOMEM; + goto err; + } + + for (i = 0; i < kpp_dev.kpp_rows; i++) { + memset(press_scancode[i], -1, + sizeof(press_scancode[0][0]) * kpp_dev.kpp_cols); + memset(release_scancode[i], -1, + sizeof(release_scancode[0][0]) * kpp_dev.kpp_cols); + } + memset(cur_rcmap, 0, kpp_dev.kpp_rows * sizeof(cur_rcmap[0])); + memset(prev_rcmap, 0, kpp_dev.kpp_rows * sizeof(prev_rcmap[0])); + + return 0; + +err: + mxc_kpp_free_allocated(); + return retval; +} diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index dd4b0ac0c33..3408c21eecd 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -47,4 +47,12 @@ config ZYNQMP_IPI help This enables support for the Xilinx ZynqMP Inter Processor Interrupt communication controller. + +config IMX_MU + bool "Enable i.MX MU support" + depends on DM_MAILBOX + help + Enable support for i.MX Messaging Unit for communication with other + processors on the SoC + endmenu diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index d2ace8cd212..6983cb57888 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -10,3 +10,4 @@ obj-$(CONFIG_STM32_IPCC) += stm32-ipcc.o obj-$(CONFIG_TEGRA_HSP) += tegra-hsp.o obj-$(CONFIG_K3_SEC_PROXY) += k3-sec-proxy.o obj-$(CONFIG_ZYNQMP_IPI) += zynqmp-ipi.o +obj-$(CONFIG_IMX_MU) += imx-mu.o diff --git a/drivers/mailbox/imx-mu.c b/drivers/mailbox/imx-mu.c new file mode 100644 index 00000000000..d08f9d1500d --- /dev/null +++ b/drivers/mailbox/imx-mu.c @@ -0,0 +1,191 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include + +#define NUM_MU_CHANNELS 4 +#define NUM_MU_FLAGS 4 +#define NUM_MU_GIP 4 + +#define mu_rr(x) (0x10 + (x * 0x4)) +#define mu_tr(x) (x * 0x4) +#define MU_SR_OFFSET 0x20 +#define MU_CR_OFFSET 0x24 +#define CHAN_TE_MASK(x) (0x00100000 << (x)) +#define CHAN_RF_MASK(x) (0x01000000 << (x)) +#define MU_CR_INT_MSK 0xFFF00000 +#define MU_FLGS_MSK 0x00000007 +#define MU_GIP_MSK 0xF0000000 + + + +/* This driver only exposes the status bits to keep with the + * polling methodology of u-boot. + */ + +DECLARE_GLOBAL_DATA_PTR; + +struct imx_mu_mbox { + fdt_addr_t base; + + /* use pointers to channel as a way to reserve channels */ + void *channels[NUM_MU_CHANNELS]; + bool flags[NUM_MU_FLAGS]; + + /* TODO add support for the reading/setting of flags to + * B side of MU + */ +}; + + +/* check that the channel is open or owned by caller */ +static int mu_check_channel(struct mbox_chan *chan) +{ + struct imx_mu_mbox *mailbox = dev_get_priv(chan->dev); + + /* use id as number of channel within mbox only */ + if ((chan->id < 0) || (chan->id >= NUM_MU_CHANNELS)) { + debug("nxp mu id out of range: %lu\n", chan->id); + return -EINVAL; + } + if (mailbox->channels[chan->id] != NULL) { + /* if reserved check that caller owns */ + if (mailbox->channels[chan->id] == chan) + return 1; /* caller owns the channel */ + + return -EACCES; + } + return 0;/* channel empty */ +} + +static int mu_chan_request(struct mbox_chan *chan) +{ + struct imx_mu_mbox *mailbox = dev_get_priv(chan->dev); + + debug("%s(chan=%p)\n", __func__, chan); + + int status = mu_check_channel(chan); + if (status < 0) { + debug("channel not available :%d\n", status); + return -EPERM; + } + mailbox->channels[chan->id] = chan; + + return 0; +} +/* currently not dynamically allocated + * only change pointer back to NULL */ +static int mu_chan_free(struct mbox_chan *chan) +{ + struct imx_mu_mbox *mailbox = dev_get_priv(chan->dev); + int status = mu_check_channel(chan); + + debug("%s(chan=%p)\n", __func__, chan); + if (status <= 0) { /* check that the channel is also not empty */ + debug("mu_chan_free() failed exit code: %d\n", status); + return status; + } + /*if you own channel and channel is NOT empty */ + mailbox->channels[chan->id] = NULL; + + return 0; +} + +static int mu_send(struct mbox_chan *chan, const void *data) +{ + struct imx_mu_mbox *mbox = dev_get_priv(chan->dev); + int status = mu_check_channel(chan); + uint32_t val = *((uint32_t *)data); + + debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + if (status < 1) { + debug("mu_send() failed. mu_chan_status is :%d\n", status); + return -EPERM; + } + + /*check if transmit register is empty */ + if (!(readl(mbox->base+MU_SR_OFFSET) & CHAN_TE_MASK(chan->id))) + return -EBUSY; + + /* send out on transmit register*/ + writel(val, mbox->base + mu_tr(chan->id)); + return 0; +} + +static int mu_recv(struct mbox_chan *chan, void *data) +{ + struct imx_mu_mbox *mbox = dev_get_priv(chan->dev); + int status = mu_check_channel(chan); + uint32_t *buffer = data; + + debug("%s(chan=%p, data=%p)\n", __func__, chan, data); + + if (status < 1) + return -EPERM; /* return if channel isnt owned */ + + if (readl(mbox->base + MU_SR_OFFSET) & CHAN_RF_MASK(chan->id)) + return -ENODATA; + + *buffer = readl(mu_rr(chan->id)); + + return 0; +} + +static int imx_mu_bind(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static int imx_mu_probe(struct udevice *dev) +{ + struct imx_mu_mbox *mbox = dev_get_priv(dev); + uint32_t val; + debug("%s(dev=%p)\n", __func__, dev); + + /* get address from device tree */ + mbox->base = dev_get_addr(dev); + if (mbox->base == FDT_ADDR_T_NONE) + return -ENODEV; + + val = readl(mbox->base + MU_CR_OFFSET); + val = val & ~MU_CR_INT_MSK;/* disable all interrupts */ + val = val & ~MU_FLGS_MSK; /* clear all flags */ + + writel(val, mbox->base + MU_CR_OFFSET); + + val = readl(mbox->base + MU_SR_OFFSET); + val = val | MU_GIP_MSK; /* clear any pending GIP */ + writel(val, mbox->base + MU_SR_OFFSET); + + return 0; +} + +static const struct udevice_id imx_mu_ids[] = { + { .compatible = "nxp,imx-mu" }, + { } +}; + +struct mbox_ops imx_mu_mbox_ops = { + .request = mu_chan_request, + .free = mu_chan_free, + .send = mu_send, + .recv = mu_recv, +}; + +U_BOOT_DRIVER(imx_mu) = { + .name = "imx-mu", + .id = UCLASS_MAILBOX, + .of_match = imx_mu_ids, + .bind = imx_mu_bind, + .probe = imx_mu_probe, + .priv_auto_alloc_size = sizeof(struct imx_mu_mbox), + .ops = &imx_mu_mbox_ops, +}; diff --git a/drivers/mailbox/mailbox-uclass.c b/drivers/mailbox/mailbox-uclass.c index c972d846089..57b30f14575 100644 --- a/drivers/mailbox/mailbox-uclass.c +++ b/drivers/mailbox/mailbox-uclass.c @@ -113,13 +113,29 @@ int mbox_free(struct mbox_chan *chan) return 0; } -int mbox_send(struct mbox_chan *chan, const void *data) +int mbox_send(struct mbox_chan *chan, const void *data, ulong timeout_us) { struct mbox_ops *ops = mbox_dev_ops(chan->dev); + ulong start_time; + int ret; debug("%s(chan=%p, data=%p)\n", __func__, chan, data); - return ops->send(chan, data); + start_time = timer_get_us(); + /* + * Account for partial us ticks, but if timeout_us is 0, ensure we + * still don't wait at all. + */ + if (timeout_us) + timeout_us++; + + for (;;) { + ret = ops->send(chan, data); + if (ret != -EBUSY) + return ret; + if ((timer_get_us() - start_time) >= timeout_us) + return -ETIMEDOUT; + } } int mbox_recv(struct mbox_chan *chan, void *data, ulong timeout_us) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 7d2a2997797..58e76d6411c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -211,10 +211,9 @@ config FSL_SEC_MON like software violations or hardware security violations. config IRQ - bool "Intel Interrupt controller" - depends on X86 || SANDBOX + bool "Interrupt controller" help - This enables support for Intel interrupt controllers, including ITSS. + This enables support for interrupt controllers, including ITSS. Some devices have extra features, such as Apollo Lake. The device has its own uclass since there are several operations involved. @@ -234,6 +233,13 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config IMX_M4_MU + bool "Enable i.MX MU Driver to communicate with Cortex M4" + depends on MISC + help + If you say Y here to enable Message Unit driver to work with + Cortex M4 core on AMP Freescale i.MX processors. + config NUVOTON_NCT6102D bool "Enable Nuvoton NCT6102D Super I/O driver" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 1a493960074..58501b0302b 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o obj-$(CONFIG_SANDBOX) += p2sb_sandbox.o p2sb_emul.o obj-$(CONFIG_SANDBOX) += swap_case.o +obj-$(CONFIG_IMX_M4_MU) += imx_m4_mu.o endif ifdef CONFIG_$(SPL_)DM_I2C diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 38111c52548..9de05914284 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -20,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_IMX8QM #define FSL_ECC_WORD_START_2 0x1A0 #define FSL_ECC_WORD_END_2 0x1FF -#elif defined(CONFIG_IMX8QXP) +#elif defined(CONFIG_IMX8QXP) || defined(CONFIG_IMX8DXL) #define FSL_ECC_WORD_START_2 0x220 #define FSL_ECC_WORD_END_2 0x31F #endif @@ -55,13 +56,14 @@ int fuse_sense(u32 bank, u32 word, u32 *val) int fuse_prog(u32 bank, u32 word, u32 val) { struct arm_smccc_res res; + int force_prog = 0; if (bank != 0) { printf("Invalid bank argument, ONLY bank 0 is supported\n"); return -EINVAL; } - if (IS_ENABLED(CONFIG_IMX8QXP)) { + if (IS_ENABLED(CONFIG_IMX8QXP) || IS_ENABLED(CONFIG_IMX8DXL)) { if (word >= FSL_QXP_FUSE_GAP_START && word <= FSL_QXP_FUSE_GAP_END) { printf("Invalid word argument for this SoC\n"); @@ -69,16 +71,19 @@ int fuse_prog(u32 bank, u32 word, u32 val) } } - if ((word >= FSL_ECC_WORD_START_1 && word <= FSL_ECC_WORD_END_1) || - (word >= FSL_ECC_WORD_START_2 && word <= FSL_ECC_WORD_END_2)) { - puts("Warning: Words in this index range have ECC protection\n" - "and can only be programmed once per word. Individual bit\n" - "operations will be rejected after the first one.\n" - "\n\n Really program this word? \n"); - - if (!confirm_yesno()) { - puts("Word programming aborted\n"); - return -EPERM; + force_prog = env_get_yesno("force_prog_ecc"); + if (force_prog != 1) { + if ((word >= FSL_ECC_WORD_START_1 && word <= FSL_ECC_WORD_END_1) || + (word >= FSL_ECC_WORD_START_2 && word <= FSL_ECC_WORD_END_2)) { + puts("Warning: Words in this index range have ECC protection\n" + "and can only be programmed once per word. Individual bit\n" + "operations will be rejected after the first one.\n" + "\n\n Really program this word? \n"); + + if (!confirm_yesno()) { + puts("Word programming aborted\n"); + return -EPERM; + } } } diff --git a/drivers/misc/imx8/scu.c b/drivers/misc/imx8/scu.c index 035a600f71c..87ba90328e5 100644 --- a/drivers/misc/imx8/scu.c +++ b/drivers/misc/imx8/scu.c @@ -213,18 +213,6 @@ static int imx8_scu_remove(struct udevice *dev) static int imx8_scu_bind(struct udevice *dev) { - int ret; - struct udevice *child; - ofnode node; - - debug("%s(dev=%p)\n", __func__, dev); - ofnode_for_each_subnode(node, dev_ofnode(dev)) { - ret = lists_bind_fdt(dev, node, &child, true); - if (ret) - return ret; - debug("bind child dev %s\n", child->name); - } - return 0; } diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index 27ecce710fc..1e8b801b1d8 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -481,6 +481,24 @@ int sc_misc_get_temp(sc_ipc_t ipc, sc_rsrc_t resource, sc_misc_temp_t temp, return 0; } +void sc_misc_get_button_status(sc_ipc_t ipc, sc_bool_t *status) +{ + struct sc_rpc_msg_s msg; + struct udevice *dev = gd->arch.scu_dev; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_MISC); + RPC_FUNC(&msg) = (u8)(MISC_FUNC_GET_BUTTON_STATUS); + + misc_call(dev, SC_FALSE, &msg, 1U, &msg, 1U); + + if (status != NULL) + { + *status = (sc_bool_t)(!!(RPC_U8(&msg, 0U))); + } +} + /* RM */ sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr) { @@ -788,7 +806,7 @@ sc_bool_t sc_rm_is_pad_owned(sc_ipc_t ipc, sc_pad_t pad) RPC_VER(&msg) = SC_RPC_VERSION; RPC_SVC(&msg) = (u8)SC_RPC_SVC_RM; RPC_FUNC(&msg) = (u8)RM_FUNC_IS_PAD_OWNED; - RPC_U8(&msg, 0U) = (u8)pad; + RPC_U16(&msg, 0U) = (u16)pad; RPC_SIZE(&msg) = 2U; ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); @@ -851,6 +869,21 @@ int sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, sc_bool_t enable, return ret; } +void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_PM); + RPC_FUNC(&msg) = (u8)(PM_FUNC_REBOOT); + RPC_U8(&msg, 0U) = (u8)(type); + RPC_SIZE(&msg) = 2U; + + misc_call(dev, SC_TRUE, &msg, size, &msg, size); +} + int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_power_mode_t *mode) { @@ -877,6 +910,28 @@ int sc_pm_get_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, return ret; } +int sc_timer_set_wdog_window(sc_ipc_t ipc, sc_timer_wdog_time_t window) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 2U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_TIMER); + RPC_FUNC(&msg) = (u8)(TIMER_FUNC_SET_WDOG_WINDOW); + + RPC_U32(&msg, 0U) = (u32)(window); + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: window:%u: res:%d\n", + __func__, window, RPC_R8(&msg)); + + return ret; +} + int sc_seco_authenticate(sc_ipc_t ipc, sc_seco_auth_cmd_t cmd, sc_faddr_t addr) { @@ -974,6 +1029,31 @@ void sc_seco_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) *commit = RPC_U32(&msg, 4U); } +int sc_seco_v2x_build_info(sc_ipc_t ipc, u32 *version, u32 *commit) +{ + struct udevice *dev = gd->arch.scu_dev; + struct sc_rpc_msg_s msg; + int size = sizeof(struct sc_rpc_msg_s); + int ret; + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = (u8)(SC_RPC_SVC_SECO); + RPC_FUNC(&msg) = (u8)(SECO_FUNC_V2X_BUILD_INFO); + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret) + printf("%s: res:%d\n", __func__, RPC_R8(&msg)); + + if (version) + *version = RPC_U32(&msg, 0U); + + if (commit) + *commit = RPC_U32(&msg, 4U); + + return ret; +} + int sc_seco_get_event(sc_ipc_t ipc, u8 idx, u32 *event) { struct udevice *dev = gd->arch.scu_dev; @@ -1163,8 +1243,7 @@ int sc_seco_secvio_dgo_config(sc_ipc_t ipc, u8 id, u8 access, u32 *data) printf("%s, id:0x%x, access:%x, res:%d\n", __func__, id, access, RPC_R8(&msg)); - if (data) - *data = RPC_U32(&msg, 0U); + *data = RPC_U32(&msg, 0U); return ret; } diff --git a/drivers/misc/imx_m4_mu.c b/drivers/misc/imx_m4_mu.c new file mode 100644 index 00000000000..4168d8cdffb --- /dev/null +++ b/drivers/misc/imx_m4_mu.c @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct mu_type { + u32 tr[4]; + u32 rr[4]; + u32 sr; + u32 cr; +}; + +struct imx_m4_mu { + struct mu_type *base; +}; + +#define MU_CR_GIE_MASK 0xF0000000u +#define MU_CR_RIE_MASK 0xF000000u +#define MU_CR_GIR_MASK 0xF0000u +#define MU_CR_TIE_MASK 0xF00000u +#define MU_CR_F_MASK 0x7u +#define MU_SR_TE0_MASK BIT(23) +#define MU_SR_RF0_MASK BIT(27) +#define MU_TR_COUNT 4 +#define MU_RR_COUNT 4 + +static inline void mu_hal_init(struct mu_type *base) +{ + /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ + clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK | + MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK); +} + +static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg) +{ + u32 mask = MU_SR_TE0_MASK >> reg_index; + u32 val; + int ret; + + assert(reg_index < MU_TR_COUNT); + + debug("sendmsg sr 0x%x\n", readl(&base->sr)); + + /* Wait TX register to be empty. */ + ret = readl_poll_timeout(&base->sr, val, val & mask, 10000); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + debug("tr[%d] 0x%x\n",reg_index, msg); + + writel(msg, &base->tr[reg_index]); + + return 0; +} + +static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg) +{ + u32 mask = MU_SR_RF0_MASK >> reg_index; + u32 val; + int ret; + + assert(reg_index < MU_TR_COUNT); + + debug("receivemsg sr 0x%x\n", readl(&base->sr)); + + /* Wait RX register to be full. */ + ret = readl_poll_timeout(&base->sr, val, val & mask, 10000); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + *msg = readl(&base->rr[reg_index]); + + debug("rr[%d] 0x%x\n",reg_index, *msg); + + return 0; +} + +static int mu_hal_poll_receive(struct mu_type *base, ulong rx_timeout) +{ + u32 mask = MU_SR_RF0_MASK; + u32 val; + int ret; + + debug("receivemsg sr 0x%x\n", readl(&base->sr)); + + /* Wait RX register to be full. */ + ret = readl_poll_timeout(&base->sr, val, val & mask, rx_timeout); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + return 0; +} + +static int imx_m4_mu_read(struct mu_type *base, void *data) +{ + union imx_m4_msg *msg = (union imx_m4_msg *)data; + int ret; + u8 count = 0; + + if (!msg) + return -EINVAL; + + /* Read 4 words */ + while (count < 4) { + ret = mu_hal_receivemsg(base, count % MU_RR_COUNT, + &msg->data[count]); + if (ret) + return ret; + count++; + } + + return 0; +} + +static int imx_m4_mu_write(struct mu_type *base, void *data) +{ + union imx_m4_msg *msg = (union imx_m4_msg *)data; + int ret; + u8 count = 0; + + if (!msg) + return -EINVAL; + + /* Write 4 words */ + while (count < 4) { + ret = mu_hal_sendmsg(base, count % MU_TR_COUNT, + msg->data[count]); + if (ret) + return ret; + count++; + } + + return 0; +} + +/* + * Note the function prototype use msgid as the 2nd parameter, here + * we take it as no_resp. + */ +static int imx_m4_mu_call(struct udevice *dev, int resp_timeout, void *tx_msg, + int tx_size, void *rx_msg, int rx_size) +{ + struct imx_m4_mu *priv = dev_get_priv(dev); + int ret; + + if (resp_timeout < 0) + return -EINVAL; + + if (tx_msg) { + ret = imx_m4_mu_write(priv->base, tx_msg); + if (ret) + return ret; + } + + if (rx_msg) { + if (resp_timeout) { + ret = mu_hal_poll_receive(priv->base, resp_timeout); + if (ret) + return ret; + } + + ret = imx_m4_mu_read(priv->base, rx_msg); + if (ret) + return ret; + } + + return 0; +} + +static int imx_m4_mu_probe(struct udevice *dev) +{ + struct imx_m4_mu *priv = dev_get_priv(dev); + fdt_addr_t addr; + + debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (struct mu_type *)addr; + + debug("mu base 0x%lx\n", (ulong)priv->base); + + /* U-Boot not enable interrupts, so need to enable RX interrupts */ + mu_hal_init(priv->base); + + return 0; +} + +static int imx_m4_mu_remove(struct udevice *dev) +{ + return 0; +} + +static int imx_m4_mu_bind(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static struct misc_ops imx_m4_mu_ops = { + .call = imx_m4_mu_call, +}; + +static const struct udevice_id imx_m4_mu_ids[] = { + { .compatible = "fsl,imx-m4-mu" }, + { } +}; + +U_BOOT_DRIVER(imx_m4_mu) = { + .name = "imx_m4_mu", + .id = UCLASS_MISC, + .of_match = imx_m4_mu_ids, + .probe = imx_m4_mu_probe, + .bind = imx_m4_mu_bind, + .remove = imx_m4_mu_remove, + .ops = &imx_m4_mu_ops, + .priv_auto = sizeof(struct imx_m4_mu), +}; diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c index 926c62c8a14..b1893a5c7eb 100644 --- a/drivers/misc/mxc_ocotp.c +++ b/drivers/misc/mxc_ocotp.c @@ -335,7 +335,7 @@ int fuse_sense(u32 bank, u32 word, u32 *val) struct ocotp_regs *regs; int ret; - if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) { + if (is_imx8mq() && (soc_rev() >= CHIP_REV_2_1)) { printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__); return -EPERM; } diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index f8ca52efb6b..0d21716ae3c 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -105,6 +105,14 @@ config SUPPORT_EMMC_RPMB Enable support for reading, writing and programming the key for the Replay Protection Memory Block partition in eMMC. +config SPL_SUPPORT_EMMC_RPMB + bool "Support eMMC replay protected memory block (RPMB) in SPL" + default n + imply CMD_MMC_RPMB + help + Enable support for reading, writing and programming the + key for the Replay Protection Memory Block partition in eMMC. + config SUPPORT_EMMC_BOOT bool "Support some additional features of the eMMC boot partitions" help @@ -786,6 +794,13 @@ config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND This option assumes no hotplug, and u-boot has to make all the way to to linux to use 1.8v UHS-I speed mode if has card. +config FSL_ESDHC_VS33_NOT_SUPPORT + bool "3.3V power supply not supported" + depends on FSL_ESDHC + help + For eSDHC, power supply is through peripheral circuit. 3.3V support is + common. Select this if 3.3V power supply not supported. + config FSL_ESDHC_IMX bool "Freescale/NXP i.MX eSDHC controller support" help @@ -812,3 +827,9 @@ config SYS_FSL_ERRATUM_ESDHC135 config SYS_FSL_ERRATUM_ESDHC_A001 bool + +config SYS_FSL_ERRATUM_A011334 + bool + +config SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND + bool diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 6014e1c5cac..b3c71c86950 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP * Andy Fleming * * Based vaguely on the pxa mmc code: @@ -71,7 +71,8 @@ struct fsl_esdhc { uint sdtimingctl; /* SD timing control register */ char reserved8[20]; /* reserved */ uint dllcfg0; /* DLL config 0 register */ - char reserved9[12]; /* reserved */ + uint dllcfg1; /* DLL config 1 register */ + char reserved9[8]; /* reserved */ uint dllstat0; /* DLL status 0 register */ char reserved10[664];/* reserved */ uint esdhcctl; /* eSDHC control register */ @@ -518,6 +519,24 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) while (sdhc_clk / (div * pre_div) > clock && div < 16) div++; + if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) && + clock == 200000000 && mmc->selected_mode == MMC_HS_400) { + u32 div_ratio = pre_div * div; + + if (div_ratio <= 4) { + pre_div = 4; + div = 1; + } else if (div_ratio <= 8) { + pre_div = 4; + div = 2; + } else if (div_ratio <= 12) { + pre_div = 4; + div = 3; + } else { + printf("unsupported clock division.\n"); + } + } + mmc->clock = sdhc_clk / pre_div / div; priv->clock = mmc->clock; @@ -749,6 +768,9 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); + if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND)) + esdhc_clrbits32(®s->dllcfg1, DLL_PD_PULSE_STRETCH_SEL); + return 0; } @@ -773,10 +795,12 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv, u32 caps; caps = esdhc_read32(®s->hostcapblt); + + if (!IS_ENABLED(CONFIG_FSL_ESDHC_VS33_NOT_SUPPORT)) + caps |= HOSTCAPBLT_VS33; + if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_ESDHC135)) caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30); - if (IS_ENABLED(CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33)) - caps |= HOSTCAPBLT_VS33; if (caps & HOSTCAPBLT_VS18) cfg->voltages |= MMC_VDD_165_195; if (caps & HOSTCAPBLT_VS30) @@ -1063,9 +1087,14 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) struct fsl_esdhc_plat *plat = dev_get_plat(dev); struct fsl_esdhc_priv *priv = dev_get_priv(dev); struct fsl_esdhc *regs = priv->esdhc_regs; + struct mmc *mmc = &plat->mmc; u32 val, irqstaten; int i; + if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A011334) && + plat->mmc.hs400_tuning) + set_sysctl(priv, mmc, mmc->clock); + esdhc_tuning_block_enable(priv, true); esdhc_setbits32(®s->autoc12err, EXECUTE_TUNING); @@ -1073,7 +1102,7 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) esdhc_write32(®s->irqstaten, IRQSTATEN_BRR); for (i = 0; i < MAX_TUNING_LOOP; i++) { - mmc_send_tuning(&plat->mmc, opcode, NULL); + mmc_send_tuning(mmc, opcode, NULL); mdelay(1); val = esdhc_read32(®s->autoc12err); diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 6a9403dc004..58a4d925ecd 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -38,6 +38,9 @@ #include #include #include +#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE) +#include +#endif #if !CONFIG_IS_ENABLED(BLK) #include "mmc_private.h" @@ -146,6 +149,7 @@ struct esdhc_soc_data { * @start_tuning_tap: the start point for tuning in tuning_ctrl register * @strobe_dll_delay_target: settings in strobe_dllctrl * @signal_voltage: indicating the current voltage + * @signal_voltage_switch_extra_delay_ms: extra delay for IO voltage switch * @cd_gpio: gpio for card detection * @wp_gpio: gpio for write protection */ @@ -153,6 +157,8 @@ struct fsl_esdhc_priv { struct fsl_esdhc *esdhc_regs; unsigned int sdhc_clk; struct clk per_clk; + struct clk ipg_clk; + struct clk ahb_clk; unsigned int clock; unsigned int mode; unsigned int bus_width; @@ -170,6 +176,7 @@ struct fsl_esdhc_priv { u32 tuning_start_tap; u32 strobe_dll_delay_target; u32 signal_voltage; + u32 signal_voltage_switch_extra_delay_ms; #if CONFIG_IS_ENABLED(DM_REGULATOR) struct udevice *vqmmc_dev; struct udevice *vmmc_dev; @@ -521,15 +528,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, goto out; } - /* Switch voltage to 1.8V if CMD11 succeeded */ - if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) { - esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); - - printf("Run CMD11 1.8V switch\n"); - /* Sleep for 5 ms - max time for card to switch to 1.8V */ - udelay(5000); - } - /* Workaround for ESDHC errata ENGcm03648 */ if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { int timeout = 50000; @@ -660,7 +658,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) clk = (pre_div << 8) | (div << 4); #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); #else esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); #endif @@ -672,7 +673,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n"); #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #else esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif @@ -727,8 +728,14 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); struct fsl_esdhc *regs = priv->esdhc_regs; u32 val; + u32 tmp; + int ret; if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); esdhc_write32(®s->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); /* @@ -746,6 +753,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc) pr_warn("HS400 strobe DLL status REF not lock!\n"); if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) pr_warn("HS400 strobe DLL status SLV not lock!\n"); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); } } @@ -835,6 +843,14 @@ static int esdhc_set_voltage(struct mmc *mmc) } #endif esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); + /* + * some board like imx8mm-evk need about 18ms to switch + * the IO voltage from 3.3v to 1.8v, common code only + * delay 10ms, so need to delay extra time to make sure + * the IO voltage change to 1.8v. + */ + if (priv->signal_voltage_switch_extra_delay_ms) + mdelay(priv->signal_voltage_switch_extra_delay_ms); if (esdhc_read32(®s->vendorspec) & ESDHC_VENDORSPEC_VSELECT) return 0; @@ -966,22 +982,26 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) if (priv->clock != clock) set_sysctl(priv, mmc, clock); -#ifdef MMC_SUPPORTS_TUNING if (mmc->clk_disable) { #ifdef CONFIG_FSL_USDHC - esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN); + u32 tmp; + + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); + ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); + if (ret) + pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n"); #else esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); #endif } else { #ifdef CONFIG_FSL_USDHC - esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | - VENDORSPEC_CKEN); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #else esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); #endif } +#ifdef MMC_SUPPORTS_TUNING /* * For HS400/HS400ES mode, make sure set the strobe dll in the * target clock rate. So call esdhc_set_strobe_dll() after the @@ -1052,7 +1072,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) #ifndef CONFIG_FSL_USDHC esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); #else - esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #endif /* Set the initial clock speed */ @@ -1190,8 +1210,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv, esdhc_write32(®s->autoc12err, 0); esdhc_write32(®s->clktunectrlstatus, 0); #else - esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | - VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN); + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); #endif if (priv->vs18_enable) @@ -1333,6 +1352,13 @@ int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg) if (!cfg) return -EINVAL; +#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE) + if (esdhc_fused(cfg->esdhc_base)) { + printf("ESDHC@0x%lx is fused, disable it\n", cfg->esdhc_base); + return -ENODEV; + } +#endif + priv = calloc(sizeof(struct fsl_esdhc_priv), 1); if (!priv) return -ENOMEM; @@ -1426,6 +1452,14 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; + +#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE) + if (esdhc_fused(addr)) { + printf("ESDHC@0x%lx is fused, disable it\n", addr); + return -ENODEV; + } +#endif + priv->esdhc_regs = (struct fsl_esdhc *)addr; priv->dev = dev; priv->mode = -1; @@ -1446,6 +1480,8 @@ static int fsl_esdhc_of_to_plat(struct udevice *dev) val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target", ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT); priv->strobe_dll_delay_target = val; + val = fdtdec_get_int(fdt, node, "fsl,signal-voltage-switch-extra-delay-ms", 0); + priv->signal_voltage_switch_extra_delay_ms = val; if (dev_read_bool(dev, "broken-cd")) priv->broken_cd = 1; @@ -1567,10 +1603,26 @@ static int fsl_esdhc_probe(struct udevice *dev) * work as expected. */ - init_clk_usdhc(dev_seq(dev)); - #if CONFIG_IS_ENABLED(CLK) /* Assigned clock already set clock */ + ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); + if (!ret) { + ret = clk_enable(&priv->ipg_clk); + if (ret) { + printf("Failed to enable ipg_clk\n"); + return ret; + } + } + + ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk); + if (!ret) { + ret = clk_enable(&priv->ahb_clk); + if (ret) { + printf("Failed to enable ahb_clk\n"); + return ret; + } + } + ret = clk_get_by_name(dev, "per", &priv->per_clk); if (ret) { printf("Failed to get per_clk\n"); @@ -1584,6 +1636,8 @@ static int fsl_esdhc_probe(struct udevice *dev) priv->sdhc_clk = clk_get_rate(&priv->per_clk); #else + init_clk_usdhc(dev_seq(dev)); + priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev_seq(dev)); if (priv->sdhc_clk <= 0) { dev_err(dev, "Unable to get clk for %s\n", dev->name); diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index b4c8e7f293b..785ebc0cd31 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -823,7 +823,7 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value, * capable of polling by using mmc_wait_dat0, then rely on waiting the * stated timeout to be sufficient. */ - if (ret == -ENOSYS && !send_status) { + if (ret == -ENOSYS || !send_status) { mdelay(timeout_ms); return 0; } @@ -2092,14 +2092,16 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps) } #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \ - CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) + CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \ + CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT) /* * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode * before doing anything else, since a transition from either of * the HS200/HS400 mode directly to legacy mode is not supported. */ if (mmc->selected_mode == MMC_HS_200 || - mmc->selected_mode == MMC_HS_400) + mmc->selected_mode == MMC_HS_400 || + mmc->selected_mode == MMC_HS_400_ES) mmc_set_card_speed(mmc, MMC_HS, true); else #endif @@ -2951,7 +2953,7 @@ int mmc_deinit(struct mmc *mmc) return sd_select_mode_and_width(mmc, caps_filtered); } else { caps_filtered = mmc->card_caps & - ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400)); + ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_400_ES)); return mmc_select_mode_and_width(mmc, caps_filtered); } diff --git a/drivers/mmc/rpmb.c b/drivers/mmc/rpmb.c index ea7e506666b..0aafc7e95b7 100644 --- a/drivers/mmc/rpmb.c +++ b/drivers/mmc/rpmb.c @@ -41,12 +41,6 @@ #define RPMB_ERR_CNT_EXPIRED 0x80 #define RPMB_ERR_MSK 0x7 -/* Sizes of RPMB data frame */ -#define RPMB_SZ_STUFF 196 -#define RPMB_SZ_MAC 32 -#define RPMB_SZ_DATA 256 -#define RPMB_SZ_NONCE 16 - #define SHA256_BLOCK_SIZE 64 /* Error messages */ @@ -61,20 +55,6 @@ static const char * const rpmb_err_msg[] = { "Authentication key not yet programmed", }; - -/* Structure of RPMB data frame. */ -struct s_rpmb { - unsigned char stuff[RPMB_SZ_STUFF]; - unsigned char mac[RPMB_SZ_MAC]; - unsigned char data[RPMB_SZ_DATA]; - unsigned char nonce[RPMB_SZ_NONCE]; - unsigned int write_counter; - unsigned short address; - unsigned short block_count; - unsigned short result; - unsigned short request; -}; - static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount, bool is_rel_write) { @@ -88,7 +68,7 @@ static int mmc_set_blockcount(struct mmc *mmc, unsigned int blockcount, return mmc_send_cmd(mmc, &cmd, NULL); } -static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, +int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, unsigned int count, bool is_rel_write) { struct mmc_cmd cmd = {0}; @@ -112,7 +92,7 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, cmd.resp_type = MMC_RSP_R1; data.src = (const char *)s; - data.blocks = 1; + data.blocks = count; data.blocksize = MMC_MAX_BLOCK_LEN; data.flags = MMC_DATA_WRITE; @@ -125,14 +105,14 @@ static int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, } return 0; } -static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, - unsigned short expected) +int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, + unsigned int count, unsigned short expected) { struct mmc_cmd cmd = {0}; struct mmc_data data; int ret; - ret = mmc_set_blockcount(mmc, 1, false); + ret = mmc_set_blockcount(mmc, count, false); if (ret) { #ifdef CONFIG_MMC_RPMB_TRACE printf("%s:mmc_set_blockcount-> %d\n", __func__, ret); @@ -144,7 +124,7 @@ static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, cmd.resp_type = MMC_RSP_R1; data.dest = (char *)s; - data.blocks = 1; + data.blocks = count; data.blocksize = MMC_MAX_BLOCK_LEN; data.flags = MMC_DATA_READ; @@ -156,7 +136,7 @@ static int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, return -1; } /* Check the response and the status */ - if (be16_to_cpu(s->request) != expected) { + if (expected && be16_to_cpu(s->request) != expected) { #ifdef CONFIG_MMC_RPMB_TRACE printf("%s:response= %x\n", __func__, be16_to_cpu(s->request)); @@ -183,7 +163,7 @@ static int mmc_rpmb_status(struct mmc *mmc, unsigned short expected) return -1; /* Read the result */ - return mmc_rpmb_response(mmc, rpmb_frame, expected); + return mmc_rpmb_response(mmc, rpmb_frame, 1, expected); } static void rpmb_hmac(unsigned char *key, unsigned char *buff, int len, unsigned char *output) @@ -241,7 +221,7 @@ int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *pcounter) return -1; /* Read the result */ - ret = mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_WCOUNTER); + ret = mmc_rpmb_response(mmc, rpmb_frame, 1, RPMB_RESP_WCOUNTER); if (ret) return ret; @@ -277,7 +257,7 @@ int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, break; /* Read the result */ - if (mmc_rpmb_response(mmc, rpmb_frame, RPMB_RESP_READ_DATA)) + if (mmc_rpmb_response(mmc, rpmb_frame, 1, RPMB_RESP_READ_DATA)) break; /* Check the HMAC if key is provided */ diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c index e6bbfac4d68..603a84395f0 100644 --- a/drivers/mtd/nand/raw/mxs_nand.c +++ b/drivers/mtd/nand/raw/mxs_nand.c @@ -1254,6 +1254,13 @@ static int mxs_nand_init_dma(struct mxs_nand_info *info) { int i = 0, j, ret = 0; + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_GPMI)) { + printf("NAND GPMI@0x%lx is fused, disable it\n", (ulong)info->gpmi_regs); + return -EPERM; + } + } + info->desc = malloc(sizeof(struct mxs_dma_desc *) * MXS_NAND_DMA_DESCRIPTOR_COUNT); if (!info->desc) { diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 46dc29df369..aa6780d9006 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -291,3 +291,8 @@ void nand_deselect(void) { } +u32 nand_spl_adjust_offset(u32 sector, u32 offs) +{ + /* Handle the offset adjust in nand_spl_load_image,*/ + return offs; +} diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c index b59edd152cc..34e2aa63fbd 100644 --- a/drivers/mtd/spi/sf_dataflash.c +++ b/drivers/mtd/spi/sf_dataflash.c @@ -136,11 +136,11 @@ static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len) memset(dataflash->command, 0 , sizeof(dataflash->command)); command = dataflash->command; - debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len); + debug("%s: erase addr=0x%x len 0x%lx\n", dev->name, offset, len); div_u64_rem(len, spi_flash->page_size, &rem); if (rem) { - printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n", + printf("%s: len(0x%lx) isn't the multiple of page size(0x%x)\n", dev->name, len, spi_flash->page_size); return -EINVAL; } @@ -227,7 +227,7 @@ static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len, memset(dataflash->command, 0 , sizeof(dataflash->command)); command = dataflash->command; - debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len); + debug("%s: erase addr=0x%x len 0x%lx\n", dev->name, offset, len); debug("READ: (%x) %x %x %x\n", command[0], command[1], command[2], command[3]); @@ -285,7 +285,7 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len, memset(dataflash->command, 0 , sizeof(dataflash->command)); command = dataflash->command; - debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len)); + debug("%s: write 0x%x..0x%lx\n", dev->name, offset, (offset + len)); pageaddr = ((unsigned)offset / spi_flash->page_size); to = ((unsigned)offset % spi_flash->page_size); diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 2b57797954c..a004cc4b62a 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -97,6 +97,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lq16", 0xc86015, 0, 64 * 1024, 32, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("gd25lq32", 0xc86016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | @@ -328,6 +333,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + + { INFO("w25q128dw", 0x1f4218, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 0e84c22b507..f96ee642494 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -78,6 +78,15 @@ config DM_ETH_PHY help Enable driver model for Ethernet Generic PHY . +config DSA_SANDBOX + depends on DM_DSA && SANDBOX + default y + bool "Sandbox: Mocked DSA driver" + help + This driver implements a dummy DSA switch connected to a dummy sandbox + Ethernet device used as DSA master, to test DSA class code, including + exported DSA API and datapath processing of Ethernet traffic. + menuconfig NETDEVICES bool "Network device support" depends on NET diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a19511aaa7b..108138fdb97 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DNET) += dnet.o +obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o diff --git a/drivers/net/dsa_sandbox.c b/drivers/net/dsa_sandbox.c new file mode 100644 index 00000000000..4b62670e5d1 --- /dev/null +++ b/drivers/net/dsa_sandbox.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP Semiconductors + */ + +#include +#include +#include + +#define DSA_SANDBOX_MAGIC 0x00415344 +#define DSA_SANDBOX_TAG_LEN sizeof(struct dsa_sandbox_tag) + +struct dsa_sandbox_priv { + struct eth_sandbox_priv *master_priv; + int port_en_mask; +}; + +struct dsa_sandbox_tag { + u32 magic; + u32 port; +}; + +static bool sb_dsa_port_enabled(struct udevice *dev, int port) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + + return priv->port_en_mask & BIT(port); +} + +static bool sb_dsa_master_enabled(struct udevice *dev) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + + return !priv->master_priv->disabled; +} + +static int dsa_sandbox_port_enable(struct udevice *dev, int port, + struct phy_device *phy) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + + if (!sb_dsa_master_enabled(dev)) + return -EFAULT; + + priv->port_en_mask |= BIT(port); + + return 0; +} + +static void dsa_sandbox_port_disable(struct udevice *dev, int port, + struct phy_device *phy) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + + priv->port_en_mask &= ~BIT(port); +} + +static int dsa_sandbox_xmit(struct udevice *dev, int port, void *packet, + int length) +{ + struct dsa_sandbox_tag *tag = packet; + + if (!sb_dsa_master_enabled(dev)) + return -EFAULT; + + if (!sb_dsa_port_enabled(dev, port)) + return -EFAULT; + + tag->magic = DSA_SANDBOX_MAGIC; + tag->port = port; + + return 0; +} + +static int dsa_sandbox_rcv(struct udevice *dev, int *port, void *packet, + int length) +{ + struct dsa_sandbox_tag *tag = packet; + + if (!sb_dsa_master_enabled(dev)) + return -EFAULT; + + if (tag->magic != DSA_SANDBOX_MAGIC) + return -EFAULT; + + *port = tag->port; + if (!sb_dsa_port_enabled(dev, tag->port)) + return -EFAULT; + + return 0; +} + +static const struct dsa_ops dsa_sandbox_ops = { + .port_enable = dsa_sandbox_port_enable, + .port_disable = dsa_sandbox_port_disable, + .xmit = dsa_sandbox_xmit, + .rcv = dsa_sandbox_rcv, +}; + +static int sb_dsa_handler(struct udevice *dev, void *packet, + unsigned int len) +{ + struct eth_sandbox_priv *master_priv; + struct dsa_sandbox_tag *tag = packet; + struct udevice *dsa_dev; + u32 port_index; + void *rx_buf; + int i; + + /* this emulates the switch hw and the network side */ + if (tag->magic != DSA_SANDBOX_MAGIC) + return -EFAULT; + + port_index = tag->port; + master_priv = dev_get_priv(dev); + dsa_dev = master_priv->priv; + if (!sb_dsa_port_enabled(dsa_dev, port_index)) + return -EFAULT; + + packet += DSA_SANDBOX_TAG_LEN; + len -= DSA_SANDBOX_TAG_LEN; + + if (!sandbox_eth_arp_req_to_reply(dev, packet, len)) + goto dsa_tagging; + if (!sandbox_eth_ping_req_to_reply(dev, packet, len)) + goto dsa_tagging; + + return 0; + +dsa_tagging: + master_priv->recv_packets--; + i = master_priv->recv_packets; + rx_buf = master_priv->recv_packet_buffer[i]; + len = master_priv->recv_packet_length[i]; + memmove(rx_buf + DSA_SANDBOX_TAG_LEN, rx_buf, len); + + tag = rx_buf; + tag->magic = DSA_SANDBOX_MAGIC; + tag->port = port_index; + len += DSA_SANDBOX_TAG_LEN; + master_priv->recv_packet_length[i] = len; + master_priv->recv_packets++; + + return 0; +} + +static int dsa_sandbox_probe(struct udevice *dev) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + struct udevice *master = dsa_get_master(dev); + struct eth_sandbox_priv *master_priv; + + if (!master) + return -ENODEV; + + dsa_set_tagging(dev, DSA_SANDBOX_TAG_LEN, 0); + + master_priv = dev_get_priv(master); + master_priv->priv = dev; + master_priv->tx_handler = sb_dsa_handler; + + priv->master_priv = master_priv; + + return 0; +} + +static const struct udevice_id dsa_sandbox_ids[] = { + { .compatible = "sandbox,dsa" }, + { } +}; + +U_BOOT_DRIVER(dsa_sandbox) = { + .name = "dsa_sandbox", + .id = UCLASS_DSA, + .of_match = dsa_sandbox_ids, + .probe = dsa_sandbox_probe, + .ops = &dsa_sandbox_ops, + .priv_auto = sizeof(struct dsa_sandbox_priv), +}; diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c index e8242ca4e1b..1fd4e7a28f7 100644 --- a/drivers/net/dwc_eth_qos.c +++ b/drivers/net/dwc_eth_qos.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2016, NVIDIA CORPORATION. + * Copyright 2020 NXP * * Portions based on U-Boot's rtl8169.c. */ @@ -45,7 +46,7 @@ #include #include #include -#ifdef CONFIG_ARCH_IMX8M +#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8DXL) #include #include #endif @@ -303,6 +304,8 @@ struct eqos_priv { struct eqos_tegra186_regs *tegra186_regs; struct reset_ctl reset_ctl; struct gpio_desc phy_reset_gpio; + uint32_t reset_delay; + uint32_t reset_post_delay; struct clk clk_master_bus; struct clk clk_rx; struct clk clk_ptp_ref; @@ -311,6 +314,7 @@ struct eqos_priv { struct clk clk_slave_bus; struct mii_dev *mii; struct phy_device *phy; + ofnode phy_of_node; int phyaddr; u32 max_speed; void *descs; @@ -618,7 +622,43 @@ static int eqos_start_clks_stm32(struct udevice *dev) static int eqos_start_clks_imx(struct udevice *dev) { +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) + struct eqos_priv *eqos = dev_get_priv(dev); + int ret; + + debug("%s(dev=%p):\n", __func__, dev); + + ret = clk_enable(&eqos->clk_slave_bus); + if (ret < 0) { + pr_err("clk_enable(clk_slave_bus) failed: %d", ret); + goto err; + } + + ret = clk_enable(&eqos->clk_master_bus); + if (ret < 0) { + pr_err("clk_enable(clk_master_bus) failed: %d", ret); + goto err_disable_clk_slave_bus; + } + + ret = clk_enable(&eqos->clk_tx); + if (ret < 0) { + pr_err("clk_enable(clk_tx) failed: %d", ret); + goto err_disable_clk_master_bus; + } +#endif + + debug("%s: OK\n", __func__); return 0; + +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) +err_disable_clk_master_bus: + clk_disable(&eqos->clk_master_bus); +err_disable_clk_slave_bus: + clk_disable(&eqos->clk_slave_bus); +err: + debug("%s: FAILED: %d\n", __func__, ret); + return ret; +#endif } static void eqos_stop_clks_tegra186(struct udevice *dev) @@ -657,7 +697,17 @@ static void eqos_stop_clks_stm32(struct udevice *dev) static void eqos_stop_clks_imx(struct udevice *dev) { - /* empty */ +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + clk_disable(&eqos->clk_tx); + clk_disable(&eqos->clk_slave_bus); + clk_disable(&eqos->clk_master_bus); +#endif + + debug("%s: OK\n", __func__); } static int eqos_start_resets_tegra186(struct udevice *dev) @@ -849,7 +899,12 @@ __weak int imx_eqos_txclk_set_rate(unsigned long rate) static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev) { +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) + struct eqos_priv *eqos = dev_get_priv(dev); + return clk_get_rate(&eqos->clk_slave_bus); +#else return imx_get_eqos_csr_clk(); +#endif } static int eqos_calibrate_pads_stm32(struct udevice *dev) @@ -977,7 +1032,7 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); ulong rate; - int ret; + int ret = 0; debug("%s(dev=%p):\n", __func__, dev); @@ -996,7 +1051,12 @@ static int eqos_set_tx_clk_speed_imx(struct udevice *dev) return -EINVAL; } +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) + if (!is_imx8dxl()) + ret = clk_set_rate(&eqos->clk_tx, rate); +#else ret = imx_eqos_txclk_set_rate(rate); +#endif if (ret < 0) { pr_err("imx (tx_clk, %lu) failed: %d", rate, ret); return ret; @@ -1116,12 +1176,30 @@ static int eqos_read_rom_hwaddr(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); -#ifdef CONFIG_ARCH_IMX8M +#if defined(CONFIG_IMX8MP) || defined(CONFIG_IMX8DXL) imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr); #endif return !is_valid_ethaddr(pdata->enetaddr); } +static int eqos_get_phy_addr(struct eqos_priv *priv, struct udevice *dev) +{ + struct ofnode_phandle_args phandle_args; + int reg; + + if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, + &phandle_args)) { + debug("Failed to find phy-handle"); + return -ENODEV; + } + + priv->phy_of_node = phandle_args.node; + + reg = ofnode_read_u32_default(phandle_args.node, "reg", 0); + + return reg; +} + static int eqos_start(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); @@ -1176,9 +1254,7 @@ static int eqos_start(struct udevice *dev) */ if (!eqos->phy) { int addr = -1; -#ifdef CONFIG_DM_ETH_PHY - addr = eth_phy_get_addr(dev); -#endif + addr = eqos_get_phy_addr(eqos, dev); #ifdef DWC_NET_PHYADDR addr = DWC_NET_PHYADDR; #endif @@ -1197,6 +1273,7 @@ static int eqos_start(struct udevice *dev) } } + eqos->phy->node = eqos->phy_of_node; ret = phy_config(eqos->phy); if (ret < 0) { pr_err("phy_config() failed: %d", ret); @@ -1880,6 +1957,7 @@ static int eqos_probe_resources_imx(struct udevice *dev) { struct eqos_priv *eqos = dev_get_priv(dev); phy_interface_t interface; + int ret = 0; debug("%s(dev=%p):\n", __func__, dev); @@ -1890,8 +1968,78 @@ static int eqos_probe_resources_imx(struct udevice *dev) return -EINVAL; } + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &eqos->phy_reset_gpio, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + if (ret) { + pr_debug("gpio_request_by_name(phy reset) failed: %d", ret); + } + + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + eqos->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1); + if (eqos->reset_delay > 1000) { + pr_err("phy reset duration should be <= 1000ms\n"); + /* property value wrong, use default value */ + eqos->reset_delay = 1; + } + + mdelay(eqos->reset_delay); + + eqos->reset_post_delay = dev_read_u32_default(dev, + "phy-reset-post-delay", + 0); + if (eqos->reset_post_delay > 1000) { + pr_err("phy reset post delay should be <= 1000ms\n"); + /* property value wrong, use default value */ + eqos->reset_post_delay = 0; + } + + ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + if (ret < 0) { + pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret); + goto err_free_gpio_phy_reset; + } + + if (eqos->reset_post_delay) + mdelay(eqos->reset_post_delay); + } + +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) + ret = clk_get_by_name(dev, "aclk", &eqos->clk_master_bus); + if (ret) { + pr_err("clk_get_by_name(csr) failed: %d", ret); + goto err_free_gpio_phy_reset; + } + + ret = clk_get_by_name(dev, "csr", &eqos->clk_slave_bus); + if (ret) { + pr_err("clk_get_by_name(aclk) failed: %d", ret); + goto err_free_clk_master_bus; + } + + ret = clk_get_by_name(dev, "tx_clk", &eqos->clk_tx); + if (ret) { + pr_err("clk_get_by_name(tx) failed: %d", ret); + goto err_free_clk_slave_bus; + } +#endif + debug("%s: OK\n", __func__); return 0; + +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) +err_free_clk_slave_bus: + clk_free(&eqos->clk_slave_bus); +err_free_clk_master_bus: + clk_free(&eqos->clk_master_bus); +#endif +err_free_gpio_phy_reset: + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + dm_gpio_free(dev, &eqos->phy_reset_gpio); + } + + debug("%s: returns %d\n", __func__, ret); + return ret; } static phy_interface_t eqos_get_interface_imx(struct udevice *dev) @@ -1951,6 +2099,19 @@ static int eqos_remove_resources_stm32(struct udevice *dev) static int eqos_remove_resources_imx(struct udevice *dev) { + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) + clk_free(&eqos->clk_tx); + clk_free(&eqos->clk_slave_bus); + clk_free(&eqos->clk_master_bus); +#endif + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + dm_gpio_free(dev, &eqos->phy_reset_gpio); + } + + debug("%s: OK\n", __func__); return 0; } diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 694114eca79..1f0d5594152 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -4738,12 +4738,16 @@ e1000_phy_init_script(struct e1000_hw *hw) uint16_t fused, fine, coarse; /* Move to analog registers page */ - e1000_read_phy_reg(hw, - IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused); + if (e1000_read_phy_reg(hw, + IGP01E1000_ANALOG_SPARE_FUSE_STATUS, + &fused)) + return; if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { - e1000_read_phy_reg(hw, - IGP01E1000_ANALOG_FUSE_STATUS, &fused); + if (e1000_read_phy_reg(hw, + IGP01E1000_ANALOG_FUSE_STATUS, + &fused)) + return; fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; coarse = fused diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index ec21157d710..ef5b3a3db57 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -6,7 +6,6 @@ * (C) Copyright 2007 Pengutronix, Sascha Hauer * (C) Copyright 2007 Pengutronix, Juergen Beisert */ - #include #include #include @@ -146,7 +145,7 @@ static int fec_get_clk_rate(void *udev, int idx) CONFIG_IS_ENABLED(CLK_CCF)) { dev = udev; if (!dev) { - ret = uclass_get_device(UCLASS_ETH, idx, &dev); + ret = uclass_get_device_by_seq(UCLASS_ETH, idx, &dev); if (ret < 0) { debug("Can't get FEC udev: %d\n", ret); return ret; @@ -163,7 +162,7 @@ static int fec_get_clk_rate(void *udev, int idx) } } -static void fec_mii_setspeed(struct ethernet_regs *eth) +static void fec_mii_setspeed(struct ethernet_regs *eth, int idx) { /* * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock @@ -185,7 +184,7 @@ static void fec_mii_setspeed(struct ethernet_regs *eth) u32 hold; int ret; - ret = fec_get_clk_rate(NULL, 0); + ret = fec_get_clk_rate(NULL, idx); if (ret < 0) { printf("Can't find FEC0 clk rate: %d\n", ret); return; @@ -617,7 +616,7 @@ static int fec_init(struct eth_device *dev, struct bd_info *bd) fec_reg_setup(fec); if (fec->xcv_type != SEVENWIRE) - fec_mii_setspeed(fec->bus->priv); + fec_mii_setspeed(fec->bus->priv, fec->dev_id); /* Set Opcode/Pause Duration Register */ writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ @@ -1097,10 +1096,14 @@ struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id) free(bus); return NULL; } - fec_mii_setspeed(eth); + fec_mii_setspeed(eth, dev_id); return bus; } +__weak void init_clk_fec(int index) +{ +} + #ifndef CONFIG_DM_ETH #ifdef CONFIG_PHYLIB int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr, @@ -1166,7 +1169,7 @@ static int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr, fec_set_dev_name(edev->name, dev_id); fec->dev_id = (dev_id == -1) ? 0 : dev_id; fec->bus = bus; - fec_mii_setspeed(bus->priv); + fec_mii_setspeed(bus->priv, fec->dev_id); #ifdef CONFIG_PHYLIB fec->phydev = phydev; phy_connect_dev(phydev, edev); @@ -1226,6 +1229,7 @@ int fecmxc_initialize_multi(struct bd_info *bd, int dev_id, int phy_id, #else base_mii = addr; #endif + init_clk_fec(dev_id); debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); bus = fec_get_miibus(base_mii, dev_id); if (!bus) @@ -1366,6 +1370,7 @@ static int fecmxc_probe(struct udevice *dev) } if (IS_ENABLED(CONFIG_IMX8)) { + struct clk clk_2x_txclk; ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); if (ret < 0) { debug("Can't get FEC ipg clk: %d\n", ret); @@ -1377,6 +1382,35 @@ static int fecmxc_probe(struct udevice *dev) return ret; } + ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk); + if (ret < 0) { + debug("Can't get FEC ahb clk: %d\n", ret); + return ret; + } + ret = clk_enable(&priv->ahb_clk); + if (ret < 0) { + debug("Can't enable FEC ahb clk: %d\n", ret); + return ret; + } + + ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref); + if (ret >= 0) { + ret = clk_enable(&priv->clk_ref); + if (ret < 0) { + debug("Can't enable FEC ref clk: %d\n", ret); + return ret; + } + } + + ret = clk_get_by_name(dev, "enet_2x_txclk", &clk_2x_txclk); + if (ret >= 0) { + ret = clk_enable(&clk_2x_txclk); + if (ret < 0) { + debug("Can't enable FEC 2x_tx clk: %d\n", ret); + return ret; + } + } + priv->clk_rate = clk_get_rate(&priv->ipg_clk); } else if (CONFIG_IS_ENABLED(CLK_CCF)) { ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk); @@ -1588,6 +1622,7 @@ static const struct udevice_id fecmxc_ids[] = { { .compatible = "fsl,imx53-fec" }, { .compatible = "fsl,imx7d-fec" }, { .compatible = "fsl,mvf600-fec" }, + { .compatible = "fsl,imx8qm-fec" }, { } }; diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 0e89e663f71..7c23ccc1f0e 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -288,8 +288,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth) /* alloc Rx buffer from main memory */ rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE); - if (!rx_buf_pool) + if (!rx_buf_pool) { + free(rx_bd_ring_base); return -ENOMEM; + } memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE); debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool); diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index eee70a2e73a..ac86e33c550 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2015-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017,2021 NXP */ /* @@ -262,7 +262,8 @@ int pfe_firmware_init(void) uintptr_t pfe_img_addr = 0; #endif int ret = 0; - int fw_count; + int fw_count, max_fw_count; + const char *p; ret = pfe_spi_flash_init(); if (ret) @@ -293,6 +294,61 @@ int pfe_firmware_init(void) } #endif + p = env_get("load_util"); + if (!p) { + max_fw_count = 2; + } else { + max_fw_count = simple_strtoul(p, NULL, 10); + if (max_fw_count) + max_fw_count = 3; + else + max_fw_count = 2; + } + + for (fw_count = 0; fw_count < max_fw_count; fw_count++) { + switch (fw_count) { + case 0: + pfe_firmware_name = "class_slowpath"; + break; + case 1: + pfe_firmware_name = "tmu_slowpath"; + break; + case 2: + pfe_firmware_name = "util_slowpath"; + break; + } + + if (pfe_get_fw(&raw_image_addr, &raw_image_size, + pfe_firmware_name)) { + printf("%s firmware couldn't be found in FIT image\n", + pfe_firmware_name); + break; + } + pfe_firmware = malloc(raw_image_size); + if (!pfe_firmware) + return -ENOMEM; + memcpy((void *)pfe_firmware, (void *)raw_image_addr, + raw_image_size); + + switch (fw_count) { + case 0: + env_set_addr("class_elf_firmware", pfe_firmware); + env_set_addr("class_elf_size", (void *)raw_image_size); + break; + case 1: + env_set_addr("tmu_elf_firmware", pfe_firmware); + env_set_addr("tmu_elf_size", (void *)raw_image_size); + break; + case 2: + env_set_addr("util_elf_firmware", pfe_firmware); + env_set_addr("util_elf_size", (void *)raw_image_size); + break; + } + } + + raw_image_addr = NULL; + pfe_firmware = NULL; + raw_image_size = 0; for (fw_count = 0; fw_count < 2; fw_count++) { if (fw_count == 0) pfe_firmware_name = "class"; diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index d69503067d8..2d53cd5d569 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -144,6 +144,69 @@ config PHY_DAVICOM config PHY_ET1011C bool "LSI TruePHY ET1011C support" +config PHY_INPHI + bool "Inphi IN112525 gen1/gen2 retimers support" + help + This enables the IN112525 Retimer support + Supported speeds: + gen1(S03): 10G/25G + gen2(S05): 10G/25G & 40G/50G/100G using multiple chips + Phy initialization sequence differs depending on target + configurations: 10G or 25G. Higher speeds refer to use-cases + where multiple retimers are used on multiple data-paths and + speed adds up (e.g. 100G = 4x25G lanes -> 2 retimers). + The driver also uses a microcode firmware in the form of + address-data tuples for phy initialization +choice + prompt "Speed selection for INPHI in112525 s03 retimer" + default IN112525_S03_25G + help + Configure the speed settings for the Inphi S03 retimer + Default speed is 25G, but 10G speed can be set using + a half-rate configuration + +config IN112525_S03_10G + bool "10G" + help + 10G settings (half-rate) for Inphi in112525 gen1 retimer +config IN112525_S03_25G + bool "25G" + help + 25G settings for Inphi in112525 gen1 retimer +endchoice + +choice + prompt "Speed selection for INPHI in112525 s05 retimer" + default IN112525_S05_100G + help + This configures the IN112525_S05 driver for different speeds. + For 40G and 100G speeds two Inphi retimers must be used. Each + chip has two data paths and each path can support 10G or 25G. + +config IN112525_S05_10G + bool "10G" + help + 10G settings for Inphi in112525 gen2 retimer +config IN112525_S05_25G + bool "25G" + help + 25G settings for Inphi in112525 gen2 retimer + Two lanes are shutdown for individual port operation +config IN112525_S05_40G + bool "40G" + help + 40G settings for Inphi in112525 gen2 retimer +config IN112525_S05_50G + bool "50G" + help + 50G settings for Inphi in112525 gen2 retimer + +config IN112525_S05_100G + bool "100G" + help + 100G best settings for Inphi in112525 gen2 retimer +endchoice + config PHY_LXT bool "LXT971 Ethernet PHY support" @@ -292,6 +355,7 @@ config PHY_XILINX config PHY_XILINX_GMII2RGMII bool "Xilinx GMII to RGMII Ethernet PHYs support" + depends on DM_ETH help This adds support for Xilinx GMII to RGMII IP core. This IP acts as bridge between MAC connected over GMII and external phy that diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index e967f822016..fa7d9e20a6b 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -11,9 +11,10 @@ obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6352.o obj-$(CONFIG_PHYLIB) += phy.o obj-$(CONFIG_PHYLIB_10G) += generic_10g.o obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o +obj-$(CONFIG_PHY_INPHI) += in112525.o obj-$(CONFIG_PHY_ATHEROS) += atheros.o obj-$(CONFIG_PHY_BROADCOM) += broadcom.o -obj-$(CONFIG_PHY_CORTINA) += cortina.o +obj-$(CONFIG_PHY_CORTINA) += cortina.o cortina_api.o obj-$(CONFIG_PHY_CORTINA_ACCESS) += ca_phy.o obj-$(CONFIG_PHY_DAVICOM) += davicom.o obj-$(CONFIG_PHY_ET1011C) += et1011c.o diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index b381a431fd9..37a68bb9ac3 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -1,9 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Cortina CS4315/CS4340 10G PHY drivers + * Cortina CS4223 40G PHY driver * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018, 2020 NXP + * Copyright 2018-2021 NXP * */ @@ -17,6 +18,7 @@ #include #include #include +#include #ifdef CONFIG_SYS_CORTINA_FW_IN_NAND #include #elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH) @@ -24,11 +26,16 @@ #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) #include #endif +#include #ifndef CONFIG_PHYLIB_10G #error The Cortina PHY needs 10G support #endif +/* Cortina CS4223 EQ & driver traceloss defaults */ +#define CS4223_LINE_DEFAULT_TRACELOSS CS_HSIO_TRACE_LOSS_4dB +#define CS4223_HOST_DEFAULT_TRACELOSS CS_HSIO_TRACE_LOSS_4dB + #ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD struct cortina_reg_config cortina_reg_cfg[] = { /* CS4315_enable_sr_mode */ @@ -291,14 +298,185 @@ int cs4340_startup(struct phy_device *phydev) return 0; } +int cs4223_phy_setup(struct phy_device *phydev) +{ + int status = CS_OK; + struct cs4224_rules_t rules; + unsigned int slice = 0; + char *env_host_driver_ptr = env_get("cs4223_host_gain"); + char *env_host_eq_ptr = env_get("cs4223_host_eq"); + char *env_host_edc_ptr = env_get("cs4223_host_edc"); + char *env_line_driver_ptr = env_get("cs4223_line_gain"); + char *env_line_eq_ptr = env_get("cs4223_line_eq"); + char *env_line_edc_ptr = env_get("cs4223_line_edc"); + + char *env_autoconfig_ptr = env_get("cs4223_autoconfig"); + int autoconfig_success = 0; + int mseq_dyn_reconfig = CS_FALSE; + + int host_driver_settings = CS4223_HOST_DEFAULT_TRACELOSS; + int host_eq_settings = CS4223_HOST_DEFAULT_TRACELOSS; + int host_edc_mode = CS_HSIO_EDC_MODE_CX1; + + int line_driver_settings = CS4223_LINE_DEFAULT_TRACELOSS; + int line_eq_settings = CS4223_LINE_DEFAULT_TRACELOSS; + int line_edc_mode = CS_HSIO_EDC_MODE_SR; + + cs4223_glue_phydev_set(phydev); + + status |= cs4224_hard_reset(slice); + if (status != CS_OK) { + printf("error trying to reset the device\n"); + return status; + } + + if (env_autoconfig_ptr) { + if (!strncmp(env_autoconfig_ptr, "copper", 6)) { + line_edc_mode = CS_HSIO_EDC_MODE_CX1; + host_edc_mode = CS_HSIO_EDC_MODE_CX1; + host_driver_settings = CS_HSIO_TRACE_LOSS_4dB; + host_eq_settings = CS_HSIO_TRACE_LOSS_4dB; + line_driver_settings = CS_HSIO_TRACE_LOSS_6dB; + line_eq_settings = CS_HSIO_TRACE_LOSS_6dB; + mseq_dyn_reconfig = CS_TRUE; + autoconfig_success = 1; + } + + if (!strncmp(env_autoconfig_ptr, "optical", 7)) { + line_edc_mode = CS_HSIO_EDC_MODE_SR; + host_edc_mode = CS_HSIO_EDC_MODE_CX1; + host_driver_settings = CS_HSIO_TRACE_LOSS_4dB; + host_eq_settings = CS_HSIO_TRACE_LOSS_4dB; + line_driver_settings = CS_HSIO_TRACE_LOSS_4dB; + line_eq_settings = CS_HSIO_TRACE_LOSS_4dB; + mseq_dyn_reconfig = CS_FALSE; + autoconfig_success = 1; + } + } + + if (autoconfig_success) { + printf("CS4223: setting defaults for %s medium type...\n", + env_autoconfig_ptr); + goto skip_config; + } + + if (env_host_driver_ptr) { + host_driver_settings = + simple_strtoul(env_host_driver_ptr, NULL, 10); + + if ((host_driver_settings < CS_HSIO_TRACE_LOSS_0dB) || + (host_driver_settings > CS_HSIO_TRACE_LOSS_6dB)) { + printf("CS4223: host driver settings (%ddB) not ", + host_driver_settings); + printf("supported. Using defaults.\n"); + host_driver_settings = CS4223_HOST_DEFAULT_TRACELOSS; + } else { + host_eq_settings = host_driver_settings; + } + } + + if (env_line_driver_ptr) { + line_driver_settings = + simple_strtoul(env_line_driver_ptr, NULL, 10); + + if ((line_driver_settings < CS_HSIO_TRACE_LOSS_0dB) || + (line_driver_settings > CS_HSIO_TRACE_LOSS_6dB)) { + printf("CS4223: line driver settings (%ddB) not ", + line_driver_settings); + printf("supported. Using defaults.\n"); + line_driver_settings = CS4223_LINE_DEFAULT_TRACELOSS; + } else { + line_eq_settings = line_driver_settings; + } + } + + if (env_host_eq_ptr) { + host_eq_settings = simple_strtoul(env_host_eq_ptr, NULL, 10); + if ((host_eq_settings < CS_HSIO_TRACE_LOSS_0dB) || + (host_eq_settings > CS_HSIO_TRACE_LOSS_6dB)) { + printf("CS4223: host EQ traceloss (%ddB) not supported", + host_eq_settings); + printf(". Matching driver settings or defaults.\n"); + host_eq_settings = host_driver_settings; + } + } + + if (env_line_eq_ptr) { + line_eq_settings = simple_strtoul(env_line_eq_ptr, NULL, 10); + if ((line_eq_settings < CS_HSIO_TRACE_LOSS_0dB) || + (line_eq_settings > CS_HSIO_TRACE_LOSS_6dB)) { + printf("CS4223: line EQ traceloss (%ddB) not supported", + line_eq_settings); + printf(". Matching driver settings or defaults.\n"); + line_eq_settings = line_driver_settings; + } + } + + if (env_line_edc_ptr) { + if (!strncmp(env_line_edc_ptr, "cx", 2)) + line_edc_mode = CS_HSIO_EDC_MODE_CX1; + + if (!strncmp(env_line_edc_ptr, "sr", 2)) + line_edc_mode = CS_HSIO_EDC_MODE_SR; + } + + if (env_host_edc_ptr) { + if (!strncmp(env_host_edc_ptr, "cx", 2)) + host_edc_mode = CS_HSIO_EDC_MODE_CX1; + + if (!strncmp(env_host_edc_ptr, "sr", 2)) + host_edc_mode = CS_HSIO_EDC_MODE_SR; + } + +skip_config: + printf("CS4223: edc/gain/equalization settings: "); + printf("host: %s/%ddB/%ddB, line: %s/%ddB/%ddB\n", + host_edc_mode == CS_HSIO_EDC_MODE_CX1 ? "CX" : "SR", + host_driver_settings, + host_eq_settings, + line_edc_mode == CS_HSIO_EDC_MODE_CX1 ? "CX" : "SR", + line_driver_settings, + line_eq_settings); + + memset(&rules, 0, sizeof(struct cs4224_rules_t)); + status |= cs4224_rules_set_default(CS4224_TARGET_APPLICATION_10G, + &rules); + + if (host_edc_mode == CS_HSIO_EDC_MODE_CX1 && + line_edc_mode == CS_HSIO_EDC_MODE_CX1) + mseq_dyn_reconfig = CS_TRUE; + else + mseq_dyn_reconfig = CS_FALSE; + + rules.mseq_dyn_reconfig = mseq_dyn_reconfig; + rules.rx_if.dplx_line_edc_mode = line_edc_mode; + rules.rx_if.dplx_line_eq.traceloss = line_eq_settings; + rules.tx_if.dplx_line_driver.traceloss = line_driver_settings; + rules.rx_if.dplx_host_edc_mode = host_edc_mode; + rules.rx_if.dplx_host_eq.traceloss = host_eq_settings; + rules.tx_if.dplx_host_driver.traceloss = host_driver_settings; + + for (slice = 0; slice < CS4224_MAX_NUM_SLICES(0); slice++) + status |= cs4224_slice_enter_operational_state(slice, &rules); + + return status; +} + int cs4223_phy_init(struct phy_device *phydev) { int reg_value; + int status; reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); if (!(reg_value & CS4223_EEPROM_FIRMWARE_LOADDONE)) { - printf("%s CS4223 Firmware not present in EERPOM\n", __func__); - return -ENOSYS; + printf("\nCS4223: Using software initialization...\n"); + status = cs4223_phy_setup(phydev); + if (status != CS_OK) + printf("CS4223: Software initialization had issues!\n"); + + } else { + printf("\nCS4223: WARNING: Using EEPROM configuration...\n"); + printf("CS4223: WARNING: Change SW2[2] for software config\n"); } return 0; diff --git a/drivers/net/phy/cortina_api.c b/drivers/net/phy/cortina_api.c new file mode 100644 index 00000000000..6943f93d368 --- /dev/null +++ b/drivers/net/phy/cortina_api.c @@ -0,0 +1,8078 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Cortina PHY drivers framework + * + * Copyright 2018-2021 NXP + * Copyright (C) 2006-2017 Inphi Corporation, Inc. All rights reserved. + */ + +#include "cortina_api.h" + +static struct phy_device *cs4223_phydev; +static struct mii_dev *cs4223_bus; + +void cs4223_glue_phydev_set(struct phy_device *phydev) +{ + cs4223_phydev = phydev; + cs4223_bus = phydev->bus; +} + +int cs4224_reg_set(unsigned int slice, + unsigned int addr, + unsigned short data) +{ + cs4223_bus->write(cs4223_bus, 0, 0, addr, data); + return CS_OK; +} + +int cs4224_reg_get(unsigned int slice, + unsigned int addr, + unsigned short *data) +{ + *data = cs4223_bus->read(cs4223_bus, 0, 0, addr); + return CS_OK; +} + +unsigned char cs4224_diags_register_can_read(unsigned short addr) +{ + /* don't read from select register ranges */ + if ((addr >= CS4224_PP_LINE_SDS_DSP_MSEQ_IX && + addr <= CS4224_PP_LINE_SDS_DSP_MSEQ_BASE3_INST) || + (addr >= CS4224_PP_HOST_SDS_DSP_MSEQ_IX && + addr <= CS4224_PP_HOST_SDS_DSP_MSEQ_BASE3_INST)) { + return CS_FALSE; + } + return CS_TRUE; +} + +#if !defined(CS_SKIP_UCODE_DOWNLOAD) +/* The following array contains the microcode image to download + * to the device. It consists of a series of register writes + * in the format: + * address, data + */ +unsigned short cs4224_kr_ucode_image[] = { + 0x0011, 0x0001, 0x0017, 0x8080, 0x1091, 0x0001, 0x1007, 0x8004, 0x1225, + 0x0008, 0x1238, 0x0000, 0x0301, 0x9000, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x7c0d, 0x0302, 0x0084, 0x0303, 0x7c02, 0x0302, + 0x0088, 0x0303, 0x010d, 0x0302, 0x0060, 0x0303, 0x7c02, 0x0302, 0x0009, + 0x0303, 0x019f, 0x0302, 0x00e0, 0x0303, 0x7c02, 0x0302, 0x008d, 0x0303, + 0x0187, 0x0302, 0x00e0, 0x0303, 0x7c02, 0x0302, 0x00af, 0x0303, 0x01ea, + 0x0302, 0x0060, 0x0303, 0x7c02, 0x0302, 0x002e, 0x0303, 0x016d, 0x0302, + 0x0060, 0x0303, 0xc167, 0x0302, 0x0003, 0x0303, 0x0180, 0x0302, 0x0060, + 0x0303, 0x016d, 0x0302, 0x0060, 0x0303, 0xe805, 0x0302, 0x008d, 0x0303, + 0x4804, 0x0302, 0x008c, 0x0303, 0xc167, 0x0302, 0x0003, 0x0303, 0xc068, + 0x0302, 0x0083, 0x0303, 0x001b, 0x0302, 0x0000, 0x0303, 0xc067, 0x0302, + 0x0083, 0x0303, 0xc168, 0x0302, 0x0003, 0x0303, 0x6893, 0x0302, 0x0083, + 0x0303, 0x000b, 0x0302, 0x00ba, 0x0303, 0x9002, 0x0302, 0x008c, 0x0303, + 0x000f, 0x0302, 0x003a, 0x0303, 0x03f6, 0x0302, 0x0003, 0x0303, 0x9002, + 0x0302, 0x008a, 0x0303, 0x6793, 0x0302, 0x0083, 0x0303, 0x9006, 0x0302, + 0x0009, 0x0303, 0x0708, 0x0302, 0x003a, 0x0303, 0x03f5, 0x0302, 0x0003, + 0x0303, 0x050b, 0x0302, 0x00ba, 0x0303, 0x03f6, 0x0302, 0x0003, 0x0303, + 0x002d, 0x0302, 0x0000, 0x0303, 0x9003, 0x0302, 0x0028, 0x0303, 0xe2f5, + 0x0302, 0x0003, 0x0303, 0x002d, 0x0302, 0x0000, 0x0303, 0xc8f5, 0x0302, + 0x0083, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0xe605, 0x0302, 0x002f, + 0x0303, 0xe6f5, 0x0302, 0x0083, 0x0303, 0x0000, 0x0302, 0x0093, 0x0303, + 0xe643, 0x0302, 0x009f, 0x0303, 0x03f6, 0x0302, 0x0003, 0x0303, 0xe7f9, + 0x0302, 0x0003, 0x0303, 0x0000, 0x0302, 0x0093, 0x0303, 0x8503, 0x0302, + 0x0086, 0x0303, 0x035f, 0x0302, 0x0003, 0x0303, 0x037a, 0x0302, 0x009e, + 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, 0x003c, 0x0302, 0x0041, 0x0303, + 0x7a5f, 0x0302, 0x009e, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, 0x0045, + 0x0302, 0x0080, 0x0303, 0x7b75, 0x0302, 0x0097, 0x0303, 0x004e, 0x0302, + 0x0041, 0x0303, 0xf970, 0x0302, 0x001c, 0x0303, 0x03f9, 0x0302, 0x0003, + 0x0303, 0x757b, 0x0302, 0x009e, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, + 0x7b5f, 0x0302, 0x0099, 0x0303, 0x035f, 0x0302, 0x0003, 0x0303, 0x003c, + 0x0302, 0x0000, 0x0303, 0x7b75, 0x0302, 0x0097, 0x0303, 0x004e, 0x0302, + 0x0041, 0x0303, 0xf970, 0x0302, 0x009d, 0x0303, 0x03f9, 0x0302, 0x0003, + 0x0303, 0x757b, 0x0302, 0x009e, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, + 0x5f7b, 0x0302, 0x001e, 0x0303, 0x035f, 0x0302, 0x0003, 0x0303, 0x0045, + 0x0302, 0x0080, 0x0303, 0xcc60, 0x0302, 0x0003, 0x0303, 0xdb68, 0x0302, + 0x0083, 0x0303, 0x000b, 0x0302, 0x00ba, 0x0303, 0x03db, 0x0302, 0x0011, + 0x0303, 0x03db, 0x0302, 0x0003, 0x0303, 0x0000, 0x0302, 0x0093, 0x0303, + 0x000f, 0x0302, 0x005a, 0x0303, 0x0381, 0x0302, 0x0003, 0x0303, 0xc375, + 0x0302, 0x0083, 0x0303, 0x00f6, 0x0302, 0x0060, 0x0303, 0xf467, 0x0302, + 0x0003, 0x0303, 0x4df4, 0x0302, 0x0097, 0x0303, 0x0056, 0x0302, 0x0041, + 0x0303, 0x0017, 0x0302, 0x009a, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, + 0x00f6, 0x0302, 0x0060, 0x0303, 0xf40f, 0x0302, 0x001f, 0x0303, 0x2267, + 0x0302, 0x0002, 0x0303, 0x4df4, 0x0302, 0x0097, 0x0303, 0x005b, 0x0302, + 0x00c1, 0x0303, 0x002b, 0x0302, 0x009a, 0x0303, 0x0375, 0x0302, 0x0083, + 0x0303, 0x00f6, 0x0302, 0x0060, 0x0303, 0xf472, 0x0302, 0x0083, 0x0303, + 0x4df4, 0x0302, 0x0097, 0x0303, 0x0062, 0x0302, 0x00c1, 0x0303, 0x003f, + 0x0302, 0x009a, 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, 0x00f6, 0x0302, + 0x0060, 0x0303, 0xf40f, 0x0302, 0x001f, 0x0303, 0x2272, 0x0302, 0x0082, + 0x0303, 0x4df4, 0x0302, 0x0097, 0x0303, 0x0068, 0x0302, 0x00c1, 0x0303, + 0x720f, 0x0302, 0x009f, 0x0303, 0x4f75, 0x0302, 0x0082, 0x0303, 0x7567, + 0x0302, 0x0011, 0x0303, 0x03ec, 0x0302, 0x0083, 0x0303, 0x68db, 0x0302, + 0x0083, 0x0303, 0xc081, 0x0302, 0x0003, 0x0303, 0x00e6, 0x0302, 0x00ba, + 0x0303, 0x03f4, 0x0302, 0x0083, 0x0303, 0x03b2, 0x0302, 0x0003, 0x0303, + 0xcffe, 0x0302, 0x0083, 0x0303, 0xc2fd, 0x0302, 0x0003, 0x0303, 0x9015, + 0x0302, 0x000b, 0x0303, 0x780f, 0x0302, 0x009f, 0x0303, 0x0106, 0x0302, + 0x00e0, 0x0303, 0x0083, 0x0302, 0x0080, 0x0303, 0xfd03, 0x0302, 0x0004, + 0x0303, 0xc0fd, 0x0302, 0x0083, 0x0303, 0x0083, 0x0302, 0x0080, 0x0303, + 0xfe70, 0x0302, 0x001d, 0x0303, 0x03fe, 0x0302, 0x0083, 0x0303, 0xc1ae, + 0x0302, 0x0003, 0x0303, 0xc2ae, 0x0302, 0x0003, 0x0303, 0x6f0f, 0x0302, + 0x009f, 0x0303, 0x0106, 0x0302, 0x00e0, 0x0303, 0xc0ae, 0x0302, 0x0083, + 0x0303, 0xb100, 0x0302, 0x00af, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x01f4, 0x0302, 0x003a, 0x0303, 0xb003, + 0x0302, 0x0097, 0x0303, 0xfe02, 0x0302, 0x0009, 0x0303, 0x007e, 0x0302, + 0x0041, 0x0303, 0x00c0, 0x0302, 0x003a, 0x0303, 0x03f4, 0x0302, 0x0083, + 0x0303, 0xc0ea, 0x0302, 0x0083, 0x0303, 0x8403, 0x0302, 0x008d, 0x0303, + 0xc067, 0x0302, 0x0083, 0x0303, 0x01ea, 0x0302, 0x0060, 0x0303, 0xe805, + 0x0302, 0x000a, 0x0303, 0x8000, 0x0302, 0x00ba, 0x0303, 0x9000, 0x0302, + 0x005a, 0x0303, 0x03b7, 0x0302, 0x0003, 0x0303, 0x0354, 0x0302, 0x0083, + 0x0303, 0x9000, 0x0302, 0x0018, 0x0303, 0x0390, 0x0302, 0x0003, 0x0303, + 0xe812, 0x0302, 0x0024, 0x0303, 0xe811, 0x0302, 0x00aa, 0x0303, 0xe809, + 0x0302, 0x0009, 0x0303, 0x810f, 0x0302, 0x009f, 0x0303, 0x037d, 0x0302, + 0x001b, 0x0303, 0x0370, 0x0302, 0x001c, 0x0303, 0x0370, 0x0302, 0x0019, + 0x0303, 0x0381, 0x0302, 0x0003, 0x0303, 0x7d81, 0x0302, 0x001b, 0x0303, + 0x037d, 0x0302, 0x0017, 0x0303, 0x009f, 0x0302, 0x0021, 0x0303, 0x800f, + 0x0302, 0x00da, 0x0303, 0x0106, 0x0302, 0x00e0, 0x0303, 0x810f, 0x0302, + 0x009f, 0x0303, 0x037d, 0x0302, 0x001b, 0x0303, 0x0370, 0x0302, 0x009d, + 0x0303, 0x0381, 0x0302, 0x0003, 0x0303, 0x8184, 0x0302, 0x0028, 0x0303, + 0xc280, 0x0302, 0x0003, 0x0303, 0x07d0, 0x0302, 0x003a, 0x0303, 0x036f, + 0x0302, 0x0011, 0x0303, 0x0106, 0x0302, 0x00e0, 0x0303, 0xc380, 0x0302, + 0x0083, 0x0303, 0x9c40, 0x0302, 0x00ba, 0x0303, 0x036f, 0x0302, 0x0011, + 0x0303, 0x0106, 0x0302, 0x00e0, 0x0303, 0xc280, 0x0302, 0x0003, 0x0303, + 0x00c0, 0x0302, 0x009a, 0x0303, 0x03f4, 0x0302, 0x0083, 0x0303, 0x8503, + 0x0302, 0x0086, 0x0303, 0x035f, 0x0302, 0x0003, 0x0303, 0xd294, 0x0302, + 0x0083, 0x0303, 0xd295, 0x0302, 0x0003, 0x0303, 0xb2ef, 0x0302, 0x0083, + 0x0303, 0xc067, 0x0302, 0x0083, 0x0303, 0x01ea, 0x0302, 0x0060, 0x0303, + 0xd100, 0x0302, 0x0090, 0x0303, 0x03e8, 0x0302, 0x001b, 0x0303, 0x03e8, + 0x0302, 0x0003, 0x0303, 0xc0e1, 0x0302, 0x0003, 0x0303, 0x8503, 0x0302, + 0x0086, 0x0303, 0x03c8, 0x0302, 0x009d, 0x0303, 0x03cf, 0x0302, 0x001b, + 0x0303, 0x0375, 0x0302, 0x0083, 0x0303, 0xc3df, 0x0302, 0x0083, 0x0303, + 0xe803, 0x0302, 0x0003, 0x0303, 0x03c8, 0x0302, 0x009d, 0x0303, 0x03cf, + 0x0302, 0x001b, 0x0303, 0x0372, 0x0302, 0x0003, 0x0303, 0xc04c, 0x0302, + 0x0083, 0x0303, 0x0053, 0x0302, 0x003a, 0x0303, 0x7503, 0x0302, 0x0097, + 0x0303, 0x00d6, 0x0302, 0x00c1, 0x0303, 0x7572, 0x0302, 0x0019, 0x0303, + 0x0375, 0x0302, 0x0083, 0x0303, 0xdf00, 0x0302, 0x0098, 0x0303, 0x03df, + 0x0302, 0x0083, 0x0303, 0x00ce, 0x0302, 0x0080, 0x0303, 0xe803, 0x0302, + 0x0003, 0x0303, 0x03c9, 0x0302, 0x001d, 0x0303, 0x03cc, 0x0302, 0x001b, + 0x0303, 0x03df, 0x0302, 0x0097, 0x0303, 0x00dc, 0x0302, 0x00c1, 0x0303, + 0x03df, 0x0302, 0x0083, 0x0303, 0xe50f, 0x0302, 0x001f, 0x0303, 0x0358, + 0x0302, 0x009b, 0x0303, 0xdf03, 0x0302, 0x009e, 0x0303, 0x03cf, 0x0302, + 0x001b, 0x0303, 0x03df, 0x0302, 0x0083, 0x0303, 0xe802, 0x0302, 0x008f, + 0x0303, 0x00e8, 0x0302, 0x0000, 0x0303, 0x9003, 0x0302, 0x008b, 0x0303, + 0xdc0f, 0x0302, 0x001f, 0x0303, 0x00e7, 0x0302, 0x0000, 0x0303, 0x0021, + 0x0302, 0x003a, 0x0303, 0x03fa, 0x0302, 0x0003, 0x0303, 0xe36e, 0x0302, + 0x001b, 0x0303, 0x03c5, 0x0302, 0x009c, 0x0303, 0x035d, 0x0302, 0x0083, + 0x0303, 0x0000, 0x0302, 0x0093, 0x0303, 0xf663, 0x0302, 0x009f, 0x0303, + 0x0375, 0x0302, 0x0083, 0x0303, 0x0000, 0x0302, 0x0093, 0x0303, 0xf501, + 0x0302, 0x001f, 0x0303, 0x0375, 0x0302, 0x0019, 0x0303, 0x757f, 0x0302, + 0x0003, 0x0303, 0xc0eb, 0x0302, 0x0003, 0x0303, 0xc07c, 0x0302, 0x0083, + 0x0303, 0xc167, 0x0302, 0x0003, 0x0303, 0x0180, 0x0302, 0x0060, 0x0303, + 0xcbf4, 0x0302, 0x0003, 0x0303, 0x7580, 0x0302, 0x0003, 0x0303, 0xf400, + 0x0302, 0x0098, 0x0303, 0x03f4, 0x0302, 0x0083, 0x0303, 0x4dd1, 0x0302, + 0x0011, 0x0303, 0x0386, 0x0302, 0x0083, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x8003, + 0x0302, 0x00a4, 0x0303, 0x838a, 0x0302, 0x002b, 0x0303, 0x0105, 0x0302, + 0x0080, 0x0303, 0x838c, 0x0302, 0x00af, 0x0303, 0x0000, 0x0302, 0x00e1, + 0x0303, 0x0386, 0x0302, 0x0083, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 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0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, + 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, + 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, + 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, 0x0303, 0x0000, 0x0302, 0x0042, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8000, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x8001, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8002, + 0x1222, 0x0005, 0x1221, 0x4818, 0x1220, 0x8003, 0x1222, 0x000b, 0x1221, + 0x4818, 0x1220, 0x8004, 0x1222, 0x0017, 0x1221, 0x4820, 0x1220, 0x8005, + 0x1222, 0x001f, 0x1221, 0x0000, 0x1220, 0x8006, 0x1222, 0x0010, 0x1221, + 0x0000, 0x1220, 0x8007, 0x1222, 0x0010, 0x1221, 0x0000, 0x1220, 0x8008, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8009, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x800a, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x800b, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x800c, 0x1222, 0x0028, 0x1221, + 0x0000, 0x1220, 0x800d, 0x1222, 0x0001, 0x1221, 0x0000, 0x1220, 0x800e, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x800f, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x8010, 0x1222, 0x0a60, 0x1221, 0x8000, 0x1220, 0x8011, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8012, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x8013, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8014, + 0x1222, 0x001e, 0x1221, 0x0000, 0x1220, 0x8015, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x8016, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8017, + 0x1222, 0x7fff, 0x1221, 0x0000, 0x1220, 0x8018, 0x1222, 0x0003, 0x1221, + 0x0000, 0x1220, 0x8019, 0x1222, 0x0003, 0x1221, 0x0000, 0x1220, 0x801a, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x801b, 0x1222, 0x0003, 0x1221, + 0x0000, 0x1220, 0x801c, 0x1222, 0x0400, 0x1221, 0x0000, 0x1220, 0x801d, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x801e, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x801f, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8020, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8021, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x8022, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8023, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8024, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x8025, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8026, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8027, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x8028, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8029, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x802a, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x802b, 0x1222, 0x0f70, 0x1221, 0x8000, 0x1220, 0x802c, + 0x1222, 0x0100, 0x1221, 0x0000, 0x1220, 0x802d, 0x1222, 0x007f, 0x1221, + 0x0000, 0x1220, 0x802e, 0x1222, 0x0040, 0x1221, 0x8000, 0x1220, 0x802f, + 0x1222, 0x0001, 0x1221, 0x0000, 0x1220, 0x8030, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x8031, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8032, + 0x1222, 0x00fa, 0x1221, 0x0000, 0x1220, 0x8033, 0x1222, 0x00d2, 0x1221, + 0x0000, 0x1220, 0x8034, 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8035, + 0x1222, 0x02aa, 0x1221, 0x0000, 0x1220, 0x8036, 0x1222, 0x0000, 0x1221, + 0x0000, 0x1220, 0x8037, 0x1222, 0x0014, 0x1221, 0x8000, 0x1220, 0x8038, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x8039, 0x1222, 0x47ab, 0x1221, + 0x0000, 0x1220, 0x803a, 0x1222, 0x0554, 0x1221, 0x0000, 0x1220, 0x803b, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x803c, 0x1222, 0x03ff, 0x1221, + 0x0000, 0x1220, 0x803d, 0x1222, 0x1fff, 0x1221, 0x8000, 0x1220, 0x803e, + 0x1222, 0x0000, 0x1221, 0x0000, 0x1220, 0x803f, 0x102f, 0xc0f0, 0x1000, + 0x0000, 0x100b, 0xf182, 0x1001, 0x0000, 0x1007, 0x0004, 0x1228, 0x0000, + 0x1235, 0x0000, 0x1a35, 0x0000, 0x1327, 0x0000, 0x132b, 0x0000, 0x0003, + 0x0001, 0x0004, 0x0001, 0x0005, 0x0001, 0x0006, 0x0001, 0x0007, 0x0001, + 0x0301, 0x0000, 0x1320, 0x0000, 0x1324, 0x0000, 0x1328, 0x0000, 0x0017, + 0x0040, 0x1238, 0x0003, 0x1a38, 0x0003, 0x1249, 0x0001, 0x1343, 0x0006, + 0x1262, 0x007f, 0x1263, 0x007f, 0x1264, 0x007f, 0x1248, 0x8100, 0x1247, + 0x8010, 0x1268, 0x0002, 0x1282, 0x0005, 0x1288, 0x3000, 0x124c, 0x8001, + 0x1298, 0x0003, 0x1245, 0x8c0f, 0x10aa, 0xff5d, 0x1265, 0x001e, 0x1027, + 0x00dd, 0x12b1, 0x0000, 0x1a98, 0x0003, 0x18ae, 0x0441, 0x18a1, 0x0004, + 0x18a7, 0xdfff, 0x18a6, 0x000d, 0x1a45, 0x8c0f, 0x18aa, 0xff5d, 0x1a34, + 0x0002, 0x1a5e, 0x0000, 0x1a5f, 0x0700, 0x1a49, 0x0001, 0x1b43, 0x0006, + 0x1a65, 0x001e, 0x1a62, 0x007f, 0x1a63, 0x007f, 0x1a64, 0x007f, 0x1a48, + 0x8100, 0x1a47, 0x8010, 0x1a68, 0x0002, 0x1a82, 0x0014, 0x1a4c, 0x8001, + 0x1827, 0x00dd, 0x1a35, 0x01f7, 0x1ab1, 0x0000, 0x0017, 0x0000, 0x000a, + 0x0946, 0x0009, 0x2016, 0x0008, 0x0314, 0x0005, 0x0003, 0x0007, 0x0000, + 0x0011, 0x0000, 0x0014, 0x12cd, 0x0017, 0x0000, +}; + +unsigned int cs4224_kr_ucode_image_length = sizeof(cs4224_kr_ucode_image) + / sizeof(cs4224_kr_ucode_image[0]); + +#endif /* !CS_SKIP_UCODE_DOWNLOAD */ + +/* extern unsigned short g_cs4224_simplex_valid_mate_slice[]; */ +/* unsigned char cs4224_diags_register_can_read(unsigned short addr); */ + +static enum e_cs4224_hardware_id cs4224_sku_hw_id = CS4224_HW_UNDEF; + +int g_cs4224_mseq_stall_delay_us = 100; + +void cs4224_reset_static_state_for_slice(unsigned int slice) +{ + CS_TRACE(("resetting slice %d\n", slice)); +} + +void cs4224_reset_static_state(void) +{ + cs4224_reset_die_static_state(0); +} + +void cs4224_reset_die_static_state(unsigned int die) +{ + unsigned int upper_bits = die & 0xFFFFFF00; + unsigned int slice; + + for (slice = upper_bits; (slice & 0xFF) < CS4224_MAX_NUM_SLICES(die); + slice++) { + cs4224_reset_static_state_for_slice(slice); + } + + /* this forces the cached hw_id to be re-initialized */ + cs4224_sku_hw_id = CS4224_HW_UNDEF; +} + +int cs4224_init_api_version(unsigned int slice) +{ + int status = CS_OK; + unsigned short api_version; + + /* Program the API version number */ + api_version = (CS_API_VERSION_MAJOR & 0xF); + api_version <<= 4; + api_version |= (CS_API_VERSION_MINOR & 0xF); + api_version <<= 8; + api_version |= CS_API_VERSION_UPDATE; + status |= cs4224_reg_set_channel(slice, CS4224_GLOBAL_SCRATCH7, + api_version); + + return status; +} + +unsigned int cs4224_max_num_ports; +unsigned int cs4224_max_num_dies; + +unsigned int CS4224_MAX_NUM_PORTS(void) +{ + return CS4224_MAX_NUM_SLICES(0); +} + +unsigned int CS4224_MAX_NUM_SLICES(unsigned int slice) +{ + /* Determine the h/w ID in order to + * initialize the number of ports + */ + cs4224_hw_id(slice); + + /* Now that the number of ports has been identified + * just return the initialized value + */ + return cs4224_max_num_ports; +} + +unsigned int CS4224_MAX_NUM_DIES(unsigned int slice) +{ + cs4224_hw_id(slice); + return cs4224_max_num_dies; +} + +cs4224_callback_lock g_cs4224_callback_lock = NULL; +cs4224_callback_unlock g_cs4224_callback_unlock; + +void cs4224_set_callback_for_lock(cs4224_callback_lock callback) +{ + g_cs4224_callback_lock = callback; +} + +void cs4224_set_callback_for_unlock(cs4224_callback_unlock callback) +{ + g_cs4224_callback_unlock = callback; +} + +int cs4224_lock(unsigned int slice) +{ + if (!g_cs4224_callback_lock) + return CS_OK; + + return g_cs4224_callback_lock(slice); +} + +int cs4224_unlock(unsigned int slice) +{ + if (!g_cs4224_callback_unlock) + return CS_OK; + + return g_cs4224_callback_unlock(slice); +} + +enum e_cs4224_hardware_id cs4224_hw_id(unsigned int slice) +{ + if (cs4224_sku_hw_id == CS4224_HW_UNDEF) { + unsigned short sku; + int status = CS_OK; + + cs4224_lock(slice); + + status |= cs4224_reg_get(0 | (slice & 0xffffff00), + CS4224_EFUSE_PDF_SKU, &sku); + + cs4224_unlock(slice); + + if (status != CS_OK) { + CS_TRACE(("WARNING: Could not read SKU\n")); + sku = 0x0000; + } + + /* clear SKU bits [15:5] and [3] */ + sku &= 0x0017; + + /* If the EFUSE is not programmed then default to CS4343. + * Bit 5 will be set to 1 if the EFUSE is programmed. If it + * is not programmed it will 0. + */ + if ((sku & 0x10) != 0x10) { + unsigned short chip_id; + + /* Try reading the ASIC ID from the second die. If it + * returns a non valid value then assume this is a 4D + * part. If it is a 4D part then the ASIC ID should + * return 0xffff. A value of 0 probably means that we're + * running CS Explorer in offline mode. + */ + status |= cs4224_reg_get( + 1 | (slice & 0xffffff00), + CS4224_GLOBAL_CHIP_ID_MSB, &chip_id); + + if (chip_id == 0 || chip_id == 0x3e5) { + CS_TRACE(("WARNING: EFUSE not programmed\n")); + CS_TRACE(("WARNING: Defaulting to CS4243\n")); + + cs4224_sku_hw_id = CS4224_HW_CS4343; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4343_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4343_DIES; + } else { + CS_TRACE(("WARNING: EFUSE not programmed\n")); + CS_TRACE(("WARNING: Defaulting to CS4223\n")); + + cs4224_sku_hw_id = CS4224_HW_CS4223; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4223_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4223_DIES; + } + } + /* Otherwise check what SKU is programmed */ + else { + switch (sku) { + case CS4224_HW_CS4223: + /* 4 port duplex */ + cs4224_sku_hw_id = CS4224_HW_CS4223; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4223_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4223_DIES; + break; + case CS4224_HW_CS4224: + /* 16 port simplex */ + cs4224_sku_hw_id = CS4224_HW_CS4224; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4224_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4224_DIES; + break; + case CS4224_HW_CS4221: + /* 10 port simplex */ + cs4224_sku_hw_id = CS4224_HW_CS4221; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4221_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4221_DIES; + break; + case CS4224_HW_CS4227: + /* 2 port duplex */ + cs4224_sku_hw_id = CS4224_HW_CS4227; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4227_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4227_DIES; + break; + case CS4224_HW_CS4210: + /* 16 port simplex */ + cs4224_sku_hw_id = CS4224_HW_CS4210; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4210_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4210_DIES; + break; + case CS4224_HW_CS4341: + /* 8 port duplex */ + cs4224_sku_hw_id = CS4224_HW_CS4341; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4341_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4341_DIES; + break; + default: + /* SKU must be cs4343 or if undefined + * we default to 8 port duplex + */ + cs4224_sku_hw_id = CS4224_HW_CS4343; + cs4224_max_num_ports = + CS4224_MAX_NUM_CS4343_PORTS; + cs4224_max_num_dies = + CS4224_MAX_NUM_CS4343_DIES; + break; + } + } + } + + return cs4224_sku_hw_id; +} + +unsigned char cs4224_is_hw_simplex(unsigned int slice) +{ + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + if ((hw_id == CS4224_HW_CS4224) || + (hw_id == CS4224_HW_CS4221) || + (hw_id == CS4224_HW_CS4210)) { + return CS_TRUE; + } + return CS_FALSE; +} + +unsigned char cs4224_is_hw_duplex(unsigned int slice) +{ + /* only keep the 'list' of simplex/duplex slices in one place */ + if (cs4224_is_hw_simplex(slice)) + return CS_FALSE; + + return CS_TRUE; +} + +unsigned short cs4224_pp_sku_cs4343_offset[8] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x1000, 0x2000, 0x3000, 0x3000, 0x2000, 0x1000, 0x0000 +}; + +unsigned short cs4224_mseq_sku_cs4343_offset[8] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x0000, 0x100, 0x100, 0x0100, 0x0100, 0x0000, 0x0000 +}; + +/* CS4224_HW_CS4224 16 port simplex + * CS4224_HW_CS4210 16 port simplex, 15G only + */ +unsigned short cs4224_pp_sku_cs4224_offset[16] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x1000, 0x3000, 0x1000, 0x2000, 0x0000, 0x3000, 0x2000, + /* slice 8, 9, 10, 11, 12, 13, 14, 15 */ + 0x0000, 0x2000, 0x1000, 0x3000, 0x2000, 0x0000, 0x1000, 0x3000 +}; + +unsigned short cs4224_mseq_sku_cs4224_offset[16] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x0000, 0x0100, 0x0000, 0x0100, 0x0000, 0x0100, 0x0100, + /* slice 8, 9, 10, 11, 12, 13, 14, 15 */ + 0x0000, 0x0100, 0x0000, 0x0100, 0x0100, 0x0000, 0x0000, 0x0100 +}; + +/* CS4224_HW_CS4221 10 port simplex + * Relative to CS4224, CS4221 is mapped: + * CS4221 CS4224 + * Port Port + * 0 1 + * 1 0 + * 2 3 + * 3 5 + * 4 6 + * 5 10 + * 6 9 + * 7 11 + * 8 13 + * 9 14 + */ +unsigned short cs4224_pp_sku_cs4221_offset[10] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x1000, 0x0000, 0x1000, 0x0000, 0x3000, 0x1000, 0x2000, 0x3000, + /* slice 8, 9, */ + 0x0000, 0x1000 +}; + +unsigned short cs4224_mseq_sku_cs4221_offset[10] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 0x0000, 0x0000, 0x0000, 0x0000, 0x0100, 0x0000, 0x0100, 0x0100, + /* slice 8, 9, */ + 0x0000, 0x0000 +}; + +unsigned int cs4224_adj_pp(unsigned int slice, unsigned short addr) +{ + unsigned short adj_addr = addr; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + switch (hw_id) { + case CS4224_HW_CS4223: /* 4 port duplex */ + + if ((slice & 0xFF) > 3) { + CS_TRACE(("ERROR: Duplex slice arg > 3, slice=0x%x\n", + slice)); + } + /* same mapping as cs4343 */ + adj_addr = (addr + cs4224_pp_sku_cs4343_offset[slice & 0x7]); + break; + + case CS4224_HW_CS4224: /* 16 port simplex */ + + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: Simplex slice arg > 15, slice=0x%x\n", + slice)); + } + adj_addr = (addr + cs4224_pp_sku_cs4224_offset[slice & 0xF]); + + break; + + case CS4224_HW_CS4343: /* 8 port duplex */ + + if ((slice & 0xFF) > 7) { + CS_TRACE(("ERROR: Duplex slice arg > 7, slice=0x%x\n", + slice)); + } + adj_addr = (addr + cs4224_pp_sku_cs4343_offset[slice & 0x7]); + + break; + + case CS4224_HW_CS4221: /* 10 port simplex */ + + if ((slice & 0xFF) > 9) { + CS_TRACE(("ERROR: Simplex slice arg > 9, slice=0x%x\n", + slice)); + adj_addr = (addr + cs4224_pp_sku_cs4221_offset[0]); + } else { + adj_addr = (addr + + cs4224_pp_sku_cs4221_offset[slice & 0xF]); + } + + break; + + case CS4224_HW_CS4227: /* 2 port duplex */ + + if ((slice & 0xFF) > 1) { + CS_TRACE(("ERROR: Duplex slice arg > 1, slice=0x%x\n", + slice)); + } + /* same mapping as cs4343 */ + adj_addr = (addr + cs4224_pp_sku_cs4343_offset[slice & 0x7]); + break; + + case CS4224_HW_CS4210: /* 16 port simplex */ + + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: Simplex slice arg > 15, slice=0x%x\n", + slice)); + } + adj_addr = (addr + cs4224_pp_sku_cs4224_offset[slice & 0xF]); + + break; + + case CS4224_HW_CS4341: /* 8 port duplex */ + if ((slice & 0xFF) > 7) { + CS_TRACE(("ERROR: Duplex slice arg > 7, slice=0x%x\n", + slice)); + } + adj_addr = (addr + cs4224_pp_sku_cs4343_offset[slice & 0x7]); + + break; + + default: + CS_TRACE(("ERROR: invalid hw_id: %x\n", hw_id)); + break; + } + + return adj_addr; +} + +unsigned int cs4224_adj_mseq(unsigned int slice, unsigned short addr) +{ + unsigned short adj_addr = addr; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + switch (hw_id) { + case CS4224_HW_CS4223: /* 4 port duplex */ + if ((slice & 0xFF) > 3) { + CS_TRACE(("ERROR: Duplex slice arg > 3, slice=%d\n", + slice)); + } + /* same mapping as cs4343 */ + adj_addr = (addr + cs4224_mseq_sku_cs4343_offset[slice & 0x7]); + break; + + case CS4224_HW_CS4224: /* 16 port simplex */ + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: Simplex slice arg > 15, slice=%d\n", + slice)); + } + adj_addr = (addr + cs4224_mseq_sku_cs4224_offset[slice & 0xF]); + + break; + + case CS4224_HW_CS4343: /* 8 port duplex */ + if ((slice & 0xFF) > 7) { + CS_TRACE(("ERROR: Duplex slice arg > 7, slice=%d\n", + slice)); + } + adj_addr = (addr + cs4224_mseq_sku_cs4343_offset[slice & 0x7]); + + break; + + case CS4224_HW_CS4221: /* 10 port simplex */ + if ((slice & 0xFF) > 9) { + CS_TRACE(("ERROR: Simplex slice arg > 9, slice=%d\n", + slice)); + adj_addr = (addr + cs4224_mseq_sku_cs4221_offset[0]); + } else { + adj_addr = (addr + + cs4224_mseq_sku_cs4221_offset[slice & 0xF]); + } + + break; + + case CS4224_HW_CS4227: /* 2 port duplex */ + if ((slice & 0xFF) > 1) { + CS_TRACE(("ERROR: Duplex slice arg > 1, slice=%d\n", + slice)); + } + /* same mapping as cs4343 */ + adj_addr = (addr + cs4224_mseq_sku_cs4343_offset[slice & 0x7]); + break; + + case CS4224_HW_CS4210: /* 16 port simplex */ + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: Simplex slice arg > 15, slice=%d\n", + slice)); + } + adj_addr = (addr + cs4224_mseq_sku_cs4224_offset[slice & 0xF]); + + break; + + case CS4224_HW_CS4341: /* 8 port duplex */ + if ((slice & 0xFF) > 7) { + CS_TRACE(("ERROR: Duplex slice arg > 7, slice=%d\n", + slice)); + } + adj_addr = (addr + cs4224_mseq_sku_cs4343_offset[slice & 0x7]); + + break; + + default: + CS_TRACE(("ERROR: invalid hw_id: %x\n", hw_id)); + break; + } + + return adj_addr; +} + +/* simplex mate slices (slices with the same PP number on the die) */ +unsigned short cs4224_mate_slice_sku_cs4224[16] = { + /* slice 0, 1, 2, 3, 4, 5, 6, 7 */ + 5, 3, 6, 1, 7, 0, 2, 4, + /* slice 8, 9, 10, 11, 12, 13, 14, 15 */ + 13, 12, 14, 15, 9, 8, 10, 11 }; + +/* CS4221 has some 'empty' slices that don't have a mate slice, those must be + * handled manually, as there is no way to address them with reg_Xet_channel + */ +unsigned short cs4224_mate_slice_sku_cs4221[10] = { + /* slice 0, 1, 2, 3, 4 */ + 2, 3, 0, 1, 0xff, + /* slice 5, 6, 7, 8, 9 */ + 9, 0xff, 0xff, 0xff, 5 +}; + +int cs4224_simplex_mate_slice(unsigned int slice, unsigned int *mate) +{ + int status = CS_OK; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + unsigned char base_slice = (slice & 0xFF); + unsigned int upper_bits = (slice & 0xFFFFFF00); + + *mate = 0xFF; + + switch (hw_id) { + case CS4224_HW_CS4224: + case CS4224_HW_CS4210: /*16 port simplex*/ + if ((slice & 0xFF) > 15) { + CS_TRACE(("ERROR: slice parameter > 15\n")); + return CS_ERROR; + } + *mate = cs4224_mate_slice_sku_cs4224[base_slice]; + + break; + case CS4224_HW_CS4221: /*10 port simplex*/ + if ((slice & 0xFF) > 10) { + CS_TRACE(("ERROR: slice parameter > 10\n")); + return CS_ERROR; + } + *mate = cs4224_mate_slice_sku_cs4221[base_slice]; + + break; + default: + /* if duplex then just return the same slice, + * since that's technically correct + */ + *mate = base_slice; + + break; + } + + if (*mate == 0xFF) { + CS_TRACE(("ERROR: base_slice %d simplex mate missing\n", + base_slice)); + status |= CS_ERROR; + } + + *mate |= upper_bits; + + return status; +} + +unsigned char cs4224_line_rx_to_host_tx_dir(unsigned int slice) +{ + unsigned char lrx_to_htx = CS_TRUE; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + /* Mask off the upper bits in case they are set + * by the user. Otherwise the switch statement + * below won't work properly. + */ + slice = slice & 0xFF; + + if ((hw_id == CS4224_HW_CS4224) || (hw_id == CS4224_HW_CS4210)) { + /* 16 port simplex */ + switch (slice) { + case 0: + case 1: + case 2: + lrx_to_htx = CS_TRUE; + break; + + case 3: + lrx_to_htx = CS_FALSE; + break; + + case 4: + lrx_to_htx = CS_TRUE; + break; + + case 5: + case 6: + case 7: + lrx_to_htx = CS_FALSE; + break; + + case 8: + case 9: + case 10: + case 11: + lrx_to_htx = CS_TRUE; + break; + + case 12: + case 13: + case 14: + case 15: + lrx_to_htx = CS_FALSE; + break; + + default: + lrx_to_htx = CS_TRUE; + break; + } + } else if (hw_id == CS4224_HW_CS4221) { + /* 10 port simplex */ + switch (slice) { + case 0: + case 1: + lrx_to_htx = CS_TRUE; + break; + + case 2: + case 3: + case 4: + lrx_to_htx = CS_FALSE; + break; + + case 5: + case 6: + case 7: + lrx_to_htx = CS_TRUE; + break; + + case 8: + case 9: + lrx_to_htx = CS_FALSE; + break; + + default: + lrx_to_htx = CS_TRUE; + break; + } + } + + return lrx_to_htx; +} + +int cs4224_get_mseq_id(unsigned int slice, enum e_cs4224_mseq_id *mseq_id) +{ + int status = CS_OK; + + /* if mseq_id isn't simplex then just assume the user + * knows what they are doing + */ + if (cs4224_is_hw_simplex(slice) && *mseq_id == CS4224_SPLX_MSEQ) { + if (cs4224_line_rx_to_host_tx_dir(slice)) + *mseq_id = CS4224_DPLX_LINE_MSEQ; + else + *mseq_id = CS4224_DPLX_HOST_MSEQ; + } else { + if (*mseq_id == CS4224_SPLX_MSEQ) { + CS_TRACE(("ERROR: Duplex slice, invalid mseq_id\n")); + status |= CS_ERROR; + } + } + + return status; +} + +unsigned int cs4224_mseq_get_addr_offset(unsigned int slice, + enum e_cs4224_mseq_id mseq) +{ + unsigned int offset = 0; /* 0 is line side, 0x800 is host side */ + + if (cs4224_is_hw_simplex(slice) && mseq == CS4224_SPLX_MSEQ) { + if (!cs4224_line_rx_to_host_tx_dir(slice)) + offset = 0x800; + } else if (mseq == CS4224_DPLX_HOST_MSEQ) { + offset = 0x800; + } + + return offset; +} + +int cs4224_get_cfg_side(unsigned int slice, enum e_cs4224_cfg_sides_t *side) +{ + int status = CS_OK; + + /* a bit different than get_mseq_id, if you specify a non-simplex side + * then default to using that, otherwise use the Rx side of the simplex + * slice + */ + if (cs4224_is_hw_simplex(slice) && (*side == CS4224_CFG_SIMPLEX)) { + if (cs4224_line_rx_to_host_tx_dir(slice)) + *side = CS4224_CFG_LINE_SIDE; + else + *side = CS4224_CFG_HOST_SIDE; + } else { + if (*side == CS4224_CFG_SIMPLEX) { + CS_TRACE(("ERROR: Duplex slice, not simplex\n")); + status |= CS_ERROR; + } + } + + return status; +} + +int cs4224_mux_enable(unsigned int slice, + enum e_cs4224_cfg_sides_t side, + unsigned char enable) +{ + int status = CS_OK; + unsigned short stx0_misc_addr; + unsigned short data; + + if (side == CS4224_CFG_SIMPLEX) { + CS_TRACE(("ERROR: CS4224_CFG_SIMPLEX arg not supported\n")); + return CS_ERROR; + } + + if (side == CS4224_CFG_LINE_SIDE) + stx0_misc_addr = CS4224_PP_LINE_SDS_COMMON_STX0_MISC; + else + stx0_misc_addr = CS4224_PP_HOST_SDS_COMMON_STX0_MISC; + + cs4224_lock(slice); + + status |= cs4224_reg_get_channel(slice, stx0_misc_addr, &data); + if (enable) + data &= ~0x11; /* power-up mux, STX_EYEMODE_EN=0 */ + else + data |= 0x11; /* power-down mux, STX_EYEMODE_EN=1 */ + + status |= cs4224_reg_set_channel(slice, stx0_misc_addr, data); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_demux_enable(unsigned int slice, enum e_cs4224_cfg_sides_t side, + unsigned char enable) +{ + int status = CS_OK; + unsigned short mseq_power_down_addr; + unsigned short agc_config1_addr; + unsigned short data; + + if (side == CS4224_CFG_SIMPLEX) { + CS_TRACE(("ERROR: CS4224_CFG_SIMPLEX arg not supported\n")); + return CS_ERROR; + } + + if (side == CS4224_CFG_LINE_SIDE) { + mseq_power_down_addr = + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB; + agc_config1_addr = CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1; + } else { + mseq_power_down_addr = + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB; + agc_config1_addr = CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1; + } + + cs4224_lock(slice); + + cs4224_reg_get_channel(slice, agc_config1_addr, &data); + + /* Don't touch the power down registers if we're in CX1 mode */ + if (data != 0x5) { + if (enable) { + status |= cs4224_reg_get_channel( + slice, mseq_power_down_addr, &data); + data |= 0x001f; /* partial power-up */ + status |= cs4224_reg_set_channel( + slice, mseq_power_down_addr, data); + data &= ~0x001f; /* clear the partial power-up */ + data &= ~0x01c0; /* full power-up demux */ + status |= cs4224_reg_set_channel( + slice, mseq_power_down_addr, data); + } else { + status |= cs4224_reg_get_channel( + slice, mseq_power_down_addr, &data); + data |= 0x01c0; /* power-down demux */ + status |= cs4224_reg_set_channel( + slice, mseq_power_down_addr, data); + } + } + + cs4224_unlock(slice); + + return status; +} + +#define CS4224_SENSE_POINT_LOCAL_TEMPERATURE 1 << 0 +#define CS4224_SENSE_POINT_REMOTE_TEMPERATURE 1 << 1 +#define CS4224_SENSE_POINT_0p9_RX_VOLTAGE 1 << 2 +#define CS4224_SENSE_POINT_0p9_TX_VOLTAGE 1 << 3 +#define CS4224_SENSE_POINT_0p9_DIG_RX_VOLTAGE 1 << 4 +#define CS4224_SENSE_POINT_0p9_DIG_TX_VOLTAGE 1 << 5 +#define CS4224_SENSE_POINT_1p8_RX_VOLTAGE 1 << 6 +#define CS4224_SENSE_POINT_1p8_TX_VOLTAGE 1 << 7 +#define CS4224_SENSE_POINT_1p5_RX_VOLTAGE 1 << 8 +#define CS4224_SENSE_POINT_1p5_TX_VOLTAGE 1 << 9 + +int cs4224_enable_monitor_sense_points(unsigned int die, + unsigned char wait_till_stabilized) +{ + unsigned short reg_data; + int status = CS_OK; + + status |= cs4224_reg_get(die, CS4224_MONITOR_CONTROL0, ®_data); + + if (reg_data != 0x630F) { + status |= cs4224_reg_set(die, CS4224_MONITOR_CONFIG_MASK, + CS4224_SENSE_POINT_LOCAL_TEMPERATURE | + CS4224_SENSE_POINT_0p9_RX_VOLTAGE | + CS4224_SENSE_POINT_1p8_RX_VOLTAGE); + + status |= cs4224_reg_set(die, CS4224_MONITOR_CONTROL0, 0x630F); + + if (wait_till_stabilized) { + unsigned short reg_data; + int last = 0; + int i; + + /* Waiting for the monitors to stabilize */ + cs4224_reg_get(die, CS4224_MONITOR_STATUS_FINAL6, + ®_data); + + for (i = 0; i < 100; i++) { + CS_MDELAY(10); + + if (last > (int)reg_data) + break; + + last = (int)reg_data; + cs4224_reg_get(die, + CS4224_MONITOR_STATUS_FINAL6, + ®_data); + } + } + } + + return status; +} + +int cs4224_version(char *buffer, unsigned int buffer_len) +{ + CS_STRNCPY(buffer, + "CS4224 API Version " CS_API_VERSION "\n" + "Built on " CS_API_BUILD_DATE "\n", + buffer_len); + + return CS_OK; +} + +int cs4224_init_vco(unsigned int slice, unsigned int addr) +{ + int status = CS_OK; + unsigned short offset = 0; + unsigned short data = 0; + unsigned short i = 0; + + if (addr & CS4224_LINE_TO_HOST_OFFSET) + offset = CS4224_LINE_TO_HOST_OFFSET; + else + offset = 0; + + cs4224_lock(slice); + + /* re-initialize the VCO ALT coarse tuning algorithm + * to start searching for the correct frequency + */ + status |= cs4224_reg_set_channel(slice, addr, 0x2001); + status |= cs4224_reg_set_channel(slice, addr, 0xa001); + status |= cs4224_reg_set_channel(slice, addr, 0x2001); + + /* the worst-case time out value is where F(ref_clk) > F(vco_clk) so a + * timeout of 3.3ms should suffice for the completion of coarse tuning. + */ + for (i = 1500; i > 0; i--) { + /* check for CTVALID */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_STATUS + offset, + &data); + if ((data & CS_BIT15) || (status != CS_OK)) { + /* tuning done or error, exit */ + break; + } + CS_UDELAY(10); + } + cs4224_unlock(slice); + + if (i == 0) { + if (offset == 0) + CS_TRACE(("ERROR: Timeout slice %d Line VCO\n", slice)); + else + CS_TRACE(("ERROR: Timeout slice %d Host VCO\n", slice)); + + CS_TRACE(("ERROR: check CS_UDELAY implementation\n")); + status |= CS_ERROR; + } + + return status; +} + +int cs4224_gbl_clock_monitor(unsigned int slice, + struct cs4224_gbl_clk_mon_cfg_t *clk_mon_cfg) +{ + int status = CS_OK; + unsigned short data; + + CS_PRINTF(("Configuring the GBL clkmon\n")); + + data = clk_mon_cfg->clksel_divider | clk_mon_cfg->clksel_src; + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_CLKSEL, data); + + data = 0; + if (clk_mon_cfg->go) + data = 0x0002; + + if (clk_mon_cfg->free_run) + data |= 0x0010; + + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_CTRL, data); + + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_DURATION, + clk_mon_cfg->duration); + + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_MINTHRESH0, + clk_mon_cfg->min_thresh_0); + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_MINTHRESH1, + clk_mon_cfg->min_thresh_1); + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_MAXTHRESH0, + clk_mon_cfg->max_thresh_0); + status |= cs4224_reg_set_channel(slice, CS4224_CLKMON_GBL_MAXTHRESH1, + clk_mon_cfg->max_thresh_1); + + return status; +} + +void cs4224_pp_clk_mon_cfg_init(struct cs4224_pp_clk_mon_cfg_t *clk_mon_cfg) +{ + clk_mon_cfg->clksel_divider = CS4224_CLK_MON_DIV1; + clk_mon_cfg->clksel_src = CS4224_CLK_MON_PP_SRX; + clk_mon_cfg->go = CS_TRUE; + clk_mon_cfg->free_run = CS_TRUE; + clk_mon_cfg->duration = 0x4000; + clk_mon_cfg->min_thresh = 0; + clk_mon_cfg->max_thresh = 0; +} + +int cs4224_pp_clock_monitor(unsigned int slice, + enum e_cs4224_cfg_sides_t side, + struct cs4224_pp_clk_mon_cfg_t *clk_mon_cfg) +{ + int status = CS_OK; + unsigned short clksel_addr; + unsigned short ctrl_addr; + unsigned short duration_addr; + unsigned short min_thresh0_addr; + unsigned short min_thresh1_addr; + unsigned short max_thresh0_addr; + unsigned short max_thresh1_addr; + unsigned short data; + + status |= cs4224_get_cfg_side(slice, &side); + + if (side == CS4224_CFG_HOST_SIDE) { + clksel_addr = CS4224_PP_CLKMON_EGR_CLKSEL; + ctrl_addr = CS4224_PP_CLKMON_EGR_CTRL; + duration_addr = CS4224_PP_CLKMON_EGR_DURATION; + min_thresh0_addr = CS4224_PP_CLKMON_EGR_MINTHRESH0; + min_thresh1_addr = CS4224_PP_CLKMON_EGR_MINTHRESH1; + max_thresh0_addr = CS4224_PP_CLKMON_EGR_MAXTHRESH0; + max_thresh1_addr = CS4224_PP_CLKMON_EGR_MAXTHRESH1; + } else { + clksel_addr = CS4224_PP_CLKMON_ING_CLKSEL; + ctrl_addr = CS4224_PP_CLKMON_ING_CTRL; + duration_addr = CS4224_PP_CLKMON_ING_DURATION; + min_thresh0_addr = CS4224_PP_CLKMON_ING_MINTHRESH0; + min_thresh1_addr = CS4224_PP_CLKMON_ING_MINTHRESH1; + max_thresh0_addr = CS4224_PP_CLKMON_ING_MAXTHRESH0; + max_thresh1_addr = CS4224_PP_CLKMON_ING_MAXTHRESH1; + } + + data = clk_mon_cfg->clksel_divider | clk_mon_cfg->clksel_src; + status |= cs4224_reg_set_channel(slice, clksel_addr, data); + + status |= cs4224_reg_set_channel( + slice, + duration_addr, + clk_mon_cfg->duration); + + status |= cs4224_reg_set_channel( + slice, + min_thresh0_addr, + (unsigned short)clk_mon_cfg->min_thresh); + + status |= cs4224_reg_set_channel( + slice, + min_thresh1_addr, + (clk_mon_cfg->min_thresh >> 16)); + + status |= cs4224_reg_set_channel( + slice, + max_thresh0_addr, + (unsigned short)clk_mon_cfg->max_thresh); + + status |= cs4224_reg_set_channel( + slice, + max_thresh1_addr, + (clk_mon_cfg->max_thresh >> 16)); + + data = 0x0100; /* config */ + if (clk_mon_cfg->go) + data |= CS_BIT1; /* go */ + + if (clk_mon_cfg->free_run) + data |= CS_BIT4; /* free-run */ + + status |= cs4224_reg_set_channel(slice, ctrl_addr, data); + data &= ~CS_BIT1; /* clear go */ + status |= cs4224_reg_set_channel(slice, ctrl_addr, data); + + return status; +} + +int cs4224_pp_clock_monitor_freq_fixp( + unsigned int slice, enum e_cs4224_cfg_sides_t side, + struct cs4224_pp_clk_mon_cfg_t *pp_clk_mon_cfg, + unsigned int ref_clk_rate, + unsigned short *freq) +{ + int status = CS_OK; + signed char i = 0; + unsigned short data = 0; + unsigned int count = 0; + unsigned int ticks_per_sec = 0; + unsigned short des_freq = *freq; + unsigned char stalled = CS_FALSE; + unsigned short power_down = 0; + + unsigned short status_addr; + unsigned short count0_addr; + unsigned short count1_addr; + unsigned short power_down_addr; + enum e_cs4224_mseq_id mseq_id; + + status |= cs4224_get_cfg_side(slice, &side); + + if (side == CS4224_CFG_HOST_SIDE) { + status_addr = CS4224_PP_CLKMON_EGR_STATUS; + count0_addr = CS4224_PP_CLKMON_EGR_COUNT0; + count1_addr = CS4224_PP_CLKMON_EGR_COUNT1; + power_down_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB; + mseq_id = CS4224_DPLX_HOST_MSEQ; + } else { + status_addr = CS4224_PP_CLKMON_ING_STATUS; + count0_addr = CS4224_PP_CLKMON_ING_COUNT0; + count1_addr = CS4224_PP_CLKMON_ING_COUNT1; + power_down_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB; + mseq_id = CS4224_DPLX_LINE_MSEQ; + } + + status |= cs4224_query_mseq_is_stalled(slice, mseq_id, &stalled); + if (!stalled) + cs4224_mseq_stall(slice, mseq_id, CS_TRUE); + + status |= cs4224_reg_get_channel(slice, power_down_addr, &power_down); + if (power_down != 0x0000) { + status |= cs4224_reg_set_channel(slice, power_down_addr, 0x1f); + status |= cs4224_reg_set_channel(slice, power_down_addr, 0x00); + } + + /* setup clock mon */ + pp_clk_mon_cfg->clksel_divider = CS4224_CLK_MON_DIV1; + pp_clk_mon_cfg->go = CS_TRUE; + pp_clk_mon_cfg->free_run = CS_TRUE; + pp_clk_mon_cfg->duration = 0x4000; + + status |= cs4224_pp_clock_monitor(slice, side, pp_clk_mon_cfg); + + for (i = 10; i > 0; i--) { + status |= cs4224_reg_get_channel(slice, status_addr, &data); + if (data & 0x1) + break; + CS_UDELAY(200); /* 1/156.25MHz * 0x4000 = 154us */ + } + if (i <= 0) { + CS_TRACE(("ERROR: clock monitor count never completed\n")); + status |= CS_ERROR; + return status; + } + + status |= cs4224_reg_get_channel(slice, count1_addr, &data); + count = (unsigned int)data << 16; + status |= cs4224_reg_get_channel(slice, count0_addr, &data); + count |= (unsigned int)data; + + /* freq = count * ref * div / duration */ + /* control the truncating; don't loose precision unintentionally */ + ticks_per_sec = ((long long int)count * ref_clk_rate) / 1000; + + *freq = (ticks_per_sec * 1) / 0x4000; + + if (des_freq != 0) { + unsigned short temp = des_freq * 9; + + if ((*freq * 10) < temp) + CS_TRACE(("WARNING: freq < des_freq -10%%: %u < %u\n", + *freq, temp / 9)); + temp = des_freq * 11; + if ((*freq * 10) > temp) + CS_TRACE(("WARNING: freq > des_freq +10%%: %u > %u\n", + *freq, temp / 11)); + } + + if (power_down != 0x0000) + status |= cs4224_reg_set_channel(slice, power_down_addr, + power_down); + + if (!stalled) + cs4224_mseq_stall(slice, mseq_id, CS_FALSE); + + return status; +} + +int cs4224_init_ac_decoupling_caps(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short reg_data; + + if ((cs4224_is_hw_simplex(slice) && + cs4224_line_rx_to_host_tx_dir(slice)) || + (cs4224_is_hw_duplex(slice))) { + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4, + ®_data); + + if (rules->enable_ac_decoupling_caps) + reg_data |= 0x0080; + else + reg_data &= ~0x0080; + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4, + reg_data); + } + if ((cs4224_is_hw_simplex(slice) && + !cs4224_line_rx_to_host_tx_dir(slice)) || + (cs4224_is_hw_duplex(slice))) { + status |= cs4224_reg_get_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG4, + ®_data); + + if (rules->enable_ac_decoupling_caps) + reg_data |= 0x0080; + else + reg_data &= ~0x0080; + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG4, + reg_data); + } + + return status; +} + +int cs4224_rules_set_default(enum e_cs4224_target_application application, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + rules->application = application; + + rules->rx_if.splx_eq.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->rx_if.splx_edc_mode = CS_HSIO_EDC_MODE_SR; + + rules->tx_if.splx_driver.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->tx_if.splx_disable = CS_FALSE; + + rules->rx_if.dplx_line_eq.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->rx_if.dplx_host_eq.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->rx_if.dplx_line_edc_mode = CS_HSIO_EDC_MODE_SR; + rules->rx_if.dplx_host_edc_mode = CS_HSIO_EDC_MODE_SR; + + rules->tx_if.dplx_line_driver.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->tx_if.dplx_host_driver.traceloss = CS_HSIO_TRACE_LOSS_2dB; + rules->tx_if.dplx_line_disable = CS_FALSE; + rules->tx_if.dplx_host_disable = CS_FALSE; + + rules->unsquelch_driver = CS_TRUE; + rules->tx_auto_squelch = CS_FALSE; + rules->enable_ac_decoupling_caps = CS_TRUE; + rules->enable_power_savings = CS_TRUE; + rules->enable_die_broadcast = CS_TRUE; + + /* By default leave debugging info disabled. Customers + * can turn this on if desired. + */ + rules->show_debug_info = CS_TRUE; + + /* By default turn off the ability of the microsequencer to + * perform a dynamic reconfig + */ + rules->mseq_dyn_reconfig = CS_FALSE; + + switch (application) { + case CS4224_TARGET_APPLICATION_OC12: + case CS4224_TARGET_APPLICATION_1G: + case CS4224_TARGET_APPLICATION_5G: + case CS4224_TARGET_APPLICATION_7p5G: + case CS4224_TARGET_APPLICATION_8G: + case CS4224_TARGET_APPLICATION_8p5G: + case CS4224_TARGET_APPLICATION_15G: + case CS4224_TARGET_APPLICATION_16G_FC: + case CS4224_TARGET_APPLICATION_10G_FC: + case CS4224_TARGET_APPLICATION_8G_FC: + case CS4224_TARGET_APPLICATION_4G_FC: + case CS4224_TARGET_APPLICATION_2G_FC: + case CS4224_TARGET_APPLICATION_1G_FC: + case CS4224_TARGET_APPLICATION_10G_KR: + case CS4224_TARGET_APPLICATION_40G_KR: + case CS4224_TARGET_APPLICATION_KRAN: + case CS4224_TARGET_APPLICATION_FCAN: + status = CS_ERROR; + printf("Application not yet supported\n"); + break; + case CS4224_TARGET_APPLICATION_10G: + /* 156.25MHz ref clock, 10.3125GHz */ + rules->ref_clk_rate = CS4224_REF_CLK_156p25; + + rules->clkdiv.enable = CS_TRUE; + rules->clkdiv.fastdiv = 0x3; /* div by 40 (default) */ + rules->clkdiv.ddiv = CS4224_DDIV_DIV1; + rules->clkdiv.rdiv = CS4224_RDIV_DIV66; + + break; + + default: { + CS_TRACE(("ERROR: Invalid application=%d\n", application)); + status = CS_ERROR; + break; + } + } + + return status; +} + +int cs4224_mseq_squelch_ctrl(unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned char enable) +{ + int status = CS_OK; + unsigned short offset = 0x0; + unsigned short spare12; + enum e_cs4224_mseq_id mate_mseq; + unsigned char stalled = CS_FALSE; + unsigned short data; + + status |= cs4224_get_cfg_side(slice, (enum e_cs4224_cfg_sides_t *)&dir); + if (status != CS_OK) + return status; + + if (dir == CS4224_LINE_RX_TO_HOST_TX_DIR) { + offset = 0x0; + mate_mseq = CS4224_DPLX_HOST_MSEQ; + } else { + offset = CS4224_LINE_TO_HOST_OFFSET; + mate_mseq = CS4224_DPLX_LINE_MSEQ; + } + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + offset, + &spare12); + + if (enable) { + if (cs4224_is_hw_simplex(slice)) { + status |= cs4224_query_mseq_is_stalled(slice, mate_mseq, + &stalled); + if (stalled) + status |= cs4224_mseq_stall(slice, mate_mseq, + CS_FALSE); + } + if (CS_IF_CLR(spare12, CS_BIT2)) { + /* enable MSEQ control of squelch */ + spare12 = CS_SET(spare12, CS_BIT2); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + + offset, + spare12); + } + } else { + if (spare12 & CS_BIT2) { + /* disable MSEQ control of squelch */ + spare12 = CS_CLR(spare12, CS_BIT2); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + + offset, + spare12); + + /* delay for mseq to catch up */ + CS_UDELAY(30); + + /* disable this interfaces mail-out */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB + + offset, + 0); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_MSB + + offset, + 0); + /* disable the connected interface's mail in */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_MSB - + offset, + &data); + data = CS_CLR(data, CS_BIT15 | CS_BIT12); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_MSB - + offset, + data); + } + } + + return status; +} + +int cs4224_send_squelch_request(unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned char squelch) +{ + int status = CS_OK; + unsigned short offset = 0; + + status |= cs4224_get_cfg_side(slice, (enum e_cs4224_cfg_sides_t *)&dir); + if (status != CS_OK) + return status; + + if (dir == CS4224_LINE_RX_TO_HOST_TX_DIR) + offset = 0; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + if (squelch) + /* enable squelch */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB + offset, + 0x8000); + else + /* disable squelch */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB + offset, + 0x0000); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_MSB + offset, + 0x9000); + + return status; +} + +int cs4224_squelch_driver(unsigned int slice, enum e_cs4224_cfg_sides_t side, + unsigned char squelch) +{ + int status = CS_OK; + unsigned short squelch_addr; + unsigned short ctrla_addr; + unsigned short ctrla_storage_addr; + unsigned short spare12_addr; + unsigned short ctrla_storage_dft; + unsigned short ctrla; + unsigned short spare12; + + /* Cannot use cs4224_get_cfg_side, that is for the Rx side, not Tx */ + if (cs4224_is_hw_simplex(slice) && (side == CS4224_CFG_SIMPLEX)) { + if (cs4224_line_rx_to_host_tx_dir(slice)) + side = CS4224_CFG_HOST_SIDE; + else + side = CS4224_CFG_LINE_SIDE; + } else { + if (side == CS4224_CFG_SIMPLEX) { + CS_TRACE(("ERROR: Duplex slice, not simplex\n")); + status |= CS_ERROR; + } + } + + if (side == CS4224_CFG_LINE_SIDE) { + squelch_addr = CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH; + ctrla_addr = CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA; + ctrla_storage_addr = + CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0; + spare12_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_LSB; + } else { + squelch_addr = CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH; + ctrla_addr = CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA; + ctrla_storage_addr = + CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0; + spare12_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB; + } + ctrla_storage_dft = + CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0_dft; + + status |= cs4224_reg_get_channel(slice, spare12_addr, &spare12); + if (spare12 & 4) { + CS_TRACE(("ERROR: Squelching controlled by microsequencer,")); + CS_TRACE(("call cs4224_mseq_squelch_ctrl to disable auto")); + CS_TRACE((" Tx squelch control on slice, or use ")); + CS_TRACE(("cs4224_send_squelch_request instead.\n")); + return CS_ERROR; + } + + if (squelch) { + /* enable squelch */ + + status |= cs4224_reg_get_channel(slice, ctrla_addr, &ctrla); + if (ctrla != 0x0000) { + /* save then clear ctrla */ + status |= cs4224_reg_set_channel( + slice, ctrla_storage_addr, ctrla); + status |= cs4224_reg_set_channel(slice, ctrla_addr, + 0x0000); + } + status |= cs4224_reg_set_channel(slice, squelch_addr, 0x0001); + } else { + /* disable squelch */ + + status |= cs4224_reg_get_channel(slice, ctrla_storage_addr, + &ctrla); + if (ctrla != ctrla_storage_dft) { + /* restore cltra */ + status |= cs4224_reg_set_channel(slice, ctrla_addr, + ctrla); + /* set cltra storage back to 0xcccc (default) */ + status |= cs4224_reg_set_channel( + slice, ctrla_storage_addr, ctrla_storage_dft); + } + status |= cs4224_reg_set_channel(slice, squelch_addr, 0x0000); + } + + return status; +} + +/* This method performs a hard reset of a single die. See the + * header file for details + */ +int cs4224_hard_reset_die(unsigned int die) +{ + int status = CS_OK; + unsigned int stride = 0; + unsigned short data = 0x0; + + /* Wait for EEPROM download (which will be running after reset) */ + status |= cs4224_wait_for_eeprom_finished(die, 2500, 1); + + cs4224_lock(die); + + /* Fix the MDIO_CONFIG register so accesses to MSEQ registers + * don't time out (bug 35875) + */ + if (cs4224_reg_set(die, CS4224_GLOBAL_MDIO_CONFIG, + CS4224_GLOBAL_MDIO_CONFIG_pref) != CS_OK) { + /* If there is something wrong with the comms then quit */ + CS_TRACE(("ERROR: Something wrong with reg get/set methods\n")); + return CS_ERROR; + } + + /* Blindly stall all the mseqs */ + for (stride = 0; stride < 0x4000; stride += 0x1000) { + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + stride, + 0x8004); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + stride, + 0x0008); + status |= cs4224_reg_set( + die, CS4224_PP_HOST_HOSTMISC_MSEQCLKCTRL + stride, + 0x8004); + status |= cs4224_reg_set( + die, CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS + stride, + 0x0008); + } + + /* Use broadcast to write to all the ports at once, + * which can't be used to stall the mseqs + */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + { + /* Reset all port-pairs (PP) on the die */ + status |= cs4224_reg_set(die, CS4224_PP_LINE_LINEMISC_CLKEN, + 0xFFFF); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x0000); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_SOFT_RESET, 0x0001); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG, 0x0007); + /* Fix common_tx_sr default (ACJTAG) (bug 37448) */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_SOFT_RESET, 0x0000); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG, 0x0000); + status |= cs4224_reg_set(die, CS4224_PP_LINE_LINEMISC_CLKEN, + 0x0000); + } + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + +#ifndef CS_DONT_USE_MPIF_SOFT_RESET + /* Reset a die of the ASIC. This write is self clearing */ + cs4224_reg_set(die, CS4224_GLOBAL_MPIF_SOFT_RESET, 0xDEAD); +#endif + + /* Wait for the EEPROM to finish downloading the die */ + status |= cs4224_wait_for_eeprom_finished(die, 2500, 1); + + /* Squelch all transmitters out of reset */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH, 0x1); + + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + + if (status == CS_OK) { + /* if everything worked, then set the scratch to say this die + * was successfully reset + */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + status |= cs4224_reg_set(die, CS4224_GLOBAL_SCRATCH6, + CS_SET(data, CS_BIT1)); + } + + cs4224_unlock(die); + + /* reset the API static-state */ + cs4224_reset_die_static_state(die); + + return status; +} + +/* This method performs a hard reset on the K2 package. See + * the header file for details + */ +int cs4224_hard_reset(unsigned int slice) +{ + int status = CS_OK; + unsigned int die = slice & 0xFFFFFF00; + + /* reset die 0, which is always present */ + status |= cs4224_hard_reset_die(die); + + if (CS4224_MAX_NUM_DIES(die) > 1) { + /* reset die 1, which is chip-dependent */ + status |= cs4224_hard_reset_die(die | 0x1); + } + + return status; +} + +int cs4224_mseq_enable_power_savings(unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char enable) +{ + int status = CS_OK; + unsigned short reg_data = 0; + unsigned short spare12 = 0; + unsigned short clkdiv_ctrl = 0; + enum e_cs4224_edc_mode edc_mode = CS_HSIO_EDC_MODE_DISABLED; + unsigned char stalled; + unsigned short offset = 0; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + offset = 0; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + /* get the edc mode */ + status |= cs4224_query_edc_mode(slice, mseq_id, &edc_mode); + /* see if the mseq is stalled */ + status |= cs4224_query_mseq_is_stalled(slice, mseq_id, &stalled); + /* check the power-savings state */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + offset, + &spare12); + + if (enable) { + /* ring oscillator can't have power savings enabled; allow one + * to turn it off but not on + */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG + offset, + ®_data); + if (reg_data & CS_BIT7) + return status; + + /* clkdiv helps us figure out the config of this Rx intf */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL + offset, + &clkdiv_ctrl); + + /* if the mseq is stalled or in SR mode then you need to control + * power savings manually + */ + if (stalled || (edc_mode == CS_HSIO_EDC_MODE_SR)) { + /* if the fracn is needed we need to make sure we don't + * turn it off! + */ + if ((clkdiv_ctrl & 0x000F) == 0x0009) + /*fracn used*/ + reg_data = 0x1e7; + else + /*fracn not used*/ + reg_data = 0x1f7; + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + + offset, + reg_data); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB + + offset, + 0x0); + } + + /* power savings enable bit */ + spare12 |= CS_BIT1; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + offset, + spare12); + } else { /* disable */ + /* if the mseq is stalled or in SR mode then you need to control + * power savings manually + */ + if (stalled || (edc_mode == CS_HSIO_EDC_MODE_SR)) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + + offset, + 0x65); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB + + offset, + 0x0); + } + + /* power savings bit */ + spare12 = CS_CLR(spare12, CS_BIT1); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + offset, + spare12); + + /* Delay while the mseq changes the power down reg */ + CS_UDELAY(50); + } + + return status; +} + +int cs4224_query_mseq_power_savings(unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char *enabled) +{ + int status = CS_OK; + unsigned short reg_data = 0; + unsigned int spare12_addr; + + *enabled = CS_FALSE; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + spare12_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB; + else + spare12_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_LSB; + + status |= cs4224_reg_get_channel(slice, spare12_addr, ®_data); + + if ((reg_data & 0x2) == 0x2) + *enabled = CS_TRUE; + else + *enabled = CS_FALSE; + + return status; +} + +int cs4224_query_mseq_is_stalled(unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char *stalled) +{ + int status = CS_OK; + unsigned short options_shadow_addr; + unsigned short data; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + options_shadow_addr = + CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW; + else + options_shadow_addr = + CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_SHADOW; + + status |= cs4224_reg_get_channel(slice, options_shadow_addr, &data); + + if (data == 0xbada) { + /* some kind of read issue with power savings */ + CS_TRACE(("ERROR: SDS_DSP_MSEQ_OPTIONS_SHADOW == 0xbada\n")); + return CS_ERROR; + } + + if ((data & 0x8) == 0x8) + *stalled = CS_TRUE; + else + *stalled = CS_FALSE; + + return status; +} + +int cs4224_clear_mailbox(unsigned int slice, enum e_cs4224_mseq_id mseq_id) +{ + int status = CS_OK; + unsigned short mailbox_in_addr, mailbox_out_addr; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) { + mailbox_in_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_LSB; + mailbox_out_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB; + } else { + mailbox_in_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_LSB; + mailbox_out_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_LSB; + } + + cs4224_lock(slice); + + /* clear the out mail box queues in case they have a squelch/un-squelch + * request in them + */ + status |= cs4224_reg_set_channel(slice, mailbox_out_addr, 0); + status |= cs4224_reg_set_channel(slice, mailbox_out_addr + 1, 0); + /* clear the in mail box queue request */ + status |= cs4224_reg_set_channel(slice, mailbox_in_addr, 0); + status |= cs4224_reg_set_channel(slice, mailbox_in_addr + 1, 0); + + cs4224_unlock(slice); + + return status; +} + +void cs4224_mseq_stall_set_delay(int us) +{ + g_cs4224_mseq_stall_delay_us = us; +} + +int cs4224_mseq_stall_get_delay(void) +{ + return g_cs4224_mseq_stall_delay_us; +} + +int cs4224_mseq_stall(unsigned int slice, enum e_cs4224_mseq_id mseq_id, + unsigned char stall) +{ + int status = CS_OK; + unsigned short reg_offset = 0x0; + unsigned short reg_data = 0; + unsigned short bank, spare12 = 0; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + reg_offset = 0x0; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + reg_offset, + &spare12); + + if (stall) { + /* this enables the clocks even if the mseq is powered-down */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + reg_offset, + 0x8004); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + reg_offset, + 0x0008); + + /* Delay after stalling the microsequencer to ensure any timers + * have expired + */ + CS_UDELAY(cs4224_mseq_stall_get_delay()); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_ENABLE + reg_offset, + 0x0000); + + /* When stalling the microsequencer need to revert MSEQ_SERDES + * to it's default value or it may get set temporarily to 0x3b + * by the slicer calibration + */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + ®_data); + reg_data &= ~0xf; /* don't overwrite custom filtr */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + reg_data); + } else { /* un-stall */ + /* clear the SNR control reg, see youtrack cs-170 */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_CTRL + reg_offset, + 0x0000); + + /* save the current bank */ + cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + &bank); + + /* force a bank change to trigger the clearing of the + * micro-sequencer power-down timer. See MSEQBANKSWAP reg for + * details + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0007); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0000); + + /* if slice configured for FC-AN. Note that KR-AN does not use + * this stall/un-stall method + */ + if (spare12 & 0x0020) { + if (mseq_id == CS4224_DPLX_LINE_MSEQ) { + /* In FC-AN mode the the LINE side bank select + * is initialized to 4 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR, + 0x0004); + } else { + /* In FC-AN mode the the HOST side bank select + * is initialized to 7 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_BANK_SELECTOR, + 0x0007); + } + } else { /* not FC-AN */ + /* Revert the bank-select in DFE mode. This will not + * work for protocol modes like KR-AN and FC-AN. + */ + if (bank == 3) { + /* In SR mode the bank select is fixed at 3. */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0003); + } else { + /* DFE modes */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0000); + } + } + + /* if the microsequencer triggered dynamic reconfig is enabled, + * then force the bank to 7 + */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB + reg_offset, + ®_data); + if (reg_data & 0x8000) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0007); + } + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + reg_offset, + 0x0004); + + /* Restore the datastore registers before un-stalling */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + 1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + 2 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + reg_offset, + 0x803c); + + /* reset the program counter and unstall */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_PC + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + reg_offset, + 0x0007); + } + + cs4224_unlock(slice); + + return status; +} + +int cs4224_mseqs_stall(struct cs4224_interface_t interfaces[], + unsigned short length, + unsigned char stall) +{ + int status = CS_OK; + unsigned short reg_data = 0; + unsigned short bank, spare12_lsb = 0; + unsigned int i = 0; + + for (i = 0; i < length; i++) { + unsigned short reg_offset = 0x0; + unsigned int slice = interfaces[i].slice; + enum e_cs4224_mseq_id mseq_id; + + /* first convert mseq_id to be either line/host, so we don't + * have to have this check in the next loop + */ + status |= cs4224_get_mseq_id(interfaces[i].slice, + &interfaces[i].mseq_id); + if (status != CS_OK) { + CS_TRACE(("ERROR: Converting interfaces\n")); + return status; + } + mseq_id = interfaces[i].mseq_id; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + reg_offset = 0x0; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + if (stall) { + /* this enables the clocks even if the microsequencer is + * powered-down + */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + + reg_offset, + 0x8004); + + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + + reg_offset, + 0x0008); + + /* rest of stall code is after the loop */ + } else { /* un-stall */ + /* If the mseq is in control of squelch, set squelch + * right off the bat because the mseq starts off in a + * non EDC converged state. + */ + status |= + cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + + reg_offset, + &spare12_lsb); + if (spare12_lsb & CS_BIT2) { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH - + reg_offset, + 0x1); /* Tx side,inverse the mseq side*/ + } + + /* save the current bank */ + status |= + cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + &bank); + + /* force a bank change to trigger the clearing of the + * micro-sequencer power-down timer. See MSEQBANKSWAP + * reg for details + */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0007); + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0000); + + /* if slice configured for FC-AN. Note that KR-AN does + * not use this stall/un-stall method + */ + if (spare12_lsb & 0x0020) { + if (mseq_id == CS4224_DPLX_LINE_MSEQ) { + /* In FC-AN mode the the LINE side bank + * select is initialized to 4 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR, + 0x0004); + } else { + /* In FC-AN mode the the HOST side bank + * select is initialized to 7 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_BANK_SELECTOR, + 0x0007); + } + } else { + /* not FC-AN: Revert the bank-select in DFE + * mode. This will not work for protocol modes + * like KR-AN and FC-AN + */ + if (bank == 3) { + /* In SR mode the bank select is fixed + * at 3. + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0003); + } else { + /* DFE modes */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0000); + } + } + + /* if the microsequencer triggered dynamic reconfig is + * enabled, then force the bank to 7 + */ + status |= + cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB + + reg_offset, + ®_data); + if (reg_data & 0x8000) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + + reg_offset, + 0x0007); + } + /* rest of unstall code after the loop */ + } + cs4224_unlock(slice); + } + + if (stall) { + /* Delay after stalling the microsequencer to ensure any timers + * have expired + */ + CS_UDELAY(100); + } + + for (i = 0; i < length; i++) { + unsigned short reg_offset = 0x0; + unsigned int slice = interfaces[i].slice; + enum e_cs4224_mseq_id mseq_id = interfaces[i].mseq_id; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + reg_offset = 0x0; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + if (stall) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_ENABLE + reg_offset, + 0x0000); + + /* When stalling the microsequencer need to revert + * MSEQ_SERDES to it's default value or it may get set + * temporarily to 0x3b by the slicer calibration + */ + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + ®_data); + reg_data &= ~0xf; /* don't overwrite custom filtr */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + reg_data); + } else { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL + + reg_offset, + 0x0004); + + /* Restore the datastore registers before un-stalling */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + 1 + + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + 2 + + reg_offset, + 0x0000); + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + + reg_offset, + 0x803c); + + /* reset the program counter and unstall */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_PC + reg_offset, + 0x0000); + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS + + reg_offset, + 0x0007); + } + cs4224_unlock(slice); + } + + return status; +} + +int cs4224_init_global_timer_fixp(unsigned int slice, unsigned int ref_clk_freq) +{ + int status = CS_OK; + unsigned int ref_clk_per; + unsigned int num_clks; + + ref_clk_per = 1000000000L / ref_clk_freq; + num_clks = 100000000L / ref_clk_per; + + cs4224_lock(slice); + + status |= cs4224_reg_set_channel( + slice, CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT0, num_clks); + status |= cs4224_reg_set_channel( + slice, CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT1, num_clks >> 16); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_init_lc_vco_tmp_thresh(unsigned int slice, + enum e_cs4224_cfg_sides_t intf) +{ + int status = CS_OK; + unsigned short offset; + + if (intf == CS4224_CFG_LINE_SIDE) + offset = 0x0000; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + /* These thresholds valid for LC VCO only */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES00 + offset, + 0x13a); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES01 + offset, + 0x127); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES02 + offset, + 0x117); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES03 + offset, + 0x0); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES04 + offset, + 0x0); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES10 + offset, + 0x13f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES11 + offset, + 0x12f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES12 + offset, + 0x127); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES13 + offset, + 0x0); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES14 + offset, + 0x0); + + return status; +} + +int cs4224_init_ro_vco_tmp_thresh(unsigned int slice, + enum e_cs4224_cfg_sides_t intf) +{ + int status = CS_OK; + unsigned short offset; + + if (intf == CS4224_CFG_LINE_SIDE) + offset = 0x0000; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + /* These thresholds valid for Ring Oscillator VCO only */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES00 + offset, + 0x018f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES01 + offset, + 0x015f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES02 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES03 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES04 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES10 + offset, + 0x018f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES11 + offset, + 0x015f); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES12 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES13 + offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES14 + offset, + 0x0000); + + return status; +} + +int cs4224_init_10g(unsigned int slice, enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short offset = 0; + + if (intf == CS4224_CFG_LINE_SIDE) + offset = 0x0000; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL2 + offset, + 0x1000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL1 + offset, + 0x0008); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_config_target_application_intf(unsigned int slice, + enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + status |= cs4224_get_cfg_side(slice, &intf); + if (status != CS_OK) + return status; + + switch (rules->application) { + case CS4224_TARGET_APPLICATION_5G: + case CS4224_TARGET_APPLICATION_7p5G: + case CS4224_TARGET_APPLICATION_8G: + case CS4224_TARGET_APPLICATION_8p5G: + case CS4224_TARGET_APPLICATION_10G_FC: + case CS4224_TARGET_APPLICATION_10G_KR: + case CS4224_TARGET_APPLICATION_40G_KR: + case CS4224_TARGET_APPLICATION_KRAN: + case CS4224_TARGET_APPLICATION_15G: + case CS4224_TARGET_APPLICATION_16G_FC: + case CS4224_TARGET_APPLICATION_8G_FC: + case CS4224_TARGET_APPLICATION_1G_FC: + case CS4224_TARGET_APPLICATION_2G_FC: + case CS4224_TARGET_APPLICATION_4G_FC: + case CS4224_TARGET_APPLICATION_FCAN: + case CS4224_TARGET_APPLICATION_OC12: + case CS4224_TARGET_APPLICATION_1G: + status = CS_ERROR; + break; + case CS4224_TARGET_APPLICATION_10G: + status |= cs4224_init_10g(slice, intf, rules); + break; + + default: + status = CS_ERROR; + break; + } + + return status; +} + +int cs4224_config_target_application(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) + status |= cs4224_config_target_application_intf( + slice, CS4224_CFG_LINE_SIDE, rules); + + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) + status |= cs4224_config_target_application_intf( + slice, CS4224_CFG_HOST_SIDE, rules); + + return status; +} + +int cs4224_pgm_reg_from_efuse(unsigned int slice, + enum e_cs4224_cfg_sides_t dir) +{ + int status = CS_OK; + unsigned short efuse_data0, efuse_data1, efuse_data2; + unsigned short cml_itune, cml_rtune; + unsigned short vco_itune; + unsigned short driver_rtune, driver_itune; + unsigned short agc_itune, agc_rtune; + unsigned short drivercml_rtune, drivercml_itune; + unsigned short reg_data, old_data; + unsigned int die = cs4224_get_die_from_slice(slice); + unsigned short reg_offset = 0x0000; + + cs4224_lock(slice); + + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_POLY_RES_CAL_DATA0, + &efuse_data0); + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_POLY_RES_CAL_DATA1, + &efuse_data1); + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_POLY_RES_CAL_DATA2, + &efuse_data2); + + if (dir == CS4224_CFG_LINE_SIDE) + reg_offset = 0; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + /* assign efuse cml_itune to + * PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE[2:0] + */ + cml_itune = efuse_data0 & 0x0070; + + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE + reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0007) | (cml_itune >> 4); + if (old_data != reg_data) { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE + + reg_offset, + reg_data); + } + + /* assign vco_itune to PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE[6:4] + * and cml_rtune to PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE[2:0] + */ + vco_itune = efuse_data0 & 0x7000; + cml_rtune = efuse_data1 & 0x7000; + + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE + reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0077) | (cml_rtune >> 12) | (vco_itune >> 8); + if (old_data != reg_data) { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE + + reg_offset, + reg_data); + } + + /* assign efuse agc_itune to + * CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2[6:4] + */ + agc_itune = efuse_data0 & 0x0007; + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2 + reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0xFF8F) | (agc_itune << 4); + if (old_data != reg_data) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2 + reg_offset, + reg_data); + } + + /* assign driver_rtune to + * CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_TUNE[10:8] and + * driver_itune to CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_TUNE[2:0] + */ + driver_rtune = efuse_data2 & 0x0070; + driver_itune = efuse_data1 & 0x0007; + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE - reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0707) | (driver_rtune << 4) + | (driver_itune >> 0); + if (old_data != reg_data) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE - reg_offset, + reg_data); + } + + /* assign drivercml_rtune to + * CS4224_PP_LINE_SDS_COMMON_STX0_DRIVERCML_TUNE[10:8] + * and drivercml_itune to + * CS4224_PP_LINE_SDS_COMMON_STX0_DRIVERCML_TUNE[2:0] + */ + drivercml_rtune = efuse_data2 & 0x0700; + drivercml_itune = efuse_data1 & 0x0070; + + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE - reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0707) | (drivercml_rtune << 0) + | (drivercml_itune >> 4); + if (old_data != reg_data) { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE - + reg_offset, + reg_data); + } + + /* assign efuse agc_itune to + * CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE[2:0] + */ + agc_rtune = efuse_data1 & 0x0700; + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE + reg_offset, + ®_data); + old_data = reg_data; + reg_data = (reg_data & ~0x0007) | (agc_rtune >> 8); + if (old_data != reg_data) + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE + reg_offset, + reg_data); + + /* the value for the dfe i/rtune should not be based on the + * E-Fuse setting + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG + reg_offset, + 0x1910); + + /* over-ride efuse data with registers */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_OVERRIDE_EN + reg_offset, + 0x0006); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_update_pre_equalizer(unsigned int slice, unsigned short reg_offset, + enum e_cs4224_trace_loss traceloss) +{ + int status = CS_OK; + unsigned short lim_eqadj; + unsigned short pass_eqadj1; + unsigned short pass_eqadj2; + + switch (traceloss) { + case CS_HSIO_TRACE_LOSS_0dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0001; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_1dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0000; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_2dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0001; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_3dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0004; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_4dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0005; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_5dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0006; + pass_eqadj2 = 0x070F; + break; + } + case CS_HSIO_TRACE_LOSS_6dB: { + lim_eqadj = 0x0100; + pass_eqadj1 = 0x0007; + pass_eqadj2 = 0x070F; + break; + } + default: { + return CS_OK; + } + } + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_MISC + reg_offset, + lim_eqadj); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ1 + reg_offset, + pass_eqadj1); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ2 + reg_offset, + pass_eqadj2); + + return status; +} + +int cs4224_save_edc_mode(unsigned int slice, unsigned short reg_offset, + enum e_cs4224_edc_mode edc_mode) +{ + int status = CS_OK; + unsigned short saved_edc_mode; + + switch (edc_mode) { + case CS_HSIO_EDC_MODE_DISABLED: + saved_edc_mode = 0; + break; + case CS_HSIO_EDC_MODE_CX1: + saved_edc_mode = 1; + break; + case CS_HSIO_EDC_MODE_SR: + saved_edc_mode = 2; + break; + case CS_HSIO_EDC_MODE_ZR: + saved_edc_mode = 3; + break; + case CS_HSIO_EDC_MODE_DWDM: + saved_edc_mode = 4; + break; + case CS_HSIO_EDC_MODE_10G_BP: + saved_edc_mode = 5; + break; + case CS_HSIO_EDC_MODE_15G_BP: + saved_edc_mode = 6; + break; + case CS_HSIO_EDC_MODE_5G_BP: + saved_edc_mode = 7; + break; + case CS_HSIO_EDC_MODE_7p5G_BP: + saved_edc_mode = 8; + break; + case CS_HSIO_EDC_MODE_8p5G_BP: + saved_edc_mode = 9; + break; + case CS_HSIO_EDC_MODE_FCAN: + saved_edc_mode = 10; + break; + case CS_HSIO_EDC_MODE_15G_BP_27dB: + saved_edc_mode = 11; + break; + case CS_HSIO_EDC_MODE_SMLRM: + saved_edc_mode = 12; + break; + + default: + CS_TRACE(("ERROR: %s: slice = %d, ", __func__, slice)); + CS_TRACE(("unknown EDC mode = %d\n", edc_mode)); + status |= CS_ERROR; + saved_edc_mode = 1; + break; + } + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE2PRELOAD0 + reg_offset, + saved_edc_mode); + + return status; +} + +int cs4224_query_edc_mode(unsigned int slice, enum e_cs4224_mseq_id mseq_id, + enum e_cs4224_edc_mode *edc_mode) +{ + int status = CS_OK; + unsigned short saved_edc_mode = 0; + /* offset used for accessing host addresses over line ones */ + unsigned short reg_offset = 0x0000; + + /* init to disabled */ + *edc_mode = CS_HSIO_EDC_MODE_DISABLED; + + status |= cs4224_get_mseq_id(slice, &mseq_id); + if (status != CS_OK) + return status; + + if (mseq_id == CS4224_DPLX_LINE_MSEQ) + reg_offset = 0x0000; + else + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + status |= cs4224_reg_get_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE2PRELOAD0 + reg_offset, + &saved_edc_mode); + + switch (saved_edc_mode) { + /* Note, edc mode enum uses too many bits, hense the custom mapping here + * If the EDC version has never been initialized then the preloader will + * have the h/w reset value of 0xCCCC. Report this as EDC disabled + */ + case 0: + case 0xCCCC: + *edc_mode = CS_HSIO_EDC_MODE_DISABLED; + break; + case 1: + *edc_mode = CS_HSIO_EDC_MODE_CX1; + break; + case 2: + *edc_mode = CS_HSIO_EDC_MODE_SR; + break; + case 3: + *edc_mode = CS_HSIO_EDC_MODE_ZR; + break; + case 4: + *edc_mode = CS_HSIO_EDC_MODE_DWDM; + break; + case 5: + *edc_mode = CS_HSIO_EDC_MODE_10G_BP; + break; + case 6: + *edc_mode = CS_HSIO_EDC_MODE_15G_BP; + break; + case 7: + *edc_mode = CS_HSIO_EDC_MODE_5G_BP; + break; + case 8: + *edc_mode = CS_HSIO_EDC_MODE_7p5G_BP; + break; + case 9: + *edc_mode = CS_HSIO_EDC_MODE_8p5G_BP; + break; + case 10: + *edc_mode = CS_HSIO_EDC_MODE_FCAN; + break; + case 11: + *edc_mode = CS_HSIO_EDC_MODE_15G_BP_27dB; + break; + case 12: + *edc_mode = CS_HSIO_EDC_MODE_SMLRM; + break; + + default: + CS_TRACE(("ERROR: slice = %x, unknown saved EDC mode = %x\n", + slice, saved_edc_mode)); + status |= CS_ERROR; + break; + } + return status; +} + +int cs4224_init_edc_mode_intf(unsigned int slice, + struct cs4224_rules_t *rules, + enum e_cs4224_mseq_id intf) +{ + int status = CS_OK; + enum e_cs4224_edc_mode mode; + enum e_cs4224_trace_loss traceloss; + /* offset used for accessing host addresses over line ones */ + unsigned short reg_offset = 0x0000; + /* flags for fc or 8g apps */ + unsigned short reg_data = 0x0000; + + cs4224_lock(slice); + + if (cs4224_is_hw_simplex(slice)) { + mode = rules->rx_if.splx_edc_mode; + traceloss = rules->rx_if.splx_eq.traceloss; + + if (cs4224_line_rx_to_host_tx_dir(slice)) { + intf = CS4224_DPLX_LINE_MSEQ; + reg_offset = 0x0000; + } else { + intf = CS4224_DPLX_HOST_MSEQ; + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + } + } else if (cs4224_is_hw_duplex(slice)) { + if (intf == CS4224_DPLX_LINE_MSEQ) { + reg_offset = 0x0000; + + mode = rules->rx_if.dplx_line_edc_mode; + traceloss = rules->rx_if.dplx_line_eq.traceloss; + } else if (intf == CS4224_DPLX_HOST_MSEQ) { + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + + mode = rules->rx_if.dplx_host_edc_mode; + traceloss = rules->rx_if.dplx_host_eq.traceloss; + } else { + CS_TRACE(("ERROR: Invalid interface. intf=%d\n", intf)); + return CS_ERROR; + } + } else { + /* error in the API checks for SKU... */ + CS_TRACE(("ERROR: unknown hardware id\n")); + return CS_ERROR; + } + + /* reset reset count */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_MSB + reg_offset, + 0x0000); + + /* Reset MSEQ datastore register between mode switches */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + reg_offset, + 0x803c); + + /* function number */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + reg_offset, + 0x800E); + + /* Reset some MSEQ registers to defaults between mode switches + * (may be overwritten below) + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4 + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_LSB + reg_offset, + 0x3000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES + reg_offset, + CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_RESOLUTION + reg_offset, + 0x0001); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_LSB + reg_offset, + 0x0008); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_BIAS1 + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_BIAS1_dft); + + status |= cs4224_save_edc_mode(slice, reg_offset, mode); + + switch (mode) { + case CS_HSIO_EDC_MODE_SR: { + /* only set the SR bit, everything else is off by default */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + reg_offset, + 0x0001); + + /* set spare1[0] = 1 to speed up locking in SR mode */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_LSB + reg_offset, + 0x0001); + + /* power down is set differently from the scripts since spare12 + * is also different + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x0065); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB + reg_offset, + 0x0000); + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0003); + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x0099); + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1 + reg_offset, + 0x0004); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG + reg_offset, + 0x0441); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB + reg_offset, + 0xDFFF); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB + reg_offset, + 0x000D); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL + reg_offset, + 0x001E); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_OVERRIDE_EN + reg_offset, + 0x0000); + + /* function number set to 1 for SR only */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0 + reg_offset, + 0x0001); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR + reg_offset, + 0x800E); + + /* apply pre-equalizer settings */ + status |= cs4224_update_pre_equalizer(slice, reg_offset, + traceloss); + + break; + } + + case CS_HSIO_EDC_MODE_CX1: + case CS_HSIO_EDC_MODE_SMLRM: { + /* differs from script, don't enable power savings or + * auto squelch by default + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB + reg_offset, + 0x0B00); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB + reg_offset, + 0x0C09); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x001F); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x0099); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1 + reg_offset, + 0x0005); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB + reg_offset, + 0x8F00); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB + reg_offset, + 0x000c); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ1 + reg_offset, + 0x0008); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ2 + reg_offset, + 0x000B); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_LSB + reg_offset, + 0x00FF); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_MSB + reg_offset, + 0x0030); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_LSB + reg_offset, + 0x000F); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_LSB + reg_offset, + 0x2350); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_MSB + reg_offset, + 0x1650); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_MSB + reg_offset, + 0x07FF); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_LSB + reg_offset, + 0xFFFE); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_LSB + reg_offset, + 0x0010); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_MSB + reg_offset, + 0x0030); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_FLOAT + reg_offset, + 0x8001); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_LSB + reg_offset, + 0x001D); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_MSB + reg_offset, + 0x000A); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_LSB + reg_offset, + 0x3000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_MSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4 + reg_offset, + 0x85f0); + + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_LSB + reg_offset, + 0x000A); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE0_1 + reg_offset, + 0x00F0); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE1_1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE2_1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE3_1 + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_IC_DFE4_1 + reg_offset, + 0x0000); + + /* Read efuse data (POLY_RES_CAL_DATAx) and configure + * itune/rtune settings + */ + if (intf == CS4224_DPLX_LINE_MSEQ) + status |= cs4224_pgm_reg_from_efuse( + slice, CS4224_CFG_LINE_SIDE); + else + status |= cs4224_pgm_reg_from_efuse( + slice, CS4224_CFG_HOST_SIDE); + + if (mode == CS_HSIO_EDC_MODE_CX1) { + /* the following sets the data slicer offset: + * 0x80 for CX1, 0x90 for ZR, DWDM TBD + */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_SLICER + + reg_offset, + 0x0080); + /* max PHASE_SELECT+1 */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB + + reg_offset, + 0x0023); + } else { + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_SLICER + + reg_offset, + 0x0040); + /* max PHASE_SELECT+1 */ + status |= + cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB + + reg_offset, + 0x0020); + } + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2 + reg_offset, + 0x0000); + + break; + } + + case CS_HSIO_EDC_MODE_DWDM: + case CS_HSIO_EDC_MODE_ZR: + case CS_HSIO_EDC_MODE_10G_BP: + case CS_HSIO_EDC_MODE_15G_BP: + case CS_HSIO_EDC_MODE_15G_BP_27dB: + case CS_HSIO_EDC_MODE_5G_BP: + case CS_HSIO_EDC_MODE_7p5G_BP: + case CS_HSIO_EDC_MODE_8p5G_BP: + printf("EDC Mode not supported\n"); + break; + case CS_HSIO_EDC_MODE_DISABLED: { + /* un-rail the driver charge pump current */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x0099); + + /* power everything up */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x001f); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x0000); + + /* un-squelch the driver */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH - reg_offset, + 0x0000); + + /* apply pre-equalizer settings */ + status |= cs4224_update_pre_equalizer(slice, reg_offset, + traceloss); + + break; + } + default: { + status |= cs4224_save_edc_mode(slice, reg_offset, + CS_HSIO_EDC_MODE_DISABLED); + + CS_TRACE( + ("ERROR: Invalid application mode %d.\n", mode)); + status |= CS_ERROR; + return status; + } + } + + /* if the ring oscillator VCO is used, override some of these values */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG + reg_offset, + ®_data); + if (reg_data & CS_BIT7) { + /* the ring oscillator requires the charge pump = 0x44 */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x0044); + + /* when using the ring oscillator, override srx_cml_rtune=0, + * srx_vco_itune=2 and srx_cml_itune=0 + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE + reg_offset, + 0x0020); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE + reg_offset, + 0); + } + + cs4224_unlock(slice); + + return status; +} + +int cs4224_init_edc_mode_set(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (cs4224_is_hw_simplex(slice)) { + status |= cs4224_init_edc_mode_intf(slice, rules, + CS4224_SPLX_MSEQ); + } else if (cs4224_is_hw_duplex(slice)) { + if (rules->application != CS4224_TARGET_APPLICATION_FCAN) { + /* the FC-AN ucode configures the line side DFE mode, + * don't do it here... + */ + status |= cs4224_init_edc_mode_intf( + slice, rules, CS4224_DPLX_LINE_MSEQ); + } + status |= cs4224_init_edc_mode_intf(slice, rules, + CS4224_DPLX_HOST_MSEQ); + } else { + /* error in the API checks for SKU... */ + CS_TRACE(("ERROR: init_edc_mode_set: unknown hardware id")); + return CS_ERROR; + } + + return status; +} + +unsigned int cs4224_query_vco_rate(const struct cs4224_rules_t *rules) +{ + /* ref_clk_rate is in KHz */ + unsigned int ref_clk_rate = 0; + /* rdiv from clkdiv rules */ + unsigned int rdiv = 0; + /* calculated (approx) vco rate */ + unsigned int vco_rate = 0; + +#if defined(CS_HAS_FLOATING_POINT) + /* if we're using floating point then the ref_clk is in MHz, + * multiply up to get KHz and scrap the decimal + */ + ref_clk_rate = rules->ref_clk_rate * 1000; +#else + /* if we're not using floating point, then ref_clk_rate is in KHz */ + ref_clk_rate = rules->ref_clk_rate; +#endif + + /* decode clkdiv.rdiv for use in the calc */ + switch (rules->clkdiv.rdiv) { + case CS4224_RDIV_DIV64: + rdiv = 64; + break; + case CS4224_RDIV_DIV66: + rdiv = 66; + break; + case CS4224_RDIV_DIV80: + rdiv = 80; + break; + case CS4224_RDIV_DIV100: + rdiv = 100; + break; + case CS4224_RDIV_DIV128: + rdiv = 128; + break; + default: + /* doesn't matter,we might be out of range or using the FRACn */ + rdiv = 0; + break; + } + + if (rules->clkdiv.enable) { + /* we're just trying to find the VCO rate, not the data-rate, + * so ignore ddiv + */ + vco_rate = ref_clk_rate * rdiv; + } + + /* if using the clkdiv (for ddiv) AND the fracn, then this if statement + * must come last + */ + if (rules->fracdiv.enable) { + unsigned long long frac_part = + (unsigned long long)(ref_clk_rate) * + (rules->fracdiv.numerator); + /* decimate the 'fractional' part, left with int KHz */ + frac_part = frac_part >> 21; + vco_rate = (ref_clk_rate * 8 * rules->fracdiv.divisor) + + (unsigned int)frac_part; + } + + return vco_rate; +} + +unsigned int cs4224_query_data_rate(const struct cs4224_rules_t *rules) +{ + unsigned int vco_rate = cs4224_query_vco_rate(rules); + unsigned int data_rate = vco_rate; + + if (rules->clkdiv.enable) { + switch (rules->clkdiv.ddiv) { + case CS4224_RULE_DISABLED: + /* not sure how this happened, but ignore it */ + break; + default: + /* shift by the enum, since the divide + * amount == 2**(enum) + */ + data_rate = + vco_rate >> (unsigned short)(rules->clkdiv.ddiv); + break; + } + } + + return data_rate; +} + +unsigned char cs4224_need_low_lc_vco(const struct cs4224_rules_t *rules) +{ + unsigned int vco_rate = cs4224_query_vco_rate(rules); + + /* the 'real' range is 11.3G to 12.5G, but we'll fudge it a bit in case + * our fracn calcs have some rounding errors + */ + if ((vco_rate >= 11280000) && (vco_rate <= 12520000)) + return CS_TRUE; + + return CS_FALSE; +} + +int cs4224_force_low_lc_vco_intf(unsigned int slice, + enum e_cs4224_datapath_dir_t intf, + unsigned char force_enable) +{ + int status = CS_OK; + unsigned short offset = 0; + + if (intf == CS4224_LINE_RX_TO_HOST_TX_DIR) + offset = 0; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + if (force_enable) + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI + offset, + 0x40); + else + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI + offset, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI_dft); + + return status; +} + +int cs4224_force_and_init_low_lc_vco(unsigned int slice, + unsigned char force_enable) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_force_low_lc_vco_intf( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, force_enable); + status |= cs4224_init_vco( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_CONTROL); + } + + if (cs4224_is_hw_duplex(slice) || + (!cs4224_line_rx_to_host_tx_dir(slice))) { + status |= cs4224_force_low_lc_vco_intf( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, force_enable); + status |= cs4224_init_vco( + slice, CS4224_PP_HOST_SDS_COMMON_RXVCO0_CONTROL); + } + + return status; +} + +int cs4224_force_low_lc_vco(unsigned int slice, unsigned char force_enable) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_force_low_lc_vco_intf( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, force_enable); + } + + if (cs4224_is_hw_duplex(slice) || + (!cs4224_line_rx_to_host_tx_dir(slice))) { + status |= cs4224_force_low_lc_vco_intf( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, force_enable); + } + + return status; +} + +int cs4224_init_alt_coarse_tuning_intf(unsigned int slice, + enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short reg_data = 0; + unsigned short offset = 0x0000; + /* flag to say whether we should force the low lc vco or not */ + unsigned char force_low_lc_vco = CS_FALSE; + + status |= cs4224_get_cfg_side(slice, &intf); + if (status != CS_OK) + return status; + + cs4224_lock(slice); + + if (intf == CS4224_CFG_LINE_SIDE) { + offset = 0x0000; + } else if (intf == CS4224_CFG_HOST_SIDE) { + offset = CS4224_LINE_TO_HOST_OFFSET; + } else { + CS_TRACE(("ERROR: Invalid interface. intf=%d\n", intf)); + return CS_ERROR; + } + + /* level 4d00 is approx 77 deg C */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL3 + offset, + 0x4d00); + /* level 4100 is approx 65 deg C */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL2 + offset, + 0x4100); + /* level 3900 is approx 30 deg C */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL1 + offset, + 0x3900); + /* level 2d00 is approx 0 deg C */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL0 + offset, + 0x2d00); + + /* ring oscillator config reg */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG + offset, + ®_data); + + if (reg_data & CS_BIT7) { + /* if the 8G ring oscillator VCO is used */ + status |= cs4224_init_ro_vco_tmp_thresh(slice, intf); + } else { + /* the LC VCO */ + status |= cs4224_init_lc_vco_tmp_thresh(slice, intf); + + /* determine if we need to force the low LC VCO */ + force_low_lc_vco = cs4224_need_low_lc_vco(rules); + } + + status |= cs4224_force_low_lc_vco(slice, force_low_lc_vco); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_init_alt_coarse_tuning(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_init_alt_coarse_tuning_intf( + slice, CS4224_CFG_LINE_SIDE, rules); + } + if (cs4224_is_hw_duplex(slice) || !cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_init_alt_coarse_tuning_intf( + slice, CS4224_CFG_HOST_SIDE, rules); + } + + return status; +} + +int cs4224_disable_tx_driver_if_req(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + cs4224_lock(slice); + + /* Disable the transmitters if requested */ + if (cs4224_is_hw_simplex(slice)) { + if (cs4224_line_rx_to_host_tx_dir(slice) && + (rules->tx_if.splx_disable == CS_TRUE)) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, + 0x0800); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, + 0); + } + + if (!cs4224_line_rx_to_host_tx_dir(slice) && + (rules->tx_if.splx_disable == CS_TRUE)) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, + 0x0800); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, + 0); + } + } else { /* duplex */ + if (rules->tx_if.dplx_line_disable == CS_TRUE) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, + 0x0800); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, + 0); + } + if (rules->tx_if.dplx_host_disable == CS_TRUE) { + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, + 0x0800); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, + 0); + } + } + + cs4224_unlock(slice); + + return status; +} + +int cs4224_init_driver_trace_loss_intf( + unsigned int slice, + enum e_cs4224_datapath_dir_t intf, + enum e_cs4224_trace_loss trace_loss) +{ + int status = CS_OK; + unsigned short ctrla = 0; + unsigned short ctrlb = 0; + enum e_cs4224_tx_driver_interface driver; + + if (intf == CS4224_LINE_RX_TO_HOST_TX_DIR) { + driver = CS4224_TX_HOST_INTERFACE; + } else if (intf == CS4224_HOST_RX_TO_LINE_TX_DIR) { + driver = CS4224_TX_LINE_INTERFACE; + } else { + CS_TRACE(("ERROR: intf must be line or host, not simplex\n")); + return CS_ERROR; + } + + switch (trace_loss) { + case CS_HSIO_TRACE_LOSS_0dB: + case CS_HSIO_TRACE_LOSS_1dB: { + ctrla = 0x814; + ctrlb = 0x4; + break; + } + case CS_HSIO_TRACE_LOSS_2dB: { + ctrla = 0x3810; + ctrlb = 0x5; + break; + } + case CS_HSIO_TRACE_LOSS_3dB: { + ctrla = 0x4818; + ctrlb = 0x9; + break; + } + case CS_HSIO_TRACE_LOSS_4dB: { + ctrla = 0x4818; + ctrlb = 0xb; + break; + } + case CS_HSIO_TRACE_LOSS_5dB: { + ctrla = 0x4818; + ctrlb = 0xd; + break; + } + case CS_HSIO_TRACE_LOSS_6dB: { + ctrla = 0x4818; + ctrlb = 0xe; + break; + } + case CS_HSIO_TRACE_LOSS_15dB: { + ctrla = 0x782B; + ctrlb = 0x4; + break; + } + case CS_HSIO_TRACE_LOSS_27dB: { + ctrla = 0x7828; + ctrlb = 0x80A; + break; + } + case CS_HSIO_TRACE_LOSS_CR4: { + ctrla = 0x5827; + ctrlb = 0x6; + break; + } + case CS_HSIO_TRACE_LOSS_LAB: { + ctrla = 0x0813; + ctrlb = 0x1; + break; + } + default: { + CS_TRACE(("ERROR: Unsupported traceloss setting %d\n", + trace_loss)); + return CS_ERROR; + } + } + + status |= cs4224_init_driver_settings(slice, driver, ctrla, ctrlb); + + return status; +} + +int cs4224_init_mseq_dyn_reconfig_intf(unsigned int slice, + unsigned short offset) +{ + int status = CS_OK; + unsigned short reg_data; + + /* SPARE12[30] tells the DFE mission mode code mseq_dyn_reconfig is + * being used and to back to the mseq_dyn_reconfig code once each + * mission mode loop is done. + */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB + offset, + ®_data); + reg_data |= 0x4000; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB + offset, + reg_data); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_MSB + offset, + 0x4000); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_MSB + offset, + 0x4000); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB + offset, + 0x801e); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_MSB + offset, 0x0d80); + + return status; +} + +int cs4224_init_mseq_dyn_reconfig(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short reg_data; + + if ((rules->mseq_dyn_reconfig == CS_TRUE) && + (rules->application != CS4224_TARGET_APPLICATION_KRAN) && + (rules->application != CS4224_TARGET_APPLICATION_FCAN)) { + /* The mseq_dyn_reconfig feature is not compatible with + * the FC microcode + */ + status |= cs4224_reg_get_channel( + slice, CS4224_GLOBAL_UCODE_VERSION_KR, ®_data); + if (reg_data == 0) { + CS_TRACE(("ERROR: mseq_dyn_reconfig requires KR\n")); + return CS_ERROR; + } + + status |= cs4224_init_mseq_dyn_reconfig_intf(slice, 0); + status |= cs4224_init_mseq_dyn_reconfig_intf( + slice, CS4224_LINE_TO_HOST_OFFSET); + } + + return status; +} + +int cs4224_init_driver_trace_loss(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + enum e_cs4224_trace_loss host_traceloss, line_traceloss; + + if (cs4224_is_hw_simplex(slice)) { + host_traceloss = rules->tx_if.splx_driver.traceloss; + line_traceloss = rules->tx_if.splx_driver.traceloss; + } else { + host_traceloss = rules->tx_if.dplx_host_driver.traceloss; + line_traceloss = rules->tx_if.dplx_line_driver.traceloss; + } + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_init_driver_trace_loss_intf( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, host_traceloss); + } + + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_init_driver_trace_loss_intf( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, line_traceloss); + } + + return status; +} + +int cs4224_init_driver_settings(unsigned int slice, + enum e_cs4224_tx_driver_interface intf, + unsigned short ctrla, + unsigned short ctrlb) +{ + int status = CS_OK; + unsigned short offset = 0; + + if (cs4224_is_hw_simplex(slice) && + intf == CS4224_TX_SIMPLEX_INTERFACE) { + /* figure out which driver we need to change */ + if (cs4224_line_rx_to_host_tx_dir(slice)) + intf = CS4224_TX_HOST_INTERFACE; + else + intf = CS4224_TX_LINE_INTERFACE; + } else if (intf == CS4224_TX_SIMPLEX_INTERFACE) { + CS_TRACE(("ERROR: duplex slice cannot use intf = ")); + CS_TRACE(("CS4224_TX_SIMPLEX_INTERFACE\n")); + return CS_ERROR; + } + + if (intf == CS4224_TX_HOST_INTERFACE) + offset = CS4224_LINE_TO_HOST_OFFSET; + else + offset = 0; + + cs4224_lock(slice); + + /* update CTRLA/CTRLB registers */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA + offset, + ctrla); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB + offset, + ctrlb); + + cs4224_unlock(slice); + + return status; +} + +unsigned char cs4224_datarate_less_than_10G(struct cs4224_rules_t *rules) +{ + unsigned int data_rate = cs4224_query_data_rate(rules); + + if (data_rate < 10000000) + return CS_TRUE; + + return CS_FALSE; +} + +int cs4224_update_clkdiv_ctrl_intf(unsigned int slice, + enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned short reg_data, old_data; + unsigned short offset = 0; + + status |= cs4224_get_cfg_side(slice, &intf); + if (status != CS_OK) + return status; + + if (intf == CS4224_CFG_LINE_SIDE) + offset = 0x0000; + else + offset = CS4224_LINE_TO_HOST_OFFSET; + + cs4224_lock(slice); + + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL + offset, + ®_data); + old_data = reg_data; + + if (rules->clkdiv.enable) { + if (rules->clkdiv.rdiv != CS4224_RULE_DISABLED) { + reg_data &= ~0x000f; + reg_data |= rules->clkdiv.rdiv; + } + if (rules->clkdiv.ddiv != CS4224_RULE_DISABLED) { + reg_data &= ~0x0070; + reg_data |= (rules->clkdiv.ddiv << 4); + } + if (rules->clkdiv.fastdiv != CS4224_RULE_DISABLED) { + reg_data &= ~0xf000; + reg_data |= (rules->clkdiv.fastdiv << 12); + } + } else + /* Only time clkdiv rule is not enabled is when using the + * fracdiv without any integer divide (so ~10G rates, etc). + * In that case reset it to defaults. + * LINE dft == HOST dft + */ + reg_data = CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL_dft; + + if (old_data != reg_data) + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL + offset, + reg_data); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_update_clkdiv_ctrl(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_update_clkdiv_ctrl_intf( + slice, CS4224_CFG_LINE_SIDE, rules); + } + if (cs4224_is_hw_duplex(slice) || !cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_update_clkdiv_ctrl_intf( + slice, CS4224_CFG_HOST_SIDE, rules); + } + + return status; +} + +int cs4224_fracdiv_cdr_init(unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned short divisor, + unsigned int numerator) +{ + int status = CS_OK; + unsigned short reg_data, old_data; + + unsigned short frac0_reset_addr; + unsigned short clkdiv_ctrl_addr; + unsigned short frac0_width_addr; + unsigned short frac0_intdiv_addr; + unsigned short frac0_numerator0_addr; + unsigned short frac0_numerator1_addr; + unsigned short frac0_stage1preload0_addr; + unsigned short frac0_stage1preload1_addr; + unsigned short frac0_dither_addr; + unsigned short frac0_stage_en_addr; + unsigned short frac0_power_down_addr; + unsigned short mseq_options_addr; + unsigned short mseq_options; + enum e_cs4224_mseq_id mseq_id; + + /* sides and datapath_dir are the same enum */ + status |= cs4224_get_cfg_side(slice, &dir); + if (status != CS_OK) + return status; + + if (dir == CS4224_LINE_RX_TO_HOST_TX_DIR) { + frac0_reset_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_RESET; + clkdiv_ctrl_addr = + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL; + frac0_width_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_WIDTH; + frac0_intdiv_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_INTDIV; + frac0_numerator0_addr = + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR0; + frac0_numerator1_addr = + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR1; + frac0_stage1preload0_addr = + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0; + frac0_stage1preload1_addr = + CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1; + frac0_dither_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_DITHER; + frac0_stage_en_addr = CS4224_PP_LINE_SDS_COMMON_FRAC0_STAGE_EN; + frac0_power_down_addr = + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB; + mseq_options_addr = CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW; + mseq_id = CS4224_DPLX_LINE_MSEQ; + } else { + frac0_reset_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_RESET; + clkdiv_ctrl_addr = + CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL; + frac0_width_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_WIDTH; + frac0_intdiv_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_INTDIV; + frac0_numerator0_addr = + CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR0; + frac0_numerator1_addr = + CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR1; + frac0_stage1preload0_addr = + CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0; + frac0_stage1preload1_addr = + CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1; + frac0_dither_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_DITHER; + frac0_stage_en_addr = CS4224_PP_HOST_SDS_COMMON_FRAC0_STAGE_EN; + frac0_power_down_addr = + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB; + mseq_options_addr = CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_SHADOW; + mseq_id = CS4224_DPLX_HOST_MSEQ; + } + + cs4224_lock(slice); + + /* find out if microsequencer is running */ + status |= cs4224_reg_get_channel(slice, mseq_options_addr, + &mseq_options); + + /* if microsequencer is running */ + if (0 == (0x0008 & mseq_options)) + /* stall the microsequencer */ + status |= cs4224_mseq_stall(slice, mseq_id, CS_TRUE); + + status |= cs4224_reg_get_channel(slice, frac0_power_down_addr, + ®_data); + old_data = reg_data; + reg_data &= ~0x0010; /* power-up FracN for configuration */ + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, frac0_power_down_addr, + reg_data); + + status |= cs4224_reg_get_channel(slice, frac0_reset_addr, ®_data); + old_data = reg_data; + reg_data &= ~0x0001; /* pull out of reset CDR fracn */ + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, frac0_reset_addr, + reg_data); + + status |= cs4224_reg_get_channel(slice, clkdiv_ctrl_addr, ®_data); + old_data = reg_data; + reg_data &= ~0x000f; + reg_data |= 0x9; /* Set the RDIV_SEL field to Fractional-N */ + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, clkdiv_ctrl_addr, + reg_data); + + status |= cs4224_reg_get_channel(slice, frac0_width_addr, ®_data); + old_data = reg_data; + reg_data &= ~0x0003; /* Setup to use a 24 bit accumulator */ + reg_data |= CS4224_FRACDIV_ACCUM_WIDTH_24BIT; + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, frac0_width_addr, + reg_data); + + status |= cs4224_reg_get_channel(slice, frac0_intdiv_addr, ®_data); + old_data = reg_data; + reg_data &= ~0x00ff; + reg_data |= (divisor & 0xff); /* Configure the denominator value */ + if (old_data != reg_data) + status |= cs4224_reg_set_channel(slice, frac0_intdiv_addr, + reg_data); + + /* Configure the numerator value */ + status |= cs4224_reg_set_channel(slice, frac0_numerator0_addr, + numerator & 0xFFFF); + status |= cs4224_reg_set_channel(slice, frac0_numerator1_addr, + (numerator >> 16) & 0xFF); + + /* Configure the stage 1 preload value */ + status |= cs4224_reg_set_channel(slice, frac0_stage1preload0_addr, + 0x5DC6); + status |= cs4224_reg_set_channel(slice, frac0_stage1preload1_addr, + 0x0034); + + status |= cs4224_reg_set_channel(slice, frac0_dither_addr, 0x0000); + + /* Enable stage1 only */ + status |= cs4224_reg_set_channel(slice, frac0_stage_en_addr, 0x0408); + + status |= cs4224_reg_get_channel(slice, frac0_reset_addr, ®_data); + reg_data |= 0x0001; /* reset CDR fracn */ + status |= cs4224_reg_set_channel(slice, frac0_reset_addr, reg_data); + reg_data &= ~0x0001; /* pull out of reset CDR fracn */ + status |= cs4224_reg_set_channel(slice, frac0_reset_addr, reg_data); + + /* if microsequencer was running */ + if (0 == (0x0008 & mseq_options)) { + /* un-stall the microsequencer */ + status |= cs4224_mseq_stall(slice, mseq_id, CS_FALSE); + } + + cs4224_unlock(slice); + + return status; +} + +int cs4224_update_cdr_fracn(unsigned int slice, struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + if (rules->fracdiv.enable) { + /* enable the fractional divider */ + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_fracdiv_cdr_init( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, + rules->fracdiv.divisor, + rules->fracdiv.numerator); + } + + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_fracdiv_cdr_init( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, + rules->fracdiv.divisor, + rules->fracdiv.numerator); + } + } + /* clkdiv rdiv will control the use of the fracn, so we never have to + * reset the fracn settings as long as the clkdiv is re-programmed + */ + + return status; +} + +int cs4224_restore_powered_down_regs(unsigned int slice) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_MISC, + CS4224_PP_HOST_SDS_COMMON_STX0_MISC_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1, + CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG, + CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG, + CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft); + } + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_MISC, + CS4224_PP_LINE_SDS_COMMON_STX0_MISC_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1, + CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG, + CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB, + CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB, + CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG, + CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG, + CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft); + } + return status; +} + +int cs4224_slice_power_down(unsigned int slice) +{ + int status = CS_OK; + + if ((cs4224_is_hw_simplex(slice) && + cs4224_line_rx_to_host_tx_dir(slice)) || + (cs4224_is_hw_duplex(slice))) { + /* stall the microsequencer */ + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_LINE_MSEQ, CS_TRUE); + + /* STX_PD=1, STX_PD_MUX=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_MISC, 0x8033); + /* SRX_AGC_ENB_LIMAMP=0 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1, + 0x0004); + /* SRX_DFE_BYPASS_EN=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG, + 0x0441); + /* SRX_DAC_ENB<19:0>=0xfffff */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB, + 0xffff); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB, + 0x000f); + /* SRX_AMP_PD=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG, + 0x0044); + /* SRX_VCO_EN=0, SRX_VCO_PDMUX_EN=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG, + 0x0705); + /* SRX_CLKDIV_PD=1, SRX_PD_DEMUX=7 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x03ff); + } + if ((cs4224_is_hw_simplex(slice) && + !cs4224_line_rx_to_host_tx_dir(slice)) || + (cs4224_is_hw_duplex(slice))) { + /* stall the microsequencer */ + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_HOST_MSEQ, CS_TRUE); + + /* STX_PD=1, STX_PD_MUX=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_MISC, 0x8033); + /* SRX_AGC_ENB_LIMAMP=0 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1, + 0x0004); + /* SRX_DFE_BYPASS_EN=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG, + 0x0441); + /* SRX_DAC_ENB<19:0>=0xfffff */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB, + 0xffff); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB, + 0x000f); + /* SRX_AMP_PD=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG, + 0x0044); + /* SRX_VCO_EN=0, SRX_VCO_PDMUX_EN=1 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG, + 0x0705); + /* SRX_CLKDIV_PD=1, SRX_PD_DEMUX=7 */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x03ff); + } + + return status; +} + +int cs4224_apply_workarounds_power_down(unsigned int die) +{ + int status = CS_OK; + unsigned short data; + + cs4224_lock(die); + + /* get scratch 6 value from die to determine if we have already applied + * workarounds + */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + if (CS_IF_SET(data, CS_BIT0)) + /* workarounds already applied, bail out. */ + return CS_OK; + + /* make sure the mseqs are stalled, can't use broadcast otherwise! */ + status |= cs4224_reg_get( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW, &data); + if (CS_IF_CLR(data, CS_BIT3)) { + CS_TRACE(("ERROR: MSEQs on die 0x%x are not stalled.\n" + "This method is being used incorrectly.\n", die)); + return CS_ERROR; + } + + /* Apply workarounds to all port-pairs on the die, Bugzilla #37471 */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + { + /* power-down all slices as per Bug #38832 */ + /* STX_PD=1, STX_PD_MUX=1 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_STX0_MISC, 0x8033); + /* SRX_AGC_ENB_LIMAMP=0 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1, + 0x0004); + /* SRX_DFE_BYPASS_EN=1 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG, 0x0441); + /* SRX_DAC_ENB<19:0>=0xfffff */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB, + 0xffff); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB, + 0x000f); + /* SRX_AMP_PD=1 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG, 0x0044); + /* SRX_VCO_EN=0, SRX_VCO_PDMUX_EN=1 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG, 0x0705); + /* SRX_CLKDIV_PD=1, SRX_PD_DEMUX=7 */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x03ff); + } + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + + /* Mark all of the workarounds as complete */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + status |= cs4224_reg_set(die, CS4224_GLOBAL_SCRATCH6, + CS_SET(data, CS_BIT0)); + + cs4224_unlock(die); + + return status; +} + +int cs4224_slice_soft_reset_intf(unsigned int slice, + enum e_cs4224_cfg_sides_t intf) +{ + int status = CS_OK; + int tmp_status = CS_OK; + unsigned short data = 0; + unsigned short reg_offset = 0; + enum e_cs4224_mseq_id mseq_id = CS4224_DPLX_LINE_MSEQ; + enum e_cs4224_mseq_id other_mseq_id = CS4224_DPLX_HOST_MSEQ; + unsigned int mate_slice = 0xFF; + unsigned char stalled = CS_FALSE; + unsigned char power_savings = CS_FALSE; + unsigned short other_power_down = 0x0; + + if (intf == CS4224_CFG_LINE_SIDE) { + reg_offset = 0; + mseq_id = CS4224_DPLX_LINE_MSEQ; + other_mseq_id = CS4224_DPLX_HOST_MSEQ; + } else if (intf == CS4224_CFG_HOST_SIDE) { + reg_offset = CS4224_LINE_TO_HOST_OFFSET; + mseq_id = CS4224_DPLX_HOST_MSEQ; + other_mseq_id = CS4224_DPLX_LINE_MSEQ; + } else { + CS_TRACE(("ERROR: intf must be line/host, not splx. intf=%d\n", + intf)); + return CS_ERROR; + } + + /* make sure mseq is stalled on this interface, if not, then stall and + * don't unstall after the reset + */ + status |= cs4224_query_mseq_is_stalled(slice, mseq_id, &stalled); + if (!stalled) + status |= cs4224_mseq_stall(slice, mseq_id, CS_TRUE); + + /* we need to control the power_down on both line and host interfaces. + * In simplex, the other interface's mseq may be running, so turn off + * power savings so we can mess around with power_down without affecting + * traffic + */ + tmp_status |= cs4224_simplex_mate_slice(slice, &mate_slice); + if ((mate_slice & 0xFF) == 0xFF) { + /* doesn't have a mate slice, which means the other slice is not + * configured nor running + */ + power_savings = CS_FALSE; + } else if (tmp_status != CS_OK) { + /* some other kind of error, not good */ + CS_TRACE(("ERROR getting mate slice\n")); + status |= tmp_status; + } else { + /* we do have a mate slice, or on duplex it's the same slice, + * either way check power savings + */ + status |= cs4224_query_mseq_power_savings(mate_slice, + other_mseq_id, + &power_savings); + if (power_savings) + status |= cs4224_mseq_enable_power_savings( + mate_slice, other_mseq_id, CS_FALSE); + } + + if (status != CS_OK) + return status; + + cs4224_lock(slice); + + /* clock and power up everything */ + if (intf == CS4224_CFG_LINE_SIDE) { + /* only touch Rx stuff */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, &data); + data |= 0x00ff; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, data); + + /* host-side reg doesn't have Tx settings */ + } else { + /* only touch Rx stuff */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_HOSTMISC_CLKEN, 0x0041); + + /* only touch Tx stuff on the other side */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, &data); + data |= 0xff00; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, data); + } + + /* save the other-side's power down so we can restore it later */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB - reg_offset, + &other_power_down); + + /* stagger power up */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x001F); + /* stagger power up only if we won't kill anything, this works because + * if it's already on (cleared to 0) then this won't turn it off trying + * to write 0x1F into the reg + * NOTE: There is an issue (maybe?) in the PRBS checker that when you + * clear bit6 you will get a momenary loss of PRBS sync this does not + * effect traffic through the device, only the PRBS checker + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB - reg_offset, + (other_power_down & 0x001F)); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB - reg_offset, + 0x0000); + + /* reset most of the Rx settings */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_SOFT_RESET + reg_offset, 0x0031); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG + reg_offset, + 0x0003); + + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_SOFT_RESET + reg_offset, 0x0000); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG + reg_offset, + 0x0000); + + /* some stuff isn't hit by those resets, so reset those manually */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_CONTROL + reg_offset, + CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_CONTROL_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RX0_Config + reg_offset, + CS4224_PP_LINE_SDS_COMMON_RX0_Config_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_RXELST0_Control + reg_offset, + CS4224_PP_LINE_SDS_COMMON_RXELST0_Control_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKOUT_CTRL + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKOUT_CTRL_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_MONCTRL + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_MONCTRL_dft); + + /* RX_CONFIG on the RX side has a Tx side Tx bit for some reason. + * Yes this register is correct, so the LINE_SDRX0_RX_CONFIG + * will contain the analog host Tx polarity inversion bit + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_dft); + + /* Reset some Tx registers that weren't hit by the Rx soft reset + * These are mostly just registers not touched by + * cs4224_slice_enter_operational_state + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_TX0_Config - reg_offset, + CS4224_PP_HOST_SDS_COMMON_TX0_Config_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_TXELST0_Control - reg_offset, + CS4224_PP_HOST_SDS_COMMON_TXELST0_Control_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_CONFIG - reg_offset, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_CONFIG_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE - reg_offset, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE_dft); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE - reg_offset, + CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_MISC - reg_offset, + CS4224_PP_HOST_SDS_COMMON_STX0_MISC_dft); + + /* Reset some stuff that's normally reset in + * cs4224_restore_powered_down_regs + */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB_dft); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG + reg_offset, + CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG_dft); + + /* Unfortunately the soft reset wipes out the per-port workarounds on + * this slice, so re-apply them + * NOTE: Sync this block of writes with those in the + * cs4224_apply_workarounds method + */ + + /* Adjust the LC-VCO bias current because the defaults are wrong. + * See bugzilla #36619,39270 for details + */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_VCOBIAS + reg_offset, + 0x0907); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL00 + reg_offset, + 0x3222); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL01 + reg_offset, + 0x4444); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL02 + reg_offset, + 0x5555); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL03 + reg_offset, + 0x6666); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL10 + reg_offset, + 0x7654); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL11 + reg_offset, + 0x8877); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL12 + reg_offset, + 0xa999); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL13 + reg_offset, + 0xccba); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL + reg_offset, + 0x001e); + + /* clear bit 13 (bug 37471) */ + data = CS_CLR(CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE_dft, CS_BIT13); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE + reg_offset, + data); + + /* clear common_tx_sr reset */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_SOFT_RESET + reg_offset, + 0x0000); + + /* force driver charge pump high to eliminate cross-talk */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA + reg_offset, + 0x80dd); + + /* DATAPATH_CTRL is different between line and host, but the + * host bits that are different are reserved so it doesn't + * matter if we try to write them + */ + data = CS_SET(CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL_dft, CS_BIT1); + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL + reg_offset, + data); + + /* Reset power-down and clken before proceeding */ + if (intf == CS4224_CFG_LINE_SIDE) { + /* reset Rx stuff */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, &data); + data &= 0xff00; + data |= 0x0060; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, data); + /* no Tx stuff in host reg */ + } else { + /* reset Rx stuff */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_HOSTMISC_CLKEN, 0x0000); + + /* reset Tx stuff on other side */ + status |= cs4224_reg_get_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, &data); + data &= 0x00ff; + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_LINEMISC_CLKEN, data); + } + + /* set power down to default on this interface */ + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB + reg_offset, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft); + + if (!power_savings) { + /* restore power down on the other interface */ + status |= cs4224_reg_set_channel( + slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB - reg_offset, + other_power_down); + } + + cs4224_unlock(slice); + + /* re-enable power savings on the other interface if needed */ + if (power_savings) { + status |= cs4224_mseq_enable_power_savings(mate_slice, + other_mseq_id, + CS_TRUE); + } + + return status; +} + +int cs4224_slice_soft_reset(unsigned int slice) +{ + int status = CS_OK; + + if (cs4224_is_hw_duplex(slice) || cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_slice_soft_reset_intf(slice, + CS4224_CFG_LINE_SIDE); + } + if (cs4224_is_hw_duplex(slice) || !cs4224_line_rx_to_host_tx_dir( + slice)) { + status |= cs4224_slice_soft_reset_intf(slice, + CS4224_CFG_HOST_SIDE); + } + + return status; +} + +int cs4224_apply_workarounds(unsigned int die) +{ + int status = CS_OK; + unsigned short data; + + cs4224_lock(die); + + /* scratch6 value determines if we have already applied workarounds */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + if (CS_IF_SET(data, CS_BIT0)) { + /* workarounds already applied, bail out. */ + return CS_OK; + } + + /* make sure the mseqs are stalled, can't use broadcast otherwise! */ + status |= cs4224_reg_get( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW, &data); + if (CS_IF_CLR(data, CS_BIT3)) { + CS_TRACE(("ERROR: MSEQs on die 0x%x are not stalled.\n" + "This method is being used incorrectly.\n", die)); + return CS_ERROR; + } + + /* At this point, the device is essentially right out of reset */ + + /* Change the temperature and voltage monitors to poll */ + status |= cs4224_enable_monitor_sense_points(die, CS_FALSE); + + /* Increase MDIO timeout as per Bugzilla 35875 */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_MDIO_CONFIG, + CS4224_GLOBAL_MDIO_CONFIG_pref); + + /* load the 0.9v monitor calibration constant */ + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_MON_GAIN_DATA, &data); + status |= cs4224_reg_set(die, CS4224_MONITOR_CAL_OVERRIDE, data); + + /* load the 1.8v monitor calibration constant */ + status |= cs4224_reg_get(die, CS4224_EFUSE_PDF_MON_LUT15, &data); + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_VALUE0, data); + + /* make use of the temperature and 0.9v voltage calibration constants */ + status |= cs4224_reg_set(die, CS4224_MONITOR_CAL_CONST_OVERRIDE_ENA, + 0x0004); + status |= cs4224_reg_set(die, CS4224_MONITOR_CAL_CONST_APPLY, 0x0005); + + /* make use of the 1.8v voltage calibration constant */ + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_RANGE0, 0xffff); + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_SELECT, 0x0000); + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_LOCAL_SELECT, 0x0040); + status |= cs4224_reg_set(die, CS4224_MONITOR_LUT_APPLY, 0x0040); + + /* Apply workarounds to all port-pairs (PP) on the die */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + + /* Adjust the LC-VCO bias current because the defaults are wrong. + * See bugzilla #36619,39270 for details + * NOTE: Sync these values with those in the cs4224_slice_soft_reset + * method + */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_VCOBIAS, + 0x0907); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL00, + 0x3222); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL01, + 0x4444); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL02, + 0x5555); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL03, + 0x6666); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL10, + 0x7654); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL11, + 0x8877); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL12, + 0xa999); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL13, + 0xccba); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL, 0x001e); + + /* clear bit 13 (bug 37471) */ + data = CS_CLR(CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE_dft, CS_BIT13); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE, data); + + /* clear common_tx_sr reset */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_SOFT_RESET, 0x0); + + /* force driver charge pump high to eliminate cross-talk */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA, 0x80dd); + + /* DATAPATH_CTRL is different between line and host, but the + * host bits that are different are reserved so it doesn't + * matter if we try to write them + */ + data = CS_SET(CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL_dft, + CS_BIT1); + status |= cs4224_reg_set( + die, CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL, data); + + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + + cs4224_unlock(die); + + return status; +} + +int cs4224_apply_post_ucode_dwld_workarounds(unsigned int die) +{ + int status = CS_OK; + unsigned short data; + + cs4224_lock(die); + + /* make sure the mseqs are stalled, can't use broadcast otherwise! */ + status |= cs4224_reg_get( + die, CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW, &data); + if (CS_IF_CLR(data, CS_BIT3)) { + CS_TRACE(("ERROR: MSEQs on die 0x%x are not stalled.\n" + "This method is being used incorrectly.\n", die)); + return CS_ERROR; + } + + /* Apply workarounds to all port-pairs on the die, Bugzilla #37471 */ + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x80); + + /* force driver charge pump high (to rail) to elimitnate cross-talk */ + status |= cs4224_reg_set( + die, CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA, 0x80dd); + + status |= cs4224_reg_set(die, CS4224_GLOBAL_BROADCAST, 0x0); + + cs4224_unlock(die); + + return status; +} + +int cs4224_dump_debug_info(unsigned int slice, struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + const char *app = cs4224_translate_app_mode(rules->application); + const char *edc_mode; + const char *edc_mode2; + + char data_rate_str[15] = ""; + + if (rules->application == CS4224_TARGET_APPLICATION_KRAN) + CS_SNPRINTF((data_rate_str, + ARRAY_SIZE(data_rate_str), + "0x%04x", + rules->kran.data_rates)); + else + CS_SNPRINTF((data_rate_str, + ARRAY_SIZE(data_rate_str), + "%uMbps", + (cs4224_query_data_rate(rules) / 1000))); + + if (cs4224_is_hw_simplex(slice)) { + edc_mode = + cs4224_translate_edc_mode(rules->rx_if.splx_edc_mode); + edc_mode2 = edc_mode; + } else { + edc_mode = cs4224_translate_edc_mode( + rules->rx_if.dplx_line_edc_mode); + edc_mode2 = cs4224_translate_edc_mode( + rules->rx_if.dplx_host_edc_mode); + } + + switch (hw_id) { + case CS4224_HW_CS4223: /* 4 port duplex */ + CS_PRINTF(("\nK2 configured for Duplex CS4223,Max ports = %d\n", + cs4224_max_num_ports)); + CS_PRINTF(("slice = %x, die = %x, PP offset = 0x%05x\n", + slice & 0xff, + cs4224_get_die_from_slice(slice), + cs4224_adj_pp(slice, 0))); + CS_PRINTF(("application = %s, data rate = %s, ", + app, data_rate_str)); + CS_PRINTF(("line edc_mode = %s, host edc_mode = %s\n", + edc_mode, edc_mode2)); + + break; + + case CS4224_HW_CS4224: /* 16 port simplex */ + case CS4224_HW_CS4343: /* 8 port duplex */ + case CS4224_HW_CS4221: /* 10 port simplex */ + case CS4224_HW_CS4227: /* 2 port duplex */ + case CS4224_HW_CS4210: /* 16 port simplex */ + case CS4224_HW_CS4341: /* 8 port duplex */ + status = CS_ERROR; + printf("SKU not yet supported !\n"); + break; + default: + CS_PRINTF(("\nERROR: K2 Efuse SKU not configured\n\n")); + status = CS_ERROR; + + break; + } + + return status; +} + +unsigned char cs4224_is_eeprom_finished(unsigned int die) +{ + unsigned short efuse_general_status; + unsigned short global_pin_status; + unsigned short eeprom_loader_status; + + cs4224_reg_get(die, CS4224_EFUSE_GENERAL_STATUS, &efuse_general_status); + if (efuse_general_status != 0x0001) { + /* EFUSE has not finished loading */ + return CS_FALSE; + } + + cs4224_reg_get(die, CS4224_GLOBAL_PIN_STATUS, &global_pin_status); + /* 0xf00d means the eeprom loader is still running + * 0xffff means the refclk isn't stable + */ + if (global_pin_status == 0xf00d || + global_pin_status == 0xffff || + global_pin_status == 0xbada) { + return CS_FALSE; + } else if ((global_pin_status & 0x4000) == 0) + /* EEPROM not present */ + return CS_TRUE; + + cs4224_reg_get(die, CS4224_EEPROM_LOADER_STATUS, &eeprom_loader_status); + if (eeprom_loader_status == 0xbada) + return CS_FALSE; + + if ((eeprom_loader_status & 0x0007) != 0) + /* EEPROM load abort, load failed, or load done */ + return CS_TRUE; + + return CS_FALSE; +} + +int cs4224_wait_for_eeprom_finished( + unsigned int die, unsigned int max_iterations, + unsigned int ms_delay_between_iterations) +{ + int status = CS_OK; + unsigned char finished = CS_FALSE; + unsigned int attempt = 0; + + do { + finished = cs4224_is_eeprom_finished(die); + + if (!finished) { + if (ms_delay_between_iterations == 0) + CS_MDELAY(1); + else + CS_MDELAY(ms_delay_between_iterations); + } + } while ((attempt++ < max_iterations) && (finished == CS_FALSE)); + + if (finished == CS_TRUE) { + status = CS_OK; + } else { + CS_TRACE(("ERROR: EEPROM not loading, die=%x\n", die)); + status = CS_ERROR; + } + + return status; +} + +int cs4224_update_scratch_regs(unsigned int slice) +{ + int status = CS_OK; + unsigned short reg_addr = 0x0; + unsigned short inc = 0x0; + unsigned short counter = 0x0; + unsigned char local_slice = slice & 0xff; + + /* which scratch you use is based off of the PP, + * ex PP2 is GLOBAL_SCRATCH2 + */ + reg_addr = CS4224_GLOBAL_SCRATCH0 + (cs4224_adj_pp(slice, 0x0) >> 12); + + /* increment is based off of the die, ex slice 2 is die 1 which is the + * upper bits of GLOBAL_SCRATCH2, so inc will be 0x0100. + * See global_scratch_allocation.txt for more info + */ + inc = (cs4224_get_die_from_slice(local_slice) == 1) ? 0x0100 : 0x0001; + + cs4224_lock(slice); + + status |= cs4224_reg_get_channel(slice, reg_addr, &counter); + counter += inc; + status |= cs4224_reg_set_channel(slice, reg_addr, counter); + + cs4224_unlock(slice); + + return status; +} + +int cs4224_check_rules(unsigned int slice, struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned char bad_state = CS_FALSE; + unsigned short valid_edc_modes = 0; + + switch (rules->application) { + case CS4224_TARGET_APPLICATION_OC12: + case CS4224_TARGET_APPLICATION_1G: + case CS4224_TARGET_APPLICATION_1G_FC: + case CS4224_TARGET_APPLICATION_2G_FC: + case CS4224_TARGET_APPLICATION_4G_FC: + case CS4224_TARGET_APPLICATION_5G: + case CS4224_TARGET_APPLICATION_7p5G: + case CS4224_TARGET_APPLICATION_8G_FC: + case CS4224_TARGET_APPLICATION_16G_FC: + case CS4224_TARGET_APPLICATION_15G: + case CS4224_TARGET_APPLICATION_10G_KR: + case CS4224_TARGET_APPLICATION_40G_KR: + case CS4224_TARGET_APPLICATION_KRAN: + case CS4224_TARGET_APPLICATION_FCAN: + case CS4224_TARGET_APPLICATION_8G: + case CS4224_TARGET_APPLICATION_8p5G: + case CS4224_TARGET_APPLICATION_10G_FC: + printf("Target application mode not yet supported!\n"); + status = CS_ERROR; + break; + case CS4224_TARGET_APPLICATION_10G: { + valid_edc_modes = + CS_HSIO_EDC_MODE_SR | + CS_HSIO_EDC_MODE_10G_BP | + CS_HSIO_EDC_MODE_CX1 | + CS_HSIO_EDC_MODE_SMLRM | + CS_HSIO_EDC_MODE_DWDM | + CS_HSIO_EDC_MODE_ZR; + + if (cs4224_is_hw_simplex(slice)) + bad_state = + !(rules->rx_if.splx_edc_mode & valid_edc_modes); + else + bad_state = + !((rules->rx_if.dplx_host_edc_mode & + valid_edc_modes) && + (rules->rx_if.dplx_line_edc_mode & + valid_edc_modes)); + + if (bad_state) { + CS_TRACE(("ERROR: target app only supports EDC modes")); + CS_TRACE(("SR, CX1, 10G_BP, DWDM, and ZR\n")); + status |= CS_ERROR; + } + break; + } + } + + /* validate simplex/duplex rules */ + if (cs4224_is_hw_simplex(slice)) { + /* These traceloss settings are for the driver only */ + bad_state = + rules->rx_if.splx_eq.traceloss == + CS_HSIO_TRACE_LOSS_CR4 || + rules->rx_if.splx_eq.traceloss == + CS_HSIO_TRACE_LOSS_27dB || + rules->rx_if.splx_eq.traceloss == + CS_HSIO_TRACE_LOSS_15dB || + rules->rx_if.splx_eq.traceloss == + CS_HSIO_TRACE_LOSS_LAB; + if (bad_state) { + CS_TRACE(("ERROR: Traceloss settings of 15/27dB or ")); + CS_TRACE(("CR4/LAB are for the tx_if.*_driver.")); + CS_TRACE(("traceloss setting only.\n")); + status |= CS_ERROR; + } + + /* FEC available for simplex parts only */ + bad_state = rules->enable_fec; + if (bad_state) { + CS_TRACE(("ERROR: FEC not supported on simplex\n")); + status |= CS_ERROR; + } + } else { + /* These traceloss settings are for the driver only */ + bad_state = + rules->rx_if.dplx_host_eq.traceloss == + CS_HSIO_TRACE_LOSS_15dB || + rules->rx_if.dplx_host_eq.traceloss == + CS_HSIO_TRACE_LOSS_27dB || + rules->rx_if.dplx_host_eq.traceloss == + CS_HSIO_TRACE_LOSS_CR4 || + rules->rx_if.dplx_host_eq.traceloss == + CS_HSIO_TRACE_LOSS_LAB || + rules->rx_if.dplx_line_eq.traceloss == + CS_HSIO_TRACE_LOSS_15dB || + rules->rx_if.dplx_line_eq.traceloss == + CS_HSIO_TRACE_LOSS_27dB || + rules->rx_if.dplx_line_eq.traceloss == + CS_HSIO_TRACE_LOSS_CR4 || + rules->rx_if.dplx_line_eq.traceloss == + CS_HSIO_TRACE_LOSS_LAB; + if (bad_state) { + CS_TRACE(("ERROR: Traceloss settings of 15/27dB or ")); + CS_TRACE(("CR4/LAB are for the tx_if.*_driver.")); + CS_TRACE(("traceloss setting only.\n")); + status |= CS_ERROR; + } + } + + /* validate the refclk is correct */ + if ((rules->ref_clk_rate > 180000) || (rules->ref_clk_rate < 50000)) { + /* ref clk can only be 50-180MHz */ + CS_TRACE(("ERROR: ref_clk_rate is the internal reference ")); + CS_TRACE(("clock rate, which can only be between 50MHz and ")); + CS_TRACE(("180MHz\nIf you are using the REFDIV2_ENB pin then")); + CS_TRACE((" div your refclk by 2 for the ref_clk_rate val\n")); + status |= CS_ERROR; + } + + if (status != CS_OK) + CS_TRACE(("ERROR: bad rules config on slice %x\n", slice)); + + return status; +} + +int cs4224_manage_ucode_download(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + + unsigned short timestamp[2] = { 0xffff, 0xffff }; + unsigned short yyyy, mmdd, hhmm; + unsigned int die, other_die; + unsigned char die_broadcast = CS_FALSE; + unsigned short version_kr, version_fc; + unsigned short *ucode_image = NULL; + unsigned int size_image = 0; + unsigned char stalled = CS_FALSE; + enum e_cs4224_ucode_image required_image = CS4224_UCODE_IMAGE_ANY; + enum e_cs4224_ucode_image loaded_image = CS4224_UCODE_IMAGE_NONE; + + /* die being programmed */ + die = cs4224_get_die_from_slice(slice); + /* the other die */ + other_die = die ^ 0x1; + + cs4224_lock(slice); + + /* Check to see if the microcode has already been programmed */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_TIMESTAMP0, + ×tamp[0]); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_VERSION_KR, + &version_kr); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_VERSION_FC, + &version_fc); + + if (cs4224_max_num_dies == 2) { + status |= cs4224_reg_get(other_die, + CS4224_GLOBAL_UCODE_TIMESTAMP0, + ×tamp[1]); + } + cs4224_unlock(slice); + + /* decide if we should broadcast ucode to both dies */ + if (rules->enable_die_broadcast && + (cs4224_max_num_dies == 2) && + (timestamp[0] == 0) && + (timestamp[1] == 0)) + die_broadcast = CS_TRUE; + + /* apply die workarounds, if necessary */ + status |= cs4224_apply_workarounds(die); + if (die_broadcast) + status |= cs4224_apply_workarounds(other_die); + + if (status != CS_OK) + return status; + + /* determine what our microcode requirements are */ + if (rules->application == CS4224_TARGET_APPLICATION_KRAN) + required_image = CS4224_UCODE_IMAGE_KR; + else if (rules->application == CS4224_TARGET_APPLICATION_FCAN) + required_image = CS4224_UCODE_IMAGE_FC; + + /* determine what is currently loaded */ + if (version_kr != 0) + loaded_image = CS4224_UCODE_IMAGE_KR; + else if (version_fc != 0) + loaded_image = CS4224_UCODE_IMAGE_FC; + + /* if the currently loaded ucode is not what we need */ + if ((loaded_image & required_image) == 0) { + if (required_image != CS4224_UCODE_IMAGE_FC) { + ucode_image = cs4224_kr_ucode_image; + size_image = sizeof(cs4224_kr_ucode_image) + / sizeof(unsigned short); + } + + if (die_broadcast) { + CS_PRINTF(("Broadcasting image\n")); + /* broadcast to both dies */ + status |= cs4224_ucode_data_prgm_image_broadcast( + slice, ucode_image, size_image); + } else { /* unicast */ + CS_PRINTF(("Unicasting image\n")); + /* only broadcast to single die */ + status |= cs4224_ucode_data_prgm_image(slice, + ucode_image, + size_image); + } + + /* check that the ucode programmed correctly */ + if (status != CS_OK) { + CS_TRACE(("ERROR downloading microcode, exiting\n")); + return status; + } + + /* check if post-setup in the ucode image unstalled the mseqs + * (it shouldn't). Note you can check any mseq on this die, + * since they should all be configured equally + */ + status |= cs4224_query_mseq_is_stalled(slice, + CS4224_DPLX_LINE_MSEQ, + &stalled); + if (!stalled) { + /* Iterate over all the slices on this die */ + unsigned int first_slice = 0; + unsigned int last_slice = 0; + unsigned int mid_slice = + CS4224_MAX_NUM_SLICES(slice) / 2; + unsigned int upper_bits = slice & 0xffffff00; + unsigned char i = 0; + unsigned int slice_i = 0; + + if (die_broadcast || CS4224_MAX_NUM_DIES(slice) == 1) { + /* reset all the slices */ + first_slice = 0; + last_slice = CS4224_MAX_NUM_SLICES(slice) - 1; + } else { + /* only reset mseqs on this die */ + if (slice < mid_slice) { + first_slice = 0; + last_slice = mid_slice - 1; + } else { + first_slice = mid_slice; + last_slice = CS4224_MAX_NUM_SLICES( + slice) + - 1; + } + } + + for (i = first_slice; i <= last_slice; i++) { + slice_i = upper_bits | i; + + /* stall the microsequencer(s) again */ + if (cs4224_is_hw_simplex(slice_i)) { + status |= cs4224_mseq_stall( + slice_i, CS4224_SPLX_MSEQ, + CS_TRUE); + } else { + status |= cs4224_mseq_stall( + slice_i, CS4224_DPLX_LINE_MSEQ, + CS_TRUE); + status |= cs4224_mseq_stall( + slice_i, CS4224_DPLX_HOST_MSEQ, + CS_TRUE); + } + } + } /* stall mseq block */ + + /* re-apply some die workarounds that got removed in the ucode + * download + */ + status |= cs4224_apply_post_ucode_dwld_workarounds(die); + if (die_broadcast) + status |= cs4224_apply_post_ucode_dwld_workarounds( + other_die); + } /* pgm ucode block */ + + if (rules->show_debug_info) { + /* Get the timestamp of the loaded microcode */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_TIMESTAMP1, + &yyyy); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_TIMESTAMP0, + &mmdd); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_TIMESTAMP2, + &hhmm); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_VERSION_KR, + &version_kr); + status |= cs4224_reg_get(die, CS4224_GLOBAL_UCODE_VERSION_FC, + &version_fc); + /* Note that for now both KR and FC versions are set to 1 */ + if ((version_kr != 0) && (version_fc != 0)) { + CS_TRACE(("ERROR: uCode version is both KR + FC, KR(")); + CS_TRACE(("v.%04x),FC(v.%04x) built %04x/%04x/%04x\n", + version_kr, version_fc, yyyy, mmdd, hhmm)); + return CS_ERROR; + } + if (version_kr != 0) { + CS_PRINTF(("uCode on die %x: KR(v.%04x), built on", + die, version_kr)); + CS_PRINTF((" (yyyy/mmdd/hhmm) = %04x/%04x/%04x\n", + yyyy, mmdd, hhmm)); + } + if (version_fc != 0) { + CS_PRINTF(("uCode on die %x: FC(v.%04x), built on", + die, version_fc)); + CS_PRINTF((" (yyyy/mmdd/hhmm) = %04x/%04x/%04x\n", + yyyy, mmdd, hhmm)); + } + if (cs4224_max_num_dies == 2 && die_broadcast) { + /* Get the timestamp of the other loaded microcode */ + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_TIMESTAMP1, + &yyyy); + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_TIMESTAMP0, + &mmdd); + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_TIMESTAMP2, + &hhmm); + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_VERSION_KR, + &version_kr); + status |= cs4224_reg_get( + other_die, CS4224_GLOBAL_UCODE_VERSION_FC, + &version_fc); + if (version_kr != 0) { + CS_PRINTF(("uCode on die %x: KR(v.%04x) built", + die, version_kr)); + CS_PRINTF((" (yyyy/mmdd/hhmm)=%04x/%04x/%04x\n", + yyyy, mmdd, hhmm)); + } + if (version_fc != 0) { + CS_PRINTF(("uCode on die %x: FC(v.%04x) built", + die, version_fc)); + CS_PRINTF((" (yyyy/mmdd/hhmm)=%04x/%04x/%04x\n", + yyyy, mmdd, hhmm)); + } + } + } + + /* power down all slices for bug #38832 */ + status |= cs4224_apply_workarounds_power_down(die); + if (die_broadcast) + status |= cs4224_apply_workarounds_power_down(other_die); + + return status; +} + +int cs4224_slice_enter_operational_state(unsigned int slice, + struct cs4224_rules_t *rules) +{ + int status = CS_OK; + unsigned int die = cs4224_get_die_from_slice(slice); + unsigned short data = 0; + + cs4224_sku_hw_id = CS4224_HW_UNDEF; + + /* Before we do anything, do some sanity checking of the rules */ + status |= cs4224_check_rules(slice, rules); + if (status != CS_OK) + return status; + + /* Before configuring the device, the die MUST have been reset and the + * EEPROM must already be loaded (if an EEPROM is available). Otherwise + * this method will exit immediately because it's unsafe to configure + * the device in this state. + */ + status |= cs4224_reg_get(die, CS4224_GLOBAL_SCRATCH6, &data); + if (CS_IF_CLR(data, CS_BIT1)) { + CS_TRACE(("ERROR: cs4224_hard_reset hasn't been run on die\n")); + return CS_ERROR; + } + if (!cs4224_is_eeprom_finished(die)) { + CS_TRACE(("ERROR: EEPROM is still loading; aborting.\n")); + return CS_ERROR; + } + + /* Program the API version number */ + status |= cs4224_init_api_version(slice); + + /* Increment the slice configure count */ + status |= cs4224_update_scratch_regs(slice); + + /* Reset any static state stored by the slice */ + cs4224_reset_static_state_for_slice(slice); + + /* stall the microsequencer(s), always */ + if (cs4224_is_hw_simplex(slice)) { + status |= cs4224_mseq_stall(slice, CS4224_SPLX_MSEQ, CS_TRUE); + } else { + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_LINE_MSEQ, CS_TRUE); + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_HOST_MSEQ, CS_TRUE); + } + + /* Re-assert the squelch after stalling the microsequencer if it is not + * already squelched + */ + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH, 0x0001); + } + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH, 0x0001); + } + + if ((cs4224_is_hw_simplex(slice) && + (rules->rx_if.splx_edc_mode == CS_HSIO_EDC_MODE_DISABLED)) || + (cs4224_is_hw_duplex(slice) && + (rules->rx_if.dplx_line_edc_mode == CS_HSIO_EDC_MODE_DISABLED)) || + (cs4224_is_hw_duplex(slice) && + (rules->rx_if.dplx_host_edc_mode == CS_HSIO_EDC_MODE_DISABLED))) { + /* When using an eeprom image the mseq can set the squelch bit + * before we are able to stall it. This will force the bit high + * if we're in disabled mode and the mseq won't be unstalled. + */ + rules->unsquelch_driver = CS_TRUE; + } + + /* dump out debug info */ + if (rules->show_debug_info == CS_TRUE) + status |= cs4224_dump_debug_info(slice, rules); + + /* Apply post-reset configuration and program the microcode */ + status |= cs4224_manage_ucode_download(slice, rules); + if (status != CS_OK) { + /* ucode download has a lot of potential to go wrong, exit */ + CS_TRACE(("ERROR: Ucode download on slice %x failed, exiting\n", + slice)); + return status; + } + + /* Apply a soft reset to put the slice in a known state. + * This only really helps dynamic reconfig. + */ + if (rules->application != CS4224_TARGET_APPLICATION_FCAN) + status |= cs4224_slice_soft_reset(slice); + + status |= cs4224_config_target_application(slice, rules); + + status |= cs4224_update_clkdiv_ctrl(slice, rules); + + status |= cs4224_init_driver_trace_loss(slice, rules); + + status |= cs4224_init_edc_mode_set(slice, rules); + + status |= cs4224_update_cdr_fracn(slice, rules); + + if (cs4224_is_hw_simplex(slice)) + status |= cs4224_mseq_enable_power_savings( + slice, CS4224_SPLX_MSEQ, rules->enable_power_savings); + else { + if (rules->application != CS4224_TARGET_APPLICATION_FCAN) { + /* the FC-AN ucode configures the line side DFE mode, + * do not muck around with power savings here... + */ + status |= cs4224_mseq_enable_power_savings( + slice, CS4224_DPLX_LINE_MSEQ, + rules->enable_power_savings); + } + status |= cs4224_mseq_enable_power_savings( + slice, CS4224_DPLX_HOST_MSEQ, + rules->enable_power_savings); + } + + status |= cs4224_init_alt_coarse_tuning(slice, rules); + status |= cs4224_disable_tx_driver_if_req(slice, rules); + status |= cs4224_init_ac_decoupling_caps(slice, rules); + status |= cs4224_init_mseq_dyn_reconfig(slice, rules); + + cs4224_lock(slice); + + /* coarse tune VCOs because ref clock is not at 106.25Mhz */ + + /* Enable then trigger VCO coarse tuning */ + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_get_channel(slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + &data); + status |= cs4224_reg_set_channel(slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x01e7); + CS_MDELAY(1); + + /* init_vco has built-in delays after coarse tuning */ + status |= cs4224_init_vco(slice, + CS4224_PP_LINE_SDS_COMMON_RXVCO0_CONTROL); + + if ((data & 0x1c0) != 0x1c0) { + /* demux enabled, needs staggered power up */ + status |= cs4224_reg_set_channel(slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + (data | 0x1f)); + } + status |= cs4224_reg_set_channel(slice, + CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB, + data); + } + + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_reg_get_channel(slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + &data); + status |= cs4224_reg_set_channel(slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + 0x01e7); + CS_MDELAY(1); + + /* init_vco has built-in delays after coarse tuning */ + status |= cs4224_init_vco(slice, + CS4224_PP_HOST_SDS_COMMON_RXVCO0_CONTROL); + + if ((data & 0x1c0) != 0x1c0) { + /* demux enabled, needs staggered power up */ + status |= cs4224_reg_set_channel(slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + (data | 0x1f)); + } + + status |= cs4224_reg_set_channel(slice, + CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB, + data); + } + + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_mseq_squelch_ctrl( + slice, CS4224_LINE_RX_TO_HOST_TX_DIR, + rules->tx_auto_squelch); + } + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + status |= cs4224_mseq_squelch_ctrl( + slice, CS4224_HOST_RX_TO_LINE_TX_DIR, + rules->tx_auto_squelch); + } + + /* Unsquelching before the microcode is unstalled to prevent ordering + * issues. See bug #41747 for details. + */ + if (rules->unsquelch_driver) { + if (cs4224_is_hw_duplex(slice) || + cs4224_line_rx_to_host_tx_dir(slice)) { + /* remove any pending squelch requests */ + status |= cs4224_clear_mailbox(slice, + CS4224_DPLX_LINE_MSEQ); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH, + 0x0000); + } + if (cs4224_is_hw_duplex(slice) || + !cs4224_line_rx_to_host_tx_dir(slice)) { + /* remove any pending squelch requests */ + status |= cs4224_clear_mailbox(slice, + CS4224_DPLX_HOST_MSEQ); + status |= cs4224_reg_set_channel( + slice, CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH, + 0x0000); + } + } + + /* do not start microsequencer if protocol running on the line side */ + if ((rules->application != CS4224_TARGET_APPLICATION_10G_KR) && + (rules->application != CS4224_TARGET_APPLICATION_40G_KR) && + (rules->application != CS4224_TARGET_APPLICATION_KRAN) && + (rules->application != CS4224_TARGET_APPLICATION_FCAN)) { + /* un-stall the microsequencer(s), if required */ + if (cs4224_is_hw_simplex(slice)) { + if (rules->rx_if.splx_edc_mode != + CS_HSIO_EDC_MODE_DISABLED) { + status |= cs4224_mseq_stall( + slice, CS4224_SPLX_MSEQ, CS_FALSE); + } + } else { /* duplex */ + if (rules->rx_if.dplx_line_edc_mode != + CS_HSIO_EDC_MODE_DISABLED) + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_LINE_MSEQ, CS_FALSE); + if (rules->rx_if.dplx_host_edc_mode != + CS_HSIO_EDC_MODE_DISABLED) + status |= cs4224_mseq_stall( + slice, CS4224_DPLX_HOST_MSEQ, CS_FALSE); + } + } + + cs4224_unlock(slice); + + return status; +} + +unsigned int cs4224_get_die_from_slice(unsigned int slice) +{ + unsigned int die = 0; + enum e_cs4224_hardware_id hw_id = cs4224_hw_id(slice); + + /* Save the upper bits to pass thru to the die parameter */ + unsigned int upper_bits = slice & 0xffffff00; + + switch (hw_id) { + case CS4224_HW_CS4223: /* 4 port duplex */ + case CS4224_HW_CS4227: /* 2 port duplex */ + die = 0; + break; + + case CS4224_HW_CS4343: /* 8 port duplex */ + case CS4224_HW_CS4341: + /* Only the lower 8 bits belong to the API. They represent + * the duplex channel (0-7) of the device. + */ + if ((slice & 0xFF) > 3) + die = 0; + else + die = 1; + break; + + case CS4224_HW_CS4224: /* 16 port simplex */ + case CS4224_HW_CS4210: + /* Only the lower 8 bits belong to the API. They represent + * the simplex channel (0-15) of the device. + */ + if ((slice & 0xFF) > 7) + die = 0; + else + die = 1; + break; + + case CS4224_HW_CS4221: /* 10 port simplex */ + /* Only the lower 8 bits belong to the API. They represent + * the duplex channel (0-9) of the device. + */ + if ((slice & 0xFF) > 4) + die = 0; + else + die = 1; + break; + + default: + CS_TRACE(("ERROR: HW ID not valid, hw_id = %x\n", hw_id)); + die = 0; + break; + } + + return die | upper_bits; +} + +int cs4224_reg_get_channel(unsigned int slice, unsigned int addr, + unsigned short *data) +{ + unsigned int die = 0; + int status = CS_OK; + + /* If the address has not already been adjusted + * then do the port pair adjustment here + */ + if ((addr >= 0x1000) && (addr < 0x5000)) { + /* Mask out the upper bits if they have already been adjusted */ + addr = (addr | 0x3000) & 0x1fff; + + /* guard against reading from bad registers */ + if (!cs4224_diags_register_can_read((unsigned short)addr)) { + *data = 0xbeef; + return CS_OK; + } + + /* Now adjust them to access the proper port pair */ + addr = cs4224_adj_pp(slice, addr); + + /* CS_PRINTF(("after slice = %d, addr = %x\n", slice, addr));*/ + } + /* Handle the MSEQ_PS space */ + else if ((addr >= 0x300) && (addr < 0x500)) { + /* Mask out any upper bits if they have already been adjusted */ + addr = (addr | 0x300) & 0x3ff; + addr = cs4224_adj_mseq(slice, addr); + } + + /* get the die associated with this slice */ + die = cs4224_get_die_from_slice(slice); + + /* Set the die but make sure to pass the upper 24 bits of the + * slice parameter through to the lower level API. These are + * used by the customer to address multiple devices + */ + status |= cs4224_reg_get(die | (slice >> 8 << 8), addr, data); + + return status; +} + +unsigned short cs4224_reg_read(unsigned int slice, unsigned int addr) +{ + unsigned short data; + int status = CS_OK; + + status |= cs4224_reg_get_channel(slice, addr, &data); + if (status != CS_OK) { + CS_TRACE( + ("ERROR: reg get failed; status %x, returning 0xDEAD\n", + status)); + data = 0xDEAD; + } + + return data; +} + +int cs4224_reg_set_channel(unsigned int slice, unsigned int addr, + unsigned short data) +{ + unsigned int die = 0; + + /* If the PP address has not already been adjusted + * then do the port pair adjustment here + */ + if ((addr >= 0x1000) && (addr < 0x5000)) { + /* Mask out the upper bits if they have already been adjusted */ + addr = (addr | 0x3000) & 0x1fff; + + /* Now adjust them to access the proper port pair */ + addr = cs4224_adj_pp(slice, addr); + } + /* Handle the MSEQ_PS space */ + else if ((addr >= 0x300) && (addr < 0x500)) { + /* Mask out any upper bits if they have already been adjusted */ + addr = (addr | 0x300) & 0x3ff; + addr = cs4224_adj_mseq(slice, addr); + } + + /* get the die associated with this slice */ + die = cs4224_get_die_from_slice(slice); + + /* Set the die but make sure to pass the upper 24 bits of the + * slice parameter through to the lower level API. These are + * used by the customer to address multiple devices + */ + return cs4224_reg_set(die | (slice >> 8 << 8), addr, data); +} + +int cs4224_reg_set_chk_channel(unsigned int slice, unsigned int addr, + unsigned short data) +{ + int status = CS_OK; + unsigned short get_data = 0; + + status |= cs4224_reg_set_channel(slice, addr, data); + status |= cs4224_reg_get_channel(slice, addr, &get_data); + if (get_data != data) { + CS_TRACE( + ("ERROR: Data was written to register\n")); + CS_PRINTF( + ("reg addr: %4x data written: %4x data read: %4x\n", + addr, data, get_data)); + status |= CS_ERROR; + } + return status; +} + +const char *cs4224_translate_edc_mode(enum e_cs4224_edc_mode edc_mode) +{ + switch (edc_mode) { + case CS_HSIO_EDC_MODE_DISABLED: { + return "CS_HSIO_EDC_MODE_DISABLED"; + } + case CS_HSIO_EDC_MODE_CX1: { + return "CS_HSIO_EDC_MODE_CX1"; + } + case CS_HSIO_EDC_MODE_SR: { + return "CS_HSIO_EDC_MODE_SR"; + } + case CS_HSIO_EDC_MODE_ZR: { + return "CS_HSIO_EDC_MODE_ZR"; + } + case CS_HSIO_EDC_MODE_DWDM: { + return "CS_HSIO_EDC_MODE_DWDM"; + } + case CS_HSIO_EDC_MODE_10G_BP: { + return "CS_HSIO_EDC_MODE_10G_BP"; + } + case CS_HSIO_EDC_MODE_15G_BP: { + return "CS_HSIO_EDC_MODE_15G_BP"; + } + case CS_HSIO_EDC_MODE_15G_BP_27dB: { + return "CS_HSIO_EDC_MODE_15G_BP_27dB"; + } + case CS_HSIO_EDC_MODE_5G_BP: { + return "CS_HSIO_EDC_MODE_5G_BP"; + } + case CS_HSIO_EDC_MODE_7p5G_BP: { + return "CS_HSIO_EDC_MODE_7p5G_BP"; + } + case CS_HSIO_EDC_MODE_8p5G_BP: { + return "CS_HSIO_EDC_MODE_8p5G_BP"; + } + case CS_HSIO_EDC_MODE_FCAN: { + return "CS_HSIO_EDC_MODE_FCAN"; + } + case CS_HSIO_EDC_MODE_SMLRM: { + return "CS_HSIO_EDC_MODE_SMLRM"; + } + } + + return "UNKNOWN EDC MODE"; +} + +const char *cs4224_translate_app_mode(enum e_cs4224_target_application app_mode) +{ + switch (app_mode) { + case CS4224_TARGET_APPLICATION_1G: { + return "CS4224_TARGET_APPLICATION_1G"; + } + case CS4224_TARGET_APPLICATION_5G: { + return "CS4224_TARGET_APPLICATION_5G"; + } + case CS4224_TARGET_APPLICATION_7p5G: { + return "CS4224_TARGET_APPLICATION_7p5G"; + } + case CS4224_TARGET_APPLICATION_8G: { + return "CS4224_TARGET_APPLICATION_8G"; + } + case CS4224_TARGET_APPLICATION_8p5G: { + return "CS4224_TARGET_APPLICATION_8p5G"; + } + case CS4224_TARGET_APPLICATION_10G: { + return "CS4224_TARGET_APPLICATION_10G"; + } + case CS4224_TARGET_APPLICATION_15G: { + return "CS4224_TARGET_APPLICATION_15G"; + } + case CS4224_TARGET_APPLICATION_10G_KR: { + return "CS4224_TARGET_APPLICATION_10G_KR"; + } + case CS4224_TARGET_APPLICATION_40G_KR: { + return "CS4224_TARGET_APPLICATION_40G_KR"; + } + case CS4224_TARGET_APPLICATION_KRAN: { + return "CS4224_TARGET_APPLICATION_KRAN"; + } + case CS4224_TARGET_APPLICATION_FCAN: { + return "CS4224_TARGET_APPLICATION_FCAN"; + } + case CS4224_TARGET_APPLICATION_16G_FC: { + return "CS4224_TARGET_APPLICATION_16G_FC"; + } + case CS4224_TARGET_APPLICATION_10G_FC: { + return "CS4224_TARGET_APPLICATION_10G_FC"; + } + case CS4224_TARGET_APPLICATION_8G_FC: { + return "CS4224_TARGET_APPLICATION_8G_FC"; + } + case CS4224_TARGET_APPLICATION_4G_FC: { + return "CS4224_TARGET_APPLICATION_4G_FC"; + } + case CS4224_TARGET_APPLICATION_2G_FC: { + return "CS4224_TARGET_APPLICATION_2G_FC"; + } + case CS4224_TARGET_APPLICATION_1G_FC: { + return "CS4224_TARGET_APPLICATION_1G_FC"; + } + case CS4224_TARGET_APPLICATION_OC12: { + return "CS4224_TARGET_APPLICATION_OC12"; + } + } + + return "UNKNOWN APP MODE"; +} + +const char *cs4224_switch_translate_state(enum e_cs4224_switch_action_t state) +{ + switch (state) { + case CS4224_SWITCH_DISABLE: + return "CS4224_SWITCH_DISABLE"; + case CS4224_SWITCH_DUPLEX_BROADCAST_1_to_1: + return "CS4224_SWITCH_DUPLEX_BROADCAST_1_to_1"; + case CS4224_SWITCH_DUPLEX_BROADCAST_0_to_0: + return "CS4224_SWITCH_DUPLEX_BROADCAST_0_to_0"; + case CS4224_SWITCH_DUPLEX_BROADCAST_0_to_1: + return "CS4224_SWITCH_DUPLEX_BROADCAST_0_to_1"; + case CS4224_SWITCH_DUPLEX_BROADCAST_1_to_0: + return "CS4224_SWITCH_DUPLEX_BROADCAST_1_to_0"; + case CS4224_SWITCH_DUPLEX_SWITCH_2x2: + return "CS4224_SWITCH_DUPLEX_SWITCH_2x2"; + case CS4224_SWITCH_SIMPLEX_SWITCH_2x2: + return "CS4224_SWITCH_SIMPLEX_SWITCH_2x2"; + case CS4224_SWITCH_SIMPLEX_BROADCAST: + return "CS4224_SWITCH_SIMPLEX_BROADCAST"; + + default: + break; + } + + return "???"; +} + +const char *cs4224_translate_cfg_side(enum e_cs4224_cfg_sides_t side) +{ + switch (side) { + case CS4224_CFG_HOST_SIDE: + return "host"; + case CS4224_CFG_LINE_SIDE: + return "line"; + case CS4224_CFG_SIMPLEX: + return "splx"; + default: + break; + } + return "????"; +} + +#if !defined(CS_SKIP_UCODE_DOWNLOAD) + +int cs4224_ucode_data_prgm_image(unsigned int slice, unsigned short microcode[], + unsigned int len_buffer) +{ + unsigned int i; + int status = CS_OK; + unsigned short data0, data1; + unsigned int die; + + /* get the die associated to this slice */ + die = cs4224_get_die_from_slice(slice); + + /* toggle the checksum calculator, note that the file data will + * assert the checksum bit to start calculating the checksum + */ + cs4224_lock(slice); + cs4224_reg_set(die, CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL, 0x01); + cs4224_reg_set(die, CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL, 0x00); + cs4224_unlock(slice); + + for (i = 0; i < len_buffer; i += 2) { + unsigned short addr = microcode[i]; + unsigned short data = microcode[i + 1]; + unsigned short access_status = 0; + short max_iterations = 100; + + /* Program data here */ + cs4224_lock(slice); + + status |= cs4224_reg_set(die, addr, data); + + /* If this is a write to the EEPROM_MICRO_ACCESS_CONTROL + * then wait for the previous access to finish. + */ + if (addr == CS4224_EEPROM_MICRO_ACCESS_CONTROL) { + /* Wait for EEPROM_MICRO_ACCESS_STATUS.MicroAccessDone + * bit to be set. + */ + while (CS_IF_CLR(access_status, CS_BIT0) && + (max_iterations > 0)) { + cs4224_reg_get( + die, CS4224_EEPROM_MICRO_ACCESS_STATUS, + &access_status); + max_iterations -= 1; + } + + if (max_iterations <= 0) { + CS_TRACE(("ERROR: Timed out on die %x\n", die)); + return CS_ERROR; + } + } + + cs4224_unlock(slice); + } + + status |= cs4224_reg_get(die, CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS, + &data0); + if (data0 == 0x1) { + status |= cs4224_reg_get(die, CS4224_GLOBAL_DWNLD_CHECKSUM_HW, + &data0); + status |= cs4224_reg_get(die, CS4224_GLOBAL_DWNLD_CHECKSUM_SW, + &data1); + CS_TRACE( + ("ERROR: Comms issue! checksum: img=0x%04x,hw=0x%04x\n", + data1, data0)); + status |= CS_ERROR; + } + + return status; +} + +unsigned int cs4224_calc_crc16(unsigned int input_data, unsigned int crc_init) +{ + unsigned int i, j, crc; + unsigned int tmp, msb, data = 0; + + crc = crc_init & 0x0000ffff; + + for (i = 0; i < 4; i++) { + if (i == 0) + data = (input_data & 0xff000000) >> 24; + if (i == 1) + data = (input_data & 0x00ff0000) >> 16; + if (i == 2) + data = (input_data & 0x0000ff00) >> 8; + if (i == 3) + data = (input_data & 0xff0000ff) >> 0; + + tmp = 0x000080; + + for (j = 0; j < 8; j++) { + msb = crc & 0x8000; + crc <<= 1; + crc &= 0x0000ffff; + if (data & tmp) + msb ^= 0x00008000; + if (msb) + crc ^= 0x1021; + tmp >>= 1; + } + } + return crc; +} + +enum e_cs4224_ucode_crc16_t { + CS4224_UCODE_PRE_CRC16_CALC = 1, /* Pre CRC-16 calculation state */ + CS4224_UCODE_ACTIVE_CRC16_CALC = 2, /* CRC-16 calculation state */ + CS4224_UCODE_POST_CRC16_CALC = 3, /* Post CRC-16 calculation state */ +}; + +int cs4224_ucode_data_prgm_image_broadcast(unsigned int slice, + unsigned short microcode[], + unsigned int len_buffer) +{ + unsigned int i; + int status = CS_OK; + int tmp_status = CS_OK; + unsigned short checksum, data; + unsigned int crc_sw = 0xffff; + unsigned int crc_hw = 0xffff; + unsigned int input_data_hw, input_data_sw; + enum e_cs4224_ucode_crc16_t crc_sm = CS4224_UCODE_PRE_CRC16_CALC; + + /* upper bits of slice used to pick chip being used */ + unsigned int upper_bits = slice & 0xffffff00; + + if (!microcode || len_buffer == 0) + return CS_ERROR; + + /* Ensure the MDIO timeout is increased on both dies, Bugzilla 35875 */ + status |= cs4224_reg_set(0 | upper_bits, CS4224_GLOBAL_MDIO_CONFIG, + CS4224_GLOBAL_MDIO_CONFIG_pref); + status |= cs4224_reg_set(1 | upper_bits, CS4224_GLOBAL_MDIO_CONFIG, + CS4224_GLOBAL_MDIO_CONFIG_pref); + + /* config to broadcast to both dies */ + data = 0x0100; + + /* force die 1 to listen to die 0's address */ + /* ignore the status returned by the reg set since an I2C transaction + * will fail to get the checksum + */ + cs4224_reg_set(1 | upper_bits, CS4224_GLOBAL_BROADCAST, data); + + if (status != CS_OK) + return status; + + for (i = 0; i < len_buffer; i += 2) { + unsigned short addr = microcode[i]; + unsigned short data = microcode[i + 1]; + + if (addr == CS4224_EEPROM_MICRO_ACCESS_CONTROL) { + CS_TRACE(("ERROR: Cannot program the EEPROM bcast!\n")); + + /* disable broadcasting to both dies */ + cs4224_reg_set(0 | upper_bits, CS4224_GLOBAL_BROADCAST, + 0x0000); + + return CS_ERROR; + } + + if (crc_sm == CS4224_UCODE_ACTIVE_CRC16_CALC) { + /* calculate our own crc that will mirror the one in + * the image, without the below BROADCAST trap + */ + input_data_sw = (addr << 16) + data; + crc_sw = cs4224_calc_crc16(input_data_sw, crc_sw); + } + + if (addr == CS4224_GLOBAL_BROADCAST) { + /* intercept to ensure the broadcast bit remains set */ + data |= 0x0100; + } + + if (crc_sm == CS4224_UCODE_ACTIVE_CRC16_CALC) { + /* calculate our own crc that that will mirror the + * HW calculated one, + * with the above BROADCAST trap + */ + input_data_hw = (addr << 16) + data; + crc_hw = cs4224_calc_crc16(input_data_hw, crc_hw); + } + + cs4224_lock(slice); + + /* Program hw here */ + tmp_status = cs4224_reg_set(0 | upper_bits, addr, data); + + cs4224_unlock(slice); + + if (addr != CS4224_GLOBAL_BROADCAST) { + /* ignore the status of writes to BROADCAST */ + status |= tmp_status; + } + + if (status != CS_OK) { + /* some kind of legitimate write issue */ + CS_TRACE( + ("ERROR: cs4224_reg_set(0x%x, 0x%x, 0x%x)\n", + upper_bits, + addr, + data)); + + /* disable broadcasting to both dies */ + cs4224_reg_set(0 | upper_bits, CS4224_GLOBAL_BROADCAST, + 0x0000); + + return CS_ERROR; + } + + /* update our checksum calculator state machine */ + if (addr == CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL) { + if (data == 0x0001) { + /* HW CRC-16 calculator enabled */ + crc_sm = CS4224_UCODE_ACTIVE_CRC16_CALC; + } else { + /* HW CRC-16 calculator disabled */ + crc_sm = CS4224_UCODE_POST_CRC16_CALC; + } + } + } + + /* disable broadcasting to both dies */ + status |= cs4224_reg_set(0 | upper_bits, CS4224_GLOBAL_BROADCAST, + 0x0000); + + /* get the image checksum */ + status |= cs4224_reg_get(0 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_SW, + &checksum); + + /* compare our mirror checksum with the image checksum, this + * checks that OUR program memory or wherever we got the image from + * isn't corrupted + */ + if (crc_sw != checksum) { + CS_TRACE(("ERROR: (image corrupt?),calc=0x%04x, image=0x%04x\n", + crc_sw, + checksum)); + status |= CS_ERROR; + } + + /* write our calculated hardware checksum to CHECKSUM_SW reg so the + * CHECKSUM_STATUS clears + */ + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_SW, + crc_hw); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_SW, + crc_hw); + + /* check that the chip hw checksum and our calculated + * crc_hw checksum match + */ + status |= cs4224_reg_get(0 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS, + &data); + if (data == 0x1) { + status |= cs4224_reg_get(0 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_HW, + &checksum); + CS_TRACE(("ERROR: Comms issue checksum calc=0x%04x,hw=0x%04x\n", + crc_hw, + checksum)); + status |= CS_ERROR; + } + + status |= cs4224_reg_get(1 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS, + &data); + if (data == 0x1) { + status |= cs4224_reg_get(1 | upper_bits, + CS4224_GLOBAL_DWNLD_CHECKSUM_HW, + &checksum); + CS_TRACE(("ERROR: checksum match, calc=0x%04x, hw=0x%04x\n", + crc_hw, + checksum)); + status |= CS_ERROR; + } + + if (status != CS_OK) { + /* Clear the timestamps */ + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP0, + 0x0); + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP1, + 0x0); + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP2, + 0x0); + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_VERSION_KR, + 0x0); + status |= cs4224_reg_set(0 | upper_bits, + CS4224_GLOBAL_UCODE_VERSION_FC, + 0x0); + + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP0, + 0x0); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP1, + 0x0); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_TIMESTAMP2, + 0x0); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_VERSION_KR, + 0x0); + status |= cs4224_reg_set(1 | upper_bits, + CS4224_GLOBAL_UCODE_VERSION_FC, + 0x0); + } + + return status; +} + +#endif /* !CS_SKIP_UCODE_DOWNLOAD */ diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c index 1a38c29469a..1192915ee52 100644 --- a/drivers/net/phy/fixed.c +++ b/drivers/net/phy/fixed.c @@ -15,18 +15,42 @@ DECLARE_GLOBAL_DATA_PTR; -int fixedphy_probe(struct phy_device *phydev) +static int fixedphy_probe(struct phy_device *phydev) { + /* fixed-link phy must not be reset by core phy code */ + phydev->flags |= PHY_FLAG_BROKEN_RESET; + + return 0; +} + +static int fixedphy_config(struct phy_device *phydev) +{ + ofnode node = phy_get_ofnode(phydev); struct fixed_link *priv; - int ofnode = phydev->addr; + bool old_binding = false; + u32 old_val[5]; u32 val; + if (!ofnode_valid(node)) + return -EINVAL; + /* check for mandatory properties within fixed-link node */ - val = fdt_getprop_u32_default_node(gd->fdt_blob, - ofnode, 0, "speed", 0); + val = ofnode_read_u32_default(node, "speed", 0); + + if (!val) { + /* try old binding */ + old_binding = true; + if (ofnode_read_u32_array(node, "fixed-link", old_val, + ARRAY_SIZE(old_val))) { + printf("ERROR: no/invalid property!\n"); + return -ENOENT; + } + val = old_val[2]; + } + if (val != SPEED_10 && val != SPEED_100 && val != SPEED_1000 && val != SPEED_2500 && val != SPEED_10000) { - printf("ERROR: no/invalid speed given in fixed-link node!"); + printf("ERROR: no/invalid speed given in fixed-link node!\n"); return -EINVAL; } @@ -38,17 +62,20 @@ int fixedphy_probe(struct phy_device *phydev) phydev->priv = priv; priv->link_speed = val; - priv->duplex = fdtdec_get_bool(gd->fdt_blob, ofnode, "full-duplex"); - priv->pause = fdtdec_get_bool(gd->fdt_blob, ofnode, "pause"); - priv->asym_pause = fdtdec_get_bool(gd->fdt_blob, ofnode, "asym-pause"); - - /* fixed-link phy must not be reset by core phy code */ - phydev->flags |= PHY_FLAG_BROKEN_RESET; + if (!old_binding) { + priv->duplex = ofnode_read_bool(node, "full-duplex"); + priv->pause = ofnode_read_bool(node, "pause"); + priv->asym_pause = ofnode_read_bool(node, "asym-pause"); + } else { + priv->duplex = old_val[1]; + priv->pause = old_val[3]; + priv->asym_pause = old_val[4]; + } return 0; } -int fixedphy_startup(struct phy_device *phydev) +static int fixedphy_startup(struct phy_device *phydev) { struct fixed_link *priv = phydev->priv; @@ -61,7 +88,7 @@ int fixedphy_startup(struct phy_device *phydev) return 0; } -int fixedphy_shutdown(struct phy_device *phydev) +static int fixedphy_shutdown(struct phy_device *phydev) { return 0; } @@ -72,6 +99,7 @@ static struct phy_driver fixedphy_driver = { .name = "Fixed PHY", .features = PHY_GBIT_FEATURES | SUPPORTED_MII, .probe = fixedphy_probe, + .config = fixedphy_config, .startup = fixedphy_startup, .shutdown = fixedphy_shutdown, }; diff --git a/drivers/net/phy/in112525.c b/drivers/net/phy/in112525.c new file mode 100644 index 00000000000..026a82e9798 --- /dev/null +++ b/drivers/net/phy/in112525.c @@ -0,0 +1,1089 @@ +/* + * Copyright 2018-2021 NXP + * Copyright 2018 INPHI + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Inphi is a registered trademark of Inphi Corporation + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_SYS_IN112525_FW_IN_MMC +#include +#endif + +#ifndef CONFIG_PHYLIB_10G +#error The INPHI PHY needs 10G support +#endif + +/* lookup table to map the multiply options and MUX selects to the bit values */ +unsigned char tx_pll_mpy_map[][2] = { + /* MPY MS, LS */ + [10] = {0, 0}, + [20] = {1, 0}, + [40] = {2, 0}, + [8] = {0, 1}, + [16] = {1, 1}, + [32] = {2, 1}, + [33] = {1, 6}, + [66] = {2, 6}, + [15] = {0, 7}, + [30] = {1, 7}, + [60] = {2, 7}, +}; + +static struct in112525_config inphi_s03_config[] = { + [INIT_OC192] = { .enable_otu_protocol = 0, + .enable_external_refclk = 0, + .enable_prescaler = 0, + .tx_pll_mpy_ratio = 20, + .enable_half_rate = 1, + .enable_extended_range = 1, + .tx_pll_refclk_source = RECOV_CLK, + .ctle_mode = MODE_25_25_10, + .rx_common_mode = 3, + .rx_odt_override = 0, + .l0_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l1_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l2_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l3_phase_adjust_val = IN112525_PHASE_ADJUST_VAL + }, + + [INIT_10GE] = { .enable_otu_protocol = 0, + .enable_external_refclk = 0, + .enable_prescaler = 0, + .tx_pll_mpy_ratio = 20, + .enable_half_rate = 1, + .enable_extended_range = 1, + .tx_pll_refclk_source = RECOV_CLK, + .ctle_mode = MODE_25_25_10, + .rx_common_mode = 3, + .rx_odt_override = 0, + .l0_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l1_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l2_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l3_phase_adjust_val = IN112525_PHASE_ADJUST_VAL + }, + + [INIT_16GFC] = { .enable_otu_protocol = 0, + .enable_external_refclk = 0, + .enable_prescaler = 0, + .tx_pll_mpy_ratio = 20, + .enable_half_rate = 1, + .enable_extended_range = 1, + .tx_pll_refclk_source = RECOV_CLK, + .ctle_mode = MODE_25_25_10, + .rx_common_mode = 3, + .rx_odt_override = 0, + .l0_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l1_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l2_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l3_phase_adjust_val = IN112525_PHASE_ADJUST_VAL + }, + + [INIT_20GE] = { .enable_otu_protocol = 0, + .enable_external_refclk = 0, + .enable_prescaler = 0, + .tx_pll_mpy_ratio = 10, + .enable_half_rate = 0, + .enable_extended_range = 1, + .tx_pll_refclk_source = RECOV_CLK, + .ctle_mode = MODE_25_25_10, + .rx_common_mode = 3, + .rx_odt_override = 0, + .l0_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l1_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l2_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l3_phase_adjust_val = IN112525_PHASE_ADJUST_VAL + }, + + [INIT_100GE] = { .enable_otu_protocol = 0, + .enable_external_refclk = 0, + .enable_prescaler = 0, + .tx_pll_mpy_ratio = 10, + .enable_half_rate = 0, + .enable_extended_range = 0, + .tx_pll_refclk_source = RECOV_CLK, + .ctle_mode = MODE_25_25_10, + .rx_common_mode = 3, + .rx_odt_override = 0, + .l0_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l1_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l2_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l3_phase_adjust_val = IN112525_PHASE_ADJUST_VAL + }, + + [INIT_25GE] = { .enable_otu_protocol = 0, + .enable_external_refclk = 0, + .enable_prescaler = 0, + .tx_pll_mpy_ratio = 10, + .enable_half_rate = 0, + .enable_extended_range = 0, + .tx_pll_refclk_source = RECOV_CLK, + .ctle_mode = MODE_25_25_10, + .rx_common_mode = 3, + .rx_odt_override = 0, + .l0_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l1_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l2_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l3_phase_adjust_val = IN112525_PHASE_ADJUST_VAL + }, + + [INIT_OTU4] = { .enable_otu_protocol = 1, + .enable_external_refclk = 0, + .enable_prescaler = 0, + .tx_pll_mpy_ratio = 10, + .enable_half_rate = 0, + .enable_extended_range = 0, + .tx_pll_refclk_source = RECOV_CLK, + .ctle_mode = MODE_25_25_10, + .rx_common_mode = 3, + .rx_odt_override = 0, + .l0_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l1_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l2_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l3_phase_adjust_val = IN112525_PHASE_ADJUST_VAL + }, + + [INIT_32GFC] = { .enable_otu_protocol = 0, + .enable_external_refclk = 0, + .enable_prescaler = 0, + .tx_pll_mpy_ratio = 10, + .enable_half_rate = 0, + .enable_extended_range = 0, + .tx_pll_refclk_source = RECOV_CLK, + .ctle_mode = MODE_25_25_10, + .rx_common_mode = 3, + .rx_odt_override = 0, + .l0_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l1_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l2_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l3_phase_adjust_val = IN112525_PHASE_ADJUST_VAL + }, + + [INIT_F28P2G] = { .enable_otu_protocol = 0, + .enable_external_refclk = 0, + .enable_prescaler = 0, + .tx_pll_mpy_ratio = 10, + .enable_half_rate = 0, + .enable_extended_range = 0, + .tx_pll_refclk_source = RECOV_CLK, + .ctle_mode = MODE_25_25_10, + .rx_common_mode = 3, + .rx_odt_override = 0, + .l0_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l1_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l2_phase_adjust_val = IN112525_PHASE_ADJUST_VAL, + .l3_phase_adjust_val = IN112525_PHASE_ADJUST_VAL + } +}; + +static struct in112525_s03_vco_codes s03_vco_codes; + +#ifdef CONFIG_IN112525_S03_25G +#define CURRENT_CONFIG (inphi_s03_config[INIT_25GE]) +#else +#define CURRENT_CONFIG (inphi_s03_config[INIT_10GE]) +#endif + +#define ALL_LANES 4 +#define mdio_wr(a, b) phy_write(inphi_phydev, MDIO_MMD_VEND1, (a), (b)) +#define mdio_rd(a) phy_read(inphi_phydev, MDIO_MMD_VEND1, (a)) + +struct phy_device *inphi_phydev; + +int in112525_upload_firmware(struct phy_device *phydev) +{ + char line_temp[0x50] = {0}; + char reg_addr[0x50] = {0}; + char reg_data[0x50] = {0}; + int i, line_cnt = 0, column_cnt = 0; + struct in112525_reg_config fw_temp; + char *addr = NULL; + + addr = (char *)IN112525_FW_ADDR; + +#if defined(CONFIG_SYS_IN112525_FW_IN_MMC) + int dev = CONFIG_SYS_MMC_ENV_DEV; + u32 cnt = IN112525_FW_LENGTH / 512; + u32 blk = IN112525_FW_ADDR / 512; + struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + + if (!mmc) { + puts("Failed to find MMC device for IN112525 ucode\n"); + } else { + addr = malloc(IN112525_FW_LENGTH); + printf("MMC read: dev # %u, block # %u, count %u ...\n", + dev, blk, cnt); + mmc_init(mmc); + (void)mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, + addr); + /* flush cache after read */ + flush_cache((ulong)addr, cnt * 512); + } +#endif + while (*addr != 'Q') { + i = 0; + + while (*addr != 0xa) { + line_temp[i++] = *addr++; + if (i > 0x50) { + printf("IN112525 ucode not found @ 0x%p\n", + (char *)IN112525_FW_ADDR); + return -1; + } + } + + addr++; /* skip '\n' */ + line_cnt++; + column_cnt = i; + line_temp[column_cnt] = '\0'; + + if (line_cnt > IN112525_FW_LENGTH) { + printf("IN112525 ucode not found @ 0x%p\n", + (char *)IN112525_FW_ADDR); + return -1; + } + for (i = 0; i < column_cnt; i++) { + if (isspace(line_temp[i++])) + break; + } + + memcpy(reg_addr, line_temp, i); + memcpy(reg_data, &line_temp[i], column_cnt - i); + strim(reg_addr); + strim(reg_data); + fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; + fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & + 0xffff; + /* check if garbage is present at ucode location */ + if (fw_temp.reg_addr < 0x700) { + printf("IN112525 ucode not found @ 0x%p\n", + (char *)IN112525_FW_ADDR); + return -1; + } + phy_write(phydev, MDIO_MMD_VEND1, fw_temp.reg_addr, + fw_temp.reg_value); + } + return 0; +} + +int in112525_s05_phy_init(struct phy_device *phydev) +{ + u32 reg_value, ret; + u32 l0_vco_code, l1_vco_code, l2_vco_code, l3_vco_code; + + phy_write(phydev, MDIO_MMD_VEND1, PHYMISC_REG11, 0); + phy_write(phydev, MDIO_MMD_VEND1, PHYMISC_REG11, IN112525_FORCE_PC); + phy_write(phydev, MDIO_MMD_VEND1, PHYMISC_REG11, IN112525_LOL_CTRL); + + /* The S05 retimer seems to work only when ALL lanes are locked. + * Datapath is Lane0<->Lane1, Lane2<->Lane3. + * For individual lane operation to work, pair 0-1 must be disabled + */ + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG0, + IN112525_MDIOINIT | IN112525_HRESET | +#if defined(CONFIG_IN112525_S05_10G) || defined(CONFIG_IN112525_S05_25G) + IN112525_LANE0_DISABLE | IN112525_LANE1_DISABLE | +#endif + IN112525_SRESET + ); + + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG0, + IN112525_HRESET | +#if defined(CONFIG_IN112525_S05_10G) || defined(CONFIG_IN112525_S05_25G) + IN112525_LANE0_DISABLE | IN112525_LANE1_DISABLE | +#endif + IN112525_SRESET + ); + + phy_write(phydev, MDIO_MMD_VEND1, PHYMISC_REG3, + IN112525_EXT_REFCLK_EN | IN112525_CTLE_10G); + + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG0, +#if defined(CONFIG_IN112525_S05_10G) || defined(CONFIG_IN112525_S05_25G) + IN112525_LANE0_DISABLE | IN112525_LANE1_DISABLE | +#endif + IN112525_SRESET); + + mdelay(10); + + reg_value = phy_read(phydev, MDIO_MMD_VEND1, IN112525_EFUSE_REG); + if (!(reg_value & IN112525_EFUSE_DONE)) { + printf("IN112525 phy init failed: EFUSE Done not set\n"); + return -1; + } + + udelay(100); + + reg_value = phy_read(phydev, MDIO_MMD_VEND1, PHYMISC_REG2); + if (!(reg_value & IN112525_CALIBRATION_DONE)) { + printf("IN112525 phy init failed: CAL DONE not set\n"); + return -1; + } + + phy_write(phydev, MDIO_MMD_VEND1, PHYMISC_REG2, + (IN112525_RX_PLL_RESET | IN112525_TX_PLL_RESET | + IN112525_CORE_DATAPATH_RESET | IN112525_TX_SERDES_RESET)); + + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG0, + IN112525_MANUALRESET_SELECT | +#if defined(CONFIG_IN112525_S05_10G) || defined(CONFIG_IN112525_S05_25G) + IN112525_LANE0_DISABLE | IN112525_LANE1_DISABLE | +#endif + IN112525_SRESET); + +#if defined(CONFIG_IN112525_S05_25G) || defined(CONFIG_IN112525_S05_50G) + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG15, PHYCTRL_REG15_VAL); + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG17, PHYCTRL_REG17_VAL); +#else + /* 100G requires specific extended-range settings */ + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG15, PHYCTRL_REG15_VAL_EXT); + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG17, PHYCTRL_REG17_VAL_EXT); +#endif + + /* chip internals */ + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG18, 0xff); + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG19, 0x2d); + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG19, 0x802d); + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG19, 0x0); + + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG18, 0xe9); + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG19, 0x8); + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG19, 0x8008); + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG19, 0x0); + + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG11, + IN112525_TXPLL_MSDIV | IN112525_TXPLL_IQDIV); + +#if defined(CONFIG_IN112525_S05_10G) || defined(CONFIG_IN112525_S05_40G) + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG14, + IN112525_RX_HALFRATE_EN); + + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG13, PHYCTRL_REG13_VAL); + + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG20, + IN112525_RX_LOS_EN | IN112525_RX_LOS_10G_THRESHOLD); + + phy_write(phydev, MDIO_MMD_VEND1, PHYMISC_REG30, + IN112525_RX_MISC_TRIM1_VAL); +#else + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG13, + PHYCTRL_REG13_VAL | IN112525_LOSD_HYSTERESIS_EN); + + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG20, + IN112525_RX_LOS_EN | IN112525_RX_LOS_100G_THRESHOLD); +#endif + phy_write(phydev, MDIO_MMD_VEND1, PHYMISC_REG8, IN112525_FA_WIN_SIZE); + +#if !defined(CONFIG_IN112525_S05_10G) && !defined(CONFIG_IN112525_S05_40G) + /* specific stuff required when not in half-rate operation before + * reading VCO codes + */ + phy_write(phydev, MDIO_MMD_VEND1, PHYCTRL_REG2, 0x5000); + phy_write(phydev, MDIO_MMD_VEND1, 0x501, 0x0200); + phy_write(phydev, MDIO_MMD_VEND1, 0x510, 0x001F); + phy_write(phydev, MDIO_MMD_VEND1, 0x517, 0x803F); +#endif + + /* actual VCO codes reading; save codes for later */ + l0_vco_code = phy_read(phydev, MDIO_MMD_VEND1, PHYMISC_REG7); + l1_vco_code = phy_read(phydev, MDIO_MMD_VEND1, PHYMISC_REG7 + 0x100); + l2_vco_code = phy_read(phydev, MDIO_MMD_VEND1, PHYMISC_REG7 + 0x200); + l3_vco_code = phy_read(phydev, MDIO_MMD_VEND1, PHYMISC_REG7 + 0x300); + + +#if defined(CONFIG_IN112525_S05_10G) || defined(CONFIG_IN112525_S05_40G) + /* adjust VCOs with 20/25 ratio when in half-rate operation */ + l0_vco_code *= 0.8; + l1_vco_code *= 0.8; + l2_vco_code *= 0.8; + l3_vco_code *= 0.8; + +#endif + + ret = in112525_upload_firmware(phydev); + if (ret) { + printf("IN112525: upload firmware failed\n"); + return -1; + } + + phy_write(phydev, MDIO_MMD_VEND1, 0x73b, l0_vco_code); + phy_write(phydev, MDIO_MMD_VEND1, 0x73c, l1_vco_code); + phy_write(phydev, MDIO_MMD_VEND1, 0x73d, l2_vco_code); + phy_write(phydev, MDIO_MMD_VEND1, 0x73e, l3_vco_code); + + phy_write(phydev, MDIO_MMD_VEND1, 0x737, IN112525_PHASE_ADJUST_VAL); + phy_write(phydev, MDIO_MMD_VEND1, 0x738, IN112525_PHASE_ADJUST_VAL); + phy_write(phydev, MDIO_MMD_VEND1, 0x739, IN112525_PHASE_ADJUST_VAL); + phy_write(phydev, MDIO_MMD_VEND1, 0x73a, IN112525_PHASE_ADJUST_VAL); + + phy_write(phydev, MDIO_MMD_VEND1, PHYMISC_REG12, IN112525_USEQ_FL); + + printf("IN112525: starting ucode...\n"); + phy_write(phydev, MDIO_MMD_VEND1, PHYMISC_REG11, + IN112525_LOL_CTRL | IN112525_USEQ_EN); + + return 0; +} + +int in112525_s05_config(struct phy_device *phydev) +{ + return in112525_s05_phy_init(phydev); +} + +int tx_pll_lock_test(int lane) +{ + int i, val, locked = 1; + + if (lane == ALL_LANES) { + for (i = 0; i < ALL_LANES; i++) { + val = mdio_rd(i * 0x100 + PHYSTAT_REG3); + locked = locked & bit_test(val, 15); + } + } else { + val = mdio_rd(lane * 0x100 + PHYSTAT_REG3); + locked = locked & bit_test(val, 15); + } + + return locked; +} + +void tx_pll_assert(int lane) +{ + int val, recal; + + if (lane == ALL_LANES) { + val = mdio_rd(PHYMISC_REG2); + recal = (1 << 12); + mdio_wr(PHYMISC_REG2, val | recal); + } else { + val = mdio_rd(lane * 0x100 + PHYCTRL_REG4); + recal = (1 << 15); + mdio_wr(lane * 0x100 + PHYCTRL_REG4, val | recal); + } +} + +void tx_pll_de_assert(int lane) +{ + int recal, val; + + if (lane == ALL_LANES) { + val = mdio_rd(PHYMISC_REG2); + recal = 0xefff; + mdio_wr(PHYMISC_REG2, val & recal); + } else { + val = mdio_rd(lane * 0x100 + PHYCTRL_REG4); + recal = 0x7fff; + mdio_wr(lane * 0x100 + PHYCTRL_REG4, val & recal); + } +} + +void tx_core_assert(int lane) +{ + int recal, val, val2, core_reset; + + if (lane == 4) { + val = mdio_rd(PHYMISC_REG2); + recal = 1 << 10; + mdio_wr(PHYMISC_REG2, val | recal); + } else { + val2 = mdio_rd(PHYMISC_REG3); + core_reset = (1 << (lane + 8)); + mdio_wr(PHYMISC_REG3, val2 | core_reset); + } +} + +void lol_disable(int lane) +{ + int val, mask; + + val = mdio_rd(PHYMISC_REG3); + mask = 1 << (lane + 4); + mdio_wr(PHYMISC_REG3, val | mask); +} + +void tx_core_de_assert(int lane) +{ + int val, recal, val2, core_reset; + + if (lane == ALL_LANES) { + val = mdio_rd(PHYMISC_REG2); + recal = 0xffff - (1 << 10); + mdio_wr(PHYMISC_REG2, val & recal); + } else { + val2 = mdio_rd(PHYMISC_REG3); + core_reset = 0xffff - (1 << (lane + 8)); + mdio_wr(PHYMISC_REG3, val2 & core_reset); + } +} + +void tx_restart(int lane) +{ + tx_core_assert(lane); + tx_pll_assert(lane); + tx_pll_de_assert(lane); + WAIT(150); + tx_core_de_assert(lane); +} + +void disable_lane(int lane) +{ + rx_reset_assert(lane); + rx_powerdown_assert(lane); + tx_core_assert(lane); + lol_disable(lane); +} + +void WAIT(int delay_cycles) +{ + udelay(delay_cycles * 10); +} + +int bit_test(int value, int bit_field) +{ + int bit_mask = (1 << bit_field); + int result; + + result = ((value & bit_mask) == bit_mask); + return result; +} + +void toggle_reset(int lane) +{ + int reg, val, orig; + + if (lane == ALL_LANES) { + mdio_wr(PHYMISC_REG2, 0x8000); + WAIT(10); + mdio_wr(PHYMISC_REG2, 0x0000); + } else { + reg = lane * 0x100 + PHYCTRL_REG8; + val = (1 << 6); + orig = mdio_rd(reg); + mdio_wr(reg, orig + val); + WAIT(10); + mdio_wr(reg, orig); + } +} + +int az_complete_test(int lane) +{ + int success = 1, value; + + if (lane == 0 || lane == ALL_LANES) { + value = mdio_rd(PHYCTRL_REG5); + success = success & bit_test(value, 2); + } + if (lane == 1 || lane == ALL_LANES) { + value = mdio_rd(PHYCTRL_REG5 + 0x100); + success = success & bit_test(value, 2); + } + if (lane == 2 || lane == ALL_LANES) { + value = mdio_rd(PHYCTRL_REG5 + 0x200); + success = success & bit_test(value, 2); + } + if (lane == 3 || lane == ALL_LANES) { + value = mdio_rd(PHYCTRL_REG5 + 0x300); + success = success & bit_test(value, 2); + } + + return success; +} + +void rx_reset_assert(int lane) +{ + int mask, val; + + if (lane == ALL_LANES) { + val = mdio_rd(PHYMISC_REG2); + mask = (1 << 15); + mdio_wr(PHYMISC_REG2, val + mask); + } else { + val = mdio_rd(lane * 0x100 + PHYCTRL_REG8); + mask = (1 << 6); + mdio_wr(lane * 0x100 + PHYCTRL_REG8, val + mask); + } +} + +void rx_reset_de_assert(int lane) +{ + int mask, val; + + if (lane == ALL_LANES) { + val = mdio_rd(PHYMISC_REG2); + mask = 0xffff - (1 << 15); + mdio_wr(PHYMISC_REG2, val & mask); + } else { + val = mdio_rd(lane*0x100 + PHYCTRL_REG8); + mask = 0xffff - (1 << 6); + mdio_wr(lane*0x100 + PHYCTRL_REG8, val & mask); + } +} + +void rx_powerdown_assert(int lane) +{ + int mask, val; + + val = mdio_rd(lane * 0x100 + PHYCTRL_REG8); + mask = (1 << 5); + mdio_wr(lane * 0x100 + PHYCTRL_REG8, val + mask); +} + +void rx_powerdown_de_assert(int lane) +{ + int mask, val; + + val = mdio_rd(lane * 0x100 + PHYCTRL_REG8); + mask = 0xffff - (1 << 5); + mdio_wr(lane * 0x100 + PHYCTRL_REG8, val & mask); +} + +void save_vco_codes(int lane) +{ + int value0, value1, value2, value3; + + if (lane == 0 || lane == ALL_LANES) { + value0 = mdio_rd(PHYMISC_REG5); + mdio_wr(PHYMISC_REG7, value0 + IN112525_RX_VCO_CODE_OFFSET); + s03_vco_codes.l0_vco_code = value0; + } + if (lane == 1 || lane == ALL_LANES) { + value1 = mdio_rd(PHYMISC_REG5 + 0x100); + mdio_wr(PHYMISC_REG7 + 0x100, + value1 + IN112525_RX_VCO_CODE_OFFSET); + s03_vco_codes.l1_vco_code = value1; + } + if (lane == 2 || lane == ALL_LANES) { + value2 = mdio_rd(PHYMISC_REG5 + 0x200); + mdio_wr(PHYMISC_REG7 + 0x200, + value2 + IN112525_RX_VCO_CODE_OFFSET); + s03_vco_codes.l2_vco_code = value2; + } + if (lane == 3 || lane == ALL_LANES) { + value3 = mdio_rd(PHYMISC_REG5 + 0x300); + mdio_wr(PHYMISC_REG7 + 0x300, + value3 + IN112525_RX_VCO_CODE_OFFSET); + s03_vco_codes.l3_vco_code = value3; + } +} + +void save_az_offsets(int lane) +{ + int i; + +#define AZ_OFFSET_LANE_UPDATE(reg, lane) \ + mdio_wr((reg) + (lane) * 0x100, \ + (mdio_rd((reg) + (lane) * 0x100) >> 8)) + + if (lane == ALL_LANES) { + for (i = 0; i < ALL_LANES; i++) { + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG20, i); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG20 + 1, i); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG20 + 2, i); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG20 + 3, i); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG21, i); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG21 + 1, i); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG21 + 2, i); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG21 + 3, i); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG22, i); + } + } else { + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG20, lane); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG20 + 1, lane); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG20 + 2, lane); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG20 + 3, lane); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG21, lane); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG21 + 1, lane); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG21 + 2, lane); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG21 + 3, lane); + AZ_OFFSET_LANE_UPDATE(PHYMISC_REG22, lane); + } + + mdio_wr(PHYCTRL_REG7, 0x0001); +} + +int in112525_s03_lane_recovery(int lane) +{ + int i, value, az_pass; + + switch (lane) { + case 0: + case 1: + case 2: + case 3: + rx_reset_assert(lane); + WAIT(2000); + break; + case ALL_LANES: + mdio_wr(PHYMISC_REG2, 0x9C00); + WAIT(2000); + while (1) { + value = mdio_rd(PHYMISC_REG2); + if (bit_test(value, 4)) + break; + } + break; + default: + dev_err(inphi_phydev->dev, + "Incorrect usage of APIs in %s driver\n", + inphi_phydev->drv->name); + break; + } + + if (lane == 0 || lane == ALL_LANES) + mdio_wr(PHYMISC_REG7, L0_VCO_CODE_trim); + if (lane == 1 || lane == ALL_LANES) + mdio_wr(PHYMISC_REG7 + 0x100, L1_VCO_CODE_trim); + if (lane == 2 || lane == ALL_LANES) + mdio_wr(PHYMISC_REG7 + 0x200, L2_VCO_CODE_trim); + if (lane == 3 || lane == ALL_LANES) + mdio_wr(PHYMISC_REG7 + 0x300, L3_VCO_CODE_trim); + + if (lane == 0 || lane == 4) + mdio_wr(PHYCTRL_REG5, 0x0418); + if (lane == 1 || lane == 4) + mdio_wr(PHYCTRL_REG5 + 0x100, 0x0418); + if (lane == 2 || lane == 4) + mdio_wr(PHYCTRL_REG5 + 0x200, 0x0418); + if (lane == 3 || lane == 4) + mdio_wr(PHYCTRL_REG5 + 0x300, 0x0418); + + mdio_wr(PHYCTRL_REG7, 0x0000); + rx_reset_de_assert(lane); + + if (lane == 0 || lane == 4) { + mdio_wr(PHYCTRL_REG5, 0x0410); + mdio_wr(PHYCTRL_REG5, 0x0412); + } + if (lane == 1 || lane == 4) { + mdio_wr(PHYCTRL_REG5 + 0x100, 0x0410); + mdio_wr(PHYCTRL_REG5 + 0x100, 0x0412); + } + if (lane == 2 || lane == 4) { + mdio_wr(PHYCTRL_REG5 + 0x200, 0x0410); + mdio_wr(PHYCTRL_REG5 + 0x200, 0x0412); + } + if (lane == 3 || lane == 4) { + mdio_wr(PHYCTRL_REG5 + 0x300, 0x0410); + mdio_wr(PHYCTRL_REG5 + 0x300, 0x0412); + } + + for (i = 0; i < 64; i++) { + /* wait 1000 times 10us */ + WAIT(10000); + az_pass = az_complete_test(lane); + if (az_pass) { + save_az_offsets(lane); + break; + } + } + + if (!az_pass) { + debug("auto-zero calibration timed out for lane %d\n", lane); + return 0; + } + + mdio_wr(lane * 0x100 + PHYMISC_REG4, 0x0002); + mdio_wr(lane * 0x100 + PHYMISC_REG6, 0x2028); + mdio_wr(lane * 0x100 + PHYCTRL_REG5, 0x0010); + WAIT(100); + mdio_wr(lane * 0x100 + PHYCTRL_REG5, 0x0110); + WAIT(3000); + mdio_wr(lane * 0x100 + PHYMISC_REG6, 0x3020); + + if (lane == ALL_LANES) { + mdio_wr(PHYMISC_REG2, 0x1C00); + mdio_wr(PHYMISC_REG2, 0x0C00); + } else { + tx_restart(lane); + /* delay > 10ms is required */ + WAIT(1100); + } + + if (lane == ALL_LANES) { + if (bit_test(mdio_rd(PHYMISC_REG2), 6) == 0) + debug("TX PLL not locked on ALL lanes\n"); + } else { + if (tx_pll_lock_test(lane) == 0) { + debug("TX PLL not locked on lane %d\n", lane); + return -1; + } + } + + save_vco_codes(lane); + + if (lane == ALL_LANES) { + mdio_wr(PHYMISC_REG2, 0x0400); + mdio_wr(PHYMISC_REG2, 0x0000); + value = mdio_rd(PHYCTRL_REG1); + value = value & 0xffbf; + mdio_wr(PHYCTRL_REG2, value); + } else { + tx_core_de_assert(lane); + } + + if (lane == ALL_LANES) { + mdio_wr(PHYMISC_REG1, 0x8000); + mdio_wr(PHYMISC_REG1, 0x0000); + } + + mdio_rd(PHYMISC_REG1); + mdio_rd(PHYMISC_REG1); + + WAIT(100); + mdio_rd(PHYSTAT_REG1); + mdio_rd(PHYSTAT_REG2); + + return 0; +} + +int in112525_s03_phy_init(struct phy_device *phydev) +{ + u32 reg_value; + u32 reg; + int i; + int tx_pll_MSDIV_value; + int tx_pll_LSDIV_value; + int tx_pll_iqdiv; + int tx_pll_ctrl2_value; + + /* put the chip in hw/sw and MDIO reset */ + mdio_wr(PHYCTRL_REG0, + IN112525_HRESET | IN112525_SRESET | IN112525_MDIOINIT); + + /* de-assert MDIO init */ + mdio_wr(PHYCTRL_REG0, IN112525_HRESET | IN112525_SRESET); + + /* apply configuration */ + if (CURRENT_CONFIG.enable_prescaler) + mdio_wr(IN112525_PRESCALE_20M, 0x0001); + + if (CURRENT_CONFIG.enable_external_refclk) + mdio_wr(PHYMISC_REG3, (1 << 15)); + else + mdio_wr(PHYMISC_REG3, 0x0); + + mdio_wr(PHYCTRL_REG0, IN112525_SRESET); + + WAIT(1000); + + reg_value = phy_read(phydev, MDIO_MMD_VEND1, IN112525_EFUSE_REG); + if (!(reg_value & IN112525_EFUSE_DONE)) { + puts("IN112525_s03 init failed: EFUSE Done not set\n"); + return -1; + } + WAIT(1000); + + reg_value = phy_read(phydev, MDIO_MMD_VEND1, PHYMISC_REG2); + if (!(reg_value & IN112525_CALIBRATION_DONE)) { + puts("IN112525_s03 init failed: CALIBRATION_DONE not set\n"); + return -1; + } + + mdio_wr(PHYMISC_REG2, + IN112525_RX_PLL_RESET | + IN112525_TX_PLL_RESET | + IN112525_TX_SERDES_RESET | + IN112525_CORE_DATAPATH_RESET); + + if (CURRENT_CONFIG.enable_otu_protocol) + mdio_wr(PHYCTRL_REG0, 0x8C00); + else + mdio_wr(PHYCTRL_REG0, 0x8200); + + if (CURRENT_CONFIG.enable_extended_range) { + mdio_wr(PHYCTRL_REG10, 0x2032); + printf("IN112525_s03 possible misconfig [ext range]\n"); + mdio_wr(PHYCTRL_REG12, 0x0007); + } else { + mdio_wr(PHYCTRL_REG10, 0xA02D); + mdio_wr(PHYCTRL_REG12, 0x0005); + } + + mdio_wr(PHYCTRL_REG18, 0x00ff); + mdio_wr(PHYCTRL_REG19, 0x002d); + mdio_wr(PHYCTRL_REG19, 0x802d); + mdio_wr(PHYCTRL_REG19, 0x0000); + mdio_wr(PHYCTRL_REG18, 0x00e9); + mdio_wr(PHYCTRL_REG19, 0x0008); + mdio_wr(PHYCTRL_REG19, 0x8008); + mdio_wr(PHYCTRL_REG19, 0x0000); + + tx_pll_MSDIV_value = tx_pll_mpy_map[CURRENT_CONFIG.tx_pll_mpy_ratio][0]; + tx_pll_LSDIV_value = tx_pll_mpy_map[CURRENT_CONFIG.tx_pll_mpy_ratio][1]; + tx_pll_iqdiv = (CURRENT_CONFIG.enable_half_rate) ? 1 : 0; + tx_pll_ctrl2_value = + (CURRENT_CONFIG.tx_pll_refclk_source << 11) + + (tx_pll_iqdiv << 8) + + (tx_pll_MSDIV_value << 4) + + tx_pll_LSDIV_value; + + mdio_wr(PHYCTRL_REG11, tx_pll_ctrl2_value); + + if (CURRENT_CONFIG.enable_half_rate) + mdio_wr(PHYCTRL_REG14, 0x0020); + + /* set the CTLE mode (bw on the front end stages) + * for example '25:25:10', '10:10:10' etc. + */ + for (i = 0; i < ALL_LANES; i++) { + reg = i * 0x100 + PHYCTRL_REG8; + reg_value = phy_read(phydev, MDIO_MMD_VEND1, reg); + reg_value = reg_value & 0xFF7C; + /* put bits 7,1,0 for EQ */ + reg_value = reg_value | CURRENT_CONFIG.ctle_mode; + mdio_wr(reg, reg_value); + } + + + /* rx common code settings */ + mdio_wr(PHYMISC_REG32, CURRENT_CONFIG.rx_common_mode); + mdio_wr(PHYMISC_REG32 + 0x100, CURRENT_CONFIG.rx_common_mode); + mdio_wr(PHYMISC_REG32 + 0x200, CURRENT_CONFIG.rx_common_mode - 1); + mdio_wr(PHYMISC_REG32 + 0x300, CURRENT_CONFIG.rx_common_mode - 1); + /* mdio_wr(PHYMISC_REG30, CURRENT_CONFIG.rx_common_mode); */ + + if (CURRENT_CONFIG.rx_odt_override) + mdio_wr(PHYMISC_REG31, CURRENT_CONFIG.rx_odt_override); + + s03_vco_codes.l0_vco_code = mdio_rd(PHYMISC_REG7); + s03_vco_codes.l1_vco_code = mdio_rd(PHYMISC_REG7 + 0x100); + s03_vco_codes.l2_vco_code = mdio_rd(PHYMISC_REG7 + 0x200); + s03_vco_codes.l3_vco_code = mdio_rd(PHYMISC_REG7 + 0x300); + + if (CURRENT_CONFIG.enable_extended_range) { + s03_vco_codes.l0_vco_code = + (int)(s03_vco_codes.l0_vco_code * 0.8); + s03_vco_codes.l1_vco_code = + (int)(s03_vco_codes.l1_vco_code * 0.8); + s03_vco_codes.l2_vco_code = + (int)(s03_vco_codes.l2_vco_code * 0.8); + s03_vco_codes.l3_vco_code = + (int)(s03_vco_codes.l3_vco_code * 0.8); + } + + mdio_wr(PHYMISC_REG2, 0x0); + WAIT(10000); + + /* start fresh */ + in112525_s03_lane_recovery(ALL_LANES); + + return 0; +} + +int in112525_s03_config(struct phy_device *phydev) +{ + inphi_phydev = phydev; + return in112525_s03_phy_init(phydev); +} + +int in112525_probe(struct phy_device *phydev) +{ + phydev->flags = PHY_FLAG_BROKEN_RESET; + return 0; +} + +int in112525_s03_startup(struct phy_device *phydev) +{ + int reg_value, i; + + phydev->link = 1; + +#ifdef CONFIG_IN112525_S03_10G + phydev->speed = SPEED_10000; +#else + phydev->speed = SPEED_25000; +#endif + phydev->duplex = DUPLEX_FULL; + + for (i = 0; i < ALL_LANES; i++) { + reg_value = mdio_rd(PHYSTAT_REG3 + i * 0x100); + if (!bit_test(reg_value, 15)) { + debug("starting recovery for lane %d\n", i); + in112525_s03_lane_recovery(i); + } + } + + return 0; +} + +int in112525_s05_startup(struct phy_device *phydev) +{ + phydev->link = 1; + +#if defined(CONFIG_IN112525_S05_10G) + phydev->speed = SPEED_10000; +#elif defined(CONFIG_IN112525_S05_25G) + phydev->speed = SPEED_25000; +#elif defined(CONFIG_IN112525_S05_40G) + phydev->speed = SPEED_40000; +#elif defined(CONFIG_IN112525_S05_50G) + phydev->speed = SPEED_50000; +#elif defined(CONFIG_IN112525_S05_100G) + phydev->speed = SPEED_100000; +#endif + phydev->duplex = DUPLEX_FULL; + return 0; +} + +struct phy_driver in112525_s05_driver = { + .name = "Inphi in112525_S05P", + .uid = PHY_UID_IN112525_S05, + .mask = 0x0ff0ffff, + .features = PHY_10G_FEATURES, + .mmds = MDIO_DEVS_VEND1, + .config = &in112525_s05_config, + .probe = &in112525_probe, + .startup = &in112525_s05_startup, + .shutdown = &gen10g_shutdown, +}; + +struct phy_driver in112525_s03_driver = { + .name = "Inphi in112525_S03P", + .uid = PHY_UID_IN112525_S03, + .mask = 0x0ff0fff0, + .features = PHY_10G_FEATURES, + .mmds = MDIO_DEVS_VEND1, + .config = &in112525_s03_config, + .probe = &in112525_probe, + .startup = &in112525_s03_startup, + .shutdown = &gen10g_shutdown, +}; + +int phy_in112525_init(void) +{ + phy_register(&in112525_s05_driver); + phy_register(&in112525_s03_driver); + return 0; +} diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 89e3076bfd2..57b5c4b8524 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -510,6 +511,9 @@ int phy_init(void) #ifdef CONFIG_PHY_ET1011C phy_et1011c_init(); #endif +#ifdef CONFIG_PHY_INPHI + phy_in112525_init(); +#endif #ifdef CONFIG_PHY_LXT phy_lxt_init(); #endif @@ -942,34 +946,25 @@ void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev) } #ifdef CONFIG_PHY_XILINX_GMII2RGMII -#ifdef CONFIG_DM_ETH static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, struct udevice *dev, phy_interface_t interface) -#else -static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, - struct eth_device *dev, - phy_interface_t interface) -#endif { struct phy_device *phydev = NULL; - int sn = dev_of_offset(dev); - int off; - - while (sn > 0) { - off = fdt_node_offset_by_compatible(gd->fdt_blob, sn, - "xlnx,gmii-to-rgmii-1.0"); - if (off > 0) { - phydev = phy_device_create(bus, off, + ofnode node = dev_ofnode(dev); + + while (ofnode_valid(node)) { + node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0"); + if (ofnode_valid(node)) { + phydev = phy_device_create(bus, 0, PHY_GMII2RGMII_ID, false, interface); + if (phydev) + phydev->node = node; break; } - if (off == -FDT_ERR_NOTFOUND) - sn = fdt_first_subnode(gd->fdt_blob, sn); - else - printf("%s: Error finding compat string:%d\n", - __func__, off); + + node = ofnode_first_subnode(node); } return phydev; @@ -988,6 +983,7 @@ static struct phy_device *phy_connect_gmii2rgmii(struct mii_dev *bus, struct phy_device *fixed_phy_create(ofnode node) { phy_interface_t interface = PHY_INTERFACE_MODE_NONE; + struct phy_device *phydev; const char *if_str; ofnode subnode; @@ -1004,33 +1000,25 @@ struct phy_device *fixed_phy_create(ofnode node) return NULL; } - return phy_device_create(NULL, ofnode_to_offset(subnode), PHY_FIXED_ID, - false, interface); + phydev = phy_device_create(NULL, 0, PHY_FIXED_ID, false, interface); + if (phydev) + phydev->node = subnode; + + return phydev; } -#ifdef CONFIG_DM_ETH static struct phy_device *phy_connect_fixed(struct mii_dev *bus, struct udevice *dev, phy_interface_t interface) -#else -static struct phy_device *phy_connect_fixed(struct mii_dev *bus, - struct eth_device *dev, - phy_interface_t interface) -#endif { + ofnode node = dev_ofnode(dev), subnode; struct phy_device *phydev = NULL; - int sn; - const char *name; - - sn = fdt_first_subnode(gd->fdt_blob, dev_of_offset(dev)); - while (sn > 0) { - name = fdt_get_name(gd->fdt_blob, sn, NULL); - if (name && strcmp(name, "fixed-link") == 0) { - phydev = phy_device_create(bus, sn, PHY_FIXED_ID, false, - interface); - break; - } - sn = fdt_next_subnode(gd->fdt_blob, sn); + + if (ofnode_phy_is_fixed_link(node, &subnode)) { + phydev = phy_device_create(bus, 0, PHY_FIXED_ID, + false, interface); + if (phydev) + phydev->node = subnode; } return phydev; diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index 74105c0b7d6..635c0570efe 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -18,9 +18,38 @@ DECLARE_GLOBAL_DATA_PTR; static int xilinxgmiitorgmii_config(struct phy_device *phydev) { - struct phy_device *ext_phydev = phydev->priv; + ofnode node = phy_get_ofnode(phydev); + struct phy_device *ext_phydev; + struct ofnode_phandle_args phandle; + int ext_phyaddr = -1; + int ret; debug("%s\n", __func__); + + if (!ofnode_valid(node)) + return -EINVAL; + + phydev->addr = ofnode_read_u32_default(node, "reg", -1); + ret = ofnode_parse_phandle_with_args(node, "phy-handle", + NULL, 0, 0, &phandle); + if (ret) + return ret; + + ext_phyaddr = ofnode_read_u32_default(phandle.node, "reg", -1); + ext_phydev = phy_find_by_mask(phydev->bus, + 1 << ext_phyaddr, + PHY_INTERFACE_MODE_RGMII); + if (!ext_phydev) { + printf("%s, No external phy device found\n", __func__); + return -EINVAL; + } + + ext_phydev->node = phandle.node; + phydev->priv = ext_phydev; + + debug("%s, gmii2rgmmi:0x%x, extphy:0x%x\n", __func__, phydev->addr, + ext_phyaddr); + if (ext_phydev->drv->config) ext_phydev->drv->config(ext_phydev); @@ -83,11 +112,6 @@ static int xilinxgmiitorgmii_startup(struct phy_device *phydev) static int xilinxgmiitorgmii_probe(struct phy_device *phydev) { - int ofnode = phydev->addr; - u32 phy_of_handle; - int ext_phyaddr = -1; - struct phy_device *ext_phydev; - debug("%s\n", __func__); if (phydev->interface != PHY_INTERFACE_MODE_GMII) { @@ -95,31 +119,6 @@ static int xilinxgmiitorgmii_probe(struct phy_device *phydev) return -EINVAL; } - /* - * Read the phy address again as the one we read in ethernet driver - * was overwritten for the purpose of storing the ofnode - */ - phydev->addr = fdtdec_get_int(gd->fdt_blob, ofnode, "reg", -1); - phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, ofnode, - "phy-handle"); - if (phy_of_handle > 0) - ext_phyaddr = fdtdec_get_int(gd->fdt_blob, - phy_of_handle, - "reg", -1); - ext_phydev = phy_find_by_mask(phydev->bus, - 1 << ext_phyaddr, - PHY_INTERFACE_MODE_RGMII); - if (!ext_phydev) { - printf("%s, No external phy device found\n", __func__); - return -EINVAL; - } - - ext_phydev->node = offset_to_ofnode(phy_of_handle); - phydev->priv = ext_phydev; - - debug("%s, gmii2rgmmi:0x%x, extphy:0x%x\n", __func__, phydev->addr, - ext_phyaddr); - phydev->flags |= PHY_FLAG_BROKEN_RESET; return 0; diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index ec486893725..c68e4b7fb5e 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -707,11 +707,7 @@ static int init_phy(struct tsec_private *priv) tsec_configure_serdes(priv); #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO) - if (ofnode_valid(ofnode_find_subnode(dev_ofnode(priv->dev), - "fixed-link"))) - phydev = phy_connect(NULL, 0, priv->dev, priv->interface); - else - phydev = dm_eth_phy_connect(priv->dev); + phydev = dm_eth_phy_connect(priv->dev); #else phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev, priv->interface); @@ -830,14 +826,40 @@ int tsec_probe(struct udevice *dev) u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; struct tsec_data *data; const char *phy_mode; + ofnode parent, child; fdt_addr_t reg; - ofnode parent; int ret; data = (struct tsec_data *)dev_get_driver_data(dev); pdata->iobase = (phys_addr_t)dev_read_addr(dev); - priv->regs = dev_remap_addr(dev); + if (pdata->iobase == FDT_ADDR_T_NONE) { + ofnode_for_each_subnode(child, dev_ofnode(dev)) { + if (strncmp(ofnode_get_name(child), "queue-group", + strlen("queue-group"))) + continue; + + reg = ofnode_get_addr(child); + if (reg == FDT_ADDR_T_NONE) { + printf("No 'reg' property of \n"); + return -ENOENT; + } + pdata->iobase = reg; + + /* + * if there are multiple queue groups, + * only the first one is used. + */ + break; + } + + if (!ofnode_valid(child)) { + printf("No child node for ?\n"); + return -ENOENT; + } + } + + priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE); ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0, &phandle_args); diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index d9c2325a221..ccb4d5809b5 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -4,6 +4,9 @@ * * Copyright (C) 2013 Marek Vasut * + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * Copyright 2019 NXP + * * Based on upstream Linux kernel driver: * pci-imx6.c: Sean Cross * pcie-designware.c: Jingoo Han @@ -14,35 +17,56 @@ #include #include #include +#if CONFIG_IS_ENABLED(CLK) +#include +#else #include +#endif #include +#ifdef CONFIG_MX6 #include +#endif #include #include #include #include #include +#include #include #include +#include +#include +#include +#include +#include +#include + +enum imx_pcie_variants { + IMX6Q, + IMX6SX, + IMX6QP, + IMX8QM, + IMX8QXP, +}; #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 #ifdef CONFIG_MX6SX #define MX6_DBI_ADDR 0x08ffc000 -#define MX6_IO_ADDR 0x08000000 -#define MX6_MEM_ADDR 0x08100000 +#define MX6_IO_ADDR 0x08f80000 +#define MX6_MEM_ADDR 0x08000000 #define MX6_ROOT_ADDR 0x08f00000 #else #define MX6_DBI_ADDR 0x01ffc000 -#define MX6_IO_ADDR 0x01000000 -#define MX6_MEM_ADDR 0x01100000 +#define MX6_IO_ADDR 0x01f80000 +#define MX6_MEM_ADDR 0x01000000 #define MX6_ROOT_ADDR 0x01f00000 #endif #define MX6_DBI_SIZE 0x4000 -#define MX6_IO_SIZE 0x100000 -#define MX6_MEM_SIZE 0xe00000 -#define MX6_ROOT_SIZE 0xfc000 +#define MX6_IO_SIZE 0x10000 +#define MX6_MEM_SIZE 0xf00000 +#define MX6_ROOT_SIZE 0x80000 /* PCIe Port Logic registers (memory-mapped) */ #define PL_OFFSET 0x700 @@ -54,6 +78,22 @@ #define PCIE_PHY_DEBUG_R1_LINK_UP (1 << 4) #define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (1 << 29) +#define PCIE_PORT_LINK_CONTROL 0x710 +#define PORT_LINK_MODE_MASK (0x3f << 16) +#define PORT_LINK_MODE_1_LANES (0x1 << 16) +#define PORT_LINK_MODE_2_LANES (0x3 << 16) +#define PORT_LINK_MODE_4_LANES (0x7 << 16) +#define PORT_LINK_MODE_8_LANES (0xf << 16) + + +#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C +#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17) +#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8) +#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8) +#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8) +#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8) +#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8) + #define PCIE_PHY_CTRL (PL_OFFSET + 0x114) #define PCIE_PHY_CTRL_DATA_LOC 0 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16 @@ -78,6 +118,7 @@ #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +#define PCIE_ATU_REGION_INDEX2 (0x2 << 0) #define PCIE_ATU_REGION_INDEX1 (0x1 << 0) #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) #define PCIE_ATU_CR1 0x904 @@ -97,9 +138,137 @@ #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16) #define PCIE_ATU_UPPER_TARGET 0x91C +#define PCIE_MISC_CTRL (PL_OFFSET + 0x1BC) +#define PCIE_MISC_DBI_RO_WR_EN BIT(0) + +/* iMX8 HSIO registers */ +#define IMX8QM_LPCG_PHYX2_OFFSET 0x00000 +#define IMX8QM_CSR_PHYX2_OFFSET 0x90000 +#define IMX8QM_CSR_PHYX1_OFFSET 0xA0000 +#define IMX8QM_CSR_PHYX_STTS0_OFFSET 0x4 +#define IMX8QM_CSR_PCIEA_OFFSET 0xB0000 +#define IMX8QM_CSR_PCIEB_OFFSET 0xC0000 +#define IMX8QM_CSR_PCIE_CTRL1_OFFSET 0x4 +#define IMX8QM_CSR_PCIE_CTRL2_OFFSET 0x8 +#define IMX8QM_CSR_PCIE_STTS0_OFFSET 0xC +#define IMX8QM_CSR_MISC_OFFSET 0xE0000 + +#define IMX8QM_LPCG_PHY_PCG0 BIT(1) +#define IMX8QM_LPCG_PHY_PCG1 BIT(5) + +#define IMX8QM_CTRL_LTSSM_ENABLE BIT(4) +#define IMX8QM_CTRL_READY_ENTR_L23 BIT(5) +#define IMX8QM_CTRL_PM_XMT_TURNOFF BIT(9) +#define IMX8QM_CTRL_BUTTON_RST_N BIT(21) +#define IMX8QM_CTRL_PERST_N BIT(22) +#define IMX8QM_CTRL_POWER_UP_RST_N BIT(23) + +#define IMX8QM_CTRL_STTS0_PM_LINKST_IN_L2 BIT(13) +#define IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST BIT(19) +#define IMX8QM_STTS0_LANE0_TX_PLL_LOCK BIT(4) +#define IMX8QM_STTS0_LANE1_TX_PLL_LOCK BIT(12) + +#define IMX8QM_PCIE_TYPE_MASK (0xF << 24) + +#define IMX8QM_PHYX2_CTRL0_APB_MASK 0x3 +#define IMX8QM_PHY_APB_RSTN_0 BIT(0) +#define IMX8QM_PHY_APB_RSTN_1 BIT(1) + +#define IMX8QM_MISC_IOB_RXENA BIT(0) +#define IMX8QM_MISC_IOB_TXENA BIT(1) +#define IMX8QM_CSR_MISC_IOB_A_0_TXOE BIT(2) +#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK (0x3 << 3) +#define IMX8QM_CSR_MISC_IOB_A_0_M1M0_2 BIT(4) +#define IMX8QM_MISC_PHYX1_EPCS_SEL BIT(12) +#define IMX8QM_MISC_PCIE_AB_SELECT BIT(13) + +#define HW_PHYX2_CTRL0_PIPE_LN2LK_MASK (0xF << 13) +#define HW_PHYX2_CTRL0_PIPE_LN2LK_0 BIT(13) +#define HW_PHYX2_CTRL0_PIPE_LN2LK_1 BIT(14) +#define HW_PHYX2_CTRL0_PIPE_LN2LK_2 BIT(15) +#define HW_PHYX2_CTRL0_PIPE_LN2LK_3 BIT(16) + +#define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000 + +#ifdef DEBUG + +#ifdef DEBUG_STRESS_WR /* warm-reset stress tests */ +#define SNVS_LPGRP 0x020cc068 +#endif + +#define DBGF(x...) printf(x) + +static void print_regs(int contain_pcie_reg) +{ +#ifdef CONFIG_MX6 + u32 val; + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + val = readl(&iomuxc_regs->gpr[1]); + DBGF("GPR01 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[1], val); + val = readl(&iomuxc_regs->gpr[5]); + DBGF("GPR05 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[5], val); + val = readl(&iomuxc_regs->gpr[8]); + DBGF("GPR08 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[8], val); + val = readl(&iomuxc_regs->gpr[12]); + DBGF("GPR12 a:0x%08x v:0x%08x\n", (u32)&iomuxc_regs->gpr[12], val); + val = readl(&ccm_regs->analog_pll_enet); + DBGF("PLL06 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->analog_pll_enet, val); + val = readl(&ccm_regs->ana_misc1); + DBGF("MISC1 a:0x%08x v:0x%08x\n", (u32)&ccm_regs->ana_misc1, val); + if (contain_pcie_reg) { + val = readl(MX6_DBI_ADDR + 0x728); + DBGF("dbr0 offset 0x728 %08x\n", val); + val = readl(MX6_DBI_ADDR + 0x72c); + DBGF("dbr1 offset 0x72c %08x\n", val); + } +#endif +} +#else +#define DBGF(x...) +static void print_regs(int contain_pcie_reg) {} +#endif + struct imx_pcie_priv { void __iomem *dbi_base; void __iomem *cfg_base; + void __iomem *cfg1_base; + enum imx_pcie_variants variant; + struct regmap *iomuxc_gpr; + u32 hsio_cfg; + u32 ctrl_id; + u32 ext_osc; + u32 cpu_base; + u32 lanes; + u32 cfg_size; + int cpu_addr_offset; + struct gpio_desc clkreq_gpio; + struct gpio_desc dis_gpio; + struct gpio_desc reset_gpio; + struct gpio_desc power_on_gpio; + + struct pci_region *io; + struct pci_region *mem; + struct pci_region *pref; + +#if CONFIG_IS_ENABLED(CLK) + struct clk pcie_bus; + struct clk pcie_phy; + struct clk pcie_phy_pclk; + struct clk pcie_inbound_axi; + struct clk pcie_per; + struct clk pciex2_per; + struct clk phy_per; + struct clk misc_per; + struct clk pcie; + struct clk pcie_ext_src; +#endif + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + struct udevice *epdev_on; + struct udevice *pcie_bus_regulator; + struct udevice *pcie_phy_regulator; +#endif }; /* @@ -235,6 +404,32 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) return 0; } +#if !CONFIG_IS_ENABLED(DM_PCI) +void imx_pcie_gpr_read(struct imx_pcie_priv *priv, uint offset, uint *valp) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + *valp = readl(&iomuxc_regs->gpr[offset >> 2]); +} + +void imx_pcie_gpr_update_bits(struct imx_pcie_priv *priv, uint offset, uint mask, uint val) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + clrsetbits_32(&iomuxc_regs->gpr[offset >> 2], mask, val); +} + +#else +void imx_pcie_gpr_read(struct imx_pcie_priv *priv, uint offset, uint *valp) +{ + regmap_read(priv->iomuxc_gpr, offset, valp); +} + +void imx_pcie_gpr_update_bits(struct imx_pcie_priv *priv, uint offset, uint mask, uint val) +{ + regmap_update_bits(priv->iomuxc_gpr, offset, mask, val); +} + +#endif + static int imx6_pcie_link_up(struct imx_pcie_priv *priv) { u32 rc, ltssm; @@ -277,45 +472,122 @@ static int imx6_pcie_link_up(struct imx_pcie_priv *priv) return 0; } -/* - * iATU region setup - */ -static int imx_pcie_regions_setup(struct imx_pcie_priv *priv) +/* Fix class value */ +static void imx_pcie_fix_class(struct imx_pcie_priv *priv) { - /* - * i.MX6 defines 16MB in the AXI address map for PCIe. - * - * That address space excepted the pcie registers is - * split and defined into different regions by iATU, - * with sizes and offsets as follows: - * - * 0x0100_0000 --- 0x010F_FFFF 1MB IORESOURCE_IO - * 0x0110_0000 --- 0x01EF_FFFF 14MB IORESOURCE_MEM - * 0x01F0_0000 --- 0x01FF_FFFF 1MB Cfg + Registers - */ + writew(PCI_CLASS_BRIDGE_PCI, priv->dbi_base + PCI_CLASS_DEVICE); +} + +/* Clear multi-function bit */ +static void imx_pcie_clear_multifunction(struct imx_pcie_priv *priv) +{ + writeb(PCI_HEADER_TYPE_BRIDGE, priv->dbi_base + PCI_HEADER_TYPE); +} + +static void imx_pcie_setup_ctrl(struct imx_pcie_priv *priv) +{ + u32 val; - /* CMD reg:I/O space, MEM space, and Bus Master Enable */ - setbits_le32(priv->dbi_base + PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + writel(PCIE_MISC_DBI_RO_WR_EN, priv->dbi_base + PCIE_MISC_CTRL); + + /* Set the number of lanes */ + val = readl(priv->dbi_base + PCIE_PORT_LINK_CONTROL); + val &= ~PORT_LINK_MODE_MASK; + switch (priv->lanes) { + case 1: + val |= PORT_LINK_MODE_1_LANES; + break; + case 2: + val |= PORT_LINK_MODE_2_LANES; + break; + case 4: + val |= PORT_LINK_MODE_4_LANES; + break; + case 8: + val |= PORT_LINK_MODE_8_LANES; + break; + default: + printf("num-lanes %u: invalid value\n", priv->lanes); + return; + } + writel(val, priv->dbi_base + PCIE_PORT_LINK_CONTROL); + + /* Set link width speed control register */ + val = readl(priv->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); + val &= ~PORT_LOGIC_LINK_WIDTH_MASK; + switch (priv->lanes) { + case 1: + val |= PORT_LOGIC_LINK_WIDTH_1_LANES; + break; + case 2: + val |= PORT_LOGIC_LINK_WIDTH_2_LANES; + break; + case 4: + val |= PORT_LOGIC_LINK_WIDTH_4_LANES; + break; + case 8: + val |= PORT_LOGIC_LINK_WIDTH_8_LANES; + break; + } + writel(val, priv->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL); - /* Set the CLASS_REV of RC CFG header to PCI_CLASS_BRIDGE_PCI */ - setbits_le32(priv->dbi_base + PCI_CLASS_REVISION, - PCI_CLASS_BRIDGE_PCI << 16); + /* setup RC BARs */ + writel(0, priv->dbi_base + PCI_BASE_ADDRESS_0); + writel(0, priv->dbi_base + PCI_BASE_ADDRESS_1); - /* Region #0 is used for Outbound CFG space access. */ - writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT); + /* setup bus numbers */ + val = readl(priv->dbi_base + PCI_PRIMARY_BUS); + val &= 0xff000000; + val |= 0x00ff0100; + writel(val, priv->dbi_base + PCI_PRIMARY_BUS); - writel(lower_32_bits((uintptr_t)priv->cfg_base), - priv->dbi_base + PCIE_ATU_LOWER_BASE); - writel(upper_32_bits((uintptr_t)priv->cfg_base), - priv->dbi_base + PCIE_ATU_UPPER_BASE); - writel(lower_32_bits((uintptr_t)priv->cfg_base + MX6_ROOT_SIZE), - priv->dbi_base + PCIE_ATU_LIMIT); + /* setup command register */ + val = readl(priv->dbi_base + PCI_COMMAND); + val &= 0xffff0000; + val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER; + writel(val, priv->dbi_base + PCI_COMMAND); - writel(0, priv->dbi_base + PCIE_ATU_LOWER_TARGET); - writel(0, priv->dbi_base + PCIE_ATU_UPPER_TARGET); - writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1); + imx_pcie_fix_class(priv); + imx_pcie_clear_multifunction(priv); + + writel(0, priv->dbi_base + PCIE_MISC_CTRL); +} + +static void imx_pcie_atu_outbound_set(struct imx_pcie_priv *priv, int idx, int type, + u64 phys, u64 bus_addr, u32 size) +{ + writel(PCIE_ATU_REGION_OUTBOUND | idx, priv->dbi_base + PCIE_ATU_VIEWPORT); + writel((u32)(phys + priv->cpu_addr_offset), priv->dbi_base + PCIE_ATU_LOWER_BASE); + writel((phys + priv->cpu_addr_offset) >> 32, priv->dbi_base + PCIE_ATU_UPPER_BASE); + writel((u32)(phys + priv->cpu_addr_offset) + size - 1, priv->dbi_base + PCIE_ATU_LIMIT); + writel((u32)bus_addr, priv->dbi_base + PCIE_ATU_LOWER_TARGET); + writel(bus_addr >> 32, priv->dbi_base + PCIE_ATU_UPPER_TARGET); + writel(type, priv->dbi_base + PCIE_ATU_CR1); writel(PCIE_ATU_ENABLE, priv->dbi_base + PCIE_ATU_CR2); +} + +/* + * iATU region setup + */ +static int imx_pcie_regions_setup(struct imx_pcie_priv *priv) +{ + if (priv->io) + /* ATU : OUTBOUND : IO */ + imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX2, + PCIE_ATU_TYPE_IO, + priv->io->phys_start, + priv->io->bus_start, + priv->io->size); + + if (priv->mem) + /* ATU : OUTBOUND : MEM */ + imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX0, + PCIE_ATU_TYPE_MEM, + priv->mem->phys_start, + priv->mem->bus_start, + priv->mem->size); + return 0; } @@ -328,30 +600,40 @@ static void __iomem *get_bus_address(struct imx_pcie_priv *priv, { void __iomem *va_address; - /* Reconfigure Region #0 */ - writel(0, priv->dbi_base + PCIE_ATU_VIEWPORT); - - if (PCI_BUS(d) < 2) - writel(PCIE_ATU_TYPE_CFG0, priv->dbi_base + PCIE_ATU_CR1); - else - writel(PCIE_ATU_TYPE_CFG1, priv->dbi_base + PCIE_ATU_CR1); - if (PCI_BUS(d) == 0) { + /* Outbound TLP matched primary interface of the bridge */ va_address = priv->dbi_base; } else { - writel(d << 8, priv->dbi_base + PCIE_ATU_LOWER_TARGET); - va_address = priv->cfg_base; + if (PCI_BUS(d) < 2) { + /* Outbound TLP matched secondary interface of the bridge changes to CFG0 */ + imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_CFG0, + (ulong)priv->cfg_base, + (u64)d << 8, + priv->cfg_size >> 1); + va_address = priv->cfg_base; + } else { + /* Outbound TLP matched the bus behind the bridge uses type CFG1 */ + imx_pcie_atu_outbound_set(priv, PCIE_ATU_REGION_INDEX1, + PCIE_ATU_TYPE_CFG1, + (ulong)priv->cfg1_base, + (u64)d << 8, + priv->cfg_size >> 1); + va_address = priv->cfg1_base; + } } va_address += (where & ~0x3); return va_address; + } static int imx_pcie_addr_valid(pci_dev_t d) { - if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 1)) + if ((PCI_BUS(d) == 0) && (PCI_DEV(d) > 0)) return -EINVAL; + /* ARI forward is not enabled, so non-zero device at downstream must be blocked */ if ((PCI_BUS(d) == 1) && (PCI_DEV(d) > 0)) return -EINVAL; return 0; @@ -372,6 +654,7 @@ static int imx_pcie_addr_valid(pci_dev_t d) */ static void imx_pcie_fix_dabt_handler(bool set) { +#ifdef CONFIG_MX6 extern uint32_t *_data_abort; uint32_t *data_abort_addr = (uint32_t *)&_data_abort; @@ -386,6 +669,7 @@ static void imx_pcie_fix_dabt_handler(bool set) } else { *data_abort_addr = data_abort_backup; } +#endif } static int imx_pcie_read_cfg(struct imx_pcie_priv *priv, pci_dev_t d, @@ -441,27 +725,375 @@ static int imx_pcie_write_cfg(struct imx_pcie_priv *priv, pci_dev_t d, return 0; } +static int imx8_pcie_assert_core_reset(struct imx_pcie_priv *priv, + bool prepare_for_boot) +{ + u32 val; + + switch (priv->variant) { + case IMX8QXP: + val = IMX8QM_CSR_PCIEB_OFFSET; + imx_pcie_gpr_update_bits(priv, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_BUTTON_RST_N, + IMX8QM_CTRL_BUTTON_RST_N); + imx_pcie_gpr_update_bits(priv, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_PERST_N, + IMX8QM_CTRL_PERST_N); + imx_pcie_gpr_update_bits(priv, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_POWER_UP_RST_N, + IMX8QM_CTRL_POWER_UP_RST_N); + break; + case IMX8QM: + val = IMX8QM_CSR_PCIEA_OFFSET + priv->ctrl_id * SZ_64K; + imx_pcie_gpr_update_bits(priv, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_BUTTON_RST_N, + IMX8QM_CTRL_BUTTON_RST_N); + imx_pcie_gpr_update_bits(priv, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_PERST_N, + IMX8QM_CTRL_PERST_N); + imx_pcie_gpr_update_bits(priv, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_POWER_UP_RST_N, + IMX8QM_CTRL_POWER_UP_RST_N); + break; + default: + break; + } + + return 0; +} + +static int imx8_pcie_init_phy(struct imx_pcie_priv *priv) +{ + u32 tmp, val; + + if (priv->variant == IMX8QM + || priv->variant == IMX8QXP) { + switch (priv->hsio_cfg) { + case PCIEAX2SATA: + /* + * bit 0 rx ena 1. + * bit12 PHY_X1_EPCS_SEL 1. + * bit13 phy_ab_select 0. + */ + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_PHYX2_OFFSET, + IMX8QM_PHYX2_CTRL0_APB_MASK, + IMX8QM_PHY_APB_RSTN_0 + | IMX8QM_PHY_APB_RSTN_1); + + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PHYX1_EPCS_SEL, + IMX8QM_MISC_PHYX1_EPCS_SEL); + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PCIE_AB_SELECT, + 0); + break; + + case PCIEAX1PCIEBX1SATA: + tmp = IMX8QM_PHY_APB_RSTN_1; + tmp |= IMX8QM_PHY_APB_RSTN_0; + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_PHYX2_OFFSET, + IMX8QM_PHYX2_CTRL0_APB_MASK, tmp); + + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PHYX1_EPCS_SEL, + IMX8QM_MISC_PHYX1_EPCS_SEL); + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PCIE_AB_SELECT, + IMX8QM_MISC_PCIE_AB_SELECT); + + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_PHYX2_OFFSET, + HW_PHYX2_CTRL0_PIPE_LN2LK_MASK, + HW_PHYX2_CTRL0_PIPE_LN2LK_3 | HW_PHYX2_CTRL0_PIPE_LN2LK_0); + + break; + + case PCIEAX2PCIEBX1: + /* + * bit 0 rx ena 1. + * bit12 PHY_X1_EPCS_SEL 0. + * bit13 phy_ab_select 1. + */ + if (priv->ctrl_id) + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_PHYX1_OFFSET, + IMX8QM_PHY_APB_RSTN_0, + IMX8QM_PHY_APB_RSTN_0); + else + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_PHYX2_OFFSET, + IMX8QM_PHYX2_CTRL0_APB_MASK, + IMX8QM_PHY_APB_RSTN_0 + | IMX8QM_PHY_APB_RSTN_1); + + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PHYX1_EPCS_SEL, + 0); + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_PCIE_AB_SELECT, + IMX8QM_MISC_PCIE_AB_SELECT); + break; + } + + if (priv->ext_osc) { + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + IMX8QM_MISC_IOB_RXENA); + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + 0); + } else { + /* Try to used the internal pll as ref clk */ + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_RXENA, + 0); + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_MISC_IOB_TXENA, + IMX8QM_MISC_IOB_TXENA); + imx_pcie_gpr_update_bits(priv, + IMX8QM_CSR_MISC_OFFSET, + IMX8QM_CSR_MISC_IOB_A_0_TXOE + | IMX8QM_CSR_MISC_IOB_A_0_M1M0_MASK, + IMX8QM_CSR_MISC_IOB_A_0_TXOE + | IMX8QM_CSR_MISC_IOB_A_0_M1M0_2); + } + + val = IMX8QM_CSR_PCIEA_OFFSET + + priv->ctrl_id * SZ_64K; + imx_pcie_gpr_update_bits(priv, + val, IMX8QM_PCIE_TYPE_MASK, + 0x4 << 24); + + mdelay(10); + } + + return 0; +} + +static int imx8_pcie_wait_for_phy_pll_lock(struct imx_pcie_priv *priv) +{ + u32 val, tmp, orig; + unsigned int retries = 0; + + if (priv->variant == IMX8QXP + || priv->variant == IMX8QM) { + for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; + retries++) { + if (priv->hsio_cfg == PCIEAX1PCIEBX1SATA) { + imx_pcie_gpr_read(priv, + IMX8QM_CSR_PHYX2_OFFSET + 0x4, + &tmp); + if (priv->ctrl_id == 0) /* pciea 1 lanes */ + orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK; + else /* pcieb 1 lanes */ + orig = IMX8QM_STTS0_LANE1_TX_PLL_LOCK; + tmp &= orig; + if (tmp == orig) { + imx_pcie_gpr_update_bits(priv, + IMX8QM_LPCG_PHYX2_OFFSET, + IMX8QM_LPCG_PHY_PCG0 + | IMX8QM_LPCG_PHY_PCG1, + IMX8QM_LPCG_PHY_PCG0 + | IMX8QM_LPCG_PHY_PCG1); + break; + } + } + + if (priv->hsio_cfg == PCIEAX2PCIEBX1) { + val = IMX8QM_CSR_PHYX2_OFFSET + + priv->ctrl_id * SZ_64K; + imx_pcie_gpr_read(priv, + val + IMX8QM_CSR_PHYX_STTS0_OFFSET, + &tmp); + orig = IMX8QM_STTS0_LANE0_TX_PLL_LOCK; + if (priv->ctrl_id == 0) /* pciea 2 lanes */ + orig |= IMX8QM_STTS0_LANE1_TX_PLL_LOCK; + tmp &= orig; + if (tmp == orig) { + val = IMX8QM_CSR_PHYX2_OFFSET + + priv->ctrl_id * SZ_64K; + imx_pcie_gpr_update_bits(priv, + val, IMX8QM_LPCG_PHY_PCG0, + IMX8QM_LPCG_PHY_PCG0); + break; + } + } + udelay(10); + } + } + + if (retries >= PHY_PLL_LOCK_WAIT_MAX_RETRIES) { + printf("pcie phy pll can't be locked.\n"); + return -ENODEV; + } else { + debug("pcie phy pll is locked.\n"); + return 0; + } +} + +static int imx8_pcie_deassert_core_reset(struct imx_pcie_priv *priv) +{ + int ret, i; + u32 val, tmp; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_enable(&priv->pcie); + if (ret) { + printf("unable to enable pcie clock\n"); + return ret; + } + + ret = clk_enable(&priv->pcie_phy); + if (ret) { + printf("unable to enable pcie_phy clock\n"); + goto err_pcie; + } + + ret = clk_enable(&priv->pcie_bus); + if (ret) { + printf("unable to enable pcie_bus clock\n"); + goto err_pcie_phy; + } + + ret = clk_enable(&priv->pcie_inbound_axi); + if (ret) { + printf("unable to enable pcie_axi clock\n"); + goto err_pcie_bus; + } + ret = clk_enable(&priv->pcie_per); + if (ret) { + printf("unable to enable pcie_per clock\n"); + goto err_pcie_inbound_axi; + } + + ret = clk_enable(&priv->phy_per); + if (ret) { + printf("unable to enable phy_per clock\n"); + goto err_pcie_per; + } + + ret = clk_enable(&priv->misc_per); + if (ret) { + printf("unable to enable misc_per clock\n"); + goto err_phy_per; + } + + if (priv->variant == IMX8QM && priv->ctrl_id == 1) { + ret = clk_enable(&priv->pcie_phy_pclk); + if (ret) { + printf("unable to enable pcie_phy_pclk clock\n"); + goto err_misc_per; + } + + ret = clk_enable(&priv->pciex2_per); + if (ret) { + printf("unable to enable pciex2_per clock\n"); + clk_disable(&priv->pcie_phy_pclk); + goto err_misc_per; + } + } +#endif + /* allow the clocks to stabilize */ + udelay(200); + + /* bit19 PM_REQ_CORE_RST of pciex#_stts0 should be cleared. */ + for (i = 0; i < 100; i++) { + val = IMX8QM_CSR_PCIEA_OFFSET + + priv->ctrl_id * SZ_64K; + imx_pcie_gpr_read(priv, + val + IMX8QM_CSR_PCIE_STTS0_OFFSET, + &tmp); + if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) == 0) + break; + udelay(10); + } + + if ((tmp & IMX8QM_CTRL_STTS0_PM_REQ_CORE_RST) != 0) + printf("ERROR PM_REQ_CORE_RST is still set.\n"); + + /* wait for phy pll lock firstly. */ + if (imx8_pcie_wait_for_phy_pll_lock(priv)) { + ret = -ENODEV; + goto err_ref_clk;; + } + + if (dm_gpio_is_valid(&priv->reset_gpio)) { + dm_gpio_set_value(&priv->reset_gpio, 1); + mdelay(20); + dm_gpio_set_value(&priv->reset_gpio, 0); + mdelay(20); + } + + return 0; + +err_ref_clk: +#if CONFIG_IS_ENABLED(CLK) + if (priv->variant == IMX8QM && priv->ctrl_id == 1) { + clk_disable(&priv->pciex2_per); + clk_disable(&priv->pcie_phy_pclk); + } +err_misc_per: + clk_disable(&priv->misc_per); +err_phy_per: + clk_disable(&priv->phy_per); +err_pcie_per: + clk_disable(&priv->pcie_per); +err_pcie_inbound_axi: + clk_disable(&priv->pcie_inbound_axi); +err_pcie_bus: + clk_disable(&priv->pcie_bus); +err_pcie_phy: + clk_disable(&priv->pcie_phy); +err_pcie: + clk_disable(&priv->pcie); +#endif + + return ret; +} + +#ifdef CONFIG_MX6 /* * Initial bus setup */ static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv, bool prepare_for_boot) { - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - if (is_mx6dqp()) - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); + if (priv->variant == IMX6QP) + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_PCIE_SW_RST, IOMUXC_GPR1_PCIE_SW_RST); #if defined(CONFIG_MX6SX) - struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; - - /* SSP_EN is not used on MX6SX anymore */ - setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); - /* Force PCIe PHY reset */ - setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); - /* Power up PCIe PHY */ - setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); -#else + if (priv->variant == IMX6SX) { + struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; + + /* SSP_EN is not used on MX6SX anymore */ + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_TEST_POWERDOWN, IOMUXC_GPR12_TEST_POWERDOWN); + /* Force PCIe PHY reset */ + imx_pcie_gpr_update_bits(priv, 20, IOMUXC_GPR5_PCIE_BTNRST, IOMUXC_GPR5_PCIE_BTNRST); + /* Power up PCIe PHY */ + setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); + pcie_power_up(); + + return 0; + } +#endif /* * If the bootloader already enabled the link we need some special * handling to get the core back into a state where it is safe to @@ -473,11 +1105,11 @@ static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv, * If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong * indication that the bootloader activated the link. */ - if (is_mx6dq() && prepare_for_boot) { + if (priv->variant == IMX6Q && prepare_for_boot) { u32 val, gpr1, gpr12; - gpr1 = readl(&iomuxc_regs->gpr[1]); - gpr12 = readl(&iomuxc_regs->gpr[12]); + imx_pcie_gpr_read(priv, 4, &gpr1); + imx_pcie_gpr_read(priv, 48, &gpr12); if ((gpr1 & IOMUXC_GPR1_PCIE_REF_CLK_EN) && (gpr12 & IOMUXC_GPR12_PCIE_CTL_2)) { val = readl(priv->dbi_base + PCIE_PL_PFLR); @@ -488,42 +1120,44 @@ static int imx6_pcie_assert_core_reset(struct imx_pcie_priv *priv, writel(val, priv->dbi_base + PCIE_PL_PFLR); imx_pcie_fix_dabt_handler(false); - gpr12 &= ~IOMUXC_GPR12_PCIE_CTL_2; - writel(val, &iomuxc_regs->gpr[12]); + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_PCIE_CTL_2, 0); } } - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); -#endif + + if (priv->variant == IMX6QP || priv->variant == IMX6Q) { + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_TEST_POWERDOWN, + IOMUXC_GPR1_TEST_POWERDOWN); + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_REF_SSP_EN, 0); + } return 0; } -static int imx6_pcie_init_phy(void) +static int imx6_pcie_init_phy(struct imx_pcie_priv *priv) { - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); +#ifndef DEBUG + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_APPS_LTSSM_ENABLE, 0); +#endif - clrsetbits_le32(&iomuxc_regs->gpr[12], + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_DEVICE_TYPE_MASK, IOMUXC_GPR12_DEVICE_TYPE_RC); - clrsetbits_le32(&iomuxc_regs->gpr[12], + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_LOS_LEVEL_MASK, IOMUXC_GPR12_LOS_LEVEL_9); -#ifdef CONFIG_MX6SX - clrsetbits_le32(&iomuxc_regs->gpr[12], - IOMUXC_GPR12_RX_EQ_MASK, - IOMUXC_GPR12_RX_EQ_2); -#endif + if (priv->variant == IMX6SX) { + imx_pcie_gpr_update_bits(priv, 48, + IOMUXC_GPR12_RX_EQ_MASK, + IOMUXC_GPR12_RX_EQ_2); + } - writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | + imx_pcie_gpr_update_bits(priv, 32, 0xffffffff, + (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) | (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) | (127 << IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET) | - (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET), - &iomuxc_regs->gpr[8]); + (127 << IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET)); return 0; } @@ -581,19 +1215,20 @@ __weak int imx6_pcie_toggle_reset(void) #else puts("WARNING: Make sure the PCIe #PERST line is connected!\n"); #endif + return 0; } -static int imx6_pcie_deassert_core_reset(void) +static int imx6_pcie_deassert_core_reset(struct imx_pcie_priv *priv) { - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - +#if !CONFIG_IS_ENABLED(DM_PCI) imx6_pcie_toggle_power(); +#endif enable_pcie_clock(); - if (is_mx6dqp()) - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_PCIE_SW_RST); + if (priv->variant == IMX6QP) + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_PCIE_SW_RST, 0); /* * Wait for the clock to settle a bit, when the clock are sourced @@ -601,32 +1236,135 @@ static int imx6_pcie_deassert_core_reset(void) */ mdelay(50); -#if defined(CONFIG_MX6SX) - /* SSP_EN is not used on MX6SX anymore */ - clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); - /* Clear PCIe PHY reset bit */ - clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); -#else - /* Enable PCIe */ - clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); - setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); -#endif + if (priv->variant == IMX6SX) { + /* SSP_EN is not used on MX6SX anymore */ + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_TEST_POWERDOWN, 0); + /* Clear PCIe PHY reset bit */ + imx_pcie_gpr_update_bits(priv, 20, IOMUXC_GPR5_PCIE_BTNRST, 0); + } else { + /* Enable PCIe */ + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_TEST_POWERDOWN, 0); + imx_pcie_gpr_update_bits(priv, 4, IOMUXC_GPR1_REF_SSP_EN, IOMUXC_GPR1_REF_SSP_EN); + } +#if !CONFIG_IS_ENABLED(DM_PCI) imx6_pcie_toggle_reset(); +#else + if (dm_gpio_is_valid(&priv->reset_gpio)) { + dm_gpio_set_value(&priv->reset_gpio, 1); + mdelay(20); + dm_gpio_set_value(&priv->reset_gpio, 0); + mdelay(20); + } +#endif return 0; } +#endif + +static int imx_pcie_assert_core_reset(struct imx_pcie_priv *priv, + bool prepare_for_boot) +{ + switch (priv->variant) { +#ifdef CONFIG_MX6 + case IMX6Q: + case IMX6QP: + case IMX6SX: + return imx6_pcie_assert_core_reset(priv, prepare_for_boot); +#endif + case IMX8QM: + case IMX8QXP: + return imx8_pcie_assert_core_reset(priv, prepare_for_boot); + default: + return -EPERM; + } +} + +static int imx_pcie_init_phy(struct imx_pcie_priv *priv) +{ + switch (priv->variant) { +#ifdef CONFIG_MX6 + case IMX6Q: + case IMX6QP: + case IMX6SX: + return imx6_pcie_init_phy(priv); +#endif + case IMX8QM: + case IMX8QXP: + return imx8_pcie_init_phy(priv); + default: + return -EPERM; + } +} + +static int imx_pcie_deassert_core_reset(struct imx_pcie_priv *priv) +{ + switch (priv->variant) { +#ifdef CONFIG_MX6 + case IMX6Q: + case IMX6QP: + case IMX6SX: + return imx6_pcie_deassert_core_reset(priv); +#endif + case IMX8QM: + case IMX8QXP: + return imx8_pcie_deassert_core_reset(priv); + default: + return -EPERM; + } +} + +static void imx_pcie_ltssm_enable(struct imx_pcie_priv *priv, bool enable) +{ + u32 val; + + switch (priv->variant) { +#ifdef CONFIG_MX6 + case IMX6Q: + case IMX6SX: + case IMX6QP: + if (enable) + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_APPS_LTSSM_ENABLE, + IOMUXC_GPR12_APPS_LTSSM_ENABLE); /* LTSSM enable, starting link. */ + else + imx_pcie_gpr_update_bits(priv, 48, IOMUXC_GPR12_APPS_LTSSM_ENABLE, 0); + + break; +#endif + case IMX8QXP: + case IMX8QM: + /* Bit4 of the CTRL2 */ + val = IMX8QM_CSR_PCIEA_OFFSET + + priv->ctrl_id * SZ_64K; + if (enable) { + imx_pcie_gpr_update_bits(priv, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_LTSSM_ENABLE, + IMX8QM_CTRL_LTSSM_ENABLE); + } else { + imx_pcie_gpr_update_bits(priv, + val + IMX8QM_CSR_PCIE_CTRL2_OFFSET, + IMX8QM_CTRL_LTSSM_ENABLE, + 0); + } + break; + default: + break; + } + +} + static int imx_pcie_link_up(struct imx_pcie_priv *priv) { - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; uint32_t tmp; int count = 0; - imx6_pcie_assert_core_reset(priv, false); - imx6_pcie_init_phy(); - imx6_pcie_deassert_core_reset(); + imx_pcie_assert_core_reset(priv, false); + imx_pcie_init_phy(priv); + imx_pcie_deassert_core_reset(priv); + imx_pcie_setup_ctrl(priv); imx_pcie_regions_setup(priv); /* @@ -652,11 +1390,38 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv) writel(tmp, priv->dbi_base + 0x7c); /* LTSSM enable, starting link. */ - setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_APPS_LTSSM_ENABLE); + imx_pcie_ltssm_enable(priv, true); while (!imx6_pcie_link_up(priv)) { udelay(10); count++; + if (count == 1000) { + print_regs(1); + /* link down, try reset ep, and re-try link here */ + DBGF("pcie link is down, reset ep, then retry!\n"); + +#if CONFIG_IS_ENABLED(DM_PCI) + if (dm_gpio_is_valid(&priv->reset_gpio)) { + dm_gpio_set_value(&priv->reset_gpio, 1); + mdelay(20); + dm_gpio_set_value(&priv->reset_gpio, 0); + mdelay(20); + } +#elif defined(CONFIG_MX6) + imx6_pcie_toggle_reset(); +#endif + continue; + } +#ifdef DEBUG + else if (count >= 2000) { + print_regs(1); + /* link is down, stop here */ + env_set("bootcmd", "sleep 2;"); + DBGF("pcie link is down, stop here!\n"); + imx_pcie_ltssm_enable(priv, false); + return -EINVAL; + } +#endif if (count >= 4000) { #ifdef CONFIG_PCI_SCAN_SHOW puts("PCI: pcie phy link never came up\n"); @@ -664,6 +1429,7 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv) debug("DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", readl(priv->dbi_base + PCIE_PHY_DEBUG_R0), readl(priv->dbi_base + PCIE_PHY_DEBUG_R1)); + imx_pcie_ltssm_enable(priv, false); return -EINVAL; } } @@ -675,10 +1441,14 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv) static struct imx_pcie_priv imx_pcie_priv = { .dbi_base = (void __iomem *)MX6_DBI_ADDR, .cfg_base = (void __iomem *)MX6_ROOT_ADDR, + .cfg1_base = (void __iomem *)(MX6_ROOT_ADDR + MX6_ROOT_SIZE / 2), + .cfg_size = MX6_ROOT_SIZE, + .lanes = 1, }; static struct imx_pcie_priv *priv = &imx_pcie_priv; + static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d, int where, u32 *val) { @@ -701,14 +1471,25 @@ void imx_pcie_init(void) static struct pci_controller pcc; struct pci_controller *hose = &pcc; int ret; +#ifdef DEBUG_STRESS_WR + u32 dbg_reg_addr = SNVS_LPGRP; + u32 dbg_reg = readl(dbg_reg_addr) + 1; +#endif memset(&pcc, 0, sizeof(pcc)); + if (is_mx6sx()) + priv->variant = IMX6SX; + else if (is_mx6dqp()) + priv->variant = IMX6QP; + else + priv->variant = IMX6Q; + hose->priv_data = priv; /* PCI I/O space */ pci_set_region(&hose->regions[0], - MX6_IO_ADDR, MX6_IO_ADDR, + 0, MX6_IO_ADDR, MX6_IO_SIZE, PCI_REGION_IO); /* PCI memory space */ @@ -721,6 +1502,9 @@ void imx_pcie_init(void) MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR, 0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); + priv->io = &hose->regions[0]; + priv->mem = &hose->regions[1]; + hose->region_count = 3; pci_set_ops(hose, @@ -737,7 +1521,15 @@ void imx_pcie_init(void) if (!ret) { pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); +#ifdef DEBUG_STRESS_WR + dbg_reg += 1<<16; +#endif } +#ifdef DEBUG_STRESS_WR + writel(dbg_reg, dbg_reg_addr); + DBGF("PCIe Successes/Attempts: %d/%d\n", + dbg_reg >> 16, dbg_reg & 0xffff); +#endif } void imx_pcie_remove(void) @@ -750,6 +1542,12 @@ void pci_init_board(void) { imx_pcie_init(); } + +int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev) +{ + return 0; +} + #else static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf, uint offset, ulong *value, @@ -785,8 +1583,152 @@ static int imx_pcie_dm_write_config(struct udevice *dev, pci_dev_t bdf, static int imx_pcie_dm_probe(struct udevice *dev) { + int ret = 0; struct imx_pcie_priv *priv = dev_get_priv(dev); +#if CONFIG_IS_ENABLED(DM_REGULATOR) + ret = device_get_supply_regulator(dev, "epdev_on", &priv->epdev_on); + if (ret) { + priv->epdev_on = NULL; + dev_dbg(dev, "no epdev_on\n"); + } else { + ret = regulator_set_enable(priv->epdev_on, true); + if (ret) { + dev_err(dev, "fail to enable epdev_on\n"); + return ret; + } + } + + mdelay(100); +#endif + + /* Enable the osc clk */ + ret = gpio_request_by_name(dev, "clkreq-gpio", 0, &priv->clkreq_gpio, + (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)); + if (ret) { + dev_info(dev, "%d unable to get clkreq.\n", ret); + } + + /* enable */ + ret = gpio_request_by_name(dev, "disable-gpio", 0, &priv->dis_gpio, + (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)); + if (ret) { + dev_info(dev, "%d unable to get disable-gpio.\n", ret); + } + + /* Set to power on */ + ret = gpio_request_by_name(dev, "power-on-gpio", 0, &priv->power_on_gpio, + (GPIOD_IS_OUT |GPIOD_IS_OUT_ACTIVE)); + if (ret) { + dev_info(dev, "%d unable to get power-on-gpio.\n", ret); + } + + /* Set to reset status */ + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset_gpio, + (GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE)); + if (ret) { + dev_info(dev, "%d unable to get power-on-gpio.\n", ret); + } + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_name(dev, "pcie_phy", &priv->pcie_phy); + if (ret) { + printf("Failed to get pcie_phy clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "pcie_bus", &priv->pcie_bus); + if (ret) { + printf("Failed to get pcie_bus clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "pcie", &priv->pcie); + if (ret) { + printf("Failed to get pcie clk\n"); + return ret; + } +#endif + + if (priv->variant == IMX8QM || priv->variant == IMX8QXP) { +#if CONFIG_IS_ENABLED(CLK) + ret = clk_get_by_name(dev, "pcie_per", &priv->pcie_per); + if (ret) { + printf("Failed to get pcie_per clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "pcie_inbound_axi", &priv->pcie_inbound_axi); + if (ret) { + printf("Failed to get pcie_inbound_axi clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "phy_per", &priv->phy_per); + if (ret) { + printf("Failed to get phy_per clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "misc_per", &priv->misc_per); + if (ret) { + printf("Failed to get misc_per clk\n"); + return ret; + } + + if (priv->variant == IMX8QM && priv->ctrl_id == 1) { + ret = clk_get_by_name(dev, "pcie_phy_pclk", &priv->pcie_phy_pclk); + if (ret) { + printf("Failed to get pcie_phy_pclk clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "pciex2_per", &priv->pciex2_per); + if (ret) { + printf("Failed to get pciex2_per clk\n"); + return ret; + } + } +#endif + priv->iomuxc_gpr = + syscon_regmap_lookup_by_phandle(dev, "hsio"); + if (IS_ERR(priv->iomuxc_gpr)) { + dev_err(dev, "unable to find gpr registers\n"); + return PTR_ERR(priv->iomuxc_gpr); + } + } else { +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (priv->variant == IMX6QP) { + ret = device_get_supply_regulator(dev, "pcie-bus", &priv->pcie_bus_regulator); + if (ret) { + dev_dbg(dev, "no pcie_bus_regulator\n"); + priv->pcie_bus_regulator = NULL; + } + } else if (priv->variant == IMX6SX) { + ret = device_get_supply_regulator(dev, "pcie-phy", &priv->pcie_phy_regulator); + if (ret) { + dev_dbg(dev, "no pcie_phy_regulator\n"); + priv->pcie_phy_regulator = NULL; + } + } +#endif + + priv->iomuxc_gpr = + syscon_regmap_lookup_by_phandle(dev, "gpr"); + if (IS_ERR(priv->iomuxc_gpr)) { + dev_err(dev, "unable to find gpr registers\n"); + return PTR_ERR(priv->iomuxc_gpr); + } + } + + pci_get_regions(dev, &priv->io, &priv->mem, &priv->pref); + + if (priv->cpu_base) + priv->cpu_addr_offset = priv->cpu_base + - priv->mem->phys_start; + else + priv->cpu_addr_offset = 0; + return imx_pcie_link_up(priv); } @@ -794,7 +1736,7 @@ static int imx_pcie_dm_remove(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); - imx6_pcie_assert_core_reset(priv, true); + imx_pcie_assert_core_reset(priv, true); return 0; } @@ -802,12 +1744,45 @@ static int imx_pcie_dm_remove(struct udevice *dev) static int imx_pcie_of_to_plat(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); + int ret; + struct resource cfg_res; priv->dbi_base = (void __iomem *)devfdt_get_addr_index(dev, 0); - priv->cfg_base = (void __iomem *)devfdt_get_addr_index(dev, 1); - if (!priv->dbi_base || !priv->cfg_base) + if (!priv->dbi_base) return -EINVAL; + ret = dev_read_resource_byname(dev, "config", &cfg_res); + if (ret) { + printf("can't get config resource(ret = %d)\n", ret); + return -ENOMEM; + } + + priv->cfg_base = map_physmem(cfg_res.start, + resource_size(&cfg_res), + MAP_NOCACHE); + priv->cfg1_base = priv->cfg_base + resource_size(&cfg_res) / 2; + priv->cfg_size = resource_size(&cfg_res); + + priv->variant = (enum imx_pcie_variants)dev_get_driver_data(dev); + + if (dev_read_u32u(dev, "hsio-cfg", &priv->hsio_cfg)) + priv->hsio_cfg = 0; + + if (dev_read_u32u(dev, "ctrl-id", &priv->ctrl_id)) + priv->ctrl_id = 0; + + if (dev_read_u32u(dev, "ext_osc", &priv->ext_osc)) + priv->ext_osc = 0; + + if (dev_read_u32u(dev, "cpu-base-addr", &priv->cpu_base)) + priv->cpu_base = 0; + + if (dev_read_u32u(dev, "num-lanes", &priv->lanes)) + priv->lanes = 1; + + debug("hsio-cfg %u, ctrl-id %u, ext_osc %u, cpu-base 0x%x\n", + priv->hsio_cfg, priv->ctrl_id, priv->ext_osc, priv->cpu_base); + return 0; } @@ -817,8 +1792,11 @@ static const struct dm_pci_ops imx_pcie_ops = { }; static const struct udevice_id imx_pcie_ids[] = { - { .compatible = "fsl,imx6q-pcie" }, - { .compatible = "fsl,imx6sx-pcie" }, + { .compatible = "fsl,imx6q-pcie", .data = (ulong)IMX6Q, }, + { .compatible = "fsl,imx6sx-pcie", .data = (ulong)IMX6SX, }, + { .compatible = "fsl,imx6qp-pcie", .data = (ulong)IMX6QP, }, + { .compatible = "fsl,imx8qm-pcie", .data = (ulong)IMX8QM, }, + { .compatible = "fsl,imx8qxp-pcie", .data = (ulong)IMX8QXP, }, { } }; diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index c7231635e41..cf77d9f2cd0 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * Layerscape PCIe EP driver */ @@ -269,6 +269,10 @@ static int ls_pcie_ep_probe(struct udevice *dev) pcie->idx = ((unsigned long)pcie->dbi - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE; + /* This controller is disabled by RCW */ + if (!is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx))) + return 0; + pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), "big-endian"); diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 008186a10d3..0e742682802 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -268,5 +268,13 @@ config PHY_MTK_TPHY multi-ports is first version, otherwise is second veriosn, so you can easily distinguish them by banks layout. +config CDNS3_USB_PHY + bool "Support CDNS3 USB PHY" + depends on PHY + help + Support for the USB PHY in CDNS3 IP. + + This PHY is found on CDNS3 IP devices supporting USB. + source "drivers/phy/rockchip/Kconfig" endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3c4a673a83b..f81adc36a3a 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -29,5 +29,6 @@ obj-$(CONFIG_OMAP_USB2_PHY) += omap-usb2-phy.o obj-$(CONFIG_KEYSTONE_USB_PHY) += keystone-usb-phy.o obj-$(CONFIG_MT7620_USB_PHY) += mt7620-usb-phy.o obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o +obj-$(CONFIG_CDNS3_USB_PHY) += cdns3-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o diff --git a/drivers/phy/cdns3-usb-phy.c b/drivers/phy/cdns3-usb-phy.c new file mode 100644 index 00000000000..1d397a3114d --- /dev/null +++ b/drivers/phy/cdns3-usb-phy.c @@ -0,0 +1,242 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * Cadence3 USB PHY driver + * + * Author: Sherry Sun + */ + +#include +#include +#include +#include +#include +#include + +/* PHY registers */ +#define PHY_PMA_CMN_CTRL1 (0xC800 * 4) +#define TB_ADDR_CMN_DIAG_HSCLK_SEL (0x01e0 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR (0x0084 * 4) +#define TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR (0x0085 * 4) +#define TB_ADDR_CMN_PLL0_INTDIV (0x0094 * 4) +#define TB_ADDR_CMN_PLL0_FRACDIV (0x0095 * 4) +#define TB_ADDR_CMN_PLL0_HIGH_THR (0x0096 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL1 (0x0098 * 4) +#define TB_ADDR_CMN_PLL0_SS_CTRL2 (0x0099 * 4) +#define TB_ADDR_CMN_PLL0_DSM_DIAG (0x0097 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_OVRD (0x01c2 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD (0x01c0 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD (0x01c1 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE (0x01C5 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_CP_TUNE (0x01C6 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_LF_PROG (0x01C7 * 4) +#define TB_ADDR_CMN_DIAG_PLL0_TEST_MODE (0x01c4 * 4) +#define TB_ADDR_CMN_PSM_CLK_CTRL (0x0061 * 4) +#define TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR (0x40ea * 4) +#define TB_ADDR_XCVR_PSM_RCTRL (0x4001 * 4) +#define TB_ADDR_TX_PSC_A0 (0x4100 * 4) +#define TB_ADDR_TX_PSC_A1 (0x4101 * 4) +#define TB_ADDR_TX_PSC_A2 (0x4102 * 4) +#define TB_ADDR_TX_PSC_A3 (0x4103 * 4) +#define TB_ADDR_TX_DIAG_ECTRL_OVRD (0x41f5 * 4) +#define TB_ADDR_TX_PSC_CAL (0x4106 * 4) +#define TB_ADDR_TX_PSC_RDY (0x4107 * 4) +#define TB_ADDR_RX_PSC_A0 (0x8000 * 4) +#define TB_ADDR_RX_PSC_A1 (0x8001 * 4) +#define TB_ADDR_RX_PSC_A2 (0x8002 * 4) +#define TB_ADDR_RX_PSC_A3 (0x8003 * 4) +#define TB_ADDR_RX_PSC_CAL (0x8006 * 4) +#define TB_ADDR_RX_PSC_RDY (0x8007 * 4) +#define TB_ADDR_TX_TXCC_MGNLS_MULT_000 (0x4058 * 4) +#define TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 * 4) +#define TB_ADDR_RX_SLC_CU_ITER_TMR (0x80e3 * 4) +#define TB_ADDR_RX_SIGDET_HL_FILT_TMR (0x8090 * 4) +#define TB_ADDR_RX_SAMP_DAC_CTRL (0x8058 * 4) +#define TB_ADDR_RX_DIAG_SIGDET_TUNE (0x81dc * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE2 (0x81df * 4) +#define TB_ADDR_RX_DIAG_BS_TM (0x81f5 * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL1 (0x81d3 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM4 (0x81c7 * 4) +#define TB_ADDR_RX_DIAG_ILL_E_TRIM0 (0x81c2 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQ_TRIM0 (0x81c1 * 4) +#define TB_ADDR_RX_DIAG_ILL_IQE_TRIM6 (0x81c9 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM3 (0x81f8 * 4) +#define TB_ADDR_RX_DIAG_RXFE_TM4 (0x81f9 * 4) +#define TB_ADDR_RX_DIAG_LFPSDET_TUNE (0x81dd * 4) +#define TB_ADDR_RX_DIAG_DFE_CTRL3 (0x81d5 * 4) +#define TB_ADDR_RX_DIAG_SC2C_DELAY (0x81e1 * 4) +#define TB_ADDR_RX_REE_VGA_GAIN_NODFE (0x81bf * 4) +#define TB_ADDR_XCVR_PSM_CAL_TMR (0x4002 * 4) +#define TB_ADDR_XCVR_PSM_A0BYP_TMR (0x4004 * 4) +#define TB_ADDR_XCVR_PSM_A0IN_TMR (0x4003 * 4) +#define TB_ADDR_XCVR_PSM_A1IN_TMR (0x4005 * 4) +#define TB_ADDR_XCVR_PSM_A2IN_TMR (0x4006 * 4) +#define TB_ADDR_XCVR_PSM_A3IN_TMR (0x4007 * 4) +#define TB_ADDR_XCVR_PSM_A4IN_TMR (0x4008 * 4) +#define TB_ADDR_XCVR_PSM_A5IN_TMR (0x4009 * 4) +#define TB_ADDR_XCVR_PSM_A0OUT_TMR (0x400a * 4) +#define TB_ADDR_XCVR_PSM_A1OUT_TMR (0x400b * 4) +#define TB_ADDR_XCVR_PSM_A2OUT_TMR (0x400c * 4) +#define TB_ADDR_XCVR_PSM_A3OUT_TMR (0x400d * 4) +#define TB_ADDR_XCVR_PSM_A4OUT_TMR (0x400e * 4) +#define TB_ADDR_XCVR_PSM_A5OUT_TMR (0x400f * 4) +#define TB_ADDR_TX_RCVDET_EN_TMR (0x4122 * 4) +#define TB_ADDR_TX_RCVDET_ST_TMR (0x4123 * 4) +#define TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR (0x40f2 * 4) + +struct cdns3_usb_phy { + struct clk phy_clk; + void __iomem *phy_regs; +}; + +static int cdns3_usb_phy_init(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct cdns3_usb_phy *priv = dev_get_priv(dev); + void __iomem *regs = priv->phy_regs; + + writel(0x0830, regs + PHY_PMA_CMN_CTRL1); + writel(0x10, regs + TB_ADDR_CMN_DIAG_HSCLK_SEL); + writel(0x00F0, regs + TB_ADDR_CMN_PLL0_VCOCAL_INIT_TMR); + writel(0x0018, regs + TB_ADDR_CMN_PLL0_VCOCAL_ITER_TMR); + writel(0x00D0, regs + TB_ADDR_CMN_PLL0_INTDIV); + writel(0x4aaa, regs + TB_ADDR_CMN_PLL0_FRACDIV); + writel(0x0034, regs + TB_ADDR_CMN_PLL0_HIGH_THR); + writel(0x1ee, regs + TB_ADDR_CMN_PLL0_SS_CTRL1); + writel(0x7F03, regs + TB_ADDR_CMN_PLL0_SS_CTRL2); + writel(0x0020, regs + TB_ADDR_CMN_PLL0_DSM_DIAG); + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_OVRD); + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBH_OVRD); + writel(0x0000, regs + TB_ADDR_CMN_DIAG_PLL0_FBL_OVRD); + writel(0x0007, regs + TB_ADDR_CMN_DIAG_PLL0_V2I_TUNE); + writel(0x0027, regs + TB_ADDR_CMN_DIAG_PLL0_CP_TUNE); + writel(0x0008, regs + TB_ADDR_CMN_DIAG_PLL0_LF_PROG); + writel(0x0022, regs + TB_ADDR_CMN_DIAG_PLL0_TEST_MODE); + writel(0x000a, regs + TB_ADDR_CMN_PSM_CLK_CTRL); + writel(0x139, regs + TB_ADDR_XCVR_DIAG_RX_LANE_CAL_RST_TMR); + writel(0xbefc, regs + TB_ADDR_XCVR_PSM_RCTRL); + + writel(0x7799, regs + TB_ADDR_TX_PSC_A0); + writel(0x7798, regs + TB_ADDR_TX_PSC_A1); + writel(0x509b, regs + TB_ADDR_TX_PSC_A2); + writel(0x3, regs + TB_ADDR_TX_DIAG_ECTRL_OVRD); + writel(0x509b, regs + TB_ADDR_TX_PSC_A3); + writel(0x2090, regs + TB_ADDR_TX_PSC_CAL); + writel(0x2090, regs + TB_ADDR_TX_PSC_RDY); + + writel(0xA6FD, regs + TB_ADDR_RX_PSC_A0); + writel(0xA6FD, regs + TB_ADDR_RX_PSC_A1); + writel(0xA410, regs + TB_ADDR_RX_PSC_A2); + writel(0x2410, regs + TB_ADDR_RX_PSC_A3); + + writel(0x23FF, regs + TB_ADDR_RX_PSC_CAL); + writel(0x2010, regs + TB_ADDR_RX_PSC_RDY); + + writel(0x0020, regs + TB_ADDR_TX_TXCC_MGNLS_MULT_000); + writel(0x00ff, regs + TB_ADDR_TX_DIAG_BGREF_PREDRV_DELAY); + writel(0x0002, regs + TB_ADDR_RX_SLC_CU_ITER_TMR); + writel(0x0013, regs + TB_ADDR_RX_SIGDET_HL_FILT_TMR); + writel(0x0000, regs + TB_ADDR_RX_SAMP_DAC_CTRL); + writel(0x1004, regs + TB_ADDR_RX_DIAG_SIGDET_TUNE); + writel(0x4041, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE2); + writel(0x0480, regs + TB_ADDR_RX_DIAG_BS_TM); + writel(0x8006, regs + TB_ADDR_RX_DIAG_DFE_CTRL1); + writel(0x003f, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM4); + writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_E_TRIM0); + writel(0x543f, regs + TB_ADDR_RX_DIAG_ILL_IQ_TRIM0); + writel(0x0000, regs + TB_ADDR_RX_DIAG_ILL_IQE_TRIM6); + writel(0x8000, regs + TB_ADDR_RX_DIAG_RXFE_TM3); + writel(0x0003, regs + TB_ADDR_RX_DIAG_RXFE_TM4); + writel(0x2408, regs + TB_ADDR_RX_DIAG_LFPSDET_TUNE); + writel(0x05ca, regs + TB_ADDR_RX_DIAG_DFE_CTRL3); + writel(0x0258, regs + TB_ADDR_RX_DIAG_SC2C_DELAY); + writel(0x1fff, regs + TB_ADDR_RX_REE_VGA_GAIN_NODFE); + + writel(0x02c6, regs + TB_ADDR_XCVR_PSM_CAL_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0BYP_TMR); + writel(0x02c6, regs + TB_ADDR_XCVR_PSM_A0IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A1IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A2IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A3IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A4IN_TMR); + writel(0x0010, regs + TB_ADDR_XCVR_PSM_A5IN_TMR); + + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A0OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A1OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A2OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A3OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A4OUT_TMR); + writel(0x0002, regs + TB_ADDR_XCVR_PSM_A5OUT_TMR); + + /* Change rx detect parameter */ + writel(0x960, regs + TB_ADDR_TX_RCVDET_EN_TMR); + writel(0x01e0, regs + TB_ADDR_TX_RCVDET_ST_TMR); + writel(0x0090, regs + TB_ADDR_XCVR_DIAG_LANE_FCM_EN_MGN_TMR); + + udelay(10); + return 0; +} + +struct phy_ops cdns3_usb_phy_ops = { + .init = cdns3_usb_phy_init, +}; + +static int cdns3_usb_phy_remove(struct udevice *dev) +{ +#if CONFIG_IS_ENABLED(CLK) + struct cdns3_usb_phy *priv = dev_get_priv(dev); + int ret; + + if (priv->phy_clk.dev) { + ret = clk_disable(&priv->phy_clk); + if (ret) + return ret; + + ret = clk_free(&priv->phy_clk); + if (ret) + return ret; + } +#endif + + return 0; +} + +static int cdns3_usb_phy_probe(struct udevice *dev) +{ + struct cdns3_usb_phy *priv = dev_get_priv(dev); + +#if CONFIG_IS_ENABLED(CLK) + int ret; + + ret = clk_get_by_name(dev, "main_clk", &priv->phy_clk); + if (ret) { + printf("Failed to get phy_clk\n"); + return ret; + } + + ret = clk_enable(&priv->phy_clk); + if (ret) { + printf("Failed to enable phy_clk\n"); + return ret; + } +#endif + priv->phy_regs = (void *__iomem)devfdt_get_addr(dev); + + return 0; +} + +static const struct udevice_id cdns3_usb_phy_ids[] = { + { .compatible = "cdns,usb3-phy" }, + { } +}; + +U_BOOT_DRIVER(cdns3_usb_phy) = { + .name = "cdns3_usb_phy", + .id = UCLASS_PHY, + .of_match = cdns3_usb_phy_ids, + .probe = cdns3_usb_phy_probe, + .remove = cdns3_usb_phy_remove, + .ops = &cdns3_usb_phy_ops, + .priv_auto = sizeof(struct cdns3_usb_phy), +}; diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index ec55351e61e..6c3d61157ec 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -63,7 +63,6 @@ config PINCTRL_IMX7ULP config PINCTRL_IMX8 bool "IMX8 pinctrl driver" depends on ARCH_IMX8 && PINCTRL_FULL - select DEVRES select PINCTRL_IMX select PINCTRL_IMX_SCU help @@ -78,7 +77,6 @@ config PINCTRL_IMX8 config PINCTRL_IMX8M bool "IMX8M pinctrl driver" depends on ARCH_IMX8M && PINCTRL_FULL - select DEVRES select PINCTRL_IMX help Say Y here to enable the imx8m pinctrl driver diff --git a/drivers/power/domain/imx8-power-domain-legacy.c b/drivers/power/domain/imx8-power-domain-legacy.c index e2fae2dbc86..a79a116687a 100644 --- a/drivers/power/domain/imx8-power-domain-legacy.c +++ b/drivers/power/domain/imx8-power-domain-legacy.c @@ -128,8 +128,13 @@ static int imx8_power_domain_on(struct power_domain *power_domain) return 0; if (pdata->resource_id != SC_R_NONE) { - if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) + if (!sc_rm_is_resource_owned(-1, pdata->resource_id)) { printf("%s [%d] not owned by curr partition\n", dev->name, pdata->resource_id); +#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) || defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) + /* avoid failing probe, else some group of resources (gpios) may never work */ + return 0; +#endif + } ret = sc_pm_set_resource_power_mode(-1, pdata->resource_id, SC_PM_PW_MODE_ON); diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c index af829db9da1..9f6a45d4d30 100644 --- a/drivers/power/domain/power-domain-uclass.c +++ b/drivers/power/domain/power-domain-uclass.c @@ -2,13 +2,13 @@ /* * Copyright (c) 2016, NVIDIA CORPORATION. */ - #include #include #include #include #include #include +#include #include static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev) @@ -31,6 +31,45 @@ static int power_domain_of_xlate_default(struct power_domain *power_domain, return 0; } +int power_domain_lookup_name(const char *name, struct power_domain *power_domain) +{ + struct udevice *dev; + struct power_domain_ops *ops; + int ret; + + debug("%s(power_domain=%p name=%s)\n", __func__, power_domain, name); + + ret = uclass_find_device_by_name(UCLASS_POWER_DOMAIN, name, &dev); + if (!ret) { + /* Probe the dev */ + device_probe(dev); + ops = power_domain_dev_ops(dev); + + power_domain->dev = dev; + if (ops->of_xlate) + ret = ops->of_xlate(power_domain, NULL); + else + ret = power_domain_of_xlate_default(power_domain, NULL); + if (ret) { + debug("of_xlate() failed: %d\n", ret); + return ret; + } + + ret = ops->request(power_domain); + if (ret) { + debug("ops->request() failed: %d\n", ret); + return ret; + } + + debug("%s ok: %s\n", __func__, dev->name); + + return 0; + } + + printf("%s fail: %s, ret = %d\n", __func__, name, ret); + return -EINVAL; +} + int power_domain_get_by_index(struct udevice *dev, struct power_domain *power_domain, int index) { diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index 7b4c0f02c60..0ab654450ad 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o obj-$(CONFIG_POWER_MAX77696) += pmic_max77696.o +obj-$(CONFIG_POWER_BD71837) += pmic_bd71837.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_PCA9450) += pmic_pca9450.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index a886647f193..2394b196c56 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -83,6 +83,7 @@ static struct dm_pmic_ops pca9450_ops = { static const struct udevice_id pca9450_ids[] = { { .compatible = "nxp,pca9450a", .data = 0x25, }, { .compatible = "nxp,pca9450b", .data = 0x25, }, + { .compatible = "nxp,pca9450c", .data = 0x25, }, { } }; diff --git a/drivers/power/pmic/pmic_bd71837.c b/drivers/power/pmic/pmic_bd71837.c new file mode 100644 index 00000000000..4b3cb4a70a8 --- /dev/null +++ b/drivers/power/pmic/pmic_bd71837.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2014 Gateworks Corporation + * Tim Harvey + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static const char bd71837_name[] = "BD71837"; +int power_bd71837_init (unsigned char bus) { + struct pmic *p = pmic_alloc(); + + if (!p) { + printf("%s: POWER allocation error!\n", __func__); + return -ENOMEM; + } + + p->name = bd71837_name; + p->interface = PMIC_I2C; + p->number_of_regs = BD718XX_MAX_REGISTER; + p->hw.i2c.addr = 0x4b; + p->hw.i2c.tx_num = 1; + p->bus = bus; + + printf("power_bd71837_init\n"); + + return 0; +} diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index f5b3f8826fb..e89381a1e49 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -197,4 +197,11 @@ config RESET_SCMI Enable this option if you want to support reset controller devices exposed by a SCMI agent based on SCMI reset domain protocol communication with a SCMI server. + +config RESET_DISPMIX + bool "i.MX8M Display MIX Reset Driver" + depends on DM_RESET && ARCH_IMX8M && DM_VIDEO + default n + help + Support for reset controller on i.MX8M SoCs. endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 8a0f5280761..b2dc98bfe54 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -29,3 +29,4 @@ obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o obj-$(CONFIG_RESET_SCMI) += reset-scmi.o +obj-$(CONFIG_RESET_DISPMIX) += reset-dispmix.o diff --git a/drivers/reset/reset-dispmix.c b/drivers/reset/reset-dispmix.c new file mode 100644 index 00000000000..cfc1c5f0e31 --- /dev/null +++ b/drivers/reset/reset-dispmix.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* DISPMIX GPR registers */ +#define DISPLAY_MIX_SFT_RSTN_CSR 0x00 +#define DISPLAY_MIX_CLK_EN_CSR 0x00 +#define GPR_MIPI_RESET_DIV 0x00 + +struct dispmix_reset_priv { + struct regmap *map; + bool active_low; +}; + +struct dispmix_reset_entry { + uint32_t reg_off; + uint32_t bit_off; +}; + +struct dispmix_reset_drvdata { + const struct dispmix_reset_entry *resets; + ulong nr_resets; +}; + +#define RESET_ENTRY(id, reg, bit) \ + [id] = { .reg_off = (reg), .bit_off = (bit) } + +static const struct dispmix_reset_entry imx8mm_sft_rstn[] = { + /* dispmix reset entry */ + RESET_ENTRY(IMX8MM_CSI_BRIDGE_CHIP_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 0), + RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_HARD_ASYNC_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 1), + RESET_ENTRY(IMX8MM_CSI_BRIDGE_CSI_HRESET, + DISPLAY_MIX_SFT_RSTN_CSR, 2), + RESET_ENTRY(IMX8MM_CAMERA_PIXEL_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 3), + RESET_ENTRY(IMX8MM_MIPI_CSI_I_PRESET, + DISPLAY_MIX_SFT_RSTN_CSR, 4), + RESET_ENTRY(IMX8MM_MIPI_DSI_I_PRESET, + DISPLAY_MIX_SFT_RSTN_CSR, 5), + RESET_ENTRY(IMX8MM_BUS_RSTN_BLK_SYNC, + DISPLAY_MIX_SFT_RSTN_CSR, 6), +}; + +static const struct dispmix_reset_entry imx8mm_clk_en[] = { + /* dispmix clock enable entry */ + RESET_ENTRY(IMX8MM_CSI_BRIDGE_CSI_HCLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 0), + RESET_ENTRY(IMX8MM_CSI_BRIDGE_SPU_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 1), + RESET_ENTRY(IMX8MM_CSI_BRIDGE_MEM_WRAPPER_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 2), + RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 3), + RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_CLK_S_EN, + DISPLAY_MIX_CLK_EN_CSR, 4), + RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_CLK_S_RAW_EN, + DISPLAY_MIX_CLK_EN_CSR, 5), + RESET_ENTRY(IMX8MM_LCDIF_APB_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 6), + RESET_ENTRY(IMX8MM_LCDIF_PIXEL_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 7), + RESET_ENTRY(IMX8MM_MIPI_DSI_PCLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 8), + RESET_ENTRY(IMX8MM_MIPI_DSI_CLKREF_EN, + DISPLAY_MIX_CLK_EN_CSR, 9), + RESET_ENTRY(IMX8MM_MIPI_CSI_ACLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 10), + RESET_ENTRY(IMX8MM_MIPI_CSI_PCLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 11), + RESET_ENTRY(IMX8MM_BUS_BLK_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 12), +}; + +static const struct dispmix_reset_entry imx8mm_mipi_rst[] = { + /* mipi lanes reset entry */ + RESET_ENTRY(IMX8MM_MIPI_S_RESET, + GPR_MIPI_RESET_DIV, 16), + RESET_ENTRY(IMX8MM_MIPI_M_RESET, + GPR_MIPI_RESET_DIV, 17), +}; + +static const struct dispmix_reset_entry imx8mn_sft_rstn[] = { + /* dispmix reset entry */ + RESET_ENTRY(IMX8MN_MIPI_DSI_PCLK_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 0), + RESET_ENTRY(IMX8MN_MIPI_DSI_CLKREF_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 1), + RESET_ENTRY(IMX8MN_MIPI_CSI_PCLK_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 2), + RESET_ENTRY(IMX8MN_MIPI_CSI_ACLK_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 3), + RESET_ENTRY(IMX8MN_LCDIF_PIXEL_CLK_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 4), + RESET_ENTRY(IMX8MN_LCDIF_APB_CLK_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 5), + RESET_ENTRY(IMX8MN_ISI_PROC_CLK_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 6), + RESET_ENTRY(IMX8MN_ISI_APB_CLK_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 7), + RESET_ENTRY(IMX8MN_BUS_BLK_CLK_RESET, + DISPLAY_MIX_SFT_RSTN_CSR, 8), +}; + +static const struct dispmix_reset_entry imx8mn_clk_en[] = { + /* dispmix clock enable entry */ + RESET_ENTRY(IMX8MN_MIPI_DSI_PCLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 0), + RESET_ENTRY(IMX8MN_MIPI_DSI_CLKREF_EN, + DISPLAY_MIX_CLK_EN_CSR, 1), + RESET_ENTRY(IMX8MN_MIPI_CSI_PCLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 2), + RESET_ENTRY(IMX8MN_MIPI_CSI_ACLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 3), + RESET_ENTRY(IMX8MN_LCDIF_PIXEL_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 4), + RESET_ENTRY(IMX8MN_LCDIF_APB_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 5), + RESET_ENTRY(IMX8MN_ISI_PROC_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 6), + RESET_ENTRY(IMX8MN_ISI_APB_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 7), + RESET_ENTRY(IMX8MN_BUS_BLK_CLK_EN, + DISPLAY_MIX_CLK_EN_CSR, 8), +}; + +static const struct dispmix_reset_entry imx8mn_mipi_rst[] = { + /* mipi lanes reset entry */ + RESET_ENTRY(IMX8MN_MIPI_S_RESET, + GPR_MIPI_RESET_DIV, 16), + RESET_ENTRY(IMX8MN_MIPI_M_RESET, + GPR_MIPI_RESET_DIV, 17), +}; + +static const struct dispmix_reset_drvdata imx8mm_sft_rstn_pdata = { + .resets = imx8mm_sft_rstn, + .nr_resets = IMX8MM_DISPMIX_SFT_RSTN_NUM, +}; + +static const struct dispmix_reset_drvdata imx8mm_clk_en_pdata = { + .resets = imx8mm_clk_en, + .nr_resets = IMX8MM_DISPMIX_CLK_EN_NUM, +}; + +static const struct dispmix_reset_drvdata imx8mm_mipi_rst_pdata = { + .resets = imx8mm_mipi_rst, + .nr_resets = IMX8MM_MIPI_RESET_NUM, +}; + +static const struct dispmix_reset_drvdata imx8mn_sft_rstn_pdata = { + .resets = imx8mn_sft_rstn, + .nr_resets = IMX8MN_DISPMIX_SFT_RSTN_NUM, +}; + +static const struct dispmix_reset_drvdata imx8mn_clk_en_pdata = { + .resets = imx8mn_clk_en, + .nr_resets = IMX8MN_DISPMIX_CLK_EN_NUM, +}; + +static const struct dispmix_reset_drvdata imx8mn_mipi_rst_pdata = { + .resets = imx8mn_mipi_rst, + .nr_resets = IMX8MN_MIPI_RESET_NUM, +}; + +static const struct udevice_id dispmix_reset_dt_ids[] = { + { + .compatible = "fsl,imx8mm-dispmix-sft-rstn", + .data = (ulong)&imx8mm_sft_rstn_pdata, + }, + { + .compatible = "fsl,imx8mm-dispmix-clk-en", + .data = (ulong)&imx8mm_clk_en_pdata, + }, + { + .compatible = "fsl,imx8mm-dispmix-mipi-rst", + .data = (ulong)&imx8mm_mipi_rst_pdata, + }, + { + .compatible = "fsl,imx8mn-dispmix-sft-rstn", + .data = (ulong)&imx8mn_sft_rstn_pdata, + }, + { + .compatible = "fsl,imx8mn-dispmix-clk-en", + .data = (ulong)&imx8mn_clk_en_pdata, + }, + { + .compatible = "fsl,imx8mn-dispmix-mipi-rst", + .data = (ulong)&imx8mn_mipi_rst_pdata, + }, + { /* sentinel */ } +}; + +static int dispmix_reset_assert(struct reset_ctl *rst) +{ + const struct dispmix_reset_entry *rstent; + struct dispmix_reset_priv *priv = (struct dispmix_reset_priv *)dev_get_priv(rst->dev); + const struct dispmix_reset_drvdata *drvdata = (const struct dispmix_reset_drvdata *)dev_get_driver_data(rst->dev); + + + if (rst->id >= drvdata->nr_resets) { + pr_info("dispmix reset: %lu is not a valid line\n", rst->id); + return -EINVAL; + } + + rstent = &drvdata->resets[rst->id]; + + regmap_update_bits(priv->map, rstent->reg_off, + 1 << rstent->bit_off, + !priv->active_low << rstent->bit_off); + + return 0; +} + +static int dispmix_reset_deassert(struct reset_ctl *rst) +{ + const struct dispmix_reset_entry *rstent; + struct dispmix_reset_priv *priv = (struct dispmix_reset_priv *)dev_get_priv(rst->dev); + const struct dispmix_reset_drvdata *drvdata = + (const struct dispmix_reset_drvdata *)dev_get_driver_data(rst->dev); + + + if (rst->id >= drvdata->nr_resets) { + pr_info("dispmix reset: %lu is not a valid line\n", rst->id); + return -EINVAL; + } + + rstent = &drvdata->resets[rst->id]; + + regmap_update_bits(priv->map, rstent->reg_off, + 1 << rstent->bit_off, + !!priv->active_low << rstent->bit_off); + + return 0; +} + +static int dispmix_reset_free(struct reset_ctl *rst) +{ + return 0; +} + +static int dispmix_reset_request(struct reset_ctl *rst) +{ + return 0; +} + +static const struct reset_ops dispmix_reset_ops = { + .request = dispmix_reset_request, + .rfree = dispmix_reset_free, + .rst_assert = dispmix_reset_assert, + .rst_deassert = dispmix_reset_deassert, +}; + +static int dispmix_reset_probe(struct udevice *dev) +{ + struct dispmix_reset_priv *priv = (struct dispmix_reset_priv *)dev_get_priv(dev); + int ret; + + priv->active_low = dev_read_bool(dev, "active_low"); + + ret = regmap_init_mem(dev_ofnode(dev), &priv->map); + if (ret) { + debug("%s: Could not initialize regmap (err = %d)\n", dev->name, + ret); + return ret; + } + + return 0; +} + +U_BOOT_DRIVER(dispmix_reset) = { + .name = "dispmix_reset", + .id = UCLASS_RESET, + .of_match = dispmix_reset_dt_ids, + .ops = &dispmix_reset_ops, + .probe = dispmix_reset_probe, + .priv_auto = sizeof(struct dispmix_reset_priv), +}; diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index 071c389ca07..8d14a6021b3 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -142,6 +142,42 @@ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk) return __reset_get_bulk(dev, dev_ofnode(dev), bulk); } +int reset_get_bulk_nodev(ofnode node, struct reset_ctl_bulk *bulk) +{ + int i, ret, err, count; + + bulk->count = 0; + + count = ofnode_count_phandle_with_args(node, "resets", "#reset-cells", + 0); + if (count < 1) + return count; + + bulk->resets = kzalloc(count * sizeof(struct reset_ctl), + GFP_KERNEL); + if (!bulk->resets) + return -ENOMEM; + + for (i = 0; i < count; i++) { + ret = reset_get_by_index_nodev(node, i, &bulk->resets[i]); + if (ret < 0) + goto bulk_get_err; + + ++bulk->count; + } + + return 0; + +bulk_get_err: + err = reset_release_all(bulk->resets, bulk->count); + if (err) + debug("%s: could release all resets\n", + __func__); + + return ret; +} + + int reset_get_by_name(struct udevice *dev, const char *name, struct reset_ctl *reset_ctl) { diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 8a87eed6839..95d18420e57 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -200,8 +200,17 @@ static void _serial_putc(struct udevice *dev, char ch) static void _serial_puts(struct udevice *dev, const char *str) { - while (*str) - _serial_putc(dev, *str++); + struct dm_serial_ops *ops = serial_get_ops(dev); + int err; + + if (ops->puts) { + do { + err = ops->puts(dev, str); + } while (err == -EAGAIN); + } else { + while (*str) + _serial_putc(dev, *str++); + } } static int __serial_getc(struct udevice *dev) diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index dea25a049c8..94f9d344372 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -128,6 +128,7 @@ serial_initfunc(pl01x_serial_initialize); serial_initfunc(pxa_serial_initialize); serial_initfunc(sh_serial_initialize); serial_initfunc(mtk_serial_initialize); +serial_initfunc(xen_debug_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -182,6 +183,7 @@ int serial_initialize(void) pxa_serial_initialize(); sh_serial_initialize(); mtk_serial_initialize(); + xen_debug_serial_initialize(); serial_assign(default_serial_console()->name); diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 2b473d70f64..3067bebd7d3 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -492,18 +492,30 @@ static int lpuart_serial_probe(struct udevice *dev) { #if CONFIG_IS_ENABLED(CLK) struct clk per_clk; + struct clk ipg_clk; int ret; ret = clk_get_by_name(dev, "per", &per_clk); if (!ret) { ret = clk_enable(&per_clk); if (ret) { - dev_err(dev, "Failed to get per clk: %d\n", ret); + dev_err(dev, "Failed to enable per clk: %d\n", ret); return ret; } } else { debug("%s: Failed to get per clk: %d\n", __func__, ret); } + + ret = clk_get_by_name(dev, "ipg", &ipg_clk); + if (!ret) { + ret = clk_enable(&ipg_clk); + if (ret) { + dev_err(dev, "Failed to enable ipg clk: %d\n", ret); + return ret; + } + } else { + debug("%s: Failed to get ipg clk: %d\n", __func__, ret); + } #endif if (is_lpuart32(dev)) diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index e4970a169bd..058f526b2cc 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -217,12 +217,27 @@ static void mxc_serial_putc(const char c) WATCHDOG_RESET(); } -/* Test whether a character is in the RX buffer */ +/* + * Test whether a character is in the RX buffer + */ +static int one_time_rx_line_always_low_workaround_needed = 1; static int mxc_serial_tstc(void) { /* If receive fifo is empty, return false */ if (readl(&mxc_base->ts) & UTS_RXEMPTY) return 0; + + /* Empty RX FIFO if receiver is stuck because of RXD line being low */ + if (one_time_rx_line_always_low_workaround_needed) { + one_time_rx_line_always_low_workaround_needed = 0; + if (!(readl(&mxc_base->sr2) & USR2_RDR)) { + while (!(readl(&mxc_base->ts) & UTS_RXEMPTY)) { + (void) readl(&mxc_base->rxd); + } + return 0; + } + } + return 1; } diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c index e1d5b229bd7..039baf43a81 100644 --- a/drivers/serial/serial_xen.c +++ b/drivers/serial/serial_xen.c @@ -181,3 +181,62 @@ U_BOOT_DRIVER(serial_xen) = { #endif }; +#ifndef CONFIG_DM_SERIAL +extern void xenprintf(const char *buf); +extern void xenprintc(const char c); + +static void xen_debug_serial_putc(const char c) +{ + /* If \n, also do \r */ + if (c == '\n') + serial_putc('\r'); + + xenprintc(c); +} + +static void xen_debug_serial_puts(const char *buf) +{ + xenprintf(buf); +} + +static int xen_debug_serial_start(void) +{ + return 0; +} + +static void xen_debug_serial_setbrg(void) +{ + +} + +static int xen_debug_serial_getc(void) +{ + return 0; +} + +static int xen_debug_serial_tstc(void) +{ + return 0; +} + +static struct serial_device xen_debug_serial_drv = { + .name = "xen_debug_serial", + .start = xen_debug_serial_start, + .stop = NULL, + .setbrg = xen_debug_serial_setbrg, + .putc = xen_debug_serial_putc, + .puts = xen_debug_serial_puts, + .getc = xen_debug_serial_getc, + .tstc = xen_debug_serial_tstc, +}; + +void xen_debug_serial_initialize(void) +{ + serial_register(&xen_debug_serial_drv); +} + +__weak struct serial_device *default_serial_console(void) +{ + return &xen_debug_serial_drv; +} +#endif diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 1494c917635..8be85e83d90 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -469,6 +469,13 @@ config FSL_ESPI access the SPI interface and SPI NOR flash on platforms embedding this Freescale eSPI IP core. +config FSL_FSPI_NAND + bool "Freescale FlexSPI driver for SPI NAND" + help + Enable the Freescale FlexSPI (FSPI) NAND driver. This driver can be + used to access the SPI NAND flash on platforms embedding this + Freescale IP core. + config SH_QSPI bool "Renesas Quad SPI driver" help @@ -481,4 +488,10 @@ config MXC_SPI Enable the MXC SPI controller driver. This driver can be used on various i.MX SoCs such as i.MX31/35/51/6/7. +config FSL_LPSPI + bool "FSL LPSPI Driver" + help + Enable the FSL LPSPI controller driver. This driver can be used + on various i.MX SoCs such as i.MX7ULP/8QM/8QXP/8DX/8DXL. + endif # menu "SPI Support" diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index cfe4fae1d4b..003216ff84e 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -30,6 +30,8 @@ obj-$(CONFIG_DESIGNWARE_SPI) += designware_spi.o obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o obj-$(CONFIG_FSL_ESPI) += fsl_espi.o +obj-$(CONFIG_FSL_LPSPI) += fsl_lpspi.o +obj-$(CONFIG_FSL_FSPI_NAND) += fsl_fspi_nand.o obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o obj-$(CONFIG_ICH_SPI) += ich.o obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o diff --git a/drivers/spi/fsl_fspi_nand.c b/drivers/spi/fsl_fspi_nand.c new file mode 100644 index 00000000000..f5ea338fa71 --- /dev/null +++ b/drivers/spi/fsl_fspi_nand.c @@ -0,0 +1,988 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fsl_fspi.h" +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define FSL_FSPI_NAND_SIZE SZ_4G +#define FSL_FSPI_NAND_NUM 1 +#define RX_BUFFER_SIZE 0x200 +#define TX_BUFFER_SIZE 0x400 +#define AHB_BUFFER_SIZE 0x800 + +#define FLASH_STATUS_WEL 0x02 + +#define FSPI_NAND_CAS 12 + +/* SEQID */ +enum fspi_lut_id { + SEQID_RESET = 0, + SEQID_WREN = 1, + SEQID_READID = 2, + SEQID_SET_FEATURE = 3, + SEQID_GET_FEATURE = 4, + SEQID_BLK_ERASE = 5, + SEQID_PAGE_READ = 6, + SEQID_READ_FROM_CACHE_NORMAL = 7, + SEQID_READ_FROM_CACHE_FAST = 8, + SEQID_READ_FROM_CACHE_X2 = 9, + SEQID_READ_FROM_CACHE_X4 = 10, + SEQID_READ_FROM_CACHE_DUALIO = 11, + SEQID_READ_FROM_CACHE_QUADIO = 12, + SEQID_PROG_EXEC = 13, + SEQID_PROG_LOAD = 14, + SEQID_PROG_LOAD_RANDOM = 15, + SEQID_PROG_LOAD_X4 = 16, + SEQID_PROG_LOAD_RANDOM_X4 = 17, + SEQID_END, +}; + +/* SPI NAND CMD */ +#define SPINAND_CMD_RESET 0xff +#define SPINAND_CMD_WREN 0x06 +#define SPINAND_CMD_READID 0x9f +#define SPINAND_CMD_SET_FEATURE 0x1f +#define SPINAND_CMD_GET_FEATURE 0x0f +#define SPINAND_CMD_BLK_ERASE 0xd8 +#define SPINAND_CMD_PAGE_READ 0x13 +#define SPINAND_CMD_PAGE_READ_FROM_CACHE_NORMAL 0x03 +#define SPINAND_CMD_PAGE_READ_FROM_CACHE_FAST 0x0b +#define SPINAND_CMD_PAGE_READ_FROM_CACHE_X2 0x3b +#define SPINAND_CMD_PAGE_READ_FROM_CACHE_X4 0x6b +#define SPINAND_CMD_PAGE_READ_FROM_CACHE_DUALIO 0xbb +#define SPINAND_CMD_PAGE_READ_FROM_CACHE_QUADIO 0xeb +#define SPINAND_CMD_PROG_EXEC 0x10 +#define SPINAND_CMD_PROG_LOAD 0x02 +#define SPINAND_CMD_PROG_LOAD_RANDOM 0x84 +#define SPINAND_CMD_PROG_LOAD_X4 0x32 +#define SPINAND_CMD_PROG_LOAD_RANDOM_X4 0x34 + +/* fsl_fspi_platdata flags */ +#define FSPI_FLAG_REGMAP_ENDIAN_BIG BIT(0) + +/* default SCK frequency, unit: HZ */ +#define FSL_FSPI_DEFAULT_SCK_FREQ 50000000 + +/* FSPI max chipselect signals number */ +#define FSL_FSPI_MAX_CHIPSELECT_NUM 4 + +/** + * struct fsl_fspi_platdata - platform data for NXP FSPI + * + * @flags: Flags for FSPI FSPI_FLAG_... + * @speed_hz: Default SCK frequency + * @reg_base: Base address of FSPI registers + * @amba_base: Base address of FSPI memory mapping + * @amba_total_size: size of FSPI memory mapping + * @flash_num: Number of active slave devices + * @num_chipselect: Number of FSPI chipselect signals + */ +struct fsl_fspi_platdata { + u32 flags; + u32 speed_hz; + u32 reg_base; + u32 amba_base; + u32 amba_total_size; + u32 flash_num; + u32 num_chipselect; +}; + +/** + * struct fsl_fspi_priv - private data for NXP FSPI + * + * @flags: Flags for FSPI FSPI_FLAG_... + * @bus_clk: FSPI input clk frequency + * @speed_hz: Default SCK frequency + * @cur_seqid: current LUT table sequence id + * @sf_addr: flash access offset + * @amba_base: Base address of FSPI memory mapping of every CS + * @amba_total_size: size of FSPI memory mapping + * @cur_amba_base: Base address of FSPI memory mapping of current CS + * @flash_num: Number of active slave devices + * @num_chipselect: Number of FSPI chipselect signals + * @regs: Point to FSPI register structure for I/O access + */ +struct fsl_fspi_priv { + u32 flags; + u32 bus_clk; + u32 speed_hz; + u32 cur_seqid; + u32 sf_addr; + u32 amba_base[FSL_FSPI_MAX_CHIPSELECT_NUM]; + u32 amba_total_size; + u32 cur_amba_base; + u32 flash_num; + u32 num_chipselect; + struct fsl_fspi_regs *regs; +}; + +struct fspi_cmd_func_pair { + u8 cmd; + int (*fspi_op_func)(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op); +}; + +static u32 fspi_read32(u32 flags, u32 *addr) +{ + return flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ? + in_be32(addr) : in_le32(addr); +} + +static void fspi_write32(u32 flags, u32 *addr, u32 val) +{ + flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ? + out_be32(addr, val) : out_le32(addr, val); +} + +static void fspi_nand_set_lut(struct fsl_fspi_priv *priv) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 lut_base; + + /* Unlock the LUT */ + fspi_write32(priv->flags, ®s->lutkey, FLEXSPI_LUTKEY_VALUE); + fspi_write32(priv->flags, ®s->lutcr, FLEXSPI_LCKER_UNLOCK); + + /* RESET */ + lut_base = SEQID_RESET * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_RESET) | PAD0(LUT_PAD1) | + INSTR0(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Write Enable */ + lut_base = SEQID_WREN * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(SPINAND_CMD_WREN) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Read ID*/ + lut_base = SEQID_READID * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(SPINAND_CMD_READID) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(4) | + PAD1(LUT_PAD1) | INSTR1(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Set Feature */ + lut_base = SEQID_SET_FEATURE * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(SPINAND_CMD_SET_FEATURE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0xB0) | + PAD1(LUT_PAD1) | INSTR1(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(1) | + PAD0(LUT_PAD1) | INSTR0(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Get Feature */ + lut_base = SEQID_GET_FEATURE * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(SPINAND_CMD_GET_FEATURE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0xC0) | + PAD1(LUT_PAD1) | INSTR1(LUT_CMD)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(1) | + PAD0(LUT_PAD1) | INSTR0(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Erase a block */ + lut_base = SEQID_BLK_ERASE * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], OPRND0(SPINAND_CMD_BLK_ERASE) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Page read */ + lut_base = SEQID_PAGE_READ * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PAGE_READ) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Read from cache normal */ + lut_base = SEQID_READ_FROM_CACHE_NORMAL * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_NORMAL) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(8) | + PAD1(LUT_PAD1) | INSTR1(LUT_DUMMY)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], OPRND0(0) | + PAD0(LUT_PAD1) | INSTR0(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Read from cache fast */ + lut_base = SEQID_READ_FROM_CACHE_FAST * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_FAST) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(8) | + PAD1(LUT_PAD1) | INSTR1(LUT_DUMMY)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], OPRND0(0) | + PAD0(LUT_PAD1) | INSTR0(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Read from cache x2 */ + lut_base = SEQID_READ_FROM_CACHE_X2 * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_X2) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(8) | + PAD1(LUT_PAD1) | INSTR1(LUT_DUMMY)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], OPRND0(0) | + PAD0(LUT_PAD2) | INSTR0(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Read from cache x4 */ + lut_base = SEQID_READ_FROM_CACHE_X4 * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_X4) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(8) | + PAD1(LUT_PAD1) | INSTR1(LUT_DUMMY)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], OPRND0(0) | + PAD0(LUT_PAD4) | INSTR0(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Read from cache dual IO */ + lut_base = SEQID_READ_FROM_CACHE_DUALIO * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_DUALIO) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD2) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD2) | INSTR0(LUT_CADDR_SDR) | OPRND1(4) | + PAD1(LUT_PAD2) | INSTR1(LUT_DUMMY)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], OPRND0(0) | + PAD0(LUT_PAD2) | INSTR0(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Read from cache Quad IO */ + lut_base = SEQID_READ_FROM_CACHE_QUADIO * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PAGE_READ_FROM_CACHE_QUADIO) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD4) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD4) | INSTR0(LUT_CADDR_SDR) | OPRND1(4) | + PAD1(LUT_PAD4) | INSTR1(LUT_DUMMY)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], OPRND0(0) | + PAD0(LUT_PAD4) | INSTR0(LUT_READ)); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Program execute */ + lut_base = SEQID_PROG_EXEC * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PROG_EXEC) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR24BIT) | + PAD1(LUT_PAD1) | INSTR1(LUT_ADDR)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Program load */ + lut_base = SEQID_PROG_LOAD * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PROG_LOAD) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Program load random */ + lut_base = SEQID_PROG_LOAD_RANDOM * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PROG_LOAD_RANDOM) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Program load x4 */ + lut_base = SEQID_PROG_LOAD_X4 * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PROG_LOAD_X4) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(0) | + PAD1(LUT_PAD4) | INSTR1(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Program load random x4 */ + lut_base = SEQID_PROG_LOAD_RANDOM_X4 * 4; + fspi_write32(priv->flags, ®s->lut[lut_base], + OPRND0(SPINAND_CMD_PROG_LOAD_RANDOM_X4) | + PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(0) | + PAD1(LUT_PAD1) | INSTR1(LUT_MODE4)); + fspi_write32(priv->flags, ®s->lut[lut_base + 1], OPRND0(ADDR12BIT) | + PAD0(LUT_PAD1) | INSTR0(LUT_CADDR_SDR) | OPRND1(0) | + PAD1(LUT_PAD4) | INSTR1(LUT_WRITE)); + fspi_write32(priv->flags, ®s->lut[lut_base + 2], 0); + fspi_write32(priv->flags, ®s->lut[lut_base + 3], 0); + + /* Lock the LUT */ + fspi_write32(priv->flags, ®s->lutkey, FLEXSPI_LUTKEY_VALUE); + fspi_write32(priv->flags, ®s->lutcr, FLEXSPI_LCKER_LOCK); +} + +static int fspi_nand_op_cmd(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 addr = priv->cur_amba_base; + + debug("%s seqid=%u, addr_nbytes = %u, addr_val = %llx\n", + __func__, seqid, op->addr.nbytes, op->addr.val); + + if (op->addr.nbytes != 0) + addr = (op->addr.val << FSPI_NAND_CAS) + addr; + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, addr); + + fspi_write32(priv->flags, ®s->ipcr1, + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | 0); + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); + + return 0; +} + +static void fspi_nand_set_oprnd1(struct fsl_fspi_priv *priv, u32 seqid, u8 oprnd) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 lut_base, val; + + debug("set oprnd1 %u\n", oprnd); + + /* Unlock the LUT */ + fspi_write32(priv->flags, ®s->lutkey, FLEXSPI_LUTKEY_VALUE); + fspi_write32(priv->flags, ®s->lutcr, FLEXSPI_LCKER_UNLOCK); + + lut_base = seqid * 4; + val = fspi_read32(priv->flags, ®s->lut[lut_base]); + val &= ~(OPRND1(0xff)); + fspi_write32(priv->flags, ®s->lut[lut_base], + val | OPRND1(oprnd)); + + /* Lock the LUT */ + fspi_write32(priv->flags, ®s->lutkey, FLEXSPI_LUTKEY_VALUE); + fspi_write32(priv->flags, ®s->lutcr, FLEXSPI_LCKER_LOCK); +} + +static int fspi_nand_op_read_reg(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 data, size, len = op->data.nbytes; + int i; + u8 *rxbuf = op->data.buf.in; + + debug("%s seqid=%u, data_nbytes = %u, data_buf_in = %lx\n", + __func__, seqid, op->data.nbytes, (ulong)rxbuf); + + if (op->addr.nbytes == 1) { + fspi_nand_set_oprnd1(priv, seqid, (u8)op->addr.val); + } else if (op->addr.nbytes != 0) { + printf("Error: %s seqid=%u, reg addr size is %u\n", + __func__, seqid, op->addr.nbytes); + return -EINVAL; + } + + /* invalid the RXFIFO first */ + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + fspi_write32(priv->flags, ®s->ipcr1, + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | len); + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + i = 0; + while ((32 >= len) && (len > 0)) { + data = fspi_read32(priv->flags, ®s->rfdr[i]); + + debug("rfdr 0x%x\n", data); + size = (len < 4) ? len : 4; + memcpy(rxbuf, &data, size); + len -= size; + rxbuf += size; + i++; + } + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPRXWA_MASK); + + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPCMDDONE_MASK); + + return 0; +} + +static int fspi_nand_op_write_reg(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op) +{ + struct fsl_fspi_regs *regs = priv->regs; + u32 data, size, len = op->data.nbytes; + int i; + u8 *txbuf = (u8 *)(op->data.buf.out); + + debug("%s seqid=%u, data_nbytes = %u, data_buf_out = %lx\n", + __func__, seqid, op->data.nbytes, (ulong)txbuf); + + if (op->addr.nbytes != 1) { + printf("Error: fspi_nand_%s seqid=%u, reg addr size is %u\n", + __func__, seqid, op->addr.nbytes); + return -EINVAL; + } + + fspi_nand_set_oprnd1(priv, seqid, (u8)op->addr.val); + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPTXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, priv->cur_amba_base); + + i = 0; + while ((32 >= len) && (len > 0)) { + data = 0; + size = (len < 4) ? len : 4; + memcpy(&data, txbuf, size); + fspi_write32(priv->flags, ®s->tfdr[i], data); + len -= size; + txbuf += size; + i++; + } + fspi_write32(priv->flags, ®s->intr, FLEXSPI_INTR_IPTXWE_MASK); + + fspi_write32(priv->flags, ®s->ipcr1, + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | len); + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, + FLEXSPI_IPTXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPCMDDONE_MASK); + + return 0; +} + +static int fspi_nand_op_read(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op) +{ + struct fsl_fspi_regs *regs = priv->regs; + int i, size; + u32 to_or_from; + u8 *rxbuf; + u8 panel; + + to_or_from = op->addr.val + priv->cur_amba_base; + rxbuf = op->data.buf.in; + panel = op->addr.val >> FSPI_NAND_CAS; + + /* Update LUT to select plane */ + fspi_nand_set_oprnd1(priv, seqid, panel); + + debug("%s seqid=%u, addr_val = 0x%llx, addr_nbytes = %u, data_buf_in = 0x%lx, data_nbytes = 0x%x\n", + __func__, seqid, op->addr.val, op->addr.nbytes, + (ulong)rxbuf, op->data.nbytes); + + /* invalid the RXFIFO */ + fspi_write32(priv->flags, ®s->iprxfcr, FLEXSPI_IPRXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, to_or_from); + + fspi_write32(priv->flags, ®s->ipcr1, + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | + op->data.nbytes); + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + size = op->data.nbytes / 8; + for (i = 0; i < size; ++i) { + /* Wait for RXFIFO available*/ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPRXWA_MASK)) + ; + + memcpy(rxbuf, ®s->rfdr, 8); + rxbuf += 8; + + /* move the FIFO pointer */ + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPRXWA_MASK); + } + + size = op->data.nbytes % 8; + + if (size) { + /* Wait for data filled*/ + while (!(fspi_read32(priv->flags, ®s->iprxfsts) + & FLEXSPI_IPRXFSTS_FILL_MASK)) + ; + memcpy(rxbuf, ®s->rfdr, size); + } + + /* invalid the RXFIFO */ + fspi_write32(priv->flags, ®s->iprxfcr, + FLEXSPI_IPRXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPCMDDONE_MASK); + + return 0; +} + +static int fspi_nand_op_write(struct fsl_fspi_priv *priv, u32 seqid, const struct spi_mem_op *op) +{ + struct fsl_fspi_regs *regs = priv->regs; + int i, size; + u8 *txbuf; + u8 panel; + u32 to_or_from = op->addr.val + priv->cur_amba_base; + + txbuf = (u8 *)(op->data.buf.out); + panel = op->addr.val >> FSPI_NAND_CAS; + + /* Update LUT to select plane */ + fspi_nand_set_oprnd1(priv, seqid, panel); + + debug("%s seqid=%u, addr_val = 0x%llx, addr_nbytes = %u, data_buf_in = 0x%lx, data_nbytes = 0x%x\n", + __func__, seqid, op->addr.val, op->addr.nbytes, + (ulong)txbuf, op->data.nbytes); + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, FLEXSPI_IPTXFCR_CLR_MASK); + + fspi_write32(priv->flags, ®s->ipcr0, to_or_from); + + size = op->data.nbytes / 8; + for (i = 0; i < size; i++) { + /* Wait for TXFIFO empty*/ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPTXWE_MASK)) + ; + + memcpy(®s->tfdr, txbuf, 8); + txbuf += 8; + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPTXWE_MASK); + } + + size = op->data.nbytes % 8; + if (size) { + /* Wait for TXFIFO empty*/ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPTXWE_MASK)) + ; + + memcpy(®s->tfdr, txbuf, size); + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPTXWE_MASK); + } + + fspi_write32(priv->flags, ®s->ipcr1, + (seqid << FLEXSPI_IPCR1_SEQID_SHIFT) | op->data.nbytes); + + /* Trigger the command */ + fspi_write32(priv->flags, ®s->ipcmd, 1); + + /* Wait for command done */ + while (!(fspi_read32(priv->flags, ®s->intr) + & FLEXSPI_INTR_IPCMDDONE_MASK)) + ; + + /* invalid the TXFIFO first */ + fspi_write32(priv->flags, ®s->iptxfcr, + FLEXSPI_IPTXFCR_CLR_MASK); + fspi_write32(priv->flags, ®s->intr, + FLEXSPI_INTR_IPCMDDONE_MASK); + + return 0; +} + +void fspi_nand_module_disable(struct fsl_fspi_priv *priv, u8 disable) +{ + u32 mcr_val; + + mcr_val = fspi_read32(priv->flags, &priv->regs->mcr0); + if (disable) + mcr_val |= FLEXSPI_MCR0_MDIS_MASK; + else + mcr_val &= ~FLEXSPI_MCR0_MDIS_MASK; + fspi_write32(priv->flags, &priv->regs->mcr0, mcr_val); +} + +__weak void init_clk_fspi(int index) +{ +} + +static int fsl_fspi_nand_child_pre_probe(struct udevice *dev) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + + slave->max_write_size = TX_BUFFER_SIZE; + slave->max_read_size = RX_BUFFER_SIZE; + + return 0; +} + +static int fsl_fspi_nand_probe(struct udevice *bus) +{ + u32 total_size; + struct fsl_fspi_platdata *plat = dev_get_platdata(bus); + struct fsl_fspi_priv *priv = dev_get_priv(bus); + struct dm_spi_bus *dm_spi_bus; + u32 val; + + if (CONFIG_IS_ENABLED(CLK)) { + /* Assigned clock already set clock */ + struct clk fspi_clk; + int ret; + + ret = clk_get_by_name(bus, "fspi", &fspi_clk); + if (ret < 0) { + printf("Can't get fspi clk: %d\n", ret); + return ret; + } + + ret = clk_enable(&fspi_clk); + if (ret < 0) { + printf("Can't enable fspi clk: %d\n", ret); + return ret; + } + } else { + init_clk_fspi(bus->seq); + } + dm_spi_bus = bus->uclass_priv; + + dm_spi_bus->max_hz = plat->speed_hz; + + priv->regs = (struct fsl_fspi_regs *)(uintptr_t)plat->reg_base; + priv->flags = plat->flags; + + priv->speed_hz = plat->speed_hz; + priv->amba_base[0] = plat->amba_base; + priv->amba_total_size = plat->amba_total_size; + priv->flash_num = plat->flash_num; + priv->num_chipselect = plat->num_chipselect; + + fspi_write32(priv->flags, &priv->regs->mcr0, + FLEXSPI_MCR0_SWRST_MASK); + do { + udelay(1); + } while (0x1 & fspi_read32(priv->flags, &priv->regs->mcr0)); + + /* Disable the module */ + fspi_nand_module_disable(priv, 1); + + /* Enable the module and set to proper value*/ + fspi_write32(priv->flags, &priv->regs->mcr0, + 0xFFFF0000); + + /* Reset the DLL register to default value */ + fspi_write32(priv->flags, &priv->regs->dllacr, 0x0100); + fspi_write32(priv->flags, &priv->regs->dllbcr, 0x0100); + + /* Flash Size in KByte */ + total_size = FSL_FSPI_NAND_SIZE * FSL_FSPI_NAND_NUM >> 10; + + /* + * Any read access to non-implemented addresses will provide + * undefined results. + * + * In case single die flash devices, TOP_ADDR_MEMA2 and + * TOP_ADDR_MEMB2 should be initialized/programmed to + * TOP_ADDR_MEMA1 and TOP_ADDR_MEMB1 respectively - in effect, + * setting the size of these devices to 0. This would ensure + * that the complete memory map is assigned to only one flash device. + */ + + fspi_write32(priv->flags, &priv->regs->flsha1cr0, + total_size); + fspi_write32(priv->flags, &priv->regs->flsha2cr0, + 0); + fspi_write32(priv->flags, &priv->regs->flshb1cr0, + 0); + fspi_write32(priv->flags, &priv->regs->flshb2cr0, + 0); + + val = fspi_read32(priv->flags, &priv->regs->flsha1cr1); + val &= ~FLEXSPI_FLSHXCR1_CAS_MASK; + val |= FSPI_NAND_CAS << FLEXSPI_FLSHXCR1_CAS_SHIFT; + fspi_write32(priv->flags, &priv->regs->flsha1cr1, + val); + fspi_nand_module_disable(priv, 0); + + fspi_nand_set_lut(priv); + + return 0; +} + +static int fsl_fspi_nand_ofdata_to_platdata(struct udevice *bus) +{ + struct fdt_resource res_regs, res_mem; + struct fsl_fspi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = ofnode_to_offset(bus->node); + int ret, flash_num = 0, subnode; + + if (fdtdec_get_bool(blob, node, "big-endian")) + plat->flags |= FSPI_FLAG_REGMAP_ENDIAN_BIG; + + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", + "FlexSPI", &res_regs); + if (ret) { + debug("Error: can't get regs base addresses(ret = %d)!\n", ret); + return -ENOMEM; + } + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", + "FlexSPI-memory", &res_mem); + if (ret) { + debug("Error: can't get AMBA base addresses(ret = %d)!\n", ret); + return -ENOMEM; + } + + /* Count flash numbers */ + fdt_for_each_subnode(subnode, blob, node) + ++flash_num; + + if (flash_num == 0) { + debug("Error: Missing flashes!\n"); + return -ENODEV; + } + + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + FSL_FSPI_DEFAULT_SCK_FREQ); + plat->num_chipselect = fdtdec_get_int(blob, node, "num-cs", + FSL_FSPI_MAX_CHIPSELECT_NUM); + + plat->reg_base = res_regs.start; + plat->amba_base = 0; + plat->amba_total_size = res_mem.end - res_mem.start + 1; + plat->flash_num = flash_num; + + debug("%s: regs=<0x%x> <0x%x, 0x%x>, max-frequency=%d, endianness=%s\n", + __func__, + plat->reg_base, + plat->amba_base, + plat->amba_total_size, + plat->speed_hz, + plat->flags & FSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le" + ); + + return 0; +} + +static int fsl_fspi_nand_claim_bus(struct udevice *dev) +{ + struct fsl_fspi_priv *priv; + struct udevice *bus; + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + + bus = dev->parent; + priv = dev_get_priv(bus); + + priv->cur_amba_base = + priv->amba_base[0] + FSL_FSPI_NAND_SIZE * slave_plat->cs; + + return 0; +} + +static int fsl_fspi_nand_release_bus(struct udevice *dev) +{ + return 0; +} + +static int fsl_fspi_nand_set_speed(struct udevice *bus, uint speed) +{ + /* Nothing to do */ + return 0; +} + +static int fsl_fspi_nand_set_mode(struct udevice *bus, uint mode) +{ + /* Nothing to do */ + return 0; +} + +struct fspi_cmd_func_pair fspi_supported_cmds[SEQID_END] = { + {SPINAND_CMD_RESET, &fspi_nand_op_cmd}, + {SPINAND_CMD_WREN, &fspi_nand_op_cmd}, + {SPINAND_CMD_READID, &fspi_nand_op_read_reg}, + {SPINAND_CMD_SET_FEATURE, &fspi_nand_op_write_reg}, + {SPINAND_CMD_GET_FEATURE, &fspi_nand_op_read_reg}, + {SPINAND_CMD_BLK_ERASE, &fspi_nand_op_cmd}, + {SPINAND_CMD_PAGE_READ, &fspi_nand_op_cmd}, + {SPINAND_CMD_PAGE_READ_FROM_CACHE_NORMAL, &fspi_nand_op_read}, + {SPINAND_CMD_PAGE_READ_FROM_CACHE_FAST, &fspi_nand_op_read}, + {SPINAND_CMD_PAGE_READ_FROM_CACHE_X2, &fspi_nand_op_read}, + {SPINAND_CMD_PAGE_READ_FROM_CACHE_X4, &fspi_nand_op_read}, + {SPINAND_CMD_PAGE_READ_FROM_CACHE_DUALIO, &fspi_nand_op_read}, + {SPINAND_CMD_PAGE_READ_FROM_CACHE_QUADIO, &fspi_nand_op_read}, + {SPINAND_CMD_PROG_EXEC, &fspi_nand_op_cmd}, + {SPINAND_CMD_PROG_LOAD, &fspi_nand_op_write}, + {SPINAND_CMD_PROG_LOAD_RANDOM, &fspi_nand_op_write}, + {SPINAND_CMD_PROG_LOAD_X4, &fspi_nand_op_write}, + {SPINAND_CMD_PROG_LOAD_RANDOM_X4, &fspi_nand_op_write}, +}; + +static int fsl_fspi_nand_get_lut_index(const struct spi_mem_op *op) +{ + int i; + + for (i = 0; i < SEQID_END; i++) { + if (fspi_supported_cmds[i].cmd == op->cmd.opcode) + break; + } + + return i; +} + +bool fsl_fspi_nand_supports_op(struct spi_slave *slave, const struct spi_mem_op *op) +{ + int i; + + if (!op || !slave) + return false; + + i = fsl_fspi_nand_get_lut_index(op); + if (i == SEQID_END) { + printf("fsl_fspi_nand: fail to find cmd %u from lut\n", op->cmd.opcode); + return false; + } + + debug("fsl_fspi_nand: find seqid %d for cmd %u from lut\n", i, op->cmd.opcode); + + return true; +} + +int fsl_fspi_nand_exec_op(struct spi_slave *slave, const struct spi_mem_op *op) +{ + int i; + struct fsl_fspi_priv *priv; + struct udevice *bus; + + bus = slave->dev->parent; + priv = dev_get_priv(bus); + + if (!op || !slave) + return -EINVAL; + + i = fsl_fspi_nand_get_lut_index(op); + if (i == SEQID_END) { + printf("fsl_fspi_nand: fail to find cmd %u from lut\n", op->cmd.opcode); + return -EPERM; + } + + return fspi_supported_cmds[i].fspi_op_func(priv, i, op); +} + +int fsl_fspi_nand_adjust_op_size(struct spi_slave *slave, struct spi_mem_op *op) +{ + switch (op->cmd.opcode) { + case SPINAND_CMD_PAGE_READ_FROM_CACHE_NORMAL: + case SPINAND_CMD_PAGE_READ_FROM_CACHE_FAST: + case SPINAND_CMD_PAGE_READ_FROM_CACHE_X2: + case SPINAND_CMD_PAGE_READ_FROM_CACHE_X4: + case SPINAND_CMD_PAGE_READ_FROM_CACHE_DUALIO: + case SPINAND_CMD_PAGE_READ_FROM_CACHE_QUADIO: + if (op->data.nbytes > RX_BUFFER_SIZE) + op->data.nbytes = RX_BUFFER_SIZE; + break; + case SPINAND_CMD_PROG_LOAD: + case SPINAND_CMD_PROG_LOAD_RANDOM: + case SPINAND_CMD_PROG_LOAD_X4: + case SPINAND_CMD_PROG_LOAD_RANDOM_X4: + if (op->data.nbytes > TX_BUFFER_SIZE) + op->data.nbytes = TX_BUFFER_SIZE; + break; + } + + return 0; +} + +static struct spi_controller_mem_ops fspi_nand_mem_ops = { + .adjust_op_size = fsl_fspi_nand_adjust_op_size, + .supports_op = fsl_fspi_nand_supports_op, + .exec_op = fsl_fspi_nand_exec_op, +}; + +static const struct dm_spi_ops fsl_fspi_nand_ops = { + .claim_bus = fsl_fspi_nand_claim_bus, + .release_bus = fsl_fspi_nand_release_bus, + .set_speed = fsl_fspi_nand_set_speed, + .set_mode = fsl_fspi_nand_set_mode, + .mem_ops = &fspi_nand_mem_ops, +}; + +static const struct udevice_id fsl_fspi_nand_ids[] = { + { .compatible = "fsl,imx8-fspi-nand" }, + { } +}; + +U_BOOT_DRIVER(fsl_fspi_nand) = { + .name = "fsl_fspi_nand", + .id = UCLASS_SPI, + .of_match = fsl_fspi_nand_ids, + .ops = &fsl_fspi_nand_ops, + .of_to_plat = fsl_fspi_nand_ofdata_to_platdata, + .plat_auto = sizeof(struct fsl_fspi_platdata), + .priv_auto = sizeof(struct fsl_fspi_priv), + .probe = fsl_fspi_nand_probe, + .child_pre_probe = fsl_fspi_nand_child_pre_probe, +}; diff --git a/drivers/spi/fsl_lpspi.c b/drivers/spi/fsl_lpspi.c new file mode 100644 index 00000000000..7870b2702a3 --- /dev/null +++ b/drivers/spi/fsl_lpspi.c @@ -0,0 +1,530 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * LPSPI controller driver. + * + * Copyright 2020 NXP Semiconductor, Inc. + * Author: Clark Wang (xiaoning.wang@nxp.com) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "fsl_lpspi.h" + +DECLARE_GLOBAL_DATA_PTR; + +__weak int enable_lpspi_clk(unsigned char enable, unsigned int spi_num) +{ + return 0; +} + +__weak u32 imx_get_spiclk(u32 spi_num) +{ + return 0; +} + +#define reg_read readl +#define reg_write(a, v) writel(v, a) + +#define MAX_CS_COUNT 4 +#define MAX_SPI_BYTES 16 + +struct fsl_lpspi_slave { + struct spi_slave slave; + unsigned long base; + unsigned int seq; + unsigned int prescale; + unsigned int max_hz; + unsigned int speed; + unsigned int mode; + unsigned int wordlen; + unsigned int fifolen; + struct gpio_desc ss; + struct gpio_desc cs_gpios[MAX_CS_COUNT]; + struct udevice *dev; + struct clk per_clk; + struct clk ipg_clk; + + /* SPI FiFo accessor */ + void *rx_buf; + const void *tx_buf; + void (*rx_fifo)(struct fsl_lpspi_slave *); + void (*tx_fifo)(struct fsl_lpspi_slave *); +}; + +static inline struct fsl_lpspi_slave *to_fsl_lpspi_slave(struct spi_slave *slave) +{ + return container_of(slave, struct fsl_lpspi_slave, slave); +} + +#define BUILD_SPI_FIFO_RW(__name, __type) \ +static void fsl_lpspi_rx_##__name(struct fsl_lpspi_slave *lpspi) \ +{ \ + struct LPSPI_Type *regs = (struct LPSPI_Type *)lpspi->base; \ + unsigned int val = reg_read(®s->RDR); \ + \ + if (lpspi->rx_buf) { \ + *(__type *)lpspi->rx_buf = val; \ + lpspi->rx_buf += sizeof(__type); \ + } \ +} \ + \ +static void fsl_lpspi_tx_##__name(struct fsl_lpspi_slave *lpspi) \ +{ \ + __type val = 0; \ + struct LPSPI_Type *regs = (struct LPSPI_Type *)lpspi->base; \ + \ + if (lpspi->tx_buf) { \ + val = *(__type *)lpspi->tx_buf; \ + lpspi->tx_buf += sizeof(__type); \ + } \ + \ + reg_write(®s->TDR, val); \ +} +BUILD_SPI_FIFO_RW(byte, u8); +BUILD_SPI_FIFO_RW(word, u16); +BUILD_SPI_FIFO_RW(dword, u32); + +static int fsl_lpspi_set_word_size(struct fsl_lpspi_slave *lpspi, + unsigned int wordlen) +{ + lpspi->wordlen = wordlen; + + switch (wordlen) { + case 8: + lpspi->rx_fifo = fsl_lpspi_rx_byte; + lpspi->tx_fifo = fsl_lpspi_tx_byte; + break; + case 16: + lpspi->rx_fifo = fsl_lpspi_rx_word; + lpspi->tx_fifo = fsl_lpspi_tx_word; + break; + case 32: + lpspi->rx_fifo = fsl_lpspi_rx_dword; + lpspi->tx_fifo = fsl_lpspi_tx_dword; + break; + default: + dev_err(lpspi->dev, "fsl_lpspi: unsupported wordlen: %d\n", + wordlen); + return -EINVAL; + } + + return 0; +} + +static void fsl_lpspi_cs_activate(struct fsl_lpspi_slave *lpspi) +{ + struct udevice *dev = lpspi->dev; + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + + u32 cs = slave_plat->cs; + + if (!dm_gpio_is_valid(&lpspi->cs_gpios[cs])) + return; + + dm_gpio_set_value(&lpspi->cs_gpios[cs], 1); +} + +static void fsl_lpspi_cs_deactivate(struct fsl_lpspi_slave *lpspi) +{ + struct udevice *dev = lpspi->dev; + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + + u32 cs = slave_plat->cs; + + if (!dm_gpio_is_valid(&lpspi->cs_gpios[cs])) + return; + + dm_gpio_set_value(&lpspi->cs_gpios[cs], 0); +} + +static int clkdivs[] = {1, 2, 4, 8, 16, 32, 64, 128}; + +static s32 spi_cfg_lpspi(struct fsl_lpspi_slave *lpspi, unsigned int cs) +{ + s32 reg_config; + unsigned int perclk_rate, scldiv; + u8 prescale; + struct LPSPI_Type *regs = (struct LPSPI_Type *)lpspi->base; + unsigned int speed = lpspi->speed; + + /* Disable all interrupt */ + reg_write(®s->IER, 0); + /* W1C for all flags in SR */ + reg_write(®s->SR, (0x3F << 8)); + /* Clear FIFO and disable module */ + reg_write(®s->CR, (LPSPI_CR_RTF_MASK | LPSPI_CR_RRF_MASK)); + + lpspi->fifolen = 1 << (reg_read(®s->PARAM) & LPSPI_PARAM_TXFIFO_MASK); + + reg_config = reg_read(®s->CFGR1); + reg_config = (reg_config & (~LPSPI_CFGR1_MASTER_MASK)) | + LPSPI_CFGR1_MASTER(1); + if (lpspi->mode & SPI_CS_HIGH) + reg_config = reg_config | + (1UL << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)cs)); + else + reg_config = reg_config & + ~(1UL << (LPSPI_CFGR1_PCSPOL_SHIFT + (uint32_t)cs)); + reg_config = (reg_config & ~(LPSPI_CFGR1_OUTCFG_MASK | + LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK)) | + LPSPI_CFGR1_OUTCFG(0) | LPSPI_CFGR1_PINCFG(0) | + LPSPI_CFGR1_NOSTALL(0); + reg_write(®s->CFGR1, reg_config); + + if (IS_ENABLED(CONFIG_CLK)) { + perclk_rate = clk_get_rate(&lpspi->per_clk); + if (perclk_rate <= 0) { + dev_err(lpspi->dev, "Failed to get spi clk: %d\n", + perclk_rate); + return perclk_rate; + } + } else { + perclk_rate = imx_get_spiclk(lpspi->seq); + if (!perclk_rate) + return -EPERM; + } + + if (speed > perclk_rate / 2) { + dev_err(lpspi->dev, + "per-clk should be at least two times of transfer speed, speed=%d", speed); + return -EINVAL; + } + + for (prescale = 0; prescale < 8; prescale++) { + scldiv = perclk_rate / + (clkdivs[prescale] * speed) - 2; + if (scldiv < 256) { + lpspi->prescale = prescale; + break; + } + } + + if (prescale == 8 && scldiv >= 256) + return -EINVAL; + + reg_write(®s->CCR, (scldiv | (scldiv << 8) | ((scldiv >> 1) << 16))); + + dev_dbg(lpspi->dev, "perclk=%d, speed=%d, prescale=%d, scldiv=%d\n", + perclk_rate, speed, prescale, scldiv); + + return 0; +} + +int spi_xfer_single(struct fsl_lpspi_slave *lpspi, unsigned int bitlen, + unsigned long flags) +{ + int nbytes = DIV_ROUND_UP(bitlen, 8); + u32 ts; + struct LPSPI_Type *regs = (struct LPSPI_Type *)lpspi->base; + int status; + + dev_dbg(lpspi->dev, "%s: bitlen %d tx_buf 0x%lx rx_buf 0x%lx\n", + __func__, bitlen, (ulong)lpspi->tx_buf, (ulong)lpspi->rx_buf); + + while (nbytes > 0) { + lpspi->tx_fifo(lpspi); + nbytes -= (lpspi->wordlen / 8); + } + + reg_write(®s->TCR, ((lpspi->mode & 0x3) << LPSPI_TCR_CPHA_SHIFT | + LPSPI_TCR_FRAMESZ(lpspi->wordlen - 1) | + LPSPI_TCR_PRESCALE(lpspi->prescale) | + LPSPI_TCR_PCS(1) | LPSPI_TCR_CONT(1) | LPSPI_TCR_CONTC(0))); + + ts = get_timer(0); + status = reg_read(®s->SR); + /* Wait until the TC (Transfer completed) bit is set */ + while ((status & LPSPI_SR_TCF_MASK) != 0) { + if (get_timer(ts) > (CONFIG_SYS_HZ / 2)) { + dev_err(lpspi->dev, "lpspi_xfer_single: TX Timeout!\n"); + return -ETIMEDOUT; + } + status = reg_read(®s->RSR); + } + nbytes = DIV_ROUND_UP(bitlen, 8); + ts = get_timer(0); + while (nbytes > 0) { + if (get_timer(ts) > (CONFIG_SYS_HZ / 2)) { + dev_err(lpspi->dev, "lpspi_xfer_single: RX Timeout!\n"); + return -ETIMEDOUT; + } + if ((reg_read(®s->FSR) & LPSPI_FSR_RXCOUNT_MASK) > 0) { + lpspi->rx_fifo(lpspi); + nbytes -= (lpspi->wordlen / 8); + } + } + + return nbytes; +} + +static int fsl_lpspi_check_trans_len(unsigned int len, unsigned int wordlen) +{ + int ret = 0; + + switch (wordlen) { + case 32: + if (len % 4) + ret = -EINVAL; + break; + case 16: + if (len % 2) + ret = -EINVAL; + break; + case 8: + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static int fsl_lpspi_xfer_internal(struct fsl_lpspi_slave *lpspi, + unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + int n_bytes = DIV_ROUND_UP(bitlen, 8); + int n_bits; + int ret = 0; + u32 blk_size; + struct LPSPI_Type *regs; + u8 watermark = 0; + struct udevice *dev; + struct dm_spi_slave_plat *slave_plat; + + if (!lpspi) + return -EINVAL; + + regs = (struct LPSPI_Type *)lpspi->base; + dev = lpspi->dev; + slave_plat = dev_get_parent_plat(dev); + + ret = fsl_lpspi_check_trans_len(n_bytes, lpspi->wordlen); + if (ret) + { + dev_err(lpspi->dev, "fsl_lpspi: wordlen(%d) and transfer len(%d) mismatch!\n", + DIV_ROUND_UP(lpspi->wordlen, 8), n_bytes); + return ret; + } + + if (dout) + lpspi->tx_buf = dout; + if (din) + lpspi->rx_buf = din; + + if (n_bytes <= lpspi->fifolen) + watermark = n_bytes; + else + watermark = lpspi->fifolen; + reg_write(®s->FCR, watermark >> 1 | (watermark >> 1) << 16); + + reg_write(®s->TCR, ((lpspi->mode & 0x3) << LPSPI_TCR_CPHA_SHIFT | + LPSPI_TCR_FRAMESZ(lpspi->wordlen - 1) | + LPSPI_TCR_PRESCALE(lpspi->prescale) | + LPSPI_TCR_PCS(slave_plat->cs) | LPSPI_TCR_CONT(1) | + LPSPI_TCR_CONTC(0))); + + reg_write(®s->CR, LPSPI_CR_MEN_MASK); + + if (flags & SPI_XFER_BEGIN) + fsl_lpspi_cs_activate(lpspi); + + while (n_bytes > 0) { + if (n_bytes < lpspi->fifolen * lpspi->wordlen / 8) + blk_size = n_bytes; + else + blk_size = lpspi->fifolen * lpspi->wordlen / 8; + + n_bits = blk_size * 8; + + ret = spi_xfer_single(lpspi, n_bits, 0); + if (ret) + break; + + n_bytes -= blk_size; + } + + /* Disable all interrupt */ + reg_write(®s->IER, 0); + /* W1C for all flags in SR */ + reg_write(®s->SR, (0x3F << 8)); + /* Clear FIFO and disable module */ + reg_write(®s->CR, (LPSPI_CR_RTF_MASK | LPSPI_CR_RRF_MASK)); + + if (flags & SPI_XFER_END || ret) + fsl_lpspi_cs_deactivate(lpspi); + + lpspi->tx_buf = NULL; + lpspi->rx_buf = NULL; + + return ret; +} + +static int fsl_lpspi_claim_bus_internal(struct fsl_lpspi_slave *lpspi, int cs) +{ + int ret; + + ret = spi_cfg_lpspi(lpspi, cs); + if (ret) { + dev_err(lpspi->dev, "fsl_lpspi: cannot setup SPI controller\n"); + return ret; + } + + return 0; +} + +static int fsl_lpspi_probe(struct udevice *bus) +{ + struct fsl_lpspi_slave *lpspi = dev_get_plat(bus); + int node = dev_of_offset(bus); + const void *blob = gd->fdt_blob; + int ret; + int i; + + ret = gpio_request_list_by_name(bus, "cs-gpios", lpspi->cs_gpios, + ARRAY_SIZE(lpspi->cs_gpios), 0); + if (ret < 0) { + dev_err(bus, "Can't get %s gpios! Error: %d", bus->name, ret); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(lpspi->cs_gpios); i++) { + if (!dm_gpio_is_valid(&lpspi->cs_gpios[i])) + continue; + + ret = dm_gpio_set_dir_flags(&lpspi->cs_gpios[i], + GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); + if (ret) { + dev_err(bus, "Setting cs %d error\n", i); + return ret; + } + } + + lpspi->base = devfdt_get_addr(bus); + if (lpspi->base == FDT_ADDR_T_NONE) + return -ENODEV; + + lpspi->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + 500000); + + if (IS_ENABLED(CONFIG_CLK)) { + //Enable clks + ret = clk_get_by_name(bus, "per", &lpspi->per_clk); + if (ret) { + dev_err(bus, "Failed to get per clk\n"); + return ret; + } + ret = clk_enable(&lpspi->per_clk); + if (ret) { + dev_err(bus, "Failed to enable per clk, ret=%d\n", ret); + return ret; + } + + ret = clk_get_by_name(bus, "ipg", &lpspi->ipg_clk); + if (ret) { + dev_err(bus, "Failed to get ipg clk\n"); + return ret; + } + ret = clk_enable(&lpspi->ipg_clk); + if (ret) { + dev_err(bus, "Failed to enable ipg clk\n"); + return ret; + } + } else { + lpspi->seq = dev_seq(bus); + /* To i.MX7ULP, only spi2/3 can be handled by A7 core */ + ret = enable_lpspi_clk(1, lpspi->seq); + if (ret < 0) + return ret; + } + + return 0; +} + +static int fsl_lpspi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct fsl_lpspi_slave *lpspi = dev_get_plat(dev->parent); + + return fsl_lpspi_xfer_internal(lpspi, bitlen, dout, din, flags); +} + +static int fsl_lpspi_claim_bus(struct udevice *dev) +{ + struct fsl_lpspi_slave *lpspi = dev_get_plat(dev->parent); + struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); + + lpspi->dev = dev; + + /* set default configurations */ + lpspi->mode = 0; + lpspi->speed = lpspi->max_hz; + lpspi->wordlen = 8; + fsl_lpspi_set_word_size(lpspi, lpspi->wordlen); + + return fsl_lpspi_claim_bus_internal(lpspi, slave_plat->cs); +} + +static int fsl_lpspi_release_bus(struct udevice *dev) +{ + return 0; +} + +static int fsl_lpspi_set_speed(struct udevice *bus, uint speed) +{ + struct fsl_lpspi_slave *lpspi = dev_get_plat(bus); + + lpspi->speed = speed; + + return 0; +} + +static int fsl_lpspi_set_mode(struct udevice *bus, uint mode) +{ + struct fsl_lpspi_slave *lpspi = dev_get_plat(bus); + + lpspi->mode = mode; + + return 0; +} + +static int fsl_lpspi_set_wordlen(struct udevice *bus, unsigned int wordlen) +{ + struct fsl_lpspi_slave *lpspi = dev_get_plat(bus); + + return fsl_lpspi_set_word_size(lpspi, wordlen); +} + +static const struct dm_spi_ops fsl_lpspi_ops = { + .claim_bus = fsl_lpspi_claim_bus, + .release_bus = fsl_lpspi_release_bus, + .xfer = fsl_lpspi_xfer, + .set_speed = fsl_lpspi_set_speed, + .set_mode = fsl_lpspi_set_mode, + .set_wordlen = fsl_lpspi_set_wordlen, +}; + +static const struct udevice_id fsl_lpspi_ids[] = { + { .compatible = "fsl,imx7ulp-spi" }, + { } +}; + +U_BOOT_DRIVER(fsl_lpspi) = { + .name = "fsl_lpspi", + .id = UCLASS_SPI, + .of_match = fsl_lpspi_ids, + .ops = &fsl_lpspi_ops, + .plat_auto = sizeof(struct fsl_lpspi_slave), + .probe = fsl_lpspi_probe, +}; diff --git a/drivers/spi/fsl_lpspi.h b/drivers/spi/fsl_lpspi.h new file mode 100644 index 00000000000..998a9f6774e --- /dev/null +++ b/drivers/spi/fsl_lpspi.h @@ -0,0 +1,531 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Register definitions for Freescale QSPI + * + * Copyright 2020 NXP Semiconductor, Inc. + * Author: Clark Wang (xiaoning.wang@nxp.com) + */ +#ifndef _FSL_LPSPI_H_ +#define _FSL_LPSPI_H_ + +/* ---------------------------------------------------------------------------- + - LPSPI Peripheral Access Layer + * ---------------------------------------------------------------------------- */ + +/* + * LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer + */ + +/** LPSPI - Register Layout Typedef */ +struct LPSPI_Type +{ + u32 VERID; /**< Version ID Register, offset: 0x0 */ + u32 PARAM; /**< Parameter Register, offset: 0x4 */ + u8 RESERVED_0[8]; + u32 CR; /**< Control Register, offset: 0x10 */ + u32 SR; /**< Status Register, offset: 0x14 */ + u32 IER; /**< Interrupt Enable Register, offset: 0x18 */ + u32 DER; /**< DMA Enable Register, offset: 0x1C */ + u32 CFGR0; /**< Configuration Register 0, offset: 0x20 */ + u32 CFGR1; /**< Configuration Register 1, offset: 0x24 */ + u8 RESERVED_1[8]; + u32 DMR0; /**< Data Match Register 0, offset: 0x30 */ + u32 DMR1; /**< Data Match Register 1, offset: 0x34 */ + u8 RESERVED_2[8]; + u32 CCR; /**< Clock Configuration Register, offset: 0x40 */ + u8 RESERVED_3[20]; + u32 FCR; /**< FIFO Control Register, offset: 0x58 */ + u32 FSR; /**< FIFO Status Register, offset: 0x5C */ + u32 TCR; /**< Transmit Command Register, offset: 0x60 */ + u32 TDR; /**< Transmit Data Register, offset: 0x64 */ + u8 RESERVED_4[8]; + u32 RSR; /**< Receive Status Register, offset: 0x70 */ + u32 RDR; /**< Receive Data Register, offset: 0x74 */ +}; + +/* ---------------------------------------------------------------------------- + - LPSPI Register Masks + * ---------------------------------------------------------------------------- */ + +/* + * LPSPI_Register_Masks LPSPI Register Masks + */ + +/* VERID - Version ID Register */ +#define LPSPI_VERID_FEATURE_MASK (0xFFFFU) +#define LPSPI_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Module Identification Number + * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. + */ +#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) +#define LPSPI_VERID_MINOR_MASK (0xFF0000U) +#define LPSPI_VERID_MINOR_SHIFT (16U) +#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) +#define LPSPI_VERID_MAJOR_MASK (0xFF000000U) +#define LPSPI_VERID_MAJOR_SHIFT (24U) +#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) + +/* PARAM - Parameter Register */ +#define LPSPI_PARAM_TXFIFO_MASK (0xFFU) +#define LPSPI_PARAM_TXFIFO_SHIFT (0U) +#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) +#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) +#define LPSPI_PARAM_RXFIFO_SHIFT (8U) +#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) +#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) +#define LPSPI_PARAM_PCSNUM_SHIFT (16U) +#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) + +/* CR - Control Register */ +#define LPSPI_CR_MEN_MASK (0x1U) +#define LPSPI_CR_MEN_SHIFT (0U) +/*! MEN - Module Enable + * 0b0..Module is disabled + * 0b1..Module is enabled + */ +#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) +#define LPSPI_CR_RST_MASK (0x2U) +#define LPSPI_CR_RST_SHIFT (1U) +/*! RST - Software Reset + * 0b0..Module is not reset + * 0b1..Module is reset + */ +#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) +#define LPSPI_CR_DOZEN_MASK (0x4U) +#define LPSPI_CR_DOZEN_SHIFT (2U) +/*! DOZEN - Doze Mode Enable + * 0b0..LPSPI module is enabled in Doze mode + * 0b1..LPSPI module is disabled in Doze mode + */ +#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) +#define LPSPI_CR_DBGEN_MASK (0x8U) +#define LPSPI_CR_DBGEN_SHIFT (3U) +/*! DBGEN - Debug Enable + * 0b0..LPSPI module is disabled in debug mode + * 0b1..LPSPI module is enabled in debug mode + */ +#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) +#define LPSPI_CR_RTF_MASK (0x100U) +#define LPSPI_CR_RTF_SHIFT (8U) +/*! RTF - Reset Transmit FIFO + * 0b0..No effect + * 0b1..Transmit FIFO is reset + */ +#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) +#define LPSPI_CR_RRF_MASK (0x200U) +#define LPSPI_CR_RRF_SHIFT (9U) +/*! RRF - Reset Receive FIFO + * 0b0..No effect + * 0b1..Receive FIFO is reset + */ +#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) + +/* SR - Status Register */ +#define LPSPI_SR_TDF_MASK (0x1U) +#define LPSPI_SR_TDF_SHIFT (0U) +/*! TDF - Transmit Data Flag + * 0b0..Transmit data not requested + * 0b1..Transmit data is requested + */ +#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) +#define LPSPI_SR_RDF_MASK (0x2U) +#define LPSPI_SR_RDF_SHIFT (1U) +/*! RDF - Receive Data Flag + * 0b0..Receive Data is not ready + * 0b1..Receive data is ready + */ +#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) +#define LPSPI_SR_WCF_MASK (0x100U) +#define LPSPI_SR_WCF_SHIFT (8U) +/*! WCF - Word Complete Flag + * 0b0..Transfer of a received word has not yet completed + * 0b1..Transfer of a received word has completed + */ +#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) +#define LPSPI_SR_FCF_MASK (0x200U) +#define LPSPI_SR_FCF_SHIFT (9U) +/*! FCF - Frame Complete Flag + * 0b0..Frame transfer has not completed + * 0b1..Frame transfer has completed + */ +#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) +#define LPSPI_SR_TCF_MASK (0x400U) +#define LPSPI_SR_TCF_SHIFT (10U) +/*! TCF - Transfer Complete Flag + * 0b0..All transfers have not completed + * 0b1..All transfers have completed + */ +#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) +#define LPSPI_SR_TEF_MASK (0x800U) +#define LPSPI_SR_TEF_SHIFT (11U) +/*! TEF - Transmit Error Flag + * 0b0..Transmit FIFO underrun has not occurred + * 0b1..Transmit FIFO underrun has occurred + */ +#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) +#define LPSPI_SR_REF_MASK (0x1000U) +#define LPSPI_SR_REF_SHIFT (12U) +/*! REF - Receive Error Flag + * 0b0..Receive FIFO has not overflowed + * 0b1..Receive FIFO has overflowed + */ +#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) +#define LPSPI_SR_DMF_MASK (0x2000U) +#define LPSPI_SR_DMF_SHIFT (13U) +/*! DMF - Data Match Flag + * 0b0..Have not received matching data + * 0b1..Have received matching data + */ +#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) +#define LPSPI_SR_MBF_MASK (0x1000000U) +#define LPSPI_SR_MBF_SHIFT (24U) +/*! MBF - Module Busy Flag + * 0b0..LPSPI is idle + * 0b1..LPSPI is busy + */ +#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) + +/* IER - Interrupt Enable Register */ +#define LPSPI_IER_TDIE_MASK (0x1U) +#define LPSPI_IER_TDIE_SHIFT (0U) +/*! TDIE - Transmit Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) +#define LPSPI_IER_RDIE_MASK (0x2U) +#define LPSPI_IER_RDIE_SHIFT (1U) +/*! RDIE - Receive Data Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) +#define LPSPI_IER_WCIE_MASK (0x100U) +#define LPSPI_IER_WCIE_SHIFT (8U) +/*! WCIE - Word Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) +#define LPSPI_IER_FCIE_MASK (0x200U) +#define LPSPI_IER_FCIE_SHIFT (9U) +/*! FCIE - Frame Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) +#define LPSPI_IER_TCIE_MASK (0x400U) +#define LPSPI_IER_TCIE_SHIFT (10U) +/*! TCIE - Transfer Complete Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) +#define LPSPI_IER_TEIE_MASK (0x800U) +#define LPSPI_IER_TEIE_SHIFT (11U) +/*! TEIE - Transmit Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) +#define LPSPI_IER_REIE_MASK (0x1000U) +#define LPSPI_IER_REIE_SHIFT (12U) +/*! REIE - Receive Error Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) +#define LPSPI_IER_DMIE_MASK (0x2000U) +#define LPSPI_IER_DMIE_SHIFT (13U) +/*! DMIE - Data Match Interrupt Enable + * 0b0..Disabled + * 0b1..Enabled + */ +#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) + +/* DER - DMA Enable Register */ +#define LPSPI_DER_TDDE_MASK (0x1U) +#define LPSPI_DER_TDDE_SHIFT (0U) +/*! TDDE - Transmit Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) +#define LPSPI_DER_RDDE_MASK (0x2U) +#define LPSPI_DER_RDDE_SHIFT (1U) +/*! RDDE - Receive Data DMA Enable + * 0b0..DMA request is disabled + * 0b1..DMA request is enabled + */ +#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) + +/* CFGR0 - Configuration Register 0 */ +#define LPSPI_CFGR0_HREN_MASK (0x1U) +#define LPSPI_CFGR0_HREN_SHIFT (0U) +/*! HREN - Host Request Enable + * 0b0..Host request is disabled + * 0b1..Host request is enabled + */ +#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) +#define LPSPI_CFGR0_HRPOL_MASK (0x2U) +#define LPSPI_CFGR0_HRPOL_SHIFT (1U) +/*! HRPOL - Host Request Polarity + * 0b0..LPSPI_HREQ pin is active low + * 0b1..LPSPI_HREQ pin is active high + */ +#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) +#define LPSPI_CFGR0_HRSEL_MASK (0x4U) +#define LPSPI_CFGR0_HRSEL_SHIFT (2U) +/*! HRSEL - Host Request Select + * 0b0..Host request input is the LPSPI_HREQ pin + * 0b1..Host request input is the input trigger + */ +#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) +#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) +#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) +/*! CIRFIFO - Circular FIFO Enable + * 0b0..Circular FIFO is disabled + * 0b1..Circular FIFO is enabled + */ +#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) +#define LPSPI_CFGR0_RDMO_MASK (0x200U) +#define LPSPI_CFGR0_RDMO_SHIFT (9U) +/*! RDMO - Receive Data Match Only + * 0b0..Received data is stored in the receive FIFO as in normal operations + * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set + */ +#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) + +/* CFGR1 - Configuration Register 1 */ +#define LPSPI_CFGR1_MASTER_MASK (0x1U) +#define LPSPI_CFGR1_MASTER_SHIFT (0U) +/*! MASTER - Master Mode + * 0b0..Slave mode + * 0b1..Master mode + */ +#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) +#define LPSPI_CFGR1_SAMPLE_MASK (0x2U) +#define LPSPI_CFGR1_SAMPLE_SHIFT (1U) +/*! SAMPLE - Sample Point + * 0b0..Input data is sampled on SCK edge + * 0b1..Input data is sampled on delayed SCK edge + */ +#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) +#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) +#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) +/*! AUTOPCS - Automatic PCS + * 0b0..Automatic PCS generation is disabled + * 0b1..Automatic PCS generation is enabled + */ +#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) +#define LPSPI_CFGR1_NOSTALL_MASK (0x8U) +#define LPSPI_CFGR1_NOSTALL_SHIFT (3U) +/*! NOSTALL - No Stall + * 0b0..Transfers will stall when the transmit FIFO is empty or the receive FIFO is full + * 0b1..Transfers will not stall, allowing transmit FIFO underruns or receive FIFO overruns to occur + */ +#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) +#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) +#define LPSPI_CFGR1_PCSPOL_SHIFT (8U) +#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) +#define LPSPI_CFGR1_MATCFG_MASK (0x70000U) +#define LPSPI_CFGR1_MATCFG_SHIFT (16U) +/*! MATCFG - Match Configuration + * 0b000..Match is disabled + * 0b001..Reserved + * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) + * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) + * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st + * data word = MATCH0) * (2nd data word = MATCH1)] + * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., + * [(any data word = MATCH0) * (next data word = MATCH1)] + * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * + * MATCH1) = (MATCH0 * MATCH1)] 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND + * MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + */ +#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) +#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) +#define LPSPI_CFGR1_PINCFG_SHIFT (24U) +/*! PINCFG - Pin Configuration + * 0b00..SIN is used for input data and SOUT is used for output data + * 0b01..SIN is used for both input and output data, only half-duplex serial transfers are supported + * 0b10..SOUT is used for both input and output data, only half-duplex serial transfers are supported + * 0b11..SOUT is used for input data and SIN is used for output data + */ +#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) +#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) +#define LPSPI_CFGR1_OUTCFG_SHIFT (26U) +/*! OUTCFG - Output Configuration + * 0b0..Output data retains last value when chip select is negated + * 0b1..Output data is tristated when chip select is negated + */ +#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) +#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) +#define LPSPI_CFGR1_PCSCFG_SHIFT (27U) +/*! PCSCFG - Peripheral Chip Select Configuration + * 0b0..PCS[3:2] are configured for chip select function + * 0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2]) + */ +#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) + +/* DMR0 - Data Match Register 0 */ +#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) +#define LPSPI_DMR0_MATCH0_SHIFT (0U) +#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) + +/* DMR1 - Data Match Register 1 */ +#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) +#define LPSPI_DMR1_MATCH1_SHIFT (0U) +#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) + +/* CCR - Clock Configuration Register */ +#define LPSPI_CCR_SCKDIV_MASK (0xFFU) +#define LPSPI_CCR_SCKDIV_SHIFT (0U) +#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) +#define LPSPI_CCR_DBT_MASK (0xFF00U) +#define LPSPI_CCR_DBT_SHIFT (8U) +#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) +#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) +#define LPSPI_CCR_PCSSCK_SHIFT (16U) +#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) +#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) +#define LPSPI_CCR_SCKPCS_SHIFT (24U) +#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) + +/* FCR - FIFO Control Register */ +#define LPSPI_FCR_TXWATER_MASK (0x7U) +#define LPSPI_FCR_TXWATER_SHIFT (0U) +#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) +#define LPSPI_FCR_RXWATER_MASK (0x70000U) +#define LPSPI_FCR_RXWATER_SHIFT (16U) +#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) + +/* FSR - FIFO Status Register */ +#define LPSPI_FSR_TXCOUNT_MASK (0xFU) +#define LPSPI_FSR_TXCOUNT_SHIFT (0U) +#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) +#define LPSPI_FSR_RXCOUNT_MASK (0xF0000U) +#define LPSPI_FSR_RXCOUNT_SHIFT (16U) +#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) + +/* TCR - Transmit Command Register */ +#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) +#define LPSPI_TCR_FRAMESZ_SHIFT (0U) +#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) +#define LPSPI_TCR_WIDTH_MASK (0x30000U) +#define LPSPI_TCR_WIDTH_SHIFT (16U) +/*! WIDTH - Transfer Width + * 0b00..1 bit transfer + * 0b01..2 bit transfer + * 0b10..4 bit transfer + * 0b11..Reserved + */ +#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) +#define LPSPI_TCR_TXMSK_MASK (0x40000U) +#define LPSPI_TCR_TXMSK_SHIFT (18U) +/*! TXMSK - Transmit Data Mask + * 0b0..Normal transfer + * 0b1..Mask transmit data + */ +#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) +#define LPSPI_TCR_RXMSK_MASK (0x80000U) +#define LPSPI_TCR_RXMSK_SHIFT (19U) +/*! RXMSK - Receive Data Mask + * 0b0..Normal transfer + * 0b1..Receive data is masked + */ +#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) +#define LPSPI_TCR_CONTC_MASK (0x100000U) +#define LPSPI_TCR_CONTC_SHIFT (20U) +/*! CONTC - Continuing Command + * 0b0..Command word for start of new transfer + * 0b1..Command word for continuing transfer + */ +#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) +#define LPSPI_TCR_CONT_MASK (0x200000U) +#define LPSPI_TCR_CONT_SHIFT (21U) +/*! CONT - Continuous Transfer + * 0b0..Continuous transfer is disabled + * 0b1..Continuous transfer is enabled + */ +#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) +#define LPSPI_TCR_BYSW_MASK (0x400000U) +#define LPSPI_TCR_BYSW_SHIFT (22U) +/*! BYSW - Byte Swap + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ +#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) +#define LPSPI_TCR_LSBF_MASK (0x800000U) +#define LPSPI_TCR_LSBF_SHIFT (23U) +/*! LSBF - LSB First + * 0b0..Data is transferred MSB first + * 0b1..Data is transferred LSB first + */ +#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) +#define LPSPI_TCR_PCS_MASK (0x3000000U) +#define LPSPI_TCR_PCS_SHIFT (24U) +/*! PCS - Peripheral Chip Select + * 0b00..Transfer using LPSPI_PCS[0] + * 0b01..Transfer using LPSPI_PCS[1] + * 0b10..Transfer using LPSPI_PCS[2] + * 0b11..Transfer using LPSPI_PCS[3] + */ +#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) +#define LPSPI_TCR_PRESCALE_MASK (0x38000000U) +#define LPSPI_TCR_PRESCALE_SHIFT (27U) +/*! PRESCALE - Prescaler Value + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 + * 0b110..Divide by 64 + * 0b111..Divide by 128 + */ +#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) +#define LPSPI_TCR_CPHA_MASK (0x40000000U) +#define LPSPI_TCR_CPHA_SHIFT (30U) +/*! CPHA - Clock Phase + * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK + * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK + */ +#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) +#define LPSPI_TCR_CPOL_MASK (0x80000000U) +#define LPSPI_TCR_CPOL_SHIFT (31U) +/*! CPOL - Clock Polarity + * 0b0..The inactive state value of SCK is low + * 0b1..The inactive state value of SCK is high + */ +#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) + +/* TDR - Transmit Data Register */ +#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_TDR_DATA_SHIFT (0U) +#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) + +/* RSR - Receive Status Register */ +#define LPSPI_RSR_SOF_MASK (0x1U) +#define LPSPI_RSR_SOF_SHIFT (0U) +/*! SOF - Start Of Frame + * 0b0..Subsequent data word received after LPSPI_PCS assertion + * 0b1..First data word received after LPSPI_PCS assertion + */ +#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) +#define LPSPI_RSR_RXEMPTY_MASK (0x2U) +#define LPSPI_RSR_RXEMPTY_SHIFT (1U) +/*! RXEMPTY - RX FIFO Empty + * 0b0..RX FIFO is not empty + * 0b1..RX FIFO is empty + */ +#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) + +/* RDR - Receive Data Register */ +#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) +#define LPSPI_RDR_DATA_SHIFT (0U) +#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK) + +/* end of group LPSPI_Register_Masks */ + +#endif /* _FSL_LPSPI_H_ */ diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 3f97730bad0..c9a92d4acc4 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -39,6 +39,9 @@ #include #include #include +#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE) +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -809,6 +812,13 @@ static int fsl_qspi_probe(struct udevice *bus) q->iobase = map_physmem(res.start, res.end - res.start, MAP_NOCACHE); +#if CONFIG_IS_ENABLED(IMX_MODULE_FUSE) + if (qspi_fused((ulong)(q->iobase))) { + printf("QSPI@0x%lx is fused, disable it\n", (ulong)(q->iobase)); + return -ENODEV; + } +#endif + ret = fdt_get_named_resource(blob, node, "reg", "reg-names", "QuadSPI-memory", &res); if (ret) { diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index f3dddbdbd73..974bb56e210 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2008, Guennadi Liakhovetski + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * */ #include @@ -19,6 +21,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -547,6 +550,13 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, return NULL; } + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (ecspi_fused(spi_bases[bus])) { + printf("ECSPI@0x%lx is fused, disable it\n", spi_bases[bus]); + return NULL; + } + } + mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); if (!mxcs) { puts("mxc_spi: SPI Slave not allocated !\n"); diff --git a/drivers/spi/nxp_fspi.c b/drivers/spi/nxp_fspi.c index 6c5bad4c2ca..6eddaee4b89 100644 --- a/drivers/spi/nxp_fspi.c +++ b/drivers/spi/nxp_fspi.c @@ -54,6 +54,7 @@ * read operation, so let's use the last entry (31). */ #define SEQID_LUT 31 +#define SEQID_AHB_LUT 30 /* Registers used by the driver */ #define FSPI_MCR0 0x00 @@ -242,6 +243,10 @@ #define FSPI_LUT_REG(idx) \ (FSPI_LUT_BASE + FSPI_LUT_OFFSET + (idx) * 4) +#define FSPI_AHB_LUT_OFFSET (SEQID_AHB_LUT * 4 * 4) +#define FSPI_AHB_LUT_REG(idx) \ + (FSPI_LUT_BASE + FSPI_AHB_LUT_OFFSET + (idx) * 4) + /* register map end */ /* Instruction set for the LUT register. */ @@ -304,6 +309,9 @@ #define POLL_TOUT 5000 #define NXP_FSPI_MAX_CHIPSELECT 4 +/* access memory via IPS only due to this errata */ +#define NXP_FSPI_QUIRK_ERR050601 BIT(0) + struct nxp_fspi_devtype_data { unsigned int rxfifo; unsigned int txfifo; @@ -328,6 +336,22 @@ static const struct nxp_fspi_devtype_data imx8mm_data = { .little_endian = true, /* little-endian */ }; +static const struct nxp_fspi_devtype_data imx8qxp_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = 0, + .little_endian = true, /* little-endian */ +}; + +static const struct nxp_fspi_devtype_data imx8dxl_data = { + .rxfifo = SZ_512, /* (64 * 64 bits) */ + .txfifo = SZ_1K, /* (128 * 64 bits) */ + .ahb_buf_size = SZ_2K, /* (256 * 64 bits) */ + .quirks = NXP_FSPI_QUIRK_ERR050601, + .little_endian = true, /* little-endian */ +}; + struct nxp_fspi { struct udevice *dev; void __iomem *iobase; @@ -361,6 +385,11 @@ static u32 fspi_readl(struct nxp_fspi *f, void __iomem *addr) return in_be32(addr); } +static inline int nxp_fspi_ips_access_only(struct nxp_fspi *f) +{ + return f->devtype_data->quirks & NXP_FSPI_QUIRK_ERR050601; +} + static int nxp_fspi_check_buswidth(struct nxp_fspi *f, u8 width) { switch (width) { @@ -521,6 +550,13 @@ static void nxp_fspi_prepare_lut(struct nxp_fspi *f, for (i = 0; i < ARRAY_SIZE(lutval); i++) fspi_writel(f, lutval[i], base + FSPI_LUT_REG(i)); + + if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_IN && + op->addr.nbytes) { + for (i = 0; i < ARRAY_SIZE(lutval); i++) + fspi_writel(f, lutval[i], base + FSPI_AHB_LUT_REG(i)); + } + dev_dbg(f->dev, "CMD[%x] lutval[0:%x \t 1:%x \t 2:%x \t 3:%x]\n", op->cmd.opcode, lutval[0], lutval[1], lutval[2], lutval[3]); @@ -773,7 +809,8 @@ static int nxp_fspi_exec_op(struct spi_slave *slave, * by accessing the mapped memory. In all other cases we use * IP commands to access the flash. */ - if (op->data.nbytes > (f->devtype_data->rxfifo - 4) && + if (!nxp_fspi_ips_access_only(f) && + op->data.nbytes > (f->devtype_data->rxfifo - 4) && op->data.dir == SPI_MEM_DATA_IN) { nxp_fspi_read_ahb(f, op); } else { @@ -806,6 +843,11 @@ static int nxp_fspi_adjust_op_size(struct spi_slave *slave, op->data.nbytes = f->devtype_data->ahb_buf_size; else if (op->data.nbytes > (f->devtype_data->rxfifo - 4)) op->data.nbytes = ALIGN_DOWN(op->data.nbytes, 8); + + /* dxl won't use ahb to access data, limit to rxfifo size */ + if (nxp_fspi_ips_access_only(f) && + op->data.nbytes > f->devtype_data->rxfifo) + op->data.nbytes = f->devtype_data->rxfifo; } return 0; @@ -872,10 +914,10 @@ static int nxp_fspi_default_setup(struct nxp_fspi *f) base + FSPI_AHBCR); /* AHB Read - Set lut sequence ID for all CS. */ - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA1CR2); - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHA2CR2); - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB1CR2); - fspi_writel(f, SEQID_LUT, base + FSPI_FLSHB2CR2); + fspi_writel(f, SEQID_AHB_LUT, base + FSPI_FLSHA1CR2); + fspi_writel(f, SEQID_AHB_LUT, base + FSPI_FLSHA2CR2); + fspi_writel(f, SEQID_AHB_LUT, base + FSPI_FLSHB1CR2); + fspi_writel(f, SEQID_AHB_LUT, base + FSPI_FLSHB2CR2); return 0; } @@ -994,6 +1036,8 @@ static const struct dm_spi_ops nxp_fspi_ops = { static const struct udevice_id nxp_fspi_ids[] = { { .compatible = "nxp,lx2160a-fspi", .data = (ulong)&lx2160a_data, }, { .compatible = "nxp,imx8mm-fspi", .data = (ulong)&imx8mm_data, }, + { .compatible = "nxp,imx8qxp-fspi", .data = (ulong)&imx8qxp_data, }, + { .compatible = "nxp,imx8dxl-fspi", .data = (ulong)&imx8dxl_data, }, { } }; diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index ac77ffbc8be..ac4e69b815c 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -80,7 +80,7 @@ config SYSRESET_OCTEON config SYSRESET_PSCI bool "Enable support for PSCI System Reset" depends on ARM_PSCI_FW - select SPL_ARM_PSCI_FW if SPL + select SPL_ARM_PSCI_FW if SPL_SYSRESET help Enable PSCI SYSTEM_RESET function call. To use this, PSCI firmware must be running on your system. diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index f6975730bf8..eb1c0b18a98 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -68,12 +68,12 @@ config SPL_DM_USB_GADGET source "drivers/usb/host/Kconfig" -source "drivers/usb/cdns3/Kconfig" - source "drivers/usb/dwc3/Kconfig" source "drivers/usb/mtu3/Kconfig" +source "drivers/usb/cdns3/Kconfig" + source "drivers/usb/musb/Kconfig" source "drivers/usb/musb-new/Kconfig" diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig index 4cf59c70d43..11a7144b050 100644 --- a/drivers/usb/cdns3/Kconfig +++ b/drivers/usb/cdns3/Kconfig @@ -1,58 +1,20 @@ config USB_CDNS3 tristate "Cadence USB3 Dual-Role Controller" - depends on USB_HOST || USB_GADGET + depends on (USB && USB_GADGET) help - Say Y here if your system has a Cadence USB3 dual-role controller. - It supports: Host-only, and Peripheral-only. + Say Y here if your system has a cadence USB3 dual-role controller. + It supports: dual-role switch Host-only, and Peripheral-only. + + When compiled dynamically, the module will be called cdns3.ko. if USB_CDNS3 config USB_CDNS3_GADGET bool "Cadence USB3 device controller" depends on USB_GADGET - select USB_GADGET_DUALSPEED + select USB_GADGET_DUALSPEED help Say Y here to enable device controller functionality of the - Cadence USBSS-DEV driver. - - This controller supports FF and HS mode. It doesn't support - LS and SSP mode. - -config USB_CDNS3_HOST - bool "Cadence USB3 host controller" - depends on USB_XHCI_HCD - help - Say Y here to enable host controller functionality of the - Cadence driver. + cadence usb3 driver. - Host controller is compliant with XHCI so it will use - standard XHCI driver. - -config SPL_USB_CDNS3_GADGET - bool "SPL support for Cadence USB3 device controller" - depends on SPL_USB_GADGET - select USB_GADGET_DUALSPEED - help - Say Y here to enable device controller functionality of the - Cadence USBSS-DEV driver in SPL. - - This controller supports FF and HS mode. It doesn't support - LS and SSP mode. - -config SPL_USB_CDNS3_HOST - bool "Cadence USB3 host controller" - depends on USB_XHCI_HCD && SPL_USB_HOST_SUPPORT - help - Say Y here to enable host controller functionality of the - Cadence driver. - - Host controller is compliant with XHCI so it will use - standard XHCI driver. - -config USB_CDNS3_TI - tristate "Cadence USB3 support on TI platforms" - default USB_CDNS3 - help - Say 'Y' here if you are building for Texas Instruments - platforms that contain Cadence USB3 controller core. E.g.: J721e. endif diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile index 18d7190755d..374fa06efa1 100644 --- a/drivers/usb/cdns3/Makefile +++ b/drivers/usb/cdns3/Makefile @@ -1,11 +1,5 @@ -# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_USB_CDNS3) += cdns3.o -cdns3-y := core.o drd.o - -obj-$(CONFIG_USB_CDNS3) += cdns3.o - -cdns3-$(CONFIG_$(SPL_)USB_CDNS3_GADGET) += gadget.o ep0.o - -cdns3-$(CONFIG_$(SPL_)USB_CDNS3_HOST) += host.o - -obj-$(CONFIG_USB_CDNS3_TI) += cdns3-ti.o +cdns3-y := core.o +cdns3-$(CONFIG_USB_CDNS3_GADGET) += gadget.o +cdns3-$(CONFIG_$(SPL_)DM_USB_GADGET) += cdns3-generic.o diff --git a/drivers/usb/cdns3/cdns3-generic.c b/drivers/usb/cdns3/cdns3-generic.c new file mode 100644 index 00000000000..bb9e7f91d0e --- /dev/null +++ b/drivers/usb/cdns3/cdns3-generic.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include "core.h" +#include "gadget.h" + +static int cdns3_generic_peripheral_clk_init(struct udevice *dev, + struct cdns3_generic_peripheral + *priv) +{ +#if CONFIG_IS_ENABLED(CLK) + int ret; + + ret = clk_get_bulk(dev, &priv->clks); + if (ret == -ENOSYS) + return 0; + if (ret) + return ret; + + ret = clk_enable_bulk(&priv->clks); + if (ret) { + clk_release_bulk(&priv->clks); + return ret; + } +#endif + + return 0; +} + +static int cdns3_generic_handle_interrupts(struct udevice *dev) +{ + struct cdns3_generic_peripheral *priv = dev_get_priv(dev); + struct cdns3 *cdns3 = &priv->cdns3; + + cdns3_role_irq_handler(cdns3); + + return 0; +} + +static int cdns3_generic_peripheral_probe(struct udevice *dev) +{ + int ret; + struct cdns3_generic_peripheral *priv = dev_get_priv(dev); + struct cdns3 *cdns3 = &priv->cdns3; + + cdns3->dev = dev; + + ret = generic_phy_get_by_index(dev, 0, &priv->phy); + if (ret && ret != -ENOENT) { + printf("Failed to get USB PHY for %s\n", dev->name); + return ret; + } + + ret = cdns3_generic_peripheral_clk_init(dev, priv); + if (ret) + return ret; + + ret = cdns3_init(cdns3); + + return 0; +} + +static int cdns3_generic_peripheral_remove(struct udevice *dev) +{ + struct cdns3_generic_peripheral *priv = dev_get_priv(dev); + struct cdns3 *cdns3 = &priv->cdns3; + + cdns3_exit(cdns3); + + clk_release_bulk(&priv->clks); + + if (generic_phy_valid(&priv->phy)) + device_remove(priv->phy.dev, DM_REMOVE_NORMAL); + + return 0; +} + +static int cdns3_generic_peripheral_ofdata_to_platdata(struct udevice *dev) +{ + struct cdns3_generic_peripheral *priv = dev_get_priv(dev); + struct cdns3 *cdns3 = &priv->cdns3; + + cdns3->none_core_regs = (void __iomem *)devfdt_get_addr_name(dev, + "none-core"); + cdns3->xhci_regs = (void __iomem *)devfdt_get_addr_name(dev, "xhci"); + cdns3->dev_regs = (void __iomem *)devfdt_get_addr_name(dev, "dev"); + cdns3->phy_regs = (void __iomem *)devfdt_get_addr_name(dev, "phy"); + cdns3->otg_regs = (void __iomem *)devfdt_get_addr_name(dev, "otg"); + + return 0; +} + +static const struct udevice_id cdns3_generic_peripheral_ids[] = { + { .compatible = "Cadence,usb3" }, + {}, +}; + +U_BOOT_DRIVER(cdns3_generic_peripheral) = { + .name = "cdns3-generic-peripheral", + .id = UCLASS_USB_GADGET_GENERIC, + .of_match = cdns3_generic_peripheral_ids, + .of_to_plat = cdns3_generic_peripheral_ofdata_to_platdata, + .probe = cdns3_generic_peripheral_probe, + .remove = cdns3_generic_peripheral_remove, + .handle_interrupts = cdns3_generic_handle_interrupts, + .priv_auto = sizeof(struct cdns3_generic_peripheral), +}; diff --git a/drivers/usb/cdns3/cdns3-nxp-reg-def.h b/drivers/usb/cdns3/cdns3-nxp-reg-def.h new file mode 100644 index 00000000000..4819957be4e --- /dev/null +++ b/drivers/usb/cdns3/cdns3-nxp-reg-def.h @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __DRIVERS_USB_CDNS3_NXP_H +#define __DRIVERS_USB_CDNS3_NXP_H + +#define USB3_CORE_CTRL1 0x00 +#define USB3_CORE_CTRL2 0x04 +#define USB3_INT_REG 0x08 +#define USB3_CORE_STATUS 0x0c +#define XHCI_DEBUG_LINK_ST 0x10 +#define XHCI_DEBUG_BUS 0x14 +#define USB3_SSPHY_CTRL1 0x40 +#define USB3_SSPHY_CTRL2 0x44 +#define USB3_SSPHY_STATUS 0x4c +#define USB2_PHY_CTRL1 0x50 +#define USB2_PHY_CTRL2 0x54 +#define USB2_PHY_STATUS 0x5c + +/* Register bits definition */ + +/* USB3_CORE_CTRL1 */ +#define SW_RESET_MASK (0x3f << 26) +#define PWR_SW_RESET BIT(31) +#define APB_SW_RESET BIT(30) +#define AXI_SW_RESET BIT(29) +#define RW_SW_RESET BIT(28) +#define PHY_SW_RESET BIT(27) +#define PHYAHB_SW_RESET BIT(26) +#define ALL_SW_RESET (PWR_SW_RESET | APB_SW_RESET | AXI_SW_RESET | \ + RW_SW_RESET | PHY_SW_RESET | PHYAHB_SW_RESET) +#define OC_DISABLE BIT(9) +#define MDCTRL_CLK_SEL BIT(7) +#define MODE_STRAP_MASK (0x7) +#define DEV_MODE BIT(2) +#define HOST_MODE BIT(1) +#define OTG_MODE BIT(0) + +/* USB3_INT_REG */ +#define CLK_125_REQ BIT(29) +#define LPM_CLK_REQ BIT(28) +#define DEVU3_WAEKUP_EN BIT(14) +#define OTG_WAKEUP_EN BIT(12) +#define DEV_INT_EN (3 << 8) /* DEV INT b9:8 */ +#define HOST_INT1_EN BIT(0) /* HOST INT b7:0 */ + +/* USB3_CORE_STATUS */ +#define MDCTRL_CLK_STATUS BIT(15) +#define DEV_POWER_ON_READY BIT(13) +#define HOST_POWER_ON_READY BIT(12) + +/* USB3_SSPHY_STATUS */ +#define PHY_REFCLK_REQ BIT(0) +#define CLK_VLD 0xf0000000 + +/* PHY register definition */ +#define TB_ADDR_TX_RCVDETSC_CTRL (0x4124 * 4) +#define CDNS3_USB2_PHY_BASE (0x38000) +#define USB2_PHY_AFE_BC_REG4 (CDNS3_USB2_PHY_BASE + 0x29 * 4) + +/* USB2_PHY_AFE_BC_REG4 */ +#define SET_FORCE_B_SESS_VALID 0x60 + +/* TB_ADDR_TX_RCVDETSC_CTRL */ +#define RXDET_IN_P3_32KHZ BIT(0) + +/* OTG registers definition */ +#define OTGSTS 0x4 +#define OTGREFCLK 0xc + +/* Register bits definition */ +/* OTGSTS */ +#define OTG_NRDY BIT(11) +/* OTGREFCLK */ +#define OTG_STB_CLK_SWITCH_EN BIT(31) + +/* xHCI registers definition */ +#define XECP_PORT_CAP_REG 0x8000 +#define XECP_PM_PMCSR 0x8018 +#define XECP_AUX_CTRL_REG1 0x8120 + +/* Register bits definition */ +/* XECP_PORT_CAP_REG */ +#define LPM_2_STB_SWITCH_EN BIT(25) + +/* XECP_AUX_CTRL_REG1 */ +#define CFG_RXDET_P3_EN BIT(15) + +/* XECP_PM_PMCSR */ +#define PS_D0 BIT(0) +#endif /* __DRIVERS_USB_CDNS3_NXP_H */ diff --git a/drivers/usb/cdns3/cdns3-ti.c b/drivers/usb/cdns3/cdns3-ti.c deleted file mode 100644 index 7b205c56567..00000000000 --- a/drivers/usb/cdns3/cdns3-ti.c +++ /dev/null @@ -1,195 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/** - * cdns_ti-ti.c - TI specific Glue layer for Cadence USB Controller - * - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "core.h" - -/* USB Wrapper register offsets */ -#define USBSS_PID 0x0 -#define USBSS_W1 0x4 -#define USBSS_STATIC_CONFIG 0x8 -#define USBSS_PHY_TEST 0xc -#define USBSS_DEBUG_CTRL 0x10 -#define USBSS_DEBUG_INFO 0x14 -#define USBSS_DEBUG_LINK_STATE 0x18 -#define USBSS_DEVICE_CTRL 0x1c - -/* Wrapper 1 register bits */ -#define USBSS_W1_PWRUP_RST BIT(0) -#define USBSS_W1_OVERCURRENT_SEL BIT(8) -#define USBSS_W1_MODESTRAP_SEL BIT(9) -#define USBSS_W1_OVERCURRENT BIT(16) -#define USBSS_W1_MODESTRAP_MASK GENMASK(18, 17) -#define USBSS_W1_MODESTRAP_SHIFT 17 -#define USBSS_W1_USB2_ONLY BIT(19) - -/* Static config register bits */ -#define USBSS1_STATIC_PLL_REF_SEL_MASK GENMASK(8, 5) -#define USBSS1_STATIC_PLL_REF_SEL_SHIFT 5 -#define USBSS1_STATIC_LOOPBACK_MODE_MASK GENMASK(4, 3) -#define USBSS1_STATIC_LOOPBACK_MODE_SHIFT 3 -#define USBSS1_STATIC_VBUS_SEL_MASK GENMASK(2, 1) -#define USBSS1_STATIC_VBUS_SEL_SHIFT 1 -#define USBSS1_STATIC_LANE_REVERSE BIT(0) - -/* Modestrap modes */ -enum modestrap_mode { USBSS_MODESTRAP_MODE_NONE, - USBSS_MODESTRAP_MODE_HOST, - USBSS_MODESTRAP_MODE_PERIPHERAL}; - -struct cdns_ti { - struct udevice *dev; - void __iomem *usbss; - int usb2_only:1; - int vbus_divider:1; - struct clk *usb2_refclk; - struct clk *lpm_clk; -}; - -static const int cdns_ti_rate_table[] = { /* in KHZ */ - 9600, - 10000, - 12000, - 19200, - 20000, - 24000, - 25000, - 26000, - 38400, - 40000, - 58000, - 50000, - 52000, -}; - -static inline u32 cdns_ti_readl(struct cdns_ti *data, u32 offset) -{ - return readl(data->usbss + offset); -} - -static inline void cdns_ti_writel(struct cdns_ti *data, u32 offset, u32 value) -{ - writel(value, data->usbss + offset); -} - -static int cdns_ti_probe(struct udevice *dev) -{ - struct cdns_ti *data = dev_get_plat(dev); - struct clk usb2_refclk; - int modestrap_mode; - unsigned long rate; - int rate_code, i; - u32 reg; - int ret; - - data->dev = dev; - - data->usbss = dev_remap_addr_index(dev, 0); - if (!data->usbss) - return -EINVAL; - - ret = clk_get_by_name(dev, "usb2_refclk", &usb2_refclk); - if (ret) { - dev_err(dev, "Failed to get usb2_refclk\n"); - return ret; - } - - rate = clk_get_rate(&usb2_refclk); - rate /= 1000; /* To KHz */ - for (i = 0; i < ARRAY_SIZE(cdns_ti_rate_table); i++) { - if (cdns_ti_rate_table[i] == rate) - break; - } - - if (i == ARRAY_SIZE(cdns_ti_rate_table)) { - dev_err(dev, "unsupported usb2_refclk rate: %lu KHz\n", rate); - return -EINVAL; - } - - rate_code = i; - - /* assert RESET */ - reg = cdns_ti_readl(data, USBSS_W1); - reg &= ~USBSS_W1_PWRUP_RST; - cdns_ti_writel(data, USBSS_W1, reg); - - /* set static config */ - reg = cdns_ti_readl(data, USBSS_STATIC_CONFIG); - reg &= ~USBSS1_STATIC_PLL_REF_SEL_MASK; - reg |= rate_code << USBSS1_STATIC_PLL_REF_SEL_SHIFT; - - reg &= ~USBSS1_STATIC_VBUS_SEL_MASK; - data->vbus_divider = dev_read_bool(dev, "ti,vbus-divider"); - if (data->vbus_divider) - reg |= 1 << USBSS1_STATIC_VBUS_SEL_SHIFT; - - cdns_ti_writel(data, USBSS_STATIC_CONFIG, reg); - reg = cdns_ti_readl(data, USBSS_STATIC_CONFIG); - - /* set USB2_ONLY mode if requested */ - reg = cdns_ti_readl(data, USBSS_W1); - data->usb2_only = dev_read_bool(dev, "ti,usb2-only"); - if (data->usb2_only) - reg |= USBSS_W1_USB2_ONLY; - - /* set modestrap */ - if (dev_read_bool(dev, "ti,modestrap-host")) - modestrap_mode = USBSS_MODESTRAP_MODE_HOST; - else if (dev_read_bool(dev, "ti,modestrap-peripheral")) - modestrap_mode = USBSS_MODESTRAP_MODE_PERIPHERAL; - else - modestrap_mode = USBSS_MODESTRAP_MODE_NONE; - - reg |= USBSS_W1_MODESTRAP_SEL; - reg &= ~USBSS_W1_MODESTRAP_MASK; - reg |= modestrap_mode << USBSS_W1_MODESTRAP_SHIFT; - cdns_ti_writel(data, USBSS_W1, reg); - - /* de-assert RESET */ - reg |= USBSS_W1_PWRUP_RST; - cdns_ti_writel(data, USBSS_W1, reg); - - return 0; -} - -static int cdns_ti_remove(struct udevice *dev) -{ - struct cdns_ti *data = dev_get_plat(dev); - u32 reg; - - /* put device back to RESET*/ - reg = cdns_ti_readl(data, USBSS_W1); - reg &= ~USBSS_W1_PWRUP_RST; - cdns_ti_writel(data, USBSS_W1, reg); - - return 0; -} - -static const struct udevice_id cdns_ti_of_match[] = { - { .compatible = "ti,j721e-usb", }, - {}, -}; - -U_BOOT_DRIVER(cdns_ti) = { - .name = "cdns-ti", - .id = UCLASS_NOP, - .of_match = cdns_ti_of_match, - .bind = cdns3_bind, - .probe = cdns_ti_probe, - .remove = cdns_ti_remove, - .plat_auto = sizeof(struct cdns_ti), - .flags = DM_FLAG_OS_PREPARE, -}; diff --git a/drivers/usb/cdns3/core.c b/drivers/usb/cdns3/core.c index 798a21793f7..377e0bd4f31 100644 --- a/drivers/usb/cdns3/core.c +++ b/drivers/usb/cdns3/core.c @@ -1,499 +1,205 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ /* - * Cadence USBSS DRD Driver. - * - * Copyright (C) 2018-2019 Cadence. - * Copyright (C) 2017-2018 NXP - * Copyright (C) 2019 Texas Instruments - * - * Author: Peter Chen - * Pawel Laszczak - * Roger Quadros + * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/ + * Copyright 2019 NXP */ - #include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include +#include "cdns3-nxp-reg-def.h" #include "core.h" -#include "host-export.h" #include "gadget-export.h" -#include "drd.h" - -static int cdns3_idle_init(struct cdns3 *cdns); - -struct cdns3_host_priv { - struct xhci_ctrl xhci_ctrl; - struct cdns3 cdns; -}; - -struct cdns3_gadget_priv { - struct cdns3 cdns; -}; +#include "gadget.h" -static inline -struct cdns3_role_driver *cdns3_get_current_role_driver(struct cdns3 *cdns) +static void cdns3_reset_core(struct cdns3 *cdns) { - WARN_ON(!cdns->roles[cdns->role]); - return cdns->roles[cdns->role]; + /* Set all Reset bits */ + setbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1, ALL_SW_RESET); + udelay(1); } -static int cdns3_role_start(struct cdns3 *cdns, enum usb_role role) +static int cdns3_host_role_set(struct cdns3 *cdns) { int ret; - if (WARN_ON(role > USB_ROLE_DEVICE)) - return 0; - - mutex_lock(&cdns->mutex); - cdns->role = role; - mutex_unlock(&cdns->mutex); - - if (!cdns->roles[role]) - return -ENXIO; - - if (cdns->roles[role]->state == CDNS3_ROLE_STATE_ACTIVE) - return 0; - - mutex_lock(&cdns->mutex); - ret = cdns->roles[role]->start(cdns); - if (!ret) - cdns->roles[role]->state = CDNS3_ROLE_STATE_ACTIVE; - mutex_unlock(&cdns->mutex); + struct cdns3_generic_peripheral *priv = container_of(cdns, + struct cdns3_generic_peripheral, cdns3); + + clrsetbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1, + MODE_STRAP_MASK, HOST_MODE | OC_DISABLE); + clrbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1, + PHYAHB_SW_RESET); + mdelay(1); + generic_phy_init(&priv->phy); + setbits_le32(cdns->phy_regs + TB_ADDR_TX_RCVDETSC_CTRL, + RXDET_IN_P3_32KHZ); + udelay(10); + /* Force B Session Valid as 1 */ + writel(SET_FORCE_B_SESS_VALID, cdns->phy_regs + USB2_PHY_AFE_BC_REG4); + mdelay(1); + + setbits_le32(cdns->none_core_regs + USB3_INT_REG, HOST_INT1_EN); + + clrbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1, + ALL_SW_RESET); + + dev_dbg(cdns->dev, "wait xhci_power_on_ready\n"); + ret = wait_for_bit_le32(cdns->none_core_regs + USB3_CORE_STATUS, + HOST_POWER_ON_READY, true, 100, false); + if (ret) { + dev_err(cdns->dev, "wait xhci_power_on_ready timeout\n"); + return ret; + } - return ret; + return 0; } -static void cdns3_role_stop(struct cdns3 *cdns) +static int cdns3_gadget_role_set(struct cdns3 *cdns) { - enum usb_role role = cdns->role; - - if (WARN_ON(role > USB_ROLE_DEVICE)) - return; - - if (cdns->roles[role]->state == CDNS3_ROLE_STATE_INACTIVE) - return; + int ret; - mutex_lock(&cdns->mutex); - cdns->roles[role]->stop(cdns); - cdns->roles[role]->state = CDNS3_ROLE_STATE_INACTIVE; - mutex_unlock(&cdns->mutex); -} + struct cdns3_generic_peripheral *priv = container_of(cdns, + struct cdns3_generic_peripheral, cdns3); -static void cdns3_exit_roles(struct cdns3 *cdns) -{ - cdns3_role_stop(cdns); - cdns3_drd_exit(cdns); -} + clrsetbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1, + MODE_STRAP_MASK, DEV_MODE); + clrbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1, + PHYAHB_SW_RESET); -static enum usb_role cdsn3_hw_role_state_machine(struct cdns3 *cdns); + generic_phy_init(&priv->phy); + setbits_le32(cdns->phy_regs + TB_ADDR_TX_RCVDETSC_CTRL, + RXDET_IN_P3_32KHZ); + udelay(10); + /* Force B Session Valid as 1 */ + writel(SET_FORCE_B_SESS_VALID, cdns->phy_regs + USB2_PHY_AFE_BC_REG4); + setbits_le32(cdns->none_core_regs + USB3_INT_REG, DEV_INT_EN); -/** - * cdns3_core_init_role - initialize role of operation - * @cdns: Pointer to cdns3 structure - * - * Returns 0 on success otherwise negative errno - */ -static int cdns3_core_init_role(struct cdns3 *cdns) -{ - struct udevice *dev = cdns->dev; - enum usb_dr_mode best_dr_mode; - enum usb_dr_mode dr_mode; - int ret = 0; - - dr_mode = usb_get_dr_mode(dev_ofnode(dev)); - cdns->role = USB_ROLE_NONE; - - /* - * If driver can't read mode by means of usb_get_dr_mode function then - * chooses mode according with Kernel configuration. This setting - * can be restricted later depending on strap pin configuration. - */ - if (dr_mode == USB_DR_MODE_UNKNOWN) { - if (IS_ENABLED(CONFIG_USB_CDNS3_HOST) && - IS_ENABLED(CONFIG_USB_CDNS3_GADGET)) - dr_mode = USB_DR_MODE_OTG; - else if (IS_ENABLED(CONFIG_USB_CDNS3_HOST)) - dr_mode = USB_DR_MODE_HOST; - else if (IS_ENABLED(CONFIG_USB_CDNS3_GADGET)) - dr_mode = USB_DR_MODE_PERIPHERAL; - } + clrbits_le32(cdns->none_core_regs + USB3_CORE_CTRL1, + ALL_SW_RESET); - /* - * At this point cdns->dr_mode contains strap configuration. - * Driver try update this setting considering kernel configuration - */ - best_dr_mode = cdns->dr_mode; - - ret = cdns3_idle_init(cdns); - if (ret) + dev_dbg(cdns->dev, "wait gadget_power_on_ready\n"); + ret = wait_for_bit_le32(cdns->none_core_regs + USB3_CORE_STATUS, + DEV_POWER_ON_READY, true, 100, false); + if (ret) { + dev_err(cdns->dev, "wait gadget_power_on_ready timeout\n"); return ret; - - if (dr_mode == USB_DR_MODE_OTG) { - best_dr_mode = cdns->dr_mode; - } else if (cdns->dr_mode == USB_DR_MODE_OTG) { - best_dr_mode = dr_mode; - } else if (cdns->dr_mode != dr_mode) { - dev_err(dev, "Incorrect DRD configuration\n"); - return -EINVAL; - } - - dr_mode = best_dr_mode; - -#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) - if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { - ret = cdns3_host_init(cdns); - if (ret) { - dev_err(dev, "Host initialization failed with %d\n", - ret); - goto err; - } - } -#endif - -#if CONFIG_IS_ENABLED(DM_USB_GADGET) - if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) { - ret = cdns3_gadget_init(cdns); - if (ret) { - dev_err(dev, "Device initialization failed with %d\n", - ret); - goto err; - } } -#endif - cdns->dr_mode = dr_mode; - - ret = cdns3_drd_update_mode(cdns); - if (ret) - goto err; - - if (cdns->dr_mode != USB_DR_MODE_OTG) { - ret = cdns3_hw_role_switch(cdns); - if (ret) - goto err; - } - - return ret; -err: - cdns3_exit_roles(cdns); - return ret; + return 0; } -/** - * cdsn3_hw_role_state_machine - role switch state machine based on hw events - * @cdns: Pointer to controller structure. - * - * Returns next role to be entered based on hw events. - */ -static enum usb_role cdsn3_hw_role_state_machine(struct cdns3 *cdns) +static int cdns3_set_role(struct cdns3 *cdns, enum cdns3_roles role) { - enum usb_role role; - int id, vbus; - - if (cdns->dr_mode != USB_DR_MODE_OTG) - goto not_otg; - - id = cdns3_get_id(cdns); - vbus = cdns3_get_vbus(cdns); - - /* - * Role change state machine - * Inputs: ID, VBUS - * Previous state: cdns->role - * Next state: role - */ - role = cdns->role; - - switch (role) { - case USB_ROLE_NONE: - /* - * Driver treats USB_ROLE_NONE synonymous to IDLE state from - * controller specification. - */ - if (!id) - role = USB_ROLE_HOST; - else if (vbus) - role = USB_ROLE_DEVICE; - break; - case USB_ROLE_HOST: /* from HOST, we can only change to NONE */ - if (id) - role = USB_ROLE_NONE; - break; - case USB_ROLE_DEVICE: /* from GADGET, we can only change to NONE*/ - if (!vbus) - role = USB_ROLE_NONE; - break; - } + int ret; - dev_dbg(cdns->dev, "role %d -> %d\n", cdns->role, role); + if (role == CDNS3_ROLE_END) + return -EPERM; - return role; + /* Wait clk value */ + writel(CLK_VLD, cdns->none_core_regs + USB3_SSPHY_STATUS); + ret = wait_for_bit_le32(cdns->none_core_regs + USB3_SSPHY_STATUS, + CLK_VLD, true, 100, false); + if (ret) { + dev_err(cdns->dev, "wait clkvld timeout\n"); + return ret; + } -not_otg: - if (cdns3_is_host(cdns)) - role = USB_ROLE_HOST; - if (cdns3_is_device(cdns)) - role = USB_ROLE_DEVICE; + cdns3_reset_core(cdns); - return role; -} + if (role == CDNS3_ROLE_HOST) { + cdns3_host_role_set(cdns); + dev_dbg(cdns->dev, "switch to host role successfully\n"); + } else { /* gadget mode */ + cdns3_gadget_role_set(cdns); + dev_dbg(cdns->dev, "switch to gadget role successfully\n"); + } -static int cdns3_idle_role_start(struct cdns3 *cdns) -{ return 0; } -static void cdns3_idle_role_stop(struct cdns3 *cdns) +static enum cdns3_roles cdns3_get_role(struct cdns3 *cdns) { - /* Program Lane swap and bring PHY out of RESET */ - generic_phy_reset(&cdns->usb3_phy); -} - -static int cdns3_idle_init(struct cdns3 *cdns) -{ - struct cdns3_role_driver *rdrv; - - rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL); - if (!rdrv) - return -ENOMEM; - - rdrv->start = cdns3_idle_role_start; - rdrv->stop = cdns3_idle_role_stop; - rdrv->state = CDNS3_ROLE_STATE_INACTIVE; - rdrv->suspend = NULL; - rdrv->resume = NULL; - rdrv->name = "idle"; - - cdns->roles[USB_ROLE_NONE] = rdrv; - - return 0; + return cdns->roles[CDNS3_ROLE_HOST] + ? CDNS3_ROLE_HOST + : CDNS3_ROLE_GADGET; } /** - * cdns3_hw_role_switch - switch roles based on HW state - * @cdns3: controller + * cdns3_core_init_role - initialize role of operation + * @cdns: Pointer to cdns3 structure + * @dr_mode: Role mode of device + * + * Returns 0 on success otherwise negative errno */ -int cdns3_hw_role_switch(struct cdns3 *cdns) +static int cdns3_core_init_role(struct cdns3 *cdns, enum usb_dr_mode dr_mode) { - enum usb_role real_role, current_role; - int ret = 0; - - /* Do nothing if role based on syfs. */ - if (cdns->role_override) - return 0; - - current_role = cdns->role; - real_role = cdsn3_hw_role_state_machine(cdns); - - /* Do nothing if nothing changed */ - if (current_role == real_role) - goto exit; + cdns->role = CDNS3_ROLE_END; + if (dr_mode == USB_DR_MODE_UNKNOWN) + dr_mode = USB_DR_MODE_OTG; - cdns3_role_stop(cdns); - - dev_dbg(cdns->dev, "Switching role %d -> %d", current_role, real_role); - - ret = cdns3_role_start(cdns, real_role); - if (ret) { - /* Back to current role */ - dev_err(cdns->dev, "set %d has failed, back to %d\n", - real_role, current_role); - ret = cdns3_role_start(cdns, current_role); - if (ret) - dev_err(cdns->dev, "back to %d failed too\n", - current_role); + /* Currently, only support gadget mode */ + if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { + dev_err(cdns->dev, "doesn't support host and OTG, only for gadget\n"); + return -EPERM; } -exit: - return ret; -} - -static int cdns3_probe(struct cdns3 *cdns) -{ - struct udevice *dev = cdns->dev; - int ret; - - cdns->xhci_regs = dev_remap_addr_name(dev, "xhci"); - if (!cdns->xhci_regs) - return -EINVAL; - - cdns->dev_regs = dev_remap_addr_name(dev, "dev"); - if (!cdns->dev_regs) - return -EINVAL; - - mutex_init(&cdns->mutex); - - ret = generic_phy_get_by_name(dev, "cdns3,usb2-phy", &cdns->usb2_phy); - if (ret) - dev_warn(dev, "Unable to get USB2 phy (ret %d)\n", ret); - - ret = generic_phy_init(&cdns->usb2_phy); - if (ret) - return ret; - - ret = generic_phy_get_by_name(dev, "cdns3,usb3-phy", &cdns->usb3_phy); - if (ret) - dev_warn(dev, "Unable to get USB3 phy (ret %d)\n", ret); - - ret = generic_phy_init(&cdns->usb3_phy); - if (ret) - return ret; - ret = generic_phy_power_on(&cdns->usb2_phy); - if (ret) - return ret; - - ret = generic_phy_power_on(&cdns->usb3_phy); - if (ret) - return ret; - - ret = cdns3_drd_init(cdns); - if (ret) - return ret; - - ret = cdns3_core_init_role(cdns); - if (ret) - return ret; + if (dr_mode == USB_DR_MODE_PERIPHERAL) { + if (cdns3_gadget_init(cdns)) + dev_info(cdns->dev, "doesn't support gadget\n"); + } - dev_dbg(dev, "Cadence USB3 core: probe succeed\n"); + if (!cdns->roles[CDNS3_ROLE_HOST] && !cdns->roles[CDNS3_ROLE_GADGET]) { + dev_err(cdns->dev, "no supported roles\n"); + return -ENODEV; + } return 0; } -static int cdns3_remove(struct cdns3 *cdns) +static void cdns3_remove_roles(struct cdns3 *cdns) { - cdns3_exit_roles(cdns); - generic_phy_power_off(&cdns->usb2_phy); - generic_phy_power_off(&cdns->usb3_phy); - generic_phy_exit(&cdns->usb2_phy); - generic_phy_exit(&cdns->usb3_phy); - return 0; + /* Only support gadget */ + cdns3_gadget_remove(cdns); } -static const struct udevice_id cdns3_ids[] = { - { .compatible = "cdns,usb3" }, - { }, -}; - -int cdns3_bind(struct udevice *parent) +int cdns3_init(struct cdns3 *cdns) { - enum usb_dr_mode dr_mode; - struct udevice *dev; - const char *driver; - const char *name; - ofnode node; int ret; - node = ofnode_by_compatible(dev_ofnode(parent), "cdns,usb3"); - if (!ofnode_valid(node)) { - ret = -ENODEV; - goto fail; - } + ret = cdns3_core_init_role(cdns, USB_DR_MODE_PERIPHERAL); - name = ofnode_get_name(node); - dr_mode = usb_get_dr_mode(node); - - switch (dr_mode) { -#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || \ - (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)) - case USB_DR_MODE_HOST: - debug("%s: dr_mode: HOST\n", __func__); - driver = "cdns-usb3-host"; - break; -#endif -#if CONFIG_IS_ENABLED(DM_USB_GADGET) - case USB_DR_MODE_PERIPHERAL: - debug("%s: dr_mode: PERIPHERAL\n", __func__); - driver = "cdns-usb3-peripheral"; - break; -#endif - default: - printf("%s: unsupported dr_mode\n", __func__); - ret = -ENODEV; - goto fail; - }; - - ret = device_bind_driver_to_node(parent, driver, name, node, &dev); + cdns->role = cdns3_get_role(cdns); + dev_dbg(cdns->dev, "the init role is %d\n", cdns->role); + cdns3_set_role(cdns, cdns->role); + ret = cdns3_role_start(cdns, cdns->role); if (ret) { - printf("%s: not able to bind usb device mode\n", - __func__); - goto fail; + dev_err(cdns->dev, "can't start %s role\n", cdns3_role(cdns)->name); + goto err; } - return 0; + dev_dbg(cdns->dev, "Cadence USB3 core: probe succeed\n"); -fail: - /* do not return an error: failing to bind would hang the board */ return 0; -} -#if CONFIG_IS_ENABLED(DM_USB_GADGET) -static int cdns3_gadget_probe(struct udevice *dev) -{ - struct cdns3_gadget_priv *priv = dev_get_priv(dev); - struct cdns3 *cdns = &priv->cdns; - - cdns->dev = dev; - - return cdns3_probe(cdns); -} - -static int cdns3_gadget_remove(struct udevice *dev) -{ - struct cdns3_gadget_priv *priv = dev_get_priv(dev); - struct cdns3 *cdns = &priv->cdns; - - return cdns3_remove(cdns); -} - -U_BOOT_DRIVER(cdns_usb3_peripheral) = { - .name = "cdns-usb3-peripheral", - .id = UCLASS_USB_GADGET_GENERIC, - .of_match = cdns3_ids, - .probe = cdns3_gadget_probe, - .remove = cdns3_gadget_remove, - .priv_auto = sizeof(struct cdns3_gadget_priv), - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; -#endif - -#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || \ - (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)) -static int cdns3_host_probe(struct udevice *dev) -{ - struct cdns3_host_priv *priv = dev_get_priv(dev); - struct cdns3 *cdns = &priv->cdns; - - cdns->dev = dev; +err: + cdns3_remove_roles(cdns); - return cdns3_probe(cdns); + return ret; } -static int cdns3_host_remove(struct udevice *dev) +void cdns3_exit(struct cdns3 *cdns) { - struct cdns3_host_priv *priv = dev_get_priv(dev); - struct cdns3 *cdns = &priv->cdns; - - return cdns3_remove(cdns); + cdns3_role_stop(cdns); + cdns3_remove_roles(cdns); + cdns3_reset_core(cdns); } - -U_BOOT_DRIVER(cdns_usb3_host) = { - .name = "cdns-usb3-host", - .id = UCLASS_USB, - .of_match = cdns3_ids, - .probe = cdns3_host_probe, - .remove = cdns3_host_remove, - .priv_auto = sizeof(struct cdns3_host_priv), - .ops = &xhci_usb_ops, - .flags = DM_FLAG_ALLOC_PRIV_DMA, -}; -#endif diff --git a/drivers/usb/cdns3/core.h b/drivers/usb/cdns3/core.h index 0668d646fc4..d097678e52e 100644 --- a/drivers/usb/cdns3/core.h +++ b/drivers/usb/cdns3/core.h @@ -1,28 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Cadence USBSS DRD Header File. - * - * Copyright (C) 2017-2018 NXP - * Copyright (C) 2018-2019 Cadence. - * - * Authors: Peter Chen - * Pawel Laszczak + * Copyright 2019 NXP */ -#include -#include -#include -#include - -#ifndef __LINUX_CDNS3_CORE_H -#define __LINUX_CDNS3_CORE_H - -enum usb_role { - USB_ROLE_NONE, - USB_ROLE_HOST, - USB_ROLE_DEVICE, -}; + +#ifndef __DRIVERS_USB_CDNS3_CORE_H +#define __DRIVERS_USB_CDNS3_CORE_H struct cdns3; +enum cdns3_roles { + CDNS3_ROLE_HOST = 0, + CDNS3_ROLE_GADGET, + CDNS3_ROLE_END, +}; /** * struct cdns3_role_driver - host/gadget role driver @@ -32,77 +21,98 @@ struct cdns3; * @resume: resume callback for this role * @irq: irq handler for this role * @name: role name string (host/gadget) - * @state: current state */ struct cdns3_role_driver { int (*start)(struct cdns3 *cdns); void (*stop)(struct cdns3 *cdns); int (*suspend)(struct cdns3 *cdns, bool do_wakeup); int (*resume)(struct cdns3 *cdns, bool hibernated); + int (*irq)(struct cdns3 *cdns); const char *name; -#define CDNS3_ROLE_STATE_INACTIVE 0 -#define CDNS3_ROLE_STATE_ACTIVE 1 - int state; }; -#define CDNS3_XHCI_RESOURCES_NUM 2 +#define CDNS3_NUM_OF_CLKS 5 /** * struct cdns3 - Representation of Cadence USB3 DRD controller. * @dev: pointer to Cadence device struct * @xhci_regs: pointer to base of xhci registers + * @xhci_res: the resource for xhci * @dev_regs: pointer to base of dev registers - * @otg_v0_regs: pointer to base of v0 otg registers - * @otg_v1_regs: pointer to base of v1 otg registers + * @none_core_regs: pointer to base of nxp wrapper registers + * @phy_regs: pointer to base of phy registers * @otg_regs: pointer to base of otg registers - * @otg_irq: irq number for otg controller - * @dev_irq: irq number for device controller + * @irq: irq number for controller * @roles: array of supported roles for this controller * @role: current role * @host_dev: the child host device pointer for cdns3 core * @gadget_dev: the child gadget device pointer for cdns3 core - * @usb2_phy: pointer to USB2 PHY - * @usb3_phy: pointer to USB3 PHY - * @mutex: the mutex for concurrent code at driver - * @dr_mode: supported mode of operation it can be only Host, only Device - * or OTG mode that allow to switch between Device and Host mode. - * This field based on firmware setting, kernel configuration - * and hardware configuration. - * @role_sw: pointer to role switch object. - * @role_override: set 1 if role rely on SW. + * @usbphy: usbphy for this controller + * @cdns3_clks: Clock pointer array for cdns3 core + * @extcon: Type-C extern connector + * @extcon_nb: notifier block for Type-C extern connector + * @role_switch_wq: work queue item for role switch + * @in_lpm: the controller in low power mode + * @wakeup_int: the wakeup interrupt */ struct cdns3 { - struct udevice *dev; - void __iomem *xhci_regs; - struct cdns3_usb_regs __iomem *dev_regs; - - struct cdns3_otg_legacy_regs *otg_v0_regs; - struct cdns3_otg_regs *otg_v1_regs; - struct cdns3_otg_common_regs *otg_regs; -#define CDNS3_CONTROLLER_V0 0 -#define CDNS3_CONTROLLER_V1 1 - u32 version; - - int otg_irq; - int dev_irq; - struct cdns3_role_driver *roles[USB_ROLE_DEVICE + 1]; - enum usb_role role; - struct cdns3_device *gadget_dev; - struct phy usb2_phy; - struct phy usb3_phy; - /* mutext used in workqueue*/ - struct mutex mutex; - enum usb_dr_mode dr_mode; - int role_override; + struct udevice *dev; + void __iomem *xhci_regs; + struct resource *xhci_res; + struct usbss_dev_register_block_type __iomem *dev_regs; + void __iomem *none_core_regs; + void __iomem *phy_regs; + void __iomem *otg_regs; + int irq; + struct cdns3_role_driver *roles[CDNS3_ROLE_END]; + enum cdns3_roles role; + struct udevice *host_dev; + struct udevice *gadget_dev; + struct clk *cdns3_clks[CDNS3_NUM_OF_CLKS]; + + int index; + struct list_head list; }; -int cdns3_hw_role_switch(struct cdns3 *cdns); +static inline struct cdns3_role_driver *cdns3_role(struct cdns3 *cdns) +{ + WARN_ON(cdns->role >= CDNS3_ROLE_END || !cdns->roles[cdns->role]); + return cdns->roles[cdns->role]; +} -/** - * cdns3_bind - generic bind function - * @parent - pointer to parent udevice of which cdns3 USB controller - * node is child of - * - * return 0 on success, negative errno otherwise - */ -int cdns3_bind(struct udevice *dev); -#endif /* __LINUX_CDNS3_CORE_H */ +static inline int cdns3_role_start(struct cdns3 *cdns, enum cdns3_roles role) +{ + if (role >= CDNS3_ROLE_END) + return 0; + + if (!cdns->roles[role]) + return -ENXIO; + + cdns->role = role; + return cdns->roles[role]->start(cdns); +} + +static inline void cdns3_role_stop(struct cdns3 *cdns) +{ + enum cdns3_roles role = cdns->role; + + if (role == CDNS3_ROLE_END) + return; + + cdns->roles[role]->stop(cdns); + cdns->role = CDNS3_ROLE_END; +} + +static inline void cdns3_role_irq_handler(struct cdns3 *cdns) +{ + enum cdns3_roles role = cdns->role; + + if (role == CDNS3_ROLE_END) + return; + + cdns->roles[role]->irq(cdns); +} + +int cdns3_init(struct cdns3 *cdns); +void cdns3_exit(struct cdns3 *cdns); + +#endif /* __DRIVERS_USB_CDNS3_CORE_H */ diff --git a/drivers/usb/cdns3/debug.h b/drivers/usb/cdns3/debug.h deleted file mode 100644 index 0b4673a3a61..00000000000 --- a/drivers/usb/cdns3/debug.h +++ /dev/null @@ -1,162 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Cadence USBSS DRD Driver. - * Debug header file. - * - * Copyright (C) 2018-2019 Cadence. - * - * Author: Pawel Laszczak - */ -#ifndef __LINUX_CDNS3_DEBUG -#define __LINUX_CDNS3_DEBUG - -#include "core.h" -#include "gadget.h" - -static inline char *cdns3_decode_usb_irq(char *str, - enum usb_device_speed speed, - u32 usb_ists) -{ - int ret; - - ret = sprintf(str, "IRQ %08x = ", usb_ists); - - if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) { - ret += sprintf(str + ret, "Connection %s\n", - usb_speed_string(speed)); - } - if (usb_ists & USB_ISTS_DIS2I || usb_ists & USB_ISTS_DISI) - ret += sprintf(str + ret, "Disconnection "); - if (usb_ists & USB_ISTS_L2ENTI) - ret += sprintf(str + ret, "suspended "); - if (usb_ists & USB_ISTS_L1ENTI) - ret += sprintf(str + ret, "L1 enter "); - if (usb_ists & USB_ISTS_L1EXTI) - ret += sprintf(str + ret, "L1 exit "); - if (usb_ists & USB_ISTS_L2ENTI) - ret += sprintf(str + ret, "L2 enter "); - if (usb_ists & USB_ISTS_L2EXTI) - ret += sprintf(str + ret, "L2 exit "); - if (usb_ists & USB_ISTS_U3EXTI) - ret += sprintf(str + ret, "U3 exit "); - if (usb_ists & USB_ISTS_UWRESI) - ret += sprintf(str + ret, "Warm Reset "); - if (usb_ists & USB_ISTS_UHRESI) - ret += sprintf(str + ret, "Hot Reset "); - if (usb_ists & USB_ISTS_U2RESI) - ret += sprintf(str + ret, "Reset"); - - return str; -} - -static inline char *cdns3_decode_ep_irq(char *str, - u32 ep_sts, - const char *ep_name) -{ - int ret; - - ret = sprintf(str, "IRQ for %s: %08x ", ep_name, ep_sts); - - if (ep_sts & EP_STS_SETUP) - ret += sprintf(str + ret, "SETUP "); - if (ep_sts & EP_STS_IOC) - ret += sprintf(str + ret, "IOC "); - if (ep_sts & EP_STS_ISP) - ret += sprintf(str + ret, "ISP "); - if (ep_sts & EP_STS_DESCMIS) - ret += sprintf(str + ret, "DESCMIS "); - if (ep_sts & EP_STS_STREAMR) - ret += sprintf(str + ret, "STREAMR "); - if (ep_sts & EP_STS_MD_EXIT) - ret += sprintf(str + ret, "MD_EXIT "); - if (ep_sts & EP_STS_TRBERR) - ret += sprintf(str + ret, "TRBERR "); - if (ep_sts & EP_STS_NRDY) - ret += sprintf(str + ret, "NRDY "); - if (ep_sts & EP_STS_PRIME) - ret += sprintf(str + ret, "PRIME "); - if (ep_sts & EP_STS_SIDERR) - ret += sprintf(str + ret, "SIDERRT "); - if (ep_sts & EP_STS_OUTSMM) - ret += sprintf(str + ret, "OUTSMM "); - if (ep_sts & EP_STS_ISOERR) - ret += sprintf(str + ret, "ISOERR "); - if (ep_sts & EP_STS_IOT) - ret += sprintf(str + ret, "IOT "); - - return str; -} - -static inline char *cdns3_decode_epx_irq(char *str, - char *ep_name, - u32 ep_sts) -{ - return cdns3_decode_ep_irq(str, ep_sts, ep_name); -} - -static inline char *cdns3_decode_ep0_irq(char *str, - int dir, - u32 ep_sts) -{ - return cdns3_decode_ep_irq(str, ep_sts, - dir ? "ep0IN" : "ep0OUT"); -} - -/** - * Debug a transfer ring. - * - * Prints out all TRBs in the endpoint ring, even those after the Link TRB. - *. - */ -static inline char *cdns3_dbg_ring(struct cdns3_endpoint *priv_ep, - struct cdns3_trb *ring, char *str) -{ - dma_addr_t addr = priv_ep->trb_pool_dma; - struct cdns3_trb *trb; - int trb_per_sector; - int ret = 0; - int i; - - trb_per_sector = GET_TRBS_PER_SEGMENT(priv_ep->type); - - trb = &priv_ep->trb_pool[priv_ep->dequeue]; - ret += sprintf(str + ret, "\n\t\tRing contents for %s:", priv_ep->name); - - ret += sprintf(str + ret, - "\n\t\tRing deq index: %d, trb: %p (virt), 0x%llx (dma)\n", - priv_ep->dequeue, trb, - (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb)); - - trb = &priv_ep->trb_pool[priv_ep->enqueue]; - ret += sprintf(str + ret, - "\t\tRing enq index: %d, trb: %p (virt), 0x%llx (dma)\n", - priv_ep->enqueue, trb, - (unsigned long long)cdns3_trb_virt_to_dma(priv_ep, trb)); - - ret += sprintf(str + ret, - "\t\tfree trbs: %d, CCS=%d, PCS=%d\n", - priv_ep->free_trbs, priv_ep->ccs, priv_ep->pcs); - - if (trb_per_sector > TRBS_PER_SEGMENT) - trb_per_sector = TRBS_PER_SEGMENT; - - if (trb_per_sector > TRBS_PER_SEGMENT) { - sprintf(str + ret, "\t\tTo big transfer ring %d\n", - trb_per_sector); - return str; - } - - for (i = 0; i < trb_per_sector; ++i) { - trb = &ring[i]; - ret += sprintf(str + ret, - "\t\t@%pad %08x %08x %08x\n", &addr, - le32_to_cpu(trb->buffer), - le32_to_cpu(trb->length), - le32_to_cpu(trb->control)); - addr += sizeof(*trb); - } - - return str; -} - -#endif /*__LINUX_CDNS3_DEBUG*/ diff --git a/drivers/usb/cdns3/dev-regs-macro.h b/drivers/usb/cdns3/dev-regs-macro.h new file mode 100644 index 00000000000..e09d5c28ad1 --- /dev/null +++ b/drivers/usb/cdns3/dev-regs-macro.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com + * Copyright 2019 NXP + */ + +#ifndef __REG_USBSS_DEV_ADDR_MAP_MACRO_H__ +#define __REG_USBSS_DEV_ADDR_MAP_MACRO_H__ + +/* macros for field CFGRST */ +#define USB_CONF__CFGRST__MASK 0x00000001U +#define USB_CONF__CFGSET__MASK 0x00000002U +#define USB_CONF__USB3DIS__MASK 0x00000008U +#define USB_CONF__DEVEN__MASK 0x00004000U +#define USB_CONF__DEVDS__MASK 0x00008000U +#define USB_CONF__L1EN__MASK 0x00010000U +#define USB_CONF__L1DS__MASK 0x00020000U +#define USB_CONF__CLK2OFFDS__MASK 0x00080000U +#define USB_CONF__U1EN__MASK 0x01000000U +#define USB_CONF__U1DS__MASK 0x02000000U +#define USB_CONF__U2EN__MASK 0x04000000U +#define USB_CONF__U2DS__MASK 0x08000000U + +/* macros for field CFGSTS */ +#define USB_STS__CFGSTS__MASK 0x00000001U +#define USB_STS__USBSPEED__READ(src) (((u32)(src) & 0x00000070U) >> 4) + +/* macros for field ENDIAN_MIRROR */ +#define USB_STS__LPMST__READ(src) (((u32)(src) & 0x000c0000U) >> 18) + +/* macros for field USB2CONS */ +#define USB_STS__U1ENS__MASK 0x01000000U +#define USB_STS__U2ENS__MASK 0x02000000U +#define USB_STS__LST__READ(src) (((u32)(src) & 0x3c000000U) >> 26) + +/* macros for field SET_ADDR */ +#define USB_CMD__SET_ADDR__MASK 0x00000001U +#define USB_CMD__STMODE 0x00000200U +#define USB_CMD__TMODE_SEL(x) (x << 10) +#define USB_CMD__FADDR__WRITE(src) (((u32)(src) << 1) & 0x000000feU) + +/* macros for field CONIEN */ +#define USB_IEN__CONIEN__MASK 0x00000001U +#define USB_IEN__DISIEN__MASK 0x00000002U +#define USB_IEN__UWRESIEN__MASK 0x00000004U +#define USB_IEN__UHRESIEN__MASK 0x00000008U +#define USB_IEN__U3EXTIEN__MASK 0x00000020U +#define USB_IEN__CON2IEN__MASK 0x00010000U +#define USB_IEN__U2RESIEN__MASK 0x00040000U +#define USB_IEN__L2ENTIEN__MASK 0x00100000U +#define USB_IEN__L2EXTIEN__MASK 0x00200000U + +/* macros for field CONI */ +#define USB_ISTS__CONI__SHIFT 0 +#define USB_ISTS__DISI__SHIFT 1 +#define USB_ISTS__UWRESI__SHIFT 2 +#define USB_ISTS__UHRESI__SHIFT 3 +#define USB_ISTS__U3EXTI__SHIFT 5 +#define USB_ISTS__CON2I__SHIFT 16 +#define USB_ISTS__DIS2I__SHIFT 17 +#define USB_ISTS__DIS2I__MASK 0x00020000U +#define USB_ISTS__U2RESI__SHIFT 18 +#define USB_ISTS__L2ENTI__SHIFT 20 +#define USB_ISTS__L2EXTI__SHIFT 21 + +/* macros for field TRADDR */ +#define EP_TRADDR__TRADDR__WRITE(src) ((u32)(src) & 0xffffffffU) + +/* macros for field ENABLE */ +#define EP_CFG__ENABLE__MASK 0x00000001U +#define EP_CFG__EPTYPE__WRITE(src) (((u32)(src) << 1) & 0x00000006U) +#define EP_CFG__MAXBURST__WRITE(src) (((u32)(src) << 8) & 0x00000f00U) +#define EP_CFG__MAXPKTSIZE__WRITE(src) (((u32)(src) << 16) & 0x07ff0000U) +#define EP_CFG__BUFFERING__WRITE(src) (((u32)(src) << 27) & 0xf8000000U) + +/* macros for field EPRST */ +#define EP_CMD__EPRST__MASK 0x00000001U +#define EP_CMD__SSTALL__MASK 0x00000002U +#define EP_CMD__CSTALL__MASK 0x00000004U +#define EP_CMD__ERDY__MASK 0x00000008U +#define EP_CMD__REQ_CMPL__MASK 0x00000020U +#define EP_CMD__DRDY__MASK 0x00000040U +#define EP_CMD__DFLUSH__MASK 0x00000080U + +/* macros for field SETUP */ +#define EP_STS__SETUP__MASK 0x00000001U +#define EP_STS__STALL__MASK 0x00000002U +#define EP_STS__IOC__MASK 0x00000004U +#define EP_STS__ISP__MASK 0x00000008U +#define EP_STS__DESCMIS__MASK 0x00000010U +#define EP_STS__TRBERR__MASK 0x00000080U +#define EP_STS__NRDY__MASK 0x00000100U +#define EP_STS__DBUSY__MASK 0x00000200U +#define EP_STS__BUFFEMPTY__MASK 0x00000400U +#define EP_STS__OUTSMM__MASK 0x00004000U +#define EP_STS__ISOERR__MASK 0x00008000U + +/* macros for field SETUPEN */ +#define EP_STS_EN__SETUPEN__MASK 0x00000001U +#define EP_STS_EN__DESCMISEN__MASK 0x00000010U +#define EP_STS_EN__TRBERREN__MASK 0x00000080U + +/* macros for field EOUTEN0 */ +#define EP_IEN__EOUTEN0__MASK 0x00000001U +#define EP_IEN__EINEN0__MASK 0x00010000U + +/* macros for field EOUT0 */ +#define EP_ISTS__EOUT0__MASK 0x00000001U +#define EP_ISTS__EIN0__MASK 0x00010000U + +/* macros for field LFPS_MIN_DET_U1_EXIT */ +#define DBG_LINK1__LFPS_MIN_GEN_U1_EXIT__WRITE(src) \ + (((u32)(src)\ + << 8) & 0x0000ff00U) +#define DBG_LINK1__LFPS_MIN_GEN_U1_EXIT_SET__MASK 0x02000000U + +#endif /* __REG_USBSS_DEV_ADDR_MAP_MACRO_H__ */ diff --git a/drivers/usb/cdns3/dev-regs-map.h b/drivers/usb/cdns3/dev-regs-map.h new file mode 100644 index 00000000000..c2d43068b78 --- /dev/null +++ b/drivers/usb/cdns3/dev-regs-map.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com + * Copyright 2019 NXP + */ + +#ifndef __REG_USBSS_DEV_ADDR_MAP_H__ +#define __REG_USBSS_DEV_ADDR_MAP_H__ + +#include "dev-regs-macro.h" + +struct usbss_dev_register_block_type { + u32 usb_conf; /* 0x0 - 0x4 */ + u32 usb_sts; /* 0x4 - 0x8 */ + u32 usb_cmd; /* 0x8 - 0xc */ + u32 usb_iptn; /* 0xc - 0x10 */ + u32 usb_lpm; /* 0x10 - 0x14 */ + u32 usb_ien; /* 0x14 - 0x18 */ + u32 usb_ists; /* 0x18 - 0x1c */ + u32 ep_sel; /* 0x1c - 0x20 */ + u32 ep_traddr; /* 0x20 - 0x24 */ + u32 ep_cfg; /* 0x24 - 0x28 */ + u32 ep_cmd; /* 0x28 - 0x2c */ + u32 ep_sts; /* 0x2c - 0x30 */ + u32 ep_sts_sid; /* 0x30 - 0x34 */ + u32 ep_sts_en; /* 0x34 - 0x38 */ + u32 drbl; /* 0x38 - 0x3c */ + u32 ep_ien; /* 0x3c - 0x40 */ + u32 ep_ists; /* 0x40 - 0x44 */ + u32 usb_pwr; /* 0x44 - 0x48 */ + u32 usb_conf2; /* 0x48 - 0x4c */ + u32 usb_cap1; /* 0x4c - 0x50 */ + u32 usb_cap2; /* 0x50 - 0x54 */ + u32 usb_cap3; /* 0x54 - 0x58 */ + u32 usb_cap4; /* 0x58 - 0x5c */ + u32 usb_cap5; /* 0x5c - 0x60 */ + u32 PAD2_73; /* 0x60 - 0x64 */ + u32 usb_cpkt1; /* 0x64 - 0x68 */ + u32 usb_cpkt2; /* 0x68 - 0x6c */ + u32 usb_cpkt3; /* 0x6c - 0x70 */ + char pad__0[0x90]; /* 0x70 - 0x100 */ + u32 PAD2_78; /* 0x100 - 0x104 */ + u32 dbg_link1; /* 0x104 - 0x108 */ + u32 PAD2_80; /* 0x108 - 0x10c */ + u32 PAD2_81; /* 0x10c - 0x110 */ + u32 PAD2_82; /* 0x110 - 0x114 */ + u32 PAD2_83; /* 0x114 - 0x118 */ + u32 PAD2_84; /* 0x118 - 0x11c */ + u32 PAD2_85; /* 0x11c - 0x120 */ + u32 PAD2_86; /* 0x120 - 0x124 */ + u32 PAD2_87; /* 0x124 - 0x128 */ + u32 PAD2_88; /* 0x128 - 0x12c */ + u32 PAD2_89; /* 0x12c - 0x130 */ + u32 PAD2_90; /* 0x130 - 0x134 */ + u32 PAD2_91; /* 0x134 - 0x138 */ + u32 PAD2_92; /* 0x138 - 0x13c */ + u32 PAD2_93; /* 0x13c - 0x140 */ + u32 PAD2_94; /* 0x140 - 0x144 */ + u32 PAD2_95; /* 0x144 - 0x148 */ + u32 PAD2_96; /* 0x148 - 0x14c */ + u32 PAD2_97; /* 0x14c - 0x150 */ + u32 PAD2_98; /* 0x150 - 0x154 */ + u32 PAD2_99; /* 0x154 - 0x158 */ + u32 PAD2_100; /* 0x158 - 0x15c */ + u32 PAD2_101; /* 0x15c - 0x160 */ + u32 PAD2_102; /* 0x160 - 0x164 */ + u32 PAD2_103; /* 0x164 - 0x168 */ + u32 PAD2_104; /* 0x168 - 0x16c */ + u32 PAD2_105; /* 0x16c - 0x170 */ + u32 PAD2_106; /* 0x170 - 0x174 */ + u32 PAD2_107; /* 0x174 - 0x178 */ + u32 PAD2_108; /* 0x178 - 0x17c */ + u32 PAD2_109; /* 0x17c - 0x180 */ + u32 PAD2_110; /* 0x180 - 0x184 */ + u32 PAD2_111; /* 0x184 - 0x188 */ + u32 PAD2_112; /* 0x188 - 0x18c */ + char pad__1[0x20]; /* 0x18c - 0x1ac */ + u32 PAD2_114; /* 0x1ac - 0x1b0 */ + u32 PAD2_115; /* 0x1b0 - 0x1b4 */ + u32 PAD2_116; /* 0x1b4 - 0x1b8 */ + u32 PAD2_117; /* 0x1b8 - 0x1bc */ + u32 PAD2_118; /* 0x1bc - 0x1c0 */ + u32 PAD2_119; /* 0x1c0 - 0x1c4 */ + u32 PAD2_120; /* 0x1c4 - 0x1c8 */ + u32 PAD2_121; /* 0x1c8 - 0x1cc */ + u32 PAD2_122; /* 0x1cc - 0x1d0 */ + u32 PAD2_123; /* 0x1d0 - 0x1d4 */ + u32 PAD2_124; /* 0x1d4 - 0x1d8 */ + u32 PAD2_125; /* 0x1d8 - 0x1dc */ + u32 PAD2_126; /* 0x1dc - 0x1e0 */ + u32 PAD2_127; /* 0x1e0 - 0x1e4 */ + u32 PAD2_128; /* 0x1e4 - 0x1e8 */ + u32 PAD2_129; /* 0x1e8 - 0x1ec */ + u32 PAD2_130; /* 0x1ec - 0x1f0 */ + u32 PAD2_131; /* 0x1f0 - 0x1f4 */ + u32 PAD2_132; /* 0x1f4 - 0x1f8 */ + u32 PAD2_133; /* 0x1f8 - 0x1fc */ + u32 PAD2_134; /* 0x1fc - 0x200 */ + u32 PAD2_135; /* 0x200 - 0x204 */ + u32 PAD2_136; /* 0x204 - 0x208 */ + u32 PAD2_137; /* 0x208 - 0x20c */ + u32 PAD2_138; /* 0x20c - 0x210 */ + u32 PAD2_139; /* 0x210 - 0x214 */ + u32 PAD2_140; /* 0x214 - 0x218 */ + u32 PAD2_141; /* 0x218 - 0x21c */ + u32 PAD2_142; /* 0x21c - 0x220 */ + u32 PAD2_143; /* 0x220 - 0x224 */ + u32 PAD2_144; /* 0x224 - 0x228 */ + char pad__2[0xd8]; /* 0x228 - 0x300 */ + u32 dma_axi_ctrl; /* 0x300 - 0x304 */ + u32 PAD2_147; /* 0x304 - 0x308 */ + u32 PAD2_148; /* 0x308 - 0x30c */ + u32 PAD2_149; /* 0x30c - 0x310 */ + u32 PAD2_150; /* 0x310 - 0x314 */ +}; + +#endif /* __REG_USBSS_DEV_ADDR_MAP_H__ */ diff --git a/drivers/usb/cdns3/drd.c b/drivers/usb/cdns3/drd.c deleted file mode 100644 index 47874fec29e..00000000000 --- a/drivers/usb/cdns3/drd.c +++ /dev/null @@ -1,302 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Cadence USBSS DRD Driver. - * - * Copyright (C) 2018-2019 Cadence. - * Copyright (C) 2019 Texas Instruments - * - * Author: Pawel Laszczak - * Roger Quadros - * - * - */ -#include -#include -#include -#include -#include -#include - -#include "gadget.h" -#include "drd.h" -#include "core.h" - -#define readl_poll_timeout_atomic readl_poll_timeout -#define usleep_range(a, b) udelay((b)) -/** - * cdns3_set_mode - change mode of OTG Core - * @cdns: pointer to context structure - * @mode: selected mode from cdns_role - * - * Returns 0 on success otherwise negative errno - */ -int cdns3_set_mode(struct cdns3 *cdns, enum usb_dr_mode mode) -{ - int ret = 0; - u32 reg; - - switch (mode) { - case USB_DR_MODE_PERIPHERAL: - break; - case USB_DR_MODE_HOST: - break; - case USB_DR_MODE_OTG: - dev_dbg(cdns->dev, "Set controller to OTG mode\n"); - if (cdns->version == CDNS3_CONTROLLER_V1) { - reg = readl(&cdns->otg_v1_regs->override); - reg |= OVERRIDE_IDPULLUP; - writel(reg, &cdns->otg_v1_regs->override); - } else { - reg = readl(&cdns->otg_v0_regs->ctrl1); - reg |= OVERRIDE_IDPULLUP_V0; - writel(reg, &cdns->otg_v0_regs->ctrl1); - } - - /* - * Hardware specification says: "ID_VALUE must be valid within - * 50ms after idpullup is set to '1" so driver must wait - * 50ms before reading this pin. - */ - usleep_range(50000, 60000); - break; - default: - dev_err(cdns->dev, "Unsupported mode of operation %d\n", mode); - return -EINVAL; - } - - return ret; -} - -int cdns3_get_id(struct cdns3 *cdns) -{ - int id; - - id = readl(&cdns->otg_regs->sts) & OTGSTS_ID_VALUE; - dev_dbg(cdns->dev, "OTG ID: %d", id); - - return id; -} - -int cdns3_get_vbus(struct cdns3 *cdns) -{ - int vbus; - - vbus = !!(readl(&cdns->otg_regs->sts) & OTGSTS_VBUS_VALID); - dev_dbg(cdns->dev, "OTG VBUS: %d", vbus); - - return vbus; -} - -int cdns3_is_host(struct cdns3 *cdns) -{ - if (cdns->dr_mode == USB_DR_MODE_HOST) - return 1; - else if (!cdns3_get_id(cdns)) - return 1; - - return 0; -} - -int cdns3_is_device(struct cdns3 *cdns) -{ - if (cdns->dr_mode == USB_DR_MODE_PERIPHERAL) - return 1; - else if (cdns->dr_mode == USB_DR_MODE_OTG) - if (cdns3_get_id(cdns)) - return 1; - - return 0; -} - -/** - * cdns3_drd_switch_host - start/stop host - * @cdns: Pointer to controller context structure - * @on: 1 for start, 0 for stop - * - * Returns 0 on success otherwise negative errno - */ -int cdns3_drd_switch_host(struct cdns3 *cdns, int on) -{ - int ret, val; - u32 reg = OTGCMD_OTG_DIS; - - /* switch OTG core */ - if (on) { - writel(OTGCMD_HOST_BUS_REQ | reg, &cdns->otg_regs->cmd); - - dev_dbg(cdns->dev, "Waiting till Host mode is turned on\n"); - ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val, - val & OTGSTS_XHCI_READY, - 100000); - if (ret) { - dev_err(cdns->dev, "timeout waiting for xhci_ready\n"); - return ret; - } - } else { - writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP | - OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF, - &cdns->otg_regs->cmd); - /* Waiting till H_IDLE state.*/ - readl_poll_timeout_atomic(&cdns->otg_regs->state, val, - !(val & OTGSTATE_HOST_STATE_MASK), - 2000000); - } - - return 0; -} - -/** - * cdns3_drd_switch_gadget - start/stop gadget - * @cdns: Pointer to controller context structure - * @on: 1 for start, 0 for stop - * - * Returns 0 on success otherwise negative errno - */ -int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on) -{ - int ret, val; - u32 reg = OTGCMD_OTG_DIS; - - /* switch OTG core */ - if (on) { - writel(OTGCMD_DEV_BUS_REQ | reg, &cdns->otg_regs->cmd); - - dev_dbg(cdns->dev, "Waiting till Device mode is turned on\n"); - - ret = readl_poll_timeout_atomic(&cdns->otg_regs->sts, val, - val & OTGSTS_DEV_READY, - 100000); - if (ret) { - dev_err(cdns->dev, "timeout waiting for dev_ready\n"); - return ret; - } - } else { - /* - * driver should wait at least 10us after disabling Device - * before turning-off Device (DEV_BUS_DROP) - */ - usleep_range(20, 30); - writel(OTGCMD_HOST_BUS_DROP | OTGCMD_DEV_BUS_DROP | - OTGCMD_DEV_POWER_OFF | OTGCMD_HOST_POWER_OFF, - &cdns->otg_regs->cmd); - /* Waiting till DEV_IDLE state.*/ - readl_poll_timeout_atomic(&cdns->otg_regs->state, val, - !(val & OTGSTATE_DEV_STATE_MASK), - 2000000); - } - - return 0; -} - -/** - * cdns3_init_otg_mode - initialize drd controller - * @cdns: Pointer to controller context structure - * - * Returns 0 on success otherwise negative errno - */ -static int cdns3_init_otg_mode(struct cdns3 *cdns) -{ - int ret = 0; - - /* clear all interrupts */ - writel(~0, &cdns->otg_regs->ivect); - - ret = cdns3_set_mode(cdns, USB_DR_MODE_OTG); - if (ret) - return ret; - - return ret; -} - -/** - * cdns3_drd_update_mode - initialize mode of operation - * @cdns: Pointer to controller context structure - * - * Returns 0 on success otherwise negative errno - */ -int cdns3_drd_update_mode(struct cdns3 *cdns) -{ - int ret = 0; - - switch (cdns->dr_mode) { - case USB_DR_MODE_PERIPHERAL: - ret = cdns3_set_mode(cdns, USB_DR_MODE_PERIPHERAL); - break; - case USB_DR_MODE_HOST: - ret = cdns3_set_mode(cdns, USB_DR_MODE_HOST); - break; - case USB_DR_MODE_OTG: - ret = cdns3_init_otg_mode(cdns); - break; - default: - dev_err(cdns->dev, "Unsupported mode of operation %d\n", - cdns->dr_mode); - return -EINVAL; - } - - return ret; -} - -int cdns3_drd_init(struct cdns3 *cdns) -{ - void __iomem *regs; - int ret = 0; - u32 state; - - regs = dev_remap_addr_name(cdns->dev, "otg"); - if (!regs) - return -EINVAL; - - /* Detection of DRD version. Controller has been released - * in two versions. Both are similar, but they have same changes - * in register maps. - * The first register in old version is command register and it's read - * only, so driver should read 0 from it. On the other hand, in v1 - * the first register contains device ID number which is not set to 0. - * Driver uses this fact to detect the proper version of - * controller. - */ - cdns->otg_v0_regs = regs; - if (!readl(&cdns->otg_v0_regs->cmd)) { - cdns->version = CDNS3_CONTROLLER_V0; - cdns->otg_v1_regs = NULL; - cdns->otg_regs = regs; - writel(1, &cdns->otg_v0_regs->simulate); - dev_info(cdns->dev, "DRD version v0 (%08x)\n", - readl(&cdns->otg_v0_regs->version)); - } else { - cdns->otg_v0_regs = NULL; - cdns->otg_v1_regs = regs; - cdns->otg_regs = (void *)&cdns->otg_v1_regs->cmd; - cdns->version = CDNS3_CONTROLLER_V1; - writel(1, &cdns->otg_v1_regs->simulate); - dev_info(cdns->dev, "DRD version v1 (ID: %08x, rev: %08x)\n", - readl(&cdns->otg_v1_regs->did), - readl(&cdns->otg_v1_regs->rid)); - } - - state = OTGSTS_STRAP(readl(&cdns->otg_regs->sts)); - - /* Update dr_mode according to STRAP configuration. */ - cdns->dr_mode = USB_DR_MODE_OTG; - if (state == OTGSTS_STRAP_HOST) { - dev_dbg(cdns->dev, "Controller strapped to HOST\n"); - cdns->dr_mode = USB_DR_MODE_HOST; - } else if (state == OTGSTS_STRAP_GADGET) { - dev_dbg(cdns->dev, "Controller strapped to PERIPHERAL\n"); - cdns->dr_mode = USB_DR_MODE_PERIPHERAL; - } - - state = readl(&cdns->otg_regs->sts); - if (OTGSTS_OTG_NRDY(state) != 0) { - dev_err(cdns->dev, "Cadence USB3 OTG device not ready\n"); - return -ENODEV; - } - - return ret; -} - -int cdns3_drd_exit(struct cdns3 *cdns) -{ - return 0; -} diff --git a/drivers/usb/cdns3/drd.h b/drivers/usb/cdns3/drd.h deleted file mode 100644 index fffda7b43a4..00000000000 --- a/drivers/usb/cdns3/drd.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Cadence USB3 DRD header file. - * - * Copyright (C) 2018-2019 Cadence. - * - * Author: Pawel Laszczak - */ -#ifndef __LINUX_CDNS3_DRD -#define __LINUX_CDNS3_DRD - -#include -#include -#include -#include "core.h" - -/* DRD register interface for version v1. */ -struct cdns3_otg_regs { - __le32 did; - __le32 rid; - __le32 capabilities; - __le32 reserved1; - __le32 cmd; - __le32 sts; - __le32 state; - __le32 reserved2; - __le32 ien; - __le32 ivect; - __le32 refclk; - __le32 tmr; - __le32 reserved3[4]; - __le32 simulate; - __le32 override; - __le32 susp_ctrl; - __le32 reserved4; - __le32 anasts; - __le32 adp_ramp_time; - __le32 ctrl1; - __le32 ctrl2; -}; - -/* DRD register interface for version v0. */ -struct cdns3_otg_legacy_regs { - __le32 cmd; - __le32 sts; - __le32 state; - __le32 refclk; - __le32 ien; - __le32 ivect; - __le32 reserved1[3]; - __le32 tmr; - __le32 reserved2[2]; - __le32 version; - __le32 capabilities; - __le32 reserved3[2]; - __le32 simulate; - __le32 reserved4[5]; - __le32 ctrl1; -}; - -/* - * Common registers interface for both version of DRD. - */ -struct cdns3_otg_common_regs { - __le32 cmd; - __le32 sts; - __le32 state; - __le32 different1; - __le32 ien; - __le32 ivect; -}; - -/* CDNS_RID - bitmasks */ -#define CDNS_RID(p) ((p) & GENMASK(15, 0)) - -/* CDNS_VID - bitmasks */ -#define CDNS_DID(p) ((p) & GENMASK(31, 0)) - -/* OTGCMD - bitmasks */ -/* "Request the bus for Device mode. */ -#define OTGCMD_DEV_BUS_REQ BIT(0) -/* Request the bus for Host mode */ -#define OTGCMD_HOST_BUS_REQ BIT(1) -/* Enable OTG mode. */ -#define OTGCMD_OTG_EN BIT(2) -/* Disable OTG mode */ -#define OTGCMD_OTG_DIS BIT(3) -/*"Configure OTG as A-Device. */ -#define OTGCMD_A_DEV_EN BIT(4) -/*"Configure OTG as A-Device. */ -#define OTGCMD_A_DEV_DIS BIT(5) -/* Drop the bus for Device mod e. */ -#define OTGCMD_DEV_BUS_DROP BIT(8) -/* Drop the bus for Host mode*/ -#define OTGCMD_HOST_BUS_DROP BIT(9) -/* Power Down USBSS-DEV. */ -#define OTGCMD_DEV_POWER_OFF BIT(11) -/* Power Down CDNSXHCI. */ -#define OTGCMD_HOST_POWER_OFF BIT(12) - -/* OTGIEN - bitmasks */ -/* ID change interrupt enable */ -#define OTGIEN_ID_CHANGE_INT BIT(0) -/* Vbusvalid fall detected interrupt enable.*/ -#define OTGIEN_VBUSVALID_RISE_INT BIT(4) -/* Vbusvalid fall detected interrupt enable */ -#define OTGIEN_VBUSVALID_FALL_INT BIT(5) - -/* OTGSTS - bitmasks */ -/* - * Current value of the ID pin. It is only valid when idpullup in - * OTGCTRL1_TYPE register is set to '1'. - */ -#define OTGSTS_ID_VALUE BIT(0) -/* Current value of the vbus_valid */ -#define OTGSTS_VBUS_VALID BIT(1) -/* Current value of the b_sess_vld */ -#define OTGSTS_SESSION_VALID BIT(2) -/*Device mode is active*/ -#define OTGSTS_DEV_ACTIVE BIT(3) -/* Host mode is active. */ -#define OTGSTS_HOST_ACTIVE BIT(4) -/* OTG Controller not ready. */ -#define OTGSTS_OTG_NRDY_MASK BIT(11) -#define OTGSTS_OTG_NRDY(p) ((p) & OTGSTS_OTG_NRDY_MASK) -/* - * Value of the strap pins. - * 000 - no default configuration - * 010 - Controller initiall configured as Host - * 100 - Controller initially configured as Device - */ -#define OTGSTS_STRAP(p) (((p) & GENMASK(14, 12)) >> 12) -#define OTGSTS_STRAP_NO_DEFAULT_CFG 0x00 -#define OTGSTS_STRAP_HOST_OTG 0x01 -#define OTGSTS_STRAP_HOST 0x02 -#define OTGSTS_STRAP_GADGET 0x04 -/* Host mode is turned on. */ -#define OTGSTS_XHCI_READY BIT(26) -/* "Device mode is turned on .*/ -#define OTGSTS_DEV_READY BIT(27) - -/* OTGSTATE- bitmasks */ -#define OTGSTATE_DEV_STATE_MASK GENMASK(2, 0) -#define OTGSTATE_HOST_STATE_MASK GENMASK(5, 3) -#define OTGSTATE_HOST_STATE_IDLE 0x0 -#define OTGSTATE_HOST_STATE_VBUS_FALL 0x7 -#define OTGSTATE_HOST_STATE(p) (((p) & OTGSTATE_HOST_STATE_MASK) >> 3) - -/* OTGREFCLK - bitmasks */ -#define OTGREFCLK_STB_CLK_SWITCH_EN BIT(31) - -/* OVERRIDE - bitmasks */ -#define OVERRIDE_IDPULLUP BIT(0) -/* Only for CDNS3_CONTROLLER_V0 version */ -#define OVERRIDE_IDPULLUP_V0 BIT(24) - -int cdns3_is_host(struct cdns3 *cdns); -int cdns3_is_device(struct cdns3 *cdns); -int cdns3_get_id(struct cdns3 *cdns); -int cdns3_get_vbus(struct cdns3 *cdns); -int cdns3_drd_init(struct cdns3 *cdns); -int cdns3_drd_exit(struct cdns3 *cdns); -int cdns3_drd_update_mode(struct cdns3 *cdns); -int cdns3_drd_switch_gadget(struct cdns3 *cdns, int on); -int cdns3_drd_switch_host(struct cdns3 *cdns, int on); - -#endif /* __LINUX_CDNS3_DRD */ diff --git a/drivers/usb/cdns3/ep0.c b/drivers/usb/cdns3/ep0.c deleted file mode 100644 index acff79ae1ca..00000000000 --- a/drivers/usb/cdns3/ep0.c +++ /dev/null @@ -1,920 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Cadence USBSS DRD Driver - gadget side. - * - * Copyright (C) 2018 Cadence Design Systems. - * Copyright (C) 2017-2018 NXP - * - * Authors: Pawel Jez , - * Pawel Laszczak - * Peter Chen - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "gadget.h" -#include "trace.h" - -#define readl_poll_timeout_atomic readl_poll_timeout -#define usleep_range(a, b) udelay((b)) - -static struct usb_endpoint_descriptor cdns3_gadget_ep0_desc = { - .bLength = USB_DT_ENDPOINT_SIZE, - .bDescriptorType = USB_DT_ENDPOINT, - .bmAttributes = USB_ENDPOINT_XFER_CONTROL, -}; - -/** - * cdns3_ep0_run_transfer - Do transfer on default endpoint hardware - * @priv_dev: extended gadget object - * @dma_addr: physical address where data is/will be stored - * @length: data length - * @erdy: set it to 1 when ERDY packet should be sent - - * exit from flow control state - */ -static void cdns3_ep0_run_transfer(struct cdns3_device *priv_dev, - dma_addr_t dma_addr, - unsigned int length, int erdy, int zlp) -{ - struct cdns3_usb_regs __iomem *regs = priv_dev->regs; - struct cdns3_endpoint *priv_ep = priv_dev->eps[0]; - - priv_ep->trb_pool[0].buffer = TRB_BUFFER(dma_addr); - priv_ep->trb_pool[0].length = TRB_LEN(length); - - if (zlp) { - priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_TYPE(TRB_NORMAL); - priv_ep->trb_pool[1].buffer = TRB_BUFFER(dma_addr); - priv_ep->trb_pool[1].length = TRB_LEN(0); - priv_ep->trb_pool[1].control = TRB_CYCLE | TRB_IOC | - TRB_TYPE(TRB_NORMAL); - } else { - priv_ep->trb_pool[0].control = TRB_CYCLE | TRB_IOC | - TRB_TYPE(TRB_NORMAL); - priv_ep->trb_pool[1].control = 0; - } - - /* Flush both TRBs */ - flush_dcache_range((unsigned long)priv_ep->trb_pool, - (unsigned long)priv_ep->trb_pool + - ROUND(sizeof(struct cdns3_trb) * 2, - CONFIG_SYS_CACHELINE_SIZE)); - - trace_cdns3_prepare_trb(priv_ep, priv_ep->trb_pool); - - cdns3_select_ep(priv_dev, priv_dev->ep0_data_dir); - - writel(EP_STS_TRBERR, ®s->ep_sts); - writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma), ®s->ep_traddr); - trace_cdns3_doorbell_ep0(priv_dev->ep0_data_dir ? "ep0in" : "ep0out", - readl(®s->ep_traddr)); - - /* TRB should be prepared before starting transfer. */ - writel(EP_CMD_DRDY, ®s->ep_cmd); - - /* Resume controller before arming transfer. */ - __cdns3_gadget_wakeup(priv_dev); - - if (erdy) - writel(EP_CMD_ERDY, &priv_dev->regs->ep_cmd); -} - -/** - * cdns3_ep0_delegate_req - Returns status of handling setup packet - * Setup is handled by gadget driver - * @priv_dev: extended gadget object - * @ctrl_req: pointer to received setup packet - * - * Returns zero on success or negative value on failure - */ -static int cdns3_ep0_delegate_req(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl_req) -{ - int ret; - - spin_unlock(&priv_dev->lock); - priv_dev->setup_pending = 1; - ret = priv_dev->gadget_driver->setup(&priv_dev->gadget, ctrl_req); - priv_dev->setup_pending = 0; - spin_lock(&priv_dev->lock); - return ret; -} - -static void cdns3_prepare_setup_packet(struct cdns3_device *priv_dev) -{ - priv_dev->ep0_data_dir = 0; - priv_dev->ep0_stage = CDNS3_SETUP_STAGE; - cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma, - sizeof(struct usb_ctrlrequest), 0, 0); -} - -static void cdns3_ep0_complete_setup(struct cdns3_device *priv_dev, - u8 send_stall, u8 send_erdy) -{ - struct cdns3_endpoint *priv_ep = priv_dev->eps[0]; - struct usb_request *request; - - request = cdns3_next_request(&priv_ep->pending_req_list); - if (request) - list_del_init(&request->list); - - if (send_stall) { - trace_cdns3_halt(priv_ep, send_stall, 0); - /* set_stall on ep0 */ - cdns3_select_ep(priv_dev, 0x00); - writel(EP_CMD_SSTALL, &priv_dev->regs->ep_cmd); - } else { - cdns3_prepare_setup_packet(priv_dev); - } - - priv_dev->ep0_stage = CDNS3_SETUP_STAGE; - writel((send_erdy ? EP_CMD_ERDY : 0) | EP_CMD_REQ_CMPL, - &priv_dev->regs->ep_cmd); - - cdns3_allow_enable_l1(priv_dev, 1); -} - -/** - * cdns3_req_ep0_set_configuration - Handling of SET_CONFIG standard USB request - * @priv_dev: extended gadget object - * @ctrl_req: pointer to received setup packet - * - * Returns 0 if success, USB_GADGET_DELAYED_STATUS on deferred status stage, - * error code on error - */ -static int cdns3_req_ep0_set_configuration(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl_req) -{ - enum usb_device_state device_state = priv_dev->gadget.state; - struct cdns3_endpoint *priv_ep; - u32 config = le16_to_cpu(ctrl_req->wValue); - int result = 0; - int i; - - switch (device_state) { - case USB_STATE_ADDRESS: - /* Configure non-control EPs */ - for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) { - priv_ep = priv_dev->eps[i]; - if (!priv_ep) - continue; - - if (priv_ep->flags & EP_CLAIMED) - cdns3_ep_config(priv_ep); - } - - result = cdns3_ep0_delegate_req(priv_dev, ctrl_req); - - if (result) - return result; - - if (config) { - cdns3_set_hw_configuration(priv_dev); - } else { - cdns3_hw_reset_eps_config(priv_dev); - usb_gadget_set_state(&priv_dev->gadget, - USB_STATE_ADDRESS); - } - break; - case USB_STATE_CONFIGURED: - result = cdns3_ep0_delegate_req(priv_dev, ctrl_req); - - if (!config && !result) { - cdns3_hw_reset_eps_config(priv_dev); - usb_gadget_set_state(&priv_dev->gadget, - USB_STATE_ADDRESS); - } - break; - default: - result = -EINVAL; - } - - return result; -} - -/** - * cdns3_req_ep0_set_address - Handling of SET_ADDRESS standard USB request - * @priv_dev: extended gadget object - * @ctrl_req: pointer to received setup packet - * - * Returns 0 if success, error code on error - */ -static int cdns3_req_ep0_set_address(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl_req) -{ - enum usb_device_state device_state = priv_dev->gadget.state; - u32 reg; - u32 addr; - - addr = le16_to_cpu(ctrl_req->wValue); - - if (addr > USB_DEVICE_MAX_ADDRESS) { - dev_err(priv_dev->dev, - "Device address (%d) cannot be greater than %d\n", - addr, USB_DEVICE_MAX_ADDRESS); - return -EINVAL; - } - - if (device_state == USB_STATE_CONFIGURED) { - dev_err(priv_dev->dev, - "can't set_address from configured state\n"); - return -EINVAL; - } - - reg = readl(&priv_dev->regs->usb_cmd); - - writel(reg | USB_CMD_FADDR(addr) | USB_CMD_SET_ADDR, - &priv_dev->regs->usb_cmd); - - usb_gadget_set_state(&priv_dev->gadget, - (addr ? USB_STATE_ADDRESS : USB_STATE_DEFAULT)); - - return 0; -} - -/** - * cdns3_req_ep0_get_status - Handling of GET_STATUS standard USB request - * @priv_dev: extended gadget object - * @ctrl_req: pointer to received setup packet - * - * Returns 0 if success, error code on error - */ -static int cdns3_req_ep0_get_status(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl) -{ - __le16 *response_pkt; - u16 usb_status = 0; - u32 recip; - - recip = ctrl->bRequestType & USB_RECIP_MASK; - - switch (recip) { - case USB_RECIP_DEVICE: - /* self powered */ - if (priv_dev->is_selfpowered) - usb_status = BIT(USB_DEVICE_SELF_POWERED); - - if (priv_dev->wake_up_flag) - usb_status |= BIT(USB_DEVICE_REMOTE_WAKEUP); - - if (priv_dev->gadget.speed != USB_SPEED_SUPER) - break; - - if (priv_dev->u1_allowed) - usb_status |= BIT(USB_DEV_STAT_U1_ENABLED); - - if (priv_dev->u2_allowed) - usb_status |= BIT(USB_DEV_STAT_U2_ENABLED); - - break; - case USB_RECIP_INTERFACE: - return cdns3_ep0_delegate_req(priv_dev, ctrl); - case USB_RECIP_ENDPOINT: - /* check if endpoint is stalled */ - cdns3_select_ep(priv_dev, ctrl->wIndex); - if (EP_STS_STALL(readl(&priv_dev->regs->ep_sts))) - usb_status = BIT(USB_ENDPOINT_HALT); - break; - default: - return -EINVAL; - } - - response_pkt = (__le16 *)priv_dev->setup_buf; - *response_pkt = cpu_to_le16(usb_status); - - /* Flush setup response */ - flush_dcache_range((unsigned long)priv_dev->setup_buf, - (unsigned long)priv_dev->setup_buf + - ROUND(sizeof(struct usb_ctrlrequest), - CONFIG_SYS_CACHELINE_SIZE)); - - cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma, - sizeof(*response_pkt), 1, 0); - return 0; -} - -static int cdns3_ep0_feature_handle_device(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl, - int set) -{ - enum usb_device_state state; - enum usb_device_speed speed; - int ret = 0; - u16 tmode; - - state = priv_dev->gadget.state; - speed = priv_dev->gadget.speed; - - switch (ctrl->wValue) { - case USB_DEVICE_REMOTE_WAKEUP: - priv_dev->wake_up_flag = !!set; - break; - case USB_DEVICE_U1_ENABLE: - if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER) - return -EINVAL; - - priv_dev->u1_allowed = !!set; - break; - case USB_DEVICE_U2_ENABLE: - if (state != USB_STATE_CONFIGURED || speed != USB_SPEED_SUPER) - return -EINVAL; - - priv_dev->u2_allowed = !!set; - break; - case USB_DEVICE_LTM_ENABLE: - ret = -EINVAL; - break; - case USB_DEVICE_TEST_MODE: - if (state != USB_STATE_CONFIGURED || speed > USB_SPEED_HIGH) - return -EINVAL; - - tmode = le16_to_cpu(ctrl->wIndex); - - if (!set || (tmode & 0xff) != 0) - return -EINVAL; - - switch (tmode >> 8) { - case TEST_J: - case TEST_K: - case TEST_SE0_NAK: - case TEST_PACKET: - cdns3_ep0_complete_setup(priv_dev, 0, 1); - /** - * Little delay to give the controller some time - * for sending status stage. - * This time should be less then 3ms. - */ - usleep_range(1000, 2000); - cdns3_set_register_bit(&priv_dev->regs->usb_cmd, - USB_CMD_STMODE | - USB_STS_TMODE_SEL(tmode - 1)); - break; - default: - ret = -EINVAL; - } - break; - default: - ret = -EINVAL; - } - - return ret; -} - -static int cdns3_ep0_feature_handle_intf(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl, - int set) -{ - u32 wValue; - int ret = 0; - - wValue = le16_to_cpu(ctrl->wValue); - - switch (wValue) { - case USB_INTRF_FUNC_SUSPEND: - break; - default: - ret = -EINVAL; - } - - return ret; -} - -static int cdns3_ep0_feature_handle_endpoint(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl, - int set) -{ - struct cdns3_endpoint *priv_ep; - int ret = 0; - u8 index; - - if (le16_to_cpu(ctrl->wValue) != USB_ENDPOINT_HALT) - return -EINVAL; - - if (!(ctrl->wIndex & ~USB_DIR_IN)) - return 0; - - index = cdns3_ep_addr_to_index(ctrl->wIndex); - priv_ep = priv_dev->eps[index]; - - cdns3_select_ep(priv_dev, ctrl->wIndex); - - if (set) - __cdns3_gadget_ep_set_halt(priv_ep); - else if (!(priv_ep->flags & EP_WEDGE)) - ret = __cdns3_gadget_ep_clear_halt(priv_ep); - - cdns3_select_ep(priv_dev, 0x00); - - return ret; -} - -/** - * cdns3_req_ep0_handle_feature - - * Handling of GET/SET_FEATURE standard USB request - * - * @priv_dev: extended gadget object - * @ctrl_req: pointer to received setup packet - * @set: must be set to 1 for SET_FEATURE request - * - * Returns 0 if success, error code on error - */ -static int cdns3_req_ep0_handle_feature(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl, - int set) -{ - int ret = 0; - u32 recip; - - recip = ctrl->bRequestType & USB_RECIP_MASK; - - switch (recip) { - case USB_RECIP_DEVICE: - ret = cdns3_ep0_feature_handle_device(priv_dev, ctrl, set); - break; - case USB_RECIP_INTERFACE: - ret = cdns3_ep0_feature_handle_intf(priv_dev, ctrl, set); - break; - case USB_RECIP_ENDPOINT: - ret = cdns3_ep0_feature_handle_endpoint(priv_dev, ctrl, set); - break; - default: - return -EINVAL; - } - - return ret; -} - -/** - * cdns3_req_ep0_set_sel - Handling of SET_SEL standard USB request - * @priv_dev: extended gadget object - * @ctrl_req: pointer to received setup packet - * - * Returns 0 if success, error code on error - */ -static int cdns3_req_ep0_set_sel(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl_req) -{ - if (priv_dev->gadget.state < USB_STATE_ADDRESS) - return -EINVAL; - - if (ctrl_req->wLength != 6) { - dev_err(priv_dev->dev, "Set SEL should be 6 bytes, got %d\n", - ctrl_req->wLength); - return -EINVAL; - } - - cdns3_ep0_run_transfer(priv_dev, priv_dev->setup_dma, 6, 1, 0); - return 0; -} - -/** - * cdns3_req_ep0_set_isoch_delay - - * Handling of GET_ISOCH_DELAY standard USB request - * @priv_dev: extended gadget object - * @ctrl_req: pointer to received setup packet - * - * Returns 0 if success, error code on error - */ -static int cdns3_req_ep0_set_isoch_delay(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl_req) -{ - if (ctrl_req->wIndex || ctrl_req->wLength) - return -EINVAL; - - priv_dev->isoch_delay = ctrl_req->wValue; - - return 0; -} - -/** - * cdns3_ep0_standard_request - Handling standard USB requests - * @priv_dev: extended gadget object - * @ctrl_req: pointer to received setup packet - * - * Returns 0 if success, error code on error - */ -static int cdns3_ep0_standard_request(struct cdns3_device *priv_dev, - struct usb_ctrlrequest *ctrl_req) -{ - int ret; - - switch (ctrl_req->bRequest) { - case USB_REQ_SET_ADDRESS: - ret = cdns3_req_ep0_set_address(priv_dev, ctrl_req); - break; - case USB_REQ_SET_CONFIGURATION: - ret = cdns3_req_ep0_set_configuration(priv_dev, ctrl_req); - break; - case USB_REQ_GET_STATUS: - ret = cdns3_req_ep0_get_status(priv_dev, ctrl_req); - break; - case USB_REQ_CLEAR_FEATURE: - ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 0); - break; - case USB_REQ_SET_FEATURE: - ret = cdns3_req_ep0_handle_feature(priv_dev, ctrl_req, 1); - break; - case USB_REQ_SET_SEL: - ret = cdns3_req_ep0_set_sel(priv_dev, ctrl_req); - break; - case USB_REQ_SET_ISOCH_DELAY: - ret = cdns3_req_ep0_set_isoch_delay(priv_dev, ctrl_req); - break; - default: - ret = cdns3_ep0_delegate_req(priv_dev, ctrl_req); - break; - } - - return ret; -} - -static void __pending_setup_status_handler(struct cdns3_device *priv_dev) -{ - struct usb_request *request = priv_dev->pending_status_request; - - if (priv_dev->status_completion_no_call && request && - request->complete) { - request->complete(&priv_dev->eps[0]->endpoint, request); - priv_dev->status_completion_no_call = 0; - } -} - -void cdns3_pending_setup_status_handler(struct work_struct *work) -{ - struct cdns3_device *priv_dev = container_of(work, struct cdns3_device, - pending_status_wq); - unsigned long flags; - - spin_lock_irqsave(&priv_dev->lock, flags); - __pending_setup_status_handler(priv_dev); - spin_unlock_irqrestore(&priv_dev->lock, flags); -} - -/** - * cdns3_ep0_setup_phase - Handling setup USB requests - * @priv_dev: extended gadget object - */ -static void cdns3_ep0_setup_phase(struct cdns3_device *priv_dev) -{ - struct usb_ctrlrequest *ctrl = priv_dev->setup_buf; - struct cdns3_endpoint *priv_ep = priv_dev->eps[0]; - int result; - - /* Invalidate Setup Packet received */ - invalidate_dcache_range(priv_dev->setup_dma, - priv_dev->setup_dma + ARCH_DMA_MINALIGN); - - priv_dev->ep0_data_dir = ctrl->bRequestType & USB_DIR_IN; - - trace_cdns3_ctrl_req(ctrl); - - if (!list_empty(&priv_ep->pending_req_list)) { - struct usb_request *request; - - request = cdns3_next_request(&priv_ep->pending_req_list); - priv_ep->dir = priv_dev->ep0_data_dir; - cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), - -ECONNRESET); - } - - if (le16_to_cpu(ctrl->wLength)) - priv_dev->ep0_stage = CDNS3_DATA_STAGE; - else - priv_dev->ep0_stage = CDNS3_STATUS_STAGE; - - if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) - result = cdns3_ep0_standard_request(priv_dev, ctrl); - else - result = cdns3_ep0_delegate_req(priv_dev, ctrl); - - if (result == USB_GADGET_DELAYED_STATUS) - return; - - if (result < 0) - cdns3_ep0_complete_setup(priv_dev, 1, 1); - else if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE) - cdns3_ep0_complete_setup(priv_dev, 0, 1); -} - -static void cdns3_transfer_completed(struct cdns3_device *priv_dev) -{ - struct cdns3_endpoint *priv_ep = priv_dev->eps[0]; - - if (!list_empty(&priv_ep->pending_req_list)) { - struct usb_request *request; - - trace_cdns3_complete_trb(priv_ep, priv_ep->trb_pool); - request = cdns3_next_request(&priv_ep->pending_req_list); - - /* Invalidate TRB before accessing it */ - invalidate_dcache_range((unsigned long)priv_ep->trb_pool, - (unsigned long)priv_ep->trb_pool + - ROUND(sizeof(struct cdns3_trb), - CONFIG_SYS_CACHELINE_SIZE)); - - request->actual = - TRB_LEN(le32_to_cpu(priv_ep->trb_pool->length)); - - priv_ep->dir = priv_dev->ep0_data_dir; - cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), 0); - } - - cdns3_ep0_complete_setup(priv_dev, 0, 0); -} - -/** - * cdns3_check_new_setup - Check if controller receive new SETUP packet. - * @priv_dev: extended gadget object - * - * The SETUP packet can be kept in on-chip memory or in system memory. - */ -static bool cdns3_check_new_setup(struct cdns3_device *priv_dev) -{ - u32 ep_sts_reg; - - cdns3_select_ep(priv_dev, 0 | USB_DIR_OUT); - ep_sts_reg = readl(&priv_dev->regs->ep_sts); - - return !!(ep_sts_reg & (EP_STS_SETUP | EP_STS_STPWAIT)); -} - -/** - * cdns3_check_ep0_interrupt_proceed - Processes interrupt related to endpoint 0 - * @priv_dev: extended gadget object - * @dir: USB_DIR_IN for IN direction, USB_DIR_OUT for OUT direction - */ -void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir) -{ - u32 ep_sts_reg; - - cdns3_select_ep(priv_dev, dir); - - ep_sts_reg = readl(&priv_dev->regs->ep_sts); - writel(ep_sts_reg, &priv_dev->regs->ep_sts); - - trace_cdns3_ep0_irq(priv_dev, ep_sts_reg); - - __pending_setup_status_handler(priv_dev); - - if (ep_sts_reg & EP_STS_SETUP) - priv_dev->wait_for_setup = 1; - - if (priv_dev->wait_for_setup && ep_sts_reg & EP_STS_IOC) { - priv_dev->wait_for_setup = 0; - cdns3_allow_enable_l1(priv_dev, 0); - cdns3_ep0_setup_phase(priv_dev); - } else if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) { - priv_dev->ep0_data_dir = dir; - cdns3_transfer_completed(priv_dev); - } - - if (ep_sts_reg & EP_STS_DESCMIS) { - if (dir == 0 && !priv_dev->setup_pending) - cdns3_prepare_setup_packet(priv_dev); - } -} - -/** - * cdns3_gadget_ep0_enable - * Function shouldn't be called by gadget driver, - * endpoint 0 is allways active - */ -static int cdns3_gadget_ep0_enable(struct usb_ep *ep, - const struct usb_endpoint_descriptor *desc) -{ - return -EINVAL; -} - -/** - * cdns3_gadget_ep0_disable - * Function shouldn't be called by gadget driver, - * endpoint 0 is allways active - */ -static int cdns3_gadget_ep0_disable(struct usb_ep *ep) -{ - return -EINVAL; -} - -/** - * cdns3_gadget_ep0_set_halt - * @ep: pointer to endpoint zero object - * @value: 1 for set stall, 0 for clear stall - * - * Returns 0 - */ -static int cdns3_gadget_ep0_set_halt(struct usb_ep *ep, int value) -{ - /* TODO */ - return 0; -} - -/** - * cdns3_gadget_ep0_queue Transfer data on endpoint zero - * @ep: pointer to endpoint zero object - * @request: pointer to request object - * @gfp_flags: gfp flags - * - * Returns 0 on success, error code elsewhere - */ -static int cdns3_gadget_ep0_queue(struct usb_ep *ep, - struct usb_request *request, - gfp_t gfp_flags) -{ - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - unsigned long flags; - int erdy_sent = 0; - int ret = 0; - u8 zlp = 0; - - trace_cdns3_ep0_queue(priv_dev, request); - - /* cancel the request if controller receive new SETUP packet. */ - if (cdns3_check_new_setup(priv_dev)) - return -ECONNRESET; - - /* send STATUS stage. Should be called only for SET_CONFIGURATION */ - if (priv_dev->ep0_stage == CDNS3_STATUS_STAGE) { - spin_lock_irqsave(&priv_dev->lock, flags); - cdns3_select_ep(priv_dev, 0x00); - - erdy_sent = !priv_dev->hw_configured_flag; - cdns3_set_hw_configuration(priv_dev); - - if (!erdy_sent) - cdns3_ep0_complete_setup(priv_dev, 0, 1); - - cdns3_allow_enable_l1(priv_dev, 1); - - request->actual = 0; - priv_dev->status_completion_no_call = true; - priv_dev->pending_status_request = request; - spin_unlock_irqrestore(&priv_dev->lock, flags); - - /* - * Since there is no completion interrupt for status stage, - * it needs to call ->completion in software after - * ep0_queue is back. - */ -#ifndef __UBOOT__ - queue_work(system_freezable_wq, &priv_dev->pending_status_wq); -#else - __pending_setup_status_handler(priv_dev); -#endif - return 0; - } - - spin_lock_irqsave(&priv_dev->lock, flags); - if (!list_empty(&priv_ep->pending_req_list)) { - dev_err(priv_dev->dev, - "can't handle multiple requests for ep0\n"); - spin_unlock_irqrestore(&priv_dev->lock, flags); - return -EBUSY; - } - - ret = usb_gadget_map_request(&priv_dev->gadget, request, - priv_dev->ep0_data_dir); - if (ret) { - spin_unlock_irqrestore(&priv_dev->lock, flags); - dev_err(priv_dev->dev, "failed to map request\n"); - return -EINVAL; - } - - request->status = -EINPROGRESS; - list_add_tail(&request->list, &priv_ep->pending_req_list); - - if (request->zero && request->length && - (request->length % ep->maxpacket == 0)) - zlp = 1; - - cdns3_ep0_run_transfer(priv_dev, request->dma, request->length, 1, zlp); - - spin_unlock_irqrestore(&priv_dev->lock, flags); - - return ret; -} - -/** - * cdns3_gadget_ep_set_wedge Set wedge on selected endpoint - * @ep: endpoint object - * - * Returns 0 - */ -int cdns3_gadget_ep_set_wedge(struct usb_ep *ep) -{ - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); - - dev_dbg(priv_ep->cdns3_dev->dev, "Wedge for %s\n", ep->name); - cdns3_gadget_ep_set_halt(ep, 1); - priv_ep->flags |= EP_WEDGE; - - return 0; -} - -const struct usb_ep_ops cdns3_gadget_ep0_ops = { - .enable = cdns3_gadget_ep0_enable, - .disable = cdns3_gadget_ep0_disable, - .alloc_request = cdns3_gadget_ep_alloc_request, - .free_request = cdns3_gadget_ep_free_request, - .queue = cdns3_gadget_ep0_queue, - .dequeue = cdns3_gadget_ep_dequeue, - .set_halt = cdns3_gadget_ep0_set_halt, - .set_wedge = cdns3_gadget_ep_set_wedge, -}; - -/** - * cdns3_ep0_config - Configures default endpoint - * @priv_dev: extended gadget object - * - * Functions sets parameters: maximal packet size and enables interrupts - */ -void cdns3_ep0_config(struct cdns3_device *priv_dev) -{ - struct cdns3_usb_regs __iomem *regs; - struct cdns3_endpoint *priv_ep; - u32 max_packet_size = 64; - - regs = priv_dev->regs; - - if (priv_dev->gadget.speed == USB_SPEED_SUPER) - max_packet_size = 512; - - priv_ep = priv_dev->eps[0]; - - if (!list_empty(&priv_ep->pending_req_list)) { - struct usb_request *request; - - request = cdns3_next_request(&priv_ep->pending_req_list); - list_del_init(&request->list); - } - - priv_dev->u1_allowed = 0; - priv_dev->u2_allowed = 0; - - priv_dev->gadget.ep0->maxpacket = max_packet_size; - cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(max_packet_size); - - /* init ep out */ - cdns3_select_ep(priv_dev, USB_DIR_OUT); - - if (priv_dev->dev_ver >= DEV_VER_V3) { - cdns3_set_register_bit(&priv_dev->regs->dtrans, - BIT(0) | BIT(16)); - cdns3_set_register_bit(&priv_dev->regs->tdl_from_trb, - BIT(0) | BIT(16)); - } - - writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size), - ®s->ep_cfg); - - writel(EP_STS_EN_SETUPEN | EP_STS_EN_DESCMISEN | EP_STS_EN_TRBERREN, - ®s->ep_sts_en); - - /* init ep in */ - cdns3_select_ep(priv_dev, USB_DIR_IN); - - writel(EP_CFG_ENABLE | EP_CFG_MAXPKTSIZE(max_packet_size), - ®s->ep_cfg); - - writel(EP_STS_EN_SETUPEN | EP_STS_EN_TRBERREN, ®s->ep_sts_en); - - cdns3_set_register_bit(®s->usb_conf, USB_CONF_U1DS | USB_CONF_U2DS); -} - -/** - * cdns3_init_ep0 Initializes software endpoint 0 of gadget - * @priv_dev: extended gadget object - * @ep_priv: extended endpoint object - * - * Returns 0 on success else error code. - */ -int cdns3_init_ep0(struct cdns3_device *priv_dev, - struct cdns3_endpoint *priv_ep) -{ - sprintf(priv_ep->name, "ep0"); - - /* fill linux fields */ - priv_ep->endpoint.ops = &cdns3_gadget_ep0_ops; - priv_ep->endpoint.maxburst = 1; - usb_ep_set_maxpacket_limit(&priv_ep->endpoint, - CDNS3_EP0_MAX_PACKET_LIMIT); -#ifndef __UBOOT__ - priv_ep->endpoint.address = 0; -#endif - priv_ep->endpoint.caps.type_control = 1; - priv_ep->endpoint.caps.dir_in = 1; - priv_ep->endpoint.caps.dir_out = 1; - priv_ep->endpoint.name = priv_ep->name; - priv_ep->endpoint.desc = &cdns3_gadget_ep0_desc; - priv_dev->gadget.ep0 = &priv_ep->endpoint; - priv_ep->type = USB_ENDPOINT_XFER_CONTROL; - - return cdns3_allocate_trb_pool(priv_ep); -} diff --git a/drivers/usb/cdns3/gadget-export.h b/drivers/usb/cdns3/gadget-export.h index 577469eee96..0b011b56c6d 100644 --- a/drivers/usb/cdns3/gadget-export.h +++ b/drivers/usb/cdns3/gadget-export.h @@ -1,19 +1,15 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* - * Cadence USBSS DRD Driver - Gadget Export APIs. - * - * Copyright (C) 2017 NXP - * Copyright (C) 2017-2018 NXP - * - * Authors: Peter Chen + * Copyright 2019 NXP */ -#ifndef __LINUX_CDNS3_GADGET_EXPORT -#define __LINUX_CDNS3_GADGET_EXPORT + +#ifndef __CDNS3_GADGET_EXPORT_H +#define __CDNS3_GADGET_EXPORT_H #ifdef CONFIG_USB_CDNS3_GADGET int cdns3_gadget_init(struct cdns3 *cdns); -void cdns3_gadget_exit(struct cdns3 *cdns); +void cdns3_gadget_remove(struct cdns3 *cdns); #else static inline int cdns3_gadget_init(struct cdns3 *cdns) @@ -21,8 +17,10 @@ static inline int cdns3_gadget_init(struct cdns3 *cdns) return -ENXIO; } -static inline void cdns3_gadget_exit(struct cdns3 *cdns) { } +static inline void cdns3_gadget_remove(struct cdns3 *cdns) +{ +} #endif -#endif /* __LINUX_CDNS3_GADGET_EXPORT */ +#endif /* __CDNS3_GADGET_EXPORT_H */ diff --git a/drivers/usb/cdns3/gadget.c b/drivers/usb/cdns3/gadget.c index 83dbb5a103d..5bd80cf9868 100644 --- a/drivers/usb/cdns3/gadget.c +++ b/drivers/usb/cdns3/gadget.c @@ -1,2717 +1,2219 @@ -// SPDX-License-Identifier: GPL-2.0 +// SPDX-License-Identifier: GPL-2.0+ /* - * Cadence USBSS DRD Driver - gadget side. - * - * Copyright (C) 2018-2019 Cadence Design Systems. - * Copyright (C) 2017-2018 NXP - * - * Authors: Pawel Jez , - * Pawel Laszczak - * Peter Chen - */ - -/* - * Work around 1: - * At some situations, the controller may get stale data address in TRB - * at below sequences: - * 1. Controller read TRB includes data address - * 2. Software updates TRBs includes data address and Cycle bit - * 3. Controller read TRB which includes Cycle bit - * 4. DMA run with stale data address - * - * To fix this problem, driver needs to make the first TRB in TD as invalid. - * After preparing all TRBs driver needs to check the position of DMA and - * if the DMA point to the first just added TRB and doorbell is 1, - * then driver must defer making this TRB as valid. This TRB will be make - * as valid during adding next TRB only if DMA is stopped or at TRBERR - * interrupt. - * - * Issue has been fixed in DEV_VER_V3 version of controller. - * - * Work around 2: - * Controller for OUT endpoints has shared on-chip buffers for all incoming - * packets, including ep0out. It's FIFO buffer, so packets must be handle by DMA - * in correct order. If the first packet in the buffer will not be handled, - * then the following packets directed for other endpoints and functions - * will be blocked. - * Additionally the packets directed to one endpoint can block entire on-chip - * buffers. In this case transfer to other endpoints also will blocked. - * - * To resolve this issue after raising the descriptor missing interrupt - * driver prepares internal usb_request object and use it to arm DMA transfer. - * - * The problematic situation was observed in case when endpoint has been enabled - * but no usb_request were queued. Driver try detects such endpoints and will - * use this workaround only for these endpoint. - * - * Driver use limited number of buffer. This number can be set by macro - * CDNS3_WA2_NUM_BUFFERS. - * - * Such blocking situation was observed on ACM gadget. For this function - * host send OUT data packet but ACM function is not prepared for this packet. - * It's cause that buffer placed in on chip memory block transfer to other - * endpoints. - * - * Issue has been fixed in DEV_VER_V2 version of controller. - * + * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/ + * Copyright 2019 NXP */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include +#include #include "core.h" #include "gadget-export.h" #include "gadget.h" -#include "trace.h" -#include "drd.h" +#include "io.h" +#include -#define readl_poll_timeout_atomic readl_poll_timeout -#define usleep_range(a, b) udelay((b)) +static void __cdns3_gadget_start(struct usb_ss_dev *usb_ss); +static void cdns_prepare_setup_packet(struct usb_ss_dev *usb_ss); +static void cdns_ep_config(struct usb_ss_endpoint *usb_ss_ep); -static int __cdns3_gadget_ep_queue(struct usb_ep *ep, - struct usb_request *request, - gfp_t gfp_flags); +static struct usb_endpoint_descriptor cdns3_gadget_ep0_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + .bmAttributes = USB_ENDPOINT_XFER_CONTROL, +}; /** - * cdns3_set_register_bit - set bit in given register. - * @ptr: address of device controller register to be read and changed - * @mask: bits requested to set + * next_request - returns next request from list + * @list: list containing requests + * + * Returns request or NULL if no requests in list */ -void cdns3_set_register_bit(void __iomem *ptr, u32 mask) +static struct usb_request *next_request(struct list_head *list) { - mask = readl(ptr) | mask; - writel(mask, ptr); + if (list_empty(list)) + return NULL; + return list_first_entry(list, struct usb_request, list); } /** - * cdns3_ep_addr_to_index - Macro converts endpoint address to - * index of endpoint object in cdns3_device.eps[] container - * @ep_addr: endpoint address for which endpoint object is required - * + * select_ep - selects endpoint + * @usb_ss: extended gadget object + * @ep: endpoint address */ -u8 cdns3_ep_addr_to_index(u8 ep_addr) +static void select_ep(struct usb_ss_dev *usb_ss, u32 ep) { - return (((ep_addr & 0x7F)) + ((ep_addr & USB_DIR_IN) ? 16 : 0)); + if (!usb_ss || !usb_ss->regs) { + dev_err(&usb_ss->dev, "Failed to select endpoint!\n"); + return; + } + + cdns_writel(&usb_ss->regs->ep_sel, ep); } -static int cdns3_get_dma_pos(struct cdns3_device *priv_dev, - struct cdns3_endpoint *priv_ep) +/** + * usb_ss_allocate_trb_pool - Allocates TRB's pool for selected endpoint + * @usb_ss_ep: extended endpoint object + * + * Function will return 0 on success or -ENOMEM on allocation error + */ +static int usb_ss_allocate_trb_pool(struct usb_ss_endpoint *usb_ss_ep) { - int dma_index; + if (usb_ss_ep->trb_pool) + return 0; + + usb_ss_ep->trb_pool = + dma_alloc_coherent(sizeof(struct usb_ss_trb) * USB_SS_TRBS_NUM, + (unsigned long *)&usb_ss_ep->trb_pool_dma); + + if (!usb_ss_ep->trb_pool) { + dev_err(&usb_ss_ep->usb_ss->dev, + "Failed to allocate TRB pool for endpoint %s\n", + usb_ss_ep->name); + return -ENOMEM; + } - dma_index = readl(&priv_dev->regs->ep_traddr) - priv_ep->trb_pool_dma; + memset(usb_ss_ep->trb_pool, 0, + sizeof(struct usb_ss_trb) * USB_SS_TRBS_NUM); - return dma_index / TRB_SIZE; + return 0; } /** - * cdns3_next_request - returns next request from list - * @list: list containing requests + * cdns_ep_stall_flush - Stalls and flushes selected endpoint + * @usb_ss_ep: extended endpoint object * - * Returns request or NULL if no requests in list + * Endpoint must be selected before call to this function */ -struct usb_request *cdns3_next_request(struct list_head *list) +static void cdns_ep_stall_flush(struct usb_ss_endpoint *usb_ss_ep) { - return list_first_entry_or_null(list, struct usb_request, list); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__DFLUSH__MASK | EP_CMD__ERDY__MASK | + EP_CMD__SSTALL__MASK); + + /* wait for DFLUSH cleared */ + while (cdns_readl(&usb_ss->regs->ep_cmd) & + EP_CMD__DFLUSH__MASK) + ; + + usb_ss_ep->stalled_flag = 1; } /** - * cdns3_next_align_buf - returns next buffer from list - * @list: list containing buffers + * cdns_ep0_config - Configures default endpoint + * @usb_ss: extended gadget object * - * Returns buffer or NULL if no buffers in list + * Functions sets parameters: maximal packet size and enables interrupts */ -struct cdns3_aligned_buf *cdns3_next_align_buf(struct list_head *list) +static void cdns_ep0_config(struct usb_ss_dev *usb_ss) { - return list_first_entry_or_null(list, struct cdns3_aligned_buf, list); + u32 max_packet_size = 0; + + switch (usb_ss->gadget.speed) { + case USB_SPEED_UNKNOWN: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_0; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_0; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(0); + break; + + case USB_SPEED_LOW: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_8; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_8; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8); + break; + + case USB_SPEED_FULL: + case USB_SPEED_HIGH: + case USB_SPEED_WIRELESS: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_64; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_64; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64); + break; + + case USB_SPEED_SUPER: + case USB_SPEED_SUPER_PLUS: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_512; + usb_ss->gadget.ep0->maxpacket = ENDPOINT_MAX_PACKET_SIZE_512; + cdns3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512); + break; + } + + /* init ep out */ + select_ep(usb_ss, USB_DIR_OUT); + + cdns_writel(&usb_ss->regs->ep_cfg, + EP_CFG__ENABLE__MASK | + EP_CFG__MAXPKTSIZE__WRITE(max_packet_size)); + cdns_writel(&usb_ss->regs->ep_sts_en, + EP_STS_EN__SETUPEN__MASK | + EP_STS_EN__DESCMISEN__MASK | + EP_STS_EN__TRBERREN__MASK); + + /* init ep in */ + select_ep(usb_ss, USB_DIR_IN); + + cdns_writel(&usb_ss->regs->ep_cfg, + EP_CFG__ENABLE__MASK | + EP_CFG__MAXPKTSIZE__WRITE(max_packet_size)); + cdns_writel(&usb_ss->regs->ep_sts_en, + EP_STS_EN__SETUPEN__MASK | + EP_STS_EN__TRBERREN__MASK); + + cdns_prepare_setup_packet(usb_ss); } /** - * cdns3_next_priv_request - returns next request from list - * @list: list containing requests - * - * Returns request or NULL if no requests in list + * cdns_gadget_unconfig - Unconfigures device controller + * @usb_ss: extended gadget object */ -struct cdns3_request *cdns3_next_priv_request(struct list_head *list) +static void cdns_gadget_unconfig(struct usb_ss_dev *usb_ss) { - return list_first_entry_or_null(list, struct cdns3_request, list); + /* RESET CONFIGURATION */ + cdns_writel(&usb_ss->regs->usb_conf, + USB_CONF__CFGRST__MASK); + + usb_ss->hw_configured_flag = 0; } /** - * select_ep - selects endpoint - * @priv_dev: extended gadget object - * @ep: endpoint address + * cdns_ep0_run_transfer - Do transfer on default endpoint hardware + * @usb_ss: extended gadget object + * @dma_addr: physical address where data is/will be stored + * @length: data length + * @erdy: set it to 1 when ERDY packet should be sent - + * exit from flow control state */ -void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep) +static void cdns_ep0_run_transfer(struct usb_ss_dev *usb_ss, + dma_addr_t dma_addr, + unsigned int length, int erdy) { - if (priv_dev->selected_ep == ep) - return; + usb_ss->trb_ep0[0] = TRB_SET_DATA_BUFFER_POINTER(dma_addr); + usb_ss->trb_ep0[1] = TRB_SET_TRANSFER_LENGTH((u32)length); + usb_ss->trb_ep0[2] = TRB_SET_CYCLE_BIT | + TRB_SET_INT_ON_COMPLETION | TRB_TYPE_NORMAL; - priv_dev->selected_ep = ep; - writel(ep, &priv_dev->regs->ep_sel); -} + cdns_flush_cache((uintptr_t)usb_ss->trb_ep0, 20); + cdns_flush_cache((uintptr_t)dma_addr, length); -dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep, - struct cdns3_trb *trb) -{ - u32 offset = (char *)trb - (char *)priv_ep->trb_pool; + dev_dbg(&usb_ss->dev, "DRBL(%02X)\n", + usb_ss->ep0_data_dir ? USB_DIR_IN : USB_DIR_OUT); - return priv_ep->trb_pool_dma + offset; -} + select_ep(usb_ss, usb_ss->ep0_data_dir + ? USB_DIR_IN : USB_DIR_OUT); -int cdns3_ring_size(struct cdns3_endpoint *priv_ep) -{ - switch (priv_ep->type) { - case USB_ENDPOINT_XFER_ISOC: - return TRB_ISO_RING_SIZE; - case USB_ENDPOINT_XFER_CONTROL: - return TRB_CTRL_RING_SIZE; - default: - return TRB_RING_SIZE; - } + cdns_writel(&usb_ss->regs->ep_traddr, + EP_TRADDR__TRADDR__WRITE(usb_ss->trb_ep0_dma)); + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__DRDY__MASK); /* drbl */ + + if (erdy) + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK); } /** - * cdns3_allocate_trb_pool - Allocates TRB's pool for selected endpoint - * @priv_ep: endpoint object + * cdns_ep_run_transfer - Do transfer on no-default endpoint hardware + * @usb_ss_ep: extended endpoint object * - * Function will return 0 on success or -ENOMEM on allocation error + * Returns zero on success or negative value on failure */ -int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep) +static int cdns_ep_run_transfer(struct usb_ss_endpoint *usb_ss_ep) { - int ring_size = cdns3_ring_size(priv_ep); - struct cdns3_trb *link_trb; - - if (!priv_ep->trb_pool) { - priv_ep->trb_pool = - dma_alloc_coherent(ring_size, - (unsigned long *)&priv_ep->trb_pool_dma); - if (!priv_ep->trb_pool) - return -ENOMEM; - } else { - memset(priv_ep->trb_pool, 0, ring_size); - } + dma_addr_t trb_dma; + struct usb_request *request = next_request(&usb_ss_ep->request_list); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + struct usb_ss_trb *trb; - if (!priv_ep->num) - return 0; + if (!request) + return -EINVAL; - priv_ep->num_trbs = ring_size / TRB_SIZE; - /* Initialize the last TRB as Link TRB. */ - link_trb = (priv_ep->trb_pool + (priv_ep->num_trbs - 1)); - link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma); - link_trb->control = TRB_CYCLE | TRB_TYPE(TRB_LINK) | TRB_TOGGLE; + dev_dbg(&usb_ss->dev, "DRBL(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); - return 0; -} + usb_ss_ep->hw_pending_flag = 1; + trb_dma = request->dma; -static void cdns3_free_trb_pool(struct cdns3_endpoint *priv_ep) -{ - if (priv_ep->trb_pool) { - dma_free_coherent(priv_ep->trb_pool); - priv_ep->trb_pool = NULL; + /* must allocate buffer aligned to 8 */ + if (request->dma % ADDR_MODULO_8) { + memcpy(usb_ss_ep->cpu_addr, request->buf, request->length); + trb_dma = usb_ss_ep->dma_addr; } -} -/** - * cdns3_ep_stall_flush - Stalls and flushes selected endpoint - * @priv_ep: endpoint object - * - * Endpoint must be selected before call to this function - */ -static void cdns3_ep_stall_flush(struct cdns3_endpoint *priv_ep) -{ - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - int val; + cdns_flush_cache((uintptr_t)trb_dma, request->length); - trace_cdns3_halt(priv_ep, 1, 1); + trb = usb_ss_ep->trb_pool; - writel(EP_CMD_DFLUSH | EP_CMD_ERDY | EP_CMD_SSTALL, - &priv_dev->regs->ep_cmd); + /* fill TRB */ + trb->offset0 = trb_dma; - /* wait for DFLUSH cleared */ - readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, - !(val & EP_CMD_DFLUSH), 1000); - priv_ep->flags |= EP_STALLED; - priv_ep->flags &= ~EP_STALL_PENDING; -} + trb->offset4 = TRB_SET_BURST_LENGTH(16) | + TRB_SET_TRANSFER_LENGTH(request->length); -/** - * cdns3_hw_reset_eps_config - reset endpoints configuration kept by controller. - * @priv_dev: extended gadget object - */ -void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev) -{ - writel(USB_CONF_CFGRST, &priv_dev->regs->usb_conf); + trb->offset8 = TRB_SET_CYCLE_BIT + | TRB_SET_INT_ON_COMPLETION + | TRB_SET_INT_ON_SHORT_PACKET + | TRB_TYPE_NORMAL; + + cdns_flush_cache((uintptr_t)trb, sizeof(struct usb_ss_trb)); + + /* arm transfer on selected endpoint */ + select_ep(usb_ss_ep->usb_ss, + usb_ss_ep->endpoint.desc->bEndpointAddress); - cdns3_allow_enable_l1(priv_dev, 0); - priv_dev->hw_configured_flag = 0; - priv_dev->onchip_used_size = 0; - priv_dev->out_mem_is_allocated = 0; - priv_dev->wait_for_setup = 0; + cdns_writel(&usb_ss->regs->ep_traddr, + EP_TRADDR__TRADDR__WRITE(usb_ss_ep->trb_pool_dma)); + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__DRDY__MASK); /* DRDY */ + return 0; } /** - * cdns3_ep_inc_trb - increment a trb index. - * @index: Pointer to the TRB index to increment. - * @cs: Cycle state - * @trb_in_seg: number of TRBs in segment + * cdns_get_setup_ret - Returns status of handling setup packet + * Setup is handled by gadget driver + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet * - * The index should never point to the link TRB. After incrementing, - * if it is point to the link TRB, wrap around to the beginning and revert - * cycle state bit The - * link TRB is always at the last TRB entry. + * Returns zero on success or negative value on failure */ -static void cdns3_ep_inc_trb(int *index, u8 *cs, int trb_in_seg) +static int cdns_get_setup_ret(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) { - (*index)++; - if (*index == (trb_in_seg - 1)) { - *index = 0; - *cs ^= 1; - } + int ret; + + spin_unlock(&usb_ss->lock); + usb_ss->setup_pending = 1; + ret = usb_ss->gadget_driver->setup(&usb_ss->gadget, ctrl_req); + usb_ss->setup_pending = 0; + spin_lock(&usb_ss->lock); + return ret; } -/** - * cdns3_ep_inc_enq - increment endpoint's enqueue pointer - * @priv_ep: The endpoint whose enqueue pointer we're incrementing - */ -static void cdns3_ep_inc_enq(struct cdns3_endpoint *priv_ep) +static void cdns_prepare_setup_packet(struct usb_ss_dev *usb_ss) { - priv_ep->free_trbs--; - cdns3_ep_inc_trb(&priv_ep->enqueue, &priv_ep->pcs, priv_ep->num_trbs); + usb_ss->ep0_data_dir = 0; + cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, 8, 0); } /** - * cdns3_ep_inc_deq - increment endpoint's dequeue pointer - * @priv_ep: The endpoint whose dequeue pointer we're incrementing + * cdns_req_ep0_set_address - Handling of SET_ADDRESS standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, error code on error */ -static void cdns3_ep_inc_deq(struct cdns3_endpoint *priv_ep) +static int cdns_req_ep0_set_address(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) { - priv_ep->free_trbs++; - cdns3_ep_inc_trb(&priv_ep->dequeue, &priv_ep->ccs, priv_ep->num_trbs); -} + enum usb_device_state device_state = usb_ss->gadget.state; + u32 reg; + u32 addr; -void cdns3_move_deq_to_next_trb(struct cdns3_request *priv_req) -{ - struct cdns3_endpoint *priv_ep = priv_req->priv_ep; - int current_trb = priv_req->start_trb; + addr = le16_to_cpu(ctrl_req->wValue); - while (current_trb != priv_req->end_trb) { - cdns3_ep_inc_deq(priv_ep); - current_trb = priv_ep->dequeue; + if (addr > DEVICE_ADDRESS_MAX) { + dev_err(&usb_ss->dev, + "Device address (%d) cannot be greater than %d\n", + addr, DEVICE_ADDRESS_MAX); + return -EINVAL; } - cdns3_ep_inc_deq(priv_ep); -} + if (device_state == USB_STATE_CONFIGURED) { + dev_err(&usb_ss->dev, "USB device already configured\n"); + return -EINVAL; + } -/** - * cdns3_allow_enable_l1 - enable/disable permits to transition to L1. - * @priv_dev: Extended gadget object - * @enable: Enable/disable permit to transition to L1. - * - * If bit USB_CONF_L1EN is set and device receive Extended Token packet, - * then controller answer with ACK handshake. - * If bit USB_CONF_L1DS is set and device receive Extended Token packet, - * then controller answer with NYET handshake. - */ -void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable) -{ - if (enable) - writel(USB_CONF_L1EN, &priv_dev->regs->usb_conf); - else - writel(USB_CONF_L1DS, &priv_dev->regs->usb_conf); -} + reg = cdns_readl(&usb_ss->regs->usb_cmd); -enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev) -{ - u32 reg; + cdns_writel(&usb_ss->regs->usb_cmd, reg + | USB_CMD__FADDR__WRITE(addr) + | USB_CMD__SET_ADDR__MASK); - reg = readl(&priv_dev->regs->usb_sts); - - if (DEV_SUPERSPEED(reg)) - return USB_SPEED_SUPER; - else if (DEV_HIGHSPEED(reg)) - return USB_SPEED_HIGH; - else if (DEV_FULLSPEED(reg)) - return USB_SPEED_FULL; - else if (DEV_LOWSPEED(reg)) - return USB_SPEED_LOW; - return USB_SPEED_UNKNOWN; + usb_gadget_set_state(&usb_ss->gadget, + (addr ? USB_STATE_ADDRESS : USB_STATE_DEFAULT)); + + cdns_prepare_setup_packet(usb_ss); + + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + return 0; } /** - * cdns3_start_all_request - add to ring all request not started - * @priv_dev: Extended gadget object - * @priv_ep: The endpoint for whom request will be started. + * cdns_req_ep0_get_status - Handling of GET_STATUS standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet * - * Returns return ENOMEM if transfer ring i not enough TRBs to start - * all requests. + * Returns 0 if success, error code on error */ -static int cdns3_start_all_request(struct cdns3_device *priv_dev, - struct cdns3_endpoint *priv_ep) +static int cdns_req_ep0_get_status(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) { - struct usb_request *request; - int ret = 0; + u16 usb_status = 0; + unsigned int length = 2; + u32 recip = ctrl_req->bRequestType & USB_RECIP_MASK; + u32 reg; - while (!list_empty(&priv_ep->deferred_req_list)) { - request = cdns3_next_request(&priv_ep->deferred_req_list); + switch (recip) { + case USB_RECIP_DEVICE: + reg = cdns_readl(&usb_ss->regs->usb_sts); - ret = cdns3_ep_run_transfer(priv_ep, request); - if (ret) - return ret; + if (reg & USB_STS__U1ENS__MASK) + usb_status |= 1uL << USB_DEV_STAT_U1_ENABLED; - list_del(&request->list); - list_add_tail(&request->list, - &priv_ep->pending_req_list); + if (reg & USB_STS__U2ENS__MASK) + usb_status |= 1uL << USB_DEV_STAT_U2_ENABLED; + + if (usb_ss->wake_up_flag) + usb_status |= 1uL << USB_DEVICE_REMOTE_WAKEUP; + + /* self powered */ + usb_status |= 1uL << USB_DEVICE_SELF_POWERED; + break; + + case USB_RECIP_INTERFACE: + return cdns_get_setup_ret(usb_ss, ctrl_req); + + case USB_RECIP_ENDPOINT: + /* check if endpoint is stalled */ + select_ep(usb_ss, ctrl_req->wIndex); + if (cdns_readl(&usb_ss->regs->ep_sts) + & EP_STS__STALL__MASK) + usb_status = 1; + break; + + default: + return -EINVAL; } - priv_ep->flags &= ~EP_RING_FULL; - return ret; -} + *(u16 *)usb_ss->setup = cpu_to_le16(usb_status); -/* - * WA2: Set flag for all not ISOC OUT endpoints. If this flag is set - * driver try to detect whether endpoint need additional internal - * buffer for unblocking on-chip FIFO buffer. This flag will be cleared - * if before first DESCMISS interrupt the DMA will be armed. - */ -#define cdns3_wa2_enable_detection(priv_dev, ep_priv, reg) do { \ - if (!priv_ep->dir && priv_ep->type != USB_ENDPOINT_XFER_ISOC) { \ - priv_ep->flags |= EP_QUIRK_EXTRA_BUF_DET; \ - (reg) |= EP_STS_EN_DESCMISEN; \ - } } while (0) + usb_ss->actual_ep0_request = NULL; + cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, length, 1); + return 0; +} /** - * cdns3_wa2_descmiss_copy_data copy data from internal requests to - * request queued by class driver. - * @priv_ep: extended endpoint object - * @request: request object + * cdns_req_ep0_handle_feature - + * Handling of GET/SET_FEATURE standard USB request + * + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * @set: must be set to 1 for SET_FEATURE request + * + * Returns 0 if success, error code on error */ -static void cdns3_wa2_descmiss_copy_data(struct cdns3_endpoint *priv_ep, - struct usb_request *request) +static int cdns_req_ep0_handle_feature(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req, + int set) { - struct usb_request *descmiss_req; - struct cdns3_request *descmiss_priv_req; + u32 recip = ctrl_req->bRequestType & USB_RECIP_MASK; + struct usb_ss_endpoint *usb_ss_ep; + u32 reg; + u8 tmode = 0; + + switch (recip) { + case USB_RECIP_DEVICE: + + switch (ctrl_req->wValue) { + case USB_DEVICE_U1_ENABLE: + if (usb_ss->gadget.state != USB_STATE_CONFIGURED) + return -EINVAL; + if (usb_ss->gadget.speed != USB_SPEED_SUPER) + return -EINVAL; + + reg = cdns_readl(&usb_ss->regs->usb_conf); + if (set) + /* set U1EN */ + reg |= USB_CONF__U1EN__MASK; + else + /* set U1 disable */ + reg |= USB_CONF__U1DS__MASK; + cdns_writel(&usb_ss->regs->usb_conf, reg); + break; - while (!list_empty(&priv_ep->wa2_descmiss_req_list)) { - int chunk_end; - int length; + case USB_DEVICE_U2_ENABLE: + if (usb_ss->gadget.state != USB_STATE_CONFIGURED) + return -EINVAL; + if (usb_ss->gadget.speed != USB_SPEED_SUPER) + return -EINVAL; - descmiss_priv_req = - cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list); - descmiss_req = &descmiss_priv_req->request; + reg = cdns_readl(&usb_ss->regs->usb_conf); + if (set) + /* set U2EN */ + reg |= USB_CONF__U2EN__MASK; + else + /* set U2 disable */ + reg |= USB_CONF__U2DS__MASK; + cdns_writel(&usb_ss->regs->usb_conf, reg); + break; - /* driver can't touch pending request */ - if (descmiss_priv_req->flags & REQUEST_PENDING) + case USB_DEVICE_A_ALT_HNP_SUPPORT: break; - chunk_end = descmiss_priv_req->flags & REQUEST_INTERNAL_CH; - length = request->actual + descmiss_req->actual; + case USB_DEVICE_A_HNP_SUPPORT: + break; - request->status = descmiss_req->status; + case USB_DEVICE_B_HNP_ENABLE: + if (!usb_ss->gadget.b_hnp_enable && set) + usb_ss->gadget.b_hnp_enable = 1; + break; - if (length <= request->length) { - memcpy(&((u8 *)request->buf)[request->actual], - descmiss_req->buf, - descmiss_req->actual); - request->actual = length; - } else { - /* It should never occur */ - request->status = -ENOMEM; - } + case USB_DEVICE_REMOTE_WAKEUP: + usb_ss->wake_up_flag = !!set; + break; - list_del_init(&descmiss_priv_req->list); + case USB_DEVICE_TEST_MODE: + if (usb_ss->gadget.state != USB_STATE_CONFIGURED) + return -EINVAL; + if (usb_ss->gadget.speed != USB_SPEED_HIGH && + usb_ss->gadget.speed != USB_SPEED_FULL) + return -EINVAL; + if (ctrl_req->wLength != 0 || + ctrl_req->bRequestType & USB_DIR_IN) { + dev_err(&usb_ss->dev, "req is error\n"); + return -EINVAL; + } + tmode = le16_to_cpu(ctrl_req->wIndex) >> 8; + switch (tmode) { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + reg = cdns_readl(&usb_ss->regs->usb_cmd); + tmode -= 1; + reg |= USB_CMD__STMODE | + USB_CMD__TMODE_SEL(tmode); + cdns_writel(&usb_ss->regs->usb_cmd, reg); + dev_info(&usb_ss->dev, + "set test mode, val=0x%x", reg); + break; + default: + return -EINVAL; + } + break; - kfree(descmiss_req->buf); - cdns3_gadget_ep_free_request(&priv_ep->endpoint, descmiss_req); - --priv_ep->wa2_counter; + default: + return -EINVAL; + } + break; - if (!chunk_end) - break; - } -} + case USB_RECIP_INTERFACE: + return cdns_get_setup_ret(usb_ss, ctrl_req); -struct usb_request *cdns3_wa2_gadget_giveback(struct cdns3_device *priv_dev, - struct cdns3_endpoint *priv_ep, - struct cdns3_request *priv_req) -{ - if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN && - priv_req->flags & REQUEST_INTERNAL) { - struct usb_request *req; + case USB_RECIP_ENDPOINT: + select_ep(usb_ss, ctrl_req->wIndex); + u8 ep_index = CAST_EP_ADDR_TO_INDEX(ctrl_req->wIndex); - req = cdns3_next_request(&priv_ep->deferred_req_list); + if (set) { + /* set stall */ + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__SSTALL__MASK); - priv_ep->descmis_req = NULL; + /* handle non zero endpoint software endpoint */ + if (ctrl_req->wIndex & 0x7F) { + usb_ss_ep = usb_ss->eps[ep_index]; + usb_ss_ep->stalled_flag = 1; + } + } else { + struct usb_request *request; - if (!req) - return NULL; + if (ctrl_req->wIndex & 0x7F) { + if (usb_ss->eps[ep_index]->wedge_flag) + goto jmp_wedge; + } - cdns3_wa2_descmiss_copy_data(priv_ep, req); - if (!(priv_ep->flags & EP_QUIRK_END_TRANSFER) && - req->length != req->actual) { - /* wait for next part of transfer */ - return NULL; + /* clear stall */ + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__CSTALL__MASK | + EP_CMD__EPRST__MASK); + /* wait for EPRST cleared */ + while (cdns_readl(&usb_ss->regs->ep_cmd) + & EP_CMD__EPRST__MASK) + ; + + /* handle non zero endpoint software endpoint */ + if (ctrl_req->wIndex & 0x7F) { + usb_ss_ep = usb_ss->eps[ep_index]; + usb_ss_ep->stalled_flag = 0; + + request = + next_request(&usb_ss_ep->request_list); + if (request) + cdns_ep_run_transfer(usb_ss_ep); + } } +jmp_wedge: + select_ep(usb_ss, 0x00); + break; - if (req->status == -EINPROGRESS) - req->status = 0; - - list_del_init(&req->list); - cdns3_start_all_request(priv_dev, priv_ep); - return req; + default: + return -EINVAL; } - return &priv_req->request; + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + + return 0; } -int cdns3_wa2_gadget_ep_queue(struct cdns3_device *priv_dev, - struct cdns3_endpoint *priv_ep, - struct cdns3_request *priv_req) +/** + * cdns_req_ep0_set_sel - Handling of SET_SEL standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, error code on error + */ +static int cdns_req_ep0_set_sel(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) { - int deferred = 0; + if (usb_ss->gadget.state < USB_STATE_ADDRESS) + return -EINVAL; - /* - * If transfer was queued before DESCMISS appear than we - * can disable handling of DESCMISS interrupt. Driver assumes that it - * can disable special treatment for this endpoint. - */ - if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) { - u32 reg; - - cdns3_select_ep(priv_dev, priv_ep->num | priv_ep->dir); - priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET; - reg = readl(&priv_dev->regs->ep_sts_en); - reg &= ~EP_STS_EN_DESCMISEN; - trace_cdns3_wa2(priv_ep, "workaround disabled\n"); - writel(reg, &priv_dev->regs->ep_sts_en); + if (ctrl_req->wLength != 6) { + dev_err(&usb_ss->dev, "Set SEL should be 6 bytes, got %d\n", + ctrl_req->wLength); + return -EINVAL; } - if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) { - u8 pending_empty = list_empty(&priv_ep->pending_req_list); - u8 descmiss_empty = list_empty(&priv_ep->wa2_descmiss_req_list); - - /* - * DESCMISS transfer has been finished, so data will be - * directly copied from internal allocated usb_request - * objects. - */ - if (pending_empty && !descmiss_empty && - !(priv_req->flags & REQUEST_INTERNAL)) { - cdns3_wa2_descmiss_copy_data(priv_ep, - &priv_req->request); - - trace_cdns3_wa2(priv_ep, "get internal stored data"); - - list_add_tail(&priv_req->request.list, - &priv_ep->pending_req_list); - cdns3_gadget_giveback(priv_ep, priv_req, - priv_req->request.status); - - /* - * Intentionally driver returns positive value as - * correct value. It informs that transfer has - * been finished. - */ - return EINPROGRESS; - } - - /* - * Driver will wait for completion DESCMISS transfer, - * before starts new, not DESCMISS transfer. - */ - if (!pending_empty && !descmiss_empty) { - trace_cdns3_wa2(priv_ep, "wait for pending transfer\n"); - deferred = 1; - } - - if (priv_req->flags & REQUEST_INTERNAL) - list_add_tail(&priv_req->list, - &priv_ep->wa2_descmiss_req_list); - } + usb_ss->ep0_data_dir = 0; + usb_ss->actual_ep0_request = NULL; + cdns_ep0_run_transfer(usb_ss, usb_ss->setup_dma, 6, 1); - return deferred; + return 0; } -static void cdns3_wa2_remove_old_request(struct cdns3_endpoint *priv_ep) +/** + * cdns_req_ep0_set_isoch_delay - + * Handling of GET_ISOCH_DELAY standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, error code on error + */ +static int cdns_req_ep0_set_isoch_delay(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) { - struct cdns3_request *priv_req; - - while (!list_empty(&priv_ep->wa2_descmiss_req_list)) { - u8 chain; - - priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list); - chain = !!(priv_req->flags & REQUEST_INTERNAL_CH); - - trace_cdns3_wa2(priv_ep, "removes eldest request"); - - kfree(priv_req->request.buf); - cdns3_gadget_ep_free_request(&priv_ep->endpoint, - &priv_req->request); - list_del_init(&priv_req->list); - --priv_ep->wa2_counter; + if (ctrl_req->wIndex || ctrl_req->wLength) + return -EINVAL; - if (!chain) - break; - } + usb_ss->isoch_delay = ctrl_req->wValue; + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + return 0; } /** - * cdns3_wa2_descmissing_packet - handles descriptor missing event. - * @priv_dev: extended gadget object + * cdns_req_ep0_set_configuration - Handling of SET_CONFIG standard USB request + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet * - * This function is used only for WA2. For more information see Work around 2 - * description. + * Returns 0 if success, 0x7FFF on deferred status stage, error code on error */ -static void cdns3_wa2_descmissing_packet(struct cdns3_endpoint *priv_ep) +static int cdns_req_ep0_set_configuration(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) { - struct cdns3_request *priv_req; - struct usb_request *request; + enum usb_device_state device_state = usb_ss->gadget.state; + u32 config = le16_to_cpu(ctrl_req->wValue); + struct usb_ep *ep; + struct usb_ss_endpoint *usb_ss_ep, *temp_ss_ep; + int i, result = 0; + + switch (device_state) { + case USB_STATE_ADDRESS: + /* Configure non-control EPs */ + list_for_each_entry_safe(usb_ss_ep, temp_ss_ep, + &usb_ss->ep_match_list, + ep_match_pending_list) { + cdns_ep_config(usb_ss_ep); + list_del(&usb_ss_ep->ep_match_pending_list); + } - if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET) { - priv_ep->flags &= ~EP_QUIRK_EXTRA_BUF_DET; - priv_ep->flags |= EP_QUIRK_EXTRA_BUF_EN; - } + list_for_each_entry(ep, &usb_ss->gadget.ep_list, ep_list) { + usb_ss_ep = to_usb_ss_ep(ep); + if (usb_ss_ep->used) + cdns_ep_config(usb_ss_ep); + } - trace_cdns3_wa2(priv_ep, "Description Missing detected\n"); + result = cdns_get_setup_ret(usb_ss, ctrl_req); + + if (result != 0) + return result; + + if (config) { + if (!usb_ss->hw_configured_flag) { + /* SET CONFIGURATION */ + cdns_writel(&usb_ss->regs->usb_conf, + USB_CONF__CFGSET__MASK); + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | + EP_CMD__REQ_CMPL__MASK); + /* wait until configuration set */ + while (!(cdns_readl(&usb_ss->regs->usb_sts) + & USB_STS__CFGSTS__MASK)) + ; + usb_ss->hw_configured_flag = 1; + + list_for_each_entry(ep, &usb_ss->gadget.ep_list, + ep_list) { + usb_ss_ep = to_usb_ss_ep(ep); + if (usb_ss_ep->enabled) + cdns_ep_run_transfer(usb_ss_ep); + } + } - if (priv_ep->wa2_counter >= CDNS3_WA2_NUM_BUFFERS) - cdns3_wa2_remove_old_request(priv_ep); + usb_gadget_set_state(&usb_ss->gadget, + USB_STATE_CONFIGURED); - request = cdns3_gadget_ep_alloc_request(&priv_ep->endpoint, - GFP_ATOMIC); - if (!request) - goto err; + } else { + cdns_gadget_unconfig(usb_ss); + for (i = 0; i < usb_ss->ep_nums; i++) + usb_ss->eps[i]->enabled = 0; + usb_gadget_set_state(&usb_ss->gadget, + USB_STATE_ADDRESS); + } + break; - priv_req = to_cdns3_request(request); - priv_req->flags |= REQUEST_INTERNAL; + case USB_STATE_CONFIGURED: + result = cdns_get_setup_ret(usb_ss, ctrl_req); + if (!config && !result) { + cdns_gadget_unconfig(usb_ss); + for (i = 0; i < usb_ss->ep_nums; i++) + usb_ss->eps[i]->enabled = 0; + usb_gadget_set_state(&usb_ss->gadget, + USB_STATE_ADDRESS); + } + break; - /* if this field is still assigned it indicate that transfer related - * with this request has not been finished yet. Driver in this - * case simply allocate next request and assign flag REQUEST_INTERNAL_CH - * flag to previous one. It will indicate that current request is - * part of the previous one. - */ - if (priv_ep->descmis_req) - priv_ep->descmis_req->flags |= REQUEST_INTERNAL_CH; + default: + result = -EINVAL; + } - priv_req->request.buf = kzalloc(CDNS3_DESCMIS_BUF_SIZE, - GFP_ATOMIC); - priv_ep->wa2_counter++; + return result; +} - if (!priv_req->request.buf) { - cdns3_gadget_ep_free_request(&priv_ep->endpoint, request); - goto err; +/** + * cdns_ep0_standard_request - Handling standard USB requests + * @usb_ss: extended gadget object + * @ctrl_req: pointer to received setup packet + * + * Returns 0 if success, error code on error + */ +static int cdns_ep0_standard_request(struct usb_ss_dev *usb_ss, + struct usb_ctrlrequest *ctrl_req) +{ + switch (ctrl_req->bRequest) { + case USB_REQ_SET_ADDRESS: + return cdns_req_ep0_set_address(usb_ss, ctrl_req); + case USB_REQ_SET_CONFIGURATION: + return cdns_req_ep0_set_configuration(usb_ss, ctrl_req); + case USB_REQ_GET_STATUS: + return cdns_req_ep0_get_status(usb_ss, ctrl_req); + case USB_REQ_CLEAR_FEATURE: + return cdns_req_ep0_handle_feature(usb_ss, ctrl_req, 0); + case USB_REQ_SET_FEATURE: + return cdns_req_ep0_handle_feature(usb_ss, ctrl_req, 1); + case USB_REQ_SET_SEL: + return cdns_req_ep0_set_sel(usb_ss, ctrl_req); + case USB_REQ_SET_ISOCH_DELAY: + return cdns_req_ep0_set_isoch_delay(usb_ss, ctrl_req); + default: + return cdns_get_setup_ret(usb_ss, ctrl_req); } +} - priv_req->request.length = CDNS3_DESCMIS_BUF_SIZE; - priv_ep->descmis_req = priv_req; +/** + * cdns_ep0_setup_phase - Handling setup USB requests + * @usb_ss: extended gadget object + */ +static void cdns_ep0_setup_phase(struct usb_ss_dev *usb_ss) +{ + int result; + struct usb_ctrlrequest *ctrl_req = + (struct usb_ctrlrequest *)usb_ss->setup; - __cdns3_gadget_ep_queue(&priv_ep->endpoint, - &priv_ep->descmis_req->request, - GFP_ATOMIC); + if ((ctrl_req->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) + result = cdns_ep0_standard_request(usb_ss, ctrl_req); + else + result = cdns_get_setup_ret(usb_ss, ctrl_req); - return; + if (result != 0 && result != USB_GADGET_DELAYED_STATUS) { + dev_dbg(&usb_ss->dev, "STALL(00) %d\n", result); -err: - dev_err(priv_ep->cdns3_dev->dev, - "Failed: No sufficient memory for DESCMIS\n"); + /* set_stall on ep0 */ + select_ep(usb_ss, 0x00); + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__SSTALL__MASK); + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK | EP_CMD__REQ_CMPL__MASK); + return; + } } /** - * cdns3_gadget_giveback - call struct usb_request's ->complete callback - * @priv_ep: The endpoint to whom the request belongs to - * @priv_req: The request we're giving back - * @status: completion code for the request + * cdns_check_ep_interrupt_proceed - Processes interrupt related to endpoint + * @usb_ss_ep: extended endpoint object * - * Must be called with controller's lock held and interrupts disabled. This - * function will unmap @req and call its ->complete() callback to notify upper - * layers that it has completed. + * Returns 0 */ -void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep, - struct cdns3_request *priv_req, - int status) +static int cdns_check_ep_interrupt_proceed(struct usb_ss_endpoint *usb_ss_ep) { - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - struct usb_request *request = &priv_req->request; + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + struct usb_request *request; + u32 ep_sts_reg; - list_del_init(&request->list); + select_ep(usb_ss, usb_ss_ep->address); + ep_sts_reg = cdns_readl(&usb_ss->regs->ep_sts); - if (request->status == -EINPROGRESS) - request->status = status; + dev_dbg(&usb_ss->dev, "EP_STS: %08X\n", ep_sts_reg); - usb_gadget_unmap_request(&priv_dev->gadget, request, - priv_ep->dir); + if (ep_sts_reg & EP_STS__TRBERR__MASK) { + cdns_writel(&usb_ss->regs->ep_sts, EP_STS__TRBERR__MASK); - if ((priv_req->flags & REQUEST_UNALIGNED) && - priv_ep->dir == USB_DIR_OUT && !request->status) - memcpy(request->buf, priv_req->aligned_buf->buf, - request->length); + dev_dbg(&usb_ss->dev, "TRBERR(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); + } - priv_req->flags &= ~(REQUEST_PENDING | REQUEST_UNALIGNED); - trace_cdns3_gadget_giveback(priv_req); + if (ep_sts_reg & EP_STS__ISOERR__MASK) { + cdns_writel(&usb_ss->regs->ep_sts, EP_STS__ISOERR__MASK); + dev_dbg(&usb_ss->dev, "ISOERR(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); + } - if (priv_dev->dev_ver < DEV_VER_V2) { - request = cdns3_wa2_gadget_giveback(priv_dev, priv_ep, - priv_req); - if (!request) - return; + if (ep_sts_reg & EP_STS__OUTSMM__MASK) { + cdns_writel(&usb_ss->regs->ep_sts, EP_STS__OUTSMM__MASK); + dev_dbg(&usb_ss->dev, "OUTSMM(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); } - if (request->complete) { - spin_unlock(&priv_dev->lock); - usb_gadget_giveback_request(&priv_ep->endpoint, - request); - spin_lock(&priv_dev->lock); + if (ep_sts_reg & EP_STS__NRDY__MASK) { + cdns_writel(&usb_ss->regs->ep_sts, EP_STS__NRDY__MASK); + dev_dbg(&usb_ss->dev, "NRDY(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); } - if (request->buf == priv_dev->zlp_buf) - cdns3_gadget_ep_free_request(&priv_ep->endpoint, request); -} + if ((ep_sts_reg & EP_STS__IOC__MASK) || + (ep_sts_reg & EP_STS__ISP__MASK)) { + u8 ep_dir; -void cdns3_wa1_restore_cycle_bit(struct cdns3_endpoint *priv_ep) -{ - /* Work around for stale data address in TRB*/ - if (priv_ep->wa1_set) { - trace_cdns3_wa1(priv_ep, "restore cycle bit"); - - priv_ep->wa1_set = 0; - priv_ep->wa1_trb_index = 0xFFFF; - if (priv_ep->wa1_cycle_bit) { - priv_ep->wa1_trb->control = - priv_ep->wa1_trb->control | 0x1; - } else { - priv_ep->wa1_trb->control = - priv_ep->wa1_trb->control & ~0x1; - } - } -} + cdns_flush_cache((uintptr_t)usb_ss_ep->trb_pool, + sizeof(struct usb_ss_trb)); -static void cdns3_free_aligned_request_buf(struct cdns3_device *priv_dev) -{ - struct cdns3_aligned_buf *buf, *tmp; - unsigned long flags; - - spin_lock_irqsave(&priv_dev->lock, flags); - - list_for_each_entry_safe(buf, tmp, &priv_dev->aligned_buf_list, list) { - if (!buf->in_use) { - list_del(&buf->list); - - /* - * Re-enable interrupts to free DMA capable memory. - * Driver can't free this memory with disabled - * interrupts. - */ - spin_unlock_irqrestore(&priv_dev->lock, flags); - dma_free_coherent(buf->buf); - kfree(buf); - spin_lock_irqsave(&priv_dev->lock, flags); - } - } - - spin_unlock_irqrestore(&priv_dev->lock, flags); -} + cdns_writel(&usb_ss->regs->ep_sts, + EP_STS__IOC__MASK | EP_STS__ISP__MASK); -static int cdns3_prepare_aligned_request_buf(struct cdns3_request *priv_req) -{ - struct cdns3_endpoint *priv_ep = priv_req->priv_ep; - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - struct cdns3_aligned_buf *buf; - - /* check if buffer is aligned to 8. */ - if (!((uintptr_t)priv_req->request.buf & 0x7)) - return 0; + /* get just completed request */ + request = next_request(&usb_ss_ep->request_list); + ep_dir = usb_ss_ep->endpoint.desc->bEndpointAddress; + cdns_flush_cache((uintptr_t)request->dma, request->length); + usb_gadget_unmap_request(&usb_ss->gadget, request, + ep_dir & ENDPOINT_DIR_MASK); - buf = priv_req->aligned_buf; + request->status = 0; + request->actual = + le32_to_cpu(((u32 *)usb_ss_ep->trb_pool)[1]) + & ACTUAL_TRANSFERRED_BYTES_MASK; - if (!buf || priv_req->request.length > buf->size) { - buf = kzalloc(sizeof(*buf), GFP_ATOMIC); - if (!buf) - return -ENOMEM; + dev_dbg(&usb_ss->dev, "IOC(%02X) %d\n", + usb_ss_ep->endpoint.desc->bEndpointAddress, + request->actual); - buf->size = priv_req->request.length; - - buf->buf = dma_alloc_coherent(buf->size, - (unsigned long *)&buf->dma); - if (!buf->buf) { - kfree(buf); - return -ENOMEM; - } + list_del(&request->list); - if (priv_req->aligned_buf) { - trace_cdns3_free_aligned_request(priv_req); - priv_req->aligned_buf->in_use = 0; -#ifndef __UBOOT__ - queue_work(system_freezable_wq, - &priv_dev->aligned_buf_wq); -#else - cdns3_free_aligned_request_buf(priv_dev); -#endif + usb_ss_ep->hw_pending_flag = 0; + if (request->complete) { + spin_unlock(&usb_ss->lock); + usb_gadget_giveback_request(&usb_ss_ep->endpoint, + request); + spin_lock(&usb_ss->lock); } - buf->in_use = 1; - priv_req->aligned_buf = buf; - - list_add_tail(&buf->list, - &priv_dev->aligned_buf_list); - } - - if (priv_ep->dir == USB_DIR_IN) { - memcpy(buf->buf, priv_req->request.buf, - priv_req->request.length); - } - - priv_req->flags |= REQUEST_UNALIGNED; - trace_cdns3_prepare_aligned_request(priv_req); - - return 0; -} - -static int cdns3_wa1_update_guard(struct cdns3_endpoint *priv_ep, - struct cdns3_trb *trb) -{ - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - - if (!priv_ep->wa1_set) { - u32 doorbell; - - doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); - - if (doorbell) { - priv_ep->wa1_cycle_bit = priv_ep->pcs ? TRB_CYCLE : 0; - priv_ep->wa1_set = 1; - priv_ep->wa1_trb = trb; - priv_ep->wa1_trb_index = priv_ep->enqueue; - trace_cdns3_wa1(priv_ep, "set guard"); + /* handle deferred STALL */ + if (usb_ss_ep->stalled_flag) { + cdns_ep_stall_flush(usb_ss_ep); return 0; } - } - return 1; -} - -static void cdns3_wa1_tray_restore_cycle_bit(struct cdns3_device *priv_dev, - struct cdns3_endpoint *priv_ep) -{ - int dma_index; - u32 doorbell; - - doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); - dma_index = cdns3_get_dma_pos(priv_dev, priv_ep); - - if (!doorbell || dma_index != priv_ep->wa1_trb_index) - cdns3_wa1_restore_cycle_bit(priv_ep); -} - -/** - * cdns3_ep_run_transfer - start transfer on no-default endpoint hardware - * @priv_ep: endpoint object - * - * Returns zero on success or negative value on failure - */ -int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep, - struct usb_request *request) -{ - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - struct cdns3_request *priv_req; - struct cdns3_trb *trb; - dma_addr_t trb_dma; - u32 togle_pcs = 1; - int sg_iter = 0; - int num_trb = 1; - int address; - u32 control; - int pcs; - - if (num_trb > priv_ep->free_trbs) { - priv_ep->flags |= EP_RING_FULL; - return -ENOBUFS; - } - - priv_req = to_cdns3_request(request); - address = priv_ep->endpoint.desc->bEndpointAddress; - - priv_ep->flags |= EP_PENDING_REQUEST; - - /* must allocate buffer aligned to 8 */ - if (priv_req->flags & REQUEST_UNALIGNED) - trb_dma = priv_req->aligned_buf->dma; - else - trb_dma = request->dma; - - trb = priv_ep->trb_pool + priv_ep->enqueue; - priv_req->start_trb = priv_ep->enqueue; - priv_req->trb = trb; - - cdns3_select_ep(priv_ep->cdns3_dev, address); - - /* prepare ring */ - if ((priv_ep->enqueue + num_trb) >= (priv_ep->num_trbs - 1)) { - struct cdns3_trb *link_trb; - int doorbell, dma_index; - u32 ch_bit = 0; - - doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); - dma_index = cdns3_get_dma_pos(priv_dev, priv_ep); - - /* Driver can't update LINK TRB if it is current processed. */ - if (doorbell && dma_index == priv_ep->num_trbs - 1) { - priv_ep->flags |= EP_DEFERRED_DRDY; - return -ENOBUFS; - } - - /*updating C bt in Link TRB before starting DMA*/ - link_trb = priv_ep->trb_pool + (priv_ep->num_trbs - 1); - /* - * For TRs size equal 2 enabling TRB_CHAIN for epXin causes - * that DMA stuck at the LINK TRB. - * On the other hand, removing TRB_CHAIN for longer TRs for - * epXout cause that DMA stuck after handling LINK TRB. - * To eliminate this strange behavioral driver set TRB_CHAIN - * bit only for TR size > 2. - */ - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC || - TRBS_PER_SEGMENT > 2) - ch_bit = TRB_CHAIN; - - link_trb->control = ((priv_ep->pcs) ? TRB_CYCLE : 0) | - TRB_TYPE(TRB_LINK) | TRB_TOGGLE | ch_bit; - } - - if (priv_dev->dev_ver <= DEV_VER_V2) - togle_pcs = cdns3_wa1_update_guard(priv_ep, trb); - - /* set incorrect Cycle Bit for first trb*/ - control = priv_ep->pcs ? 0 : TRB_CYCLE; - - do { - u32 length; - u16 td_size = 0; - - /* fill TRB */ - control |= TRB_TYPE(TRB_NORMAL); - trb->buffer = TRB_BUFFER(trb_dma); - - length = request->length; - - if (likely(priv_dev->dev_ver >= DEV_VER_V2)) - td_size = DIV_ROUND_UP(length, - priv_ep->endpoint.maxpacket); - - trb->length = TRB_BURST_LEN(priv_ep->trb_burst_size) | - TRB_LEN(length); - if (priv_dev->gadget.speed == USB_SPEED_SUPER) - trb->length |= TRB_TDL_SS_SIZE(td_size); - else - control |= TRB_TDL_HS_SIZE(td_size); - - pcs = priv_ep->pcs ? TRB_CYCLE : 0; - - /* - * first trb should be prepared as last to avoid processing - * transfer to early - */ - if (sg_iter != 0) - control |= pcs; - - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) { - control |= TRB_IOC | TRB_ISP; - } else { - /* for last element in TD or in SG list */ - if (sg_iter == (num_trb - 1) && sg_iter != 0) - control |= pcs | TRB_IOC | TRB_ISP; - } - - if (sg_iter) - trb->control = control; - else - priv_req->trb->control = control; - - control = 0; - ++sg_iter; - priv_req->end_trb = priv_ep->enqueue; - cdns3_ep_inc_enq(priv_ep); - trb = priv_ep->trb_pool + priv_ep->enqueue; - } while (sg_iter < num_trb); - - trb = priv_req->trb; - - priv_req->flags |= REQUEST_PENDING; - - if (sg_iter == 1) - trb->control |= TRB_IOC | TRB_ISP; - /* - * Memory barrier - cycle bit must be set before other filds in trb. - */ - dmb(); - - /* give the TD to the consumer*/ - if (togle_pcs) - trb->control = trb->control ^ 1; - - if (priv_dev->dev_ver <= DEV_VER_V2) - cdns3_wa1_tray_restore_cycle_bit(priv_dev, priv_ep); - - trace_cdns3_prepare_trb(priv_ep, priv_req->trb); - - /* - * Memory barrier - Cycle Bit must be set before trb->length and - * trb->buffer fields. - */ - dmb(); - - /* - * For DMULT mode we can set address to transfer ring only once after - * enabling endpoint. - */ - if (priv_ep->flags & EP_UPDATE_EP_TRBADDR) { - /* - * Until SW is not ready to handle the OUT transfer the ISO OUT - * Endpoint should be disabled (EP_CFG.ENABLE = 0). - * EP_CFG_ENABLE must be set before updating ep_traddr. - */ - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir && - !(priv_ep->flags & EP_QUIRK_ISO_OUT_EN)) { - priv_ep->flags |= EP_QUIRK_ISO_OUT_EN; - cdns3_set_register_bit(&priv_dev->regs->ep_cfg, - EP_CFG_ENABLE); - } - - writel(EP_TRADDR_TRADDR(priv_ep->trb_pool_dma + - priv_req->start_trb * TRB_SIZE), - &priv_dev->regs->ep_traddr); + /* exit if hardware transfer already started */ + if (usb_ss_ep->hw_pending_flag) + return 0; - priv_ep->flags &= ~EP_UPDATE_EP_TRBADDR; + /* if any request queued run it! */ + if (!list_empty(&usb_ss_ep->request_list)) + cdns_ep_run_transfer(usb_ss_ep); } - if (!priv_ep->wa1_set && !(priv_ep->flags & EP_STALLED)) { - trace_cdns3_ring(priv_ep); - /*clearing TRBERR and EP_STS_DESCMIS before seting DRDY*/ - writel(EP_STS_TRBERR | EP_STS_DESCMIS, &priv_dev->regs->ep_sts); - writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd); - trace_cdns3_doorbell_epx(priv_ep->name, - readl(&priv_dev->regs->ep_traddr)); + if (ep_sts_reg & EP_STS__DESCMIS__MASK) { + cdns_writel(&usb_ss->regs->ep_sts, EP_STS__DESCMIS__MASK); + dev_dbg(&usb_ss->dev, "DESCMIS(%02X)\n", + usb_ss_ep->endpoint.desc->bEndpointAddress); } - /* WORKAROUND for transition to L0 */ - __cdns3_gadget_wakeup(priv_dev); - return 0; } -void cdns3_set_hw_configuration(struct cdns3_device *priv_dev) -{ - struct cdns3_endpoint *priv_ep; - struct usb_ep *ep; - int val; - - if (priv_dev->hw_configured_flag) - return; - - writel(USB_CONF_CFGSET, &priv_dev->regs->usb_conf); - writel(EP_CMD_ERDY | EP_CMD_REQ_CMPL, &priv_dev->regs->ep_cmd); - - cdns3_set_register_bit(&priv_dev->regs->usb_conf, - USB_CONF_U1EN | USB_CONF_U2EN); - - /* wait until configuration set */ - readl_poll_timeout_atomic(&priv_dev->regs->usb_sts, val, - val & USB_STS_CFGSTS_MASK, 100); - - priv_dev->hw_configured_flag = 1; - - list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) { - priv_ep = ep_to_cdns3_ep(ep); - if (priv_ep->flags & EP_ENABLED) - cdns3_start_all_request(priv_dev, priv_ep); - } -} - /** - * cdns3_request_handled - check whether request has been handled by DMA - * - * @priv_ep: extended endpoint object. - * @priv_req: request object for checking - * - * Endpoint must be selected before invoking this function. - * - * Returns false if request has not been handled by DMA, else returns true. - * - * SR - start ring - * ER - end ring - * DQ = priv_ep->dequeue - dequeue position - * EQ = priv_ep->enqueue - enqueue position - * ST = priv_req->start_trb - index of first TRB in transfer ring - * ET = priv_req->end_trb - index of last TRB in transfer ring - * CI = current_index - index of processed TRB by DMA. - * - * As first step, function checks if cycle bit for priv_req->start_trb is - * correct. - * - * some rules: - * 1. priv_ep->dequeue never exceed current_index. - * 2 priv_ep->enqueue never exceed priv_ep->dequeue - * 3. exception: priv_ep->enqueue == priv_ep->dequeue - * and priv_ep->free_trbs is zero. - * This case indicate that TR is full. - * - * Then We can split recognition into two parts: - * Case 1 - priv_ep->dequeue < current_index - * SR ... EQ ... DQ ... CI ... ER - * SR ... DQ ... CI ... EQ ... ER - * - * Request has been handled by DMA if ST and ET is between DQ and CI. - * - * Case 2 - priv_ep->dequeue > current_index - * This situation take place when CI go through the LINK TRB at the end of - * transfer ring. - * SR ... CI ... EQ ... DQ ... ER - * - * Request has been handled by DMA if ET is less then CI or - * ET is greater or equal DQ. + * cdns_check_ep0_interrupt_proceed - Processes interrupt related to endpoint 0 + * @usb_ss: extended gadget object + * @dir: 1 for IN direction, 0 for OUT direction */ -static bool cdns3_request_handled(struct cdns3_endpoint *priv_ep, - struct cdns3_request *priv_req) +static void cdns_check_ep0_interrupt_proceed(struct usb_ss_dev *usb_ss, int dir) { - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - struct cdns3_trb *trb = priv_req->trb; - int current_index = 0; - int handled = 0; - int doorbell; + u32 ep_sts_reg; + int i; - current_index = cdns3_get_dma_pos(priv_dev, priv_ep); - doorbell = !!(readl(&priv_dev->regs->ep_cmd) & EP_CMD_DRDY); + select_ep(usb_ss, 0 | (dir ? USB_DIR_IN : USB_DIR_OUT)); + ep_sts_reg = cdns_readl(&usb_ss->regs->ep_sts); - trb = &priv_ep->trb_pool[priv_req->start_trb]; + dev_dbg(&usb_ss->dev, "EP_STS: %08X\n", ep_sts_reg); - if ((trb->control & TRB_CYCLE) != priv_ep->ccs) - goto finish; + if ((ep_sts_reg & EP_STS__SETUP__MASK) && dir == 0) { + cdns_flush_cache((uintptr_t)usb_ss->setup, 8); - if (doorbell == 1 && current_index == priv_ep->dequeue) - goto finish; + dev_dbg(&usb_ss->dev, "SETUP(%02X)\n", 0x00); - /* The corner case for TRBS_PER_SEGMENT equal 2). */ - if (TRBS_PER_SEGMENT == 2 && priv_ep->type != USB_ENDPOINT_XFER_ISOC) { - handled = 1; - goto finish; - } + cdns_writel(&usb_ss->regs->ep_sts, + EP_STS__SETUP__MASK | + EP_STS__IOC__MASK | EP_STS__ISP__MASK); - if (priv_ep->enqueue == priv_ep->dequeue && - priv_ep->free_trbs == 0) { - handled = 1; - } else if (priv_ep->dequeue < current_index) { - if ((current_index == (priv_ep->num_trbs - 1)) && - !priv_ep->dequeue) - goto finish; - - if (priv_req->end_trb >= priv_ep->dequeue && - priv_req->end_trb < current_index) - handled = 1; - } else if (priv_ep->dequeue > current_index) { - if (priv_req->end_trb < current_index || - priv_req->end_trb >= priv_ep->dequeue) - handled = 1; + dev_dbg(&usb_ss->dev, "SETUP: "); + for (i = 0; i < 8; i++) + dev_dbg(&usb_ss->dev, "%02X ", usb_ss->setup[i]); + dev_dbg(&usb_ss->dev, "\nSTATE: %d\n", usb_ss->gadget.state); + usb_ss->ep0_data_dir = usb_ss->setup[0] & USB_DIR_IN; + cdns_ep0_setup_phase(usb_ss); + ep_sts_reg &= ~(EP_STS__SETUP__MASK | + EP_STS__IOC__MASK | + EP_STS__ISP__MASK); } -finish: - trace_cdns3_request_handled(priv_req, current_index, handled); - - return handled; -} - -static void cdns3_transfer_completed(struct cdns3_device *priv_dev, - struct cdns3_endpoint *priv_ep) -{ - struct cdns3_request *priv_req; - struct usb_request *request; - struct cdns3_trb *trb; - - while (!list_empty(&priv_ep->pending_req_list)) { - request = cdns3_next_request(&priv_ep->pending_req_list); - priv_req = to_cdns3_request(request); - - /* Re-select endpoint. It could be changed by other CPU during - * handling usb_gadget_giveback_request. - */ -#ifndef __UBOOT__ - cdns3_select_ep(priv_dev, priv_ep->endpoint.address); -#else - cdns3_select_ep(priv_dev, - priv_ep->endpoint.desc->bEndpointAddress); -#endif - - if (!cdns3_request_handled(priv_ep, priv_req)) - goto prepare_next_td; - - trb = priv_ep->trb_pool + priv_ep->dequeue; - trace_cdns3_complete_trb(priv_ep, trb); - - if (trb != priv_req->trb) - dev_warn(priv_dev->dev, - "request_trb=0x%p, queue_trb=0x%p\n", - priv_req->trb, trb); - - request->actual = TRB_LEN(le32_to_cpu(trb->length)); - cdns3_move_deq_to_next_trb(priv_req); - cdns3_gadget_giveback(priv_ep, priv_req, 0); - - if (priv_ep->type != USB_ENDPOINT_XFER_ISOC && - TRBS_PER_SEGMENT == 2) - break; + if (ep_sts_reg & EP_STS__TRBERR__MASK) { + cdns_writel(&usb_ss->regs->ep_sts, EP_STS__TRBERR__MASK); + dev_dbg(&usb_ss->dev, "TRBERR(%02X)\n", + dir ? USB_DIR_IN : USB_DIR_OUT); } - priv_ep->flags &= ~EP_PENDING_REQUEST; -prepare_next_td: - if (!(priv_ep->flags & EP_STALLED) && - !(priv_ep->flags & EP_STALL_PENDING)) - cdns3_start_all_request(priv_dev, priv_ep); -} + if (ep_sts_reg & EP_STS__DESCMIS__MASK) { + cdns_writel(&usb_ss->regs->ep_sts, EP_STS__DESCMIS__MASK); -void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm) -{ - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - - cdns3_wa1_restore_cycle_bit(priv_ep); - - if (rearm) { - trace_cdns3_ring(priv_ep); - - /* Cycle Bit must be updated before arming DMA. */ - dmb(); - writel(EP_CMD_DRDY, &priv_dev->regs->ep_cmd); + dev_dbg(&usb_ss->dev, "DESCMIS(%02X)\n", + dir ? USB_DIR_IN : USB_DIR_OUT); - __cdns3_gadget_wakeup(priv_dev); - - trace_cdns3_doorbell_epx(priv_ep->name, - readl(&priv_dev->regs->ep_traddr)); + if (dir == 0 && !usb_ss->setup_pending) { + usb_ss->ep0_data_dir = 0; + cdns_ep0_run_transfer(usb_ss, + usb_ss->setup_dma, 8, 0); + } } -} -/** - * cdns3_check_ep_interrupt_proceed - Processes interrupt related to endpoint - * @priv_ep: endpoint object - * - * Returns 0 - */ -static int cdns3_check_ep_interrupt_proceed(struct cdns3_endpoint *priv_ep) -{ - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - u32 ep_sts_reg; + if ((ep_sts_reg & EP_STS__IOC__MASK) || + (ep_sts_reg & EP_STS__ISP__MASK)) { + cdns_flush_cache((uintptr_t)usb_ss->trb_ep0, 20); -#ifndef __UBOOT__ - cdns3_select_ep(priv_dev, priv_ep->endpoint.address); -#else - cdns3_select_ep(priv_dev, priv_ep->endpoint.desc->bEndpointAddress); -#endif + cdns_writel(&usb_ss->regs->ep_sts, EP_STS__IOC__MASK); + if (usb_ss->actual_ep0_request) { + usb_gadget_unmap_request(&usb_ss->gadget, + usb_ss->actual_ep0_request, + usb_ss->ep0_data_dir); - trace_cdns3_epx_irq(priv_dev, priv_ep); + usb_ss->actual_ep0_request->actual = + le32_to_cpu((usb_ss->trb_ep0)[1]) + & ACTUAL_TRANSFERRED_BYTES_MASK; - ep_sts_reg = readl(&priv_dev->regs->ep_sts); - writel(ep_sts_reg, &priv_dev->regs->ep_sts); - - if (ep_sts_reg & EP_STS_TRBERR) { - if (priv_ep->flags & EP_STALL_PENDING && - !(ep_sts_reg & EP_STS_DESCMIS && - priv_dev->dev_ver < DEV_VER_V2)) { - cdns3_ep_stall_flush(priv_ep); + dev_dbg(&usb_ss->dev, "IOC(%02X) %d\n", + dir ? USB_DIR_IN : USB_DIR_OUT, + usb_ss->actual_ep0_request->actual); + list_del_init(&usb_ss->actual_ep0_request->list); } - /* - * For isochronous transfer driver completes request on - * IOC or on TRBERR. IOC appears only when device receive - * OUT data packet. If host disable stream or lost some packet - * then the only way to finish all queued transfer is to do it - * on TRBERR event. - */ - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && - !priv_ep->wa1_set) { - if (!priv_ep->dir) { - u32 ep_cfg = readl(&priv_dev->regs->ep_cfg); - - ep_cfg &= ~EP_CFG_ENABLE; - writel(ep_cfg, &priv_dev->regs->ep_cfg); - priv_ep->flags &= ~EP_QUIRK_ISO_OUT_EN; - } - cdns3_transfer_completed(priv_dev, priv_ep); - } else if (!(priv_ep->flags & EP_STALLED) && - !(priv_ep->flags & EP_STALL_PENDING)) { - if (priv_ep->flags & EP_DEFERRED_DRDY) { - priv_ep->flags &= ~EP_DEFERRED_DRDY; - cdns3_start_all_request(priv_dev, priv_ep); - } else { - cdns3_rearm_transfer(priv_ep, - priv_ep->wa1_set); - } + if (usb_ss->actual_ep0_request && + usb_ss->actual_ep0_request->complete) { + spin_unlock(&usb_ss->lock); + usb_ss->actual_ep0_request->complete(usb_ss->gadget.ep0, + usb_ss->actual_ep0_request); + spin_lock(&usb_ss->lock); } - } - - if ((ep_sts_reg & EP_STS_IOC) || (ep_sts_reg & EP_STS_ISP)) { - if (priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN) { - if (ep_sts_reg & EP_STS_ISP) - priv_ep->flags |= EP_QUIRK_END_TRANSFER; - else - priv_ep->flags &= ~EP_QUIRK_END_TRANSFER; - } - - cdns3_transfer_completed(priv_dev, priv_ep); - } - - /* - * WA2: this condition should only be meet when - * priv_ep->flags & EP_QUIRK_EXTRA_BUF_DET or - * priv_ep->flags & EP_QUIRK_EXTRA_BUF_EN. - * In other cases this interrupt will be disabled/ - */ - if (ep_sts_reg & EP_STS_DESCMIS && priv_dev->dev_ver < DEV_VER_V2 && - !(priv_ep->flags & EP_STALLED)) - cdns3_wa2_descmissing_packet(priv_ep); - - return 0; -} - -static void cdns3_disconnect_gadget(struct cdns3_device *priv_dev) -{ - if (priv_dev->gadget_driver && priv_dev->gadget_driver->disconnect) { - spin_unlock(&priv_dev->lock); - priv_dev->gadget_driver->disconnect(&priv_dev->gadget); - spin_lock(&priv_dev->lock); + cdns_prepare_setup_packet(usb_ss); + cdns_writel(&usb_ss->regs->ep_cmd, EP_CMD__REQ_CMPL__MASK); } } /** - * cdns3_check_usb_interrupt_proceed - Processes interrupt related to device - * @priv_dev: extended gadget object + * cdns_check_usb_interrupt_proceed - Processes interrupt related to device + * @usb_ss: extended gadget object * @usb_ists: bitmap representation of device's reported interrupts * (usb_ists register value) */ -static void cdns3_check_usb_interrupt_proceed(struct cdns3_device *priv_dev, - u32 usb_ists) -{ - int speed = 0; - - trace_cdns3_usb_irq(priv_dev, usb_ists); - if (usb_ists & USB_ISTS_L1ENTI) { - /* - * WORKAROUND: CDNS3 controller has issue with hardware resuming - * from L1. To fix it, if any DMA transfer is pending driver - * must starts driving resume signal immediately. - */ - if (readl(&priv_dev->regs->drbl)) - __cdns3_gadget_wakeup(priv_dev); - } - - /* Connection detected */ - if (usb_ists & (USB_ISTS_CON2I | USB_ISTS_CONI)) { - speed = cdns3_get_speed(priv_dev); - priv_dev->gadget.speed = speed; - usb_gadget_set_state(&priv_dev->gadget, USB_STATE_POWERED); - cdns3_ep0_config(priv_dev); - } - - /* Disconnection detected */ - if (usb_ists & (USB_ISTS_DIS2I | USB_ISTS_DISI)) { - cdns3_disconnect_gadget(priv_dev); - priv_dev->gadget.speed = USB_SPEED_UNKNOWN; - usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED); - cdns3_hw_reset_eps_config(priv_dev); - } - - if (usb_ists & (USB_ISTS_L2ENTI | USB_ISTS_U3ENTI)) { - if (priv_dev->gadget_driver && - priv_dev->gadget_driver->suspend) { - spin_unlock(&priv_dev->lock); - priv_dev->gadget_driver->suspend(&priv_dev->gadget); - spin_lock(&priv_dev->lock); - } - } +static void cdns_check_usb_interrupt_proceed(struct usb_ss_dev *usb_ss, + u32 usb_ists) +{ + int interrupt_bit = ffs(usb_ists) - 1; + int speed; + u32 val; + + dev_dbg(&usb_ss->dev, "USB interrupt detected\n"); + + switch (interrupt_bit) { + case USB_ISTS__CON2I__SHIFT: + /* FS/HS Connection detected */ + dev_dbg(&usb_ss->dev, + "[Interrupt] FS/HS Connection detected\n"); + val = cdns_readl(&usb_ss->regs->usb_sts); + speed = USB_STS__USBSPEED__READ(val); + if (speed == USB_SPEED_WIRELESS) + speed = USB_SPEED_SUPER; + dev_dbg(&usb_ss->dev, "Speed value: %s (%d), usbsts:0x%x\n", + usb_speed_string(speed), speed, val); + usb_ss->gadget.speed = speed; + usb_ss->is_connected = 1; + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_POWERED); + cdns_ep0_config(usb_ss); + break; - if (usb_ists & (USB_ISTS_L2EXTI | USB_ISTS_U3EXTI)) { - if (priv_dev->gadget_driver && - priv_dev->gadget_driver->resume) { - spin_unlock(&priv_dev->lock); - priv_dev->gadget_driver->resume(&priv_dev->gadget); - spin_lock(&priv_dev->lock); - } - } + case USB_ISTS__CONI__SHIFT: + /* SS Connection detected */ + dev_dbg(&usb_ss->dev, "[Interrupt] SS Connection detected\n"); + val = cdns_readl(&usb_ss->regs->usb_sts); + speed = USB_STS__USBSPEED__READ(val); + if (speed == USB_SPEED_WIRELESS) + speed = USB_SPEED_SUPER; + dev_dbg(&usb_ss->dev, "Speed value: %s (%d), usbsts:0x%x\n", + usb_speed_string(speed), speed, val); + usb_ss->gadget.speed = speed; + usb_ss->is_connected = 1; + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_POWERED); + cdns_ep0_config(usb_ss); + break; - /* reset*/ - if (usb_ists & (USB_ISTS_UWRESI | USB_ISTS_UHRESI | USB_ISTS_U2RESI)) { - if (priv_dev->gadget_driver) { - spin_unlock(&priv_dev->lock); - usb_gadget_udc_reset(&priv_dev->gadget, - priv_dev->gadget_driver); - spin_lock(&priv_dev->lock); - - /*read again to check the actual speed*/ - speed = cdns3_get_speed(priv_dev); - priv_dev->gadget.speed = speed; - cdns3_hw_reset_eps_config(priv_dev); - cdns3_ep0_config(priv_dev); + case USB_ISTS__DIS2I__SHIFT: + case USB_ISTS__DISI__SHIFT: + /* SS Disconnection detected */ + val = cdns_readl(&usb_ss->regs->usb_sts); + dev_dbg(&usb_ss->dev, + "[Interrupt] Disconnection detected: usbsts:0x%x\n", + val); + if (usb_ss->gadget_driver && + usb_ss->gadget_driver->disconnect) { + spin_unlock(&usb_ss->lock); + usb_ss->gadget_driver->disconnect(&usb_ss->gadget); + spin_lock(&usb_ss->lock); } - } -} - -/** - * cdns3_device_irq_handler- interrupt handler for device part of controller - * - * @irq: irq number for cdns3 core device - * @data: structure of cdns3 - * - * Returns IRQ_HANDLED or IRQ_NONE - */ -static irqreturn_t cdns3_device_irq_handler(int irq, void *data) -{ - struct cdns3_device *priv_dev; - struct cdns3 *cdns = data; - irqreturn_t ret = IRQ_NONE; - u32 reg; + usb_ss->gadget.speed = USB_SPEED_UNKNOWN; + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_NOTATTACHED); + usb_ss->is_connected = 0; + cdns_gadget_unconfig(usb_ss); + break; - priv_dev = cdns->gadget_dev; + case USB_ISTS__L2ENTI__SHIFT: + dev_dbg(&usb_ss->dev, + "[Interrupt] Device suspended\n"); + break; - /* check USB device interrupt */ - reg = readl(&priv_dev->regs->usb_ists); - if (reg) { - /* After masking interrupts the new interrupts won't be - * reported in usb_ists/ep_ists. In order to not lose some - * of them driver disables only detected interrupts. - * They will be enabled ASAP after clearing source of - * interrupt. This an unusual behavior only applies to - * usb_ists register. + case USB_ISTS__L2EXTI__SHIFT: + dev_dbg(&usb_ss->dev, "[Interrupt] L2 exit detected\n"); + /* + * Exit from standby mode + * on L2 exit (Suspend in HS/FS or SS) */ - reg = ~reg & readl(&priv_dev->regs->usb_ien); - /* mask deferred interrupt. */ - writel(reg, &priv_dev->regs->usb_ien); - ret = IRQ_WAKE_THREAD; - } + break; + case USB_ISTS__U3EXTI__SHIFT: + /* + * Exit from standby mode + * on U3 exit (Suspend in HS/FS or SS) + */ + dev_dbg(&usb_ss->dev, "[Interrupt] U3 exit detected\n"); + break; - /* check endpoint interrupt */ - reg = readl(&priv_dev->regs->ep_ists); - if (reg) { - writel(0, &priv_dev->regs->ep_ien); - ret = IRQ_WAKE_THREAD; + /* resets cases */ + case USB_ISTS__UWRESI__SHIFT: + case USB_ISTS__UHRESI__SHIFT: + case USB_ISTS__U2RESI__SHIFT: + dev_dbg(&usb_ss->dev, "[Interrupt] Reset detected\n"); + val = cdns_readl(&usb_ss->regs->usb_sts); + speed = USB_STS__USBSPEED__READ(val); + if (speed == USB_SPEED_WIRELESS) + speed = USB_SPEED_SUPER; + usb_gadget_set_state(&usb_ss->gadget, USB_STATE_DEFAULT); + usb_ss->gadget.speed = speed; + cdns_gadget_unconfig(usb_ss); + cdns_ep0_config(usb_ss); + break; + default: + break; } - return ret; + /* Clear interrupt bit */ + cdns_writel(&usb_ss->regs->usb_ists, (1uL << interrupt_bit)); } /** - * cdns3_device_thread_irq_handler- interrupt handler for device part - * of controller - * - * @irq: irq number for cdns3 core device - * @data: structure of cdns3 + * cdns_irq_handler - irq line interrupt handler + * @cdns: cdns3 instance * - * Returns IRQ_HANDLED or IRQ_NONE + * Returns IRQ_HANDLED when interrupt raised by USBSS_DEV, + * IRQ_NONE when interrupt raised by other device connected + * to the irq line */ -static irqreturn_t cdns3_device_thread_irq_handler(int irq, void *data) +static int cdns_irq_handler_thread(struct cdns3 *cdns) { - struct cdns3_device *priv_dev; - struct cdns3 *cdns = data; - irqreturn_t ret = IRQ_NONE; - unsigned long flags; - int bit; + struct usb_ss_dev *usb_ss = + container_of(cdns->gadget_dev, struct usb_ss_dev, dev); u32 reg; + int ret = IRQ_NONE; + unsigned long flags; - priv_dev = cdns->gadget_dev; - spin_lock_irqsave(&priv_dev->lock, flags); + spin_lock_irqsave(&usb_ss->lock, flags); - reg = readl(&priv_dev->regs->usb_ists); + /* check USB device interrupt */ + reg = cdns_readl(&usb_ss->regs->usb_ists); if (reg) { - writel(reg, &priv_dev->regs->usb_ists); - writel(USB_IEN_INIT, &priv_dev->regs->usb_ien); - cdns3_check_usb_interrupt_proceed(priv_dev, reg); + dev_dbg(&usb_ss->dev, "usb_ists: %08X\n", reg); + cdns_check_usb_interrupt_proceed(usb_ss, reg); ret = IRQ_HANDLED; } - reg = readl(&priv_dev->regs->ep_ists); + /* check endpoint interrupt */ + reg = cdns_readl(&usb_ss->regs->ep_ists); + if (reg != 0) { + dev_dbg(&usb_ss->dev, "ep_ists: %08X\n", reg); + } else { + if (cdns_readl(&usb_ss->regs->usb_sts) & + USB_STS__CFGSTS__MASK) + ret = IRQ_HANDLED; + goto irqend; + } /* handle default endpoint OUT */ - if (reg & EP_ISTS_EP_OUT0) { - cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_OUT); + if (reg & EP_ISTS__EOUT0__MASK) { + cdns_check_ep0_interrupt_proceed(usb_ss, 0); ret = IRQ_HANDLED; } /* handle default endpoint IN */ - if (reg & EP_ISTS_EP_IN0) { - cdns3_check_ep0_interrupt_proceed(priv_dev, USB_DIR_IN); + if (reg & EP_ISTS__EIN0__MASK) { + cdns_check_ep0_interrupt_proceed(usb_ss, 1); ret = IRQ_HANDLED; } /* check if interrupt from non default endpoint, if no exit */ - reg &= ~(EP_ISTS_EP_OUT0 | EP_ISTS_EP_IN0); + reg &= ~(EP_ISTS__EOUT0__MASK | EP_ISTS__EIN0__MASK); if (!reg) goto irqend; - for_each_set_bit(bit, (unsigned long *)®, - sizeof(u32) * BITS_PER_BYTE) { - cdns3_check_ep_interrupt_proceed(priv_dev->eps[bit]); + do { + unsigned int bit_pos = ffs(reg); + u32 bit_mask = 1 << (bit_pos - 1); + u8 ep_index = CAST_EP_REG_POS_TO_INDEX(bit_pos); + + dev_dbg(&usb_ss->dev, "Interrupt on index: %d bitmask %08X\n", + ep_index, bit_mask); + cdns_check_ep_interrupt_proceed(usb_ss->eps[ep_index]); + reg &= ~bit_mask; ret = IRQ_HANDLED; - } + } while (reg); irqend: - writel(~0, &priv_dev->regs->ep_ien); - spin_unlock_irqrestore(&priv_dev->lock, flags); + spin_unlock_irqrestore(&usb_ss->lock, flags); return ret; } /** - * cdns3_ep_onchip_buffer_reserve - Try to reserve onchip buf for EP - * - * The real reservation will occur during write to EP_CFG register, - * this function is used to check if the 'size' reservation is allowed. - * - * @priv_dev: extended gadget object - * @size: the size (KB) for EP would like to allocate - * @is_in: endpoint direction - * - * Return 0 if the required size can met or negative value on failure + * usb_ss_gadget_ep0_enable + * Function shouldn't be called by gadget driver, + * endpoint 0 is allways active */ -static int cdns3_ep_onchip_buffer_reserve(struct cdns3_device *priv_dev, - int size, int is_in) +static int usb_ss_gadget_ep0_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc) { - int remained; - - /* 2KB are reserved for EP0*/ - remained = priv_dev->onchip_buffers - priv_dev->onchip_used_size - 2; - - if (is_in) { - if (remained < size) - return -EPERM; - - priv_dev->onchip_used_size += size; - } else { - int required; - - /** - * ALL OUT EPs are shared the same chunk onchip memory, so - * driver checks if it already has assigned enough buffers - */ - if (priv_dev->out_mem_is_allocated >= size) - return 0; - - required = size - priv_dev->out_mem_is_allocated; - - if (required > remained) - return -EPERM; - - priv_dev->out_mem_is_allocated += required; - priv_dev->onchip_used_size += required; - } - - return 0; + return -EINVAL; } -void cdns3_configure_dmult(struct cdns3_device *priv_dev, - struct cdns3_endpoint *priv_ep) +/** + * usb_ss_gadget_ep0_disable + * Function shouldn't be called by gadget driver, + * endpoint 0 is allways active + */ +static int usb_ss_gadget_ep0_disable(struct usb_ep *ep) { - struct cdns3_usb_regs __iomem *regs = priv_dev->regs; - - /* For dev_ver > DEV_VER_V2 DMULT is configured per endpoint */ - if (priv_dev->dev_ver <= DEV_VER_V2) - writel(USB_CONF_DMULT, ®s->usb_conf); - - if (priv_dev->dev_ver == DEV_VER_V2) - writel(USB_CONF2_EN_TDL_TRB, ®s->usb_conf2); - - if (priv_dev->dev_ver >= DEV_VER_V3 && priv_ep) { - u32 mask; - - if (priv_ep->dir) - mask = BIT(priv_ep->num + 16); - else - mask = BIT(priv_ep->num); - - if (priv_ep->type != USB_ENDPOINT_XFER_ISOC) { - cdns3_set_register_bit(®s->tdl_from_trb, mask); - cdns3_set_register_bit(®s->tdl_beh, mask); - cdns3_set_register_bit(®s->tdl_beh2, mask); - cdns3_set_register_bit(®s->dma_adv_td, mask); - } - - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) - cdns3_set_register_bit(®s->tdl_from_trb, mask); + return -EINVAL; +} - cdns3_set_register_bit(®s->dtrans, mask); - } +/** + * usb_ss_gadget_ep0_set_halt + * @ep: pointer to endpoint zero object + * @value: 1 for set stall, 0 for clear stall + * + * Returns 0 + */ +static int usb_ss_gadget_ep0_set_halt(struct usb_ep *ep, int value) +{ + /* TODO */ + return 0; } /** - * cdns3_ep_config Configure hardware endpoint - * @priv_ep: extended endpoint object + * usb_ss_gadget_ep0_queue Transfer data on endpoint zero + * @ep: pointer to endpoint zero object + * @request: pointer to request object + * @gfp_flags: gfp flags + * + * Returns 0 on success, error code elsewhere */ -void cdns3_ep_config(struct cdns3_endpoint *priv_ep) +static int usb_ss_gadget_ep0_queue(struct usb_ep *ep, + struct usb_request *request, + gfp_t gfp_flags) { - bool is_iso_ep = (priv_ep->type == USB_ENDPOINT_XFER_ISOC); - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - u32 bEndpointAddress = priv_ep->num | priv_ep->dir; - u32 max_packet_size = 0; - u8 maxburst = 0; - u32 ep_cfg = 0; - u8 buffering; - u8 mult = 0; int ret; - - buffering = CDNS3_EP_BUF_SIZE - 1; - - cdns3_configure_dmult(priv_dev, priv_ep); - - switch (priv_ep->type) { - case USB_ENDPOINT_XFER_INT: - ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_INT); - - if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) || - priv_dev->dev_ver > DEV_VER_V2) - ep_cfg |= EP_CFG_TDL_CHK; - break; - case USB_ENDPOINT_XFER_BULK: - ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_BULK); - - if ((priv_dev->dev_ver == DEV_VER_V2 && !priv_ep->dir) || - priv_dev->dev_ver > DEV_VER_V2) - ep_cfg |= EP_CFG_TDL_CHK; - break; - default: - ep_cfg = EP_CFG_EPTYPE(USB_ENDPOINT_XFER_ISOC); - mult = CDNS3_EP_ISO_HS_MULT - 1; - buffering = mult + 1; - } - - switch (priv_dev->gadget.speed) { - case USB_SPEED_FULL: - max_packet_size = is_iso_ep ? 1023 : 64; - break; - case USB_SPEED_HIGH: - max_packet_size = is_iso_ep ? 1024 : 512; - break; - case USB_SPEED_SUPER: - /* It's limitation that driver assumes in driver. */ - mult = 0; - max_packet_size = 1024; - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC) { - maxburst = CDNS3_EP_ISO_SS_BURST - 1; - buffering = (mult + 1) * - (maxburst + 1); - - if (priv_ep->interval > 1) - buffering++; - } else { - maxburst = CDNS3_EP_BUF_SIZE - 1; + unsigned long flags; + int erdy_sent = 0; + /* get extended endpoint */ + struct usb_ss_endpoint *usb_ss_ep = + to_usb_ss_ep(ep); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + + dev_dbg(&usb_ss->dev, "QUEUE(%02X) %d\n", + usb_ss->ep0_data_dir ? USB_DIR_IN : USB_DIR_OUT, + request->length); + + /* send STATUS stage */ + if (request->length == 0 && request->zero == 0) { + spin_lock_irqsave(&usb_ss->lock, flags); + select_ep(usb_ss, 0x00); + if (!usb_ss->hw_configured_flag) { + cdns_writel(&usb_ss->regs->usb_conf, + USB_CONF__CFGSET__MASK); + /* SET CONFIGURATION */ + cdns_prepare_setup_packet(usb_ss); + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK + | EP_CMD__REQ_CMPL__MASK); + /* wait until configuration set */ + while (!(cdns_readl(&usb_ss->regs->usb_sts) + & USB_STS__CFGSTS__MASK)) + ; + erdy_sent = 1; + usb_ss->hw_configured_flag = 1; + + list_for_each_entry(ep, &usb_ss->gadget.ep_list, + ep_list) { + if (to_usb_ss_ep(ep)->enabled) + cdns_ep_run_transfer(to_usb_ss_ep(ep)); + } } - break; - default: - /* all other speed are not supported */ - return; + if (!erdy_sent) + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__ERDY__MASK + | EP_CMD__REQ_CMPL__MASK); + if (request->complete) + request->complete(usb_ss->gadget.ep0, request); + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; } - if (max_packet_size == 1024) - priv_ep->trb_burst_size = 128; - else if (max_packet_size >= 512) - priv_ep->trb_burst_size = 64; - else - priv_ep->trb_burst_size = 16; - - ret = cdns3_ep_onchip_buffer_reserve(priv_dev, buffering + 1, - !!priv_ep->dir); + spin_lock_irqsave(&usb_ss->lock, flags); + ret = usb_gadget_map_request(&usb_ss->gadget, request, + usb_ss->ep0_data_dir); if (ret) { - dev_err(priv_dev->dev, "onchip mem is full, ep is invalid\n"); - return; + dev_err(&usb_ss->dev, "failed to map request\n"); + return -EINVAL; } - ep_cfg |= EP_CFG_MAXPKTSIZE(max_packet_size) | - EP_CFG_MULT(mult) | - EP_CFG_BUFFERING(buffering) | - EP_CFG_MAXBURST(maxburst); - - cdns3_select_ep(priv_dev, bEndpointAddress); - writel(ep_cfg, &priv_dev->regs->ep_cfg); - - dev_dbg(priv_dev->dev, "Configure %s: with val %08x\n", - priv_ep->name, ep_cfg); -} - -/* Find correct direction for HW endpoint according to description */ -static int cdns3_ep_dir_is_correct(struct usb_endpoint_descriptor *desc, - struct cdns3_endpoint *priv_ep) -{ - return (priv_ep->endpoint.caps.dir_in && usb_endpoint_dir_in(desc)) || - (priv_ep->endpoint.caps.dir_out && usb_endpoint_dir_out(desc)); -} - -static struct -cdns3_endpoint *cdns3_find_available_ep(struct cdns3_device *priv_dev, - struct usb_endpoint_descriptor *desc) -{ - struct usb_ep *ep; - struct cdns3_endpoint *priv_ep; - - list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) { - unsigned long num; - /* ep name pattern likes epXin or epXout */ - char c[2] = {ep->name[2], '\0'}; + usb_ss->actual_ep0_request = request; + cdns_ep0_run_transfer(usb_ss, request->dma, request->length, 1); + list_add_tail(&request->list, &usb_ss_ep->request_list); + spin_unlock_irqrestore(&usb_ss->lock, flags); - num = simple_strtoul(c, NULL, 10); - - priv_ep = ep_to_cdns3_ep(ep); - if (cdns3_ep_dir_is_correct(desc, priv_ep)) { - if (!(priv_ep->flags & EP_CLAIMED)) { - priv_ep->num = num; - return priv_ep; - } - } - } - - return ERR_PTR(-ENOENT); + return 0; } -/* - * Cadence IP has one limitation that all endpoints must be configured - * (Type & MaxPacketSize) before setting configuration through hardware - * register, it means we can't change endpoints configuration after - * set_configuration. - * - * This function set EP_CLAIMED flag which is added when the gadget driver - * uses usb_ep_autoconfig to configure specific endpoint; - * When the udc driver receives set_configurion request, - * it goes through all claimed endpoints, and configure all endpoints - * accordingly. - * - * At usb_ep_ops.enable/disable, we only enable and disable endpoint through - * ep_cfg register which can be changed after set_configuration, and do - * some software operation accordingly. +/** + * cdns_ep_config Configure hardware endpoint + * @usb_ss_ep: extended endpoint object */ -static struct -usb_ep *cdns3_gadget_match_ep(struct usb_gadget *gadget, - struct usb_endpoint_descriptor *desc, - struct usb_ss_ep_comp_descriptor *comp_desc) +static void cdns_ep_config(struct usb_ss_endpoint *usb_ss_ep) { - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); - struct cdns3_endpoint *priv_ep; - unsigned long flags; - - priv_ep = cdns3_find_available_ep(priv_dev, desc); - if (IS_ERR(priv_ep)) { - dev_err(priv_dev->dev, "no available ep\n"); - return NULL; + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + u32 ep_cfg = 0; + u32 max_packet_size = 0; + u32 bEndpointAddress = usb_ss_ep->num | usb_ss_ep->dir; + u32 interrupt_mask = 0; + bool is_iso_ep = (usb_ss_ep->type == USB_ENDPOINT_XFER_ISOC); + __maybe_unused bool is_int_ep = + (usb_ss_ep->type == USB_ENDPOINT_XFER_INT); + + dev_dbg(&usb_ss->dev, + "%s: %s addr=0x%x, speed %d, is_iso_ep %d\n", __func__, + usb_ss_ep->name, bEndpointAddress, usb_ss->gadget.speed, + is_iso_ep); + + if (is_iso_ep) { + ep_cfg = EP_CFG__EPTYPE__WRITE(USB_ENDPOINT_XFER_ISOC); + interrupt_mask = INTERRUPT_MASK; + } else { + ep_cfg = EP_CFG__EPTYPE__WRITE(USB_ENDPOINT_XFER_BULK); } - dev_dbg(priv_dev->dev, "match endpoint: %s\n", priv_ep->name); + switch (usb_ss->gadget.speed) { + case USB_SPEED_UNKNOWN: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_0; + break; - spin_lock_irqsave(&priv_dev->lock, flags); - priv_ep->endpoint.desc = desc; - priv_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT; - priv_ep->type = usb_endpoint_type(desc); - priv_ep->flags |= EP_CLAIMED; - priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0; + case USB_SPEED_LOW: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_8; + break; - spin_unlock_irqrestore(&priv_dev->lock, flags); - return &priv_ep->endpoint; -} + case USB_SPEED_FULL: + max_packet_size = (is_iso_ep ? + ENDPOINT_MAX_PACKET_SIZE_1023 : + ENDPOINT_MAX_PACKET_SIZE_64); + break; -/** - * cdns3_gadget_ep_alloc_request Allocates request - * @ep: endpoint object associated with request - * @gfp_flags: gfp flags - * - * Returns allocated request address, NULL on allocation error - */ -struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep, - gfp_t gfp_flags) -{ - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); - struct cdns3_request *priv_req; + case USB_SPEED_HIGH: + max_packet_size = (is_iso_ep ? + ENDPOINT_MAX_PACKET_SIZE_1024 : + ENDPOINT_MAX_PACKET_SIZE_512); +#if defined(CONFIG_SPL_USB_SDP_SUPPORT) || defined(CONFIG_USB_FUNCTION_SDP) + if (is_int_ep) + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_1024; +#endif + break; - priv_req = kzalloc(sizeof(*priv_req), gfp_flags); - if (!priv_req) - return NULL; + case USB_SPEED_WIRELESS: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_512; + break; - priv_req->priv_ep = priv_ep; + case USB_SPEED_SUPER: + case USB_SPEED_SUPER_PLUS: + max_packet_size = ENDPOINT_MAX_PACKET_SIZE_1024; + break; + } - trace_cdns3_alloc_request(priv_req); - return &priv_req->request; -} + ep_cfg |= EP_CFG__MAXPKTSIZE__WRITE(max_packet_size); -/** - * cdns3_gadget_ep_free_request Free memory occupied by request - * @ep: endpoint object associated with request - * @request: request to free memory - */ -void cdns3_gadget_ep_free_request(struct usb_ep *ep, - struct usb_request *request) -{ - struct cdns3_request *priv_req = to_cdns3_request(request); + if (is_iso_ep) { + ep_cfg |= EP_CFG__BUFFERING__WRITE(1); + ep_cfg |= EP_CFG__MAXBURST__WRITE(0); + } else { + ep_cfg |= EP_CFG__BUFFERING__WRITE(3); + ep_cfg |= EP_CFG__MAXBURST__WRITE(15); + } - if (priv_req->aligned_buf) - priv_req->aligned_buf->in_use = 0; + select_ep(usb_ss, bEndpointAddress); + cdns_writel(&usb_ss->regs->ep_cfg, ep_cfg); + cdns_writel(&usb_ss->regs->ep_sts_en, + EP_STS_EN__TRBERREN__MASK | interrupt_mask); - trace_cdns3_free_request(priv_req); - kfree(priv_req); + /* enable interrupt for selected endpoint */ + ep_cfg = cdns_readl(&usb_ss->regs->ep_ien); + ep_cfg |= CAST_EP_ADDR_TO_BIT_POS(bEndpointAddress); + cdns_writel(&usb_ss->regs->ep_ien, ep_cfg); } /** - * cdns3_gadget_ep_enable Enable endpoint + * usb_ss_gadget_ep_enable Enable endpoint * @ep: endpoint object * @desc: endpoint descriptor * * Returns 0 on success, error code elsewhere */ -static int cdns3_gadget_ep_enable(struct usb_ep *ep, - const struct usb_endpoint_descriptor *desc) +static int usb_ss_gadget_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc) { - struct cdns3_endpoint *priv_ep; - struct cdns3_device *priv_dev; - u32 reg = EP_STS_EN_TRBERREN; - u32 bEndpointAddress; + struct usb_ss_endpoint *usb_ss_ep; + struct usb_ss_dev *usb_ss; unsigned long flags; - int enable = 1; + unsigned long *dma_addr; int ret; - int val; + u32 ep_cfg; - priv_ep = ep_to_cdns3_ep(ep); - priv_dev = priv_ep->cdns3_dev; + usb_ss_ep = to_usb_ss_ep(ep); + usb_ss = usb_ss_ep->usb_ss; if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) { - dev_dbg(priv_dev->dev, "usbss: invalid parameters\n"); + dev_err(&usb_ss->dev, "usb-ss: invalid parameters\n"); return -EINVAL; } if (!desc->wMaxPacketSize) { - dev_err(priv_dev->dev, "usbss: missing wMaxPacketSize\n"); + dev_err(&usb_ss->dev, "usb-ss: missing wMaxPacketSize\n"); return -EINVAL; } - if (WARN_ON(priv_ep->flags & EP_ENABLED)) - return 0; - - spin_lock_irqsave(&priv_dev->lock, flags); - - priv_ep->endpoint.desc = desc; - priv_ep->type = usb_endpoint_type(desc); - priv_ep->interval = desc->bInterval ? BIT(desc->bInterval - 1) : 0; - - if (priv_ep->interval > ISO_MAX_INTERVAL && - priv_ep->type == USB_ENDPOINT_XFER_ISOC) { - dev_err(priv_dev->dev, "Driver is limited to %d period\n", - ISO_MAX_INTERVAL); - - ret = -EINVAL; - goto exit; - } - - ret = cdns3_allocate_trb_pool(priv_ep); - + ret = usb_ss_allocate_trb_pool(usb_ss_ep); if (ret) - goto exit; - - bEndpointAddress = priv_ep->num | priv_ep->dir; - cdns3_select_ep(priv_dev, bEndpointAddress); - - trace_cdns3_gadget_ep_enable(priv_ep); - - writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd); + return ret; - ret = readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, - !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)), - 1000); + if (!usb_ss_ep->cpu_addr) { + dma_addr = (unsigned long *)&usb_ss_ep->dma_addr; + usb_ss_ep->cpu_addr = dma_alloc_coherent(4096, dma_addr); - if (unlikely(ret)) { - cdns3_free_trb_pool(priv_ep); - ret = -EINVAL; - goto exit; + if (!usb_ss_ep->cpu_addr) + return -ENOMEM; } - /* enable interrupt for selected endpoint */ - cdns3_set_register_bit(&priv_dev->regs->ep_ien, - BIT(cdns3_ep_addr_to_index(bEndpointAddress))); - - if (priv_dev->dev_ver < DEV_VER_V2) - cdns3_wa2_enable_detection(priv_dev, priv_ep, reg); - - writel(reg, &priv_dev->regs->ep_sts_en); - - /* - * For some versions of controller at some point during ISO OUT traffic - * DMA reads Transfer Ring for the EP which has never got doorbell. - * This issue was detected only on simulation, but to avoid this issue - * driver add protection against it. To fix it driver enable ISO OUT - * endpoint before setting DRBL. This special treatment of ISO OUT - * endpoints are recommended by controller specification. - */ - if (priv_ep->type == USB_ENDPOINT_XFER_ISOC && !priv_ep->dir) - enable = 0; - - if (enable) - cdns3_set_register_bit(&priv_dev->regs->ep_cfg, EP_CFG_ENABLE); + dev_dbg(&usb_ss->dev, "Enabling endpoint: %s, addr=0x%x\n", + ep->name, desc->bEndpointAddress); + spin_lock_irqsave(&usb_ss->lock, flags); + select_ep(usb_ss, desc->bEndpointAddress); + ep_cfg = cdns_readl(&usb_ss->regs->ep_cfg); + ep_cfg |= EP_CFG__ENABLE__MASK; + cdns_writel(&usb_ss->regs->ep_cfg, ep_cfg); + usb_ss_ep->enabled = 1; ep->desc = desc; - priv_ep->flags &= ~(EP_PENDING_REQUEST | EP_STALLED | EP_STALL_PENDING | - EP_QUIRK_ISO_OUT_EN | EP_QUIRK_EXTRA_BUF_EN); - priv_ep->flags |= EP_ENABLED | EP_UPDATE_EP_TRBADDR; - priv_ep->wa1_set = 0; - priv_ep->enqueue = 0; - priv_ep->dequeue = 0; - reg = readl(&priv_dev->regs->ep_sts); - priv_ep->pcs = !!EP_STS_CCS(reg); - priv_ep->ccs = !!EP_STS_CCS(reg); - /* one TRB is reserved for link TRB used in DMULT mode*/ - priv_ep->free_trbs = priv_ep->num_trbs - 1; -exit: - spin_unlock_irqrestore(&priv_dev->lock, flags); + usb_ss_ep->hw_pending_flag = 0; + spin_unlock_irqrestore(&usb_ss->lock, flags); - return ret; + return 0; } -/** - * cdns3_gadget_ep_disable Disable endpoint - * @ep: endpoint object - * - * Returns 0 on success, error code elsewhere - */ -static int cdns3_gadget_ep_disable(struct usb_ep *ep) +static int cdns3_disable_reset_ep(struct usb_ss_dev *usb_ss, + struct usb_ss_endpoint *usb_ss_ep) { - struct cdns3_endpoint *priv_ep; - struct cdns3_request *priv_req; - struct cdns3_device *priv_dev; - struct usb_request *request; + u32 val; + int ret; unsigned long flags; - int ret = 0; - u32 ep_cfg; - int val; - if (!ep) { - pr_err("usbss: invalid parameters\n"); - return -EINVAL; - } + spin_lock_irqsave(&usb_ss->lock, flags); - priv_ep = ep_to_cdns3_ep(ep); - priv_dev = priv_ep->cdns3_dev; - - if (WARN_ON(!(priv_ep->flags & EP_ENABLED))) + if (usb_ss_ep->hw_reset_flag) { + spin_unlock_irqrestore(&usb_ss->lock, flags); return 0; + } - spin_lock_irqsave(&priv_dev->lock, flags); - - trace_cdns3_gadget_ep_disable(priv_ep); - - cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress); - - ep_cfg = readl(&priv_dev->regs->ep_cfg); - ep_cfg &= ~EP_CFG_ENABLE; - writel(ep_cfg, &priv_dev->regs->ep_cfg); + select_ep(usb_ss_ep->usb_ss, + usb_ss_ep->endpoint.desc->bEndpointAddress); /** * Driver needs some time before resetting endpoint. * It need waits for clearing DBUSY bit or for timeout expired. * 10us is enough time for controller to stop transfer. */ - readl_poll_timeout_atomic(&priv_dev->regs->ep_sts, val, - !(val & EP_STS_DBUSY), 10); - writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd); - - readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, - !(val & (EP_CMD_CSTALL | EP_CMD_EPRST)), - 1000); + ret = readl_poll_timeout(&usb_ss->regs->ep_sts, val, + !(val & EP_STS__DBUSY__MASK), 10); if (unlikely(ret)) - dev_err(priv_dev->dev, "Timeout: %s resetting failed.\n", - priv_ep->name); - - while (!list_empty(&priv_ep->pending_req_list)) { - request = cdns3_next_request(&priv_ep->pending_req_list); + dev_err(&usb_ss->dev, "Timeout: %s wait dbusy\n", + usb_ss->gadget.name); - cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), - -ESHUTDOWN); - } - - while (!list_empty(&priv_ep->wa2_descmiss_req_list)) { - priv_req = cdns3_next_priv_request(&priv_ep->wa2_descmiss_req_list); + ret = readl_poll_timeout(&usb_ss->regs->ep_sts, val, + (val & EP_STS__BUFFEMPTY__MASK), 1000); + if (unlikely(ret)) + dev_err(&usb_ss->dev, "Timeout: %s: %s wait buffer empty\n", + usb_ss_ep->name, usb_ss->gadget.name); - kfree(priv_req->request.buf); - cdns3_gadget_ep_free_request(&priv_ep->endpoint, - &priv_req->request); - list_del_init(&priv_req->list); - --priv_ep->wa2_counter; - } + writel(EP_CMD__EPRST__MASK, &usb_ss->regs->ep_cmd); - while (!list_empty(&priv_ep->deferred_req_list)) { - request = cdns3_next_request(&priv_ep->deferred_req_list); + ret = readl_poll_timeout(&usb_ss->regs->ep_cmd, val, + !(val & (EP_CMD__CSTALL__MASK | EP_CMD__EPRST__MASK)), + 1000); - cdns3_gadget_giveback(priv_ep, to_cdns3_request(request), - -ESHUTDOWN); - } + if (unlikely(ret)) + dev_err(&usb_ss->dev, "Timeout: %s resetting failed.\n", + usb_ss->gadget.name); - priv_ep->descmis_req = NULL; - ep->desc = NULL; - priv_ep->flags &= ~EP_ENABLED; + val = readl(&usb_ss->regs->ep_cfg); + val &= ~EP_CFG__ENABLE__MASK; + writel(val, &usb_ss->regs->ep_cfg); - spin_unlock_irqrestore(&priv_dev->lock, flags); + usb_ss_ep->hw_reset_flag = 1; + spin_unlock_irqrestore(&usb_ss->lock, flags); return ret; } -/** - * cdns3_gadget_ep_queue Transfer data on endpoint - * @ep: endpoint object - * @request: request object - * @gfp_flags: gfp flags - * - * Returns 0 on success, error code elsewhere - */ -static int __cdns3_gadget_ep_queue(struct usb_ep *ep, - struct usb_request *request, - gfp_t gfp_flags) +static int usb_ss_gadget_ep_conf(struct usb_gadget *gadget, + struct usb_ep *ep, + struct usb_endpoint_descriptor *desc) { - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - struct cdns3_request *priv_req; - int ret = 0; - - request->actual = 0; - request->status = -EINPROGRESS; - priv_req = to_cdns3_request(request); - trace_cdns3_ep_queue(priv_req); + struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget); + struct usb_ss_endpoint *usb_ss_ep; + unsigned long flags; - if (priv_dev->dev_ver < DEV_VER_V2) { - ret = cdns3_wa2_gadget_ep_queue(priv_dev, priv_ep, - priv_req); + usb_ss_ep = to_usb_ss_ep(ep); - if (ret == EINPROGRESS) - return 0; - } + dev_dbg(&usb_ss->dev, "match endpoint: %s\n", usb_ss_ep->name); - ret = cdns3_prepare_aligned_request_buf(priv_req); - if (ret < 0) - return ret; + u8 num = simple_strtoul(&ep->name[2], NULL, 10); - ret = usb_gadget_map_request(&priv_dev->gadget, request, - usb_endpoint_dir_in(ep->desc)); - if (ret) - return ret; + spin_lock_irqsave(&usb_ss->lock, flags); + usb_ss_ep->num = num; + usb_ss_ep->used = true; + usb_ss_ep->endpoint.desc = desc; + usb_ss_ep->dir = usb_endpoint_dir_in(desc) ? USB_DIR_IN : USB_DIR_OUT; + usb_ss_ep->type = usb_endpoint_type(desc); + usb_ss_ep->address = desc->bEndpointAddress; + spin_unlock_irqrestore(&usb_ss->lock, flags); - list_add_tail(&request->list, &priv_ep->deferred_req_list); + return 1; +} - /* - * If hardware endpoint configuration has not been set yet then - * just queue request in deferred list. Transfer will be started in - * cdns3_set_hw_configuration. - */ - if (priv_dev->hw_configured_flag && !(priv_ep->flags & EP_STALLED) && - !(priv_ep->flags & EP_STALL_PENDING)) - cdns3_start_all_request(priv_dev, priv_ep); +static void usb_ss_free_trb_pool(struct usb_ss_endpoint *usb_ss_ep) +{ + if (usb_ss_ep->trb_pool) { + dma_free_coherent(usb_ss_ep->trb_pool); + usb_ss_ep->trb_pool = NULL; + } - return 0; + if (usb_ss_ep->cpu_addr) { + dma_free_coherent(usb_ss_ep->cpu_addr); + usb_ss_ep->cpu_addr = NULL; + } } -static int cdns3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request, - gfp_t gfp_flags) +/** + * usb_ss_gadget_ep_disable Disable endpoint + * @ep: endpoint object + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_gadget_ep_disable(struct usb_ep *ep) { - struct usb_request *zlp_request; - struct cdns3_endpoint *priv_ep; - struct cdns3_device *priv_dev; + struct usb_ss_endpoint *usb_ss_ep; + struct usb_ss_dev *usb_ss; unsigned long flags; - int ret; + int ret = 0; + struct usb_request *request; - if (!request || !ep) + if (!ep) { + pr_debug("usb-ss: invalid parameters\n"); return -EINVAL; + } - priv_ep = ep_to_cdns3_ep(ep); - priv_dev = priv_ep->cdns3_dev; + usb_ss_ep = to_usb_ss_ep(ep); + usb_ss = usb_ss_ep->usb_ss; - spin_lock_irqsave(&priv_dev->lock, flags); + spin_lock_irqsave(&usb_ss->lock, flags); + if (!usb_ss->start_gadget) { + dev_dbg(&usb_ss->dev, + "Disabling endpoint at disconnection: %s\n", ep->name); + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } + + dev_dbg(&usb_ss->dev, + "Disabling endpoint: %s\n", ep->name); + + ret = cdns3_disable_reset_ep(usb_ss, usb_ss_ep); + + while (!list_empty(&usb_ss_ep->request_list)) { + request = next_request(&usb_ss_ep->request_list); + usb_gadget_unmap_request(&usb_ss->gadget, request, + ep->desc->bEndpointAddress & + USB_DIR_IN); + request->status = -ESHUTDOWN; + list_del(&request->list); + spin_unlock(&usb_ss->lock); + usb_gadget_giveback_request(ep, request); + spin_lock(&usb_ss->lock); + } - ret = __cdns3_gadget_ep_queue(ep, request, gfp_flags); + ep->desc = NULL; + usb_ss_ep->enabled = 0; - if (ret == 0 && request->zero && request->length && - (request->length % ep->maxpacket == 0)) { - struct cdns3_request *priv_req; + spin_unlock_irqrestore(&usb_ss->lock, flags); - zlp_request = cdns3_gadget_ep_alloc_request(ep, GFP_ATOMIC); - zlp_request->buf = priv_dev->zlp_buf; - zlp_request->length = 0; + return ret; +} - priv_req = to_cdns3_request(zlp_request); - priv_req->flags |= REQUEST_ZLP; +/** + * usb_ss_gadget_ep_alloc_request Allocates request + * @ep: endpoint object associated with request + * @gfp_flags: gfp flags + * + * Returns allocated request address, NULL on allocation error + */ +static struct usb_request *usb_ss_gadget_ep_alloc_request(struct usb_ep *ep, + gfp_t gfp_flags) +{ + struct usb_request *request; - dev_dbg(priv_dev->dev, "Queuing ZLP for endpoint: %s\n", - priv_ep->name); - ret = __cdns3_gadget_ep_queue(ep, zlp_request, gfp_flags); - } + request = kzalloc(sizeof(*request), gfp_flags); + if (!request) + return NULL; - spin_unlock_irqrestore(&priv_dev->lock, flags); - return ret; + return request; } /** - * cdns3_gadget_ep_dequeue Remove request from transfer queue + * usb_ss_gadget_ep_free_request Free memory occupied by request * @ep: endpoint object associated with request + * @request: request to free memory + */ +static void usb_ss_gadget_ep_free_request(struct usb_ep *ep, + struct usb_request *request) +{ + kfree(request); +} + +/** + * usb_ss_gadget_ep_queue Transfer data on endpoint + * @ep: endpoint object * @request: request object + * @gfp_flags: gfp flags * * Returns 0 on success, error code elsewhere */ -int cdns3_gadget_ep_dequeue(struct usb_ep *ep, - struct usb_request *request) +static int usb_ss_gadget_ep_queue(struct usb_ep *ep, + struct usb_request *request, gfp_t gfp_flags) { - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - struct usb_request *req, *req_temp; - struct cdns3_request *priv_req; - struct cdns3_trb *link_trb; + struct usb_ss_endpoint *usb_ss_ep = + to_usb_ss_ep(ep); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; unsigned long flags; int ret = 0; + int empty_list = 0; - if (!ep || !request || !ep->desc) - return -EINVAL; - - spin_lock_irqsave(&priv_dev->lock, flags); + spin_lock_irqsave(&usb_ss->lock, flags); - priv_req = to_cdns3_request(request); + request->actual = 0; + request->status = -EINPROGRESS; - trace_cdns3_ep_dequeue(priv_req); + dev_dbg(&usb_ss->dev, + "Queuing endpoint: %s\n", usb_ss_ep->name); - cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress); + dev_dbg(&usb_ss->dev, "QUEUE(%02X) %d\n", + ep->desc->bEndpointAddress, request->length); - list_for_each_entry_safe(req, req_temp, &priv_ep->pending_req_list, - list) { - if (request == req) - goto found; - } + ret = usb_gadget_map_request(&usb_ss->gadget, request, + ep->desc->bEndpointAddress & USB_DIR_IN); - list_for_each_entry_safe(req, req_temp, &priv_ep->deferred_req_list, - list) { - if (request == req) - goto found; + if (ret) { + spin_unlock_irqrestore(&usb_ss->lock, flags); + return ret; } - goto not_found; + empty_list = list_empty(&usb_ss_ep->request_list); + list_add_tail(&request->list, &usb_ss_ep->request_list); -found: - - if (priv_ep->wa1_trb == priv_req->trb) - cdns3_wa1_restore_cycle_bit(priv_ep); - - link_trb = priv_req->trb; - cdns3_move_deq_to_next_trb(priv_req); - cdns3_gadget_giveback(priv_ep, priv_req, -ECONNRESET); - - /* Update ring */ - request = cdns3_next_request(&priv_ep->deferred_req_list); - if (request) { - priv_req = to_cdns3_request(request); + if (!usb_ss->hw_configured_flag) { + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } - link_trb->buffer = TRB_BUFFER(priv_ep->trb_pool_dma + - (priv_req->start_trb * TRB_SIZE)); - link_trb->control = (link_trb->control & TRB_CYCLE) | - TRB_TYPE(TRB_LINK) | TRB_CHAIN | TRB_TOGGLE; - } else { - priv_ep->flags |= EP_UPDATE_EP_TRBADDR; + if (empty_list) { + if (!usb_ss_ep->stalled_flag) + cdns_ep_run_transfer(usb_ss_ep); } + spin_unlock_irqrestore(&usb_ss->lock, flags); -not_found: - spin_unlock_irqrestore(&priv_dev->lock, flags); return ret; } /** - * __cdns3_gadget_ep_set_halt Sets stall on selected endpoint - * Should be called after acquiring spin_lock and selecting ep - * @ep: endpoint object to set stall on. + * usb_ss_gadget_ep_dequeue Remove request from transfer queue + * @ep: endpoint object associated with request + * @request: request object + * + * Returns 0 on success, error code elsewhere */ -void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep) +static int usb_ss_gadget_ep_dequeue(struct usb_ep *ep, + struct usb_request *request) { - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - - trace_cdns3_halt(priv_ep, 1, 0); - - if (!(priv_ep->flags & EP_STALLED)) { - u32 ep_sts_reg = readl(&priv_dev->regs->ep_sts); + struct usb_ss_endpoint *usb_ss_ep = + to_usb_ss_ep(ep); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; + struct usb_request *req, *req_temp; + unsigned long flags; - if (!(ep_sts_reg & EP_STS_DBUSY)) - cdns3_ep_stall_flush(priv_ep); - else - priv_ep->flags |= EP_STALL_PENDING; + spin_lock_irqsave(&usb_ss->lock, flags); + if (!usb_ss->start_gadget) { + dev_dbg(&usb_ss->dev, + "DEQUEUE at disconnection: %s\n", ep->name); + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } + dev_dbg(&usb_ss->dev, "DEQUEUE(%02X) %d\n", + usb_ss_ep->address, request->length); + + list_for_each_entry_safe(req, req_temp, + &usb_ss_ep->request_list, list) { + if (request == req) { + request->status = -ECONNRESET; + usb_gadget_unmap_request(&usb_ss->gadget, request, + usb_ss_ep->address & + USB_DIR_IN); + list_del_init(&request->list); + if (request->complete) { + spin_unlock(&usb_ss->lock); + usb_gadget_giveback_request + (&usb_ss_ep->endpoint, request); + spin_lock(&usb_ss->lock); + } + break; + } } -} - -/** - * __cdns3_gadget_ep_clear_halt Clears stall on selected endpoint - * Should be called after acquiring spin_lock and selecting ep - * @ep: endpoint object to clear stall on - */ -int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep) -{ - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; - struct usb_request *request; - int ret = 0; - int val; - - trace_cdns3_halt(priv_ep, 0, 0); - - writel(EP_CMD_CSTALL | EP_CMD_EPRST, &priv_dev->regs->ep_cmd); - - /* wait for EPRST cleared */ - readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, - !(val & EP_CMD_EPRST), 100); - if (ret) - return -EINVAL; - - priv_ep->flags &= ~(EP_STALLED | EP_STALL_PENDING); - - request = cdns3_next_request(&priv_ep->pending_req_list); - - if (request) - cdns3_rearm_transfer(priv_ep, 1); - cdns3_start_all_request(priv_dev, priv_ep); - return ret; + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; } /** - * cdns3_gadget_ep_set_halt Sets/clears stall on selected endpoint + * usb_ss_gadget_ep_set_halt Sets/clears stall on selected endpoint * @ep: endpoint object to set/clear stall on * @value: 1 for set stall, 0 for clear stall * * Returns 0 on success, error code elsewhere */ -int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value) +static int usb_ss_gadget_ep_set_halt(struct usb_ep *ep, int value) { - struct cdns3_endpoint *priv_ep = ep_to_cdns3_ep(ep); - struct cdns3_device *priv_dev = priv_ep->cdns3_dev; + struct usb_ss_endpoint *usb_ss_ep = + to_usb_ss_ep(ep); + struct usb_ss_dev *usb_ss = usb_ss_ep->usb_ss; unsigned long flags; - int ret = 0; - if (!(priv_ep->flags & EP_ENABLED)) + /* return error when endpoint disabled */ + if (!usb_ss_ep->enabled) return -EPERM; - spin_lock_irqsave(&priv_dev->lock, flags); + /* if actual transfer is pending defer setting stall on this endpoint */ + if (usb_ss_ep->hw_pending_flag && value) { + usb_ss_ep->stalled_flag = 1; + return 0; + } + + dev_dbg(&usb_ss->dev, "HALT(%02X) %d\n", usb_ss_ep->address, value); - cdns3_select_ep(priv_dev, ep->desc->bEndpointAddress); + spin_lock_irqsave(&usb_ss->lock, flags); - if (!value) { - priv_ep->flags &= ~EP_WEDGE; - ret = __cdns3_gadget_ep_clear_halt(priv_ep); + select_ep(usb_ss, ep->desc->bEndpointAddress); + if (value) { + cdns_ep_stall_flush(usb_ss_ep); } else { - __cdns3_gadget_ep_set_halt(priv_ep); + /* + * TODO: + * epp->wedgeFlag = 0; + */ + usb_ss_ep->wedge_flag = 0; + cdns_writel(&usb_ss->regs->ep_cmd, + EP_CMD__CSTALL__MASK | EP_CMD__EPRST__MASK); + /* wait for EPRST cleared */ + while (cdns_readl(&usb_ss->regs->ep_cmd) & + EP_CMD__EPRST__MASK) + ; + usb_ss_ep->stalled_flag = 0; } + usb_ss_ep->hw_pending_flag = 0; - spin_unlock_irqrestore(&priv_dev->lock, flags); + spin_unlock_irqrestore(&usb_ss->lock, flags); - return ret; + return 0; } -extern const struct usb_ep_ops cdns3_gadget_ep0_ops; - -static const struct usb_ep_ops cdns3_gadget_ep_ops = { - .enable = cdns3_gadget_ep_enable, - .disable = cdns3_gadget_ep_disable, - .alloc_request = cdns3_gadget_ep_alloc_request, - .free_request = cdns3_gadget_ep_free_request, - .queue = cdns3_gadget_ep_queue, - .dequeue = cdns3_gadget_ep_dequeue, - .set_halt = cdns3_gadget_ep_set_halt, - .set_wedge = cdns3_gadget_ep_set_wedge, -}; - /** - * cdns3_gadget_get_frame Returns number of actual ITP frame - * @gadget: gadget object + * usb_ss_gadget_ep_set_wedge Set wedge on selected endpoint + * @ep: endpoint object * - * Returns number of actual ITP frame + * Returns 0 */ -static int cdns3_gadget_get_frame(struct usb_gadget *gadget) +static int usb_ss_gadget_ep_set_wedge(struct usb_ep *ep) { - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); + struct usb_ss_endpoint *usb_ss_ep = to_usb_ss_ep(ep); + struct usb_ss_dev __maybe_unused *usb_ss = usb_ss_ep->usb_ss; - return readl(&priv_dev->regs->usb_itpn); + dev_dbg(&usb_ss->dev, "WEDGE(%02X)\n", usb_ss_ep->address); + usb_ss_gadget_ep_set_halt(ep, 1); + usb_ss_ep->wedge_flag = 1; + return 0; } -int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev) -{ - enum usb_device_speed speed; - - speed = cdns3_get_speed(priv_dev); - - if (speed >= USB_SPEED_SUPER) - return 0; - - /* Start driving resume signaling to indicate remote wakeup. */ - writel(USB_CONF_LGO_L0, &priv_dev->regs->usb_conf); +static const struct usb_ep_ops usb_ss_gadget_ep0_ops = { + .enable = usb_ss_gadget_ep0_enable, + .disable = usb_ss_gadget_ep0_disable, + .alloc_request = usb_ss_gadget_ep_alloc_request, + .free_request = usb_ss_gadget_ep_free_request, + .queue = usb_ss_gadget_ep0_queue, + .dequeue = usb_ss_gadget_ep_dequeue, + .set_halt = usb_ss_gadget_ep0_set_halt, + .set_wedge = usb_ss_gadget_ep_set_wedge, +}; - return 0; -} +static const struct usb_ep_ops usb_ss_gadget_ep_ops = { + .enable = usb_ss_gadget_ep_enable, + .disable = usb_ss_gadget_ep_disable, + .alloc_request = usb_ss_gadget_ep_alloc_request, + .free_request = usb_ss_gadget_ep_free_request, + .queue = usb_ss_gadget_ep_queue, + .dequeue = usb_ss_gadget_ep_dequeue, + .set_halt = usb_ss_gadget_ep_set_halt, + .set_wedge = usb_ss_gadget_ep_set_wedge, +}; -static int cdns3_gadget_wakeup(struct usb_gadget *gadget) +/** + * usb_ss_gadget_get_frame Returns number of actual ITP frame + * @gadget: gadget object + * + * Returns number of actual ITP frame + */ +static int usb_ss_gadget_get_frame(struct usb_gadget *gadget) { - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); - unsigned long flags; - int ret = 0; + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget); - spin_lock_irqsave(&priv_dev->lock, flags); - ret = __cdns3_gadget_wakeup(priv_dev); - spin_unlock_irqrestore(&priv_dev->lock, flags); - return ret; + dev_dbg(&usb_ss->dev, "%s\n", __func__); + return cdns_readl(&usb_ss->regs->usb_iptn); } -static int cdns3_gadget_set_selfpowered(struct usb_gadget *gadget, - int is_selfpowered) +static int usb_ss_gadget_wakeup(struct usb_gadget *gadget) { - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); - unsigned long flags; + struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget); - spin_lock_irqsave(&priv_dev->lock, flags); - priv_dev->is_selfpowered = !!is_selfpowered; - spin_unlock_irqrestore(&priv_dev->lock, flags); + dev_dbg(&usb_ss->dev, "%s\n", __func__); return 0; } -static int cdns3_gadget_pullup(struct usb_gadget *gadget, int is_on) +static int usb_ss_gadget_set_selfpowered(struct usb_gadget *gadget, + int is_selfpowered) { - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); - - if (is_on) - writel(USB_CONF_DEVEN, &priv_dev->regs->usb_conf); - else - writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); + struct usb_ss_dev __maybe_unused *usb_ss = gadget_to_usb_ss(gadget); + dev_dbg(&usb_ss->dev, "%s: %d\n", __func__, is_selfpowered); return 0; } -static void cdns3_gadget_config(struct cdns3_device *priv_dev) +static int usb_ss_gadget_pullup(struct usb_gadget *gadget, int is_on) { - struct cdns3_usb_regs __iomem *regs = priv_dev->regs; - u32 reg; + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget); + struct usb_ep *ep; - cdns3_ep0_config(priv_dev); + if (!usb_ss->start_gadget) + return 0; - /* enable interrupts for endpoint 0 (in and out) */ - writel(EP_IEN_EP_OUT0 | EP_IEN_EP_IN0, ®s->ep_ien); + dev_dbg(&usb_ss->dev, "%s: %d\n", __func__, is_on); - /* - * Driver needs to modify LFPS minimal U1 Exit time for DEV_VER_TI_V1 - * revision of controller. - */ - if (priv_dev->dev_ver == DEV_VER_TI_V1) { - reg = readl(®s->dbg_link1); + if (is_on) { + cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVEN__MASK); + } else { + list_for_each_entry(ep, + &usb_ss->gadget.ep_list, + ep_list) { + if (to_usb_ss_ep(ep)->enabled) + cdns3_disable_reset_ep(usb_ss, to_usb_ss_ep(ep)); + } - reg &= ~DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK; - reg |= DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(0x55) | - DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET; - writel(reg, ®s->dbg_link1); + cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK); } - - /* - * By default some platforms has set protected access to memory. - * This cause problem with cache, so driver restore non-secure - * access to memory. - */ - reg = readl(®s->dma_axi_ctrl); - reg |= DMA_AXI_CTRL_MARPROT(DMA_AXI_CTRL_NON_SECURE) | - DMA_AXI_CTRL_MAWPROT(DMA_AXI_CTRL_NON_SECURE); - writel(reg, ®s->dma_axi_ctrl); - - /* enable generic interrupt*/ - writel(USB_IEN_INIT, ®s->usb_ien); - writel(USB_CONF_CLK2OFFDS | USB_CONF_L1DS, ®s->usb_conf); - - cdns3_configure_dmult(priv_dev, NULL); - - cdns3_gadget_pullup(&priv_dev->gadget, 1); + return 0; } /** - * cdns3_gadget_udc_start Gadget start + * usb_ss_gadget_udc_start Gadget start * @gadget: gadget object * @driver: driver which operates on this gadget * * Returns 0 on success, error code elsewhere */ -static int cdns3_gadget_udc_start(struct usb_gadget *gadget, - struct usb_gadget_driver *driver) +static int usb_ss_gadget_udc_start(struct usb_gadget *gadget, + struct usb_gadget_driver *driver) { - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget); unsigned long flags; - spin_lock_irqsave(&priv_dev->lock, flags); - priv_dev->gadget_driver = driver; - cdns3_gadget_config(priv_dev); - spin_unlock_irqrestore(&priv_dev->lock, flags); + if (usb_ss->gadget_driver) { + dev_err(&usb_ss->dev, "%s is already bound\n", + usb_ss->gadget.name); + return -EBUSY; + } + + dev_dbg(&usb_ss->dev, "%s begins\n", __func__); + + spin_lock_irqsave(&usb_ss->lock, flags); + usb_ss->gadget_driver = driver; + if (!usb_ss->start_gadget) { + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } + + __cdns3_gadget_start(usb_ss); + spin_unlock_irqrestore(&usb_ss->lock, flags); + dev_dbg(&usb_ss->dev, "%s ends\n", __func__); + return 0; } /** - * cdns3_gadget_udc_stop Stops gadget + * usb_ss_gadget_udc_stop Stops gadget * @gadget: gadget object * * Returns 0 */ -static int cdns3_gadget_udc_stop(struct usb_gadget *gadget) +static int usb_ss_gadget_udc_stop(struct usb_gadget *gadget) { - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); - struct cdns3_endpoint *priv_ep; - u32 bEndpointAddress; + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(gadget); struct usb_ep *ep; - int ret = 0; - int val; - - priv_dev->gadget_driver = NULL; + struct usb_ss_endpoint *usb_ss_ep; + int i; + u32 bEndpointAddress; - priv_dev->onchip_used_size = 0; - priv_dev->out_mem_is_allocated = 0; - priv_dev->gadget.speed = USB_SPEED_UNKNOWN; + usb_ss->gadget_driver = NULL; + if (!usb_ss->start_gadget) + return 0; - list_for_each_entry(ep, &priv_dev->gadget.ep_list, ep_list) { - priv_ep = ep_to_cdns3_ep(ep); - bEndpointAddress = priv_ep->num | priv_ep->dir; - cdns3_select_ep(priv_dev, bEndpointAddress); - writel(EP_CMD_EPRST, &priv_dev->regs->ep_cmd); - readl_poll_timeout_atomic(&priv_dev->regs->ep_cmd, val, - !(val & EP_CMD_EPRST), 100); + list_for_each_entry(ep, &usb_ss->gadget.ep_list, ep_list) { + usb_ss_ep = to_usb_ss_ep(ep); + bEndpointAddress = usb_ss_ep->num | usb_ss_ep->dir; + usb_ss_ep->used = false; + select_ep(usb_ss, bEndpointAddress); + cdns_writel(&usb_ss->regs->ep_cmd, EP_CMD__EPRST__MASK); + while (cdns_readl(&usb_ss->regs->ep_cmd) + & EP_CMD__EPRST__MASK) + ; } /* disable interrupt for device */ - writel(0, &priv_dev->regs->usb_ien); - writel(USB_CONF_DEVDS, &priv_dev->regs->usb_conf); + cdns_writel(&usb_ss->regs->usb_ien, 0); + cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK); - return ret; + for (i = 0; i < usb_ss->ep_nums ; i++) + usb_ss_free_trb_pool(usb_ss->eps[i]); + + return 0; } -static void cdns3_gadget_udc_set_speed(struct usb_gadget *gadget, - enum usb_device_speed speed) +static void cdns3_gadget_set_speed(struct usb_gadget *g, + enum usb_device_speed speed) { - struct cdns3_device *priv_dev = gadget_to_cdns3_device(gadget); - - switch (speed) { - case USB_SPEED_FULL: - writel(USB_CONF_SFORCE_FS, &priv_dev->regs->usb_conf); - writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf); - break; - case USB_SPEED_HIGH: - writel(USB_CONF_USB3DIS, &priv_dev->regs->usb_conf); - break; - case USB_SPEED_SUPER: - break; - default: - dev_err(priv_dev->dev, "invalid speed parameter %d\n", speed); - } + struct usb_ss_dev *usb_ss = gadget_to_usb_ss(g); - priv_dev->gadget.speed = speed; + usb_ss->gadget.max_speed = speed; } -static const struct usb_gadget_ops cdns3_gadget_ops = { - .get_frame = cdns3_gadget_get_frame, - .wakeup = cdns3_gadget_wakeup, - .set_selfpowered = cdns3_gadget_set_selfpowered, - .pullup = cdns3_gadget_pullup, - .udc_start = cdns3_gadget_udc_start, - .udc_stop = cdns3_gadget_udc_stop, - .match_ep = cdns3_gadget_match_ep, - .udc_set_speed = cdns3_gadget_udc_set_speed, -}; - -static void cdns3_free_all_eps(struct cdns3_device *priv_dev) -{ - int i; +static const struct usb_gadget_ops usb_ss_gadget_ops = { + .get_frame = usb_ss_gadget_get_frame, + .wakeup = usb_ss_gadget_wakeup, + .set_selfpowered = usb_ss_gadget_set_selfpowered, + .pullup = usb_ss_gadget_pullup, + .udc_start = usb_ss_gadget_udc_start, + .udc_stop = usb_ss_gadget_udc_stop, + .ep_conf = usb_ss_gadget_ep_conf, + .udc_set_speed = cdns3_gadget_set_speed, - /* ep0 OUT point to ep0 IN. */ - priv_dev->eps[16] = NULL; - - for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) - if (priv_dev->eps[i]) { - cdns3_free_trb_pool(priv_dev->eps[i]); - devm_kfree(priv_dev->dev, priv_dev->eps[i]); - } -} +}; /** - * cdns3_init_eps Initializes software endpoints of gadget - * @cdns3: extended gadget object + * usb_ss_init_ep Initializes software endpoints of gadget + * @usb_ss: extended gadget object * * Returns 0 on success, error code elsewhere */ -static int cdns3_init_eps(struct cdns3_device *priv_dev) +static int usb_ss_init_ep(struct usb_ss_dev *usb_ss) { - u32 ep_enabled_reg, iso_ep_reg; - struct cdns3_endpoint *priv_ep; - int ep_dir, ep_number; - u32 ep_mask; - int ret = 0; + struct usb_ss_endpoint *usb_ss_ep; + u32 ep_enabled_reg, iso_ep_reg, bulk_ep_reg; int i; + int ep_reg_pos, ep_dir, ep_number; + int found_endpoints = 0; /* Read it from USB_CAP3 to USB_CAP5 */ - ep_enabled_reg = readl(&priv_dev->regs->usb_cap3); - iso_ep_reg = readl(&priv_dev->regs->usb_cap4); - - dev_dbg(priv_dev->dev, "Initializing non-zero endpoints\n"); + ep_enabled_reg = 0x00ff00ff; + iso_ep_reg = 0x00fe00fe; + bulk_ep_reg = 0x00fe00fe; - for (i = 0; i < CDNS3_ENDPOINTS_MAX_COUNT; i++) { - ep_dir = i >> 4; /* i div 16 */ - ep_number = i & 0xF; /* i % 16 */ - ep_mask = BIT(i); + dev_dbg(&usb_ss->dev, "Initializing non-zero endpoints\n"); + dev_dbg(&usb_ss->dev, + "ep_enabled_reg: 0x%x, iso_ep_reg: 0x%x, bulk_ep_reg:0x%x\n", + ep_enabled_reg, iso_ep_reg, bulk_ep_reg); - if (!(ep_enabled_reg & ep_mask)) - continue; + for (i = 0; i < USB_SS_ENDPOINTS_MAX_COUNT; i++) { + ep_number = (i / 2) + 1; + ep_dir = i % 2; + ep_reg_pos = (16 * ep_dir) + ep_number; - if (ep_dir && !ep_number) { - priv_dev->eps[i] = priv_dev->eps[0]; + if (!(ep_enabled_reg & (1uL << ep_reg_pos))) continue; - } - priv_ep = devm_kzalloc(priv_dev->dev, sizeof(*priv_ep), - GFP_KERNEL); - if (!priv_ep) { - ret = -ENOMEM; - goto err; - } + /* create empty endpoint object */ + usb_ss_ep = devm_kzalloc(&usb_ss->dev, sizeof(*usb_ss_ep), + GFP_KERNEL); + if (!usb_ss_ep) + return -ENOMEM; /* set parent of endpoint object */ - priv_ep->cdns3_dev = priv_dev; - priv_dev->eps[i] = priv_ep; - priv_ep->num = ep_number; - priv_ep->dir = ep_dir ? USB_DIR_IN : USB_DIR_OUT; - - if (!ep_number) { - ret = cdns3_init_ep0(priv_dev, priv_ep); - if (ret) { - dev_err(priv_dev->dev, "Failed to init ep0\n"); - goto err; - } - } else { - snprintf(priv_ep->name, sizeof(priv_ep->name), "ep%d%s", - ep_number, !!ep_dir ? "in" : "out"); - priv_ep->endpoint.name = priv_ep->name; - - usb_ep_set_maxpacket_limit(&priv_ep->endpoint, - CDNS3_EP_MAX_PACKET_LIMIT); - priv_ep->endpoint.max_streams = CDNS3_EP_MAX_STREAMS; - priv_ep->endpoint.ops = &cdns3_gadget_ep_ops; - if (ep_dir) - priv_ep->endpoint.caps.dir_in = 1; - else - priv_ep->endpoint.caps.dir_out = 1; - - if (iso_ep_reg & ep_mask) - priv_ep->endpoint.caps.type_iso = 1; + usb_ss_ep->usb_ss = usb_ss; + + /* set index of endpoint in endpoints container */ + usb_ss->eps[found_endpoints++] = usb_ss_ep; + + /* set name of endpoint */ + snprintf(usb_ss_ep->name, sizeof(usb_ss_ep->name), "ep%d%s", + ep_number, !!ep_dir ? "in" : "out"); + usb_ss_ep->endpoint.name = usb_ss_ep->name; + dev_dbg(&usb_ss->dev, "Initializing endpoint: %s\n", + usb_ss_ep->name); + + usb_ep_set_maxpacket_limit(&usb_ss_ep->endpoint, + ENDPOINT_MAX_PACKET_LIMIT); + usb_ss_ep->endpoint.max_streams = ENDPOINT_MAX_STREAMS; + usb_ss_ep->endpoint.ops = &usb_ss_gadget_ep_ops; + if (ep_dir) + usb_ss_ep->caps.dir_in = 1; + else + usb_ss_ep->caps.dir_out = 1; - priv_ep->endpoint.caps.type_bulk = 1; - priv_ep->endpoint.caps.type_int = 1; + /* check endpoint type */ + if (iso_ep_reg & (1uL << ep_reg_pos)) + usb_ss_ep->caps.type_iso = 1; - list_add_tail(&priv_ep->endpoint.ep_list, - &priv_dev->gadget.ep_list); + if (bulk_ep_reg & (1uL << ep_reg_pos)) { + usb_ss_ep->caps.type_bulk = 1; + usb_ss_ep->caps.type_int = 1; + usb_ss_ep->endpoint.maxburst = 15; } - priv_ep->flags = 0; - - dev_info(priv_dev->dev, "Initialized %s support: %s %s\n", - priv_ep->name, - priv_ep->endpoint.caps.type_bulk ? "BULK, INT" : "", - priv_ep->endpoint.caps.type_iso ? "ISO" : ""); - - INIT_LIST_HEAD(&priv_ep->pending_req_list); - INIT_LIST_HEAD(&priv_ep->deferred_req_list); - INIT_LIST_HEAD(&priv_ep->wa2_descmiss_req_list); + list_add_tail(&usb_ss_ep->endpoint.ep_list, + &usb_ss->gadget.ep_list); + INIT_LIST_HEAD(&usb_ss_ep->request_list); + INIT_LIST_HEAD(&usb_ss_ep->ep_match_pending_list); } + usb_ss->ep_nums = found_endpoints; return 0; -err: - cdns3_free_all_eps(priv_dev); - return -ENOMEM; } -void cdns3_gadget_exit(struct cdns3 *cdns) +/** + * usb_ss_init_ep0 Initializes software endpoint 0 of gadget + * @usb_ss: extended gadget object + * + * Returns 0 on success, error code elsewhere + */ +static int usb_ss_init_ep0(struct usb_ss_dev *usb_ss) { - struct cdns3_device *priv_dev; - - priv_dev = cdns->gadget_dev; + struct usb_ss_endpoint *ep0; - usb_del_gadget_udc(&priv_dev->gadget); + dev_dbg(&usb_ss->dev, "Initializing EP0\n"); + ep0 = devm_kzalloc(&usb_ss->dev, sizeof(struct usb_ss_endpoint), + GFP_KERNEL); - cdns3_free_all_eps(priv_dev); - - while (!list_empty(&priv_dev->aligned_buf_list)) { - struct cdns3_aligned_buf *buf; - - buf = cdns3_next_align_buf(&priv_dev->aligned_buf_list); - dma_free_coherent(buf->buf); - - list_del(&buf->list); - kfree(buf); - } + if (!ep0) + return -ENOMEM; - dma_free_coherent(priv_dev->setup_buf); + /* fill CDNS fields */ + ep0->usb_ss = usb_ss; + sprintf(ep0->name, "ep0"); + + /* fill linux fields */ + ep0->endpoint.ops = &usb_ss_gadget_ep0_ops; + ep0->endpoint.maxburst = 1; + usb_ep_set_maxpacket_limit(&ep0->endpoint, ENDPOINT0_MAX_PACKET_LIMIT); + ep0->address = 0; + ep0->enabled = 1; + ep0->caps.type_control = 1; + ep0->caps.dir_in = 1; + ep0->caps.dir_out = 1; + ep0->endpoint.name = ep0->name; + ep0->endpoint.desc = &cdns3_gadget_ep0_desc; + usb_ss->gadget.ep0 = &ep0->endpoint; + INIT_LIST_HEAD(&ep0->request_list); - kfree(priv_dev->zlp_buf); - kfree(priv_dev); - cdns->gadget_dev = NULL; - cdns3_drd_switch_gadget(cdns, 0); + return 0; } -static int cdns3_gadget_start(struct cdns3 *cdns) +static int __cdns3_gadget_init(struct cdns3 *cdns) { - struct cdns3_device *priv_dev; - u32 max_speed; + struct usb_ss_dev *usb_ss; int ret; + struct udevice *dev; + struct cdns3_generic_peripheral *priv = container_of(cdns, + struct cdns3_generic_peripheral, cdns3); + + usb_ss = &priv->usb_ss_dev; + dev = &usb_ss->dev; + dev->parent = cdns->dev; + dev_set_name(dev, "gadget-cdns3-dev"); + cdns->gadget_dev = dev; + usb_ss->sysdev = cdns->dev; + ret = device_register(dev); + if (ret) + goto err1; - priv_dev = kzalloc(sizeof(*priv_dev), GFP_KERNEL); - if (!priv_dev) - return -ENOMEM; - - cdns->gadget_dev = priv_dev; - priv_dev->sysdev = cdns->dev; - priv_dev->dev = cdns->dev; - priv_dev->regs = cdns->dev_regs; - - dev_read_u32(priv_dev->dev, "cdns,on-chip-buff-size", - &priv_dev->onchip_buffers); - - if (priv_dev->onchip_buffers <= 0) { - u32 reg = readl(&priv_dev->regs->usb_cap2); - - priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg); - } - - if (!priv_dev->onchip_buffers) - priv_dev->onchip_buffers = 256; - - max_speed = usb_get_maximum_speed(dev_ofnode(cdns->dev)); - - /* Check the maximum_speed parameter */ - switch (max_speed) { - case USB_SPEED_FULL: - /* fall through */ - case USB_SPEED_HIGH: - /* fall through */ - case USB_SPEED_SUPER: - break; - default: - dev_err(cdns->dev, "invalid maximum_speed parameter %d\n", - max_speed); - /* fall through */ - case USB_SPEED_UNKNOWN: - /* default to superspeed */ - max_speed = USB_SPEED_SUPER; - break; - } + usb_ss->regs = cdns->dev_regs; /* fill gadget fields */ - priv_dev->gadget.max_speed = max_speed; - priv_dev->gadget.speed = USB_SPEED_UNKNOWN; - priv_dev->gadget.ops = &cdns3_gadget_ops; - priv_dev->gadget.name = "cdns3-gadget"; -#ifndef __UBOOT__ - priv_dev->gadget.name = "usb-ss-gadget"; - priv_dev->gadget.sg_supported = 1; - priv_dev->gadget.quirk_avoids_skb_reserve = 1; -#endif + usb_ss->gadget.ops = &usb_ss_gadget_ops; + usb_ss->gadget.max_speed = USB_SPEED_SUPER; + usb_ss->gadget.speed = USB_SPEED_UNKNOWN; + usb_ss->gadget.name = "cdns3-gadget"; + usb_ss->is_connected = 0; + spin_lock_init(&usb_ss->lock); - spin_lock_init(&priv_dev->lock); - INIT_WORK(&priv_dev->pending_status_wq, - cdns3_pending_setup_status_handler); + usb_ss->in_standby_mode = 1; /* initialize endpoint container */ - INIT_LIST_HEAD(&priv_dev->gadget.ep_list); - INIT_LIST_HEAD(&priv_dev->aligned_buf_list); - - ret = cdns3_init_eps(priv_dev); + INIT_LIST_HEAD(&usb_ss->gadget.ep_list); + INIT_LIST_HEAD(&usb_ss->ep_match_list); + ret = usb_ss_init_ep0(usb_ss); if (ret) { - dev_err(priv_dev->dev, "Failed to create endpoints\n"); - goto err1; + dev_err(dev, "Failed to create endpoint 0\n"); + ret = -ENOMEM; + goto err2; } - /* allocate memory for setup packet buffer */ - priv_dev->setup_buf = - dma_alloc_coherent(8, (unsigned long *)&priv_dev->setup_dma); - if (!priv_dev->setup_buf) { + ret = usb_ss_init_ep(usb_ss); + if (ret) { + dev_err(dev, "Failed to create non zero endpoints\n"); ret = -ENOMEM; goto err2; } - priv_dev->dev_ver = readl(&priv_dev->regs->usb_cap6); - - dev_dbg(priv_dev->dev, "Device Controller version: %08x\n", - readl(&priv_dev->regs->usb_cap6)); - dev_dbg(priv_dev->dev, "USB Capabilities:: %08x\n", - readl(&priv_dev->regs->usb_cap1)); - dev_dbg(priv_dev->dev, "On-Chip memory cnfiguration: %08x\n", - readl(&priv_dev->regs->usb_cap2)); - - priv_dev->dev_ver = GET_DEV_BASE_VERSION(priv_dev->dev_ver); + /* allocate memory for default endpoint TRB */ + usb_ss->trb_ep0 = (u32 *)dma_alloc_coherent(20, + (unsigned long *)&usb_ss->trb_ep0_dma); + if (!usb_ss->trb_ep0) { + dev_err(dev, "Failed to allocate memory for ep0 TRB\n"); + ret = -ENOMEM; + goto err2; + } - priv_dev->zlp_buf = kzalloc(CDNS3_EP_ZLP_BUF_SIZE, GFP_KERNEL); - if (!priv_dev->zlp_buf) { + /* allocate memory for setup packet buffer */ + usb_ss->setup = (u8 *)dma_alloc_coherent(8, + (unsigned long *)&usb_ss->setup_dma); + if (!usb_ss->setup) { + dev_err(dev, "Failed to allocate memory for SETUP buffer\n"); ret = -ENOMEM; goto err3; } /* add USB gadget device */ - ret = usb_add_gadget_udc((struct device *)priv_dev->dev, - &priv_dev->gadget); + ret = usb_add_gadget_udc((struct device *)(&usb_ss->dev), + &usb_ss->gadget); if (ret < 0) { - dev_err(priv_dev->dev, - "Failed to register USB device controller\n"); + dev_err(dev, "Failed to register USB device controller\n"); goto err4; } return 0; + err4: - kfree(priv_dev->zlp_buf); + dma_free_coherent(usb_ss->setup); err3: - dma_free_coherent(priv_dev->setup_buf); + dma_free_coherent(usb_ss->trb_ep0); err2: - cdns3_free_all_eps(priv_dev); err1: cdns->gadget_dev = NULL; + return ret; } -static int __cdns3_gadget_init(struct cdns3 *cdns) +/** + * cdns3_gadget_remove: parent must call this to remove UDC + * + * cdns: cdns3 instance + * + */ +void cdns3_gadget_remove(struct cdns3 *cdns) { - int ret = 0; + struct usb_ss_dev *usb_ss; - cdns3_drd_switch_gadget(cdns, 1); - - ret = cdns3_gadget_start(cdns); - if (ret) - return ret; + if (!cdns->roles[CDNS3_ROLE_GADGET]) + return; - return 0; + usb_ss = container_of(cdns->gadget_dev, struct usb_ss_dev, dev); + usb_del_gadget_udc(&usb_ss->gadget); + dma_free_coherent(usb_ss->setup); + dma_free_coherent(usb_ss->trb_ep0); + device_unregister(cdns->gadget_dev); + cdns->gadget_dev = NULL; } -static int cdns3_gadget_suspend(struct cdns3 *cdns, bool do_wakeup) +static void __cdns3_gadget_start(struct usb_ss_dev *usb_ss) { - struct cdns3_device *priv_dev = cdns->gadget_dev; + u32 usb_conf_reg = 0; - cdns3_disconnect_gadget(priv_dev); + /* configure endpoint 0 hardware */ + cdns_ep0_config(usb_ss); - priv_dev->gadget.speed = USB_SPEED_UNKNOWN; - usb_gadget_set_state(&priv_dev->gadget, USB_STATE_NOTATTACHED); - cdns3_hw_reset_eps_config(priv_dev); + /* enable interrupts for endpoint 0 (in and out) */ + cdns_writel(&usb_ss->regs->ep_ien, + EP_IEN__EOUTEN0__MASK | EP_IEN__EINEN0__MASK); + + /* enable interrupt for device */ + cdns_writel(&usb_ss->regs->usb_ien, + USB_IEN__U2RESIEN__MASK + | USB_ISTS__DIS2I__MASK + | USB_IEN__CON2IEN__MASK + | USB_IEN__UHRESIEN__MASK + | USB_IEN__UWRESIEN__MASK + | USB_IEN__DISIEN__MASK + | USB_IEN__CONIEN__MASK + | USB_IEN__U3EXTIEN__MASK + | USB_IEN__L2ENTIEN__MASK + | USB_IEN__L2EXTIEN__MASK); + + usb_conf_reg = USB_CONF__CLK2OFFDS__MASK | + USB_CONF__L1DS__MASK; + if (usb_ss->gadget.max_speed == USB_SPEED_HIGH) + usb_conf_reg |= USB_CONF__USB3DIS__MASK; + cdns_writel(&usb_ss->regs->usb_conf, usb_conf_reg); + + cdns_writel(&usb_ss->regs->usb_conf, + USB_CONF__U1DS__MASK + | USB_CONF__U2DS__MASK + ); + + cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVEN__MASK); + + cdns_writel(&usb_ss->regs->dbg_link1, + DBG_LINK1__LFPS_MIN_GEN_U1_EXIT_SET__MASK | + DBG_LINK1__LFPS_MIN_GEN_U1_EXIT__WRITE(0x3C)); +} - /* disable interrupt for device */ - writel(0, &priv_dev->regs->usb_ien); +static int cdns3_gadget_start(struct cdns3 *cdns) +{ + struct usb_ss_dev *usb_ss = container_of(cdns->gadget_dev, + struct usb_ss_dev, dev); + unsigned long flags; + + dev_dbg(&usb_ss->dev, "%s begins\n", __func__); + + pm_runtime_get_sync(cdns->dev); + spin_lock_irqsave(&usb_ss->lock, flags); + usb_ss->start_gadget = 1; + if (!usb_ss->gadget_driver) { + spin_unlock_irqrestore(&usb_ss->lock, flags); + return 0; + } - cdns3_gadget_pullup(&priv_dev->gadget, 0); + __cdns3_gadget_start(usb_ss); + usb_ss->in_standby_mode = 0; + spin_unlock_irqrestore(&usb_ss->lock, flags); + dev_dbg(&usb_ss->dev, "%s ends\n", __func__); return 0; } -static int cdns3_gadget_resume(struct cdns3 *cdns, bool hibernated) +static void __cdns3_gadget_stop(struct cdns3 *cdns) { - struct cdns3_device *priv_dev = cdns->gadget_dev; - - if (!priv_dev->gadget_driver) - return 0; + struct usb_ss_dev *usb_ss; + unsigned long flags; - cdns3_gadget_config(priv_dev); + usb_ss = container_of(cdns->gadget_dev, struct usb_ss_dev, dev); + if (usb_ss->gadget_driver) + usb_ss->gadget_driver->disconnect(&usb_ss->gadget); + usb_gadget_disconnect(&usb_ss->gadget); + spin_lock_irqsave(&usb_ss->lock, flags); + /* disable interrupt for device */ + cdns_writel(&usb_ss->regs->usb_ien, 0); + cdns_writel(&usb_ss->regs->usb_conf, USB_CONF__DEVDS__MASK); + usb_ss->start_gadget = 0; + spin_unlock_irqrestore(&usb_ss->lock, flags); +} - return 0; +static void cdns3_gadget_stop(struct cdns3 *cdns) +{ + if (cdns->role == CDNS3_ROLE_GADGET) + __cdns3_gadget_stop(cdns); } /** @@ -2729,36 +2231,10 @@ int cdns3_gadget_init(struct cdns3 *cdns) if (!rdrv) return -ENOMEM; - rdrv->start = __cdns3_gadget_init; - rdrv->stop = cdns3_gadget_exit; - rdrv->suspend = cdns3_gadget_suspend; - rdrv->resume = cdns3_gadget_resume; - rdrv->state = CDNS3_ROLE_STATE_INACTIVE; + rdrv->start = cdns3_gadget_start; + rdrv->stop = cdns3_gadget_stop; + rdrv->irq = cdns_irq_handler_thread; rdrv->name = "gadget"; - cdns->roles[USB_ROLE_DEVICE] = rdrv; - - return 0; -} - -/** - * cdns3_gadget_uboot_handle_interrupt - handle cdns3 gadget interrupt - * @cdns: pointer to struct cdns3 - * - * Handles ep0 and gadget interrupt - */ -static void cdns3_gadget_uboot_handle_interrupt(struct cdns3 *cdns) -{ - int ret = cdns3_device_irq_handler(0, cdns); - - if (ret == IRQ_WAKE_THREAD) - cdns3_device_thread_irq_handler(0, cdns); -} - -int dm_usb_gadget_handle_interrupts(struct udevice *dev) -{ - struct cdns3 *cdns = dev_get_priv(dev); - - cdns3_gadget_uboot_handle_interrupt(cdns); - - return 0; + cdns->roles[CDNS3_ROLE_GADGET] = rdrv; + return __cdns3_gadget_init(cdns); } diff --git a/drivers/usb/cdns3/gadget.h b/drivers/usb/cdns3/gadget.h index 8803fa48bd3..e92f283b848 100644 --- a/drivers/usb/cdns3/gadget.h +++ b/drivers/usb/cdns3/gadget.h @@ -1,1339 +1,216 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* - * USBSS device controller driver header file - * - * Copyright (C) 2018-2019 Cadence. - * Copyright (C) 2017-2018 NXP - * - * Author: Pawel Laszczak - * Pawel Jez - * Peter Chen - */ -#ifndef __LINUX_CDNS3_GADGET -#define __LINUX_CDNS3_GADGET -#include -#include - -/* - * USBSS-DEV register interface. - * This corresponds to the USBSS Device Controller Interface - */ - -/** - * struct cdns3_usb_regs - device controller registers. - * @usb_conf: Global Configuration. - * @usb_sts: Global Status. - * @usb_cmd: Global Command. - * @usb_itpn: ITP/SOF number. - * @usb_lpm: Global Command. - * @usb_ien: USB Interrupt Enable. - * @usb_ists: USB Interrupt Status. - * @ep_sel: Endpoint Select. - * @ep_traddr: Endpoint Transfer Ring Address. - * @ep_cfg: Endpoint Configuration. - * @ep_cmd: Endpoint Command. - * @ep_sts: Endpoint Status. - * @ep_sts_sid: Endpoint Status. - * @ep_sts_en: Endpoint Status Enable. - * @drbl: Doorbell. - * @ep_ien: EP Interrupt Enable. - * @ep_ists: EP Interrupt Status. - * @usb_pwr: Global Power Configuration. - * @usb_conf2: Global Configuration 2. - * @usb_cap1: Capability 1. - * @usb_cap2: Capability 2. - * @usb_cap3: Capability 3. - * @usb_cap4: Capability 4. - * @usb_cap5: Capability 5. - * @usb_cap6: Capability 6. - * @usb_cpkt1: Custom Packet 1. - * @usb_cpkt2: Custom Packet 2. - * @usb_cpkt3: Custom Packet 3. - * @ep_dma_ext_addr: Upper address for DMA operations. - * @buf_addr: Address for On-chip Buffer operations. - * @buf_data: Data for On-chip Buffer operations. - * @buf_ctrl: On-chip Buffer Access Control. - * @dtrans: DMA Transfer Mode. - * @tdl_from_trb: Source of TD Configuration. - * @tdl_beh: TDL Behavior Configuration. - * @ep_tdl: Endpoint TDL. - * @tdl_beh2: TDL Behavior 2 Configuration. - * @dma_adv_td: DMA Advance TD Configuration. - * @reserved1: Reserved. - * @cfg_regs: Configuration. - * @reserved2: Reserved. - * @dma_axi_ctrl: AXI Control. - * @dma_axi_id: AXI ID register. - * @dma_axi_cap: AXI Capability. - * @dma_axi_ctrl0: AXI Control 0. - * @dma_axi_ctrl1: AXI Control 1. + * Copyright (C) 2016 Cadence Design Systems - http://www.cadence.com + * Copyright 2019 NXP */ -struct cdns3_usb_regs { - __le32 usb_conf; - __le32 usb_sts; - __le32 usb_cmd; - __le32 usb_itpn; - __le32 usb_lpm; - __le32 usb_ien; - __le32 usb_ists; - __le32 ep_sel; - __le32 ep_traddr; - __le32 ep_cfg; - __le32 ep_cmd; - __le32 ep_sts; - __le32 ep_sts_sid; - __le32 ep_sts_en; - __le32 drbl; - __le32 ep_ien; - __le32 ep_ists; - __le32 usb_pwr; - __le32 usb_conf2; - __le32 usb_cap1; - __le32 usb_cap2; - __le32 usb_cap3; - __le32 usb_cap4; - __le32 usb_cap5; - __le32 usb_cap6; - __le32 usb_cpkt1; - __le32 usb_cpkt2; - __le32 usb_cpkt3; - __le32 ep_dma_ext_addr; - __le32 buf_addr; - __le32 buf_data; - __le32 buf_ctrl; - __le32 dtrans; - __le32 tdl_from_trb; - __le32 tdl_beh; - __le32 ep_tdl; - __le32 tdl_beh2; - __le32 dma_adv_td; - __le32 reserved1[26]; - __le32 cfg_reg1; - __le32 dbg_link1; - __le32 dbg_link2; - __le32 cfg_regs[74]; - __le32 reserved2[51]; - __le32 dma_axi_ctrl; - __le32 dma_axi_id; - __le32 dma_axi_cap; - __le32 dma_axi_ctrl0; - __le32 dma_axi_ctrl1; -}; +#ifndef __DRIVERS_CDNS3_GADGET +#define __DRIVERS_CDNS3_GADGET -/* USB_CONF - bitmasks */ -/* Reset USB device configuration. */ -#define USB_CONF_CFGRST BIT(0) -/* Set Configuration. */ -#define USB_CONF_CFGSET BIT(1) -/* Disconnect USB device in SuperSpeed. */ -#define USB_CONF_USB3DIS BIT(3) -/* Disconnect USB device in HS/FS */ -#define USB_CONF_USB2DIS BIT(4) -/* Little Endian access - default */ -#define USB_CONF_LENDIAN BIT(5) -/* - * Big Endian access. Driver assume that byte order for - * SFRs access always is as Little Endian so this bit - * is not used. - */ -#define USB_CONF_BENDIAN BIT(6) -/* Device software reset. */ -#define USB_CONF_SWRST BIT(7) -/* Singular DMA transfer mode. Only for VER < DEV_VER_V3*/ -#define USB_CONF_DSING BIT(8) -/* Multiple DMA transfers mode. Only for VER < DEV_VER_V3 */ -#define USB_CONF_DMULT BIT(9) -/* DMA clock turn-off enable. */ -#define USB_CONF_DMAOFFEN BIT(10) -/* DMA clock turn-off disable. */ -#define USB_CONF_DMAOFFDS BIT(11) -/* Clear Force Full Speed. */ -#define USB_CONF_CFORCE_FS BIT(12) -/* Set Force Full Speed. */ -#define USB_CONF_SFORCE_FS BIT(13) -/* Device enable. */ -#define USB_CONF_DEVEN BIT(14) -/* Device disable. */ -#define USB_CONF_DEVDS BIT(15) -/* L1 LPM state entry enable (used in HS/FS mode). */ -#define USB_CONF_L1EN BIT(16) -/* L1 LPM state entry disable (used in HS/FS mode). */ -#define USB_CONF_L1DS BIT(17) -/* USB 2.0 clock gate disable. */ -#define USB_CONF_CLK2OFFEN BIT(18) -/* USB 2.0 clock gate enable. */ -#define USB_CONF_CLK2OFFDS BIT(19) -/* L0 LPM state entry request (used in HS/FS mode). */ -#define USB_CONF_LGO_L0 BIT(20) -/* USB 3.0 clock gate disable. */ -#define USB_CONF_CLK3OFFEN BIT(21) -/* USB 3.0 clock gate enable. */ -#define USB_CONF_CLK3OFFDS BIT(22) -/* Bit 23 is reserved*/ -/* U1 state entry enable (used in SS mode). */ -#define USB_CONF_U1EN BIT(24) -/* U1 state entry disable (used in SS mode). */ -#define USB_CONF_U1DS BIT(25) -/* U2 state entry enable (used in SS mode). */ -#define USB_CONF_U2EN BIT(26) -/* U2 state entry disable (used in SS mode). */ -#define USB_CONF_U2DS BIT(27) -/* U0 state entry request (used in SS mode). */ -#define USB_CONF_LGO_U0 BIT(28) -/* U1 state entry request (used in SS mode). */ -#define USB_CONF_LGO_U1 BIT(29) -/* U2 state entry request (used in SS mode). */ -#define USB_CONF_LGO_U2 BIT(30) -/* SS.Inactive state entry request (used in SS mode) */ -#define USB_CONF_LGO_SSINACT BIT(31) +#include "dev-regs-map.h" -/* USB_STS - bitmasks */ -/* - * Configuration status. - * 1 - device is in the configured state. - * 0 - device is not configured. - */ -#define USB_STS_CFGSTS_MASK BIT(0) -#define USB_STS_CFGSTS(p) ((p) & USB_STS_CFGSTS_MASK) -/* - * On-chip memory overflow. - * 0 - On-chip memory status OK. - * 1 - On-chip memory overflow. - */ -#define USB_STS_OV_MASK BIT(1) -#define USB_STS_OV(p) ((p) & USB_STS_OV_MASK) -/* - * SuperSpeed connection status. - * 0 - USB in SuperSpeed mode disconnected. - * 1 - USB in SuperSpeed mode connected. - */ -#define USB_STS_USB3CONS_MASK BIT(2) -#define USB_STS_USB3CONS(p) ((p) & USB_STS_USB3CONS_MASK) -/* - * DMA transfer configuration status. - * 0 - single request. - * 1 - multiple TRB chain - * Supported only for controller version < DEV_VER_V3 - */ -#define USB_STS_DTRANS_MASK BIT(3) -#define USB_STS_DTRANS(p) ((p) & USB_STS_DTRANS_MASK) -/* - * Device speed. - * 0 - Undefined (value after reset). - * 1 - Low speed - * 2 - Full speed - * 3 - High speed - * 4 - Super speed - */ -#define USB_STS_USBSPEED_MASK GENMASK(6, 4) -#define USB_STS_USBSPEED(p) (((p) & USB_STS_USBSPEED_MASK) >> 4) -#define USB_STS_LS (0x1 << 4) -#define USB_STS_FS (0x2 << 4) -#define USB_STS_HS (0x3 << 4) -#define USB_STS_SS (0x4 << 4) -#define DEV_UNDEFSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == (0x0 << 4)) -#define DEV_LOWSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_LS) -#define DEV_FULLSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_FS) -#define DEV_HIGHSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_HS) -#define DEV_SUPERSPEED(p) (((p) & USB_STS_USBSPEED_MASK) == USB_STS_SS) -/* - * Endianness for SFR access. - * 0 - Little Endian order (default after hardware reset). - * 1 - Big Endian order - */ -#define USB_STS_ENDIAN_MASK BIT(7) -#define USB_STS_ENDIAN(p) ((p) & USB_STS_ENDIAN_MASK) -/* - * HS/FS clock turn-off status. - * 0 - hsfs clock is always on. - * 1 - hsfs clock turn-off in L2 (HS/FS mode) is enabled - * (default after hardware reset). - */ -#define USB_STS_CLK2OFF_MASK BIT(8) -#define USB_STS_CLK2OFF(p) ((p) & USB_STS_CLK2OFF_MASK) -/* - * PCLK clock turn-off status. - * 0 - pclk clock is always on. - * 1 - pclk clock turn-off in U3 (SS mode) is enabled - * (default after hardware reset). - */ -#define USB_STS_CLK3OFF_MASK BIT(9) -#define USB_STS_CLK3OFF(p) ((p) & USB_STS_CLK3OFF_MASK) -/* - * Controller in reset state. - * 0 - Internal reset is active. - * 1 - Internal reset is not active and controller is fully operational. - */ -#define USB_STS_IN_RST_MASK BIT(10) -#define USB_STS_IN_RST(p) ((p) & USB_STS_IN_RST_MASK) -/* - * Status of the "TDL calculation basing on TRB" feature. - * 0 - disabled - * 1 - enabled - * Supported only for DEV_VER_V2 controller version. - */ -#define USB_STS_TDL_TRB_ENABLED BIT(11) -/* - * Device enable Status. - * 0 - USB device is disabled (VBUS input is disconnected from internal logic). - * 1 - USB device is enabled (VBUS input is connected to the internal logic). - */ -#define USB_STS_DEVS_MASK BIT(14) -#define USB_STS_DEVS(p) ((p) & USB_STS_DEVS_MASK) -/* - * Address status. - * 0 - USB device is default state. - * 1 - USB device is at least in address state. - */ -#define USB_STS_ADDRESSED_MASK BIT(15) -#define USB_STS_ADDRESSED(p) ((p) & USB_STS_ADDRESSED_MASK) -/* - * L1 LPM state enable status (used in HS/FS mode). - * 0 - Entering to L1 LPM state disabled. - * 1 - Entering to L1 LPM state enabled. - */ -#define USB_STS_L1ENS_MASK BIT(16) -#define USB_STS_L1ENS(p) ((p) & USB_STS_L1ENS_MASK) -/* - * Internal VBUS connection status (used both in HS/FS and SS mode). - * 0 - internal VBUS is not detected. - * 1 - internal VBUS is detected. - */ -#define USB_STS_VBUSS_MASK BIT(17) -#define USB_STS_VBUSS(p) ((p) & USB_STS_VBUSS_MASK) -/* - * HS/FS LPM state (used in FS/HS mode). - * 0 - L0 State - * 1 - L1 State - * 2 - L2 State - * 3 - L3 State - */ -#define USB_STS_LPMST_MASK GENMASK(19, 18) -#define DEV_L0_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x0 << 18)) -#define DEV_L1_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x1 << 18)) -#define DEV_L2_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x2 << 18)) -#define DEV_L3_STATE(p) (((p) & USB_STS_LPMST_MASK) == (0x3 << 18)) -/* - * Disable HS status (used in FS/HS mode). - * 0 - the disconnect bit for HS/FS mode is set . - * 1 - the disconnect bit for HS/FS mode is not set. - */ -#define USB_STS_USB2CONS_MASK BIT(20) -#define USB_STS_USB2CONS(p) ((p) & USB_STS_USB2CONS_MASK) -/* - * HS/FS mode connection status (used in FS/HS mode). - * 0 - High Speed operations in USB2.0 (FS/HS) mode not disabled. - * 1 - High Speed operations in USB2.0 (FS/HS). - */ -#define USB_STS_DISABLE_HS_MASK BIT(21) -#define USB_STS_DISABLE_HS(p) ((p) & USB_STS_DISABLE_HS_MASK) -/* - * U1 state enable status (used in SS mode). - * 0 - Entering to U1 state disabled. - * 1 - Entering to U1 state enabled. - */ -#define USB_STS_U1ENS_MASK BIT(24) -#define USB_STS_U1ENS(p) ((p) & USB_STS_U1ENS_MASK) -/* - * U2 state enable status (used in SS mode). - * 0 - Entering to U2 state disabled. - * 1 - Entering to U2 state enabled. - */ -#define USB_STS_U2ENS_MASK BIT(25) -#define USB_STS_U2ENS(p) ((p) & USB_STS_U2ENS_MASK) -/* - * SuperSpeed Link LTSSM state. This field reflects USBSS-DEV current - * SuperSpeed link state - */ -#define USB_STS_LST_MASK GENMASK(29, 26) -#define DEV_LST_U0 (((p) & USB_STS_LST_MASK) == (0x0 << 26)) -#define DEV_LST_U1 (((p) & USB_STS_LST_MASK) == (0x1 << 26)) -#define DEV_LST_U2 (((p) & USB_STS_LST_MASK) == (0x2 << 26)) -#define DEV_LST_U3 (((p) & USB_STS_LST_MASK) == (0x3 << 26)) -#define DEV_LST_DISABLED (((p) & USB_STS_LST_MASK) == (0x4 << 26)) -#define DEV_LST_RXDETECT (((p) & USB_STS_LST_MASK) == (0x5 << 26)) -#define DEV_LST_INACTIVE (((p) & USB_STS_LST_MASK) == (0x6 << 26)) -#define DEV_LST_POLLING (((p) & USB_STS_LST_MASK) == (0x7 << 26)) -#define DEV_LST_RECOVERY (((p) & USB_STS_LST_MASK) == (0x8 << 26)) -#define DEV_LST_HOT_RESET (((p) & USB_STS_LST_MASK) == (0x9 << 26)) -#define DEV_LST_COMP_MODE (((p) & USB_STS_LST_MASK) == (0xa << 26)) -#define DEV_LST_LB_STATE (((p) & USB_STS_LST_MASK) == (0xb << 26)) -/* - * DMA clock turn-off status. - * 0 - DMA clock is always on (default after hardware reset). - * 1 - DMA clock turn-off in U1, U2 and U3 (SS mode) is enabled. - */ -#define USB_STS_DMAOFF_MASK BIT(30) -#define USB_STS_DMAOFF(p) ((p) & USB_STS_DMAOFF_MASK) -/* - * SFR Endian status. - * 0 - Little Endian order (default after hardware reset). - * 1 - Big Endian order. - */ -#define USB_STS_ENDIAN2_MASK BIT(31) -#define USB_STS_ENDIAN2(p) ((p) & USB_STS_ENDIAN2_MASK) - -/* USB_CMD - bitmasks */ -/* Set Function Address */ -#define USB_CMD_SET_ADDR BIT(0) -/* - * Function Address This field is saved to the device only when the field - * SET_ADDR is set '1 ' during write to USB_CMD register. - * Software is responsible for entering the address of the device during - * SET_ADDRESS request service. This field should be set immediately after - * the SETUP packet is decoded, and prior to confirmation of the status phase - */ -#define USB_CMD_FADDR_MASK GENMASK(7, 1) -#define USB_CMD_FADDR(p) (((p) << 1) & USB_CMD_FADDR_MASK) -/* Send Function Wake Device Notification TP (used only in SS mode). */ -#define USB_CMD_SDNFW BIT(8) -/* Set Test Mode (used only in HS/FS mode). */ -#define USB_CMD_STMODE BIT(9) -/* Test mode selector (used only in HS/FS mode) */ -#define USB_STS_TMODE_SEL_MASK GENMASK(11, 10) -#define USB_STS_TMODE_SEL(p) (((p) << 10) & USB_STS_TMODE_SEL_MASK) -/* - * Send Latency Tolerance Message Device Notification TP (used only - * in SS mode). - */ -#define USB_CMD_SDNLTM BIT(12) -/* Send Custom Transaction Packet (used only in SS mode) */ -#define USB_CMD_SPKT BIT(13) -/*Device Notification 'Function Wake' - Interface value (only in SS mode. */ -#define USB_CMD_DNFW_INT_MASK GENMASK(23, 16) -#define USB_STS_DNFW_INT(p) (((p) << 16) & USB_CMD_DNFW_INT_MASK) -/* - * Device Notification 'Latency Tolerance Message' -373 BELT value [7:0] - * (used only in SS mode). - */ -#define USB_CMD_DNLTM_BELT_MASK GENMASK(27, 16) -#define USB_STS_DNLTM_BELT(p) (((p) << 16) & USB_CMD_DNLTM_BELT_MASK) - -/* USB_ITPN - bitmasks */ -/* - * ITP(SS) / SOF (HS/FS) number - * In SS mode this field represent number of last ITP received from host. - * In HS/FS mode this field represent number of last SOF received from host. - */ -#define USB_ITPN_MASK GENMASK(13, 0) -#define USB_ITPN(p) ((p) & USB_ITPN_MASK) - -/* USB_LPM - bitmasks */ -/* Host Initiated Resume Duration. */ -#define USB_LPM_HIRD_MASK GENMASK(3, 0) -#define USB_LPM_HIRD(p) ((p) & USB_LPM_HIRD_MASK) -/* Remote Wakeup Enable (bRemoteWake). */ -#define USB_LPM_BRW BIT(4) - -/* USB_IEN - bitmasks */ -/* SS connection interrupt enable */ -#define USB_IEN_CONIEN BIT(0) -/* SS disconnection interrupt enable. */ -#define USB_IEN_DISIEN BIT(1) -/* USB SS warm reset interrupt enable. */ -#define USB_IEN_UWRESIEN BIT(2) -/* USB SS hot reset interrupt enable */ -#define USB_IEN_UHRESIEN BIT(3) -/* SS link U3 state enter interrupt enable (suspend).*/ -#define USB_IEN_U3ENTIEN BIT(4) -/* SS link U3 state exit interrupt enable (wakeup). */ -#define USB_IEN_U3EXTIEN BIT(5) -/* SS link U2 state enter interrupt enable.*/ -#define USB_IEN_U2ENTIEN BIT(6) -/* SS link U2 state exit interrupt enable.*/ -#define USB_IEN_U2EXTIEN BIT(7) -/* SS link U1 state enter interrupt enable.*/ -#define USB_IEN_U1ENTIEN BIT(8) -/* SS link U1 state exit interrupt enable.*/ -#define USB_IEN_U1EXTIEN BIT(9) -/* ITP/SOF packet detected interrupt enable.*/ -#define USB_IEN_ITPIEN BIT(10) -/* Wakeup interrupt enable.*/ -#define USB_IEN_WAKEIEN BIT(11) -/* Send Custom Packet interrupt enable.*/ -#define USB_IEN_SPKTIEN BIT(12) -/* HS/FS mode connection interrupt enable.*/ -#define USB_IEN_CON2IEN BIT(16) -/* HS/FS mode disconnection interrupt enable.*/ -#define USB_IEN_DIS2IEN BIT(17) -/* USB reset (HS/FS mode) interrupt enable.*/ -#define USB_IEN_U2RESIEN BIT(18) -/* LPM L2 state enter interrupt enable.*/ -#define USB_IEN_L2ENTIEN BIT(20) -/* LPM L2 state exit interrupt enable.*/ -#define USB_IEN_L2EXTIEN BIT(21) -/* LPM L1 state enter interrupt enable.*/ -#define USB_IEN_L1ENTIEN BIT(24) -/* LPM L1 state exit interrupt enable.*/ -#define USB_IEN_L1EXTIEN BIT(25) -/* Configuration reset interrupt enable.*/ -#define USB_IEN_CFGRESIEN BIT(26) -/* Start of the USB SS warm reset interrupt enable.*/ -#define USB_IEN_UWRESSIEN BIT(28) -/* End of the USB SS warm reset interrupt enable.*/ -#define USB_IEN_UWRESEIEN BIT(29) - -#define USB_IEN_INIT (USB_IEN_U2RESIEN | USB_ISTS_DIS2I | USB_IEN_CON2IEN \ - | USB_IEN_UHRESIEN | USB_IEN_UWRESIEN | USB_IEN_DISIEN \ - | USB_IEN_CONIEN | USB_IEN_U3EXTIEN | USB_IEN_L2ENTIEN \ - | USB_IEN_L2EXTIEN | USB_IEN_L1ENTIEN | USB_IEN_U3ENTIEN) - -/* USB_ISTS - bitmasks */ -/* SS Connection detected. */ -#define USB_ISTS_CONI BIT(0) -/* SS Disconnection detected. */ -#define USB_ISTS_DISI BIT(1) -/* UUSB warm reset detectede. */ -#define USB_ISTS_UWRESI BIT(2) -/* USB hot reset detected. */ -#define USB_ISTS_UHRESI BIT(3) -/* U3 link state enter detected (suspend).*/ -#define USB_ISTS_U3ENTI BIT(4) -/* U3 link state exit detected (wakeup). */ -#define USB_ISTS_U3EXTI BIT(5) -/* U2 link state enter detected.*/ -#define USB_ISTS_U2ENTI BIT(6) -/* U2 link state exit detected.*/ -#define USB_ISTS_U2EXTI BIT(7) -/* U1 link state enter detected.*/ -#define USB_ISTS_U1ENTI BIT(8) -/* U1 link state exit detected.*/ -#define USB_ISTS_U1EXTI BIT(9) -/* ITP/SOF packet detected.*/ -#define USB_ISTS_ITPI BIT(10) -/* Wakeup detected.*/ -#define USB_ISTS_WAKEI BIT(11) -/* Send Custom Packet detected.*/ -#define USB_ISTS_SPKTI BIT(12) -/* HS/FS mode connection detected.*/ -#define USB_ISTS_CON2I BIT(16) -/* HS/FS mode disconnection detected.*/ -#define USB_ISTS_DIS2I BIT(17) -/* USB reset (HS/FS mode) detected.*/ -#define USB_ISTS_U2RESI BIT(18) -/* LPM L2 state enter detected.*/ -#define USB_ISTS_L2ENTI BIT(20) -/* LPM L2 state exit detected.*/ -#define USB_ISTS_L2EXTI BIT(21) -/* LPM L1 state enter detected.*/ -#define USB_ISTS_L1ENTI BIT(24) -/* LPM L1 state exit detected.*/ -#define USB_ISTS_L1EXTI BIT(25) -/* USB configuration reset detected.*/ -#define USB_ISTS_CFGRESI BIT(26) -/* Start of the USB warm reset detected.*/ -#define USB_ISTS_UWRESSI BIT(28) -/* End of the USB warm reset detected.*/ -#define USB_ISTS_UWRESEI BIT(29) +#if IS_ENABLED(CONFIG_USB_CDNS_MISC) +#include "cdns_misc.h" +#endif -/* USB_SEL - bitmasks */ -#define EP_SEL_EPNO_MASK GENMASK(3, 0) -/* Endpoint number. */ -#define EP_SEL_EPNO(p) ((p) & EP_SEL_EPNO_MASK) -/* Endpoint direction bit - 0 - OUT, 1 - IN. */ -#define EP_SEL_DIR BIT(7) +#include +#include -#define select_ep_in(nr) (EP_SEL_EPNO(p) | EP_SEL_DIR) -#define select_ep_out (EP_SEL_EPNO(p)) +#define gadget_to_usb_ss(g) \ + (container_of(g, struct usb_ss_dev, gadget)) -/* EP_TRADDR - bitmasks */ -/* Transfer Ring address. */ -#define EP_TRADDR_TRADDR(p) ((p)) +#define to_usb_ss_ep(ep) \ + (container_of(ep, struct usb_ss_endpoint, endpoint)) -/* EP_CFG - bitmasks */ -/* Endpoint enable */ -#define EP_CFG_ENABLE BIT(0) -/* - * Endpoint type. - * 1 - isochronous - * 2 - bulk - * 3 - interrupt - */ -#define EP_CFG_EPTYPE_MASK GENMASK(2, 1) -#define EP_CFG_EPTYPE(p) (((p) << 1) & EP_CFG_EPTYPE_MASK) -/* Stream support enable (only in SS mode). */ -#define EP_CFG_STREAM_EN BIT(3) -/* TDL check (only in SS mode for BULK EP). */ -#define EP_CFG_TDL_CHK BIT(4) -/* SID check (only in SS mode for BULK OUT EP). */ -#define EP_CFG_SID_CHK BIT(5) -/* DMA transfer endianness. */ -#define EP_CFG_EPENDIAN BIT(7) -/* Max burst size (used only in SS mode). */ -#define EP_CFG_MAXBURST_MASK GENMASK(11, 8) -#define EP_CFG_MAXBURST(p) (((p) << 8) & EP_CFG_MAXBURST_MASK) -/* ISO max burst. */ -#define EP_CFG_MULT_MASK GENMASK(15, 14) -#define EP_CFG_MULT(p) (((p) << 14) & EP_CFG_MULT_MASK) -/* ISO max burst. */ -#define EP_CFG_MAXPKTSIZE_MASK GENMASK(26, 16) -#define EP_CFG_MAXPKTSIZE(p) (((p) << 16) & EP_CFG_MAXPKTSIZE_MASK) -/* Max number of buffered packets. */ -#define EP_CFG_BUFFERING_MASK GENMASK(31, 27) -#define EP_CFG_BUFFERING(p) (((p) << 27) & EP_CFG_BUFFERING_MASK) +#define ep_to_usb_ss_ep(ep) \ + (container_of(ep, struct usb_ss_endpoint, endpoint)) -/* EP_CMD - bitmasks */ -/* Endpoint reset. */ -#define EP_CMD_EPRST BIT(0) -/* Endpoint STALL set. */ -#define EP_CMD_SSTALL BIT(1) -/* Endpoint STALL clear. */ -#define EP_CMD_CSTALL BIT(2) -/* Send ERDY TP. */ -#define EP_CMD_ERDY BIT(3) -/* Request complete. */ -#define EP_CMD_REQ_CMPL BIT(5) -/* Transfer descriptor ready. */ -#define EP_CMD_DRDY BIT(6) -/* Data flush. */ -#define EP_CMD_DFLUSH BIT(7) -/* - * Transfer Descriptor Length write (used only for Bulk Stream capable - * endpoints in SS mode). - * Bit Removed from DEV_VER_V3 controller version. - */ -#define EP_CMD_STDL BIT(8) -/* - * Transfer Descriptor Length (used only in SS mode for bulk endpoints). - * Bits Removed from DEV_VER_V3 controller version. - */ -#define EP_CMD_TDL_MASK GENMASK(15, 9) -#define EP_CMD_TDL_SET(p) (((p) << 9) & EP_CMD_TDL_MASK) -#define EP_CMD_TDL_GET(p) (((p) & EP_CMD_TDL_MASK) >> 9) - -/* ERDY Stream ID value (used in SS mode). */ -#define EP_CMD_ERDY_SID_MASK GENMASK(31, 16) -#define EP_CMD_ERDY_SID(p) (((p) << 16) & EP_CMD_ERDY_SID_MASK) +/*-------------------------------------------------------------------------*/ +/* TRB macros */ -/* EP_STS - bitmasks */ -/* Setup transfer complete. */ -#define EP_STS_SETUP BIT(0) -/* Endpoint STALL status. */ -#define EP_STS_STALL(p) ((p) & BIT(1)) -/* Interrupt On Complete. */ -#define EP_STS_IOC BIT(2) -/* Interrupt on Short Packet. */ -#define EP_STS_ISP BIT(3) -/* Transfer descriptor missing. */ -#define EP_STS_DESCMIS BIT(4) -/* Stream Rejected (used only in SS mode) */ -#define EP_STS_STREAMR BIT(5) -/* EXIT from MOVE DATA State (used only for stream transfers in SS mode). */ -#define EP_STS_MD_EXIT BIT(6) -/* TRB error. */ -#define EP_STS_TRBERR BIT(7) -/* Not ready (used only in SS mode). */ -#define EP_STS_NRDY BIT(8) -/* DMA busy bit. */ -#define EP_STS_DBUSY BIT(9) -/* Endpoint Buffer Empty */ -#define EP_STS_BUFFEMPTY(p) ((p) & BIT(10)) -/* Current Cycle Status */ -#define EP_STS_CCS(p) ((p) & BIT(11)) -/* Prime (used only in SS mode. */ -#define EP_STS_PRIME BIT(12) -/* Stream error (used only in SS mode). */ -#define EP_STS_SIDERR BIT(13) -/* OUT size mismatch. */ -#define EP_STS_OUTSMM BIT(14) -/* ISO transmission error. */ -#define EP_STS_ISOERR BIT(15) -/* Host Packet Pending (only for SS mode). */ -#define EP_STS_HOSTPP(p) ((p) & BIT(16)) -/* Stream Protocol State Machine State (only for Bulk stream endpoints). */ -#define EP_STS_SPSMST_MASK GENMASK(18, 17) -#define EP_STS_SPSMST_DISABLED(p) (((p) & EP_STS_SPSMST_MASK) >> 17) -#define EP_STS_SPSMST_IDLE(p) (((p) & EP_STS_SPSMST_MASK) >> 17) -#define EP_STS_SPSMST_START_STREAM(p) (((p) & EP_STS_SPSMST_MASK) >> 17) -#define EP_STS_SPSMST_MOVE_DATA(p) (((p) & EP_STS_SPSMST_MASK) >> 17) -/* Interrupt On Transfer complete. */ -#define EP_STS_IOT BIT(19) -/* OUT queue endpoint number. */ -#define EP_STS_OUTQ_NO_MASK GENMASK(27, 24) -#define EP_STS_OUTQ_NO(p) (((p) & EP_STS_OUTQ_NO_MASK) >> 24) -/* OUT queue valid flag. */ -#define EP_STS_OUTQ_VAL_MASK BIT(28) -#define EP_STS_OUTQ_VAL(p) ((p) & EP_STS_OUTQ_VAL_MASK) -/* SETUP WAIT. */ -#define EP_STS_STPWAIT BIT(31) +/* Common TRB fields */ +#define TRB_SET_CYCLE_BIT 1uL +#define TRB_SET_CHAIN_BIT 0x10 -/* EP_STS_SID - bitmasks */ -/* Stream ID (used only in SS mode). */ -#define EP_STS_SID_MASK GENMASK(15, 0) -#define EP_STS_SID(p) ((p) & EP_STS_SID_MASK) +/* offset 0 */ +#define TRB_DATA_BUFFER_POINTER_MASK 0xFFFFFFFF +#define TRB_SET_DATA_BUFFER_POINTER(p) ((p) & TRB_DATA_BUFFER_POINTER_MASK) -/* EP_STS_EN - bitmasks */ -/* SETUP interrupt enable. */ -#define EP_STS_EN_SETUPEN BIT(0) -/* OUT transfer missing descriptor enable. */ -#define EP_STS_EN_DESCMISEN BIT(4) -/* Stream Rejected enable. */ -#define EP_STS_EN_STREAMREN BIT(5) -/* Move Data Exit enable.*/ -#define EP_STS_EN_MD_EXITEN BIT(6) -/* TRB enable. */ -#define EP_STS_EN_TRBERREN BIT(7) -/* NRDY enable. */ -#define EP_STS_EN_NRDYEN BIT(8) -/* Prime enable. */ -#define EP_STS_EN_PRIMEEEN BIT(12) -/* Stream error enable. */ -#define EP_STS_EN_SIDERREN BIT(13) -/* OUT size mismatch enable. */ -#define EP_STS_EN_OUTSMMEN BIT(14) -/* ISO transmission error enable. */ -#define EP_STS_EN_ISOERREN BIT(15) -/* Interrupt on Transmission complete enable. */ -#define EP_STS_EN_IOTEN BIT(19) -/* Setup Wait interrupt enable. */ -#define EP_STS_EN_STPWAITEN BIT(31) +/* offset 4 */ +#define TRB_TRANSFER_LENGTH_MASK 0x1FFFF +#define TRB_SET_TRANSFER_LENGTH(l) ((l) & TRB_TRANSFER_LENGTH_MASK) -/* DRBL- bitmasks */ -#define DB_VALUE_BY_INDEX(index) (1 << (index)) -#define DB_VALUE_EP0_OUT BIT(0) -#define DB_VALUE_EP0_IN BIT(16) +#define TRB_BURST_LENGTH_MASK 0xFF +#define TRB_SET_BURST_LENGTH(l) (((l) & TRB_BURST_LENGTH_MASK) << 24) -/* EP_IEN - bitmasks */ -#define EP_IEN(index) (1 << (index)) -#define EP_IEN_EP_OUT0 BIT(0) -#define EP_IEN_EP_IN0 BIT(16) +/* offset 8 */ +#define TRB_SET_INT_ON_SHORT_PACKET 0x04 +#define TRB_SET_FIFO_MODE 0x08 +#define TRB_SET_INT_ON_COMPLETION 0x20 -/* EP_ISTS - bitmasks */ -#define EP_ISTS(index) (1 << (index)) -#define EP_ISTS_EP_OUT0 BIT(0) -#define EP_ISTS_EP_IN0 BIT(16) +#define TRB_TYPE_NORMAL 0x400 -/* USB_PWR- bitmasks */ -/*Power Shut Off capability enable*/ -#define PUSB_PWR_PSO_EN BIT(0) -/*Power Shut Off capability disable*/ -#define PUSB_PWR_PSO_DS BIT(1) -/* - * Enables turning-off Reference Clock. - * This bit is optional and implemented only when support for OTG is - * implemented (indicated by OTG_READY bit set to '1'). - */ -#define PUSB_PWR_STB_CLK_SWITCH_EN BIT(8) -/* - * Status bit indicating that operation required by STB_CLK_SWITCH_EN write - * is completed - */ -#define PUSB_PWR_STB_CLK_SWITCH_DONE BIT(9) -/* This bit informs if Fast Registers Access is enabled. */ -#define PUSB_PWR_FST_REG_ACCESS_STAT BIT(30) -/* Fast Registers Access Enable. */ -#define PUSB_PWR_FST_REG_ACCESS BIT(31) +#define TRB_STREAM_ID_MASK 0xFFFF +#define TRB_SET_STREAM_ID(sid) (((sid) & TRB_STREAM_ID_MASK) << 16) -/* USB_CONF2- bitmasks */ -/* - * Writing 1 disables TDL calculation basing on TRB feature in controller - * for DMULT mode. - * Bit supported only for DEV_VER_V2 version. - */ -#define USB_CONF2_DIS_TDL_TRB BIT(1) -/* - * Writing 1 enables TDL calculation basing on TRB feature in controller - * for DMULT mode. - * Bit supported only for DEV_VER_V2 version. - */ -#define USB_CONF2_EN_TDL_TRB BIT(2) +/*-------------------------------------------------------------------------*/ +/* Driver numeric constants */ -/* USB_CAP1- bitmasks */ -/* - * SFR Interface type - * These field reflects type of SFR interface implemented: - * 0x0 - OCP - * 0x1 - AHB, - * 0x2 - PLB - * 0x3 - AXI - * 0x4-0xF - reserved - */ -#define USB_CAP1_SFR_TYPE_MASK GENMASK(3, 0) -#define DEV_SFR_TYPE_OCP(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x0) -#define DEV_SFR_TYPE_AHB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x1) -#define DEV_SFR_TYPE_PLB(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x2) -#define DEV_SFR_TYPE_AXI(p) (((p) & USB_CAP1_SFR_TYPE_MASK) == 0x3) -/* - * SFR Interface width - * These field reflects width of SFR interface implemented: - * 0x0 - 8 bit interface, - * 0x1 - 16 bit interface, - * 0x2 - 32 bit interface - * 0x3 - 64 bit interface - * 0x4-0xF - reserved - */ -#define USB_CAP1_SFR_WIDTH_MASK GENMASK(7, 4) -#define DEV_SFR_WIDTH_8(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x0 << 4)) -#define DEV_SFR_WIDTH_16(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x1 << 4)) -#define DEV_SFR_WIDTH_32(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x2 << 4)) -#define DEV_SFR_WIDTH_64(p) (((p) & USB_CAP1_SFR_WIDTH_MASK) == (0x3 << 4)) -/* - * DMA Interface type - * These field reflects type of DMA interface implemented: - * 0x0 - OCP - * 0x1 - AHB, - * 0x2 - PLB - * 0x3 - AXI - * 0x4-0xF - reserved - */ -#define USB_CAP1_DMA_TYPE_MASK GENMASK(11, 8) -#define DEV_DMA_TYPE_OCP(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x0 << 8)) -#define DEV_DMA_TYPE_AHB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x1 << 8)) -#define DEV_DMA_TYPE_PLB(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x2 << 8)) -#define DEV_DMA_TYPE_AXI(p) (((p) & USB_CAP1_DMA_TYPE_MASK) == (0x3 << 8)) -/* - * DMA Interface width - * These field reflects width of DMA interface implemented: - * 0x0 - reserved, - * 0x1 - reserved, - * 0x2 - 32 bit interface - * 0x3 - 64 bit interface - * 0x4-0xF - reserved - */ -#define USB_CAP1_DMA_WIDTH_MASK GENMASK(15, 12) -#define DEV_DMA_WIDTH_32(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x2 << 12)) -#define DEV_DMA_WIDTH_64(p) (((p) & USB_CAP1_DMA_WIDTH_MASK) == (0x3 << 12)) -/* - * USB3 PHY Interface type - * These field reflects type of USB3 PHY interface implemented: - * 0x0 - USB PIPE, - * 0x1 - RMMI, - * 0x2-0xF - reserved - */ -#define USB_CAP1_U3PHY_TYPE_MASK GENMASK(19, 16) -#define DEV_U3PHY_PIPE(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x0 << 16)) -#define DEV_U3PHY_RMMI(p) (((p) & USB_CAP1_U3PHY_TYPE_MASK) == (0x1 << 16)) -/* - * USB3 PHY Interface width - * These field reflects width of USB3 PHY interface implemented: - * 0x0 - 8 bit PIPE interface, - * 0x1 - 16 bit PIPE interface, - * 0x2 - 32 bit PIPE interface, - * 0x3 - 64 bit PIPE interface - * 0x4-0xF - reserved - * Note: When SSIC interface is implemented this field shows the width of - * internal PIPE interface. The RMMI interface is always 20bit wide. - */ -#define USB_CAP1_U3PHY_WIDTH_MASK GENMASK(23, 20) -#define DEV_U3PHY_WIDTH_8(p) \ - (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x0 << 20)) -#define DEV_U3PHY_WIDTH_16(p) \ - (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x1 << 16)) -#define DEV_U3PHY_WIDTH_32(p) \ - (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x2 << 20)) -#define DEV_U3PHY_WIDTH_64(p) \ - (((p) & USB_CAP1_U3PHY_WIDTH_MASK) == (0x3 << 16)) +#define DEVICE_ADDRESS_MAX 127 -/* - * USB2 PHY Interface enable - * These field informs if USB2 PHY interface is implemented: - * 0x0 - interface NOT implemented, - * 0x1 - interface implemented - */ -#define USB_CAP1_U2PHY_EN(p) ((p) & BIT(24)) -/* - * USB2 PHY Interface type - * These field reflects type of USB2 PHY interface implemented: - * 0x0 - UTMI, - * 0x1 - ULPI - */ -#define DEV_U2PHY_ULPI(p) ((p) & BIT(25)) -/* - * USB2 PHY Interface width - * These field reflects width of USB2 PHY interface implemented: - * 0x0 - 8 bit interface, - * 0x1 - 16 bit interface, - * Note: The ULPI interface is always 8bit wide. - */ -#define DEV_U2PHY_WIDTH_16(p) ((p) & BIT(26)) -/* - * OTG Ready - * 0x0 - pure device mode - * 0x1 - some features and ports for CDNS USB OTG controller are implemented. - */ -#define USB_CAP1_OTG_READY(p) ((p) & BIT(27)) +/* Endpoint init values */ +#define ENDPOINT_MAX_PACKET_LIMIT 1024 -/* - * When set, indicates that controller supports automatic internal TDL - * calculation basing on the size provided in TRB (TRB[22:17]) for DMULT mode - * Supported only for DEV_VER_V2 controller version. - */ -#define USB_CAP1_TDL_FROM_TRB(p) ((p) & BIT(28)) +#define ENDPOINT_MAX_STREAMS 15 -/* USB_CAP2- bitmasks */ -/* - * The actual size of the connected On-chip RAM memory in kB: - * - 0 means 256 kB (max supported mem size) - * - value other than 0 reflects the mem size in kB - */ -#define USB_CAP2_ACTUAL_MEM_SIZE(p) ((p) & GENMASK(7, 0)) -/* - * Max supported mem size - * These field reflects width of on-chip RAM address bus width, - * which determines max supported mem size: - * 0x0-0x7 - reserved, - * 0x8 - support for 4kB mem, - * 0x9 - support for 8kB mem, - * 0xA - support for 16kB mem, - * 0xB - support for 32kB mem, - * 0xC - support for 64kB mem, - * 0xD - support for 128kB mem, - * 0xE - support for 256kB mem, - * 0xF - reserved - */ -#define USB_CAP2_MAX_MEM_SIZE(p) ((p) & GENMASK(11, 8)) +#define ENDPOINT0_MAX_PACKET_LIMIT 512 -/* USB_CAP3- bitmasks */ -#define EP_IS_IMPLEMENTED(reg, index) ((reg) & (1 << (index))) +/* All endpoints except EP0 */ +#define USB_SS_ENDPOINTS_MAX_COUNT 30 -/* USB_CAP4- bitmasks */ -#define EP_SUPPORT_ISO(reg, index) ((reg) & (1 << (index))) +#define USB_SS_TRBS_NUM 32 -/* USB_CAP5- bitmasks */ -#define EP_SUPPORT_STREAM(reg, index) ((reg) & (1 << (index))) +/* Standby mode */ +#define STB_CLK_SWITCH_DONE_MASK 0x200 +#define STB_CLK_SWITCH_EN_MASK 0x100 +#define STB_CLK_SWITCH_EN_SHIFT 8 -/* USB_CAP6- bitmasks */ -/* The USBSS-DEV Controller Internal build number. */ -#define GET_DEV_BASE_VERSION(p) ((p) & GENMASK(23, 0)) -/* The USBSS-DEV Controller version number. */ -#define GET_DEV_CUSTOM_VERSION(p) ((p) & GENMASK(31, 24)) +#define ENDPOINT_MAX_PACKET_SIZE_0 0 +#define ENDPOINT_MAX_PACKET_SIZE_8 8 +#define ENDPOINT_MAX_PACKET_SIZE_64 64 +#define ENDPOINT_MAX_PACKET_SIZE_512 512 +#define ENDPOINT_MAX_PACKET_SIZE_1023 1023 +#define ENDPOINT_MAX_PACKET_SIZE_1024 1024 -#define DEV_VER_NXP_V1 0x00024502 -#define DEV_VER_TI_V1 0x00024509 -#define DEV_VER_V2 0x0002450C -#define DEV_VER_V3 0x0002450d +#define SS_LINK_STATE_U3 3 +#define FSHS_LPM_STATE_L2 2 -/* DBG_LINK1- bitmasks */ -/* - * LFPS_MIN_DET_U1_EXIT value This parameter configures the minimum - * time required for decoding the received LFPS as an LFPS.U1_Exit. - */ -#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT(p) ((p) & GENMASK(7, 0)) -/* - * LFPS_MIN_GEN_U1_EXIT value This parameter configures the minimum time for - * phytxelecidle deassertion when LFPS.U1_Exit - */ -#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_MASK GENMASK(15, 8) -#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT(p) (((p) << 8) & GENMASK(15, 8)) -/* - * RXDET_BREAK_DIS value This parameter configures terminating the Far-end - * Receiver termination detection sequence: - * 0: it is possible that USBSS_DEV will terminate Farend receiver - * termination detection sequence - * 1: USBSS_DEV will not terminate Far-end receiver termination - * detection sequence - */ -#define DBG_LINK1_RXDET_BREAK_DIS BIT(16) -/* LFPS_GEN_PING value This parameter configures the LFPS.Ping generation */ -#define DBG_LINK1_LFPS_GEN_PING(p) (((p) << 17) & GENMASK(21, 17)) -/* - * Set the LFPS_MIN_DET_U1_EXIT value Writing '1' to this bit writes the - * LFPS_MIN_DET_U1_EXIT field value to the device. This bit is automatically - * cleared. Writing '0' has no effect - */ -#define DBG_LINK1_LFPS_MIN_DET_U1_EXIT_SET BIT(24) -/* - * Set the LFPS_MIN_GEN_U1_EXIT value. Writing '1' to this bit writes the - * LFPS_MIN_GEN_U1_EXIT field value to the device. This bit is automatically - * cleared. Writing '0' has no effect - */ -#define DBG_LINK1_LFPS_MIN_GEN_U1_EXIT_SET BIT(25) -/* - * Set the RXDET_BREAK_DIS value Writing '1' to this bit writes - * the RXDET_BREAK_DIS field value to the device. This bit is automatically - * cleared. Writing '0' has no effect - */ -#define DBG_LINK1_RXDET_BREAK_DIS_SET BIT(26) -/* - * Set the LFPS_GEN_PING_SET value Writing '1' to this bit writes - * the LFPS_GEN_PING field value to the device. This bit is automatically - * cleared. Writing '0' has no effect." - */ -#define DBG_LINK1_LFPS_GEN_PING_SET BIT(27) +#define ADDR_MODULO_8 8 -/* DMA_AXI_CTRL- bitmasks */ -/* The mawprot pin configuration. */ -#define DMA_AXI_CTRL_MARPROT(p) ((p) & GENMASK(2, 0)) -/* The marprot pin configuration. */ -#define DMA_AXI_CTRL_MAWPROT(p) (((p) & GENMASK(2, 0)) << 16) -#define DMA_AXI_CTRL_NON_SECURE 0x02 +#define INTERRUPT_MASK 0xFFFFFFFF -#define gadget_to_cdns3_device(g) (container_of(g, struct cdns3_device, gadget)) +#define ACTUAL_TRANSFERRED_BYTES_MASK 0x1FFFF -#define ep_to_cdns3_ep(ep) (container_of(ep, struct cdns3_endpoint, endpoint)) +#define ENDPOINT_DIR_MASK 0x80 /*-------------------------------------------------------------------------*/ -/* - * USBSS-DEV DMA interface. - */ -#define TRBS_PER_SEGMENT 40 -#define ISO_MAX_INTERVAL 10 - -#if TRBS_PER_SEGMENT < 2 -#error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2." -#endif - -/* - *Only for ISOC endpoints - maximum number of TRBs is calculated as - * pow(2, bInterval-1) * number of usb requests. It is limitation made by - * driver to save memory. Controller must prepare TRB for each ITP even - * if bInterval > 1. It's the reason why driver needs so many TRBs for - * isochronous endpoints. +/** + * IS_REG_REQUIRING_ACTIVE_REF_CLOCK - Macro checks if desired + * register requires active clock, it involves such registers as: + * EP_CFG, EP_TR_ADDR, EP_CMD, EP_SEL, USB_CONF + * @usb_ss: extended gadget object + * @reg: register address */ -#define TRBS_PER_ISOC_SEGMENT (ISO_MAX_INTERVAL * 8) +#define IS_REG_REQUIRING_ACTIVE_REF_CLOCK(usb_ss, reg) (!(reg) || \ + ((reg) >= &(usb_ss)->regs->ep_sel && (reg) <= &(usb_ss)->regs->ep_cmd)) -#define GET_TRBS_PER_SEGMENT(ep_type) ((ep_type) == USB_ENDPOINT_XFER_ISOC ? \ - TRBS_PER_ISOC_SEGMENT : TRBS_PER_SEGMENT) /** - * struct cdns3_trb - represent Transfer Descriptor block. - * @buffer: pointer to buffer data - * @length: length of data - * @control: control flags. + * CAST_EP_REG_POS_TO_INDEX - Macro converts bit position of ep_ists register to + * index of endpoint object in usb_ss_dev.eps[] container + * @i: bit position of endpoint for which endpoint object is required * - * This structure describes transfer block serviced by DMA module. + * Remember that endpoint container doesn't contain default endpoint */ -struct cdns3_trb { - __le32 buffer; - __le32 length; - __le32 control; -}; +#define CAST_EP_REG_POS_TO_INDEX(i) (((i) / 16) + ((((i) % 16) - 2) * 2)) -#define TRB_SIZE (sizeof(struct cdns3_trb)) -#define TRB_RING_SIZE (TRB_SIZE * TRBS_PER_SEGMENT) -#define TRB_ISO_RING_SIZE (TRB_SIZE * TRBS_PER_ISOC_SEGMENT) -#define TRB_CTRL_RING_SIZE (TRB_SIZE * 2) - -/* TRB bit mask */ -#define TRB_TYPE_BITMASK GENMASK(15, 10) -#define TRB_TYPE(p) ((p) << 10) -#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) - -/* TRB type IDs */ -/* bulk, interrupt, isoc , and control data stage */ -#define TRB_NORMAL 1 -/* TRB for linking ring segments */ -#define TRB_LINK 6 - -/* Cycle bit - indicates TRB ownership by driver or hw*/ -#define TRB_CYCLE BIT(0) -/* - * When set to '1', the device will toggle its interpretation of the Cycle bit +/** + * CAST_EP_ADDR_TO_INDEX - Macro converts endpoint address to + * index of endpoint object in usb_ss_dev.eps[] container + * @ep_addr: endpoint address for which endpoint object is required + * + * Remember that endpoint container doesn't contain default endpoint */ -#define TRB_TOGGLE BIT(1) +#define CAST_EP_ADDR_TO_INDEX(ep_addr) \ + ((((ep_addr) & 0x7F) - 1) + (((ep_addr) & 0x80) ? 1 : 0)) -/* - * Short Packet (SP). OUT EPs at DMULT=1 only. Indicates if the TRB was - * processed while USB short packet was received. No more buffers defined by - * the TD will be used. DMA will automatically advance to next TD. - * - Shall be set to 0 by Software when putting TRB on the Transfer Ring - * - Shall be set to 1 by Controller when Short Packet condition for this TRB - * is detected independent if ISP is set or not. +/** + * CAST_EP_ADDR_TO_BIT_POS - Macro converts endpoint address to + * bit position in ep_ists register + * @ep_addr: endpoint address for which bit position is required + * + * Remember that endpoint container doesn't contain default endpoint */ -#define TRB_SP BIT(1) - -/* Interrupt on short packet*/ -#define TRB_ISP BIT(2) -/*Setting this bit enables FIFO DMA operation mode*/ -#define TRB_FIFO_MODE BIT(3) -/* Set PCIe no snoop attribute */ -#define TRB_CHAIN BIT(4) -/* Interrupt on completion */ -#define TRB_IOC BIT(5) - -/* stream ID bitmasks. */ -#define TRB_STREAM_ID_BITMASK GENMASK(31, 16) -#define TRB_STREAM_ID(p) ((p) << 16) -#define TRB_FIELD_TO_STREAMID(p) (((p) & TRB_STREAM_ID_BITMASK) >> 16) - -/* Size of TD expressed in USB packets for HS/FS mode. */ -#define TRB_TDL_HS_SIZE(p) (((p) << 16) & GENMASK(31, 16)) -#define TRB_TDL_HS_SIZE_GET(p) (((p) & GENMASK(31, 16)) >> 16) - -/* transfer_len bitmasks. */ -#define TRB_LEN(p) ((p) & GENMASK(16, 0)) - -/* Size of TD expressed in USB packets for SS mode. */ -#define TRB_TDL_SS_SIZE(p) (((p) << 17) & GENMASK(23, 17)) -#define TRB_TDL_SS_SIZE_GET(p) (((p) & GENMASK(23, 17)) >> 17) - -/* transfer_len bitmasks - bits 31:24 */ -#define TRB_BURST_LEN(p) (((p) << 24) & GENMASK(31, 24)) -#define TRB_BURST_LEN_GET(p) (((p) & GENMASK(31, 24)) >> 24) - -/* Data buffer pointer bitmasks*/ -#define TRB_BUFFER(p) ((p) & GENMASK(31, 0)) - -/*-------------------------------------------------------------------------*/ -/* Driver numeric constants */ - -/* Such declaration should be added to ch9.h */ -#define USB_DEVICE_MAX_ADDRESS 127 - -/* Endpoint init values */ -#define CDNS3_EP_MAX_PACKET_LIMIT 1024 -#define CDNS3_EP_MAX_STREAMS 15 -#define CDNS3_EP0_MAX_PACKET_LIMIT 512 +#define CAST_EP_ADDR_TO_BIT_POS(ep_addr) \ + (((u32)1 << ((ep_addr) & 0x7F)) << (((ep_addr) & 0x80) ? 16 : 0)) -/* All endpoints including EP0 */ -#define CDNS3_ENDPOINTS_MAX_COUNT 32 -#define CDNS3_EP_ZLP_BUF_SIZE 1024 +#define CAST_INDEX_TO_EP_ADDR(index) \ + (((index) / 2 + 1) | (((index) % 2) ? 0x80 : 0x00)) -#define CDNS3_EP_BUF_SIZE 2 /* KB */ -#define CDNS3_EP_ISO_HS_MULT 3 -#define CDNS3_EP_ISO_SS_BURST 3 -#define CDNS3_MAX_NUM_DESCMISS_BUF 32 -#define CDNS3_DESCMIS_BUF_SIZE 2048 /* Bytes */ -#define CDNS3_WA2_NUM_BUFFERS 128 /*-------------------------------------------------------------------------*/ /* Used structs */ -struct cdns3_device; - -/** - * struct cdns3_endpoint - extended device side representation of USB endpoint. - * @endpoint: usb endpoint - * @pending_req_list: list of requests queuing on transfer ring. - * @deferred_req_list: list of requests waiting for queuing on transfer ring. - * @wa2_descmiss_req_list: list of requests internally allocated by driver. - * @trb_pool: transfer ring - array of transaction buffers - * @trb_pool_dma: dma address of transfer ring - * @cdns3_dev: device associated with this endpoint - * @name: a human readable name e.g. ep1out - * @flags: specify the current state of endpoint - * @descmis_req: internal transfer object used for getting data from on-chip - * buffer. It can happen only if function driver doesn't send usb_request - * object on time. - * @dir: endpoint direction - * @num: endpoint number (1 - 15) - * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK - * @interval: interval between packets used for ISOC endpoint. - * @free_trbs: number of free TRBs in transfer ring - * @num_trbs: number of all TRBs in transfer ring - * @pcs: producer cycle state - * @ccs: consumer cycle state - * @enqueue: enqueue index in transfer ring - * @dequeue: dequeue index in transfer ring - * @trb_burst_size: number of burst used in trb. - */ -struct cdns3_endpoint { - struct usb_ep endpoint; - struct list_head pending_req_list; - struct list_head deferred_req_list; - struct list_head wa2_descmiss_req_list; - int wa2_counter; - - struct cdns3_trb *trb_pool; - dma_addr_t trb_pool_dma; - - struct cdns3_device *cdns3_dev; - char name[20]; - -#define EP_ENABLED BIT(0) -#define EP_STALLED BIT(1) -#define EP_STALL_PENDING BIT(2) -#define EP_WEDGE BIT(3) -#define EP_TRANSFER_STARTED BIT(4) -#define EP_UPDATE_EP_TRBADDR BIT(5) -#define EP_PENDING_REQUEST BIT(6) -#define EP_RING_FULL BIT(7) -#define EP_CLAIMED BIT(8) -#define EP_DEFERRED_DRDY BIT(9) -#define EP_QUIRK_ISO_OUT_EN BIT(10) -#define EP_QUIRK_END_TRANSFER BIT(11) -#define EP_QUIRK_EXTRA_BUF_DET BIT(12) -#define EP_QUIRK_EXTRA_BUF_EN BIT(13) - u32 flags; - - struct cdns3_request *descmis_req; - - u8 dir; - u8 num; - u8 type; - int interval; - - int free_trbs; - int num_trbs; - u8 pcs; - u8 ccs; - int enqueue; - int dequeue; - u8 trb_burst_size; - - unsigned int wa1_set:1; - struct cdns3_trb *wa1_trb; - unsigned int wa1_trb_index; - unsigned int wa1_cycle_bit:1; +struct usb_ss_trb { + u32 offset0; + u32 offset4; + u32 offset8; }; -/** - * struct cdns3_aligned_buf - represent aligned buffer used for DMA transfer - * @buf: aligned to 8 bytes data buffer. Buffer address used in - * TRB shall be aligned to 8. - * @dma: dma address - * @size: size of buffer - * @in_use: inform if this buffer is associated with usb_request - * @list: used to adding instance of this object to list - */ -struct cdns3_aligned_buf { - void *buf; - dma_addr_t dma; - u32 size; - int in_use:1; - struct list_head list; +struct usb_ss_dev; + +struct usb_ss_endpoint { + struct usb_ep endpoint; + struct list_head request_list; + struct list_head ep_match_pending_list; + + struct usb_ss_trb *trb_pool; + dma_addr_t trb_pool_dma; + + struct usb_ss_dev *usb_ss; + char name[20]; + int hw_pending_flag; + int stalled_flag; + int wedge_flag; + int hw_reset_flag; + void *cpu_addr; + dma_addr_t dma_addr; + u8 dir; + u8 num; + u8 type; + u8 address; + bool used; + bool enabled; + struct usb_ep_caps caps; }; -/** - * struct cdns3_request - extended device side representation of usb_request - * object . - * @request: generic usb_request object describing single I/O request. - * @priv_ep: extended representation of usb_ep object - * @trb: the first TRB association with this request - * @start_trb: number of the first TRB in transfer ring - * @end_trb: number of the last TRB in transfer ring - * @aligned_buf: object holds information about aligned buffer associated whit - * this endpoint - * @flags: flag specifying special usage of request - * @list: used by internally allocated request to add to wa2_descmiss_req_list. - */ -struct cdns3_request { - struct usb_request request; - struct cdns3_endpoint *priv_ep; - struct cdns3_trb *trb; - int start_trb; - int end_trb; - struct cdns3_aligned_buf *aligned_buf; -#define REQUEST_PENDING BIT(0) -#define REQUEST_INTERNAL BIT(1) -#define REQUEST_INTERNAL_CH BIT(2) -#define REQUEST_ZLP BIT(3) -#define REQUEST_UNALIGNED BIT(4) - u32 flags; - struct list_head list; +struct usb_ss_dev { + struct udevice dev; + struct usbss_dev_register_block_type __iomem *regs; + + struct usb_gadget gadget; + struct usb_gadget_driver *gadget_driver; + + dma_addr_t setup_dma; + dma_addr_t trb_ep0_dma; + u32 *trb_ep0; + u8 *setup; + + struct usb_ss_endpoint *eps[USB_SS_ENDPOINTS_MAX_COUNT]; + int ep_nums; + struct usb_request *actual_ep0_request; + int ep0_data_dir; + int hw_configured_flag; + int wake_up_flag; + u16 isoch_delay; + spinlock_t lock; /* protection lock */ + + unsigned is_connected:1; + unsigned in_standby_mode:1; + + u32 usb_ien; + u32 ep_ien; + int setup_pending; + struct udevice *sysdev; + bool start_gadget; /* The device mode is enabled */ + struct list_head ep_match_list; }; -#define to_cdns3_request(r) (container_of(r, struct cdns3_request, request)) - -/*Stages used during enumeration process.*/ -#define CDNS3_SETUP_STAGE 0x0 -#define CDNS3_DATA_STAGE 0x1 -#define CDNS3_STATUS_STAGE 0x2 - -/** - * struct cdns3_device - represent USB device. - * @dev: pointer to device structure associated whit this controller - * @sysdev: pointer to the DMA capable device - * @gadget: device side representation of the peripheral controller - * @gadget_driver: pointer to the gadget driver - * @dev_ver: device controller version. - * @lock: for synchronizing - * @regs: base address for device side registers - * @setup_buf: used while processing usb control requests - * @setup_dma: dma address for setup_buf - * @zlp_buf - zlp buffer - * @ep0_stage: ep0 stage during enumeration process. - * @ep0_data_dir: direction for control transfer - * @eps: array of pointers to all endpoints with exclusion ep0 - * @aligned_buf_list: list of aligned buffers internally allocated by driver - * @aligned_buf_wq: workqueue freeing no longer used aligned buf. - * @selected_ep: actually selected endpoint. It's used only to improve - * performance. - * @isoch_delay: value from Set Isoch Delay request. Only valid on SS/SSP. - * @u1_allowed: allow device transition to u1 state - * @u2_allowed: allow device transition to u2 state - * @is_selfpowered: device is self powered - * @setup_pending: setup packet is processing by gadget driver - * @hw_configured_flag: hardware endpoint configuration was set. - * @wake_up_flag: allow device to remote up the host - * @status_completion_no_call: indicate that driver is waiting for status s - * stage completion. It's used in deferred SET_CONFIGURATION request. - * @onchip_buffers: number of available on-chip buffers. - * @onchip_used_size: actual size of on-chip memory assigned to endpoints. - * @pending_status_wq: workqueue handling status stage for deferred requests. - * @pending_status_request: request for which status stage was deferred - */ -struct cdns3_device { - struct udevice *dev; - struct udevice *sysdev; - - struct usb_gadget gadget; - struct usb_gadget_driver *gadget_driver; - -#define CDNS_REVISION_V0 0x00024501 -#define CDNS_REVISION_V1 0x00024509 - u32 dev_ver; - - /* generic spin-lock for drivers */ - spinlock_t lock; - - struct cdns3_usb_regs __iomem *regs; - - struct usb_ctrlrequest *setup_buf; - dma_addr_t setup_dma; - void *zlp_buf; - - u8 ep0_stage; - int ep0_data_dir; - - struct cdns3_endpoint *eps[CDNS3_ENDPOINTS_MAX_COUNT]; - - struct list_head aligned_buf_list; - struct work_struct aligned_buf_wq; - - u32 selected_ep; - u16 isoch_delay; - - unsigned wait_for_setup:1; - unsigned u1_allowed:1; - unsigned u2_allowed:1; - unsigned is_selfpowered:1; - unsigned setup_pending:1; - int hw_configured_flag:1; - int wake_up_flag:1; - unsigned status_completion_no_call:1; - int out_mem_is_allocated; - - struct work_struct pending_status_wq; - struct usb_request *pending_status_request; - - /*in KB */ - u32 onchip_buffers; - u16 onchip_used_size; +struct cdns3_generic_peripheral { + struct cdns3 cdns3; + struct usb_ss_dev usb_ss_dev; + struct clk_bulk clks; + struct phy phy; }; -void cdns3_set_register_bit(void __iomem *ptr, u32 mask); -dma_addr_t cdns3_trb_virt_to_dma(struct cdns3_endpoint *priv_ep, - struct cdns3_trb *trb); -enum usb_device_speed cdns3_get_speed(struct cdns3_device *priv_dev); -void cdns3_pending_setup_status_handler(struct work_struct *work); -void cdns3_hw_reset_eps_config(struct cdns3_device *priv_dev); -void cdns3_set_hw_configuration(struct cdns3_device *priv_dev); -void cdns3_select_ep(struct cdns3_device *priv_dev, u32 ep); -void cdns3_allow_enable_l1(struct cdns3_device *priv_dev, int enable); -struct usb_request *cdns3_next_request(struct list_head *list); -int cdns3_ep_run_transfer(struct cdns3_endpoint *priv_ep, - struct usb_request *request); -void cdns3_rearm_transfer(struct cdns3_endpoint *priv_ep, u8 rearm); -int cdns3_allocate_trb_pool(struct cdns3_endpoint *priv_ep); -u8 cdns3_ep_addr_to_index(u8 ep_addr); -int cdns3_gadget_ep_set_wedge(struct usb_ep *ep); -int cdns3_gadget_ep_set_halt(struct usb_ep *ep, int value); -void __cdns3_gadget_ep_set_halt(struct cdns3_endpoint *priv_ep); -int __cdns3_gadget_ep_clear_halt(struct cdns3_endpoint *priv_ep); -struct usb_request *cdns3_gadget_ep_alloc_request(struct usb_ep *ep, - gfp_t gfp_flags); -void cdns3_gadget_ep_free_request(struct usb_ep *ep, - struct usb_request *request); -int cdns3_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request); -void cdns3_gadget_giveback(struct cdns3_endpoint *priv_ep, - struct cdns3_request *priv_req, - int status); - -int cdns3_init_ep0(struct cdns3_device *priv_dev, - struct cdns3_endpoint *priv_ep); -void cdns3_ep0_config(struct cdns3_device *priv_dev); -void cdns3_ep_config(struct cdns3_endpoint *priv_ep); -void cdns3_check_ep0_interrupt_proceed(struct cdns3_device *priv_dev, int dir); -int __cdns3_gadget_wakeup(struct cdns3_device *priv_dev); +#define OTG_STS_SELECTOR 0xF000 /* OTG status selector */ -#endif /* __LINUX_CDNS3_GADGET */ +#endif /* __DRIVERS_CDNS3_GADGET */ diff --git a/drivers/usb/cdns3/host-export.h b/drivers/usb/cdns3/host-export.h deleted file mode 100644 index b498a170b7e..00000000000 --- a/drivers/usb/cdns3/host-export.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Cadence USBSS DRD Driver - Host Export APIs - * - * Copyright (C) 2017-2018 NXP - * - * Authors: Peter Chen - */ -#ifndef __LINUX_CDNS3_HOST_EXPORT -#define __LINUX_CDNS3_HOST_EXPORT - -#ifdef CONFIG_USB_CDNS3_HOST - -int cdns3_host_init(struct cdns3 *cdns); -void cdns3_host_exit(struct cdns3 *cdns); - -#else - -static inline int cdns3_host_init(struct cdns3 *cdns) -{ - return -ENXIO; -} - -static inline void cdns3_host_exit(struct cdns3 *cdns) { } - -#endif /* CONFIG_USB_CDNS3_HOST */ - -#endif /* __LINUX_CDNS3_HOST_EXPORT */ diff --git a/drivers/usb/cdns3/host.c b/drivers/usb/cdns3/host.c deleted file mode 100644 index b44e7df1131..00000000000 --- a/drivers/usb/cdns3/host.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Cadence USBSS DRD Driver - host side - * - * Copyright (C) 2018-2019 Cadence Design Systems. - * Copyright (C) 2017-2018 NXP - * - * Authors: Peter Chen - * Pawel Laszczak - */ -#include -#include -#include -#include -#include - -#include "core.h" -#include "drd.h" - -static int __cdns3_host_init(struct cdns3 *cdns) -{ - struct xhci_hcor *hcor; - struct xhci_hccr *hccr; - - cdns3_drd_switch_host(cdns, 1); - - hccr = (struct xhci_hccr *)cdns->xhci_regs; - hcor = (struct xhci_hcor *)(cdns->xhci_regs + - HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); - - return xhci_register(cdns->dev, hccr, hcor); -} - -static void cdns3_host_exit(struct cdns3 *cdns) -{ - xhci_deregister(cdns->dev); - cdns3_drd_switch_host(cdns, 0); -} - -int cdns3_host_init(struct cdns3 *cdns) -{ - struct cdns3_role_driver *rdrv; - - rdrv = devm_kzalloc(cdns->dev, sizeof(*rdrv), GFP_KERNEL); - if (!rdrv) - return -ENOMEM; - - rdrv->start = __cdns3_host_init; - rdrv->stop = cdns3_host_exit; - rdrv->state = CDNS3_ROLE_STATE_INACTIVE; - rdrv->name = "host"; - - cdns->roles[USB_ROLE_HOST] = rdrv; - - return 0; -} diff --git a/drivers/usb/cdns3/io.h b/drivers/usb/cdns3/io.h new file mode 100644 index 00000000000..6bc7cfe9782 --- /dev/null +++ b/drivers/usb/cdns3/io.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Cadence Design Systems - https://www.cadence.com/ + * Copyright 2019 NXP + */ + +#ifndef __DRIVERS_USB_CDNS_IO_H +#define __DRIVERS_USB_CDNS_IO_H + +#include + +static inline u32 cdns_readl(u32 __iomem *reg) +{ + return readl(reg); +} + +static inline void cdns_writel(u32 __iomem *reg, u32 value) +{ + writel(value, reg); +} + +static inline void cdns_flush_cache(uintptr_t addr, int length) +{ + flush_dcache_range(addr, addr + length); +} + +#endif /* __DRIVERS_USB_CDNS_IO_H */ diff --git a/drivers/usb/cdns3/trace.c b/drivers/usb/cdns3/trace.c deleted file mode 100644 index 459fa72d9c7..00000000000 --- a/drivers/usb/cdns3/trace.c +++ /dev/null @@ -1,11 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * USBSS device controller driver Trace Support - * - * Copyright (C) 2018-2019 Cadence. - * - * Author: Pawel Laszczak - */ - -#define CREATE_TRACE_POINTS -#include "trace.h" diff --git a/drivers/usb/cdns3/trace.h b/drivers/usb/cdns3/trace.h deleted file mode 100644 index e86c02ae9b3..00000000000 --- a/drivers/usb/cdns3/trace.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#define trace_cdns3_prepare_trb(a, b) -#define trace_cdns3_doorbell_ep0(a, b) -#define trace_cdns3_ctrl_req(a) -#define trace_cdns3_complete_trb(a, b) -#define trace_cdns3_ep0_irq(a, b) -#define trace_cdns3_gadget_giveback(a) -#define trace_cdns3_free_aligned_request(a) -#define trace_cdns3_prepare_aligned_request(a) -#define trace_cdns3_ring(a) -#define trace_cdns3_doorbell_epx(a, b) -#define trace_cdns3_request_handled(a, b, c) -#define trace_cdns3_epx_irq(a, b) -#define trace_cdns3_usb_irq(a, b) -#define trace_cdns3_alloc_request(a) -#define trace_cdns3_free_request(a) -#define trace_cdns3_gadget_ep_enable(a) -#define trace_cdns3_gadget_ep_disable(a) -#define trace_cdns3_ep0_queue(a, b) -#define trace_cdns3_ep0_dequeue(a) -#define trace_cdns3_ep_queue(a) -#define trace_cdns3_ep_dequeue(a) -#define trace_cdns3_halt(a, b, c) -#define trace_cdns3_wa1(a, b) -#define trace_cdns3_wa2(a, b) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index dfd7cf683f7..bdd7ec27808 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -441,6 +441,25 @@ static void dwc3_phy_setup(struct dwc3 *dwc) mdelay(100); } +void dwc3_set_suspend_clk(struct dwc3 *dwc) +{ + u32 reg; + + /* + * DWC3_GCTL.PWRDNSCALE: The USB3 suspend_clk input replaces + * pipe3_rx_pclk as a clock source to a small part of the USB3 + * core that operates when the SS PHY is in its lowest power + * (P3) state, and therefore does not provide a clock. + * The Power Down Scale field specifies how many suspend_clk + * periods fit into a 16 kHz clock period. When performing the + * division, round up the remainder. + */ + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~(DWC3_GCTL_PWRDNSCALE(0x1fff)); + reg |= DWC3_GCTL_PWRDNSCALE(dwc->power_down_scale); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + /** * dwc3_core_init - Low-level initialization of DWC3 Core * @dwc: Pointer to our controller context structure @@ -491,6 +510,9 @@ static int dwc3_core_init(struct dwc3 *dwc) if (ret) goto err0; + if (dwc->power_down_scale) + dwc3_set_suspend_clk(dwc); + reg = dwc3_readl(dwc->regs, DWC3_GCTL); reg &= ~DWC3_GCTL_SCALEDOWN_MASK; @@ -561,6 +583,20 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GCTL, reg); + /* + * Disable Park Mode: + * Park mode can only be used in host mode with only a single + * async endpoint is active, but which has a known issue cause + * USB3.0 HC may die when read and write at the same time, + * considering this mode only can improve the delay between + * bursts in case only one endpoint is active, it's not really + * useful, so disable it, Synopsys will release a formal STAR + * and disable it by default in next IP release. + */ + reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); + reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + ret = dwc3_alloc_scratch_buffers(dwc); if (ret) goto err0; @@ -627,12 +663,6 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) return 0; } -static void dwc3_gadget_run(struct dwc3 *dwc) -{ - dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP); - mdelay(100); -} - static void dwc3_core_exit_mode(struct dwc3 *dwc) { switch (dwc->dr_mode) { @@ -650,13 +680,6 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc) /* do nothing */ break; } - - /* - * switch back to peripheral mode - * This enables the phy to enter idle and then, if enabled, suspend. - */ - dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); - dwc3_gadget_run(dwc); } #define DWC3_ALIGN_MASK (16 - 1) @@ -737,6 +760,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev) if (dwc3_dev->tx_de_emphasis) tx_de_emphasis = dwc3_dev->tx_de_emphasis; + dwc->power_down_scale = dwc3_dev->power_down_scale; + /* default to superspeed if no maximum_speed passed */ if (dwc->maximum_speed == USB_SPEED_UNKNOWN) dwc->maximum_speed = USB_SPEED_SUPER; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 44533fd7fed..d53d962feb9 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -168,6 +168,8 @@ /* Global User Control 1 Register */ #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) +/* Disable park mode for super speed */ +#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) @@ -665,6 +667,7 @@ struct dwc3_scratchpad_array { * - USBPHY_INTERFACE_MODE_UTMIW * @dcfg: saved contents of DCFG register * @gctl: saved contents of GCTL register + * @power_down_scale: 16KHz clock periods for suspend_clk * @isoch_delay: wValue from Set Isochronous Delay request; * @u2sel: parameter from Set SEL request. * @u2pel: parameter from Set SEL request. @@ -791,6 +794,7 @@ struct dwc3 { enum dwc3_ep0_state ep0state; enum dwc3_link_state link_state; + u16 power_down_scale; u16 isoch_delay; u16 u2sel; u16 u2pel; diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 30f835e1e3d..149e81ed531 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -128,7 +128,7 @@ static int dwc3_generic_of_to_plat(struct udevice *dev) } #if CONFIG_IS_ENABLED(DM_USB_GADGET) -int dm_usb_gadget_handle_interrupts(struct udevice *dev) +static int dwc3_generic_peripheral_handle_interrupts(struct udevice *dev) { struct dwc3_generic_priv *priv = dev_get_priv(dev); struct dwc3 *dwc3 = &priv->dwc3; @@ -158,6 +158,7 @@ U_BOOT_DRIVER(dwc3_generic_peripheral) = { .of_to_plat = dwc3_generic_of_to_plat, .probe = dwc3_generic_peripheral_probe, .remove = dwc3_generic_peripheral_remove, + .handle_interrupts = dwc3_generic_peripheral_handle_interrupts, .priv_auto = sizeof(struct dwc3_generic_priv), .plat_auto = sizeof(struct dwc3_generic_plat), }; diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c index 75ac993bc64..a93764b0bb0 100644 --- a/drivers/usb/dwc3/ep0.c +++ b/drivers/usb/dwc3/ep0.c @@ -394,7 +394,6 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc, u32 recip; u32 wValue; u32 wIndex; - u32 reg; int ret; enum usb_device_state state; @@ -418,27 +417,12 @@ static int dwc3_ep0_handle_feature(struct dwc3 *dwc, return -EINVAL; if (dwc->speed != DWC3_DSTS_SUPERSPEED) return -EINVAL; - - reg = dwc3_readl(dwc->regs, DWC3_DCTL); - if (set) - reg |= DWC3_DCTL_INITU1ENA; - else - reg &= ~DWC3_DCTL_INITU1ENA; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); break; - case USB_DEVICE_U2_ENABLE: if (state != USB_STATE_CONFIGURED) return -EINVAL; if (dwc->speed != DWC3_DSTS_SUPERSPEED) return -EINVAL; - - reg = dwc3_readl(dwc->regs, DWC3_DCTL); - if (set) - reg |= DWC3_DCTL_INITU2ENA; - else - reg &= ~DWC3_DCTL_INITU2ENA; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); break; case USB_DEVICE_LTM_ENABLE: @@ -542,7 +526,6 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) enum usb_device_state state = dwc->gadget.state; u32 cfg; int ret; - u32 reg; dwc->start_config_issued = false; cfg = le16_to_cpu(ctrl->wValue); @@ -566,14 +549,6 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl) usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED); - /* - * Enable transition to U1/U2 state when - * nothing is pending from application. - */ - reg = dwc3_readl(dwc->regs, DWC3_DCTL); - reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA); - dwc3_writel(dwc->regs, DWC3_DCTL, reg); - dwc->resize_fifos = true; dev_dbg(dwc->dev, "resize FIFOs flag SET"); } diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 4e68fb0a82f..978eb695aef 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -972,8 +972,8 @@ static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req) * so HACK the request length */ if (dep->direction == 0 && - req->request.length < dep->endpoint.maxpacket) - req->request.length = dep->endpoint.maxpacket; + req->request.length < usb_endpoint_maxp(dep->endpoint.desc)) + req->request.length = usb_endpoint_maxp(dep->endpoint.desc); /* * We only add to our list of requests now and @@ -1486,7 +1486,7 @@ static int dwc3_gadget_start(struct usb_gadget *g, if (dwc->revision < DWC3_REVISION_220A) { reg |= DWC3_DCFG_SUPERSPEED; } else { - switch (dwc->maximum_speed) { + switch (dwc->gadget.max_speed) { case USB_SPEED_LOW: reg |= DWC3_DSTS_LOWSPEED; break; @@ -1610,7 +1610,12 @@ static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, } else { int ret; - usb_ep_set_maxpacket_limit(&dep->endpoint, 512); + if (dwc->maximum_speed >= USB_SPEED_SUPER) + usb_ep_set_maxpacket_limit(&dep->endpoint, + 1024); + else + usb_ep_set_maxpacket_limit(&dep->endpoint, + 512); dep->endpoint.max_streams = 15; dep->endpoint.ops = &dwc3_gadget_ep_ops; list_add_tail(&dep->endpoint.ep_list, @@ -2563,6 +2568,7 @@ static irqreturn_t dwc3_interrupt(int irq, void *_dwc) int dwc3_gadget_init(struct dwc3 *dwc) { int ret; + u32 reg; dwc->ctrl_req = dma_alloc_coherent(sizeof(*dwc->ctrl_req), (unsigned long *)&dwc->ctrl_req_addr); @@ -2596,7 +2602,7 @@ int dwc3_gadget_init(struct dwc3 *dwc) } dwc->gadget.ops = &dwc3_gadget_ops; - dwc->gadget.max_speed = USB_SPEED_SUPER; + dwc->gadget.max_speed = dwc->maximum_speed; dwc->gadget.speed = USB_SPEED_UNKNOWN; dwc->gadget.name = "dwc3-gadget"; @@ -2621,6 +2627,10 @@ int dwc3_gadget_init(struct dwc3 *dwc) goto err4; } + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + reg &= ~(DWC3_DCTL_INITU1ENA | DWC3_DCTL_INITU2ENA); + dwc3_writel(dwc->regs, DWC3_DCTL, reg); + return 0; err4: diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 4a3b22e6def..cc1ffe873c4 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -110,6 +110,7 @@ config USB_GADGET_OS_DESCRIPTORS config CI_UDC bool "ChipIdea device controller" select USB_GADGET_DUALSPEED + imply DM_USB_GADGET help Say Y here to enable device controller functionality of the ChipIdea driver. @@ -180,6 +181,15 @@ config USB_FUNCTION_THOR Enable Tizen's THOR download protocol support in U-Boot. It allows downloading images into memory and flash them to target device. +config USB_PORT_AUTO + bool "Enable USB port autodetect" + depends on CI_UDC + help + Enable usb port autodetect function for i.MX8. There two usb ports - + usb2 and usb3 on i.MX8, when use SDP or fastboot which runs automatically + when uboot starts, enable this config will autodetect the connected usb + port instead of specify USB port to download in code. + endif # USB_GADGET_DOWNLOAD config USB_ETHER diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 226a9e6d671..441e43cda0e 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -13,16 +13,27 @@ #include #include #include +#include +#include +#include +#include #include #include #include #include #include #include +#include +#include +#include #include #include #include +#include +#include #include +#include +#include #include "../host/ehci.h" #include "ci_udc.h" @@ -93,9 +104,18 @@ static int ci_ep_dequeue(struct usb_ep *ep, struct usb_request *req); static struct usb_request * ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags); static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req); +#if CONFIG_IS_ENABLED(DM_USB_GADGET) +static int ci_udc_gadget_start(struct usb_gadget *g, + struct usb_gadget_driver *driver); +static int ci_udc_gadget_stop(struct usb_gadget *g); +#endif static struct usb_gadget_ops ci_udc_ops = { .pullup = ci_pullup, +#if CONFIG_IS_ENABLED(DM_USB_GADGET) + .udc_start = ci_udc_gadget_start, + .udc_stop = ci_udc_gadget_stop, +#endif }; static struct usb_ep_ops ci_ep_ops = { @@ -866,7 +886,7 @@ void udc_irq(void) } } -int usb_gadget_handle_interrupts(int index) +int ci_udc_handle_interrupts(void) { u32 value; struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; @@ -1010,6 +1030,112 @@ static int ci_udc_probe(void) return 0; } +bool dfu_usb_get_reset(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + + return !!(readl(&udc->usbsts) & STS_URI); +} + +static int ci_udc_otg_phy_mode2(ulong phy_addr) +{ + void *__iomem phy_ctrl, *__iomem phy_status; + void *__iomem phy_base = (void *__iomem)phy_addr; + u32 val; + + if (is_mx6() || is_mx7ulp() || is_imx8()) { + phy_ctrl = (void __iomem *)(phy_base + USBPHY_CTRL); + val = readl(phy_ctrl); + if (val & USBPHY_CTRL_OTG_ID) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + } else if (is_mx7() || is_imx8mm() || is_imx8mn()) { + phy_status = (void __iomem *)(phy_base + + USBNC_PHY_STATUS_OFFSET); + val = readl(phy_status); + if (val & USBNC_PHYSTATUS_ID_DIG) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + } else { + return -EINVAL; + } +} + +bool udc_irq_reset(void) +{ + struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + unsigned n = readl(&udc->usbsts); + writel(n, &udc->usbsts); + + n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI); + if (n == 0) + return false; + + if (n & STS_URI) { + DBG("-- reset --\n"); + return true; + } + + if (n & STS_SLI) + DBG("-- suspend --\n"); + + return false; +} + +bool ci_udc_check_bus_active(ulong ehci_addr, ulong phy_addr, int index) +{ + struct usb_ehci *ehci = (struct usb_ehci *)ehci_addr; + struct ehci_ctrl ctrl; + int ret; + bool active = false; + + ret = ehci_mx6_common_init(ehci, index); + if (ret) + return false; + + if (ci_udc_otg_phy_mode2(phy_addr) != USB_INIT_DEVICE) + return false; + + ctrl.hccr = (struct ehci_hccr *)((ulong)&ehci->caplength); + ctrl.hcor = (struct ehci_hcor *)((ulong)ctrl.hccr + + HC_LENGTH(ehci_readl(&(ctrl.hccr)->cr_capbase))); + controller.ctrl = &ctrl; + + ret = ci_udc_probe(); + if (ret) { + return false; + } + + ci_pullup(NULL, 1); + + int count = 100; + while (count > 0) { + if (udc_irq_reset()) { + active = true; + break; + } + mdelay(10); + count--; + } + + ci_pullup(NULL, 0); + + ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req); + free(controller.items_mem); + free(controller.epts); + + return active; +} + + +#if !CONFIG_IS_ENABLED(DM_USB_GADGET) +int usb_gadget_handle_interrupts(int index) +{ + return ci_udc_handle_interrupts(); +} + int usb_gadget_register_driver(struct usb_gadget_driver *driver) { int ret; @@ -1063,10 +1189,281 @@ int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) return 0; } +#else /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */ -bool dfu_usb_get_reset(void) +static int ci_udc_gadget_start(struct usb_gadget *g, + struct usb_gadget_driver *driver) { - struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; + if (!driver) + return -EINVAL; + if (!driver->bind || !driver->setup || !driver->disconnect) + return -EINVAL; - return !!(readl(&udc->usbsts) & STS_URI); + controller.driver = driver; + return 0; +} + +static int ci_udc_gadget_stop(struct usb_gadget *g) +{ + controller.driver = NULL; + + ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req); + free(controller.items_mem); + free(controller.epts); + return 0; +} + +struct ci_udc_priv_data { + struct ehci_ctrl ctrl; + struct udevice otgdev; + struct clk_bulk clks; + int phy_off; + struct power_domain otg_pd; + struct clk phy_clk; + struct power_domain phy_pd; +}; + +static int ci_udc_gadget_handle_interrupts(struct udevice *dev) +{ + return ci_udc_handle_interrupts(); +} + +static int ci_udc_phy_setup(struct udevice *dev, struct ci_udc_priv_data *priv) +{ + struct udevice __maybe_unused phy_dev; + priv->phy_off = fdtdec_lookup_phandle(gd->fdt_blob, + dev_of_offset(dev), + "fsl,usbphy"); + if (priv->phy_off < 0) + return -EINVAL; + + dev_set_ofnode(&phy_dev, offset_to_ofnode(priv->phy_off)); + +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + /* Need to power on the PHY before access it */ + if (!power_domain_get(&phy_dev, &priv->phy_pd)) { + if (power_domain_on(&priv->phy_pd)) + return -EINVAL; + } +#endif + +#if CONFIG_IS_ENABLED(CLK) + int ret; + + ret = clk_get_by_index(&phy_dev, 0, &priv->phy_clk); + if (ret) { + printf("Failed to get phy_clk\n"); + return ret; + } + + ret = clk_enable(&priv->phy_clk); + if (ret) { + printf("Failed to enable phy_clk\n"); + return ret; + } +#endif + + return 0; +} + +static int ci_udc_phy_shutdown(struct ci_udc_priv_data *priv) +{ + int ret = 0; + +#if CONFIG_IS_ENABLED(CLK) + if (priv->phy_clk.dev) { + ret = clk_disable(&priv->phy_clk); + if (ret) + return ret; + + ret = clk_free(&priv->phy_clk); + if (ret) + return ret; + } +#endif + +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + ret = power_domain_off(&priv->phy_pd); + if (ret) + printf("Power down USB PHY failed! (error = %d)\n", ret); +#endif + return ret; +} + +static int ci_udc_otg_clk_init(struct udevice *dev, + struct clk_bulk *clks) +{ + int ret; + + ret = clk_get_bulk(dev, clks); + if (ret == -ENOSYS) + return 0; + + if (ret) + return ret; + +#if CONFIG_IS_ENABLED(CLK) + ret = clk_enable_bulk(clks); + if (ret) { + clk_release_bulk(clks); + return ret; + } +#endif + + return 0; +} + +static int ci_udc_otg_phy_mode(struct udevice *dev) +{ + struct ci_udc_priv_data *priv = dev_get_priv(dev); + + void *__iomem phy_ctrl, *__iomem phy_status; + void *__iomem phy_base = (void *__iomem)devfdt_get_addr(&priv->otgdev); + u32 val; + + if (is_mx6() || is_mx7ulp() || is_imx8()) { + phy_base = (void __iomem *)fdtdec_get_addr(gd->fdt_blob, + priv->phy_off, + "reg"); + if ((fdt_addr_t)phy_base == FDT_ADDR_T_NONE) + return -EINVAL; + + phy_ctrl = (void __iomem *)(phy_base + USBPHY_CTRL); + val = readl(phy_ctrl); + if (val & USBPHY_CTRL_OTG_ID) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + } else if (is_mx7() || is_imx8mm() || is_imx8mn()) { + phy_status = (void __iomem *)(phy_base + + USBNC_PHY_STATUS_OFFSET); + val = readl(phy_status); + if (val & USBNC_PHYSTATUS_ID_DIG) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; + } else { + return -EINVAL; + } +} + +static int ci_udc_otg_ofdata_to_platdata(struct udevice *dev) +{ + struct ci_udc_priv_data *priv = dev_get_priv(dev); + int node = dev_of_offset(dev); + int usbotg_off; + + if (usb_get_dr_mode(dev_ofnode(dev)) != USB_DR_MODE_PERIPHERAL) { + dev_dbg(dev, "Invalid mode\n"); + return -ENODEV; + } + + usbotg_off = fdtdec_lookup_phandle(gd->fdt_blob, + node, + "chipidea,usb"); + if (usbotg_off < 0) + return -EINVAL; + dev_set_ofnode(&priv->otgdev, offset_to_ofnode(usbotg_off)); + priv->otgdev.parent = dev->parent; + + return 0; +} + +static int ci_udc_otg_probe(struct udevice *dev) +{ + struct ci_udc_priv_data *priv = dev_get_priv(dev); + struct usb_ehci *ehci; + int ret; + + ehci = (struct usb_ehci *)devfdt_get_addr(&priv->otgdev); + + pinctrl_select_state(&priv->otgdev, "default"); + +#if defined(CONFIG_MX6) + if (usb_fused((u32)ehci)) { + printf("USB@0x%x is fused, disable it\n", (u32)ehci); + return -ENODEV; + } +#endif + + ret = board_usb_init(dev_seq(dev), USB_INIT_DEVICE); + if (ret) { + printf("Failed to initialize board for USB\n"); + return ret; + } + +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + if (!power_domain_get(&priv->otgdev, &priv->otg_pd)) { + if (power_domain_on(&priv->otg_pd)) + return -EINVAL; + } +#endif + + ret = ci_udc_phy_setup(&priv->otgdev, priv); + if (ret) + return ret; + + ret = ci_udc_otg_clk_init(&priv->otgdev, &priv->clks); + if (ret) + return ret; + + ret = ehci_mx6_common_init(ehci, dev_seq(dev)); + if (ret) + return ret; + + if (ci_udc_otg_phy_mode(dev) != USB_INIT_DEVICE) + return -ENODEV; + + priv->ctrl.hccr = (struct ehci_hccr *)((ulong)&ehci->caplength); + priv->ctrl.hcor = (struct ehci_hcor *)((ulong)priv->ctrl.hccr + + HC_LENGTH(ehci_readl(&(priv->ctrl.hccr)->cr_capbase))); + controller.ctrl = &priv->ctrl; + + ret = ci_udc_probe(); + if (ret) { + DBG("udc probe failed, returned %d\n", ret); + return ret; + } + + ret = usb_add_gadget_udc((struct device *)dev, &controller.gadget); + + return ret; } + +static int ci_udc_otg_remove(struct udevice *dev) +{ + struct ci_udc_priv_data *priv = dev_get_priv(dev); + + usb_del_gadget_udc(&controller.gadget); + + clk_release_bulk(&priv->clks); + ci_udc_phy_shutdown(priv); +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + if (power_domain_off(&priv->otg_pd)) { + printf("Power down USB controller failed!\n"); + return -EINVAL; + } +#endif + board_usb_cleanup(dev_seq(dev), USB_INIT_DEVICE); + + controller.ctrl = NULL; + return 0; +} + +static const struct udevice_id ci_udc_otg_ids[] = { + { .compatible = "fsl,imx27-usb-gadget" }, + { } +}; + +U_BOOT_DRIVER(ci_udc_otg) = { + .name = "ci-udc-otg", + .id = UCLASS_USB_GADGET_GENERIC, + .of_match = ci_udc_otg_ids, + .of_to_plat = ci_udc_otg_ofdata_to_platdata, + .probe = ci_udc_otg_probe, + .remove = ci_udc_otg_remove, + .handle_interrupts = ci_udc_gadget_handle_interrupts, + .priv_auto = sizeof(struct ci_udc_priv_data), +}; + +#endif /* !CONFIG_IS_ENABLED(DM_USB_GADGET) */ diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c index 7da334f5d31..bcfd9e422f8 100644 --- a/drivers/usb/gadget/epautoconf.c +++ b/drivers/usb/gadget/epautoconf.c @@ -143,6 +143,7 @@ static int ep_matches( /* MATCH!! */ /* report address */ + desc->bEndpointAddress &= 0xF0; if (isdigit(ep->name[2])) { u8 num = simple_strtoul(&ep->name[2], NULL, 10); desc->bEndpointAddress |= num; diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 8ba55aab9f8..0d2b6bc2c92 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include #define FASTBOOT_INTERFACE_CLASS 0xff #define FASTBOOT_INTERFACE_SUB_CLASS 0x42 @@ -38,12 +40,20 @@ * that expect bulk OUT requests to be divisible by maxpacket size. */ +typedef struct usb_req usb_req; +struct usb_req { + struct usb_request *in_req; + usb_req *next; +}; + struct f_fastboot { struct usb_function usb_function; /* IN/OUT EP's and corresponding requests */ struct usb_ep *in_ep, *out_ep; struct usb_request *in_req, *out_req; + + usb_req *front, *rear; }; static char fb_ext_prop_name[] = "DeviceInterfaceGUID"; @@ -192,8 +202,30 @@ static struct usb_gadget_strings *fastboot_strings[] = { NULL, }; +#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) +extern struct stdio_dev g_fastboot_stdio; +#endif + static void rx_handler_command(struct usb_ep *ep, struct usb_request *req); +static void fastboot_fifo_complete(struct usb_ep *ep, struct usb_request *req) +{ + int status = req->status; + usb_req *request; + + if (!status) { + if (fastboot_func->front != NULL) { + request = fastboot_func->front; + fastboot_func->front = fastboot_func->front->next; + usb_ep_free_request(ep, request->in_req); + free(request); + } else { + printf("fail free request\n"); + } + return; + } +} + static void fastboot_complete(struct usb_ep *ep, struct usb_request *req) { int status = req->status; @@ -264,6 +296,10 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) if (s) g_dnl_set_serialnumber((char *)s); +#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) + stdio_register(&g_fastboot_stdio); +#endif + return 0; } @@ -272,6 +308,14 @@ static void fastboot_unbind(struct usb_configuration *c, struct usb_function *f) f->os_desc_table = NULL; list_del(&fb_os_desc.ext_prop); memset(fastboot_func, 0, sizeof(*fastboot_func)); + +#if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) && CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER) + struct stdio_dev *dev; + dev = stdio_get_by_name("fastboot"); + if (dev) + stdio_deregister_dev(dev, 1); +#endif + } static void fastboot_disable(struct usb_function *f) @@ -397,11 +441,57 @@ static int fastboot_add(struct usb_configuration *c) } DECLARE_GADGET_BIND_CALLBACK(usb_dnl_fastboot, fastboot_add); -static int fastboot_tx_write(const char *buffer, unsigned int buffer_size) +int fastboot_tx_write_more(const char *buffer) +{ + int ret = 0; + + /* alloc usb request FIFO node */ + usb_req *req = (usb_req *)malloc(sizeof(usb_req)); + if (!req) { + printf("failed alloc usb req!\n"); + return -ENOMEM; + } + + /* usb request node FIFO enquene */ + if ((fastboot_func->front == NULL) && (fastboot_func->rear == NULL)) { + fastboot_func->front = fastboot_func->rear = req; + req->next = NULL; + } else { + fastboot_func->rear->next = req; + fastboot_func->rear = req; + req->next = NULL; + } + + /* alloc in request for current node */ + req->in_req = fastboot_start_ep(fastboot_func->in_ep); + if (!req->in_req) { + printf("failed alloc req in\n"); + fastboot_disable(&(fastboot_func->usb_function)); + return -EINVAL; + } + req->in_req->complete = fastboot_fifo_complete; + + memcpy(req->in_req->buf, buffer, strlen(buffer)); + req->in_req->length = strlen(buffer); + + ret = usb_ep_queue(fastboot_func->in_ep, req->in_req, 0); + if (ret) { + printf("Error %d on queue\n", ret); + return -EINVAL; + } + + ret = 0; + return ret; +} + +int fastboot_tx_write(const char *buffer, unsigned int buffer_size) { struct usb_request *in_req = fastboot_func->in_req; int ret; + if (!buffer_size) + return 0; + memcpy(in_req->buf, buffer, buffer_size); in_req->length = buffer_size; @@ -418,9 +508,17 @@ static int fastboot_tx_write_str(const char *buffer) return fastboot_tx_write(buffer, strlen(buffer)); } +#ifdef CONFIG_PSCI_BOARD_REBOOT +int do_board_reboot(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]); +#endif + static void compl_do_reset(struct usb_ep *ep, struct usb_request *req) { +#ifdef CONFIG_PSCI_BOARD_REBOOT + do_board_reboot(NULL, 0, 0, NULL); +#else do_reset(NULL, 0, 0, NULL); +#endif } static unsigned int rx_bytes_expected(struct usb_ep *ep) @@ -512,6 +610,10 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) char response[FASTBOOT_RESPONSE_LEN] = {0}; int cmd = -1; + /* init in request FIFO pointer */ + fastboot_func->front = NULL; + fastboot_func->rear = NULL; + if (req->status != 0 || req->length == 0) return; @@ -542,6 +644,9 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req) case FASTBOOT_COMMAND_REBOOT_BOOTLOADER: case FASTBOOT_COMMAND_REBOOT_FASTBOOTD: case FASTBOOT_COMMAND_REBOOT_RECOVERY: +#ifdef CONFIG_ANDROID_RECOVERY + case FASTBOOT_COMMAND_RECOVERY_FASTBOOT: +#endif fastboot_func->in_req->complete = compl_do_reset; break; #if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c index afb7b74f305..444707171d6 100644 --- a/drivers/usb/gadget/g_dnl.c +++ b/drivers/usb/gadget/g_dnl.c @@ -316,3 +316,8 @@ void g_dnl_unregister(void) { usb_composite_unregister(&g_dnl_driver); } + +int __weak board_usb_gadget_port_auto(void) +{ + return -1; +} diff --git a/drivers/usb/gadget/udc/Makefile b/drivers/usb/gadget/udc/Makefile index 95dbf0c82ee..414edad9218 100644 --- a/drivers/usb/gadget/udc/Makefile +++ b/drivers/usb/gadget/udc/Makefile @@ -4,6 +4,7 @@ ifndef CONFIG_$(SPL_)DM_USB_GADGET obj-$(CONFIG_USB_DWC3_GADGET) += udc-core.o +obj-$(CONFIG_USB_CDNS3_GADGET) += udc-core.o endif obj-$(CONFIG_$(SPL_)DM_USB_GADGET) += udc-core.o diff --git a/drivers/usb/gadget/udc/udc-uclass.c b/drivers/usb/gadget/udc/udc-uclass.c index 3053ccf7d97..f117a42a656 100644 --- a/drivers/usb/gadget/udc/udc-uclass.c +++ b/drivers/usb/gadget/udc/udc-uclass.c @@ -51,9 +51,20 @@ int usb_gadget_release(int index) int usb_gadget_handle_interrupts(int index) { + const struct driver *drv; + if (index < 0 || index >= ARRAY_SIZE(dev_array)) return -EINVAL; - return dm_usb_gadget_handle_interrupts(dev_array[index]); + + drv = dev_array[index]->driver; + assert(drv); + + if (drv->handle_interrupts) + return drv->handle_interrupts(dev_array[index]); + else + pr_err("No handle_interrupts function found\n"); + + return -EINVAL; } #endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0971a7c8139..7f4ac58cc43 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -102,11 +102,26 @@ config USB_XHCI_BRCM USB controller based on the Broadcom USB3 IP Core. Supports USB2/3 functionality. +config USB_XHCI_IMX8 + bool "XHCI support for i.MX8" + depends on ARCH_IMX8 + default y + help + Enables support for the on-chip xHCI controller on i.MX8QM and + i.MX8QXP SoCs. + +config USB_XHCI_IMX8M + bool "XHCI support for imx8M(mscale)" + depends on ARCH_IMX8M + default y + help + Enables support for the on-chip xHCI controller on imx8m(mscale) SoC. + endif # USB_XHCI_HCD config USB_EHCI_HCD bool "EHCI HCD (USB 2.0) support" - default y if ARCH_MX5 || ARCH_MX6 + default y if ARCH_MX5 || ARCH_MX6 || ARCH_IMX8 select USB_HOST ---help--- The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 @@ -148,15 +163,15 @@ config USB_EHCI_MX5 Enables support for the on-chip EHCI controller on i.MX5 SoCs. config USB_EHCI_MX6 - bool "Support for i.MX6/i.MX7ULP on-chip EHCI USB controller" - depends on ARCH_MX6 || ARCH_MX7ULP + bool "Support for i.MX6/i.MX7ULP/i.MX8 on-chip EHCI USB controller" + depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMX8 default y ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. config USB_EHCI_MX7 bool "Support for i.MX7 on-chip EHCI USB controller" - depends on ARCH_MX7 + depends on ARCH_MX7 || IMX8MM || IMX8MN default y ---help--- Enables support for the on-chip EHCI controller on i.MX7 SoCs. diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index a12e8f27025..70a22a695b2 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -57,6 +57,8 @@ obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o obj-$(CONFIG_USB_XHCI_RCAR) += xhci-rcar.o obj-$(CONFIG_USB_XHCI_STI) += dwc3-sti-glue.o obj-$(CONFIG_USB_XHCI_OCTEON) += dwc3-octeon-glue.o +obj-$(CONFIG_USB_XHCI_IMX8) += xhci-imx8.o +obj-$(CONFIG_USB_XHCI_IMX8M) += xhci-imx8m.o # designware obj-$(CONFIG_USB_DWC2) += dwc2.o diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 8933f608439..ba75c27d04e 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -346,6 +346,28 @@ static int ehci_disable_async(struct ehci_ctrl *ctrl) return ret; } +static int ehci_iaa_cycle(struct ehci_ctrl *ctrl) +{ + u32 cmd, status; + int ret; + + /* Enable Interrupt on Async Advance Doorbell. */ + cmd = ehci_readl(&ctrl->hcor->or_usbcmd); + cmd |= CMD_IAAD; + ehci_writel(&ctrl->hcor->or_usbcmd, cmd); + + ret = handshake(&ctrl->hcor->or_usbsts, STS_IAA, STS_IAA, + 10 * 1000); /* 10ms timeout */ + if (ret < 0) + printf("EHCI fail timeout STS_IAA set\n"); + + status = ehci_readl(&ctrl->hcor->or_usbsts); + if (status & STS_IAA) + ehci_writel(&ctrl->hcor->or_usbsts, STS_IAA); + + return ret; +} + static int ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, int length, struct devrequest *req) @@ -631,6 +653,11 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer, flush_dcache_range((unsigned long)&ctrl->qh_list, ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1)); + /* Set IAAD, poll IAA */ + ret = ehci_iaa_cycle(ctrl); + if (ret) + goto fail; + /* * Invalidate the memory area occupied by buffer * Don't try to fix the buffer alignment, if it isn't properly diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index aeea5399995..57b0e5c548a 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -2,6 +2,8 @@ /* * Copyright (c) 2009 Daniel Mack * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * */ #include @@ -13,10 +15,12 @@ #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -24,277 +28,30 @@ #include #include "ehci.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define USB_OTGREGS_OFFSET 0x000 -#define USB_H1REGS_OFFSET 0x200 -#define USB_H2REGS_OFFSET 0x400 -#define USB_H3REGS_OFFSET 0x600 -#define USB_OTHERREGS_OFFSET 0x800 - -#define USB_H1_CTRL_OFFSET 0x04 - -#define USBPHY_CTRL 0x00000030 -#define USBPHY_CTRL_SET 0x00000034 -#define USBPHY_CTRL_CLR 0x00000038 -#define USBPHY_CTRL_TOG 0x0000003c - -#define USBPHY_PWD 0x00000000 -#define USBPHY_CTRL_SFTRST 0x80000000 -#define USBPHY_CTRL_CLKGATE 0x40000000 -#define USBPHY_CTRL_ENUTMILEVEL3 0x00008000 -#define USBPHY_CTRL_ENUTMILEVEL2 0x00004000 -#define USBPHY_CTRL_OTG_ID 0x08000000 - -#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 -#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 - -#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 -#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 -#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 -#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 - -#define USBNC_OFFSET 0x200 -#define USBNC_PHY_STATUS_OFFSET 0x23C -#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ -#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ -#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */ -#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ -#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ - -/* USBCMD */ -#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ -#define UCMD_RESET (1 << 1) /* controller reset */ - -#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) -static const unsigned phy_bases[] = { - USB_PHY0_BASE_ADDR, -#if defined(USB_PHY1_BASE_ADDR) - USB_PHY1_BASE_ADDR, +#if CONFIG_IS_ENABLED(POWER_DOMAIN) +#include #endif -}; - -static void usb_internal_phy_clock_gate(int index, int on) -{ - void __iomem *phy_reg; - - if (index >= ARRAY_SIZE(phy_bases)) - return; - - phy_reg = (void __iomem *)phy_bases[index]; - phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; - writel(USBPHY_CTRL_CLKGATE, phy_reg); -} - -static void usb_power_config(int index) -{ -#if defined(CONFIG_MX7ULP) - struct usbphy_regs __iomem *usbphy = - (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR; - - if (index > 0) - return; +#include - writel(ANADIG_USB2_CHRG_DETECT_EN_B | - ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, - &usbphy->usb1_chrg_detect); - - scg_enable_usb_pll(true); - -#else - struct anatop_regs __iomem *anatop = - (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; - void __iomem *chrg_detect; - void __iomem *pll_480_ctrl_clr; - void __iomem *pll_480_ctrl_set; - - switch (index) { - case 0: - chrg_detect = &anatop->usb1_chrg_detect; - pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; - pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set; - break; - case 1: - chrg_detect = &anatop->usb2_chrg_detect; - pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr; - pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set; - break; - default: - return; - } - /* - * Some phy and power's special controls - * 1. The external charger detector needs to be disabled - * or the signal at DP will be poor - * 2. The PLL's power and output to usb - * is totally controlled by IC, so the Software only needs - * to enable them at initializtion. - */ - writel(ANADIG_USB2_CHRG_DETECT_EN_B | - ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, - chrg_detect); - - writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, - pll_480_ctrl_clr); - - writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | - ANADIG_USB2_PLL_480_CTRL_POWER | - ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, - pll_480_ctrl_set); - -#endif -} - -/* Return 0 : host node, <>0 : device mode */ -static int usb_phy_enable(int index, struct usb_ehci *ehci) -{ - void __iomem *phy_reg; - void __iomem *phy_ctrl; - void __iomem *usb_cmd; - int ret; - - if (index >= ARRAY_SIZE(phy_bases)) - return 0; - - phy_reg = (void __iomem *)phy_bases[index]; - phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); - usb_cmd = (void __iomem *)&ehci->usbcmd; - - /* Stop then Reset */ - clrbits_le32(usb_cmd, UCMD_RUN_STOP); - ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false); - if (ret) - return ret; - - setbits_le32(usb_cmd, UCMD_RESET); - ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false); - if (ret) - return ret; - - /* Reset USBPHY module */ - setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); - udelay(10); - - /* Remove CLKGATE and SFTRST */ - clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); - udelay(10); - - /* Power up the PHY */ - writel(0, phy_reg + USBPHY_PWD); - /* enable FS/LS device */ - setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | - USBPHY_CTRL_ENUTMILEVEL3); - - return 0; -} - -int usb_phy_mode(int port) -{ - void __iomem *phy_reg; - void __iomem *phy_ctrl; - u32 val; - - phy_reg = (void __iomem *)phy_bases[port]; - phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); - - val = readl(phy_ctrl); - - if (val & USBPHY_CTRL_OTG_ID) - return USB_INIT_DEVICE; - else - return USB_INIT_HOST; -} - -#if defined(CONFIG_MX7ULP) -struct usbnc_regs { - u32 ctrl1; - u32 ctrl2; - u32 reserve0[2]; - u32 hsic_ctrl; -}; -#else -/* Base address for this IP block is 0x02184800 */ -struct usbnc_regs { - u32 ctrl[4]; /* otg/host1-3 */ - u32 uh2_hsic_ctrl; - u32 uh3_hsic_ctrl; - u32 otg_phy_ctrl_0; - u32 uh1_phy_ctrl_0; -}; -#endif - -#elif defined(CONFIG_MX7) -struct usbnc_regs { - u32 ctrl1; - u32 ctrl2; - u32 reserve1[10]; - u32 phy_cfg1; - u32 phy_cfg2; - u32 reserve2; - u32 phy_status; - u32 reserve3[4]; - u32 adp_cfg1; - u32 adp_cfg2; - u32 adp_status; -}; - -static void usb_power_config(int index) -{ - struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + - (0x10000 * index) + USBNC_OFFSET); - void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); - - /* - * Clear the ACAENB to enable usb_otg_id detection, - * otherwise it is the ACA detection enabled. - */ - clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); -} - -int usb_phy_mode(int port) -{ - struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + - (0x10000 * port) + USBNC_OFFSET); - void __iomem *status = (void __iomem *)(&usbnc->phy_status); - u32 val; - - val = readl(status); - - if (val & USBNC_PHYSTATUS_ID_DIG) - return USB_INIT_DEVICE; - else - return USB_INIT_HOST; -} -#endif +DECLARE_GLOBAL_DATA_PTR; -static void usb_oc_config(int index) +static void ehci_mx6_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, + uint32_t *reg) { -#if defined(CONFIG_MX6) - struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + - USB_OTHERREGS_OFFSET); - void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); -#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) - struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + - (0x10000 * index) + USBNC_OFFSET); - void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); -#endif + uint32_t result; + int usec = 2000; -#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 - /* mx6qarm2 seems to required a different setting*/ - clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); -#else - setbits_le32(ctrl, UCTRL_OVER_CUR_POL); -#endif + mdelay(50); - setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); + do { + result = ehci_readl(status_reg); + udelay(5); + if (!(result & EHCI_PS_PR)) + break; + usec--; + } while (usec > 0); - /* Set power polarity to high active */ -#ifdef CONFIG_MXC_USB_OTG_HACTIVE - setbits_le32(ctrl, UCTRL_PWR_POL); -#else - clrbits_le32(ctrl, UCTRL_PWR_POL); -#endif + *reg = ehci_readl(status_reg); } /** @@ -314,20 +71,6 @@ int __weak board_usb_phy_mode(int port) return usb_phy_mode(port); } -/** - * board_ehci_hcd_init - set usb vbus voltage - * @port: usb otg port - * - * Target board specific, setup iomux pad to setup supply vbus voltage - * for usb otg port. Machine board file overrides board_ehci_hcd_init - * - * Return: 0 Success - */ -int __weak board_ehci_hcd_init(int port) -{ - return 0; -} - /** * board_ehci_power - enables/disables usb vbus voltage * @port: usb otg port @@ -343,40 +86,21 @@ int __weak board_ehci_power(int port, int on) return 0; } -int ehci_mx6_common_init(struct usb_ehci *ehci, int index) -{ - int ret; - - enable_usboh3_clk(1); - mdelay(1); - - /* Do board specific initialization */ - ret = board_ehci_hcd_init(index); - if (ret) - return ret; - - usb_power_config(index); - usb_oc_config(index); - -#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) - usb_internal_phy_clock_gate(index, 1); - usb_phy_enable(index, ehci); -#endif - - return 0; -} - #if !CONFIG_IS_ENABLED(DM_USB) +static const struct ehci_ops mx6_ehci_ops = { + .powerup_fixup = ehci_mx6_powerup_fixup, +}; + int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { enum usb_init_type type; #if defined(CONFIG_MX6) u32 controller_spacing = 0x200; -#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) +#elif defined(CONFIG_USB_EHCI_MX7) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) u32 controller_spacing = 0x10000; #endif - struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR + + struct usb_ehci *ehci = (struct usb_ehci *)(ulong)(USB_BASE_ADDR + (controller_spacing * index)); int ret; @@ -395,11 +119,13 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (ret) return ret; + ehci_set_controller_priv(index, NULL, &mx6_ehci_ops); + type = board_usb_phy_mode(index); if (hccr && hcor) { - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + + *hccr = (struct ehci_hccr *)((ulong)&ehci->caplength); + *hcor = (struct ehci_hcor *)((ulong)*hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); } @@ -407,6 +133,11 @@ int ehci_hcd_init(int index, enum usb_init_type init, board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); if (type != init) return -ENODEV; + + if (is_mx6dqp() || is_mx6dq() || is_mx6sdl() || + ((is_mx6sl() || is_mx6sx()) && type == USB_INIT_HOST)) + setbits_le32(&ehci->usbmode, SDIS); + if (type == USB_INIT_DEVICE) return 0; @@ -424,11 +155,14 @@ int ehci_hcd_stop(int index) return 0; } #else +#define USB_INIT_UNKNOWN (USB_INIT_DEVICE + 1) + struct ehci_mx6_priv_data { struct ehci_ctrl ctrl; struct usb_ehci *ehci; struct udevice *vbus_supply; enum usb_init_type init_type; + void *__iomem phy_base; int portnr; }; @@ -439,6 +173,12 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) struct usb_ehci *ehci = priv->ehci; int ret; + ret = board_usb_init(priv->portnr, priv->init_type); + if (ret) { + printf("Failed to initialize board for USB\n"); + return ret; + } + ret = ehci_mx6_common_init(priv->ehci, priv->portnr); if (ret) return ret; @@ -455,6 +195,10 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) } #endif + if (is_mx6dqp() || is_mx6dq() || is_mx6sdl() || + ((is_mx6sl() || is_mx6sx()) && type == USB_INIT_HOST)) + setbits_le32(&ehci->usbmode, SDIS); + if (type == USB_INIT_DEVICE) return 0; @@ -468,23 +212,71 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) } static const struct ehci_ops mx6_ehci_ops = { - .init_after_reset = mx6_init_after_reset + .powerup_fixup = ehci_mx6_powerup_fixup, + .init_after_reset = mx6_init_after_reset }; +/** + * board_ehci_usb_phy_mode - override usb phy mode + * @port: usb host/otg port + * + * Target board specific, override usb_phy_mode. + * When usb-otg is used as usb host port, iomux pad usb_otg_id can be + * left disconnected in this case usb_phy_mode will not be able to identify + * the phy mode that usb port is used. + * Machine file overrides board_usb_phy_mode. + * When the extcon property is set in DTB, machine must provide this function, otherwise + * it will default return HOST. + * + * Return: USB_INIT_DEVICE or USB_INIT_HOST + */ +int __weak board_ehci_usb_phy_mode(struct udevice *dev) +{ + return USB_INIT_HOST; +} + static int ehci_usb_phy_mode(struct udevice *dev) { - struct usb_plat *plat = dev_get_plat(dev); - void *__iomem addr = dev_read_addr_ptr(dev); + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); void *__iomem phy_ctrl, *__iomem phy_status; + u32 val; + + if (is_mx6() || is_mx7ulp() || is_imx8()) { + phy_ctrl = (void __iomem *)(priv->phy_base + USBPHY_CTRL); + val = readl(phy_ctrl); + + if (val & USBPHY_CTRL_OTG_ID) + priv->init_type = USB_INIT_DEVICE; + else + priv->init_type = USB_INIT_HOST; + } else if (is_mx7() || is_imx8mm() || is_imx8mn()) { + phy_status = (void __iomem *)(priv->phy_base + + USBNC_PHY_STATUS_OFFSET); + val = readl(phy_status); + + if (val & USBNC_PHYSTATUS_ID_DIG) + priv->init_type = USB_INIT_DEVICE; + else + priv->init_type = USB_INIT_HOST; + } else { + return -EINVAL; + } + + return 0; +} + +static int ehci_get_usb_phy(struct udevice *dev) +{ + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); + void *__iomem addr = (void *__iomem)devfdt_get_addr(dev); const void *blob = gd->fdt_blob; int offset = dev_of_offset(dev), phy_off; - u32 val; /* * About fsl,usbphy, Refer to * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt. */ - if (is_mx6() || is_mx7ulp()) { + if (is_mx6() || is_mx7ulp() || is_imx8()) { phy_off = fdtdec_lookup_phandle(blob, offset, "fsl,usbphy"); @@ -496,22 +288,39 @@ static int ehci_usb_phy_mode(struct udevice *dev) if ((fdt_addr_t)addr == FDT_ADDR_T_NONE) return -EINVAL; - phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL); - val = readl(phy_ctrl); - if (val & USBPHY_CTRL_OTG_ID) - plat->init_type = USB_INIT_DEVICE; - else - plat->init_type = USB_INIT_HOST; - } else if (is_mx7()) { - phy_status = (void __iomem *)(addr + - USBNC_PHY_STATUS_OFFSET); - val = readl(phy_status); + struct udevice __maybe_unused phy_dev; + dev_set_ofnode(&phy_dev, offset_to_ofnode(phy_off)); - if (val & USBNC_PHYSTATUS_ID_DIG) - plat->init_type = USB_INIT_DEVICE; - else - plat->init_type = USB_INIT_HOST; + /* Need to power on the PHY before access it */ +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + struct power_domain pd; + + if (!power_domain_get(&phy_dev, &pd)) { + if (power_domain_on(&pd)) + return -EINVAL; + } +#endif + +#if CONFIG_IS_ENABLED(CLK) + int ret; + struct clk phy_clk; + + ret = clk_get_by_index(&phy_dev, 0, &phy_clk); + if (ret) { + printf("Failed to get phy_clk\n"); + return ret; + } + + ret = clk_enable(&phy_clk); + if (ret) { + printf("Failed to enable phy_clk\n"); + return ret; + } +#endif + priv->phy_base = addr; + } else if (is_mx7() || is_imx8mm() || is_imx8mn()) { + priv->phy_base = addr; } else { return -EINVAL; } @@ -522,22 +331,39 @@ static int ehci_usb_phy_mode(struct udevice *dev) static int ehci_usb_of_to_plat(struct udevice *dev) { struct usb_plat *plat = dev_get_plat(dev); + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); enum usb_dr_mode dr_mode; + const struct fdt_property *extcon; + + extcon = fdt_get_property(gd->fdt_blob, dev_of_offset(dev), + "extcon", NULL); + if (extcon) { + priv->init_type = board_ehci_usb_phy_mode(dev); + goto check_type; + } dr_mode = usb_get_dr_mode(dev_ofnode(dev)); switch (dr_mode) { case USB_DR_MODE_HOST: - plat->init_type = USB_INIT_HOST; + priv->init_type = USB_INIT_HOST; break; case USB_DR_MODE_PERIPHERAL: - plat->init_type = USB_INIT_DEVICE; + priv->init_type = USB_INIT_DEVICE; break; case USB_DR_MODE_OTG: case USB_DR_MODE_UNKNOWN: - return ehci_usb_phy_mode(dev); + priv->init_type = USB_INIT_UNKNOWN; + break; }; +check_type: + if (priv->init_type != USB_INIT_UNKNOWN && priv->init_type != plat->init_type) { + debug("Request USB type is %u, board forced type is %u\n", + plat->init_type, priv->init_type); + return -ENODEV; + } + return 0; } @@ -570,16 +396,17 @@ static int ehci_usb_bind(struct udevice *dev) * With these changes in place, the ad-hoc indexing goes away and * the driver is fully converted to DT probing. */ + u32 controller_spacing; - /* - * FIXME: This cannot work with the new sequence numbers. - * Please complete the DM conversion. - * - * u32 controller_spacing = is_mx7() ? 0x10000 : 0x200; - * fdt_addr_t addr = devfdt_get_addr_index(dev, 0); - * - * dev->req_seq = (addr - USB_BASE_ADDR) / controller_spacing; - */ + if (dev_seq(dev) == -1) { + if (IS_ENABLED(CONFIG_MX6)) + controller_spacing = 0x200; + else + controller_spacing = 0x10000; + fdt_addr_t addr = devfdt_get_addr_index(dev, 0); + + dev->seq_ = (addr - USB_BASE_ADDR) / controller_spacing; + } return 0; } @@ -604,7 +431,13 @@ static int ehci_usb_probe(struct udevice *dev) priv->ehci = ehci; priv->portnr = dev_seq(dev); - priv->init_type = type; + + /* Init usb board level according to the requested init type */ + ret = board_usb_init(priv->portnr, type); + if (ret) { + printf("Failed to initialize board for USB\n"); + return ret; + } #if CONFIG_IS_ENABLED(DM_REGULATOR) ret = device_get_supply_regulator(dev, "vbus-supply", @@ -612,14 +445,30 @@ static int ehci_usb_probe(struct udevice *dev) if (ret) debug("%s: No vbus supply\n", dev->name); #endif + + ret = ehci_get_usb_phy(dev); + if (ret) { + debug("%s: fail to get USB PHY base\n", dev->name); + return ret; + } + ret = ehci_mx6_common_init(ehci, priv->portnr); if (ret) return ret; + /* If the init_type is unknown due to it is not forced in DTB, we use USB ID to detect */ + if (priv->init_type == USB_INIT_UNKNOWN) { + ret = ehci_usb_phy_mode(dev); + if (ret) + return ret; + if (priv->init_type != type) + return -ENODEV; + } + #if CONFIG_IS_ENABLED(DM_REGULATOR) if (priv->vbus_supply) { ret = regulator_set_enable(priv->vbus_supply, - (type == USB_INIT_DEVICE) ? + (priv->init_type == USB_INIT_DEVICE) ? false : true); if (ret && ret != -ENOSYS) { printf("Error enabling VBUS supply (ret=%i)\n", ret); @@ -636,13 +485,25 @@ static int ehci_usb_probe(struct udevice *dev) mdelay(10); - hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - hcor = (struct ehci_hcor *)((uint32_t)hccr + + hccr = (struct ehci_hccr *)((ulong)&ehci->caplength); + hcor = (struct ehci_hcor *)((ulong)hccr + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type); } +int ehci_usb_remove(struct udevice *dev) +{ + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); + struct usb_plat *plat = dev_get_plat(dev); + + ehci_deregister(dev); + + plat->init_type = 0; /* Clean the requested usb type to host mode */ + + return board_usb_cleanup(dev_seq(dev), priv->init_type); +} + static const struct udevice_id mx6_usb_ids[] = { { .compatible = "fsl,imx27-usb" }, { } @@ -655,7 +516,7 @@ U_BOOT_DRIVER(usb_mx6) = { .of_to_plat = ehci_usb_of_to_plat, .bind = ehci_usb_bind, .probe = ehci_usb_probe, - .remove = ehci_deregister, + .remove = ehci_usb_remove, .ops = &ehci_usb_ops, .plat_auto = sizeof(struct usb_plat), .priv_auto = sizeof(struct ehci_mx6_priv_data), diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h index 8e0755423a9..e9e6f2a5518 100644 --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -44,6 +44,7 @@ struct ehci_hcor { #define STS_ASS (1 << 15) #define STS_PSS (1 << 14) #define STS_HALT (1 << 12) +#define STS_IAA (1 << 5) uint32_t or_usbintr; #define INTR_UE (1 << 0) /* USB interrupt enable */ #define INTR_UEE (1 << 1) /* USB error interrupt enable */ diff --git a/drivers/usb/host/xhci-imx8.c b/drivers/usb/host/xhci-imx8.c new file mode 100644 index 00000000000..dbe6f23c803 --- /dev/null +++ b/drivers/usb/host/xhci-imx8.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + * NXP i.MX8 USB HOST xHCI Controller (Cadence IP) + * + * Author: Peter Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +/* Host registers */ +#define HCIVERSION_CAPLENGTH 0x10000 +#define USBSTS 0x10084 + +/* None-core registers */ +#define USB3_CORE_CTRL1 0x00 +#define USB3_CORE_STATUS 0x0c +#define USB3_SSPHY_STATUS 0x4c + +/* USB3_CORE_CTRL1 */ +#define ALL_SW_RESET 0xfc000000 +#define MODE_STRAP_MASK 0x7 +#define PHYAHB_SW_RESET BIT(26) +#define OC_DISABLE BIT(9) +#define HOST_MODE BIT(1) +#define OTG_MODE BIT(0) + +/* USB3_CORE_STATUS */ +#define HOST_POWER_ON_READY BIT(12) + +/* USBSTS */ +#define CONTROLLER_NOT_READY BIT(11) + +/* USB3_SSPHY_STATUS */ +#define CLK_VLD 0xf0000000 + +struct xhci_imx8_data { + void __iomem *usb3_ctrl_base; + void __iomem *usb3_core_base; + struct clk_bulk clks; + struct phy phy; +}; + +static struct xhci_imx8_data imx8_data; + +static int imx8_xhci_init(void) +{ + int ret; + + writel(CLK_VLD, imx8_data.usb3_ctrl_base + USB3_SSPHY_STATUS); + ret = wait_for_bit_le32(imx8_data.usb3_ctrl_base + USB3_SSPHY_STATUS, + CLK_VLD, true, 100, false); + if (ret) { + printf("clkvld is incorrect\n"); + return ret; + } + + clrsetbits_le32(imx8_data.usb3_ctrl_base + USB3_CORE_CTRL1, + MODE_STRAP_MASK, HOST_MODE | OC_DISABLE); + clrbits_le32(imx8_data.usb3_ctrl_base + USB3_CORE_CTRL1, + PHYAHB_SW_RESET); + generic_phy_init(&imx8_data.phy); + + /* clear all sw_rst */ + clrbits_le32(imx8_data.usb3_ctrl_base + USB3_CORE_CTRL1, ALL_SW_RESET); + + debug("wait xhci_power_on_ready\n"); + ret = wait_for_bit_le32(imx8_data.usb3_ctrl_base + USB3_CORE_STATUS, + HOST_POWER_ON_READY, true, 100, false); + if (ret) { + printf("wait xhci_power_on_ready timeout\n"); + return ret; + } + debug("xhci_power_on_ready\n"); + + debug("waiting CNR\n"); + ret = wait_for_bit_le32(imx8_data.usb3_core_base + USBSTS, + CONTROLLER_NOT_READY, false, 100, false); + if (ret) { + printf("wait CNR timeout\n"); + return ret; + } + debug("check CNR has finished\n"); + + return 0; +} + +static void imx8_xhci_reset(void) +{ + /* Set CORE ctrl to default value, that all rst are hold */ + writel(ALL_SW_RESET | OTG_MODE, + imx8_data.usb3_ctrl_base + USB3_CORE_CTRL1); +} + +static int xhci_imx8_clk_init(struct udevice *dev) +{ + int ret; + + ret = clk_get_bulk(dev, &imx8_data.clks); + if (ret) + return ret; + + ret = clk_enable_bulk(&imx8_data.clks); + if (ret) + return ret; + + return 0; +} + +static inline void xhci_imx8_get_reg_addr(struct udevice *dev) +{ + imx8_data.usb3_ctrl_base = + (void __iomem *)devfdt_get_addr_name(dev, "none-core"); + imx8_data.usb3_core_base = + (void __iomem *)devfdt_get_addr_name(dev, "otg"); + +} + +static int xhci_imx8_probe(struct udevice *dev) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + struct udevice usbotg_dev; + struct power_domain pd; + int usbotg_off; + int ret = 0; + int len; + + usbotg_off = fdtdec_lookup_phandle(gd->fdt_blob, + dev_of_offset(dev), + "cdns3,usb"); + if (usbotg_off < 0) + return -EINVAL; + + dev_set_ofnode(&usbotg_dev, offset_to_ofnode(usbotg_off)); + usbotg_dev.parent = dev->parent; + xhci_imx8_get_reg_addr(&usbotg_dev); + +#if CONFIG_IS_ENABLED(POWER_DOMAIN) + if (!power_domain_get(&usbotg_dev, &pd)) { + ret = power_domain_on(&pd); + if (ret) + return ret; + } +#endif + + ret = generic_phy_get_by_index(&usbotg_dev, 0, &imx8_data.phy); + if (ret && ret != -ENOENT) { + printf("Failed to get USB PHY for %s\n", dev->name); + return ret; + } + + ret = board_usb_init(dev_seq(dev), USB_INIT_HOST); + if (ret != 0) { + printf("Failed to initialize board for USB\n"); + return ret; + } + +#if CONFIG_IS_ENABLED(CLK) + xhci_imx8_clk_init(&usbotg_dev); +#else + init_clk_usb3(dev_seq(dev)); +#endif + + imx8_xhci_init(); + + hccr = (struct xhci_hccr *)(imx8_data.usb3_core_base + + HCIVERSION_CAPLENGTH); + len = HC_LENGTH(xhci_readl(&hccr->cr_capbase)); + hcor = (struct xhci_hcor *)((uintptr_t)hccr + len); + printf("XHCI-imx8 init hccr 0x%p and hcor 0x%p hc_length %d\n", + (uint32_t *)hccr, (uint32_t *)hcor, len); + + return xhci_register(dev, hccr, hcor); +} + +static int xhci_imx8_remove(struct udevice *dev) +{ + int ret = xhci_deregister(dev); + + if (!ret) + imx8_xhci_reset(); + +#if CONFIG_IS_ENABLED(CLK) + clk_release_bulk(&imx8_data.clks); +#endif + if (generic_phy_valid(&imx8_data.phy)) + device_remove(imx8_data.phy.dev, DM_REMOVE_NORMAL); + + board_usb_cleanup(dev_seq(dev), USB_INIT_HOST); + + return ret; +} + +static const struct udevice_id xhci_usb_ids[] = { + { .compatible = "Cadence,usb3-host", }, + { } +}; + +U_BOOT_DRIVER(xhci_imx8) = { + .name = "xhci_imx8", + .id = UCLASS_USB, + .of_match = xhci_usb_ids, + .probe = xhci_imx8_probe, + .remove = xhci_imx8_remove, + .ops = &xhci_usb_ops, + .plat_auto = sizeof(struct usb_plat), + .priv_auto = sizeof(struct xhci_ctrl), + .flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_OS_PREPARE, +}; diff --git a/drivers/usb/host/xhci-imx8m.c b/drivers/usb/host/xhci-imx8m.c new file mode 100644 index 00000000000..1681a3a715f --- /dev/null +++ b/drivers/usb/host/xhci-imx8m.c @@ -0,0 +1,242 @@ +/* + * Copyright 2017 NXP + * + * FSL i.MX8M USB HOST xHCI Controller + * + * Author: Jun Li + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Declare global data pointer */ +DECLARE_GLOBAL_DATA_PTR; + +#define USBMIX_PHY_OFFSET 0xF0040 + +#define PHY_CTRL0_REF_SSP_EN BIT(2) + +#define PHY_CTRL1_RESET BIT(0) +#define PHY_CTRL1_ATERESET BIT(3) +#define PHY_CTRL1_VDATSRCENB0 BIT(19) +#define PHY_CTRL1_VDATDETENB0 BIT(20) + +#define PHY_CTRL2_TXENABLEN0 BIT(8) + +struct imx8m_usbmix { + u32 phy_ctrl0; + u32 phy_ctrl1; + u32 phy_ctrl2; + u32 phy_ctrl3; + u32 phy_ctrl4; + u32 phy_ctrl5; + u32 phy_ctrl6; +}; + +struct imx8m_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; + struct imx8m_usbmix *usbmix_reg; +}; + +struct imx8m_usbctrl_data { + u32 usb_id; + unsigned long ctr_addr; +}; +static struct imx8m_xhci imx8m_xhci; +static struct imx8m_usbctrl_data ctr_data[] = { + {0, USB1_BASE_ADDR}, + {1, USB2_BASE_ADDR}, +}; + +#ifdef CONFIG_IMX8MP +#define HSIO_GPR_BASE (0x32F10000U) +#define HSIO_GPR_REG_0 (HSIO_GPR_BASE) +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT (1) +#define HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN (0x1U << HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN_SHIFT) +#endif + +static void imx8m_usb_phy_init(struct imx8m_usbmix *usbmix_reg) +{ + u32 reg; + +#ifdef CONFIG_IMX8MP + /* enable usb clock via hsio gpr */ + reg = readl(HSIO_GPR_REG_0); + reg |= HSIO_GPR_REG_0_USB_CLOCK_MODULE_EN; + writel(reg, HSIO_GPR_REG_0); + + /* USB3.0 PHY signal fsel for 24M ref */ + reg = readl(&usbmix_reg->phy_ctrl0); + reg = (reg & 0xfffff81f) | (0x2a<<5); + writel(reg, &usbmix_reg->phy_ctrl0); + + reg = readl(&usbmix_reg->phy_ctrl6); + reg &=~0x1; + writel(reg, &usbmix_reg->phy_ctrl6); +#endif + + reg = readl(&usbmix_reg->phy_ctrl1); + reg &= ~(PHY_CTRL1_VDATSRCENB0 | PHY_CTRL1_VDATDETENB0); + reg |= PHY_CTRL1_RESET | PHY_CTRL1_ATERESET; + writel(reg, &usbmix_reg->phy_ctrl1); + + reg = readl(&usbmix_reg->phy_ctrl0); + reg |= PHY_CTRL0_REF_SSP_EN; + writel(reg, &usbmix_reg->phy_ctrl0); + + reg = readl(&usbmix_reg->phy_ctrl2); + reg |= PHY_CTRL2_TXENABLEN0; + writel(reg, &usbmix_reg->phy_ctrl2); + + reg = readl(&usbmix_reg->phy_ctrl1); + reg &= ~(PHY_CTRL1_RESET | PHY_CTRL1_ATERESET); + writel(reg, &usbmix_reg->phy_ctrl1); +} + +static void imx8m_xhci_set_suspend_clk(struct dwc3 *dwc3_reg) +{ + u32 reg; + + /* Set suspend_clk to be 32KHz */ + reg = readl(&dwc3_reg->g_ctl); + reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); + reg |= DWC3_GCTL_PWRDNSCALE(2); + + writel(reg, &dwc3_reg->g_ctl); +} + +static int imx8m_xhci_core_init(struct imx8m_xhci *imx8m_xhci) +{ + int ret = 0; + + imx8m_usb_phy_init(imx8m_xhci->usbmix_reg); + + ret = dwc3_core_init(imx8m_xhci->dwc3_reg); + if (ret) { + debug("%s:failed to initialize core\n", __func__); + return ret; + } + + imx8m_xhci_set_suspend_clk(imx8m_xhci->dwc3_reg); + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(imx8m_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + /* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */ + dwc3_set_fladj(imx8m_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT); + + return ret; +} + +#ifdef CONFIG_DM_USB +static int xhci_imx8m_probe(struct udevice *dev) +{ + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + struct imx8m_xhci *ctx = &imx8m_xhci; + int ret = 0; + + ctx->hcd = (struct xhci_hccr *)(ctr_data[dev_seq(dev)].ctr_addr); + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + ctx->usbmix_reg = (struct imx8m_usbmix *)((char *)(ctx->hcd) + + USBMIX_PHY_OFFSET); + + ret = board_usb_init(ctr_data[dev_seq(dev)].usb_id, USB_INIT_HOST); + if (ret != 0) { + imx8m_usb_power(ctr_data[dev_seq(dev)].usb_id, false); + puts("Failed to initialize board for imx8m USB\n"); + return ret; + } + + ret = imx8m_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize imx8m xhci\n"); + return ret; + } + + hccr = (struct xhci_hccr *)ctx->hcd; + hcor = (struct xhci_hcor *)((uintptr_t) hccr + + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); + + debug("imx8m-xhci: init hccr %lx and hcor %lx hc_length %lx\n", + (uintptr_t)hccr, (uintptr_t)hcor, + (uintptr_t)HC_LENGTH(xhci_readl(&(hccr)->cr_capbase))); + + return xhci_register(dev, hccr, hcor); +} + +static int xhci_imx8m_remove(struct udevice *dev) +{ + int ret = xhci_deregister(dev); + + board_usb_cleanup(dev_seq(dev), USB_INIT_HOST); + + return ret; +} + +static const struct udevice_id xhci_usb_ids[] = { + { .compatible = "fsl,imx8mq-dwc3", }, + { } +}; + +U_BOOT_DRIVER(xhci_imx8m) = { + .name = "xhci_imx8m", + .id = UCLASS_USB, + .of_match = xhci_usb_ids, + .probe = xhci_imx8m_probe, + .remove = xhci_imx8m_remove, + .ops = &xhci_usb_ops, + .plat_auto = sizeof(struct usb_plat), + .priv_auto = sizeof(struct xhci_ctrl), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +#else +int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) +{ + struct imx8m_xhci *ctx = &imx8m_xhci; + int ret = 0; + + ctx->hcd = (struct xhci_hccr *)(ctr_data[index].ctr_addr); + ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET); + ctx->usbmix_reg = (struct imx8m_usbmix *)((char *)(ctx->hcd) + + USBMIX_PHY_OFFSET); + + ret = board_usb_init(ctr_data[index].usb_id, USB_INIT_HOST); + if (ret != 0) { + imx8m_usb_power(ctr_data[index].usb_id, false); + puts("Failed to initialize board for imx8m USB\n"); + return ret; + } + + ret = imx8m_xhci_core_init(ctx); + if (ret < 0) { + puts("Failed to initialize imx8m xhci\n"); + return ret; + } + + *hccr = (struct xhci_hccr *)ctx->hcd; + *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + debug("imx8m-xhci: init hccr %lx and hcor %lx hc_length %lx\n", + (uintptr_t)*hccr, (uintptr_t)*hcor, + (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase))); + + return ret; +} + +void xhci_hcd_stop(int index) +{ + board_usb_cleanup(ctr_data[index].usb_id, USB_INIT_HOST); +} +#endif diff --git a/drivers/usb/imx/Makefile b/drivers/usb/imx/Makefile new file mode 100644 index 00000000000..30c06b7bf83 --- /dev/null +++ b/drivers/usb/imx/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2019 NXP +# + +obj-$(CONFIG_USB_EHCI_MX6) += usb-mx6-common.o +obj-$(CONFIG_USB_EHCI_MX7) += usb-mx6-common.o +obj-$(CONFIG_CI_UDC) += usb-mx6-common.o diff --git a/drivers/usb/imx/usb-mx6-common.c b/drivers/usb/imx/usb-mx6-common.c new file mode 100644 index 00000000000..d2dd715eaf7 --- /dev/null +++ b/drivers/usb/imx/usb-mx6-common.c @@ -0,0 +1,396 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2009 Daniel Mack + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define USB_OTGREGS_OFFSET 0x000 +#define USB_H1REGS_OFFSET 0x200 +#define USB_H2REGS_OFFSET 0x400 +#define USB_H3REGS_OFFSET 0x600 +#define USB_OTHERREGS_OFFSET 0x800 + +#define USB_H1_CTRL_OFFSET 0x04 + +#define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000 +#define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000 + +#define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000 +#define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000 +#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000 +#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040 + +#define USBNC_OFFSET 0x200 +#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ +#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */ +#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ +#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ + +#define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) +#define PLL_USB_PWR_MASK (0x01 << 12) +#define PLL_USB_ENABLE_MASK (0x01 << 13) +#define PLL_USB_BYPASS_MASK (0x01 << 16) +#define PLL_USB_REG_ENABLE_MASK (0x01 << 21) +#define PLL_USB_DIV_SEL_MASK (0x07 << 22) +#define PLL_USB_LOCK_MASK (0x01 << 31) + +/* USBCMD */ +#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */ +#define UCMD_RESET (1 << 1) /* controller reset */ + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) +static const ulong phy_bases[] = { + USB_PHY0_BASE_ADDR, +#if defined(USB_PHY1_BASE_ADDR) + USB_PHY1_BASE_ADDR, +#endif +}; + +static void usb_internal_phy_clock_gate(int index, int on) +{ + void __iomem *phy_reg; + + if (index >= ARRAY_SIZE(phy_bases)) + return; + + phy_reg = (void __iomem *)phy_bases[index]; + phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET; + writel(USBPHY_CTRL_CLKGATE, phy_reg); +} + +static void usb_power_config(int index) +{ + if (index >= ARRAY_SIZE(phy_bases)) + return; + +#if defined(CONFIG_MX7ULP) + struct usbphy_regs __iomem *usbphy = + (struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR; + + writel(ANADIG_USB2_CHRG_DETECT_EN_B | + ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, + &usbphy->usb1_chrg_detect); + + scg_enable_usb_pll(true); + +#elif defined(CONFIG_IMX8) + + + struct usbphy_regs __iomem *usbphy = (struct usbphy_regs __iomem *)phy_bases[index]; + + int timeout = 1000000; + + writel(ANADIG_USB2_CHRG_DETECT_EN_B | + ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, + &usbphy->usb1_chrg_detect); + + if (!(readl(&usbphy->usb1_pll_480_ctrl) & PLL_USB_LOCK_MASK)) { + + /* Enable the regulator first */ + writel(PLL_USB_REG_ENABLE_MASK, + &usbphy->usb1_pll_480_ctrl_set); + + /* Wait at least 25us */ + udelay(25); + + /* Enable the power */ + writel(PLL_USB_PWR_MASK, &usbphy->usb1_pll_480_ctrl_set); + + /* Wait lock */ + while (timeout--) { + if (readl(&usbphy->usb1_pll_480_ctrl) & + PLL_USB_LOCK_MASK) + break; + udelay(10); + } + + if (timeout <= 0) { + /* If timeout, we power down the pll */ + writel(PLL_USB_PWR_MASK, + &usbphy->usb1_pll_480_ctrl_clr); + return; + } + } + + /* Clear the bypass */ + writel(PLL_USB_BYPASS_MASK, &usbphy->usb1_pll_480_ctrl_clr); + + /* Enable the PLL clock out to USB */ + writel((PLL_USB_EN_USB_CLKS_MASK | PLL_USB_ENABLE_MASK), + &usbphy->usb1_pll_480_ctrl_set); + +#else + struct anatop_regs __iomem *anatop = + (struct anatop_regs __iomem *)ANATOP_BASE_ADDR; + void __iomem *chrg_detect; + void __iomem *pll_480_ctrl_clr; + void __iomem *pll_480_ctrl_set; + + switch (index) { + case 0: + chrg_detect = &anatop->usb1_chrg_detect; + pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr; + pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set; + break; + case 1: + chrg_detect = &anatop->usb2_chrg_detect; + pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr; + pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set; + break; + default: + return; + } + /* + * Some phy and power's special controls + * 1. The external charger detector needs to be disabled + * or the signal at DP will be poor + * 2. The PLL's power and output to usb + * is totally controlled by IC, so the Software only needs + * to enable them at initializtion. + */ + writel(ANADIG_USB2_CHRG_DETECT_EN_B | + ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B, + chrg_detect); + + writel(ANADIG_USB2_PLL_480_CTRL_BYPASS, + pll_480_ctrl_clr); + + writel(ANADIG_USB2_PLL_480_CTRL_ENABLE | + ANADIG_USB2_PLL_480_CTRL_POWER | + ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS, + pll_480_ctrl_set); + +#endif +} + +/* Return 0 : host node, <>0 : device mode */ +static int usb_phy_enable(int index, struct usb_ehci *ehci) +{ + void __iomem *phy_reg; + void __iomem *phy_ctrl; + void __iomem *usb_cmd; + int ret; + + if (index >= ARRAY_SIZE(phy_bases)) + return 0; + + phy_reg = (void __iomem *)phy_bases[index]; + phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); + usb_cmd = (void __iomem *)&ehci->usbcmd; + + /* Stop then Reset */ + clrbits_le32(usb_cmd, UCMD_RUN_STOP); + ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false); + if (ret) + return ret; + + setbits_le32(usb_cmd, UCMD_RESET); + ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false); + if (ret) + return ret; + + /* Reset USBPHY module */ + setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); + udelay(10); + + /* Remove CLKGATE and SFTRST */ + clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); + udelay(10); + + /* Power up the PHY */ + writel(0, phy_reg + USBPHY_PWD); + /* enable FS/LS device */ + setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | + USBPHY_CTRL_ENUTMILEVEL3); + + return 0; +} + +int usb_phy_mode(int port) +{ + void __iomem *phy_reg; + void __iomem *phy_ctrl; + u32 val; + + if (port >= ARRAY_SIZE(phy_bases)) + return USB_INIT_HOST; + + phy_reg = (void __iomem *)phy_bases[port]; + phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); + + val = readl(phy_ctrl); + + if (val & USBPHY_CTRL_OTG_ID) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; +} + +#if defined(CONFIG_MX7ULP) +struct usbnc_regs { + u32 ctrl1; + u32 ctrl2; + u32 reserve0[2]; + u32 hsic_ctrl; +}; +#elif defined(CONFIG_IMX8) +struct usbnc_regs { + u32 ctrl1; + u32 ctrl2; + u32 reserve1[10]; + u32 phy_cfg1; + u32 phy_cfg2; + u32 reserve2; + u32 phy_status; + u32 reserve3[4]; + u32 adp_cfg1; + u32 adp_cfg2; + u32 adp_status; +}; +#else +/* Base address for this IP block is 0x02184800 */ +struct usbnc_regs { + u32 ctrl[4]; /* otg/host1-3 */ + u32 uh2_hsic_ctrl; + u32 uh3_hsic_ctrl; + u32 otg_phy_ctrl_0; + u32 uh1_phy_ctrl_0; +}; +#endif + +#elif defined(CONFIG_USB_EHCI_MX7) +struct usbnc_regs { + u32 ctrl1; + u32 ctrl2; + u32 reserve1[10]; + u32 phy_cfg1; + u32 phy_cfg2; + u32 reserve2; + u32 phy_status; + u32 reserve3[4]; + u32 adp_cfg1; + u32 adp_cfg2; + u32 adp_status; +}; + +static void usb_power_config(int index) +{ + struct usbnc_regs *usbnc = (struct usbnc_regs *)(ulong)(USB_BASE_ADDR + + (0x10000 * index) + USBNC_OFFSET); + void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); + + /* + * Clear the ACAENB to enable usb_otg_id detection, + * otherwise it is the ACA detection enabled. + */ + clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); +} + +int usb_phy_mode(int port) +{ + struct usbnc_regs *usbnc = (struct usbnc_regs *)(ulong)(USB_BASE_ADDR + + (0x10000 * port) + USBNC_OFFSET); + void __iomem *status = (void __iomem *)(&usbnc->phy_status); + u32 val; + + val = readl(status); + + if (val & USBNC_PHYSTATUS_ID_DIG) + return USB_INIT_DEVICE; + else + return USB_INIT_HOST; +} +#endif + +static void usb_oc_config(int index) +{ +#if defined(CONFIG_MX6) + struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + + USB_OTHERREGS_OFFSET); + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]); +#elif defined(CONFIG_USB_EHCI_MX7) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) + struct usbnc_regs *usbnc = (struct usbnc_regs *)(ulong)(USB_BASE_ADDR + + (0x10000 * index) + USBNC_OFFSET); + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); +#endif + +#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2 + /* mx6qarm2 seems to required a different setting*/ + clrbits_le32(ctrl, UCTRL_OVER_CUR_POL); +#else + setbits_le32(ctrl, UCTRL_OVER_CUR_POL); +#endif + + setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); + + /* Set power polarity to high active */ +#ifdef CONFIG_MXC_USB_OTG_HACTIVE + setbits_le32(ctrl, UCTRL_PWR_POL); +#else + clrbits_le32(ctrl, UCTRL_PWR_POL); +#endif +} + +/** + * board_ehci_hcd_init - set usb vbus voltage + * @port: usb otg port + * + * Target board specific, setup iomux pad to setup supply vbus voltage + * for usb otg port. Machine board file overrides board_ehci_hcd_init + * + * Return: 0 Success + */ +int __weak board_ehci_hcd_init(int port) +{ + return 0; +} + +int ehci_mx6_common_init(struct usb_ehci *ehci, int index) +{ + int ret; + u32 portsc; + + enable_usboh3_clk(1); + mdelay(1); + + portsc = readl(&ehci->portsc); + if (portsc & PORT_PTS_PHCD) { + debug("suspended: portsc %x, enabled it.\n", portsc); + clrbits_le32(&ehci->portsc, PORT_PTS_PHCD); + } + + /* Do board specific initialization */ + ret = board_ehci_hcd_init(index); + if (ret) + return ret; + + usb_power_config(index); + usb_oc_config(index); + +#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8) + usb_internal_phy_clock_gate(index, 1); + usb_phy_enable(index, ehci); +#endif + + return 0; +} diff --git a/drivers/usb/musb-new/ti-musb.c b/drivers/usb/musb-new/ti-musb.c index 91042935b07..d90e5bfaac8 100644 --- a/drivers/usb/musb-new/ti-musb.c +++ b/drivers/usb/musb-new/ti-musb.c @@ -233,7 +233,7 @@ static int ti_musb_peripheral_of_to_plat(struct udevice *dev) } #endif -int dm_usb_gadget_handle_interrupts(struct udevice *dev) +static int ti_musb_peripheral_handle_interrupts(struct udevice *dev) { struct ti_musb_peripheral *priv = dev_get_priv(dev); @@ -278,6 +278,7 @@ U_BOOT_DRIVER(ti_musb_peripheral) = { .probe = ti_musb_peripheral_probe, .remove = ti_musb_peripheral_remove, .ops = &musb_usb_ops, + .handle_interrupts = ti_musb_peripheral_handle_interrupts, .plat_auto = sizeof(struct ti_musb_plat), .priv_auto = sizeof(struct ti_musb_peripheral), .flags = DM_FLAG_PRE_RELOC, diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 667157c2e97..a13d90f3d1b 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -430,6 +430,24 @@ config VIDEO_LCD_RAYDIUM_RM68200 Say Y here if you want to enable support for Raydium RM68200 720x1280 DSI video mode panel. +config VIDEO_LCD_RAYDIUM_RM67191 + bool "RM67191 DSI LCD panel support" + depends on DM_VIDEO + select VIDEO_MIPI_DSI + default n + help + Say Y here if you want to enable support for Raydium RM68200 + 1080x1920 DSI video mode panel. + +config VIDEO_LCD_STARTEK_ILI9881C + tristate "Startek ILI9881C-based panels" + depends on DM_VIDEO + select VIDEO_MIPI_DSI + default n + help + Say Y if you want to enable support for panels based on the + Startek panel with an ILI9881c controller. + config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" default n @@ -658,7 +676,7 @@ config VIDEO_TEGRA124 source "drivers/video/bridge/Kconfig" -source "drivers/video/imx/Kconfig" +source "drivers/video/nxp/Kconfig" config VIDEO_NX bool "Enable video support on Nexell SoC" @@ -686,6 +704,18 @@ config VIDEO model. Video drivers typically provide a colour text console and cursor. +config MXC_EPDC + bool "i.MX EPDC support" + depends on LCD && (MX7 || MX6) + help + This enable the E-ink EPD panel controller support for i.MX processors + +config WAVEFORM_BUF_SIZE + bool "The buffer size allocated for i.MX EPDC waveform file" + depends on MXC_EPDC + help + Set the buffer size for loading waveform file. + config CFB_CONSOLE bool "Enable colour frame buffer console" depends on VIDEO || ARCH_OMAP2PLUS @@ -1002,4 +1032,29 @@ config VIDEO_VCXK This enables VCXK driver which can be used with VC2K, VC4K and VC8K devices on various boards from BuS Elektronik GmbH. +config VIDEO_LINK + bool "Enable video link framework support" + depends on DM_VIDEO + help + This option enables a video link framework basing on port-endpoint graph + to connect video components. + +config VIDEO_IT6263_BRIDGE + bool "ITE6263 LVDS to HDMI connector" + depends on DM_VIDEO + select VIDEO_BRIDGE + default n + help + Say Y here if you want to enable support for ITE IT6263 + LVDS to HDMI connector, currently only support 1280x720P. + +config VIDEO_ADV7535 + bool "ADV7535 MIPI DSI to HDMI connector" + depends on DM_VIDEO + select VIDEO_MIPI_DSI + default n + help + Say Y here if you want to enable support for ADI ADV7535 + DSI to HDMI connector, currently only support 1920x1080. + endmenu diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 933f06e9d8d..c48cde47607 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_DM_VIDEO) += video_bmp.o obj-$(CONFIG_PANEL) += panel-uclass.o obj-$(CONFIG_PANEL_HX8238D) += hx8238d.o obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o +obj-$(CONFIG_VIDEO_LINK) += video_link.o endif obj-${CONFIG_EXYNOS_FB} += exynos/ @@ -50,16 +51,19 @@ obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o obj-$(CONFIG_VIDEO_EFI) += efi.o obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o -obj-$(CONFIG_VIDEO_IPUV3) += imx/ obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o +obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM67191) += raydium-rm67191.o +obj-$(CONFIG_VIDEO_LCD_STARTEK_ILI9881C) += startek-ili9881c.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_LCD_TDO_TL070WSH30) += tdo-tl070wsh30.o +obj-$(CONFIG_VIDEO_ADV7535) += adv7535.o obj-${CONFIG_VIDEO_MESON} += meson/ obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_dsi.o +obj-$(CONFIG_VIDEO_IT6263_BRIDGE) += it6263_bridge.o obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o @@ -72,6 +76,12 @@ obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o obj-$(CONFIG_VIDEO_VESA) += vesa.o obj-$(CONFIG_VIDEO_SEPS525) += seps525.o +obj-$(CONFIG_MXC_EPDC) += mxc_epdc_fb.o +obj-$(CONFIG_VIDEO_VADC) += mxc_vadc.o +obj-$(CONFIG_VIDEO_CSI) += mxc_csi.o +obj-$(CONFIG_VIDEO_PXP) += mxc_pxp.o +obj-$(CONFIG_VIDEO_GIS) += mxc_gis.o obj-y += bridge/ obj-y += sunxi/ +obj-y += nxp/ diff --git a/drivers/video/adv7535.c b/drivers/video/adv7535.c new file mode 100644 index 00000000000..48df72e671c --- /dev/null +++ b/drivers/video/adv7535.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +struct adv7535_priv { + unsigned int addr; + unsigned int addr_cec; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; + struct udevice *cec_dev; +}; + +static const struct display_timing default_timing = { + .pixelclock.typ = 148500000, + .hactive.typ = 1920, + .hfront_porch.typ = 88, + .hback_porch.typ = 148, + .hsync_len.typ = 44, + .vactive.typ = 1080, + .vfront_porch.typ = 4, + .vback_porch.typ = 36, + .vsync_len.typ = 5, +}; + +static int adv7535_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data) +{ + uint8_t valb; + int err; + + if (mask != 0xff) { + err = dm_i2c_read(dev, addr, &valb, 1); + if (err) + return err; + + valb &= ~mask; + valb |= data; + } else { + valb = data; + } + + err = dm_i2c_write(dev, addr, &valb, 1); + return err; +} + +static int adv7535_i2c_reg_read(struct udevice *dev, uint8_t addr, uint8_t *data) +{ + uint8_t valb; + int err; + + err = dm_i2c_read(dev, addr, &valb, 1); + if (err) + return err; + + *data = (int)valb; + return 0; +} + +static int adv7535_enable(struct udevice *dev) +{ + struct adv7535_priv *priv = dev_get_priv(dev); + uint8_t val; + + adv7535_i2c_reg_read(dev, 0x00, &val); + debug("Chip revision: 0x%x (expected: 0x14)\n", val); + adv7535_i2c_reg_read(priv->cec_dev, 0x00, &val); + debug("Chip ID MSB: 0x%x (expected: 0x75)\n", val); + adv7535_i2c_reg_read(priv->cec_dev, 0x01, &val); + debug("Chip ID LSB: 0x%x (expected: 0x33)\n", val); + + /* Power */ + adv7535_i2c_reg_write(dev, 0x41, 0xff, 0x10); + /* Initialisation (Fixed) Registers */ + adv7535_i2c_reg_write(dev, 0x16, 0xff, 0x20); + adv7535_i2c_reg_write(dev, 0x9A, 0xff, 0xE0); + adv7535_i2c_reg_write(dev, 0xBA, 0xff, 0x70); + adv7535_i2c_reg_write(dev, 0xDE, 0xff, 0x82); + adv7535_i2c_reg_write(dev, 0xE4, 0xff, 0x40); + adv7535_i2c_reg_write(dev, 0xE5, 0xff, 0x80); + adv7535_i2c_reg_write(priv->cec_dev, 0x15, 0xff, 0xD0); + adv7535_i2c_reg_write(priv->cec_dev, 0x17, 0xff, 0xD0); + adv7535_i2c_reg_write(priv->cec_dev, 0x24, 0xff, 0x20); + adv7535_i2c_reg_write(priv->cec_dev, 0x57, 0xff, 0x11); + adv7535_i2c_reg_write(priv->cec_dev, 0x05, 0xff, 0xc8); + + /* 4 x DSI Lanes */ + adv7535_i2c_reg_write(priv->cec_dev, 0x1C, 0xff, 0x40); + + /* DSI Pixel Clock Divider */ + //adv7535_i2c_reg_write(priv->cec_dev, 0x16, 0xff, 0x0); + adv7535_i2c_reg_write(priv->cec_dev, 0x16, 0xff, 0x18); + + /* Enable Internal Timing Generator */ + adv7535_i2c_reg_write(priv->cec_dev, 0x27, 0xff, 0xCB); + /* 1920 x 1080p 60Hz */ + adv7535_i2c_reg_write(priv->cec_dev, 0x28, 0xff, 0x89); /* total width */ + adv7535_i2c_reg_write(priv->cec_dev, 0x29, 0xff, 0x80); /* total width */ + adv7535_i2c_reg_write(priv->cec_dev, 0x2A, 0xff, 0x02); /* hsync */ + adv7535_i2c_reg_write(priv->cec_dev, 0x2B, 0xff, 0xC0); /* hsync */ + adv7535_i2c_reg_write(priv->cec_dev, 0x2C, 0xff, 0x05); /* hfp */ + adv7535_i2c_reg_write(priv->cec_dev, 0x2D, 0xff, 0x80); /* hfp */ + adv7535_i2c_reg_write(priv->cec_dev, 0x2E, 0xff, 0x09); /* hbp */ + adv7535_i2c_reg_write(priv->cec_dev, 0x2F, 0xff, 0x40); /* hbp */ + + adv7535_i2c_reg_write(priv->cec_dev, 0x30, 0xff, 0x46); /* total height */ + adv7535_i2c_reg_write(priv->cec_dev, 0x31, 0xff, 0x50); /* total height */ + adv7535_i2c_reg_write(priv->cec_dev, 0x32, 0xff, 0x00); /* vsync */ + adv7535_i2c_reg_write(priv->cec_dev, 0x33, 0xff, 0x50); /* vsync */ + adv7535_i2c_reg_write(priv->cec_dev, 0x34, 0xff, 0x00); /* vfp */ + adv7535_i2c_reg_write(priv->cec_dev, 0x35, 0xff, 0x40); /* vfp */ + adv7535_i2c_reg_write(priv->cec_dev, 0x36, 0xff, 0x02); /* vbp */ + adv7535_i2c_reg_write(priv->cec_dev, 0x37, 0xff, 0x40); /* vbp */ + + /* Reset Internal Timing Generator */ + adv7535_i2c_reg_write(priv->cec_dev, 0x27, 0xff, 0xCB); + adv7535_i2c_reg_write(priv->cec_dev, 0x27, 0xff, 0x8B); + adv7535_i2c_reg_write(priv->cec_dev, 0x27, 0xff, 0xCB); + + /* HDMI Output */ + adv7535_i2c_reg_write(dev, 0xAF, 0xff, 0x16); + /* AVI Infoframe - RGB - 16-9 Aspect Ratio */ + adv7535_i2c_reg_write(dev, 0x55, 0xff, 0x10); + //adv7535_i2c_reg_write(dev, 0x55, 0xff, 0x02); + adv7535_i2c_reg_write(dev, 0x56, 0xff, 0x28); + //adv7535_i2c_reg_write(dev, 0x56, 0xff, 0x0); + + /* GC Packet Enable */ + adv7535_i2c_reg_write(dev, 0x40, 0xff, 0x80); + //adv7535_i2c_reg_write(dev, 0x40, 0xff, 0x0); + /* GC Colour Depth - 24 Bit */ + adv7535_i2c_reg_write(dev, 0x4C, 0xff, 0x04); + //adv7535_i2c_reg_write(dev, 0x4C, 0xff, 0x0); + /* Down Dither Output Colour Depth - 8 Bit (default) */ + adv7535_i2c_reg_write(dev, 0x49, 0xff, 0x00); + + /* set low refresh 1080p30 */ + adv7535_i2c_reg_write(dev, 0x4A, 0xff, 0x80); /*should be 0x80 for 1080p60 and 0x8c for 1080p30*/ + + /* HDMI Output Enable */ + //adv7535_i2c_reg_write(priv->cec_dev, 0xbe, 0xff, 0x3c); + adv7535_i2c_reg_write(priv->cec_dev, 0xbe, 0xff, 0x3d); + adv7535_i2c_reg_write(priv->cec_dev, 0x03, 0xff, 0x89); + + return 0; +} + +static int adv7535_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + ret = mipi_dsi_attach(device); + if (ret < 0) + return ret; + + return 0; +} + +static int adv7535_get_display_timing(struct udevice *dev, + struct display_timing *timings) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + struct adv7535_priv *priv = dev_get_priv(dev); + + memcpy(timings, &default_timing, sizeof(*timings)); + + /* fill characteristics of DSI data link */ + if (device) { + device->lanes = priv->lanes; + device->format = priv->format; + device->mode_flags = priv->mode_flags; + } + + return 0; +} + +static int adv7535_probe(struct udevice *dev) +{ + struct adv7535_priv *priv = dev_get_priv(dev); + int ret; + + debug("%s\n", __func__); + + priv->format = MIPI_DSI_FMT_RGB888; + priv->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_EOT_PACKET | MIPI_DSI_MODE_VIDEO_HSE, + + priv->addr = dev_read_addr(dev); + if (priv->addr == 0) + return -ENODEV; + + ret = dev_read_u32(dev, "adi,dsi-lanes", &priv->lanes); + if (ret) { + dev_err(dev, "Failed to get dsi-lanes property (%d)\n", ret); + return ret; + } + + if (priv->lanes < 1 || priv->lanes > 4) { + dev_err(dev, "Invalid dsi-lanes: %d\n", priv->lanes); + return -EINVAL; + } + + ret = dev_read_u32(dev, "adi,addr-cec", &priv->addr_cec); + if (ret) { + dev_err(dev, "Failed to get addr-cec property (%d)\n", ret); + return -EINVAL; + } + + ret = dm_i2c_probe(dev_get_parent(dev), priv->addr_cec, 0, &priv->cec_dev); + if (ret) { + dev_err(dev, "Can't find cec device id=0x%x\n", priv->addr_cec); + return -ENODEV; + } + + adv7535_enable(dev); + + return 0; +} + +static const struct panel_ops adv7535_ops = { + .enable_backlight = adv7535_enable_backlight, + .get_display_timing = adv7535_get_display_timing, +}; + +static const struct udevice_id adv7535_ids[] = { + { .compatible = "adi,adv7533" }, + { } +}; + +U_BOOT_DRIVER(adv7535_mipi2hdmi) = { + .name = "adv7535_mipi2hdmi", + .id = UCLASS_PANEL, + .of_match = adv7535_ids, + .ops = &adv7535_ops, + .probe = adv7535_probe, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct adv7535_priv), +}; diff --git a/drivers/video/bridge/video-bridge-uclass.c b/drivers/video/bridge/video-bridge-uclass.c index 08d38b244bd..51686eb1252 100644 --- a/drivers/video/bridge/video-bridge-uclass.c +++ b/drivers/video/bridge/video-bridge-uclass.c @@ -134,6 +134,7 @@ int video_bridge_set_active(struct udevice *dev, bool active) UCLASS_DRIVER(video_bridge) = { .id = UCLASS_VIDEO_BRIDGE, .name = "video_bridge", + .flags = DM_UC_FLAG_SEQ_ALIAS, .per_device_auto = sizeof(struct video_bridge_priv), .pre_probe = video_bridge_pre_probe, }; diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 27ff7163f34..c21550bb5c0 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1182,7 +1182,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, y = __le32_to_cpu(img->header.height) - 1; ncolors = __le32_to_cpu(img->header.colors_used); bpp = VIDEO_PIXEL_SIZE; - fbp = (unsigned char *) ((unsigned int) video_fb_address + + fbp = (unsigned char *) ((unsigned long) video_fb_address + (y + yoff) * VIDEO_LINE_LEN + xoff * bpp); @@ -1237,7 +1237,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, x = 0; y--; fbp = (unsigned char *) - ((unsigned int) video_fb_address + + ((unsigned long) video_fb_address + (y + yoff) * VIDEO_LINE_LEN + xoff * bpp); continue; @@ -1250,7 +1250,7 @@ static int display_rle8_bitmap(struct bmp_image *img, int xoff, int yoff, x += bm[2]; y -= bm[3]; fbp = (unsigned char *) - ((unsigned int) video_fb_address + + ((unsigned long) video_fb_address + (y + yoff) * VIDEO_LINE_LEN + xoff * bpp); bm += 4; @@ -2024,7 +2024,7 @@ static int cfg_video_init(void) if (pGD == NULL) return -1; - video_fb_address = (void *) VIDEO_FB_ADRS; + video_fb_address = (void *)(unsigned long) VIDEO_FB_ADRS; cfb_do_flush_cache = cfb_fb_is_in_dram() && dcache_status(); diff --git a/drivers/video/display-uclass.c b/drivers/video/display-uclass.c index 068108e9155..1b7fc96b629 100644 --- a/drivers/video/display-uclass.c +++ b/drivers/video/display-uclass.c @@ -79,5 +79,6 @@ bool display_in_use(struct udevice *dev) UCLASS_DRIVER(display) = { .id = UCLASS_DISPLAY, .name = "display", + .flags = DM_UC_FLAG_SEQ_ALIAS, .per_device_plat_auto = sizeof(struct display_plat), }; diff --git a/drivers/video/dsi-host-uclass.c b/drivers/video/dsi-host-uclass.c index 1db1f88a179..f9db4483bbf 100644 --- a/drivers/video/dsi-host-uclass.c +++ b/drivers/video/dsi-host-uclass.c @@ -33,6 +33,16 @@ int dsi_host_enable(struct udevice *dev) return ops->enable(dev); } +int dsi_host_disable(struct udevice *dev) +{ + struct dsi_host_ops *ops = dsi_host_get_ops(dev); + + if (!ops->disable) + return -ENOSYS; + + return ops->disable(dev); +} + UCLASS_DRIVER(dsi_host) = { .id = UCLASS_DSI_HOST, .name = "dsi_host", diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig deleted file mode 100644 index 78eb0f29fb3..00000000000 --- a/drivers/video/imx/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ - -config VIDEO_IPUV3 - bool "i.MX IPUv3 Core video support" - depends on DM_VIDEO && (MX5 || MX6) - help - This enables framebuffer driver for i.MX processors working - on the IPUv3(Image Processing Unit) internal graphic processor. - diff --git a/drivers/video/imx/Makefile b/drivers/video/imx/Makefile deleted file mode 100644 index 179ea651fe8..00000000000 --- a/drivers/video/imx/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o diff --git a/drivers/video/it6263_bridge.c b/drivers/video/it6263_bridge.c new file mode 100644 index 00000000000..405d0571abb --- /dev/null +++ b/drivers/video/it6263_bridge.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include + +struct it6263_priv { + unsigned int addr; +}; + +static int it6263_i2c_reg_write(struct udevice *dev, uint addr, uint mask, uint data) +{ + uint8_t valb; + int err; + + if (mask != 0xff) { + err = dm_i2c_read(dev, addr, &valb, 1); + if (err) { + printf("%s, read err %d\n", __func__, err); + return err; + } + + valb &= ~mask; + valb |= data; + } else { + valb = data; + } + + err = dm_i2c_write(dev, addr, &valb, 1); + if (err) { + printf("%s, write err %d\n", __func__, err); + } + return err; +} + +static int it6263_i2c_reg_read(struct udevice *dev, uint8_t addr, uint8_t *data) +{ + uint8_t valb; + int err; + + err = dm_i2c_read(dev, addr, &valb, 1); + if (err) { + printf("%s, read err %d\n", __func__, err); + return err; + } + + *data = (int)valb; + return 0; +} + +static int it6263_enable(struct udevice *dev) +{ + uint8_t data; + int ret; + + ret = it6263_i2c_reg_read(dev, 0x00, &data); + if (ret) { + printf("faill to read from it6263 revision, ret %d\n", ret); + return ret; + } + + /* InitIT626X(): start */ + it6263_i2c_reg_write(dev, 0x04, 0xff, 0x3d); + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0x05, 0xff, 0x40); + it6263_i2c_reg_write(dev, 0x04, 0xff, 0x15); + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0x1d, 0xff, 0x66); + it6263_i2c_reg_write(dev, 0x1e, 0xff, 0x01); + + it6263_i2c_reg_write(dev, 0x61, 0xff, 0x30); + it6263_i2c_reg_read(dev, 0xf3, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0xf3, 0xff, data & ~0x30); + it6263_i2c_reg_read(dev, 0xf3, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0xf3, 0xff, data | 0x20); + + it6263_i2c_reg_write(dev, 0x09, 0xff, 0x30); + it6263_i2c_reg_write(dev, 0x0a, 0xff, 0xf8); + it6263_i2c_reg_write(dev, 0x0b, 0xff, 0x37); + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xc9, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xca, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xcb, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xcc, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xcd, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xce, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xcf, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xd0, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x01); + + it6263_i2c_reg_read(dev, 0x58, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0x58, 0xff, data & ~(3 << 5)); + + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xe1, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0x0c, 0xff, 0xff); + it6263_i2c_reg_write(dev, 0x0d, 0xff, 0xff); + it6263_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0x0e, 0xff, (data | 0x3)); + it6263_i2c_reg_write(dev, 0x0e, 0xff, (data & 0xfe)); + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x01); + it6263_i2c_reg_write(dev, 0x33, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0x34, 0xff, 0x18); + it6263_i2c_reg_write(dev, 0x35, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xc4, 0xff, 0xfe); + it6263_i2c_reg_read(dev, 0xc5, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0xc5, 0xff, data | 0x30); + /* InitIT626X end */ + + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0x04, 0xff, 0x3d); + it6263_i2c_reg_write(dev, 0x04, 0xff, 0x15); + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0x1d, 0xff, 0x66); + it6263_i2c_reg_write(dev, 0x1e, 0xff, 0x01); + + it6263_i2c_reg_read(dev, 0xc1, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0x61, 0xff, 0x10); + + /* SetupAFE(): */ + it6263_i2c_reg_write(dev, 0x62, 0xff, 0x88); + it6263_i2c_reg_write(dev, 0x63, 0xff, 0x10); + it6263_i2c_reg_write(dev, 0x64, 0xff, 0x84); + /* SetupAFE(): end */ + + it6263_i2c_reg_read(dev, 0x04, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0x04, 0xff, 0x1d); + + it6263_i2c_reg_read(dev, 0x04, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0x04, 0xff, 0x15); + + it6263_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */ + + /* Wait video stable */ + it6263_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */ + + /* Reset Video */ + it6263_i2c_reg_read(dev, 0x0d, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0x0d, 0xff, 0x40); + it6263_i2c_reg_read(dev, 0x0e, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0x0e, 0xff, 0x7d); + it6263_i2c_reg_write(dev, 0x0e, 0xff, 0x7c); + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0x61, 0xff, 0x00); + it6263_i2c_reg_read(dev, 0x61, &data); /* -> 0x00 */ + it6263_i2c_reg_read(dev, 0x62, &data); /* -> 0x00 */ + it6263_i2c_reg_read(dev, 0x63, &data); /* -> 0x00 */ + it6263_i2c_reg_read(dev, 0x64, &data); /* -> 0x00 */ + it6263_i2c_reg_read(dev, 0x65, &data); /* -> 0x00 */ + it6263_i2c_reg_read(dev, 0x66, &data); /* -> 0x00 */ + it6263_i2c_reg_read(dev, 0x67, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0x0f, 0xff, 0x00); + it6263_i2c_reg_read(dev, 0xc1, &data); /* -> 0x00 */ + it6263_i2c_reg_write(dev, 0xc1, 0xff, 0x00); + it6263_i2c_reg_write(dev, 0xc6, 0xff, 0x03); + /* Clear AV mute */ + + return 0; +} + +static int it6263_attach(struct udevice *dev) +{ + return 0; +} + +static int it6263_set_backlight(struct udevice *dev, int percent) +{ + debug("%s\n", __func__); + + mdelay(10); + it6263_enable(dev); + return 0; +} + +static int it6263_probe(struct udevice *dev) +{ + struct it6263_priv *priv = dev_get_priv(dev); + + debug("%s\n", __func__); + + priv->addr = dev_read_addr(dev); + if (priv->addr == 0) + return -ENODEV; + + return 0; +} + +struct video_bridge_ops it6263_ops = { + .attach = it6263_attach, + .set_backlight = it6263_set_backlight, +}; + +static const struct udevice_id it6263_ids[] = { + { .compatible = "ite,it6263" }, + { } +}; + +U_BOOT_DRIVER(it6263_bridge) = { + .name = "it6263_bridge", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = it6263_ids, + .ops = &it6263_ops, + .bind = dm_scan_fdt_dev, + .probe = it6263_probe, + .priv_auto = sizeof(struct it6263_priv), +}; diff --git a/drivers/video/mxc_csi.c b/drivers/video/mxc_csi.c new file mode 100644 index 00000000000..07644e6cf0c --- /dev/null +++ b/drivers/video/mxc_csi.c @@ -0,0 +1,272 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +/*! + * @file fsl_csi.c, this file is derived from mx27_csi.c + * + * @brief mx25 CMOS Sensor interface functions + * + * @ingroup CSI + */ +#include +#include + +#include +#include +#include + +#include +#include + +#include "mxc_csi.h" + +enum { + STD_NTSC = 0, + STD_PAL, +}; + +void __iomem *csi_regbase; + +static void csihw_reset_frame_count(void) +{ + __raw_writel(__raw_readl(CSI_CSICR3) | BIT_FRMCNT_RST, CSI_CSICR3); +} + +static void csihw_reset(void) +{ + csihw_reset_frame_count(); + __raw_writel(CSICR1_RESET_VAL, CSI_CSICR1); + __raw_writel(CSICR2_RESET_VAL, CSI_CSICR2); + __raw_writel(CSICR3_RESET_VAL, CSI_CSICR3); +} + +/*! + * csi_init_interface + * Init csi interface + */ +void csi_init_interface(void) +{ + unsigned int val = 0; + unsigned int imag_para; + + val |= BIT_SOF_POL; + val |= BIT_REDGE; + val |= BIT_GCLK_MODE; + val |= BIT_HSYNC_POL; + val |= BIT_FCC; + val |= 1 << SHIFT_MCLKDIV; + val |= BIT_MCLKEN; + __raw_writel(val, CSI_CSICR1); + + imag_para = (640 << 16) | 960; + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + val = 0x1010; + val |= BIT_DMA_REFLASH_RFF; + __raw_writel(val, CSI_CSICR3); +} + +void csi_format_swap16(bool enable) +{ + unsigned int val; + + val = __raw_readl(CSI_CSICR1); + if (enable) { + val |= BIT_PACK_DIR; + val |= BIT_SWAP16_EN; + } else { + val &= ~BIT_PACK_DIR; + val &= ~BIT_SWAP16_EN; + } + + __raw_writel(val, CSI_CSICR1); +} + +void csi_enable_int(int arg) +{ + unsigned long cr1 = __raw_readl(CSI_CSICR1); + + if (arg == 1) { + /* still capture needs DMA intterrupt */ + cr1 |= BIT_FB1_DMA_DONE_INTEN; + cr1 |= BIT_FB2_DMA_DONE_INTEN; + } + __raw_writel(cr1, CSI_CSICR1); +} + +void csi_disable_int(void) +{ + unsigned long cr1 = __raw_readl(CSI_CSICR1); + + cr1 &= ~BIT_FB1_DMA_DONE_INTEN; + cr1 &= ~BIT_FB2_DMA_DONE_INTEN; + __raw_writel(cr1, CSI_CSICR1); +} + +void csi_enable(int arg) +{ + unsigned long cr = __raw_readl(CSI_CSICR18); + + if (arg == 1) + cr |= BIT_CSI_ENABLE; + else + cr &= ~BIT_CSI_ENABLE; + __raw_writel(cr, CSI_CSICR18); +} + +void csi_buf_stride_set(u32 stride) +{ + __raw_writel(stride, CSI_CSIFBUF_PARA); +} + +void csi_deinterlace_enable(bool enable) +{ + unsigned long cr18 = __raw_readl(CSI_CSICR18); + + if (enable == true) + cr18 |= BIT_DEINTERLACE_EN; + else + cr18 &= ~BIT_DEINTERLACE_EN; + + __raw_writel(cr18, CSI_CSICR18); +} + +void csi_deinterlace_mode(int mode) +{ + unsigned long cr18 = __raw_readl(CSI_CSICR18); + + if (mode == STD_NTSC) + cr18 |= BIT_NTSC_EN; + else + cr18 &= ~BIT_NTSC_EN; + + __raw_writel(cr18, CSI_CSICR18); +} + +void csi_tvdec_enable(bool enable) +{ + unsigned long cr18 = __raw_readl(CSI_CSICR18); + unsigned long cr1 = __raw_readl(CSI_CSICR1); + + if (enable == true) { + cr18 |= (BIT_TVDECODER_IN_EN | BIT_BASEADDR_SWITCH_EN); + cr1 |= BIT_CCIR_MODE | BIT_EXT_VSYNC; + cr1 &= ~(BIT_SOF_POL | BIT_REDGE); + } else { + cr18 &= ~(BIT_TVDECODER_IN_EN | BIT_BASEADDR_SWITCH_EN); + cr1 &= ~(BIT_CCIR_MODE | BIT_EXT_VSYNC); + cr1 |= BIT_SOF_POL | BIT_REDGE; + } + + __raw_writel(cr18, CSI_CSICR18); + __raw_writel(cr1, CSI_CSICR1); +} + +void csi_set_32bit_imagpara(int width, int height) +{ + int imag_para = 0; + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + imag_para = (width << 16) | height; + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + + /* reflash the embeded DMA controller */ + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); +} + +void csi_set_16bit_imagpara(int width, int height) +{ + int imag_para = 0; + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + imag_para = (width << 16) | (height * 2); + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + /* reflash the embeded DMA controller */ + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); +} + +void csi_set_12bit_imagpara(int width, int height) +{ + int imag_para = 0; + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + imag_para = (width << 16) | (height * 3 / 2); + __raw_writel(imag_para, CSI_CSIIMAG_PARA); + + /* reflash the embeded DMA controller */ + __raw_writel(cr3 | BIT_DMA_REFLASH_RFF, CSI_CSICR3); +} + +void csi_dmareq_rff_enable(void) +{ + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + cr3 |= BIT_DMA_REQ_EN_RFF; + cr3 |= BIT_HRESP_ERR_EN; + __raw_writel(cr3, CSI_CSICR3); +} + +void csi_dmareq_rff_disable(void) +{ + unsigned long cr3 = __raw_readl(CSI_CSICR3); + + cr3 &= ~BIT_DMA_REQ_EN_RFF; + cr3 &= ~BIT_HRESP_ERR_EN; + __raw_writel(cr3, CSI_CSICR3); +} + +void csi_disable(void) +{ + csi_dmareq_rff_disable(); + csi_disable_int(); + csi_buf_stride_set(0); + csi_deinterlace_enable(false); + csi_tvdec_enable(false); + csi_enable(0); +} + +void csi_config(struct csi_conf_param *csi_conf) +{ + csi_regbase = (u32 *)CSI1_BASE_ADDR; + + csihw_reset(); + + csi_init_interface(); + csi_dmareq_rff_disable(); + + switch (csi_conf->bpp) { + case 32: + csi_set_32bit_imagpara(csi_conf->width, csi_conf->height); + break; + case 16: + csi_set_16bit_imagpara(csi_conf->width, csi_conf->height); + break; + default: + printf(" %s case not supported, bpp=%d\n", + __func__, csi_conf->bpp); + return; + } + + __raw_writel((u32)csi_conf->fb0addr, CSI_CSIDMASA_FB1); + __raw_writel((u32)csi_conf->fb1addr, CSI_CSIDMASA_FB2); + + csi_buf_stride_set(0); + if (csi_conf->btvmode) { + /* Enable csi PAL/NTSC deinterlace mode */ + csi_buf_stride_set(csi_conf->width); + csi_deinterlace_mode(csi_conf->std); + csi_deinterlace_enable(true); + csi_tvdec_enable(true); + } + + /* start csi */ + csi_dmareq_rff_enable(); + csi_enable_int(1); + csi_enable(1); +} + diff --git a/drivers/video/mxc_csi.h b/drivers/video/mxc_csi.h new file mode 100644 index 00000000000..694214fb70b --- /dev/null +++ b/drivers/video/mxc_csi.h @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +/*! + * @file mxc_csi.h + * + * @brief mxc CMOS Sensor interface functions + * + * @ingroup CSI + */ + +#ifndef MXC_CSI_H +#define MXC_CSI_H + +/* reset values */ +#define CSICR1_RESET_VAL 0x40000800 +#define CSICR2_RESET_VAL 0x0 +#define CSICR3_RESET_VAL 0x0 + +/* csi control reg 1 */ +#define BIT_SWAP16_EN (0x1 << 31) +#define BIT_EXT_VSYNC (0x1 << 30) +#define BIT_EOF_INT_EN (0x1 << 29) +#define BIT_PRP_IF_EN (0x1 << 28) +#define BIT_CCIR_MODE (0x1 << 27) +#define BIT_COF_INT_EN (0x1 << 26) +#define BIT_SF_OR_INTEN (0x1 << 25) +#define BIT_RF_OR_INTEN (0x1 << 24) +#define BIT_SFF_DMA_DONE_INTEN (0x1 << 22) +#define BIT_STATFF_INTEN (0x1 << 21) +#define BIT_FB2_DMA_DONE_INTEN (0x1 << 20) +#define BIT_FB1_DMA_DONE_INTEN (0x1 << 19) +#define BIT_RXFF_INTEN (0x1 << 18) +#define BIT_SOF_POL (0x1 << 17) +#define BIT_SOF_INTEN (0x1 << 16) +#define BIT_MCLKDIV (0xF << 12) +#define BIT_HSYNC_POL (0x1 << 11) +#define BIT_CCIR_EN (0x1 << 10) +#define BIT_MCLKEN (0x1 << 9) +#define BIT_FCC (0x1 << 8) +#define BIT_PACK_DIR (0x1 << 7) +#define BIT_CLR_STATFIFO (0x1 << 6) +#define BIT_CLR_RXFIFO (0x1 << 5) +#define BIT_GCLK_MODE (0x1 << 4) +#define BIT_INV_DATA (0x1 << 3) +#define BIT_INV_PCLK (0x1 << 2) +#define BIT_REDGE (0x1 << 1) +#define BIT_PIXEL_BIT (0x1 << 0) + +#define SHIFT_MCLKDIV 12 + +/* control reg 3 */ +#define BIT_FRMCNT (0xFFFF << 16) +#define BIT_FRMCNT_RST (0x1 << 15) +#define BIT_DMA_REFLASH_RFF (0x1 << 14) +#define BIT_DMA_REFLASH_SFF (0x1 << 13) +#define BIT_DMA_REQ_EN_RFF (0x1 << 12) +#define BIT_DMA_REQ_EN_SFF (0x1 << 11) +#define BIT_STATFF_LEVEL (0x7 << 8) +#define BIT_HRESP_ERR_EN (0x1 << 7) +#define BIT_RXFF_LEVEL (0x7 << 4) +#define BIT_TWO_8BIT_SENSOR (0x1 << 3) +#define BIT_ZERO_PACK_EN (0x1 << 2) +#define BIT_ECC_INT_EN (0x1 << 1) +#define BIT_ECC_AUTO_EN (0x1 << 0) + +#define SHIFT_FRMCNT 16 + +/* csi status reg */ +#define BIT_SFF_OR_INT (0x1 << 25) +#define BIT_RFF_OR_INT (0x1 << 24) +#define BIT_DMA_TSF_DONE_SFF (0x1 << 22) +#define BIT_STATFF_INT (0x1 << 21) +#define BIT_DMA_TSF_DONE_FB2 (0x1 << 20) +#define BIT_DMA_TSF_DONE_FB1 (0x1 << 19) +#define BIT_RXFF_INT (0x1 << 18) +#define BIT_EOF_INT (0x1 << 17) +#define BIT_SOF_INT (0x1 << 16) +#define BIT_F2_INT (0x1 << 15) +#define BIT_F1_INT (0x1 << 14) +#define BIT_COF_INT (0x1 << 13) +#define BIT_HRESP_ERR_INT (0x1 << 7) +#define BIT_ECC_INT (0x1 << 1) +#define BIT_DRDY (0x1 << 0) + +/* csi control reg 18 */ +#define BIT_CSI_ENABLE (0x1 << 31) +#define BIT_BASEADDR_SWITCH_SEL (0x1 << 5) +#define BIT_BASEADDR_SWITCH_EN (0x1 << 4) +#define BIT_PARALLEL24_EN (0x1 << 3) +#define BIT_DEINTERLACE_EN (0x1 << 2) +#define BIT_TVDECODER_IN_EN (0x1 << 1) +#define BIT_NTSC_EN (0x1 << 0) + +#define CSI_MCLK_VF 1 +#define CSI_MCLK_ENC 2 +#define CSI_MCLK_RAW 4 +#define CSI_MCLK_I2C 8 + +#define CSI_CSICR1 (csi_regbase) +#define CSI_CSICR2 (csi_regbase + 0x4) +#define CSI_CSICR3 (csi_regbase + 0x8) +#define CSI_STATFIFO (csi_regbase + 0xC) +#define CSI_CSIRXFIFO (csi_regbase + 0x10) +#define CSI_CSIRXCNT (csi_regbase + 0x14) +#define CSI_CSISR (csi_regbase + 0x18) +#define CSI_CSIDBG (csi_regbase + 0x1C) +#define CSI_CSIDMASA_STATFIFO (csi_regbase + 0x20) +#define CSI_CSIDMATS_STATFIFO (csi_regbase + 0x24) +#define CSI_CSIDMASA_FB1 (csi_regbase + 0x28) +#define CSI_CSIDMASA_FB2 (csi_regbase + 0x2C) +#define CSI_CSIFBUF_PARA (csi_regbase + 0x30) +#define CSI_CSIIMAG_PARA (csi_regbase + 0x34) +#define CSI_CSICR18 (csi_regbase + 0x48) +#define CSI_CSICR19 (csi_regbase + 0x4c) + +struct mxs_csi_regs { + u32 csi_csicr1; /* 0x0 */ + u32 csi_csicr2; /* 0x4 */ + u32 csi_csicr3; /* 0x8 */ + u32 csi_statfifo; /* 0xC */ + u32 csi_csirxfifo; /* 0x10 */ + u32 csi_csirxcnt; /* 0x14 */ + u32 csi_csisr; /* 0x18 */ + u32 csi_csidbg; /* 0x1C */ + u32 csi_csidmasa_statfifo; /* 0x20 */ + u32 csi_csidmats_statfifo; /* 0x24 */ + u32 csi_csidmasa_fb1; /* 0x28 */ + u32 csi_csidmasa_fb2; /* 0x2C */ + u32 csi_csifbuf_para; /* 0x30 */ + u32 csi_csiimag_para; /* 0x34 */ + u32 reserver[4]; + u32 csi_csicr18; /* 0x48 */ + u32 csi_csicr19; /* 0x4c */ +}; + +struct csi_conf_param { + unsigned short width; + unsigned short height; + unsigned int pixel_fmt; + unsigned int bpp; + bool btvmode; + unsigned int std; + void *fb0addr; + void *fb1addr; +}; + +void csi_config(struct csi_conf_param *csi_conf); +void csi_disable(void); +#endif diff --git a/drivers/video/mxc_epdc_fb.c b/drivers/video/mxc_epdc_fb.c new file mode 100644 index 00000000000..84937841f0d --- /dev/null +++ b/drivers/video/mxc_epdc_fb.c @@ -0,0 +1,489 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * Based on STMP378X LCDIF + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + +int rev; + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +#define TEMP_USE_DEFAULT 8 + +#define UPDATE_MODE_PARTIAL 0x0 +#define UPDATE_MODE_FULL 0x1 + +#define TRUE 1 +#define FALSE 0 + +#define msleep(a) udelay(a * 1000) + + +/******************************************************** + * Start Low-Level EPDC Functions + ********************************************************/ + +static inline void epdc_set_screen_res(u32 width, u32 height) +{ + u32 val = (height << EPDC_RES_VERTICAL_OFFSET) | width; + + REG_WR(EPDC_BASE, EPDC_RES, val); +} + +static inline void epdc_set_update_coord(u32 x, u32 y) +{ + u32 val = (y << EPDC_UPD_CORD_YCORD_OFFSET) | x; + + REG_WR(EPDC_BASE, EPDC_UPD_CORD, val); +} + +static inline void epdc_set_update_dimensions(u32 width, u32 height) +{ + u32 val = (height << EPDC_UPD_SIZE_HEIGHT_OFFSET) | width; + + REG_WR(EPDC_BASE, EPDC_UPD_SIZE, val); +} + +static void epdc_submit_update(u32 lut_num, u32 waveform_mode, u32 update_mode, + int use_test_mode, u32 np_val) +{ + u32 reg_val = 0; + + if (use_test_mode) { + reg_val |= + ((np_val << EPDC_UPD_FIXED_FIXNP_OFFSET) & + EPDC_UPD_FIXED_FIXNP_MASK) | EPDC_UPD_FIXED_FIXNP_EN; + + REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val); + + reg_val = EPDC_UPD_CTRL_USE_FIXED; + } else { + REG_WR(EPDC_BASE, EPDC_UPD_FIXED, reg_val); + } + + reg_val |= + ((lut_num << EPDC_UPD_CTRL_LUT_SEL_OFFSET) & + EPDC_UPD_CTRL_LUT_SEL_MASK) | + ((waveform_mode << EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET) & + EPDC_UPD_CTRL_WAVEFORM_MODE_MASK) | + update_mode; + + REG_WR(EPDC_BASE, EPDC_UPD_CTRL, reg_val); +} + +static inline int epdc_is_lut_active(u32 lut_num) +{ + u32 val = REG_RD(EPDC_BASE, EPDC_STATUS_LUTS); + int is_active = val & (1 << lut_num) ? TRUE : FALSE; + + return is_active; +} + +static void epdc_set_horizontal_timing(u32 horiz_start, u32 horiz_end, + u32 hsync_width, u32 hsync_line_length) +{ + u32 reg_val = + ((hsync_width << EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET) & + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK) + | ((hsync_line_length << EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET) & + EPDC_TCE_HSCAN1_LINE_SYNC_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_HSCAN1, reg_val); + + reg_val = + ((horiz_start << EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET) & + EPDC_TCE_HSCAN2_LINE_BEGIN_MASK) + | ((horiz_end << EPDC_TCE_HSCAN2_LINE_END_OFFSET) & + EPDC_TCE_HSCAN2_LINE_END_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_HSCAN2, reg_val); +} + +static void epdc_set_vertical_timing(u32 vert_start, u32 vert_end, + u32 vsync_width) +{ + u32 reg_val = + ((vert_start << EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET) & + EPDC_TCE_VSCAN_FRAME_BEGIN_MASK) + | ((vert_end << EPDC_TCE_VSCAN_FRAME_END_OFFSET) & + EPDC_TCE_VSCAN_FRAME_END_MASK) + | ((vsync_width << EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET) & + EPDC_TCE_VSCAN_FRAME_SYNC_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_VSCAN, reg_val); +} + +static void epdc_init_settings(void) +{ + u32 reg_val; + int num_ce; + + /* EPDC_CTRL */ + reg_val = REG_RD(EPDC_BASE, EPDC_CTRL); + reg_val &= ~EPDC_CTRL_UPD_DATA_SWIZZLE_MASK; + reg_val |= EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP; + reg_val &= ~EPDC_CTRL_LUT_DATA_SWIZZLE_MASK; + reg_val |= EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP; + REG_SET(EPDC_BASE, EPDC_CTRL, reg_val); + + /* EPDC_FORMAT - 2bit TFT and 4bit Buf pixel format */ + reg_val = EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT + | EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N + | ((0x0 << EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET) & + EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK); + REG_WR(EPDC_BASE, EPDC_FORMAT, reg_val); + + /* EPDC_FIFOCTRL (disabled) */ + reg_val = + ((100 << EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK) + | ((200 << EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK) + | ((100 << EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET) & + EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK); + REG_WR(EPDC_BASE, EPDC_FIFOCTRL, reg_val); + + /* EPDC_TEMP - Use default temperature */ + REG_WR(EPDC_BASE, EPDC_TEMP, TEMP_USE_DEFAULT); + + /* EPDC_RES */ + epdc_set_screen_res(panel_info.vl_col, panel_info.vl_row); + + /* + * EPDC_TCE_CTRL + * VSCAN_HOLDOFF = 4 + * VCOM_MODE = MANUAL + * VCOM_VAL = 0 + * DDR_MODE = DISABLED + * LVDS_MODE_CE = DISABLED + * LVDS_MODE = DISABLED + * DUAL_SCAN = DISABLED + * SDDO_WIDTH = 8bit + * PIXELS_PER_SDCLK = 4 + */ + reg_val = + ((panel_info.epdc_data.epdc_timings.vscan_holdoff << + EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET) & + EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK) + | EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4; + REG_WR(EPDC_BASE, EPDC_TCE_CTRL, reg_val); + + /* EPDC_TCE_HSCAN */ + epdc_set_horizontal_timing(panel_info.vl_left_margin, + panel_info.vl_right_margin, + panel_info.vl_hsync, + panel_info.vl_hsync); + + /* EPDC_TCE_VSCAN */ + epdc_set_vertical_timing(panel_info.vl_upper_margin, + panel_info.vl_lower_margin, + panel_info.vl_vsync); + + /* EPDC_TCE_OE */ + reg_val = + ((panel_info.epdc_data.epdc_timings.sdoed_width << + EPDC_TCE_OE_SDOED_WIDTH_OFFSET) & + EPDC_TCE_OE_SDOED_WIDTH_MASK) + | ((panel_info.epdc_data.epdc_timings.sdoed_delay << + EPDC_TCE_OE_SDOED_DLY_OFFSET) & + EPDC_TCE_OE_SDOED_DLY_MASK) + | ((panel_info.epdc_data.epdc_timings.sdoez_width << + EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET) & + EPDC_TCE_OE_SDOEZ_WIDTH_MASK) + | ((panel_info.epdc_data.epdc_timings.sdoez_delay << + EPDC_TCE_OE_SDOEZ_DLY_OFFSET) & + EPDC_TCE_OE_SDOEZ_DLY_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_OE, reg_val); + + /* EPDC_TCE_TIMING1 */ + REG_WR(EPDC_BASE, EPDC_TCE_TIMING1, 0x0); + + /* EPDC_TCE_TIMING2 */ + reg_val = + ((panel_info.epdc_data.epdc_timings.gdclk_hp_offs << + EPDC_TCE_TIMING2_GDCLK_HP_OFFSET) & + EPDC_TCE_TIMING2_GDCLK_HP_MASK) + | ((panel_info.epdc_data.epdc_timings.gdsp_offs << + EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET) & + EPDC_TCE_TIMING2_GDSP_OFFSET_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_TIMING2, reg_val); + + /* EPDC_TCE_TIMING3 */ + reg_val = + ((panel_info.epdc_data.epdc_timings.gdoe_offs << + EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET) & + EPDC_TCE_TIMING3_GDOE_OFFSET_MASK) + | ((panel_info.epdc_data.epdc_timings.gdclk_offs << + EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET) & + EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_TIMING3, reg_val); + + /* + * EPDC_TCE_SDCFG + * SDCLK_HOLD = 1 + * SDSHR = 1 + * NUM_CE = 1 + * SDDO_REFORMAT = FLIP_PIXELS + * SDDO_INVERT = DISABLED + * PIXELS_PER_CE = display horizontal resolution + */ + num_ce = panel_info.epdc_data.epdc_timings.num_ce; + if (num_ce == 0) + num_ce = 1; + reg_val = EPDC_TCE_SDCFG_SDCLK_HOLD | EPDC_TCE_SDCFG_SDSHR + | ((num_ce << EPDC_TCE_SDCFG_NUM_CE_OFFSET) & EPDC_TCE_SDCFG_NUM_CE_MASK) + | EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS + | ((panel_info.vl_col << EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET) & + EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK); + REG_WR(EPDC_BASE, EPDC_TCE_SDCFG, reg_val); + + /* + * EPDC_TCE_GDCFG + * GDRL = 1 + * GDOE_MODE = 0; + * GDSP_MODE = 0; + */ + reg_val = EPDC_TCE_SDCFG_GDRL; + REG_WR(EPDC_BASE, EPDC_TCE_GDCFG, reg_val); + + /* + * EPDC_TCE_POLARITY + * SDCE_POL = ACTIVE LOW + * SDLE_POL = ACTIVE HIGH + * SDOE_POL = ACTIVE HIGH + * GDOE_POL = ACTIVE HIGH + * GDSP_POL = ACTIVE LOW + */ + reg_val = EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH + | EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH + | EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH; + REG_WR(EPDC_BASE, EPDC_TCE_POLARITY, reg_val); + + /* EPDC_IRQ_MASK */ + REG_WR(EPDC_BASE, EPDC_IRQ_MASK, + EPDC_IRQ_TCE_UNDERRUN_IRQ); + + /* + * EPDC_GPIO + * PWRCOM = ? + * PWRCTRL = ? + * BDR = ? + */ + reg_val = ((0 << EPDC_GPIO_PWRCTRL_OFFSET) & EPDC_GPIO_PWRCTRL_MASK) + | ((0 << EPDC_GPIO_BDR_OFFSET) & EPDC_GPIO_BDR_MASK); + REG_WR(EPDC_BASE, EPDC_GPIO, reg_val); +} + +static void draw_mode0(void) +{ + int i; + + /* Program EPDC update to process buffer */ + epdc_set_update_coord(0, 0); + epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row); + epdc_submit_update(0, panel_info.epdc_data.wv_modes.mode_init, + UPDATE_MODE_FULL, FALSE, 0); + + debug("Mode0 update - Waiting for LUT to complete...\n"); + + /* Will timeout after ~4-5 seconds */ + + for (i = 0; i < 40; i++) { + if (!epdc_is_lut_active(0)) { + debug("Mode0 init complete\n"); + return; + } + msleep(100); + } + + debug("Mode0 init failed!\n"); + +} + +static void draw_splash_screen(void) +{ + int i; + int lut_num = 0; + + /* Program EPDC update to process buffer */ + epdc_set_update_coord(0, 0); + epdc_set_update_dimensions(panel_info.vl_col, panel_info.vl_row); + epdc_submit_update(lut_num, panel_info.epdc_data.wv_modes.mode_gc16, + UPDATE_MODE_FULL, FALSE, 0); + + for (i = 0; i < 40; i++) { + if (!epdc_is_lut_active(lut_num)) { + debug("Splash screen update complete\n"); + return; + } + msleep(100); + } + debug("Splash screen update failed!\n"); +} + +void lcd_enable(void) +{ + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_EPDC)) { + return; + } + } + + if (board_setup_logo_file(lcd_base)) { + debug("Load logo failed!\n"); + return; + } + + epdc_power_on(); + + flush_cache((ulong)lcd_base, panel_info.vl_col * panel_info.vl_row); + + /* Draw data to display */ + draw_mode0(); + + draw_splash_screen(); +} + +void lcd_disable(void) +{ + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_EPDC)) { + return; + } + } + + debug("lcd_disable\n"); + + /* Disable clocks to EPDC */ + REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE); +} + +void lcd_panel_disable(void) +{ + epdc_power_off(); +} + +void lcd_ctrl_init(void *lcdbase) +{ + unsigned int val; + + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_EPDC)) { + printf("EPDC@0x%x is fused, disable it\n", EPDC_BASE_ADDR); + return; + } + } + + /* + * We rely on lcdbase being a physical address, i.e., either MMU off, + * or 1-to-1 mapping. Might want to add some virt2phys here. + */ + if (!lcdbase) + return; + + panel_info.epdc_data.working_buf_addr = (u_long)memalign(ARCH_DMA_MINALIGN, + panel_info.vl_col * panel_info.vl_row * 2); + + if (!panel_info.epdc_data.working_buf_addr) { + printf("EPDC: Error allocating working buffer!\n"); + return; + } + + panel_info.epdc_data.waveform_buf_addr = (u_long)memalign(ARCH_DMA_MINALIGN, + CONFIG_WAVEFORM_BUF_SIZE); + + if (!panel_info.epdc_data.waveform_buf_addr) { + printf("EPDC: Error allocating waveform buffer!\n"); + return; + } + + lcd_color_fg = 0xFF; + lcd_color_bg = 0xFF; + + /* Reset */ + REG_SET(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST); + while (!(REG_RD(EPDC_BASE, EPDC_CTRL) & EPDC_CTRL_CLKGATE)) + ; + REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_SFTRST); + + /* Enable clock gating (clear to enable) */ + REG_CLR(EPDC_BASE, EPDC_CTRL, EPDC_CTRL_CLKGATE); + while (REG_RD(EPDC_BASE, EPDC_CTRL) & + (EPDC_CTRL_SFTRST | EPDC_CTRL_CLKGATE)) + ; + + debug("resolution %dx%d, bpp %d\n", (int)panel_info.vl_col, + (int)panel_info.vl_row, NBITS(panel_info.vl_bpix)); + + /* Get EPDC version */ + val = REG_RD(EPDC_BASE, EPDC_VERSION); + rev = ((val & EPDC_VERSION_MAJOR_MASK) >> + EPDC_VERSION_MAJOR_OFFSET) * 10 + + ((val & EPDC_VERSION_MINOR_MASK) >> + EPDC_VERSION_MINOR_OFFSET); + + /* Set framebuffer pointer */ + REG_WR(EPDC_BASE, EPDC_UPD_ADDR, (u32)lcdbase); + + /* Set Working Buffer pointer */ + REG_WR(EPDC_BASE, EPDC_WB_ADDR, panel_info.epdc_data.working_buf_addr); + if (rev > 20) + REG_WR(EPDC_BASE, EPDC_WB_ADDR_TCE, panel_info.epdc_data.working_buf_addr); + + /* Get waveform data address and offset */ + if (board_setup_waveform_file(panel_info.epdc_data.waveform_buf_addr)) { + printf("Can't load waveform data!\n"); + return; + } + + /* Set Waveform Buffer pointer */ + REG_WR(EPDC_BASE, EPDC_WVADDR, + panel_info.epdc_data.waveform_buf_addr); + + /* Initialize EPDC, passing pointer to EPDC registers */ + epdc_init_settings(); + + lcd_base = lcdbase; + + return; +} + +ulong calc_fbsize(void) +{ + return panel_info.vl_row * panel_info.vl_col * 2 \ + * NBITS(panel_info.vl_bpix) / 8; +} + + + diff --git a/drivers/video/mxc_gis.c b/drivers/video/mxc_gis.c new file mode 100644 index 00000000000..eefb63ee595 --- /dev/null +++ b/drivers/video/mxc_gis.c @@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "mxc_gis.h" +#include "mxc_csi.h" +#include "mxc_pxp.h" +#include "mxc_vadc.h" + +#define CHANNEL_OFFSET 36 +#define COMMAND_OFFSET 8 +#define REG_OFFSET 4 +#define COMMAND_OPCODE_SHIFT 8 + +enum { + CMD_SET_ACC = 0, + CMD_WR_DATA, + CMD_WR_ACC, + CMD_WR_ALU, + CMD_MOV_ACC, + CMD_RD_DATA, + CMD_RD_ALU, + CMD_WR_FB_CSI, + CMD_WR_FB_PXP_IN, + CMD_WR_FB_PXP_OUT, + CMD_WR_FB_LCDIF, +}; + +enum { + ALU_AND = 0, + ALU_OR, + ALU_XOR, + ALU_ADD, + ALU_SUB, +}; + +enum { + CH_MAPPING_CSI_ISR = 0, + CH_MAPPING_CSI_FB_UPDATE, + CH_MAPPING_PXP_ISR, + CH_MAPPING_LCDIF_FB_UPDATE, + CH_MAPPING_PXP_KICK, + CH_MAPPING_CHANNEL_UNUSED = 0xf, +}; + +enum { + LCDIF1_SEL = 0x10, + LCDIF0_SEL = 0x8, + PXP_SEL = 0x4, + CSI1_SEL = 0x2, + CSI0_SEL = 0x1, +}; + +struct command_opcode { + unsigned opcode:4; + unsigned alu:3; + unsigned acc_neg:1; +}; + +struct command_param { + union { + struct command_opcode cmd_bits; + u8 cmd_opc; + }; + u32 addr; + u32 data; +}; + +struct channel_param { + u32 ch_num; + u32 ch_map; + u32 cmd_num; + struct command_param cmd_data[4]; +}; + +static void *csibuf0, *csibuf1, *fb0, *fb1; +static struct mxs_gis_regs *gis_regs; +static struct mxs_pxp_regs *pxp_regs; +static struct mxs_csi_regs *csi_regs; +static struct mxs_lcdif_regs *lcdif_regs; +static u32 lcdif_sel; +static bool gis_running; + +static void config_channel(struct channel_param *ch) +{ + u32 val, i; + u32 reg_offset; + + if (ch->cmd_num > 3 || ch->ch_num > 5) { + printf("Error val cmd_num=%d, ch_num=%d\n , \n", ch->cmd_num, ch->ch_num); + return; + } + + /* Config channel map and command */ + switch (ch->ch_num) { + case 0: + val = readl(&gis_regs->hw_gis_config0); + val &= ~(GIS_CONFIG0_CH0_MAPPING_MASK | GIS_CONFIG0_CH0_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG0_CH0_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG0_CH0_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config0); + break; + case 1: + val = readl(&gis_regs->hw_gis_config0); + val &= ~(GIS_CONFIG0_CH1_MAPPING_MASK | GIS_CONFIG0_CH1_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG0_CH1_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG0_CH1_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config0); + break; + case 2: + val = readl(&gis_regs->hw_gis_config0); + val &= ~(GIS_CONFIG0_CH2_MAPPING_MASK | GIS_CONFIG0_CH2_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG0_CH2_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG0_CH2_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config0); + break; + case 3: + val = readl(&gis_regs->hw_gis_config0); + val &= ~(GIS_CONFIG0_CH3_MAPPING_MASK | GIS_CONFIG0_CH3_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG0_CH3_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG0_CH3_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config0); + break; + case 4: + val = readl(&gis_regs->hw_gis_config1); + val &= ~(GIS_CONFIG1_CH4_MAPPING_MASK | GIS_CONFIG1_CH4_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG1_CH4_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG1_CH4_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config1); + break; + case 5: + val = readl(&gis_regs->hw_gis_config1); + val &= ~(GIS_CONFIG1_CH5_MAPPING_MASK | GIS_CONFIG1_CH5_NUM_MASK); + val |= ch->ch_map << GIS_CONFIG1_CH5_MAPPING_SHIFT; + val |= ch->cmd_num << GIS_CONFIG1_CH5_NUM_SHIFT; + writel(val, &gis_regs->hw_gis_config1); + break; + default: + printf("Error channel num\n"); + } + + /* Config command */ + for (i = 0; i < ch->cmd_num; i++) { + val = readl(&gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET); + val &= ~(0xFF << (COMMAND_OPCODE_SHIFT * i)); + val |= ch->cmd_data[i].cmd_opc << (COMMAND_OPCODE_SHIFT * i); + writel(val, &gis_regs->hw_gis_ch0_ctrl + ch->ch_num * CHANNEL_OFFSET); + + reg_offset = ch->ch_num * CHANNEL_OFFSET + i * COMMAND_OFFSET; + writel(ch->cmd_data[i].addr, &gis_regs->hw_gis_ch0_addr0 + reg_offset); + writel(ch->cmd_data[i].data, &gis_regs->hw_gis_ch0_data0 + reg_offset); + } +} + +static void gis_channel_init(void) +{ + struct channel_param ch; + int ret; + u32 addr0, data0, addr1, data1; + u32 val; + + /* Restart the GIS block */ + ret = mxs_reset_block(&gis_regs->hw_gis_ctrl_reg); + if (ret) { + debug("MXS GIS: Block reset timeout\n"); + return; + } + + writel((u32)csibuf0, &gis_regs->hw_gis_fb0); + writel((u32)csibuf1, &gis_regs->hw_gis_fb1); + writel((u32)fb0, &gis_regs->hw_gis_pxp_fb0); + writel((u32)fb1, &gis_regs->hw_gis_pxp_fb1); + + /* Config channel 0 -- CSI clean interrupt */ + addr0 = (u32)&csi_regs->csi_csisr; + data0 = BIT_DMA_TSF_DONE_FB1 | BIT_DMA_TSF_DONE_FB2 | BIT_SOF_INT; + ch.ch_num = 0; + ch.ch_map = CH_MAPPING_CSI_ISR; + ch.cmd_num = 1; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + config_channel(&ch); + + /* Config channel 1 -- CSI set next framebuffer addr */ + addr0 = (u32)&csi_regs->csi_csidmasa_fb1; + data0 = (u32)&csi_regs->csi_csidmasa_fb2; + ch.ch_num = 1; + ch.ch_map = CH_MAPPING_CSI_FB_UPDATE; + ch.cmd_num = 1; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_CSI; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = CSI0_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + config_channel(&ch); + + /* Config channel 2 -- PXP clear interrupt and set framebuffer */ + addr0 = (u32)&pxp_regs->pxp_stat_clr; + data0 = BM_PXP_STAT_IRQ; + addr1 = (u32)&pxp_regs->pxp_out_buf; + data1 = 0; + ch.ch_num = 2; + ch.ch_map = CH_MAPPING_PXP_ISR; + ch.cmd_num = 2; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_DATA; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + ch.cmd_data[1].cmd_bits.opcode = CMD_WR_FB_PXP_OUT; + ch.cmd_data[1].cmd_bits.alu = ALU_AND; + ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1; + ch.cmd_data[1].data = data1; + config_channel(&ch); + + /* Config channel 3 -- LCDIF set framebuffer to display */ + addr0 = (u32)&lcdif_regs->hw_lcdif_next_buf; + data0 = 0; + ch.ch_num = 3; + ch.ch_map = CH_MAPPING_LCDIF_FB_UPDATE; + ch.cmd_num = 1; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_LCDIF; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = ((lcdif_sel == 0) ? LCDIF0_SEL : LCDIF1_SEL) << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + config_channel(&ch); + + /* Config channel 4 -- PXP kick to process next framebuffer */ + addr0 = (u32)&pxp_regs->pxp_ps_buf; + data0 = 0; + addr1 = (u32)&pxp_regs->pxp_ctrl; + data1 = BM_PXP_CTRL_IRQ_ENABLE | BM_PXP_CTRL_ENABLE; + ch.ch_num = 4; + ch.ch_map = CH_MAPPING_PXP_KICK; + ch.cmd_num = 2; + ch.cmd_data[0].cmd_bits.opcode = CMD_WR_FB_PXP_IN; + ch.cmd_data[0].cmd_bits.alu = ALU_AND; + ch.cmd_data[0].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[0].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr0; + ch.cmd_data[0].data = data0; + ch.cmd_data[1].cmd_bits.opcode = CMD_WR_DATA; + ch.cmd_data[1].cmd_bits.alu = ALU_AND; + ch.cmd_data[1].cmd_bits.acc_neg = GIS_CH_CTRL_CMD_ACC_NO_NEGATE; + ch.cmd_data[1].addr = PXP_SEL << GIS_CH_ADDR_SEL_SHIFT | addr1; + ch.cmd_data[1].data = data1; + config_channel(&ch); + + /* start gis */ + val = readl(&gis_regs->hw_gis_ctrl); + if (lcdif_sel == 1) + val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF1; + else + val |= GIS_CTRL_ENABLE_SET | GIS_CTRL_LCDIF_SEL_LCDIF0; + writel(val, &gis_regs->hw_gis_ctrl); +} + +void mxc_disable_gis(void) +{ + u32 val; + + if (!gis_running) + return; + + /* Stop gis */ + val = GIS_CTRL_SFTRST_SET | GIS_CTRL_CLK_GATE_SET; + writel(val, &gis_regs->hw_gis_ctrl); + + /* Stop pxp */ + mxs_reset_block(&pxp_regs->pxp_ctrl_reg); + val = BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE; + writel(val , &pxp_regs->pxp_ctrl); + + csi_disable(); + + vadc_power_down(); +} + +void mxc_enable_gis(void) +{ + struct sensor_data sensor; + struct csi_conf_param csi_conf; + struct pxp_config_data pxp_conf; + struct display_panel panel; + u32 csimemsize, pxpmemsize; + char const *gis_input = env_get("gis"); + + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_CSI)) { + printf("CSI@0x%x is fused, disable it\n", CSI1_BASE_ADDR); + return; + } + } + + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_PXP)) { + printf("PXP@0x%x is fused, disable it\n", PXP_BASE_ADDR); + return; + } + } + + gis_regs = (struct mxs_gis_regs *)GIS_BASE_ADDR; + pxp_regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + csi_regs = (struct mxs_csi_regs *)CSI1_BASE_ADDR; + + gis_running = false; + + if (gis_input != NULL && !strcmp(gis_input, "vadc")) { + printf("gis input --- vadc\n"); + /* vadc_in 0 */ + vadc_config(0); + + /* Get vadc mode */ + vadc_get_std(&sensor); + } else { + printf("gis input --- No input\n"); + return; + } + + /* Get display mode */ + mxs_lcd_get_panel(&panel); + + lcdif_regs = (struct mxs_lcdif_regs *)panel.reg_base; + if (panel.reg_base == LCDIF2_BASE_ADDR) + lcdif_sel = 1; + else + lcdif_sel = 0; + + /* Allocate csi buffer */ + if (sensor.pixel_fmt == FMT_YUV444) { + csimemsize = sensor.width * sensor.height * 4; + csi_conf.bpp = 32; + } else { + csimemsize = sensor.width * sensor.height * 2; + csi_conf.bpp = 16; + } + + pxpmemsize = panel.width * panel.height * panel.gdfbytespp; + csibuf0 = malloc(csimemsize); + csibuf1 = malloc(csimemsize); + fb0 = malloc(pxpmemsize); + fb1 = malloc(pxpmemsize); + if (!csibuf0 || !csibuf1 || !fb0 || !fb1) { + printf("MXSGIS: Error allocating csibuffer!\n"); + return; + } + /* Wipe framebuffer */ + memset(csibuf0, 0, csimemsize); + memset(csibuf1, 0, csimemsize); + memset(fb0, 0, pxpmemsize); + memset(fb1, 0, pxpmemsize); + + /*config csi */ + csi_conf.width = sensor.width; + csi_conf.height = sensor.height; + csi_conf.btvmode = true; + csi_conf.std = sensor.std_id; + csi_conf.fb0addr = csibuf0; + csi_conf.fb1addr = csibuf1; + csi_config(&csi_conf); + + /* config pxp */ + pxp_conf.s0_param.pixel_fmt = sensor.pixel_fmt; + pxp_conf.s0_param.width = sensor.width; + pxp_conf.s0_param.height = sensor.height; + pxp_conf.s0_param.stride = sensor.width * csi_conf.bpp/8; + pxp_conf.s0_param.paddr = csibuf0; + + switch (panel.gdfindex) { + case GDF_32BIT_X888RGB: + pxp_conf.out_param.pixel_fmt = FMT_RGB888; + break; + case GDF_16BIT_565RGB: + pxp_conf.out_param.pixel_fmt = FMT_RGB565; + break; + default: + printf("GIS unsupported format!"); + } + + pxp_conf.out_param.width = panel.width; + pxp_conf.out_param.height = panel.height; + pxp_conf.out_param.stride = pxp_conf.out_param.width * panel.gdfbytespp; + pxp_conf.out_param.paddr = fb0; + pxp_config(&pxp_conf); + + gis_running = true; + + /* Config gis */ + gis_channel_init(); +} diff --git a/drivers/video/mxc_gis.h b/drivers/video/mxc_gis.h new file mode 100644 index 00000000000..a1290c42418 --- /dev/null +++ b/drivers/video/mxc_gis.h @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +#ifndef MXC_GIS_H +#define MXC_GIS_H + +#include + +struct mxs_gis_regs { + mxs_reg_32(hw_gis_ctrl) /* 0x00 */ + mxs_reg_32(hw_gis_config0) /* 0x10 */ + mxs_reg_32(hw_gis_config1) /* 0x20 */ + mxs_reg_32(hw_gis_fb0) /* 0x30 */ + mxs_reg_32(hw_gis_fb1) /* 0x40 */ + mxs_reg_32(hw_gis_pxp_fb0) /* 0x50 */ + mxs_reg_32(hw_gis_pxp_fb1) /* 0x60 */ + + mxs_reg_32(hw_gis_ch0_ctrl) /* 0x70 */ + mxs_reg_32(hw_gis_ch0_addr0) /* 0x80 */ + mxs_reg_32(hw_gis_ch0_data0) /* 0x90 */ + mxs_reg_32(hw_gis_ch0_addr1) /* 0xa0 */ + mxs_reg_32(hw_gis_ch0_data1) /* 0xb0 */ + mxs_reg_32(hw_gis_ch0_addr2) /* 0xc0 */ + mxs_reg_32(hw_gis_ch0_data2) /* 0xd0 */ + mxs_reg_32(hw_gis_ch0_addr3) /* 0xe0 */ + mxs_reg_32(hw_gis_ch0_data3) /* 0xf0 */ + + mxs_reg_32(hw_gis_ch1_ctrl) /* 0x100 */ + mxs_reg_32(hw_gis_ch1_addr0) /* 0x110 */ + mxs_reg_32(hw_gis_ch1_data0) /* 0x120 */ + mxs_reg_32(hw_gis_ch1_addr1) /* 0x130 */ + mxs_reg_32(hw_gis_ch1_data1) /* 0x140 */ + mxs_reg_32(hw_gis_ch1_addr2) /* 0x150 */ + mxs_reg_32(hw_gis_ch1_data2) /* 0x160 */ + mxs_reg_32(hw_gis_ch1_addr3) /* 0x170 */ + mxs_reg_32(hw_gis_ch1_data3) /* 0x180 */ + + mxs_reg_32(hw_gis_ch2_ctrl) /* 0x190 */ + mxs_reg_32(hw_gis_ch2_addr0) /* 0x1a0 */ + mxs_reg_32(hw_gis_ch2_data0) /* 0x1b0 */ + mxs_reg_32(hw_gis_ch2_addr1) /* 0x1c0 */ + mxs_reg_32(hw_gis_ch2_data1) /* 0x1d0 */ + mxs_reg_32(hw_gis_ch2_addr2) /* 0x1e0 */ + mxs_reg_32(hw_gis_ch2_data2) /* 0x1f0 */ + mxs_reg_32(hw_gis_ch2_addr3) /* 0x200 */ + mxs_reg_32(hw_gis_ch2_data3) /* 0x210 */ + + mxs_reg_32(hw_gis_ch3_ctrl) /* 0x220 */ + mxs_reg_32(hw_gis_ch3_addr0) /* 0x230 */ + mxs_reg_32(hw_gis_ch3_data0) /* 0x240 */ + mxs_reg_32(hw_gis_ch3_addr1) /* 0x250 */ + mxs_reg_32(hw_gis_ch3_data1) /* 0x260 */ + mxs_reg_32(hw_gis_ch3_addr2) /* 0x270 */ + mxs_reg_32(hw_gis_ch3_data2) /* 0x280 */ + mxs_reg_32(hw_gis_ch3_addr3) /* 0x290 */ + mxs_reg_32(hw_gis_ch3_data3) /* 0x2a0 */ + + mxs_reg_32(hw_gis_ch4_ctrl) /* 0x2b0 */ + mxs_reg_32(hw_gis_ch4_addr0) /* 0x2c0 */ + mxs_reg_32(hw_gis_ch4_data0) /* 0x2d0 */ + mxs_reg_32(hw_gis_ch4_addr1) /* 0x2e0 */ + mxs_reg_32(hw_gis_ch4_data1) /* 0x2f0 */ + mxs_reg_32(hw_gis_ch4_addr2) /* 0x300 */ + mxs_reg_32(hw_gis_ch4_data2) /* 0x310 */ + mxs_reg_32(hw_gis_ch4_addr3) /* 0x320 */ + mxs_reg_32(hw_gis_ch4_data3) /* 0x330 */ + + mxs_reg_32(hw_gis_ch5_ctrl) /* 0x340 */ + mxs_reg_32(hw_gis_ch5_addr0) /* 0x350 */ + mxs_reg_32(hw_gis_ch5_data0) /* 0x360 */ + mxs_reg_32(hw_gis_ch5_addr1) /* 0x370 */ + mxs_reg_32(hw_gis_ch5_data1) /* 0x380 */ + mxs_reg_32(hw_gis_ch5_addr2) /* 0x390 */ + mxs_reg_32(hw_gis_ch5_data2) /* 0x3a0 */ + mxs_reg_32(hw_gis_ch5_addr3) /* 0x3b0 */ + mxs_reg_32(hw_gis_ch5_data3) /* 0x3c0 */ + + mxs_reg_32(hw_gis_debug0) /* 0x3d0 */ + mxs_reg_32(hw_gis_debug1) /* 0x3e0 */ + mxs_reg_32(hw_gis_version) /* 0x3f0 */ +}; + +/* register bit */ +#define GIS_CTRL_SFTRST_CLR 0 +#define GIS_CTRL_SFTRST_SET (1 << 31) +#define GIS_CTRL_CLK_GATE_CLR 0 +#define GIS_CTRL_CLK_GATE_SET (1 << 30) +#define GIS_CTRL_LCDIF1_IRQ_POL_LOW 0 +#define GIS_CTRL_LCDIF1_IRQ_POL_HIGH (1 << 8) +#define GIS_CTRL_LCDIF0_IRQ_POL_LOW 0 +#define GIS_CTRL_LCDIF0_IRQ_POL_HIGH (1 << 7) +#define GIS_CTRL_PXP_IRQ_POL_LOW 0 +#define GIS_CTRL_PXP_IRQ_POL_HIGH (1 << 6) +#define GIS_CTRL_CSI1_IRQ_POL_LOW 0 +#define GIS_CTRL_CSI1_IRQ_POL_HIGH (1 << 5) +#define GIS_CTRL_CSI0_IRQ_POL_LOW 0 +#define GIS_CTRL_CSI0_IRQ_POL_HIGH (1 << 4) +#define GIS_CTRL_CSI_SEL_CSI0 0 +#define GIS_CTRL_CSI_SEL_CSI1 (1 << 3) +#define GIS_CTRL_LCDIF_SEL_LCDIF0 0 +#define GIS_CTRL_LCDIF_SEL_LCDIF1 (1 << 2) +#define GIS_CTRL_FB_START_FB0 0 +#define GIS_CTRL_FB_START_FB1 (1 << 1) +#define GIS_CTRL_ENABLE_CLR 0 +#define GIS_CTRL_ENABLE_SET (1 << 0) + +#define GIS_CONFIG0_CH3_NUM_MASK (0x7 << 27) +#define GIS_CONFIG0_CH3_NUM_SHIFT 27 +#define GIS_CONFIG0_CH3_MAPPING_MASK (0x7 << 24) +#define GIS_CONFIG0_CH3_MAPPING_SHIFT 24 +#define GIS_CONFIG0_CH2_NUM_MASK (0x7 << 19) +#define GIS_CONFIG0_CH2_NUM_SHIFT 19 +#define GIS_CONFIG0_CH2_MAPPING_MASK (0x7 << 16) +#define GIS_CONFIG0_CH2_MAPPING_SHIFT 16 +#define GIS_CONFIG0_CH1_NUM_MASK (0x7 << 11) +#define GIS_CONFIG0_CH1_NUM_SHIFT 11 +#define GIS_CONFIG0_CH1_MAPPING_MASK (0x7 << 8) +#define GIS_CONFIG0_CH1_MAPPING_SHIFT 8 +#define GIS_CONFIG0_CH0_NUM_MASK (0x7 << 3) +#define GIS_CONFIG0_CH0_NUM_SHIFT 3 +#define GIS_CONFIG0_CH0_MAPPING_MASK (0x7 << 0) +#define GIS_CONFIG0_CH0_MAPPING_SHIFT 0 + +#define GIS_CONFIG1_CH5_NUM_MASK (0x7 << 11) +#define GIS_CONFIG1_CH5_NUM_SHIFT 11 +#define GIS_CONFIG1_CH5_MAPPING_MASK (0x7 << 8) +#define GIS_CONFIG1_CH5_MAPPING_SHIFT 8 +#define GIS_CONFIG1_CH4_NUM_MASK (0x7 << 3) +#define GIS_CONFIG1_CH4_NUM_SHIFT 3 +#define GIS_CONFIG1_CH4_MAPPING_MASK (0x7 << 0) +#define GIS_CONFIG1_CH4_MAPPING_SHIFT 0 + +#define GIS_CH_CTRL_CMD3_ACC_MASK (0x1 << 31) +#define GIS_CH_CTRL_CMD3_ACC_SHIFT 31 +#define GIS_CH_CTRL_CMD3_ALU_MASK (0x7 << 28) +#define GIS_CH_CTRL_CMD3_ALU_SHIFT 28 +#define GIS_CH_CTRL_CMD3_OPCODE_MASK (0xF << 24) +#define GIS_CH_CTRL_CMD3_OPCODE_SHIFT 24 +#define GIS_CH_CTRL_CMD2_ACC_MASK (0x1 << 23) +#define GIS_CH_CTRL_CMD2_ACC_SHIFT 23 +#define GIS_CH_CTRL_CMD2_ALU_MASK (0xF << 20) +#define GIS_CH_CTRL_CMD2_ALU_SHIFT 20 +#define GIS_CH_CTRL_CMD2_OPCODE_MASK (0xF << 16) +#define GIS_CH_CTRL_CMD2_OPCODE_SHIFT 16 +#define GIS_CH_CTRL_CMD1_ACC_MASK (0x1 << 15) +#define GIS_CH_CTRL_CMD1_ACC_SHIFT 15 +#define GIS_CH_CTRL_CMD1_ALU_MASK (0x7 << 12) +#define GIS_CH_CTRL_CMD1_ALU_SHIFT 12 +#define GIS_CH_CTRL_CMD1_OPCODE_MASK (0xF << 8) +#define GIS_CH_CTRL_CMD1_OPCODE_SHIFT 8 +#define GIS_CH_CTRL_CMD0_ACC_MASK (0x1 << 7) +#define GIS_CH_CTRL_CMD0_ACC_SHIFT 7 +#define GIS_CH_CTRL_CMD0_ALU_MASK (0x7 << 4) +#define GIS_CH_CTRL_CMD0_ALU_SHIFT 4 +#define GIS_CH_CTRL_CMD0_OPCODE_MASK (0xF << 0) +#define GIS_CH_CTRL_CMD0_OPCODE_SHIFT 0 + +#define GIS_CH_CTRL_CMD_ACC_NO_NEGATE 0 +#define GIS_CH_CTRL_CMD_ACC_NEGATE 1 + +#define GIS_CH_ADDR_SEL_MASK (0xF8 << 27) +#define GIS_CH_ADDR_SEL_LCDIF1 (0x1 << 31) +#define GIS_CH_ADDR_SEL_LCDIF0 (0x1 << 30) +#define GIS_CH_ADDR_SEL_PXP (0x1 << 29) +#define GIS_CH_ADDR_SEL_CSI1 (0x1 << 28) +#define GIS_CH_ADDR_SEL_CSI0 (0x1 << 27) +#define GIS_CH_ADDR_SEL_SHIFT 27 +#define GIS_CH_ADDR_ADDR_MASK 0x7FFFFFF +#define GIS_CH_ADDR_ADDR_SHIFT 0 + +#endif + diff --git a/drivers/video/mxc_pxp.c b/drivers/video/mxc_pxp.c new file mode 100644 index 00000000000..41cedfc98ca --- /dev/null +++ b/drivers/video/mxc_pxp.c @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "mxc_pxp.h" + +#define BV_PXP_OUT_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_OUT_CTRL_FORMAT__RGB555 0xC +#define BV_PXP_OUT_CTRL_FORMAT__RGB444 0xD +#define BV_PXP_OUT_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_OUT_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_OUT_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_OUT_CTRL_FORMAT__VYUY1P422 0x13 + +#define BV_PXP_PS_CTRL_FORMAT__RGB888 0x4 +#define BV_PXP_PS_CTRL_FORMAT__RGB565 0xE +#define BV_PXP_PS_CTRL_FORMAT__YUV1P444 0x10 +#define BV_PXP_PS_CTRL_FORMAT__UYVY1P422 0x12 +#define BV_PXP_PS_CTRL_FORMAT__VYUY1P422 0x13 + +#define BP_PXP_PS_CTRL_SWAP 5 +#define BM_PXP_PS_CTRL_SWAP 0x000000E0 +#define BF_PXP_PS_CTRL_SWAP(v) \ + (((v) << 5) & BM_PXP_PS_CTRL_SWAP) + +#define PXP_DOWNSCALE_THRESHOLD 0x4000 + +static void pxp_set_ctrl(struct pxp_config_data *pxp_conf) +{ + u32 ctrl; + u32 fmt_ctrl; + int need_swap = 0; /* to support YUYV and YVYU formats */ + struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + + /* Configure S0 input format */ + switch (pxp_conf->s0_param.pixel_fmt) { + case FMT_YUV444: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__YUV1P444; + break; + case FMT_UYVY: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + break; + case FMT_YUYV: + fmt_ctrl = BV_PXP_PS_CTRL_FORMAT__UYVY1P422; + need_swap = 1; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_PS_CTRL_FORMAT(fmt_ctrl) | BF_PXP_PS_CTRL_SWAP(need_swap); + writel(ctrl, ®s->pxp_ps_ctrl); + + /* Configure output format based on out_channel format */ + switch (pxp_conf->out_param.pixel_fmt) { + case FMT_RGB565: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB565; + break; + case FMT_RGB888: + fmt_ctrl = BV_PXP_OUT_CTRL_FORMAT__RGB888; + break; + default: + fmt_ctrl = 0; + } + + ctrl = BF_PXP_OUT_CTRL_FORMAT(fmt_ctrl); + writel(ctrl, ®s->pxp_out_ctrl); +} + +static int pxp_set_scaling(struct pxp_config_data *pxp_conf) +{ + int ret = 0; + u32 xscale, yscale, s0scale; + u32 decx, decy, xdec = 0, ydec = 0; + struct pxp_layer_param *s0_params = &pxp_conf->s0_param; + struct pxp_layer_param *out_params = &pxp_conf->out_param; + struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + + decx = s0_params->width / out_params->width; + decy = s0_params->height / out_params->height; + if (decx > 1) { + if (decx >= 2 && decx < 4) { + decx = 2; + xdec = 1; + } else if (decx >= 4 && decx < 8) { + decx = 4; + xdec = 2; + } else if (decx >= 8) { + decx = 8; + xdec = 3; + } + xscale = s0_params->width * 0x1000 / + (out_params->width * decx); + } else { + if ((s0_params->pixel_fmt == FMT_YUYV) || + (s0_params->pixel_fmt == FMT_UYVY) || + (s0_params->pixel_fmt == FMT_YUV444)) + xscale = (s0_params->width - 1) * 0x1000 / + (out_params->width - 1); + else + xscale = (s0_params->width - 2) * 0x1000 / + (out_params->width - 1); + } + if (decy > 1) { + if (decy >= 2 && decy < 4) { + decy = 2; + ydec = 1; + } else if (decy >= 4 && decy < 8) { + decy = 4; + ydec = 2; + } else if (decy >= 8) { + decy = 8; + ydec = 3; + } + yscale = s0_params->height * 0x1000 / + (out_params->height * decy); + } else + yscale = (s0_params->height - 1) * 0x1000 / + (out_params->height - 1); + + writel((xdec << 10) | (ydec << 8), ®s->pxp_ps_ctrl); + + if (xscale > PXP_DOWNSCALE_THRESHOLD) + xscale = PXP_DOWNSCALE_THRESHOLD; + if (yscale > PXP_DOWNSCALE_THRESHOLD) + yscale = PXP_DOWNSCALE_THRESHOLD; + s0scale = BF_PXP_PS_SCALE_YSCALE(yscale) | + BF_PXP_PS_SCALE_XSCALE(xscale); + writel(s0scale, ®s->pxp_ps_scale); + + pxp_set_ctrl(pxp_conf); + + return ret; +} + +void pxp_power_down(void) +{ + struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + u32 val; + + val = BM_PXP_CTRL_SFTRST | BM_PXP_CTRL_CLKGATE; + writel(val , ®s->pxp_ctrl); +} + +void pxp_config(struct pxp_config_data *pxp_conf) +{ + struct mxs_pxp_regs *regs = (struct mxs_pxp_regs *)PXP_BASE_ADDR; + + /* reset */ + mxs_reset_block(®s->pxp_ctrl_reg); + + /* output buffer */ + if (pxp_conf->out_param.pixel_fmt == FMT_RGB888) + writel(BV_PXP_OUT_CTRL_FORMAT__RGB888, ®s->pxp_out_ctrl); + else + writel(BV_PXP_OUT_CTRL_FORMAT__RGB565, ®s->pxp_out_ctrl); + + writel((u32)pxp_conf->out_param.paddr, ®s->pxp_out_buf); + + writel(pxp_conf->out_param.stride, ®s->pxp_out_pitch); + writel((pxp_conf->out_param.width - 1) << 16 | + (pxp_conf->out_param.height - 1), + ®s->pxp_out_lrc); + + /* scale needed */ + writel(0, ®s->pxp_out_ps_ulc); + writel((pxp_conf->out_param.width - 1) << 16 | + (pxp_conf->out_param.height - 1), + ®s->pxp_out_ps_lrc); + pxp_set_scaling(pxp_conf); + + writel(0, ®s->pxp_out_as_ulc); + writel(0, ®s->pxp_out_as_lrc); + + /* input buffer */ + if (pxp_conf->s0_param.pixel_fmt == FMT_YUV444) + writel(BV_PXP_PS_CTRL_FORMAT__YUV1P444, ®s->pxp_ps_ctrl); + else if (pxp_conf->s0_param.pixel_fmt == FMT_YUYV) + writel(BV_PXP_PS_CTRL_FORMAT__UYVY1P422 | BF_PXP_PS_CTRL_SWAP(1), + ®s->pxp_ps_ctrl); + else if (pxp_conf->s0_param.pixel_fmt == FMT_UYVY) + writel(BV_PXP_PS_CTRL_FORMAT__UYVY1P422, ®s->pxp_ps_ctrl); + else + printf("%s, unsupport fmt\n", __func__); + + writel((u32)pxp_conf->s0_param.paddr, ®s->pxp_ps_buf); + writel(pxp_conf->s0_param.stride, ®s->pxp_ps_pitch); + writel(0, ®s->pxp_ps_background); + writel(0x84ab01f0, ®s->pxp_csc1_coef0); + writel(0x01980204, ®s->pxp_csc1_coef1); + writel(0x0730079c, ®s->pxp_csc1_coef2); + + /* pxp start */ + writel(BM_PXP_CTRL_IRQ_ENABLE | BM_PXP_CTRL_ENABLE, ®s->pxp_ctrl); +} diff --git a/drivers/video/mxc_pxp.h b/drivers/video/mxc_pxp.h new file mode 100644 index 00000000000..0c50c5cec50 --- /dev/null +++ b/drivers/video/mxc_pxp.h @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +#ifndef MXC_PXP_H +#define MXC_PXP_H + +#include + +struct mxs_pxp_regs{ + mxs_reg_32(pxp_ctrl) /* 0x00 */ + mxs_reg_32(pxp_stat) /* 0x10 */ + mxs_reg_32(pxp_out_ctrl) /* 0x20 */ + mxs_reg_32(pxp_out_buf) /* 0x30 */ + mxs_reg_32(pxp_out_buf2) /* 0x40 */ + mxs_reg_32(pxp_out_pitch) /* 0x50 */ + mxs_reg_32(pxp_out_lrc) /* 0x60 */ + mxs_reg_32(pxp_out_ps_ulc) /* 0x70 */ + mxs_reg_32(pxp_out_ps_lrc) /* 0x80 */ + mxs_reg_32(pxp_out_as_ulc) /* 0x90 */ + mxs_reg_32(pxp_out_as_lrc) /* 0xa0 */ + mxs_reg_32(pxp_ps_ctrl) /* 0xb0 */ + mxs_reg_32(pxp_ps_buf) /* 0xc0 */ + mxs_reg_32(pxp_ps_ubuf) /* 0xd0 */ + mxs_reg_32(pxp_ps_vbuf) /* 0xe0 */ + mxs_reg_32(pxp_ps_pitch) /* 0xf0 */ + mxs_reg_32(pxp_ps_background) /* 0x100 */ + mxs_reg_32(pxp_ps_scale) /* 0x110 */ + mxs_reg_32(pxp_ps_offset) /* 0x120 */ + mxs_reg_32(pxp_ps_clrkeylow) /* 0x130 */ + mxs_reg_32(pxp_ps_clrkeyhigh) /* 0x140 */ + mxs_reg_32(pxp_as_ctrl) /* 0x150 */ + mxs_reg_32(pxp_as_buf) /* 0x160 */ + mxs_reg_32(pxp_as_pitch) /* 0x170 */ + mxs_reg_32(pxp_as_clrkeylow) /* 0x180 */ + mxs_reg_32(pxp_as_clrkeyhigh) /* 0x190 */ + mxs_reg_32(pxp_csc1_coef0) /* 0x1a0 */ + mxs_reg_32(pxp_csc1_coef1) /* 0x1b0 */ + mxs_reg_32(pxp_csc1_coef2) /* 0x1c0 */ + mxs_reg_32(pxp_csc2_ctrl) /* 0x1d0 */ + mxs_reg_32(pxp_csc2_coef0) /* 0x1e0 */ + mxs_reg_32(pxp_csc2_coef1) /* 0x1f0 */ + mxs_reg_32(pxp_csc2_coef2) /* 0x200 */ + mxs_reg_32(pxp_csc2_coef3) /* 0x210 */ + mxs_reg_32(pxp_csc2_coef4) /* 0x220 */ + mxs_reg_32(pxp_csc2_coef5) /* 0x230 */ + mxs_reg_32(pxp_lut_ctrl) /* 0x240 */ + mxs_reg_32(pxp_lut_addr) /* 0x250 */ + mxs_reg_32(pxp_lut_data) /* 0x260 */ + mxs_reg_32(pxp_lut_extmem) /* 0x270 */ + mxs_reg_32(pxp_cfa) /* 0x280 */ + mxs_reg_32(pxp_hist_ctrl) /* 0x290 */ + mxs_reg_32(pxp_hist2_param) /* 0x2a0 */ + mxs_reg_32(pxp_hist4_param) /* 0x2b0 */ + mxs_reg_32(pxp_hist8_param0) /* 0x2c0 */ + mxs_reg_32(pxp_hist8_param1) /* 0x2d0 */ + mxs_reg_32(pxp_hist16_param0) /* 0x2e0 */ + mxs_reg_32(pxp_hist16_param1) /* 0x2f0 */ + mxs_reg_32(pxp_hist16_param2) /* 0x300 */ + mxs_reg_32(pxp_hist16_param3) /* 0x310 */ + mxs_reg_32(pxp_power) /* 0x320 */ + uint32_t reserved1[4*13]; + mxs_reg_32(pxp_next) /* 0x400 */ +}; + +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 + +#define BM_PXP_STAT_IRQ 0x00000001 + +#define BP_PXP_OUT_CTRL_FORMAT 0 +#define BM_PXP_OUT_CTRL_FORMAT 0x0000001F +#define BF_PXP_OUT_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_OUT_CTRL_FORMAT) + +#define HW_PXP_PS_SCALE (0x00000110) + +#define BM_PXP_PS_SCALE_RSVD2 0x80000000 +#define BP_PXP_PS_SCALE_YSCALE 16 +#define BM_PXP_PS_SCALE_YSCALE 0x7FFF0000 +#define BF_PXP_PS_SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_PS_SCALE_YSCALE) +#define BM_PXP_PS_SCALE_RSVD1 0x00008000 +#define BP_PXP_PS_SCALE_XSCALE 0 +#define BM_PXP_PS_SCALE_XSCALE 0x00007FFF +#define BF_PXP_PS_SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_PS_SCALE_XSCALE) + +#define BP_PXP_PS_CTRL_SWAP 5 +#define BM_PXP_PS_CTRL_SWAP 0x000000E0 +#define BF_PXP_PS_CTRL_SWAP(v) \ + (((v) << 5) & BM_PXP_PS_CTRL_SWAP) +#define BP_PXP_PS_CTRL_FORMAT 0 +#define BM_PXP_PS_CTRL_FORMAT 0x0000001F +#define BF_PXP_PS_CTRL_FORMAT(v) \ + (((v) << 0) & BM_PXP_PS_CTRL_FORMAT) +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 + +struct pxp_layer_param { + unsigned short width; + unsigned short height; + unsigned short stride; /* aka pitch */ + unsigned int pixel_fmt; + void *paddr; +}; + +struct pxp_config_data { + struct pxp_layer_param s0_param; + struct pxp_layer_param out_param; +}; + +void pxp_config(struct pxp_config_data *pxp_conf); + +#endif diff --git a/drivers/video/mxc_vadc.c b/drivers/video/mxc_vadc.c new file mode 100644 index 00000000000..4fa49c1d7a7 --- /dev/null +++ b/drivers/video/mxc_vadc.c @@ -0,0 +1,374 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "mxc_vadc.h" + +#define reg32_write(addr, val) __raw_writel(val, addr) +#define reg32_read(addr) __raw_readl(addr) +#define reg32setbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos)))) + +#define reg32clrbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) & (0xFFFFFFFF ^ (1<<(bitpos))))) + +void __iomem *vafe_regbase; +void __iomem *vdec_regbase; + +enum { + STD_NTSC = 0, + STD_PAL, +}; + +/* Video format structure. */ +struct video_fmt_t{ + int v4l2_id; /* Video for linux ID. */ + char name[16]; /* Name (e.g., "NTSC", "PAL", etc.) */ + u16 active_width; /* Active width. */ + u16 active_height; /* Active height. */ +}; + +/* Description of video formats supported. + * + * PAL: active=720x576. + * NTSC:active=720x480. + */ +static struct video_fmt_t video_fmts[] = { + /* NTSC */ + { + .v4l2_id = STD_NTSC, + .name = "NTSC", + .active_width = 720, + .active_height = 480, + }, + /* (B, G, H, I, N) PAL */ + { + .v4l2_id = STD_PAL, + .name = "PAL", + .active_width = 720, + .active_height = 576, + }, +}; + +static void afe_voltage_clampingmode(void) +{ + reg32_write(AFE_CLAMP, 0x07); + reg32_write(AFE_CLMPAMP, 0x60); + reg32_write(AFE_CLMPDAT, 0xF0); +} + +static void afe_alwayson_clampingmode(void) +{ + reg32_write(AFE_CLAMP, 0x15); + reg32_write(AFE_CLMPDAT, 0x08); + reg32_write(AFE_CLMPAMP, 0x00); +} + +static void afe_init(void) +{ + reg32_write(AFE_PDBUF, 0x1f); + reg32_write(AFE_PDADC, 0x0f); + reg32_write(AFE_PDSARH, 0x01); + reg32_write(AFE_PDSARL, 0xff); + reg32_write(AFE_PDADCRFH, 0x01); + reg32_write(AFE_PDADCRFL, 0xff); + reg32_write(AFE_ICTRL, 0x3a); + reg32_write(AFE_ICTLSTG, 0x1e); + + reg32_write(AFE_RCTRLSTG, 0x1e); + reg32_write(AFE_INPBUF, 0x035); + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_ADCDGN, 0x40); + reg32_write(AFE_TSTSEL, 0x10); + + reg32_write(AFE_ACCTST, 0x07); + + reg32_write(AFE_BGREG, 0x08); + + reg32_write(AFE_ADCGN, 0x09); + + /* set current controlled clamping + * always on, low current */ + reg32_write(AFE_CLAMP, 0x11); + reg32_write(AFE_CLMPAMP, 0x08); +} + +static void vdec_mode_timing_init(u32 std) +{ + if (std == STD_NTSC) { + /* NTSC 720x480 */ + printf("NTSC\n"); + reg32_write(VDEC_HACTS, 0x66); + reg32_write(VDEC_HACTE, 0x24); + + reg32_write(VDEC_VACTS, 0x29); + reg32_write(VDEC_VACTE, 0x04); + + /* set V Position */ + reg32_write(VDEC_VRTPOS, 0x2); + } else if (std == STD_PAL) { + /* PAL 720x576 */ + printf("PAL\n"); + reg32_write(VDEC_HACTS, 0x66); + reg32_write(VDEC_HACTE, 0x24); + + reg32_write(VDEC_VACTS, 0x29); + reg32_write(VDEC_VACTE, 0x04); + + /* set V Position */ + reg32_write(VDEC_VRTPOS, 0x6); + } else + printf("Error not support video mode\n"); + + /* set H Position */ + reg32_write(VDEC_HZPOS, 0x60); + + /* set H ignore start */ + reg32_write(VDEC_HSIGS, 0xf8); + + /* set H ignore end */ + reg32_write(VDEC_HSIGE, 0x18); +} + +/* +* vdec_init() +* Initialises the VDEC registers +* Returns: nothing +*/ +static void vdec_init(struct sensor_data *vadc) +{ + /* Get work mode PAL or NTSC + * delay 500ms wait vdec detect input format*/ + udelay(500*1000); + vadc_get_std(vadc); + + vdec_mode_timing_init(vadc->std_id); + + /* vcr detect threshold high, automatic detections */ + reg32_write(VDEC_VSCON2, 0); + + reg32_write(VDEC_BASE + 0x110, 0x01); + + /* set the noramp mode on the Hloop PLL. */ + reg32_write(VDEC_BASE+(0x14*4), 0x10); + + /* set the YC relative delay.*/ + reg32_write(VDEC_YCDEL, 0x90); + + /* setup the Hpll */ + reg32_write(VDEC_BASE+(0x13*4), 0x13); + + /* setup the 2d comb */ + /* set the gain of the Hdetail output to 3 + * set the notch alpha gain to 1 */ + reg32_write(VDEC_CFC2, 0x34); + + /* setup various 2d comb bits.*/ + reg32_write(VDEC_BASE+(0x02*4), 0x01); + reg32_write(VDEC_BASE+(0x03*4), 0x18); + reg32_write(VDEC_BASE+(0x04*4), 0x34); + + /* set the start of the burst gate */ + reg32_write(VDEC_BRSTGT, 0x30); + + /* set 1f motion gain */ + reg32_write(VDEC_BASE+(0x0f*4), 0x20); + + /* set the 1F chroma motion detector thresh for colour reverse detection */ + reg32_write(VDEC_THSH1, 0x02); + reg32_write(VDEC_BASE+(0x4a*4), 0x20); + reg32_write(VDEC_BASE+(0x4b*4), 0x08); + + reg32_write(VDEC_BASE+(0x4c*4), 0x08); + + /* set the threshold for the narrow/wide adaptive chroma BW */ + reg32_write(VDEC_BASE+(0x20*4), 0x20); + + /* turn up the colour with the new colour gain reg */ + /* hue: */ + reg32_write(VDEC_HUE, 0x00); + + /* cbgain: 22 B4 */ + reg32_write(VDEC_CBGN, 0xb4); + /* cr gain 80 */ + reg32_write(VDEC_CRGN, 0x80); + /* luma gain (contrast) */ + reg32_write(VDEC_CNTR, 0x80); + + /* setup the signed black level register, brightness */ + reg32_write(VDEC_BRT, 0x00); + + /* filter the standard detection + * enable the comb for the ntsc443 */ + reg32_write(VDEC_STDDBG, 0x23); + + /* setup chroma kill thresh for no chroma */ + reg32_write(VDEC_CHBTH, 0x0); + + /* set chroma loop to wider BW + * no set it to normal BW. i fixed the bw problem.*/ + reg32_write(VDEC_YCDEL, 0x00); + + /* set the compensation in the chroma loop for the Hloop + * set the ratio for the nonarithmetic 3d comb modes.*/ + reg32_write(VDEC_BASE + (0x1d*4), 0x90); + + /* set the threshold for the nonarithmetic mode for the 2d comb + * the higher the value the more Fc Fh offset we will tolerate before turning off the comb. */ + reg32_write(VDEC_BASE + (0x33*4), 0xa0); + + /* setup the bluescreen output colour */ + reg32_write(VDEC_BASE + (0x3d*4), 35); + reg32_write(VDEC_BLSCRCR, 114); + reg32_write(VDEC_BLSCRCB, 212); + + /* disable the active blanking */ + reg32_write(VDEC_BASE + (0x15*4), 0x02); + + /* setup the luma agc for automatic gain. */ + reg32_write(VDEC_LMAGC2, 0x5e); + reg32_write(VDEC_BASE + (0x40*4), 0x81); + + /* setup chroma agc */ + reg32_write(VDEC_CHAGC2, 0xa0); + reg32_write(VDEC_CHAGC1, 0x01); + + /* setup the MV thresh lower nibble + * setup the sync top cap, upper nibble */ + reg32_write(VDEC_BASE + (0x3a*4), 0x80); + reg32_write(VDEC_SHPIMP, 0x00); + + /* setup the vsync block */ + reg32_write(VDEC_VSCON1, 0x87); + + /* set the nosignal threshold + * set the vsync threshold */ + reg32_write(VDEC_VSSGTH, 0x35); + + /* set length for min hphase filter (or saturate limit if saturate is chosen) */ + reg32_write(VDEC_BASE + (0x45*4), 0x40); + + /* enable the internal resampler, + * select min filter not saturate for hphase noise filter for vcr detect. + * enable vcr pause mode different field lengths */ + reg32_write(VDEC_BASE + (0x46*4), 0x90); + + /* disable VCR detection, lock to the Hsync rather than the Vsync */ + reg32_write(VDEC_VSCON2, 0x04); + + /* set tiplevel goal for dc clamp. */ + reg32_write(VDEC_BASE + (0x3c*4), 0xB0); + + /* override SECAM detection and force SECAM off */ + reg32_write(VDEC_BASE + (0x2f*4), 0x20); + + /* Set r3d_hardblend in 3D control2 reg */ + reg32_write(VDEC_BASE + (0x0c*4), 0x04); +} + +/* set Input selector & input pull-downs */ +static void vadc_select_input(int vadc_in) +{ + switch (vadc_in) { + case 0: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x1e); + break; + case 1: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x2d); + break; + case 2: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x4b); + break; + case 3: + reg32_write(AFE_INPFLT, 0x02); + reg32_write(AFE_OFFDRV, 0x00); + reg32_write(AFE_INPCONFIG, 0x87); + break; + default: + printf("error video input %d\n", vadc_in); + } +} + +/*! + * Return attributes of current video standard. + * Since this device autodetects the current standard, this function also + * sets the values that need to be changed if the standard changes. + * There is no set std equivalent function. + * + * @return None. + */ +void vadc_get_std(struct sensor_data *vadc) +{ + int tmp; + int idx; + + /* Read PAL mode detected result */ + tmp = reg32_read(VDEC_VIDMOD); + tmp &= (VDEC_VIDMOD_PAL_MASK | VDEC_VIDMOD_M625_MASK); + + if (tmp) + idx = STD_PAL; + else + idx = STD_NTSC; + + vadc->std_id = idx; + vadc->pixel_fmt = FMT_YUV444; + vadc->width = video_fmts[idx].active_width; + vadc->height = video_fmts[idx].active_height; +} + +void vadc_config(u32 vadc_in) +{ + struct sensor_data vadc; + + /* map vafe,vdec,gpr,gpc address */ + vafe_regbase = (u32 *)VADC_BASE_ADDR; + vdec_regbase = (u32 *)VDEC_BASE_ADDR; + + vadc_power_up(); + + /* clock config for vadc */ + reg32_write(VDEC_BASE + 0x320, 0xe3); + reg32_write(VDEC_BASE + 0x324, 0x38); + reg32_write(VDEC_BASE + 0x328, 0x8e); + reg32_write(VDEC_BASE + 0x32c, 0x23); + mxs_set_vadcclk(); + + afe_init(); + + /* select Video Input 0-3 */ + vadc_select_input(vadc_in); + + afe_voltage_clampingmode(); + + vdec_init(&vadc); + + /* + * current control loop will move sinewave input off below + * the bottom of the signal range visible when the testbus is viewed as magnitude, + * so have to break before this point while capturing ENOB data: + */ + afe_alwayson_clampingmode(); +} + diff --git a/drivers/video/mxc_vadc.h b/drivers/video/mxc_vadc.h new file mode 100644 index 00000000000..bd85975fb40 --- /dev/null +++ b/drivers/video/mxc_vadc.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + */ + +#ifndef MXC_VADC_H +#define MXC_VADC_H + +/*** define base address ***/ +#define VDEC_BASE vdec_regbase +#define AFE_BASE vafe_regbase + +/* AFE - Register offsets */ +#define AFE_BLOCK_ID_OFFSET 0x00000000 +#define AFE_PDBUF_OFFSET 0x00000004 +#define AFE_SWRST_OFFSET 0x00000008 +#define AFE_TSTSEL_OFFSET 0x0000000c +#define AFE_TSTMSC_OFFSET 0x00000010 +#define AFE_ENPADIO_OFFSET 0x00000014 +#define AFE_BGREG_OFFSET 0x00000018 +#define AFE_ACCESSAR_ID_OFFSET 0x00000400 +#define AFE_PDADC_OFFSET 0x00000404 +#define AFE_PDSARH_OFFSET 0x00000408 +#define AFE_PDSARL_OFFSET 0x0000040C +#define AFE_PDADCRFH_OFFSET 0x00000410 +#define AFE_PDADCRFL_OFFSET 0x00000414 +#define AFE_ACCTST_OFFSET 0x00000418 +#define AFE_ADCGN_OFFSET 0x0000041C +#define AFE_ICTRL_OFFSET 0x00000420 +#define AFE_ICTLSTG_OFFSET 0x00000424 +#define AFE_RCTRLSTG_OFFSET 0x00000428 +#define AFE_TCTRLSTG_OFFSET 0x0000042c +#define AFE_REFMOD_OFFSET 0x00000430 +#define AFE_REFTRIML_OFFSET 0x00000434 +#define AFE_REFTRIMH_OFFSET 0x00000438 +#define AFE_ADCR_OFFSET 0x0000043c +#define AFE_DUMMY0_OFFSET 0x00000440 +#define AFE_DUMMY1_OFFSET 0x00000444 +#define AFE_DUMMY2_OFFSET 0x00000448 +#define AFE_DACAMP_OFFSET 0x0000044c +#define AFE_CLMPTST_OFFSET 0x00000450 +#define AFE_CLMPDAT_OFFSET 0x00000454 +#define AFE_CLMPAMP_OFFSET 0x00000458 +#define AFE_CLAMP_OFFSET 0x0000045c +#define AFE_INPBUF_OFFSET 0x00000460 +#define AFE_INPFLT_OFFSET 0x00000464 +#define AFE_ADCDGN_OFFSET 0x00000468 +#define AFE_OFFDRV_OFFSET 0x0000046c +#define AFE_INPCONFIG_OFFSET 0x00000470 +#define AFE_PROGDELAY_OFFSET 0x00000474 +#define AFE_ADCOMT_OFFSET 0x00000478 +#define AFE_ALGDELAY_OFFSET 0x0000047c +#define AFE_ACC_ID_OFFSET 0x00000800 +#define AFE_ACCSTA_OFFSET 0x00000804 +#define AFE_ACCNOSLI_OFFSET 0x00000808 +#define AFE_ACCCALCON_OFFSET 0x0000080c +#define AFE_BWEWRICTRL_OFFSET 0x00000810 +#define AFE_SELSLI_OFFSET 0x00000814 +#define AFE_SELBYT_OFFSET 0x00000818 +#define AFE_REDVAL_OFFSET 0x00000820 +#define AFE_WRIBYT_OFFSET 0x00000824 + +/* AFE Register per module */ +#define AFE_BLOCK_ID (AFE_BASE + AFE_BLOCK_ID_OFFSET) +#define AFE_PDBUF (AFE_BASE + AFE_PDBUF_OFFSET) +#define AFE_SWRST (AFE_BASE + AFE_SWRST_OFFSET) +#define AFE_TSTSEL (AFE_BASE + AFE_TSTSEL_OFFSET) +#define AFE_TSTMSC (AFE_BASE + AFE_TSTMSC_OFFSET) +#define AFE_ENPADIO (AFE_BASE + AFE_ENPADIO_OFFSET) +#define AFE_BGREG (AFE_BASE + AFE_BGREG_OFFSET) +#define AFE_ACCESSAR_ID (AFE_BASE + AFE_ACCESSAR_ID_OFFSET) +#define AFE_PDADC (AFE_BASE + AFE_PDADC_OFFSET) +#define AFE_PDSARH (AFE_BASE + AFE_PDSARH_OFFSET) +#define AFE_PDSARL (AFE_BASE + AFE_PDSARL_OFFSET) +#define AFE_PDADCRFH (AFE_BASE + AFE_PDADCRFH_OFFSET) +#define AFE_PDADCRFL (AFE_BASE + AFE_PDADCRFL_OFFSET) +#define AFE_ACCTST (AFE_BASE + AFE_ACCTST_OFFSET) +#define AFE_ADCGN (AFE_BASE + AFE_ADCGN_OFFSET) +#define AFE_ICTRL (AFE_BASE + AFE_ICTRL_OFFSET) +#define AFE_ICTLSTG (AFE_BASE + AFE_ICTLSTG_OFFSET) +#define AFE_RCTRLSTG (AFE_BASE + AFE_RCTRLSTG_OFFSET) +#define AFE_TCTRLSTG (AFE_BASE + AFE_TCTRLSTG_OFFSET) +#define AFE_REFMOD (AFE_BASE + AFE_REFMOD_OFFSET) +#define AFE_REFTRIML (AFE_BASE + AFE_REFTRIML_OFFSET) +#define AFE_REFTRIMH (AFE_BASE + AFE_REFTRIMH_OFFSET) +#define AFE_ADCR (AFE_BASE + AFE_ADCR_OFFSET) +#define AFE_DUMMY0 (AFE_BASE + AFE_DUMMY0_OFFSET) +#define AFE_DUMMY1 (AFE_BASE + AFE_DUMMY1_OFFSET) +#define AFE_DUMMY2 (AFE_BASE + AFE_DUMMY2_OFFSET) +#define AFE_DACAMP (AFE_BASE + AFE_DACAMP_OFFSET) +#define AFE_CLMPTST (AFE_BASE + AFE_CLMPTST_OFFSET) +#define AFE_CLMPDAT (AFE_BASE + AFE_CLMPDAT_OFFSET) +#define AFE_CLMPAMP (AFE_BASE + AFE_CLMPAMP_OFFSET) +#define AFE_CLAMP (AFE_BASE + AFE_CLAMP_OFFSET) +#define AFE_INPBUF (AFE_BASE + AFE_INPBUF_OFFSET) +#define AFE_INPFLT (AFE_BASE + AFE_INPFLT_OFFSET) +#define AFE_ADCDGN (AFE_BASE + AFE_ADCDGN_OFFSET) +#define AFE_OFFDRV (AFE_BASE + AFE_OFFDRV_OFFSET) +#define AFE_INPCONFIG (AFE_BASE + AFE_INPCONFIG_OFFSET) +#define AFE_PROGDELAY (AFE_BASE + AFE_PROGDELAY_OFFSET) +#define AFE_ADCOMT (AFE_BASE + AFE_ADCOMT_OFFSET) +#define AFE_ALGDELAY (AFE_BASE + AFE_ALGDELAY_OFFSET) +#define AFE_ACC_ID (AFE_BASE + AFE_ACC_ID_OFFSET) +#define AFE_ACCSTA (AFE_BASE + AFE_ACCSTA_OFFSET) +#define AFE_ACCNOSLI (AFE_BASE + AFE_ACCNOSLI_OFFSET) +#define AFE_ACCCALCON (AFE_BASE + AFE_ACCCALCON_OFFSET) +#define AFE_BWEWRICTRL (AFE_BASE + AFE_BWEWRICTRL_OFFSET) +#define AFE_SELSLI (AFE_BASE + AFE_SELSLI_OFFSET) +#define AFE_SELBYT (AFE_BASE + AFE_SELBYT_OFFSET) +#define AFE_REDVAL (AFE_BASE + AFE_REDVAL_OFFSET) +#define AFE_WRIBYT (AFE_BASE + AFE_WRIBYT_OFFSET) + +/* VDEC - Register offsets */ +#define VDEC_CFC1_OFFSET 0x00000000 +#define VDEC_CFC2_OFFSET 0x00000004 +#define VDEC_BRSTGT_OFFSET 0x00000024 +#define VDEC_HZPOS_OFFSET 0x00000040 +#define VDEC_VRTPOS_OFFSET 0x00000044 +#define VDEC_HVSHIFT_OFFSET 0x00000054 +#define VDEC_HSIGS_OFFSET 0x00000058 +#define VDEC_HSIGE_OFFSET 0x0000005C +#define VDEC_VSCON1_OFFSET 0x00000060 +#define VDEC_VSCON2_OFFSET 0x00000064 +#define VDEC_YCDEL_OFFSET 0x0000006C +#define VDEC_AFTCLP_OFFSET 0x00000070 +#define VDEC_DCOFF_OFFSET 0x00000078 +#define VDEC_CSID_OFFSET 0x00000084 +#define VDEC_CBGN_OFFSET 0x00000088 +#define VDEC_CRGN_OFFSET 0x0000008C +#define VDEC_CNTR_OFFSET 0x00000090 +#define VDEC_BRT_OFFSET 0x00000094 +#define VDEC_HUE_OFFSET 0x00000098 +#define VDEC_CHBTH_OFFSET 0x0000009C +#define VDEC_SHPIMP_OFFSET 0x000000A4 +#define VDEC_CHPLLIM_OFFSET 0x000000A8 +#define VDEC_VIDMOD_OFFSET 0x000000AC +#define VDEC_VIDSTS_OFFSET 0x000000B0 +#define VDEC_NOISE_OFFSET 0x000000B4 +#define VDEC_STDDBG_OFFSET 0x000000B8 +#define VDEC_MANOVR_OFFSET 0x000000BC +#define VDEC_VSSGTH_OFFSET 0x000000C8 +#define VDEC_DBGFBH_OFFSET 0x000000D0 +#define VDEC_DBGFBL_OFFSET 0x000000D4 +#define VDEC_HACTS_OFFSET 0x000000D8 +#define VDEC_HACTE_OFFSET 0x000000DC +#define VDEC_VACTS_OFFSET 0x000000E0 +#define VDEC_VACTE_OFFSET 0x000000E4 +#define VDEC_HSTIP_OFFSET 0x000000EC +#define VDEC_BLSCRY_OFFSET 0x000000F4 +#define VDEC_BLSCRCR_OFFSET 0x000000F8 +#define VDEC_BLSCRCB_OFFSET 0x000000FC +#define VDEC_LMAGC2_OFFSET 0x00000104 +#define VDEC_CHAGC1_OFFSET 0x00000108 +#define VDEC_CHAGC2_OFFSET 0x0000010C +#define VDEC_MINTH_OFFSET 0x00000114 +#define VDEC_VFRQOH_OFFSET 0x0000011C +#define VDEC_VFRQOL_OFFSET 0x00000120 +#define VDEC_THSH1_OFFSET 0x00000124 +#define VDEC_THSH2_OFFSET 0x00000128 +#define VDEC_NCHTH_OFFSET 0x0000012C +#define VDEC_TH1F_OFFSET 0x00000130 + +/* VDEC Register per module */ +#define VDEC_CFC1 (VDEC_BASE + VDEC_CFC1_OFFSET) +#define VDEC_CFC2 (VDEC_BASE + VDEC_CFC2_OFFSET) +#define VDEC_BRSTGT (VDEC_BASE + VDEC_BRSTGT_OFFSET) +#define VDEC_HZPOS (VDEC_BASE + VDEC_HZPOS_OFFSET) +#define VDEC_VRTPOS (VDEC_BASE + VDEC_VRTPOS_OFFSET) +#define VDEC_HVSHIFT (VDEC_BASE + VDEC_HVSHIFT_OFFSET) +#define VDEC_HSIGS (VDEC_BASE + VDEC_HSIGS_OFFSET) +#define VDEC_HSIGE (VDEC_BASE + VDEC_HSIGE_OFFSET) +#define VDEC_VSCON1 (VDEC_BASE + VDEC_VSCON1_OFFSET) +#define VDEC_VSCON2 (VDEC_BASE + VDEC_VSCON2_OFFSET) +#define VDEC_YCDEL (VDEC_BASE + VDEC_YCDEL_OFFSET) +#define VDEC_AFTCLP (VDEC_BASE + VDEC_AFTCLP_OFFSET) +#define VDEC_DCOFF (VDEC_BASE + VDEC_DCOFF_OFFSET) +#define VDEC_CSID (VDEC_BASE + VDEC_CSID_OFFSET) +#define VDEC_CBGN (VDEC_BASE + VDEC_CBGN_OFFSET) +#define VDEC_CRGN (VDEC_BASE + VDEC_CRGN_OFFSET) +#define VDEC_CNTR (VDEC_BASE + VDEC_CNTR_OFFSET) +#define VDEC_BRT (VDEC_BASE + VDEC_BRT_OFFSET) +#define VDEC_HUE (VDEC_BASE + VDEC_HUE_OFFSET) +#define VDEC_CHBTH (VDEC_BASE + VDEC_CHBTH_OFFSET) +#define VDEC_SHPIMP (VDEC_BASE + VDEC_SHPIMP_OFFSET) +#define VDEC_CHPLLIM (VDEC_BASE + VDEC_CHPLLIM_OFFSET) +#define VDEC_VIDMOD (VDEC_BASE + VDEC_VIDMOD_OFFSET) +#define VDEC_VIDSTS (VDEC_BASE + VDEC_VIDSTS_OFFSET) +#define VDEC_NOISE (VDEC_BASE + VDEC_NOISE_OFFSET) +#define VDEC_STDDBG (VDEC_BASE + VDEC_STDDBG_OFFSET) +#define VDEC_MANOVR (VDEC_BASE + VDEC_MANOVR_OFFSET) +#define VDEC_VSSGTH (VDEC_BASE + VDEC_VSSGTH_OFFSET) +#define VDEC_DBGFBH (VDEC_BASE + VDEC_DBGFBH_OFFSET) +#define VDEC_DBGFBL (VDEC_BASE + VDEC_DBGFBL_OFFSET) +#define VDEC_HACTS (VDEC_BASE + VDEC_HACTS_OFFSET) +#define VDEC_HACTE (VDEC_BASE + VDEC_HACTE_OFFSET) +#define VDEC_VACTS (VDEC_BASE + VDEC_VACTS_OFFSET) +#define VDEC_VACTE (VDEC_BASE + VDEC_VACTE_OFFSET) +#define VDEC_HSTIP (VDEC_BASE + VDEC_HSTIP_OFFSET) +#define VDEC_BLSCRY (VDEC_BASE + VDEC_BLSCRY_OFFSET) +#define VDEC_BLSCRCR (VDEC_BASE + VDEC_BLSCRCR_OFFSET) +#define VDEC_BLSCRCB (VDEC_BASE + VDEC_BLSCRCB_OFFSET) +#define VDEC_LMAGC2 (VDEC_BASE + VDEC_LMAGC2_OFFSET) +#define VDEC_CHAGC1 (VDEC_BASE + VDEC_CHAGC1_OFFSET) +#define VDEC_CHAGC2 (VDEC_BASE + VDEC_CHAGC2_OFFSET) +#define VDEC_MINTH (VDEC_BASE + VDEC_MINTH_OFFSET) +#define VDEC_VFRQOH (VDEC_BASE + VDEC_VFRQOH_OFFSET) +#define VDEC_VFRQOL (VDEC_BASE + VDEC_VFRQOL_OFFSET) +#define VDEC_THSH1 (VDEC_BASE + VDEC_THSH1_OFFSET) +#define VDEC_THSH2 (VDEC_BASE + VDEC_THSH2_OFFSET) +#define VDEC_NCHTH (VDEC_BASE + VDEC_NCHTH_OFFSET) +#define VDEC_TH1F (VDEC_BASE + VDEC_TH1F_OFFSET) + +#define VDEC_VIDMOD_M625_SHIFT 4 +#define VDEC_VIDMOD_M625_MASK (1 << VDEC_VIDMOD_M625_SHIFT) + +#define VDEC_VIDMOD_PAL_SHIFT 7 +#define VDEC_VIDMOD_PAL_MASK (1 << VDEC_VIDMOD_PAL_SHIFT) + +struct sensor_data { + u32 width; + u32 height; + u32 pixel_fmt; + u32 std_id; +}; + +void vadc_config(u32 vadc_in); +void vadc_get_std(struct sensor_data *vadc); + +#endif diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index e1fd36a62d6..4757f3ec753 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -3,6 +3,8 @@ * Freescale i.MX23/i.MX28 LCDIF driver * * Copyright (C) 2011-2013 Marek Vasut + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * */ #include #include @@ -16,15 +18,31 @@ #include #include #include - +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) +#include +#else #include +#endif #include #include #include #include #include +#include +#include +#include +#include #include "videomodes.h" +#include +#include +#include +#include +#include + +#ifdef CONFIG_VIDEO_GIS +#include +#endif #define PS2KHZ(ps) (1000000000UL / (ps)) #define HZ2PS(hz) (1000000000UL / ((hz) / 1000)) @@ -57,39 +75,18 @@ __weak void mxsfb_system_setup(void) * le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0 */ -static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, - struct display_timing *timings, int bpp) +static void mxs_lcd_init(phys_addr_t reg_base, u32 fb_addr, + struct display_timing *timings, int bpp, bool bridge) { - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)(reg_base); const enum display_flags flags = timings->flags; uint32_t word_len = 0, bus_width = 0; uint8_t valid_data = 0; uint32_t vdctrl0; -#if CONFIG_IS_ENABLED(CLK) - struct clk per_clk; - int ret; - - ret = clk_get_by_name(dev, "per", &per_clk); - if (ret) { - dev_err(dev, "Failed to get mxs clk: %d\n", ret); - return; - } - - ret = clk_set_rate(&per_clk, timings->pixelclock.typ); - if (ret < 0) { - dev_err(dev, "Failed to set mxs clk: %d\n", ret); - return; - } - - ret = clk_enable(&per_clk); - if (ret < 0) { - dev_err(dev, "Failed to enable mxs clk: %d\n", ret); - return; - } -#else +#if !(CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8)) /* Kick in the LCDIF clock */ - mxs_set_lcdclk(MXS_LCDIF_BASE, timings->pixelclock.typ / 1000); + mxs_set_lcdclk((u32)reg_base, timings->pixelclock.typ / 1000); #endif /* Restart the LCDIF block */ @@ -125,12 +122,15 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, writel(valid_data << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET, ®s->hw_lcdif_ctrl1); + if (bridge) + writel(LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16, ®s->hw_lcdif_ctrl2); + mxsfb_system_setup(); writel((timings->vactive.typ << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) | timings->hactive.typ, ®s->hw_lcdif_transfer_count); - vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_ENABLE_POL | + vdctrl0 = LCDIF_VDCTRL0_ENABLE_PRESENT | LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT | timings->vsync_len.typ; @@ -177,11 +177,11 @@ static void mxs_lcd_init(struct udevice *dev, u32 fb_addr, writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); } -static int mxs_probe_common(struct udevice *dev, struct display_timing *timings, - int bpp, u32 fb) +static int mxs_probe_common(phys_addr_t reg_base, struct display_timing *timings, + int bpp, u32 fb, bool bridge) { /* Start framebuffer */ - mxs_lcd_init(dev, fb, timings, bpp); + mxs_lcd_init(reg_base, fb, timings, bpp, bridge); #ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM /* @@ -192,7 +192,7 @@ static int mxs_probe_common(struct udevice *dev, struct display_timing *timings, * sets the RUN bit, then waits until it gets cleared and repeats this * infinitelly. This way, we get smooth continuous updates of the LCD. */ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)reg_base; memset(&desc, 0, sizeof(struct mxs_dma_desc)); desc.address = (dma_addr_t)&desc; @@ -209,11 +209,16 @@ static int mxs_probe_common(struct udevice *dev, struct display_timing *timings, return 0; } -static int mxs_remove_common(u32 fb) +static int mxs_remove_common(phys_addr_t reg_base, u32 fb) { - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)(reg_base); int timeout = 1000000; + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_LCDIF)) + return -ENODEV; + } + if (!fb) return -EINVAL; @@ -234,10 +239,34 @@ static int mxs_remove_common(u32 fb) #ifndef CONFIG_DM_VIDEO static GraphicDevice panel; +static int setup; +static struct fb_videomode fbmode; +static int depth; + +int mxs_lcd_panel_setup(struct fb_videomode mode, int bpp, + uint32_t base_addr) +{ + fbmode = mode; + depth = bpp; + panel.isaBase = base_addr; + + setup = 1; + + return 0; +} + +void mxs_lcd_get_panel(struct display_panel *dispanel) +{ + dispanel->width = fbmode.xres; + dispanel->height = fbmode.yres; + dispanel->reg_base = panel.isaBase; + dispanel->gdfindex = panel.gdfIndex; + dispanel->gdfbytespp = panel.gdfBytesPP; +} void lcdif_power_down(void) { - mxs_remove_common(panel.frameAdrs); + mxs_remove_common(panel.isaBase, panel.frameAdrs); } void *video_hw_init(void) @@ -251,15 +280,41 @@ void *video_hw_init(void) puts("Video: "); - /* Suck display configuration from "videomode" variable */ - penv = env_get("videomode"); - if (!penv) { - puts("MXSFB: 'videomode' variable not set!\n"); - return NULL; + if (!setup) { + + /* Suck display configuration from "videomode" variable */ + penv = env_get("videomode"); + if (!penv) { + printf("MXSFB: 'videomode' variable not set!\n"); + return NULL; + } + + bpp = video_get_params(&mode, penv); + panel.isaBase = MXS_LCDIF_BASE; + } else { + mode.xres = fbmode.xres; + mode.yres = fbmode.yres; + mode.pixclock = fbmode.pixclock; + mode.left_margin = fbmode.left_margin; + mode.right_margin = fbmode.right_margin; + mode.upper_margin = fbmode.upper_margin; + mode.lower_margin = fbmode.lower_margin; + mode.hsync_len = fbmode.hsync_len; + mode.vsync_len = fbmode.vsync_len; + mode.sync = fbmode.sync; + mode.vmode = fbmode.vmode; + bpp = depth; } - bpp = video_get_params(&mode, penv); + mode.pixclock_khz = PS2KHZ(mode.pixclock); + mode.pixclock = mode.pixclock_khz * 1000; + if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) { + if (check_module_fused(MODULE_LCDIF)) { + printf("LCDIF@0x%x is fused, disable it\n", MXS_LCDIF_BASE); + return NULL; + } + } /* fill in Graphic device struct */ sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); @@ -305,11 +360,17 @@ void *video_hw_init(void) printf("%s\n", panel.modeIdent); video_ctfb_mode_to_display_timing(&mode, &timings); + timings.flags |= DISPLAY_FLAGS_DE_HIGH; /* Force enable pol */ - ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb); + ret = mxs_probe_common(panel.isaBase, &timings, bpp, (u32)fb, false); if (ret) goto dealloc_fb; +#ifdef CONFIG_VIDEO_GIS + /* Entry for GIS */ + mxc_enable_gis(); +#endif + return (void *)&panel; dealloc_fb: @@ -319,6 +380,82 @@ void *video_hw_init(void) } #else /* ifndef CONFIG_DM_VIDEO */ +struct mxsfb_priv { + fdt_addr_t reg_base; + struct udevice *disp_dev; + +#if IS_ENABLED(CONFIG_DM_RESET) + struct reset_ctl_bulk soft_resetn; + struct reset_ctl_bulk clk_enable; +#endif + +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) + struct clk lcdif_pix; + struct clk lcdif_disp_axi; + struct clk lcdif_axi; +#endif +}; + +#if IS_ENABLED(CONFIG_DM_RESET) +static int lcdif_rstc_reset(struct reset_ctl_bulk *rstc, bool assert) +{ + int ret; + + if (!rstc) + return 0; + + ret = assert ? reset_assert_bulk(rstc) : + reset_deassert_bulk(rstc); + + return ret; +} + +static int lcdif_of_parse_resets(struct udevice *dev) +{ + int ret; + ofnode parent, child; + struct ofnode_phandle_args args; + struct reset_ctl_bulk rstc; + const char *compat; + uint32_t rstc_num = 0; + + struct mxsfb_priv *priv = dev_get_priv(dev); + + ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0, + 0, &args); + if (ret) + return ret; + + parent = args.node; + ofnode_for_each_subnode(child, parent) { + compat = ofnode_get_property(child, "compatible", NULL); + if (!compat) + continue; + + ret = reset_get_bulk_nodev(child, &rstc); + if (ret) + continue; + + if (!of_compat_cmp("lcdif,soft-resetn", compat, 0)) { + priv->soft_resetn = rstc; + rstc_num++; + } else if (!of_compat_cmp("lcdif,clk-enable", compat, 0)) { + priv->clk_enable = rstc; + rstc_num++; + } + else + dev_warn(dev, "invalid lcdif reset node: %s\n", compat); + } + + if (!rstc_num) { + dev_err(dev, "no invalid reset control exists\n"); + return -EINVAL; + } + + return 0; +} +#endif + static int mxs_of_get_timings(struct udevice *dev, struct display_timing *timings, u32 *bpp) @@ -326,6 +463,7 @@ static int mxs_of_get_timings(struct udevice *dev, int ret = 0; u32 display_phandle; ofnode display_node; + struct mxsfb_priv *priv = dev_get_priv(dev); ret = ofnode_read_u32(dev_ofnode(dev), "display", &display_phandle); if (ret) { @@ -346,10 +484,19 @@ static int mxs_of_get_timings(struct udevice *dev, return -EINVAL; } - ret = ofnode_decode_display_timing(display_node, 0, timings); - if (ret) { - dev_err(dev, "failed to get any display timings\n"); - return -EINVAL; + priv->disp_dev = video_link_get_next_device(dev); + if (priv->disp_dev) { + ret = video_link_get_display_timings(timings); + if (ret) { + dev_err(dev, "failed to get any video link display timings\n"); + return -EINVAL; + } + } else { + ret = ofnode_decode_display_timing(display_node, 0, timings); + if (ret) { + dev_err(dev, "failed to get any display timings\n"); + return -EINVAL; + } } return ret; @@ -359,20 +506,126 @@ static int mxs_video_probe(struct udevice *dev) { struct video_uc_plat *plat = dev_get_uclass_plat(dev); struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct mxsfb_priv *priv = dev_get_priv(dev); struct display_timing timings; u32 bpp = 0; u32 fb_start, fb_end; int ret; + bool enable_bridge = false; debug("%s() plat: base 0x%lx, size 0x%x\n", __func__, plat->base, plat->size); + priv->reg_base = dev_read_addr(dev); + if (priv->reg_base == FDT_ADDR_T_NONE) { + dev_err(dev, "lcdif base address is not found\n"); + return -EINVAL; + } + ret = mxs_of_get_timings(dev, &timings, &bpp); if (ret) return ret; + timings.flags |= DISPLAY_FLAGS_DE_HIGH; + +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) + ret = clk_get_by_name(dev, "pix", &priv->lcdif_pix); + if (ret) { + printf("Failed to get pix clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "disp_axi", &priv->lcdif_disp_axi); + if (ret) { + printf("Failed to get disp_axi clk\n"); + return ret; + } + + ret = clk_get_by_name(dev, "axi", &priv->lcdif_axi); + if (ret) { + printf("Failed to get axi clk\n"); + return ret; + } + + ret = clk_enable(&priv->lcdif_axi); + if (ret) { + printf("unable to enable lcdif_axi clock\n"); + return ret; + } + + ret = clk_enable(&priv->lcdif_disp_axi); + if (ret) { + printf("unable to enable lcdif_disp_axi clock\n"); + return ret; + } +#endif + +#if IS_ENABLED(CONFIG_DM_RESET) + ret = lcdif_of_parse_resets(dev); + if (!ret) { + ret = lcdif_rstc_reset(&priv->soft_resetn, false); + if (ret) { + dev_err(dev, "deassert soft_resetn failed\n"); + return ret; + } + + ret = lcdif_rstc_reset(&priv->clk_enable, true); + if (ret) { + dev_err(dev, "assert clk_enable failed\n"); + return ret; + } + } +#endif + + if (priv->disp_dev) { +#if IS_ENABLED(CONFIG_VIDEO_BRIDGE) + if (device_get_uclass_id(priv->disp_dev) == UCLASS_VIDEO_BRIDGE) { + ret = video_bridge_attach(priv->disp_dev); + if (ret) { + dev_err(dev, "fail to attach bridge\n"); + return ret; + } + + ret = video_bridge_set_backlight(priv->disp_dev, 80); + if (ret) { + dev_err(dev, "fail to set backlight\n"); + return ret; + } + + enable_bridge = true; + + /* sec dsim needs enable ploarity at low, default we set to high */ + if (!strcmp(priv->disp_dev->driver->name, "imx_sec_dsim")) + timings.flags &= ~DISPLAY_FLAGS_DE_HIGH; + + } +#endif + + if (device_get_uclass_id(priv->disp_dev) == UCLASS_PANEL) { + ret = panel_enable_backlight(priv->disp_dev); + if (ret) { + dev_err(dev, "panel %s enable backlight error %d\n", + priv->disp_dev->name, ret); + return ret; + } + } + } + +#if CONFIG_IS_ENABLED(CLK) && IS_ENABLED(CONFIG_IMX8) + ret = clk_set_rate(&priv->lcdif_pix, timings.pixelclock.typ); + if (ret < 0) { + printf("Failed to set pix clk rate\n"); + return ret; + } + + ret = clk_enable(&priv->lcdif_pix); + if (ret) { + printf("unable to enable lcdif_pix clock\n"); + return ret; + } +#endif - ret = mxs_probe_common(dev, &timings, bpp, plat->base); + ret = mxs_probe_common(priv->reg_base, &timings, bpp, plat->base, enable_bridge); if (ret) return ret; @@ -397,9 +650,9 @@ static int mxs_video_probe(struct udevice *dev) uc_priv->ysize = timings.vactive.typ; /* Enable dcache for the frame buffer */ - fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); + fb_start = plat->base; fb_end = plat->base + plat->size; - fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); + mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, DCACHE_WRITEBACK); video_set_flush_dcache(dev, true); @@ -411,33 +664,10 @@ static int mxs_video_probe(struct udevice *dev) static int mxs_video_bind(struct udevice *dev) { struct video_uc_plat *plat = dev_get_uclass_plat(dev); - struct display_timing timings; - u32 bpp = 0; - u32 bytes_pp = 0; - int ret; - ret = mxs_of_get_timings(dev, &timings, &bpp); - if (ret) - return ret; - - switch (bpp) { - case 32: - case 24: - case 18: - bytes_pp = 4; - break; - case 16: - bytes_pp = 2; - break; - case 8: - bytes_pp = 1; - break; - default: - dev_err(dev, "invalid bpp specified (bpp = %i)\n", bpp); - return -EINVAL; - } - - plat->size = timings.hactive.typ * timings.vactive.typ * bytes_pp; + /* Max size supported by LCDIF, because in bind, we can't probe panel */ + plat->size = ALIGN(1920 * 1080 *4 * 2, MMU_SECTION_SIZE); + plat->align = MMU_SECTION_SIZE; return 0; } @@ -445,8 +675,14 @@ static int mxs_video_bind(struct udevice *dev) static int mxs_video_remove(struct udevice *dev) { struct video_uc_plat *plat = dev_get_uclass_plat(dev); + struct mxsfb_priv *priv = dev_get_priv(dev); + + debug("%s\n", __func__); + + if (priv->disp_dev) + device_remove(priv->disp_dev, DM_REMOVE_NORMAL); - mxs_remove_common(plat->base); + mxs_remove_common(priv->reg_base, plat->base); return 0; } @@ -456,6 +692,8 @@ static const struct udevice_id mxs_video_ids[] = { { .compatible = "fsl,imx28-lcdif" }, { .compatible = "fsl,imx7ulp-lcdif" }, { .compatible = "fsl,imxrt-lcdif" }, + { .compatible = "fsl,imx8mm-lcdif" }, + { .compatible = "fsl,imx8mn-lcdif" }, { /* sentinel */ } }; @@ -467,5 +705,6 @@ U_BOOT_DRIVER(mxs_video) = { .probe = mxs_video_probe, .remove = mxs_video_remove, .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE, + .priv_auto = sizeof(struct mxsfb_priv), }; #endif /* ifndef CONFIG_DM_VIDEO */ diff --git a/drivers/video/nxp/Kconfig b/drivers/video/nxp/Kconfig new file mode 100644 index 00000000000..609cb92a9ba --- /dev/null +++ b/drivers/video/nxp/Kconfig @@ -0,0 +1,8 @@ + +config VIDEO_NXP_HDP + bool + help + Enable NXP HDP Library for HDMI and HDMI/DP firmware loading + +source "drivers/video/nxp/imx/Kconfig" +source "drivers/video/nxp/layerscape/Kconfig" diff --git a/drivers/video/nxp/Makefile b/drivers/video/nxp/Makefile new file mode 100644 index 00000000000..420c2df7830 --- /dev/null +++ b/drivers/video/nxp/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 NXP + +UBOOTINCLUDE += -I$(srctree)/drivers/video/nxp/hdp +obj-$(CONFIG_VIDEO_NXP_HDP) += hdp/ +obj-y += imx/ +obj-y += layerscape/ diff --git a/drivers/video/nxp/hdp/API_AFE.c b/drivers/video/nxp/hdp/API_AFE.c new file mode 100644 index 00000000000..7b778cd3d58 --- /dev/null +++ b/drivers/video/nxp/hdp/API_AFE.c @@ -0,0 +1,115 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AFE.c + * + ****************************************************************************** + */ + +#include "address.h" +#include "API_AFE.h" +#include "util.h" +#ifndef __UBOOT__ +#include +#endif + +void afe_write(unsigned int offset, unsigned short val) +{ +#ifdef EXTERNAL_AFE + cdn_phapb_write(offset << 2, val); +#else + CDN_API_STATUS sts; + + sts = cdn_api_general_write_register_blocking( + ADDR_AFE + (offset << 2), val); + + if (sts != CDN_OK) { + printf("CDN_API_General_Write_Register_blocking(0x%.8X, 0x%.8X) returned %d\n", + offset, + val, + (int)sts); + } +#endif +} + +unsigned short afe_read(unsigned int offset) +{ + GENERAL_READ_REGISTER_RESPONSE resp; + +#ifdef EXTERNAL_AFE + cdn_phapb_read(offset << 2, &resp.val); +#else + CDN_API_STATUS sts; + + sts = cdn_api_general_read_register_blocking( + ADDR_AFE + (offset << 2), &resp); + + if (sts != CDN_OK) { + printf("CDN_API_General_Read_Register_blocking(0x%.8X) returned %d\n", + offset, + (int)sts); + } +#endif + return resp.val; +} + +void set_field_value(reg_field_t *reg_field, u32 value) +{ + u8 length; + u32 max_value; + u32 trunc_val; + length = (reg_field->msb - reg_field->lsb + 1); + + max_value = (1 << length) - 1; + if (value > max_value) { + trunc_val = value; + trunc_val &= (1 << length) - 1; + printf("set_field_value() Error! Specified value (0x%0X) exceeds field capacity - it will by truncated to 0x%0X (%0d-bit field - max value: %0d dec)\n", + value, trunc_val, length, max_value); + } else { + reg_field->value = value; + } +} + +int set_reg_value(reg_field_t reg_field) +{ + return reg_field.value << reg_field.lsb; +} diff --git a/drivers/video/nxp/hdp/API_AFE.h b/drivers/video/nxp/hdp/API_AFE.h new file mode 100644 index 00000000000..2ebdfb32260 --- /dev/null +++ b/drivers/video/nxp/hdp/API_AFE.h @@ -0,0 +1,99 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AFE.h + * + ****************************************************************************** + */ + +#ifndef API_AFE_H_ +#define API_AFE_H_ +#include "util.h" + +typedef enum { + AFE_LINK_RATE_1_6 = 0x6, /* 1.62 Gb/s */ + AFE_LINK_RATE_2_1 = 0x8, /* 2.16 Gb/s */ + AFE_LINK_RATE_2_4 = 0x9, /* 2.43 Gb/s */ + AFE_LINK_RATE_2_7 = 0xA, /* 2.70 Gb/s */ + AFE_LINK_RATE_3_2 = 0xC, /* 3.24 Gb/s */ + AFE_LINK_RATE_4_3 = 0x10, /* 4.32 Gb/s */ + AFE_LINK_RATE_5_4 = 0x14, /* 5.40 Gb/s */ + AFE_LINK_RATE_8_1 = 0x1E, /* 8.10 Gb/s */ +} ENUM_AFE_LINK_RATE; + +/* Some of the PHY programming sequences */ +/* depend on the reference clock frequency. */ +/* Variable of this type is used to control */ +/* the programming flow. */ +typedef enum { + REFCLK_24MHZ, + REFCLK_27MHZ +} REFCLK_FREQ; + +typedef enum { + CLK_RATIO_1_1, + CLK_RATIO_5_4, + CLK_RATIO_3_2, + CLK_RATIO_2_1, + CLK_RATIO_1_2, + CLK_RATIO_5_8, + CLK_RATIO_3_4 +} clk_ratio_t; + +typedef struct { + u32 value; + u8 lsb; + u8 msb; +} reg_field_t; + +unsigned char AFE_check_rate_supported(ENUM_AFE_LINK_RATE rate); +void afe_write(unsigned int offset, unsigned short val); +unsigned short afe_read(unsigned int offset); +void AFE_init(int num_lanes, ENUM_AFE_LINK_RATE link_rate); +void AFE_power(int num_lanes, ENUM_AFE_LINK_RATE link_rate); + +/*extern int cdn_phapb_read(unsigned int addr, unsigned int *value);*/ +/*extern int cdn_phapb_write(unsigned int addr, unsigned int value);*/ +void set_field_value(reg_field_t *reg_field, u32 value); +int set_reg_value(reg_field_t reg_field); + +#endif + diff --git a/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.c b/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.c new file mode 100644 index 00000000000..933ecfa8d43 --- /dev/null +++ b/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.c @@ -0,0 +1,1863 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AFE_t28hpc_hdmitx.c + * + ****************************************************************************** + */ + +#include "API_AFE_t28hpc_hdmitx.h" +#include "API_AFE.h" +#include "externs.h" + +#ifndef DEBUG +static inline void write16(uint32_t addr, uint16_t val) +{ + afe_write(addr, val); +} + +static inline uint16_t read16(uint32_t addr) +{ + return afe_read(addr); +} +#else +#define write16(addr, val) __write16(addr, val, __LINE__) +static inline void __write16(uint32_t addr, uint16_t val, int line) +{ + afe_write(addr, val); + debug("write16():%4d Writting value 0x%04X at address 0x%05X (0x%04X)\n", + line, val, (0x20000 * 4) + (addr << 2), addr); +} +#define read16(addr) __read16(addr, __LINE__) +static inline uint16_t __read16(uint32_t addr, int line) +{ + debug("read16():%5d Reading from address 0x%05X (0x%04X)\n", + line, (0x20000 * 4) + (addr << 2), addr); + return afe_read(addr); +} + +#endif + +static char inside(u32 value, u32 left_sharp_corner, + u32 right_sharp_corner) +{ + if (value < left_sharp_corner) + return false; + if (value > right_sharp_corner) + return false; + return true; +} + +void aux_cfg_t28hpc(void) +{ + write16(0x5025, 0x0001); + + write16(0x5024, 36); + + write16(0x5021, 0x0100); + write16(0x5021, 0x0300); + write16(0x5026, 0x0000); + write16(0x5020, 0x2008); + write16(0x5020, 0x2018); + write16(0x5020, 0xA018); + write16(0x5021, 0x030C); + write16(0x5029, 0x0000); + write16(0x5027, 0x4001); + write16(0x5020, 0xA098); + write16(0x5020, 0xA198); + write16(0x5021, 0x030D); + write16(0x5021, 0x030F); +} + +int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp, + VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy) +{ + const int phy_reset_workaround = 1; + unsigned int vco_freq; + unsigned char k; + uint32_t reg_val; + uint32_t pixel_freq_khz = vic_table[vic_mode][PIXEL_FREQ_KHZ]; + uint32_t character_clock_ratio_num = 1; + uint32_t character_clock_ratio_den = 1; + uint32_t character_freq_khz; + const unsigned int refclk_freq_khz = 27000; + unsigned int ftemp, ftemp2; + + clk_ratio_t clk_ratio = 0; + reg_field_t cmnda_pll0_hs_sym_div_sel; + reg_field_t cmnda_pll0_ip_div; + reg_field_t cmnda_pll0_fb_div_low; + reg_field_t cmnda_pll0_fb_div_high; + reg_field_t cmn_ref_clk_dig_div; + reg_field_t divider_scaler; + reg_field_t cmnda_hs_clk_0_sel; + reg_field_t cmnda_hs_clk_1_sel; + reg_field_t tx_subrate; + reg_field_t voltage_to_current_coarse; + reg_field_t voltage_to_current; + reg_field_t ndac_ctrl; + reg_field_t pmos_ctrl; + reg_field_t ptat_ndac_ctrl; + reg_field_t charge_pump_gain; + reg_field_t vco_ring_select; + reg_field_t pll_feedback_divider_total; + reg_field_t cmnda_pll0_pxdiv_high; + reg_field_t cmnda_pll0_pxdiv_low; + reg_field_t coarse_code; + reg_field_t v2i_code; + reg_field_t vco_cal_code; + + cmnda_pll0_fb_div_high.value = 0x00A; + ftemp = pixel_freq_khz; + + debug(" VIC %d, pixel clock %u kHz\n", vic_mode, ftemp); + + /* Set field position */ + cmnda_pll0_hs_sym_div_sel.msb = 9; + cmnda_pll0_hs_sym_div_sel.lsb = 8; + cmnda_pll0_ip_div.msb = 7; + cmnda_pll0_ip_div.lsb = 0; + cmnda_pll0_fb_div_low.msb = 9; + cmnda_pll0_fb_div_low.lsb = 0; + cmnda_pll0_fb_div_high.msb = 9; + cmnda_pll0_fb_div_high.lsb = 0; + cmn_ref_clk_dig_div.msb = 13; + cmn_ref_clk_dig_div.lsb = 12; + divider_scaler.msb = 14; + divider_scaler.lsb = 12; + cmnda_hs_clk_0_sel.msb = 1; + cmnda_hs_clk_0_sel.lsb = 0; + cmnda_hs_clk_1_sel.msb = 1; + cmnda_hs_clk_1_sel.lsb = 0; + tx_subrate.msb = 2; + tx_subrate.lsb = 0; + voltage_to_current_coarse.msb = 2; + voltage_to_current_coarse.lsb = 0; + voltage_to_current.msb = 5; + voltage_to_current.lsb = 4; + ndac_ctrl.msb = 11; + ndac_ctrl.lsb = 8; + pmos_ctrl.msb = 7; + pmos_ctrl.lsb = 0; + ptat_ndac_ctrl.msb = 5; + ptat_ndac_ctrl.lsb = 0; + charge_pump_gain.msb = 8; + charge_pump_gain.lsb = 0; + vco_ring_select.msb = 12; + vco_ring_select.lsb = 12; + pll_feedback_divider_total.msb = 9; + pll_feedback_divider_total.lsb = 0; + cmnda_pll0_pxdiv_high.msb = 9; + cmnda_pll0_pxdiv_high.lsb = 0; + cmnda_pll0_pxdiv_low.msb = 9; + cmnda_pll0_pxdiv_low.lsb = 0; + coarse_code.msb = 7; + coarse_code.lsb = 0; + v2i_code.msb = 3; + v2i_code.lsb = 0; + vco_cal_code.msb = 8; + vco_cal_code.lsb = 0; + + if (phy_reset_workaround) { + /* register PHY_PMA_ISOLATION_CTRL */ + write16(0xC81F, 0xD000); /* enable PHY iso mode only for CMN */ + /* register PHY_PMA_ISO_PLL_CTRL1 */ + reg_val = read16(0xC812); + reg_val &= 0xFF00; + reg_val |= 0x0012; + /* set pll0_clk_datart1_div/pll0_clk_datart0_div dividers */ + write16(0xC812, reg_val); + /* register PHY_ISO_CMN_CTRL */ + /* assert PHY reset from isolation register */ + write16(0xC010, 0x0000); + /* register PHY_PMA_ISO_CMN_CTRL */ + write16(0xC810, 0x0000); /* assert PMA CMN reset */ + /* register XCVR_DIAG_BIDI_CTRL */ + for (k = 0; k < num_lanes; k++) + write16(0x40E8 | (k << 9), 0x00FF); + } + /*--------------------------------------------------------------- + * Describing Task phy_cfg_hdp + * --------------------------------------------------------------*/ + /* register PHY_PMA_CMN_CTRL1 */ + reg_val = read16(0xC800); + reg_val &= 0xFFF7; + reg_val |= 0x0008; + write16(0xC800, reg_val); + + /* register CMN_DIAG_PLL0_TEST_MODE */ + write16(0x01C4, 0x0020); + /* register CMN_PSM_CLK_CTRL */ + write16(0x0061, 0x0016); + + switch (format) { + case YCBCR_4_2_2: + clk_ratio = CLK_RATIO_1_1; + character_clock_ratio_num = 1; + character_clock_ratio_den = 1; + break; + case YCBCR_4_2_0: + switch (bpp) { + case 8: + clk_ratio = CLK_RATIO_1_2; + character_clock_ratio_num = 1; + character_clock_ratio_den = 2; + break; + case 10: + clk_ratio = CLK_RATIO_5_8; + character_clock_ratio_num = 5; + character_clock_ratio_den = 8; + break; + case 12: + clk_ratio = CLK_RATIO_3_4; + character_clock_ratio_num = 3; + character_clock_ratio_den = 4; + break; + case 16: + clk_ratio = CLK_RATIO_1_1; + character_clock_ratio_num = 1; + character_clock_ratio_den = 1; + break; + default: + debug("Invalid ColorDepth\n"); + } + break; + + default: + switch (bpp) { + /* Assume RGB */ + case 10: + clk_ratio = CLK_RATIO_5_4; + character_clock_ratio_num = 5; + character_clock_ratio_den = 4; + break; + case 12: + clk_ratio = CLK_RATIO_3_2; + character_clock_ratio_num = 3; + character_clock_ratio_den = 2; + break; + case 16: + clk_ratio = CLK_RATIO_2_1; + character_clock_ratio_num = 2; + character_clock_ratio_den = 1; + break; + default: + clk_ratio = CLK_RATIO_1_1; + character_clock_ratio_num = 1; + character_clock_ratio_den = 1; + } + } + + character_freq_khz = pixel_freq_khz * + character_clock_ratio_num / character_clock_ratio_den; + ftemp = pixel_freq_khz; + ftemp2 = character_freq_khz; + debug("Pixel clock frequency: %u kHz, character clock frequency: %u, color depth is %0d-bit.\n", + ftemp, ftemp2, bpp); + if (pixel_clk_from_phy == 0) { + /* ----------------------------------------------------------- + * Describing Task phy_cfg_hdmi_pll0_0pt5736 (Clock is input) + * -----------------------------------------------------------*/ + + /* register CMN_PLL0_VCOCAL_INIT_TMR */ + write16(0x0084, 0x0064); + /* register CMN_PLL0_VCOCAL_ITER_TMR */ + write16(0x0085, 0x000A); + /* register PHY_HDP_CLK_CTL */ + reg_val = read16(0xC009); + reg_val &= 0x00FF; + reg_val |= 0x1200; + write16(0xC009, reg_val); + + switch (clk_ratio) { + case CLK_RATIO_1_1: + if (inside(pixel_freq_khz, 340000, 600000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x3C); + set_field_value(&cmnda_pll0_fb_div_low, 0x24A); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 600); + } else if (inside(pixel_freq_khz, 170000, 340000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x22); + set_field_value(&cmnda_pll0_fb_div_low, 0x146); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x07); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 340); + } else if (inside(pixel_freq_khz, 85000, 170000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x11); + set_field_value(&cmnda_pll0_fb_div_low, 0x146); + set_field_value(&cmn_ref_clk_dig_div, 0x00); + set_field_value(÷r_scaler, 0x07); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 340); + } else if (inside(pixel_freq_khz, 42500, 85000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + set_field_value(&cmnda_pll0_ip_div, 0x08); + set_field_value(&cmnda_pll0_fb_div_low, 0x132); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 320); + } else if (inside(pixel_freq_khz, 25000, 42500)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + set_field_value(&cmnda_pll0_ip_div, 0x05); + set_field_value(&cmnda_pll0_fb_div_low, 0x182); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 400); + } else { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } + break; + + case CLK_RATIO_5_4: + if (inside(pixel_freq_khz, 272000, 480000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x30); + set_field_value(&cmnda_pll0_fb_div_low, 0x24A); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x05); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 600); + } else if (inside(pixel_freq_khz, 136000, 272000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x1A); + set_field_value(&cmnda_pll0_fb_div_low, 0x137); + set_field_value(&cmn_ref_clk_dig_div, 0x02); + set_field_value(÷r_scaler, 0x04); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 325); + } else if (inside(pixel_freq_khz, 68000, 136000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x0D); + set_field_value(&cmnda_pll0_fb_div_low, 0x137); + set_field_value(&cmn_ref_clk_dig_div, 0x02); + set_field_value(÷r_scaler, 0x02); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 325); + } else if (inside(pixel_freq_khz, 34000, 68000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + set_field_value(&cmnda_pll0_ip_div, 0x06); + set_field_value(&cmnda_pll0_fb_div_low, 0x11E); + set_field_value(&cmn_ref_clk_dig_div, 0x02); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 300); + } else if (inside(pixel_freq_khz, 25000, 34000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmnda_pll0_fb_div_low, 0x182); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 400); + } else { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } + break; + case CLK_RATIO_3_2: + if (inside(pixel_freq_khz, 226000, 400000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x28); + set_field_value(&cmnda_pll0_fb_div_low, 0x24A); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x04); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 600); + } else if (inside(pixel_freq_khz, 113000, 226000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x16); + set_field_value(&cmnda_pll0_fb_div_low, 0x13C); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x05); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 330); + } else if (inside(pixel_freq_khz, 56000, 113000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x0B); + set_field_value(&cmnda_pll0_fb_div_low, 0x13C); + set_field_value(&cmn_ref_clk_dig_div, 0x00); + set_field_value(÷r_scaler, 0x05); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 330); + } else if (inside(pixel_freq_khz, 28000, 56000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + set_field_value(&cmnda_pll0_ip_div, 0x06); + set_field_value(&cmnda_pll0_fb_div_low, 0x15A); + set_field_value(&cmn_ref_clk_dig_div, 0x02); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 360); + } else if (inside(pixel_freq_khz, 25000, 28000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmnda_pll0_fb_div_low, 0x15A); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 360); + } else { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } + break; + case CLK_RATIO_2_1: + if (inside(pixel_freq_khz, 170000, 300000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x22); + set_field_value(&cmnda_pll0_fb_div_low, 0x29A); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 680); + } else if (inside(pixel_freq_khz, 85000, 170000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x11); + set_field_value(&cmnda_pll0_fb_div_low, 0x146); + set_field_value(&cmn_ref_clk_dig_div, 0x00); + set_field_value(÷r_scaler, 0x07); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 340); + } else if (inside(pixel_freq_khz, 42500, 85000)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x08); + set_field_value(&cmnda_pll0_fb_div_low, 0x132); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 320); + } else if (inside(pixel_freq_khz, 25000, 42500)) { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + set_field_value(&cmnda_pll0_ip_div, 0x05); + set_field_value(&cmnda_pll0_fb_div_low, 0x182); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&pll_feedback_divider_total, + 400); + } else { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } + break; + case CLK_RATIO_1_2: + if (!(inside(pixel_freq_khz, 594000, 594000))) { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } else { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + set_field_value(&cmnda_pll0_ip_div, 0x3C); + set_field_value(&cmnda_pll0_fb_div_low, 0x24A); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 600); + } + break; + case CLK_RATIO_5_8: + if (!(inside(pixel_freq_khz, 594000, 594000))) { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } else { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x3C); + set_field_value(&cmnda_pll0_fb_div_low, 0x169); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 375); + } + break; + case CLK_RATIO_3_4: + if (!(inside(pixel_freq_khz, 594000, 594000))) { + ftemp = pixel_freq_khz; + debug("Pixel clock frequency (%u) is outside of the supported range\n", + ftemp); + } else { + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + set_field_value(&cmnda_pll0_ip_div, 0x3C); + set_field_value(&cmnda_pll0_fb_div_low, 0x1B4); + set_field_value(&cmn_ref_clk_dig_div, 0x03); + set_field_value(÷r_scaler, 0x06); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&pll_feedback_divider_total, + 450); + } + break; + } + vco_freq = + pixel_freq_khz * pll_feedback_divider_total.value / + cmnda_pll0_ip_div.value; + ftemp = vco_freq; + debug("VCO frequency is %u kHz\n", ftemp); + + if (inside(vco_freq, 1700000, 2000000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x09); + set_field_value(&ptat_ndac_ctrl, 0x09); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x82); + break; + case 320: + set_field_value(&charge_pump_gain, 0x83); + break; + case 325: + set_field_value(&charge_pump_gain, 0x83); + break; + case 330: + set_field_value(&charge_pump_gain, 0x84); + break; + case 340: + set_field_value(&charge_pump_gain, 0x84); + break; + case 360: + set_field_value(&charge_pump_gain, 0x86); + break; + case 400: + set_field_value(&charge_pump_gain, 0xA2); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 2000000, 2400000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x09); + set_field_value(&ptat_ndac_ctrl, 0x09); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x47); + break; + case 320: + set_field_value(&charge_pump_gain, 0x4B); + break; + case 325: + set_field_value(&charge_pump_gain, 0x4C); + break; + case 330: + set_field_value(&charge_pump_gain, 0x80); + break; + case 340: + set_field_value(&charge_pump_gain, 0x81); + break; + case 360: + set_field_value(&charge_pump_gain, 0x82); + break; + case 400: + set_field_value(&charge_pump_gain, 0x84); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 2400000, 2800000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x43); + break; + case 320: + set_field_value(&charge_pump_gain, 0x45); + break; + case 325: + set_field_value(&charge_pump_gain, 0x45); + break; + case 330: + set_field_value(&charge_pump_gain, 0x45); + break; + case 340: + set_field_value(&charge_pump_gain, 0x86); + break; + case 360: + set_field_value(&charge_pump_gain, 0x4A); + break; + case 400: + set_field_value(&charge_pump_gain, 0x81); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 2800000, 3400000)) { + set_field_value(&voltage_to_current_coarse, 0x06); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x3D); + break; + case 320: + set_field_value(&charge_pump_gain, 0x41); + break; + case 325: + set_field_value(&charge_pump_gain, 0x41); + break; + case 330: + set_field_value(&charge_pump_gain, 0x41); + break; + case 340: + set_field_value(&charge_pump_gain, 0x42); + break; + case 360: + set_field_value(&charge_pump_gain, 0x43); + break; + case 400: + set_field_value(&charge_pump_gain, 0x46); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 3400000, 3900000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + switch (pll_feedback_divider_total.value) { + case 375: + set_field_value(&charge_pump_gain, 0x41); + break; + case 600: + set_field_value(&charge_pump_gain, 0x82); + break; + case 680: + set_field_value(&charge_pump_gain, 0x85); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 3900000, 4500000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + switch (pll_feedback_divider_total.value) { + case 450: + set_field_value(&charge_pump_gain, 0x41); + break; + case 600: + set_field_value(&charge_pump_gain, 0x4B); + break; + case 680: + set_field_value(&charge_pump_gain, 0x82); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 4500000, 5200000)) { + set_field_value(&voltage_to_current_coarse, 0x06); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 600: + set_field_value(&charge_pump_gain, 0x45); + break; + case 680: + set_field_value(&charge_pump_gain, 0x4A); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else if (inside(vco_freq, 5200000, 6000000)) { + set_field_value(&voltage_to_current_coarse, 0x07); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 600: + set_field_value(&charge_pump_gain, 0x42); + break; + case 680: + set_field_value(&charge_pump_gain, 0x45); + break; + default: + debug("pll_feedback_divider_total (%0d) is outside of the supported range for vco_freq equal %u\n", + pll_feedback_divider_total.value, ftemp); + } + } else + debug("VCO frequency %u kHz is outside of the supported range\n", + ftemp); + + /* register CMN_DIAG_PLL0_INCLK_CTRL */ + reg_val = set_reg_value(cmnda_pll0_hs_sym_div_sel); + reg_val |= set_reg_value(cmnda_pll0_ip_div); + write16(0x01CA, reg_val); + /* register CMN_DIAG_PLL0_FBL_OVRD */ + reg_val = set_reg_value(cmnda_pll0_fb_div_low); + reg_val |= (1 << 15); + write16(0x01C1, reg_val); + /* register PHY_PMA_CMN_CTRL1 */ + reg_val = read16(0xC800); + reg_val &= 0xCFFF; + reg_val |= set_reg_value(cmn_ref_clk_dig_div); + write16(0xC800, reg_val); + /* register CMN_CDIAG_REFCLK_CTRL */ + reg_val = read16(0x0062); + reg_val &= 0x8FFF; + reg_val |= set_reg_value(divider_scaler); + reg_val |= 0x00C0; + write16(0x0062, reg_val); + /* register CMN_DIAG_HSCLK_SEL */ + reg_val = read16(0x01E0); + reg_val &= 0xFF00; + reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0; + reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4; + write16(0x01E0, reg_val); + + /* register XCVR_DIAG_HSCLK_SEL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x40E1 | (k << 9)); + reg_val &= 0xCFFF; + reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12; + write16(0x40E1 | (k << 9), reg_val); + } + + /* register TX_DIAG_TX_CTRL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x41E0 | (k << 9)); + reg_val &= 0xFF3F; + reg_val |= (tx_subrate.value >> 1) << 6; + write16(0x41E0 | (k << 9), reg_val); + } + + /* register CMN_PLLSM0_USER_DEF_CTRL */ + reg_val = set_reg_value(vco_ring_select); + write16(0x002F, reg_val); + /* register CMN_DIAG_PLL0_OVRD */ + write16(0x01C2, 0x0000); + /* register CMN_DIAG_PLL0_FBH_OVRD */ + reg_val = set_reg_value(cmnda_pll0_fb_div_high); + reg_val |= (1 << 15); + write16(0x01C0, reg_val); + /* register CMN_DIAG_PLL0_V2I_TUNE */ + reg_val = set_reg_value(voltage_to_current_coarse); + reg_val |= set_reg_value(voltage_to_current); + write16(0x01C5, reg_val); + /* register CMN_DIAG_PLL0_PTATIS_TUNE1 */ + reg_val = set_reg_value(pmos_ctrl); + reg_val |= set_reg_value(ndac_ctrl); + write16(0x01C8, reg_val); + /* register CMN_DIAG_PLL0_PTATIS_TUNE2 */ + reg_val = set_reg_value(ptat_ndac_ctrl); + write16(0x01C9, reg_val); + /* register CMN_DIAG_PLL0_CP_TUNE */ + reg_val = set_reg_value(charge_pump_gain); + write16(0x01C6, reg_val); + /* register CMN_DIAG_PLL0_LF_PROG */ + write16(0x01C7, 0x0008); + + /* register XCVR_DIAG_PLLDRC_CTRL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x40E0 | (k << 9)); + reg_val &= 0xBFFF; + write16(0x40E0 | (k << 9), reg_val); + } + + } else { + /* Describing task phy_cfg_hdmi_pll0_0pt099_ver2 + (Clock is OUTPUT) */ + if (inside(pixel_freq_khz, 27000, 27000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 240); + set_field_value(&cmnda_pll0_fb_div_low, 0xBC); + set_field_value(&cmnda_pll0_fb_div_high, 0x30); + set_field_value(&cmnda_pll0_pxdiv_low, 0x26); + set_field_value(&cmnda_pll0_pxdiv_high, 0x26); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 300); + set_field_value(&cmnda_pll0_fb_div_low, 0x0EC); + set_field_value(&cmnda_pll0_fb_div_high, 0x03C); + set_field_value(&cmnda_pll0_pxdiv_low, 0x030); + set_field_value(&cmnda_pll0_pxdiv_high, 0x030); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 360); + set_field_value(&cmnda_pll0_fb_div_low, 0x11C); + set_field_value(&cmnda_pll0_fb_div_high, 0x048); + set_field_value(&cmnda_pll0_pxdiv_low, 0x03A); + set_field_value(&cmnda_pll0_pxdiv_high, 0x03A); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 240); + set_field_value(&cmnda_pll0_fb_div_low, 0x0BC); + set_field_value(&cmnda_pll0_fb_div_high, 0x030); + set_field_value(&cmnda_pll0_pxdiv_low, 0x026); + set_field_value(&cmnda_pll0_pxdiv_high, 0x026); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 54000, 54000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 480); + set_field_value(&cmnda_pll0_fb_div_low, 0x17C); + set_field_value(&cmnda_pll0_fb_div_high, 0x060); + set_field_value(&cmnda_pll0_pxdiv_low, 0x026); + set_field_value(&cmnda_pll0_pxdiv_high, 0x026); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 400); + set_field_value(&cmnda_pll0_fb_div_low, 0x13C); + set_field_value(&cmnda_pll0_fb_div_high, 0x050); + set_field_value(&cmnda_pll0_pxdiv_low, 0x017); + set_field_value(&cmnda_pll0_pxdiv_high, 0x017); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 480); + set_field_value(&cmnda_pll0_fb_div_low, 0x17C); + set_field_value(&cmnda_pll0_fb_div_high, 0x060); + set_field_value(&cmnda_pll0_pxdiv_low, 0x01C); + set_field_value(&cmnda_pll0_pxdiv_high, 0x01C); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 240); + set_field_value(&cmnda_pll0_fb_div_low, 0x0bc); + set_field_value(&cmnda_pll0_fb_div_high, 0x030); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 74250, 74250)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x026); + set_field_value(&cmnda_pll0_pxdiv_high, 0x026); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x03); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 550); + set_field_value(&cmnda_pll0_fb_div_low, 0x1b4); + set_field_value(&cmnda_pll0_fb_div_high, 0x06e); + set_field_value(&cmnda_pll0_pxdiv_low, 0x017); + set_field_value(&cmnda_pll0_pxdiv_high, 0x017); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x04); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x01c); + set_field_value(&cmnda_pll0_pxdiv_high, 0x01c); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 330); + set_field_value(&cmnda_pll0_fb_div_low, 0x104); + set_field_value(&cmnda_pll0_fb_div_high, 0x042); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 99000, 99000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 440); + set_field_value(&cmnda_pll0_fb_div_low, 0x15c); + set_field_value(&cmnda_pll0_fb_div_high, 0x058); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 275); + set_field_value(&cmnda_pll0_fb_div_low, 0x0d8); + set_field_value(&cmnda_pll0_fb_div_high, 0x037); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00b); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00a); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 330); + set_field_value(&cmnda_pll0_fb_div_low, 0x104); + set_field_value(&cmnda_pll0_fb_div_high, 0x042); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00d); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00d); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 440); + set_field_value(&cmnda_pll0_fb_div_low, 0x15c); + set_field_value(&cmnda_pll0_fb_div_high, 0x058); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 148500, 148500)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x02); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 550); + set_field_value(&cmnda_pll0_fb_div_low, 0x1b4); + set_field_value(&cmnda_pll0_fb_div_high, 0x06e); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00b); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00a); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 495); + set_field_value(&cmnda_pll0_fb_div_low, 0x188); + set_field_value(&cmnda_pll0_fb_div_high, 0x063); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00d); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00d); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x012); + set_field_value(&cmnda_pll0_pxdiv_high, 0x012); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x02); + set_field_value(&cmnda_hs_clk_1_sel, 0x02); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 198000, 198000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 220); + set_field_value(&cmnda_pll0_fb_div_low, 0x0ac); + set_field_value(&cmnda_pll0_fb_div_high, 0x02c); + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_5_4: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 550); + set_field_value(&cmnda_pll0_fb_div_low, 0x1b4); + set_field_value(&cmnda_pll0_fb_div_high, 0x06e); + set_field_value(&cmnda_pll0_pxdiv_low, 0x00b); + set_field_value(&cmnda_pll0_pxdiv_high, 0x00a); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 330); + set_field_value(&cmnda_pll0_fb_div_low, 0x104); + set_field_value(&cmnda_pll0_fb_div_high, 0x042); + set_field_value(&cmnda_pll0_pxdiv_low, 0x006); + set_field_value(&cmnda_pll0_pxdiv_high, 0x005); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 440); + set_field_value(&cmnda_pll0_fb_div_low, 0x15c); + set_field_value(&cmnda_pll0_fb_div_high, 0x058); + set_field_value(&cmnda_pll0_pxdiv_low, 0x008); + set_field_value(&cmnda_pll0_pxdiv_high, 0x008); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + default: + break; + } + } else if (inside(pixel_freq_khz, 297000, 297000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 330); + set_field_value(&cmnda_pll0_fb_div_low, 0x104); + set_field_value(&cmnda_pll0_fb_div_high, 0x042); + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x00); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_3_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 495); + set_field_value(&cmnda_pll0_fb_div_low, 0x188); + set_field_value(&cmnda_pll0_fb_div_high, 0x063); + set_field_value(&cmnda_pll0_pxdiv_low, 0x006); + set_field_value(&cmnda_pll0_pxdiv_high, 0x005); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_2_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x008); + set_field_value(&cmnda_pll0_pxdiv_high, 0x008); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + default: + ftemp = pixel_freq_khz; + debug("This pixel clock frequency (%u kHz) is not supported with this (%0d-bit) color depth.\n", + ftemp, bpp); + } + } else if (inside(pixel_freq_khz, 594000, 594000)) { + switch (clk_ratio) { + case CLK_RATIO_1_1: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_1_2: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 660); + set_field_value(&cmnda_pll0_fb_div_low, 0x20c); + set_field_value(&cmnda_pll0_fb_div_high, 0x084); + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x02); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x01); + break; + case CLK_RATIO_5_8: + set_field_value(&cmnda_pll0_ip_div, 0x04); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 550); + set_field_value(&cmnda_pll0_fb_div_low, 0x1b4); + set_field_value(&cmnda_pll0_fb_div_high, 0x06e); + /* does not matter - pixel clock delivered to + controller from SoC */ + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + /* does not matter - pixel clock delivered to + controller from SoC */ + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + case CLK_RATIO_3_4: + set_field_value(&cmnda_pll0_ip_div, 0x03); + set_field_value(&cmn_ref_clk_dig_div, 0x01); + set_field_value(÷r_scaler, 0x01); + set_field_value(&pll_feedback_divider_total, + 495); + set_field_value(&cmnda_pll0_fb_div_low, 0x188); + set_field_value(&cmnda_pll0_fb_div_high, 0x063); + /* does not matter - pixel clock delivered to + controller from SoC */ + set_field_value(&cmnda_pll0_pxdiv_low, 0x003); + /* does not matter - pixel clock delivered to + controller from SoC */ + set_field_value(&cmnda_pll0_pxdiv_high, 0x003); + set_field_value(&vco_ring_select, 0x01); + set_field_value(&cmnda_hs_clk_0_sel, 0x01); + set_field_value(&cmnda_hs_clk_1_sel, 0x01); + set_field_value(&tx_subrate, 0x01); + set_field_value(&cmnda_pll0_hs_sym_div_sel, + 0x00); + break; + default: + debug("This pixel clock frequency (%d KHz) is not supported with this (%0d-bit) color depth.\n", + pixel_freq_khz, bpp); + } + } else { + ftemp = pixel_freq_khz; + debug("This pixel clock frequency (%u kHz) is not supported.\n", + ftemp); + } + + vco_freq = + refclk_freq_khz * pll_feedback_divider_total.value / + cmnda_pll0_ip_div.value; + ftemp = vco_freq; + debug("VCO frequency is %u kHz\n", ftemp); + + if (inside(vco_freq, 1980000, 1980000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x09); + set_field_value(&ptat_ndac_ctrl, 0x09); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 160); + set_field_value(&v2i_code, 5); + set_field_value(&vco_cal_code, 183); + } else if (inside(vco_freq, 2160000, 2160000)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x09); + set_field_value(&ptat_ndac_ctrl, 0x09); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 166); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 208); + } else if (inside(vco_freq, 2475000, 2475000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 167); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 209); + } else if (inside(vco_freq, 2700000, 2700000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 300: + set_field_value(&charge_pump_gain, 0x042); + break; + case 400: + set_field_value(&charge_pump_gain, 0x04c); + break; + } + set_field_value(&coarse_code, 188); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 225); + } else if (inside(vco_freq, 2970000, 2970000)) { + set_field_value(&voltage_to_current_coarse, 0x06); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 183); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 225); + } else if (inside(vco_freq, 3240000, 3240000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + switch (pll_feedback_divider_total.value) { + case 360: + set_field_value(&charge_pump_gain, 0x042); + break; + case 480: + set_field_value(&charge_pump_gain, 0x04c); + break; + } + set_field_value(&coarse_code, 203); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 256); + } else if (inside(vco_freq, 3712500, 3712500)) { + set_field_value(&voltage_to_current_coarse, 0x04); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + set_field_value(&charge_pump_gain, 0x04c); + set_field_value(&coarse_code, 212); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 257); + } else if (inside(vco_freq, 3960000, 3960000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 184); + set_field_value(&v2i_code, 6); + set_field_value(&vco_cal_code, 226); + } else if (inside(vco_freq, 4320000, 4320000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 205); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 258); + } else if (inside(vco_freq, 4455000, 4455000)) { + set_field_value(&voltage_to_current_coarse, 0x05); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x00); + set_field_value(&pmos_ctrl, 0x07); + set_field_value(&ptat_ndac_ctrl, 0x0F); + switch (pll_feedback_divider_total.value) { + case 495: + set_field_value(&charge_pump_gain, 0x042); + break; + case 660: + set_field_value(&charge_pump_gain, 0x04c); + break; + } + set_field_value(&coarse_code, 219); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 272); + } else if (inside(vco_freq, 4950000, 4950000)) { + set_field_value(&voltage_to_current_coarse, 0x06); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 213); + set_field_value(&v2i_code, 7); + set_field_value(&vco_cal_code, 258); + } else if (inside(vco_freq, 5940000, 5940000)) { + set_field_value(&voltage_to_current_coarse, 0x07); + set_field_value(&voltage_to_current, 0x03); + set_field_value(&ndac_ctrl, 0x01); + set_field_value(&pmos_ctrl, 0x00); + set_field_value(&ptat_ndac_ctrl, 0x07); + set_field_value(&charge_pump_gain, 0x042); + set_field_value(&coarse_code, 244); + set_field_value(&v2i_code, 8); + set_field_value(&vco_cal_code, 292); + } else { + ftemp = vco_freq; + debug("Current vco_freq (%u kHz) is not supported.\n", + ftemp); + } + + /* register CMN_PLL0_VCOCAL_INIT_TMR */ + write16(0x0084, 0x0064); + /* register CMN_PLL0_VCOCAL_ITER_TMR */ + write16(0x0085, 0x000A); + /* register PHY_HDP_CLK_CTL */ + reg_val = read16(0xC009); + reg_val &= 0x00FF; + reg_val |= 0x2 << 8; + reg_val |= 0x1 << 12; + write16(0xC009, reg_val); + /* register CMN_DIAG_PLL0_INCLK_CTRL */ + reg_val = set_reg_value(cmnda_pll0_ip_div); + reg_val |= set_reg_value(cmnda_pll0_hs_sym_div_sel); + write16(0x01CA, reg_val); + /* register CMN_DIAG_PLL0_FBH_OVRD */ + reg_val = set_reg_value(cmnda_pll0_fb_div_high); + reg_val |= (1 << 15); + write16(0x01C0, reg_val); + /* register CMN_DIAG_PLL0_FBL_OVRD */ + reg_val = set_reg_value(cmnda_pll0_fb_div_low); + reg_val |= (1 << 15); + write16(0x01C1, reg_val); + /* register CMN_DIAG_PLL0_PXL_DIVL */ + reg_val = set_reg_value(cmnda_pll0_pxdiv_low); + write16(0x01CC, reg_val); + /* register CMN_DIAG_PLL0_PXL_DIVH */ + reg_val = set_reg_value(cmnda_pll0_pxdiv_high); + reg_val |= (1 << 15); + write16(0x01CB, reg_val); + + /* register TX_DIAG_TX_CTRL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x41E0 | (k << 9)); + reg_val &= 0xFF3F; + reg_val |= (tx_subrate.value >> 1) << 6; + write16(0x41E0 | (k << 9), reg_val); + } + + /* register PHY_PMA_CMN_CTRL1 */ + reg_val = read16(0xC800); + reg_val &= 0xCFFF; + reg_val |= set_reg_value(cmn_ref_clk_dig_div); + write16(0xC800, reg_val); + /* register CMN_CDIAG_REFCLK_CTRL */ + reg_val = read16(0x0062); + reg_val &= 0x8FFF; + reg_val |= set_reg_value(divider_scaler); + reg_val |= 0x00C0; + write16(0x0062, reg_val); + /* register CMN_DIAG_HSCLK_SEL */ + reg_val = read16(0x01E0); + reg_val &= 0xFF00; + reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 0; + reg_val |= (cmnda_hs_clk_1_sel.value >> 1) << 4; + write16(0x01E0, reg_val); + /* register CMN_PLLSM0_USER_DEF_CTRL */ + reg_val = set_reg_value(vco_ring_select); + write16(0x002F, reg_val); + + /* register XCVR_DIAG_HSCLK_SEL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x40E1 | (k << 9)); + reg_val &= 0xCFFF; + reg_val |= (cmnda_hs_clk_0_sel.value >> 1) << 12; + write16(0x40E1 | (k << 9), reg_val); + } + + /* register CMN_DIAG_PLL0_OVRD */ + write16(0x01C2, 0x0000); + /* register CMN_DIAG_PLL0_V2I_TUNE */ + reg_val = set_reg_value(voltage_to_current_coarse); + reg_val |= set_reg_value(voltage_to_current); + write16(0x01C5, reg_val); + /* register CMN_DIAG_PLL0_PTATIS_TUNE1 */ + reg_val = set_reg_value(pmos_ctrl); + reg_val |= set_reg_value(ndac_ctrl); + write16(0x01C8, reg_val); + /* register CMN_DIAG_PLL0_PTATIS_TUNE2 */ + reg_val = set_reg_value(ptat_ndac_ctrl); + write16(0x01C9, reg_val); + /* register CMN_PLL0_VCOCAL_START */ + reg_val = read16(0x0081); + reg_val &= 0xFE00; + reg_val |= set_reg_value(vco_cal_code); + write16(0x0081, reg_val); + /* register CMN_DIAG_PLL0_CP_TUNE */ + reg_val = set_reg_value(charge_pump_gain); + write16(0x01C6, reg_val); + /* register CMN_DIAG_PLL0_LF_PROG */ + write16(0x01C7, 0x0008); + + /* register XCVR_DIAG_PLLDRC_CTRL */ + for (k = 0; k < num_lanes; k++) { + reg_val = read16(0x40E0 | (k << 9)); + reg_val &= 0xBFFF; + write16(0x40E0 | (k << 9), reg_val); + } + } + + /* Back to task phy_cfg_hdp */ + + /* register PHY_PMA_CMN_CTRL1 */ + reg_val = read16(0xC800); + reg_val &= 0xFF8F; + /* for differential clock on the refclk_p and refclk_m + * off chip pins: PHY_PMA_CMN_CTRL1[6:4]=3'b000 */ + reg_val |= 0x0000; + write16(0xC800, reg_val); + + /* register CMN_DIAG_ACYA */ + write16(0x01FF, 0x0100); + + if (phy_reset_workaround) { + /* register PHY_ISO_CMN_CTRL */ + write16(0xC010, 0x0001); /* Deassert PHY reset */ + /* register PHY_PMA_ISO_CMN_CTRL */ + write16(0xC810, 0x0003); + for (k = 0; k < num_lanes; k++) { + /* register XCVR_PSM_RCTRL */ + write16(0x4001 | (k << 9), 0xFEFC); + } + /* register PHY_PMA_ISO_CMN_CTRL + * Assert cmn_macro_pwr_en*/ + write16(0xC810, 0x0013); + + /* PHY_PMA_ISO_CMN_CTRL + * wait for cmn_macro_pwr_en_ack*/ + while (!(read16(0xC810) & (1 << 5))) + ; + + /* PHY_PMA_CMN_CTRL1 wait for cmn_ready */ + while (!(read16(0xC800) & (1 << 0))) + ; + } else { + for (k = 0; k < num_lanes; k++) { + /* register XCVR_PSM_RCTRL */ + write16(0x4001 | (k << 9), 0xBEFC); + } + } + for (k = 0; k < num_lanes; k++) { + /* register TX_PSC_A0 */ + write16(0x4100 | (k << 9), 0x6791); + /* register TX_PSC_A1 */ + write16(0x4101 | (k << 9), 0x6790); + /* register TX_PSC_A2 */ + write16(0x4102 | (k << 9), 0x0090); + /* register TX_PSC_A3 */ + write16(0x4103 | (k << 9), 0x0090); + /* register RX_PSC_CAL */ + reg_val = read16(0x8006 | (k << 9)); + reg_val &= 0xFFBB; + write16(0x8006 | (k << 9), reg_val); + reg_val = read16(0x8000 | (k << 9)); + reg_val &= 0xFFBB; + write16(0x8000 | (k << 9), reg_val); + } + + /* End of task phy_cfg_hdp */ + /* register PHY_HDP_MODE_CTL */ + write16(0xC008, 0x0004); + + aux_cfg_t28hpc(); + return character_freq_khz; +} + +int hdmi_tx_t28hpc_power_config_seq(int num_lanes) +{ + unsigned char k; + + /* Configure the power state. + * register TX_DIAG_ACYA */ + for (k = 0; k < num_lanes; k++) { + /* register XCVR_PSM_CAL_TMR */ + write16(0x41FF | (k << 9), 0x0001); + } + + /* register PHY_DP_MODE_CTL */ + while (!(read16(0xC008) & (1 << 6))) + ; + + /* PHY_DP_MODE_CTL */ + write16(0xC008, (((0x0F << num_lanes) & 0x0F) << 12) | 0x0101); + + /* PHY_DP_MODE_CTL */ + while (!(read16(0xC008) & (1 << 4))) + ; + + return 0; +} diff --git a/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.h b/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.h new file mode 100644 index 00000000000..756c1d577e1 --- /dev/null +++ b/drivers/video/nxp/hdp/API_AFE_t28hpc_hdmitx.h @@ -0,0 +1,64 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AFE_t28hpc_hdmitx.h + * + ****************************************************************************** + */ + +#ifndef API_AFE_T28HPC_HDMITX_H_ +#define API_AFE_T28HPC_HDMITX_H_ + +#ifndef __UBOOT__ +#include +#include +#else +#include +#endif +#include "vic_table.h" +#include "API_AFE.h" +#include "externs.h" + +int phy_cfg_t28hpc(int num_lanes, VIC_MODES vic_mode, int bpp, + VIC_PXL_ENCODING_FORMAT format, bool pixel_clk_from_phy); +int hdmi_tx_t28hpc_power_config_seq(int num_lanes); + +#endif diff --git a/drivers/video/nxp/hdp/API_AVI.c b/drivers/video/nxp/hdp/API_AVI.c new file mode 100644 index 00000000000..4a6c3ee17d5 --- /dev/null +++ b/drivers/video/nxp/hdp/API_AVI.c @@ -0,0 +1,192 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AVI.c + * + ****************************************************************************** + */ + +#include "API_AVI.h" +#include "API_Infoframe.h" + +CDN_API_STATUS cdn_api_set_avi(VIC_MODES vic_mode, + VIC_PXL_ENCODING_FORMAT color_mode, + BT_TYPE itu_ver) +{ + unsigned int active_slot = vic_table[vic_mode][H_BLANK]; + unsigned int line_width = vic_table[vic_mode][H_TOTAL]; + unsigned int hactive = line_width - active_slot + 1; + unsigned int vactive = vic_table[vic_mode][V_ACTIVE] + 1; + + unsigned int hactive_l = hactive - 256 * ((unsigned int)hactive / 256); + unsigned int hactive_h = hactive / 256; + unsigned int vactive_l = vactive - 256 * ((unsigned int)vactive / 256); + unsigned int vactive_h = vactive / 256; + + /* unsigned int packet; */ + + unsigned int packet_type = 0x82; + unsigned int packet_version = 0x2; + unsigned int packet_len = 0xd; + unsigned int packet_y = 0; + unsigned int packet_c = 0; + unsigned int packet_r = 0; + unsigned int packet_vic = 0; + unsigned int packet_pr = 0; + unsigned int packet_buf_size = 5; /* Total buf length is 18, aligned with 4 bytes, need 5 words */ + unsigned int packet_buf[packet_buf_size]; + unsigned char *packet = (unsigned char *)&packet_buf[0]; + unsigned int packet_hb0 = 0; + unsigned int packet_hb1 = 0; + unsigned int packet_hb2 = 0; + unsigned int packet_pb0 = 0; + unsigned int packet_pb1 = 0; + unsigned int packet_pb2 = 0; + unsigned int packet_pb3 = 0; + unsigned int packet_pb4 = 0; + unsigned int packet_pb5 = 0; + unsigned int packet_pb6 = 0; + unsigned int packet_pb7 = 0; + unsigned int packet_pb8 = 0; + unsigned int packet_pb9 = 0; + unsigned int packet_pb10 = 0; + unsigned int packet_pb11 = 0; + unsigned int packet_pb12 = 0; + unsigned int packet_pb13 = 0; + unsigned int pb1_13_chksum = 0; + unsigned int packet_chksum = 0; + + if (color_mode == PXL_RGB) + packet_y = 0; + else if (color_mode == YCBCR_4_4_4) + packet_y = 2; + else if (color_mode == YCBCR_4_2_2) + packet_y = 1; + else if (color_mode == YCBCR_4_2_0) + packet_y = 3; + + /* Colorimetry: Nodata=0 IT601=1 ITU709=2 */ + if (itu_ver == BT_601) + packet_c = 1; + else if (itu_ver == BT_709) + packet_c = 2; + else + packet_c = 0; + + unsigned int packet_a0 = 1; + unsigned int packet_b = 0; + unsigned int packet_s = 0; + unsigned int packet_sc = 0; /* Picture Scaling */ + + /* Active Format Aspec Ratio: Same As Picture = 0x8 4:3(Center)=0x9 + 16:9=0xA 14:9=0xB */ + packet_r = vic_table[vic_mode][VIC_R3_0]; + /* Aspect Ratio: Nodata=0 4:3=1 16:9=2 */ + unsigned int packet_m = 0; + /* Quantization Range Default=0 Limited Range=0x1 FullRange=0x2 + Reserved 0x3 */ + unsigned int packet_q = 0; + /* Quantization Range 0=Limited Range FullRange=0x1 Reserved 0x3/2 */ + unsigned int packet_yq = 0; + /* Extended Colorimetry xvYCC601=0x0 xvYCC709=1 All other Reserved */ + unsigned int packet_ec = 0; + /*IT content nodata=0 ITcontent=1 */ + unsigned int packet_it = 0; + /* Video Code (CEA) */ + packet_vic = vic_table[vic_mode][VIC]; + /* Pixel Repetition 0 ... 9 (1-10) */ + packet_pr = vic_table[vic_mode][VIC_PR]; + /* Content Type */ + unsigned int packet_cn = 0; + + packet_hb0 = packet_type; + packet_hb1 = packet_version; + packet_hb2 = packet_len; + + packet_pb1 = 32 * packet_y + 16 * packet_a0 + 4 * packet_b + packet_s; + packet_pb2 = 64 * packet_c + 16 * packet_m + packet_r; + packet_pb3 = + 128 * packet_it + 16 * packet_ec + 4 * packet_q + packet_sc; + packet_pb4 = packet_vic; + packet_pb5 = 64 * packet_yq + 16 * packet_cn + packet_pr; + packet_pb6 = 0; + packet_pb7 = 0; + packet_pb8 = vactive_l; + packet_pb9 = vactive_h; + packet_pb10 = 0; + packet_pb11 = 0; + packet_pb12 = hactive_l; + packet_pb13 = hactive_h; + + pb1_13_chksum = + (packet_hb0 + packet_hb1 + packet_hb2 + packet_pb1 + + packet_pb2 + packet_pb3 + packet_pb4 + packet_pb5 + + packet_pb6 + packet_pb7 + packet_pb8 + packet_pb9 + + packet_pb10 + packet_pb11 + packet_pb12 + packet_pb13); + packet_chksum = + 256 - (pb1_13_chksum - + 256 * ((unsigned int)pb1_13_chksum / 256)); + packet_pb0 = packet_chksum; + + packet[0] = 0; + packet[1] = packet_hb0; + packet[2] = packet_hb1; + packet[3] = packet_hb2; + packet[4] = packet_pb0; + packet[5] = packet_pb1; + packet[6] = packet_pb2; + packet[7] = packet_pb3; + packet[8] = packet_pb4; + packet[9] = packet_pb5; + packet[10] = packet_pb6; + packet[11] = packet_pb7; + packet[12] = packet_pb8; + packet[13] = packet_pb9; + packet[14] = packet_pb10; + packet[15] = packet_pb11; + packet[16] = packet_pb12; + packet[17] = packet_pb13; + + cdn_api_infoframeset(0, packet_buf_size, + (unsigned int *)&packet[0], packet_type); + + return CDN_OK; +} /* End API */ diff --git a/drivers/video/nxp/hdp/API_AVI.h b/drivers/video/nxp/hdp/API_AVI.h new file mode 100644 index 00000000000..435ba3f9f8f --- /dev/null +++ b/drivers/video/nxp/hdp/API_AVI.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_AVI.h + * + ****************************************************************************** + */ + +#ifndef API_AVI_H_ +#define API_AVI_H_ + +#include "vic_table.h" +#include "API_General.h" + +CDN_API_STATUS cdn_api_set_avi( + VIC_MODES vic_mode, + VIC_PXL_ENCODING_FORMAT color_mode, + BT_TYPE itu_ver); + +#endif /*API_AVI_H_ */ + diff --git a/drivers/video/nxp/hdp/API_General.c b/drivers/video/nxp/hdp/API_General.c new file mode 100644 index 00000000000..fa3669e5346 --- /dev/null +++ b/drivers/video/nxp/hdp/API_General.c @@ -0,0 +1,486 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + ****************************************************************************** + * + * API_General.c + * + ****************************************************************************** + */ + +#include "API_General.h" +#include "util.h" +#ifndef __UBOOT__ +#include +#endif +#include "address.h" +#include "apb_cfg.h" +#include "opcodes.h" +#include "general_handler.h" +#include "externs.h" +#include +#ifndef __UBOOT__ +#include +#endif + +extern state_struct state; + +void cdn_api_init(void) +{ + memset(&state, 0, sizeof(state_struct)); +} + +CDN_API_STATUS hdp_rx_loadfirmware(unsigned char *imem, int imemsize, + unsigned char *dmem, int dmemsize) +{ + int i; + + for (i = 0; i < imemsize; i += 4) + if (hdp_rx_apb_write(ADDR_IMEM + i, + (unsigned int)imem[i] << 0 | + (unsigned int)imem[i + 1] << 8 | + (unsigned int)imem[i + 2] << 16 | + (unsigned int)imem[i + 3] << 24)) + return CDN_ERR; + for (i = 0; i < dmemsize; i += 4) + if (hdp_rx_apb_write(ADDR_DMEM + i, + (unsigned int)dmem[i] << 0 | + (unsigned int)dmem[i + 1] << 8 | + (unsigned int)dmem[i + 2] << 16 | + (unsigned int)dmem[i + 3] << 24)) + return CDN_ERR; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_loadfirmware(unsigned char *imem, int imemsize, + unsigned char *dmem, int dmemsize) +{ + int i; + + for (i = 0; i < imemsize; i += 4) + if (cdn_apb_write(ADDR_IMEM + i, + (unsigned int)imem[i] << 0 | + (unsigned int)imem[i + 1] << 8 | + (unsigned int)imem[i + 2] << 16 | + (unsigned int)imem[i + 3] << 24)) + return CDN_ERR; + for (i = 0; i < dmemsize; i += 4) + if (cdn_apb_write(ADDR_DMEM + i, + (unsigned int)dmem[i] << 0 | + (unsigned int)dmem[i + 1] << 8 | + (unsigned int)dmem[i + 2] << 16 | + (unsigned int)dmem[i + 3] << 24)) + return CDN_ERR; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_test_echo(unsigned int val, + CDN_BUS_TYPE bus_type) +{ + CDN_API_STATUS ret; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + state.bus_type = bus_type; + state.rxenable = 1; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO, + 1, 4, val); + return CDN_STARTED; + } + if (state.txenable && !internal_mbox_tx_process().txend) + return CDN_BSY; + if (state.rxenable && !internal_mbox_rx_process().rxend) + return CDN_BSY; + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO); + if (ret != CDN_OK) { + state.running = 0; + return ret; + } + state.running = 0; + if (val != internal_betoi(state.rxbuffer + INTERNAL_CMD_HEAD_SIZE, 4)) + return CDN_ERR; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_test_echo_blocking(unsigned int val, + CDN_BUS_TYPE bus_type) +{ + internal_block_function(cdn_api_general_test_echo(val, bus_type)); +} + +CDN_API_STATUS cdn_api_general_test_echo_ext(u8 const *msg, u8 *resp, + u16 num_bytes, + CDN_BUS_TYPE bus_type) +{ + CDN_API_STATUS ret; + + if (!msg || !resp) + return CDN_ERR; + + if ((num_bytes > GENERAL_TEST_ECHO_MAX_PAYLOAD) || + (num_bytes < GENERAL_TEST_ECHO_MIN_PAYLOAD)) + return CDN_ERR; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + state.bus_type = bus_type; + state.rxenable = 1; + + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO, + 1, -num_bytes, msg); + + return CDN_STARTED; + } + + if (state.txenable && !internal_mbox_tx_process().txend) + return CDN_BSY; + + if (state.rxenable && !internal_mbox_rx_process().rxend) + return CDN_BSY; + + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ECHO); + + if (ret != CDN_OK) { + state.running = 0; + return ret; + } + + state.running = 0; + + memcpy(resp, state.rxbuffer + INTERNAL_CMD_HEAD_SIZE, num_bytes); + + if (memcmp(msg, resp, num_bytes) != 0) + return CDN_ERR; + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_test_echo_ext_blocking(u8 const *msg, + u8 *resp, + u16 num_bytes, + CDN_BUS_TYPE bus_type) +{ + internal_block_function(cdn_api_general_test_echo_ext + (msg, resp, num_bytes, bus_type)); +} + +CDN_API_STATUS cdn_api_general_getcurversion(unsigned short *ver, + unsigned short *verlib) +{ + unsigned int vh, vl, vlh, vll; + + if (cdn_apb_read(VER_L << 2, &vl)) + return CDN_ERR; + if (cdn_apb_read(VER_H << 2, &vh)) + return CDN_ERR; + if (cdn_apb_read(VER_LIB_L_ADDR << 2, &vll)) + return CDN_ERR; + if (cdn_apb_read(VER_LIB_H_ADDR << 2, &vlh)) + return CDN_ERR; + *ver = F_VER_MSB_RD(vh) << 8 | F_VER_LSB_RD(vl); + *verlib = F_SW_LIB_VER_H_RD(vlh) << 8 | F_SW_LIB_VER_L_RD(vll); + return CDN_OK; +} + +CDN_API_STATUS cdn_api_get_event(uint32_t *events) +{ + u32 evt[4] = { 0 }; + + if (!events) { + printf("events pointer is NULL!\n"); + return CDN_ERR; + } + + if (cdn_apb_read(SW_EVENTS0 << 2, &evt[0]) || + cdn_apb_read(SW_EVENTS1 << 2, &evt[1]) || + cdn_apb_read(SW_EVENTS2 << 2, &evt[2]) || + cdn_apb_read(SW_EVENTS3 << 2, &evt[3])) { + printf("Failed to read events registers.\n"); + return CDN_ERR; + } + + *events = (evt[0] & 0xFF) + | ((evt[1] & 0xFF) << 8) + | ((evt[2] & 0xFF) << 16) + | ((evt[3] & 0xFF) << 24); + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_get_debug_reg_val(uint16_t *val) +{ + u32 dbg[2] = { 0 }; + + if (!val) { + printf("val pointer is NULL!\n"); + return CDN_ERR; + } + + if (cdn_apb_read(SW_DEBUG_L << 2, &dbg[0]) || + cdn_apb_read(SW_DEBUG_H << 2, &dbg[1])) { + printf("Failed to read debug registers.\n"); + return CDN_ERR; + } + + *val = (u16)((dbg[0] & 0xFF) | ((dbg[1] & 0xFF) << 8)); + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_checkalive(void) +{ + unsigned int alive, newalive; + u8 retries_left = 10; + + if (cdn_apb_read(KEEP_ALIVE << 2, &alive)) + return CDN_ERR; + + while (retries_left--) { + udelay(1); + + if (cdn_apb_read(KEEP_ALIVE << 2, &newalive)) + return CDN_ERR; + + if (alive == newalive) + continue; + + return CDN_OK; + } + + printf("%s: keep-alive counter did not increment for 10us...\n", __func__); + + return CDN_BSY; +} + +CDN_API_STATUS cdn_api_checkalive_blocking(void) +{ + internal_block_function(cdn_api_checkalive()); +} + +CDN_API_STATUS cdn_api_maincontrol(unsigned char mode, unsigned char *resp) +{ + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + state.bus_type = CDN_BUS_TYPE_APB; + state.rxenable = 1; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_MAIN_CONTROL, 1, 1, mode); + return CDN_STARTED; + } + INTERNAL_PROCESS_MESSAGES; + internal_opcode_ok_or_return(MB_MODULE_ID_GENERAL, + GENERAL_MAIN_CONTROL_RESP); + internal_readmsg(1, 1, resp); + return CDN_OK; +} + +CDN_API_STATUS cdn_api_maincontrol_blocking(unsigned char mode, + unsigned char *resp) +{ + internal_block_function(cdn_api_maincontrol(mode, resp)); +} + +CDN_API_STATUS cdn_api_apbconf(u8 dpcd_bus_sel, u8 dpcd_bus_lock, + u8 hdcp_bus_sel, u8 hdcp_bus_lock, + u8 capb_bus_sel, u8 capb_bus_lock, + u8 *dpcd_resp, u8 *hdcp_resp, + u8 *capb_resp) +{ + u8 resp; + u8 set = 0; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + state.bus_type = CDN_BUS_TYPE_APB; + state.rxenable = 1; + + set |= (dpcd_bus_sel) + ? (1 << GENERAL_BUS_SETTINGS_DPCD_BUS_BIT) + : 0; + set |= (dpcd_bus_lock) + ? (1 << GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT) + : 0; + set |= (hdcp_bus_sel) + ? (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_BIT) + : 0; + set |= (hdcp_bus_lock) + ? (1 << GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT) + : 0; + set |= (capb_bus_sel) + ? (1 << GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT) + : 0; + set |= (capb_bus_lock) + ? (1 << GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT) + : 0; + + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_BUS_SETTINGS, 1, 1, set); + + return CDN_STARTED; + } + + INTERNAL_PROCESS_MESSAGES; + internal_opcode_ok_or_return(MB_MODULE_ID_GENERAL, + GENERAL_BUS_SETTINGS_RESP); + + /* Read one one-byte response */ + internal_readmsg(1, 1, &resp); + + *dpcd_resp = + (resp & (1 << GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT)) ? 1 : 0; + *hdcp_resp = + (resp & (1 << GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT)) ? 1 : 0; + *capb_resp = + (resp & (1 << GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT)) ? 1 : 0; + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_apbconf_blocking(u8 dpcd_bus_sel, + u8 dpcd_bus_lock, + u8 hdcp_bus_sel, + u8 hdcp_bus_lock, + u8 capb_bus_sel, + u8 capb_bus_lock, + u8 *dpcd_resp, + u8 *hdcp_resp, + u8 *capb_resp) +{ + internal_block_function(cdn_api_apbconf(dpcd_bus_sel, dpcd_bus_lock, + hdcp_bus_sel, hdcp_bus_lock, + capb_bus_sel, capb_bus_lock, + dpcd_resp, hdcp_resp, + capb_resp)); +} + +CDN_API_STATUS cdn_api_setclock(unsigned char mhz) +{ + return cdn_apb_write(SW_CLK_H << 2, mhz); +} + +CDN_API_STATUS cdn_api_general_read_register(unsigned int addr, + GENERAL_READ_REGISTER_RESPONSE + *resp) +{ + CDN_API_STATUS ret; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER, 1, 4, addr); + state.bus_type = CDN_BUS_TYPE_APB; + state.rxenable = 1; + return CDN_STARTED; + } + INTERNAL_PROCESS_MESSAGES; + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, + GENERAL_READ_REGISTER_RESP); + if (ret != CDN_OK) + return ret; + internal_readmsg(2, 4, &resp->addr, 4, &resp->val); + return CDN_OK; +} + +CDN_API_STATUS +cdn_api_general_read_register_blocking(unsigned int addr, + GENERAL_READ_REGISTER_RESPONSE *resp) +{ + internal_block_function(cdn_api_general_read_register(addr, resp)); +} + +CDN_API_STATUS cdn_api_general_write_register(unsigned int addr, + unsigned int val) +{ + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_WRITE_REGISTER, 2, 4, addr, 4, + val); + state.bus_type = CDN_BUS_TYPE_APB; + return CDN_STARTED; + } + INTERNAL_PROCESS_MESSAGES; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_write_register_blocking(unsigned int addr, + unsigned int val) +{ + internal_block_function(cdn_api_general_write_register(addr, val)); +} + +CDN_API_STATUS cdn_api_general_write_field(unsigned int addr, + unsigned char startbit, + unsigned char bitsno, + unsigned int val) +{ + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_WRITE_FIELD, + 4, 4, addr, 1, startbit, 1, bitsno, 4, + val); + state.bus_type = CDN_BUS_TYPE_APB; + return CDN_STARTED; + } + INTERNAL_PROCESS_MESSAGES; + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_write_field_blocking(unsigned int addr, + unsigned char startbit, + unsigned char bitsno, + unsigned int val) +{ + internal_block_function(cdn_api_general_write_field + (addr, startbit, bitsno, val)); +} + +CDN_API_STATUS cdn_api_general_phy_test_access(uint8_t *resp) +{ + CDN_API_STATUS ret; + + *resp = 0; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, GENERAL_TEST_ACCESS, + 0); + state.bus_type = CDN_BUS_TYPE_APB; + state.rxenable = 1; + + return CDN_STARTED; + } + + INTERNAL_PROCESS_MESSAGES; + + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, GENERAL_TEST_ACCESS); + + if (ret != CDN_OK) + return ret; + + internal_readmsg(1, 1, resp); + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_general_phy_test_access_blocking(uint8_t *resp) +{ + internal_block_function(cdn_api_general_phy_test_access(resp)); +} diff --git a/drivers/video/nxp/hdp/API_General.h b/drivers/video/nxp/hdp/API_General.h new file mode 100644 index 00000000000..0a4caa1ac31 --- /dev/null +++ b/drivers/video/nxp/hdp/API_General.h @@ -0,0 +1,275 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + ****************************************************************************** + * + * API_General.h + * + ****************************************************************************** + */ + +#ifndef API_GENERAL_H_ +#define API_GENERAL_H_ + +#ifndef __UBOOT__ +#include +#else +#include +#endif + +#define GENERAL_TEST_ECHO_MAX_PAYLOAD 100 +#define GENERAL_TEST_ECHO_MIN_PAYLOAD 1 + +/** + * \addtogroup GENERAL_API + * \{ + */ +/** status code returned by API calls */ +typedef enum { + /** operation succedded */ + CDN_OK = 0, + /** CEC operation succedded */ + CDN_CEC_ERR_NONE = 0, + /** mailbox is currently sending or receiving data */ + CDN_BSY, + /** message set up and ready to be sent, no data sent yet */ + CDN_STARTED, + /** error encountered while reading/writing APB */ + CDN_ERR, + /** reply returned with bad opcode */ + CDN_BAD_OPCODE, + /** reply returned with bad module */ + CDN_BAD_MODULE, + /** reply not supported mode */ + CDN_ERROR_NOT_SUPPORTED, + /** Invalid argument passed to CEC API function */ + CDN_CEC_ERR_INVALID_ARG, + /** + * TX Buffer for CEC Messages is full. This is applicable only + * when TX Buffers for CEC Messages are implemented in the HW. + */ + CDN_CEC_ERR_TX_BUFF_FULL, + /** No Messages in the RX Buffers are present. */ + CDN_CEC_ERR_RX_BUFF_EMPTY, + /** Timeout during TX operation */ + CDN_CEC_ERR_TX_TIMEOUT, + /** Timeout during RX operation */ + CDN_CEC_ERR_RX_TIMEOUT, + /** Data transmision fail. */ + CDN_CEC_ERR_TX_FAILED, + /** Data reception fail. */ + CDN_CEC_ERR_RX_FAILED, + /** Operation aborted. */ + CDN_CEC_ERR_ABORT, + /** All Logical Addresses are in use. */ + CDN_CEC_ERR_ALL_LA_IN_USE, +} CDN_API_STATUS; + +typedef enum { + CDN_BUS_TYPE_APB = 0, + CDN_BUS_TYPE_SAPB = 1 +} CDN_BUS_TYPE; + +/** + * GENERAL_Read_Register response struct + */ +typedef struct { + unsigned int addr; + unsigned int val; +} GENERAL_READ_REGISTER_RESPONSE; + +/** + * \brief set up API, must be called before any other API call + */ +void cdn_api_init(void); + +/** + * \brief Loads firmware + * + * \param iMem - pointer to instruction memory + * \param imemSize - size of instruction memory buffer + * \param dMem - pointer to data memory + * \param dmemSize - size of data memory buffer + * \return 0 if success, 1 if apb error encountered, 2 if CPU + * isn't alive after loading firmware + * + * This function does not require initialisation by #CDN_API_Init + */ + +CDN_API_STATUS cdn_api_loadfirmware(unsigned char *imem, + int imemsize, + unsigned char *dmem, int dmemsize); +/** + * \brief debug echo command for APB + * \param val - value to echo + * \return status + * + * will return #CDN_ERROR if reply message doesn't match request + */ +CDN_API_STATUS cdn_api_general_test_echo(unsigned int val, + CDN_BUS_TYPE bus_type); + +/** + * \brief blocking version of #CDN_API_General_Test_Echo + */ +CDN_API_STATUS cdn_api_general_test_echo_blocking(unsigned int val, + CDN_BUS_TYPE bus_type); + +/** + * \brief Extended Echo test for mailbox. + * + * This test will send msg buffer to firmware's mailbox and + * receive it back to the resp buffer. Received data will be + * check against data sent and status will be returned as well + * as received data. + * + * \param msg - Pointer to a buffer to send. + * \param resp - Pointer to buffer for receiving msg payload back. + * \param num_bytes - Number of bytes to send and receive. + * \param bus_type Bus type. + * \return status + * + * will return #CDN_ERROR if reply message doesn't match request or if + * arguments are invalid. + */ +CDN_API_STATUS cdn_api_general_test_echo_ext(u8 const *msg, u8 *resp, + u16 num_bytes, + CDN_BUS_TYPE bus_type); + +/** + * \brief blocking version of #CDN_API_General_Test_Echo_Ext + */ +CDN_API_STATUS cdn_api_general_test_echo_ext_blocking(u8 const *msg, + u8 *resp, + u16 num_bytes, + CDN_BUS_TYPE bus_type); + +/** + * \brief get current version + * \param [out] ver - fw version + * \param [out] libver - lib version + * \return status + * + * this function does not require #CDN_API_Init + */ +CDN_API_STATUS cdn_api_general_getcurversion(unsigned short *ver, + unsigned short *verlib); + +/** + * \brief read event value + * \param [out] event - pointer to store 32-bit events value + * \return status + * + * this function does not require #CDN_API_Init + */ +CDN_API_STATUS cdn_api_get_event(uint32_t *events); + +/** + * \brief read debug register value + * \param [out] val - pointer to store 16-bit debug reg value + * \return status + * + * this function does not require #CDN_API_Init + */ +CDN_API_STATUS cdn_api_get_debug_reg_val(uint16_t *val); + +/** + * \brief check if KEEP_ALIVE register changed + * \return #CDN_BSY if KEEP_ALIVE not changed, #CDN_OK if changed and #CDN_ERR + * if error occurred while reading + */ +CDN_API_STATUS cdn_api_checkalive(void); + +/** + * \breif blocking version of #CDN_API_CheckAlive + * blocks until KEEP_ALIVE register changes or error occurs while reading + */ +CDN_API_STATUS cdn_api_checkalive_blocking(void); + +/** + * \brief set cpu to standby or active + * \param [in] state - 1 for active, 0 for standby + * \return status + */ +CDN_API_STATUS cdn_api_maincontrol(unsigned char mode, unsigned char *resp); + +/** + * \breif blocking version of #CDN_API_MainControl + */ +CDN_API_STATUS cdn_api_maincontrol_blocking(unsigned char mode, + unsigned char *resp); + +/** + * \brief settings for APB + * + * Sends GENERAL_APB_CONF Command via regular Mailbox. + * @param dpcd_bus_sel Set DPCD to use selected bus (0 for APB or 1 for SAPB) + * @param dpcd_bus_lock Lock bus type. Aftern that bus type cannot be changed + * by using this function. + * @param hdcp_bus_sel Same meaning as for DPCD but for HDCP. + * @param hdcp_bus_lock Same meaning as for DPCD but for HDCP. + * @param capb_bus_sel Same meaning as for DPCD but for Cipher APB. + * @param capb_bus_lock Same meaning as for DPCD but for Cipher APB. + * @param dpcd_resp [out] Status of the operation. + * If set to zero then DPCD bus type was successfully changed. + * If not then error occurred, most likely due to locked DPCD bus. + * @param hdcp_resp [out] Same as for DPCD but for HDCP. + * @param capb_resp [out] Same as for DPCD but for Cipher APB. + * + * \return status + */ +CDN_API_STATUS cdn_api_apbconf(u8 dpcd_bus_sel, u8 dpcd_bus_lock, + u8 hdcp_bus_sel, u8 hdcp_bus_lock, + u8 capb_bus_sel, u8 capb_bus_lock, + u8 *dpcd_resp, u8 *hdcp_resp, + u8 *capb_resp); + +/** + * blocking version of #CDN_API_MainControl + */ +CDN_API_STATUS cdn_api_apbconf_blocking(u8 dpcd_bus_sel, + u8 dpcd_bus_lock, + u8 hdcp_bus_sel, + u8 hdcp_bus_lock, + u8 capb_bus_sel, + u8 capb_bus_lock, + u8 *dpcd_resp, + u8 *hdcp_resp, + u8 *capb_resp); + +/** + * \brief set the xtensa clk, write this api before turn on the cpu + */ +CDN_API_STATUS cdn_api_setclock(unsigned char mhz); + +CDN_API_STATUS cdn_api_general_read_register(unsigned int addr, + GENERAL_READ_REGISTER_RESPONSE + *resp); +CDN_API_STATUS +cdn_api_general_read_register_blocking(unsigned int addr, + GENERAL_READ_REGISTER_RESPONSE *resp); +CDN_API_STATUS cdn_api_general_write_register(unsigned int addr, + unsigned int val); +CDN_API_STATUS cdn_api_general_write_register_blocking(unsigned int addr, + unsigned int val); +CDN_API_STATUS cdn_api_general_write_field(unsigned int addr, + unsigned char startbit, + unsigned char bitsno, + unsigned int val); +CDN_API_STATUS cdn_api_general_write_field_blocking(unsigned int addr, + unsigned char startbit, + unsigned char bitsno, + unsigned int val); +CDN_API_STATUS cdn_api_general_phy_test_access(u8 *resp); +CDN_API_STATUS cdn_api_general_phy_test_access_blocking(u8 *resp); +CDN_API_STATUS hdp_rx_loadfirmware(unsigned char *imem, + int imemsize, + unsigned char *dmem, + int dmemsize); +#endif diff --git a/drivers/video/nxp/hdp/API_HDMITX.c b/drivers/video/nxp/hdp/API_HDMITX.c new file mode 100644 index 00000000000..b1b3061028d --- /dev/null +++ b/drivers/video/nxp/hdp/API_HDMITX.c @@ -0,0 +1,486 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_HDMITX.c + * + ****************************************************************************** + */ + +#include "API_HDMITX.h" +#include "util.h" +#include "opcodes.h" +#ifndef __UBOOT__ +#include "string.h" +#include "stdio.h" +#endif +#include "mhl_hdtx_top.h" +#include "source_phy.h" +#include "address.h" +#include "source_car.h" +#include "source_vif.h" +#include "general_handler.h" + +CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out) +{ + internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_READ, + CDN_BUS_TYPE_APB, 3, + 1, data_in->slave, + 1, data_in->offset, + 2, data_in->len + ); + internal_readmsg(5, + 1, &data_out->status, + 1, &data_out->slave, + 1, &data_out->offset, + 2, &data_out->len, + 0, &data_out->buff + ); + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out) +{ + internal_block_function(CDN_API_HDMITX_DDC_READ(data_in, data_out)); +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out) +{ + printf("foo: %x\n", data_in->buff[0]); + internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE, + CDN_BUS_TYPE_APB, 4, + 1, data_in->slave, + 1, data_in->offset, + 2, data_in->len, + -data_in->len, data_in->buff + ); + internal_readmsg(4, + 1, &data_out->status, + 1, &data_out->slave, + 1, &data_out->offset, + 2, &data_out->len + ); + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out) +{ + internal_block_function(CDN_API_HDMITX_DDC_WRITE(data_in, data_out)); +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out) +{ + internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_UPDATE_READ, + CDN_BUS_TYPE_APB, 0); + internal_readmsg(2, + 1, &data_out->status, + 0, &data_out->buff + ); + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA + *data_out) +{ + internal_block_function(CDN_API_HDMITX_DDC_UPDATE_READ(data_out)); +} + +CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block, + unsigned char segment, + HDMITX_TRANS_DATA *data_out) +{ + internal_macro_command_txrx(MB_MODULE_ID_HDMI_TX, HDMI_TX_EDID, + CDN_BUS_TYPE_APB, 2, + 1, block, + 1, segment + ); + internal_readmsg(5, + 1, &data_out->status, + 1, &data_out->slave, + 1, &data_out->offset, + 2, &data_out->len, + 0, &data_out->buff + ); + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block, + unsigned char segment, + HDMITX_TRANS_DATA *data_out) +{ + internal_block_function(CDN_API_HDMITX_READ_EDID(block, segment, + data_out)); +} + +CDN_API_STATUS +CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol, + unsigned int character_rate) +{ + CDN_API_STATUS ret; + GENERAL_READ_REGISTER_RESPONSE resp; + HDMITX_TRANS_DATA data_in; + HDMITX_TRANS_DATA data_out; + unsigned char buff = 1; + + /*enable/disable scrambler; */ + if (protocol == HDMI_TX_MODE_HDMI_2_0) { + if (character_rate > 340000) + buff = 3; /*enable scrambling + TMDS_Bit_Clock_Ratio */ + else + buff = 1; /*enable scrambling */ + } else { + buff = 0; /*disable scrambling */ + } + + data_in.buff = &buff; + data_in.len = 1; + data_in.slave = 0x54; + data_in.offset = 0x20; /*TMDS config */ +#if 1 + if (protocol == HDMI_TX_MODE_HDMI_2_0) + ret = CDN_API_HDMITX_DDC_WRITE_blocking(&data_in, &data_out); + +#endif + ret = cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + &resp); + + /*remove data enable */ + resp.val = resp.val & (~(F_DATA_EN(1))); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + if (protocol == HDMI_TX_MODE_HDMI_2_0) { + if (character_rate > 3400000) { + /* Set TMDS clock ratio */ + ret = cdn_api_general_write_register_blocking + (ADDR_SOURCE_MHL_HD + + (HDTX_CLOCK_REG_0 << 2), + F_DATA_REGISTER_VAL_0(0x00000)); + ret = cdn_api_general_write_register_blocking + (ADDR_SOURCE_MHL_HD + + (HDTX_CLOCK_REG_1 << 2), + F_DATA_REGISTER_VAL_1(0xFFFFF)); + } + } + + /*set hdmi mode and preemble mode */ + resp.val = resp.val & (~(F_HDMI_MODE(3))); + resp.val = resp.val & (~(F_HDMI2_PREAMBLE_EN(1))); + + resp.val = (resp.val) | (F_HDMI_MODE(protocol)) | + (F_HDMI2_PREAMBLE_EN(1)); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + /*data enable */ + resp.val |= F_DATA_EN(1); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + return ret; +} + +CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void) +{ + CDN_API_STATUS ret; + + /*init phy and CAR and HDMI TX */ +/* ret = cdn_api_general_write_register_blocking + (ADDR_SOURCD_PHY + (LANES_CONFIG<<2), + F_SOURCE_PHY_LANE0_SWAP(0) | + F_SOURCE_PHY_LANE1_SWAP(1) | + F_SOURCE_PHY_LANE2_SWAP(2) | + F_SOURCE_PHY_LANE3_SWAP(3) | + F_SOURCE_PHY_COMB_BYPASS(0) | + F_SOURCE_PHY_20_10(1)); */ + + ret = cdn_api_general_write_register_blocking(ADDR_SOURCD_PHY + + (PHY_DATA_SEL << 2), + F_SOURCE_PHY_MHDP_SEL(1)); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_HPD << 2), + F_HPD_VALID_WIDTH(4) | + F_HPD_GLITCH_WIDTH(0)); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + F_HDMI_MODE(1) | + F_AUTO_MODE(0) | + F_GCP_EN(1) | + F_DATA_EN(1) | + F_CLEAR_AVMUTE(1) | + F_HDMI2_PREAMBLE_EN(1) | + F_HDMI2_CTRL_IL_MODE(1) | + F_PIC_3D(0XF) | + F_BCH_EN(1)); + /* open CARS */ + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_PHY_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_HDTX_CAR << 2), + 0xFF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_PKT_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_AIF_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_CIPHER_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_CRYPTO_CAR << 2), + 0xF); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_CAR + + (SOURCE_CEC_CAR << 2), 3); + + /*init vif */ + /*ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF + +(HSYNC2VSYNC_POL_CTRL<<2), F_HPOL(0) | F_VPOL(0)); */ + + return ret; +} + + +CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode, int bpp, + VIC_PXL_ENCODING_FORMAT format) +{ + CDN_API_STATUS ret; + GENERAL_READ_REGISTER_RESPONSE resp; + unsigned int vsync_lines = vic_table[vicMode][VSYNC]; + unsigned int eof_lines = vic_table[vicMode][TYPE_EOF]; + unsigned int sof_lines = vic_table[vicMode][SOF]; + unsigned int hblank = vic_table[vicMode][H_BLANK]; + unsigned int hactive = vic_table[vicMode][H_TOTAL] - hblank; + unsigned int vblank = vsync_lines + eof_lines + sof_lines; + unsigned int vactive = vic_table[vicMode][V_TOTAL] - vblank; + unsigned int hfront = vic_table[vicMode][FRONT_PORCH]; + unsigned int hback = vic_table[vicMode][BACK_PORCH]; + unsigned int vfront = eof_lines; + unsigned int hsync = hblank - hfront - hback; + unsigned int vsync = vsync_lines; + unsigned int vback = sof_lines; + unsigned int v_h_polarity = ((vic_table[vicMode][HSYNC_POL] == + ACTIVE_LOW) ? 0 : 1) + + ((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2); + + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (SCHEDULER_H_SIZE << 2), + (hactive << 16) + hblank); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (SCHEDULER_V_SIZE << 2), + (vactive << 16) + vblank); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_SIGNAL_FRONT_WIDTH + << 2), + (vfront << 16) + hfront); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_SIGNAL_SYNC_WIDTH + << 2), + (vsync << 16) + hsync); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_SIGNAL_BACK_WIDTH + << 2), + (vback << 16) + hback); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_VIF + + (HSYNC2VSYNC_POL_CTRL + << 2), + v_h_polarity); + + /* Data Enable is 1 */ + + /*Reset Data Enable */ + cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), &resp); + + /*reset data enable */ + resp.val = resp.val & (~(F_DATA_EN(1))); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + /*set bpp */ + resp.val = resp.val & (~(F_VIF_DATA_WIDTH(3))); + switch (bpp) { + case 8: + resp.val = resp.val | (F_VIF_DATA_WIDTH(0)); + break; + + case 10: + resp.val = resp.val | (F_VIF_DATA_WIDTH(1)); + break; + + case 12: + resp.val = resp.val | (F_VIF_DATA_WIDTH(2)); + break; + + case 16: + resp.val = resp.val | (F_VIF_DATA_WIDTH(3)); + break; + } + + /*select color encoding */ + resp.val = resp.val & (~(F_HDMI_ENCODING(3))); + switch (format) { + case PXL_RGB: + + resp.val = resp.val | (F_HDMI_ENCODING(0)); + break; + + case YCBCR_4_4_4: + resp.val = resp.val | (F_HDMI_ENCODING(2)); + break; + + case YCBCR_4_2_2: + resp.val = resp.val | (F_HDMI_ENCODING(1)); + break; + + case YCBCR_4_2_0: + resp.val = resp.val | (F_HDMI_ENCODING(3)); + break; + case Y_ONLY: + /*not exist in hdmi */ + break; + } + + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + /*set data enable */ + resp.val = resp.val | (F_DATA_EN(1)); + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + + return ret; +} + +CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force, + unsigned char val) +{ + unsigned int valToWrite = F_COLOR_DEPTH_VAL(val) | + F_COLOR_DEPTH_FORCE(force); + + return cdn_api_general_write_register_blocking + (ADDR_SOURCE_MHL_HD + + (GCP_FORCE_COLOR_DEPTH_CODING << 2), + valToWrite); +} + +CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events) +{ + CDN_API_STATUS ret; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + internal_tx_mkfullmsg(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS, 0); + state.rxenable = 1; + state.bus_type = CDN_BUS_TYPE_APB; + + return CDN_STARTED; + } + + INTERNAL_PROCESS_MESSAGES; + + ret = internal_test_rx_head(MB_MODULE_ID_HDMI_TX, HDMI_TX_EVENTS); + + if (ret != CDN_OK) + return ret; + + internal_readmsg(1, 4, events); + + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events) +{ + internal_block_function(CDN_API_HDMITX_ReadEvents(events)); +} + +CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts) +{ + CDN_API_STATUS ret; + + if (!state.running) { + if (!internal_apb_available()) + return CDN_BSY; + + /* + * General Module is used here for obtaining HPD State because + * HDMI TX Module is inactive in stand-by mode, thus cannot + * return it. + */ + internal_tx_mkfullmsg(MB_MODULE_ID_GENERAL, + GENERAL_GET_HPD_STATE, 0); + state.rxenable = 1; + state.bus_type = CDN_BUS_TYPE_APB; + + return CDN_STARTED; + } + + INTERNAL_PROCESS_MESSAGES; + + ret = internal_test_rx_head(MB_MODULE_ID_GENERAL, + GENERAL_GET_HPD_STATE); + + if (ret != CDN_OK) + return ret; + + internal_readmsg(1, 1, hpd_sts); + + return CDN_OK; +} + +CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts) +{ + internal_block_function(CDN_API_HDMITX_GetHpdStatus(hpd_sts)); +} + diff --git a/drivers/video/nxp/hdp/API_HDMITX.h b/drivers/video/nxp/hdp/API_HDMITX.h new file mode 100644 index 00000000000..099fd118714 --- /dev/null +++ b/drivers/video/nxp/hdp/API_HDMITX.h @@ -0,0 +1,182 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_HDMITX.h + * + ****************************************************************************** + */ + +#ifndef _API_HDMITX_H_ +# define _API_HDMITX_H_ + +# include "API_General.h" +# include "hdmi.h" +# include "vic_table.h" + +/** + * \addtogroup HDMI_TX_API + * \{ + */ + +# define HDMI_TX_EVENT_CODE_HPD_HIGH 0x01 +# define HDMI_TX_EVENT_CODE_HPD_LOW 0x02 +# define HDMI_TX_EVENT_CODE_HPD_STATE_LOW 0x00 +# define HDMI_TX_EVENT_CODE_HPD_STATE_HIGH 0x08 + +typedef struct { + /** if used to return data, this pointer is set (instead of being a + * destination to copy data to + */ + unsigned char *buff; + HDMI_I2C_STATUS status; + unsigned short len; + unsigned char slave; + unsigned char offset; +} HDMITX_TRANS_DATA; + + +typedef enum { + HDMI_TX_MODE_DVI, + HDMI_TX_MODE_HDMI_1_4, + HDMI_TX_MODE_HDMI_2_0, +} HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE; + +/** + * \brief I2C read transaction + * \param [in] data_in - fields used: len, slave, offset + * \param [out] data_out - fields used: all + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_DDC_READ(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out); +CDN_API_STATUS CDN_API_HDMITX_DDC_READ_blocking(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out); + +/** + * \brief I2C write transaction + * \param [in] data_in - fields used: len, slave, offset, buff + * \param [out] data_out - fields used: status, len, slave, offset + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out); +CDN_API_STATUS CDN_API_HDMITX_DDC_WRITE_blocking(HDMITX_TRANS_DATA *data_in, + HDMITX_TRANS_DATA *data_out); + +/** + * \brief I2C update read + * \param [out] data_out - fields used: status, buff + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_DDC_UPDATE_READ(HDMITX_TRANS_DATA *data_out); +CDN_API_STATUS +CDN_API_HDMITX_DDC_UPDATE_READ_blocking(HDMITX_TRANS_DATA *data_out); + +/** + * \brief I2C read edid + * \param [in] block - EDID block + * \pram [in] segment - EDID segment + * \param [out] data_out - fields used: status, buff, slave (as block), + * offset (as segment), len + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_READ_EDID(unsigned char block, + unsigned char segment, + HDMITX_TRANS_DATA *data_out); +CDN_API_STATUS CDN_API_HDMITX_READ_EDID_blocking(unsigned char block, + unsigned char segment, + HDMITX_TRANS_DATA *data_out); + +/** + * \brief set hdmi protocol type (DVI,1.x,2.x) (send scrambler command over + * scdc and set bits in controller) + * \param [in] protocol - type + * \returns status + */ +/*CDN_API_STATUS +CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol, + float character_rate);*/ +CDN_API_STATUS +CDN_API_HDMITX_Set_Mode_blocking(HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE protocol, + unsigned int character_rate); +/** + * \brief init hdmi registers + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_Init_blocking(void); + +/** + * \brief change to vid id vicMode + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_SetVic_blocking(VIC_MODES vicMode, + int bpp, + VIC_PXL_ENCODING_FORMAT format); + +/** + * \brief option to force color depth in the gcp or not force (HW mode) + * \returns status + */ +CDN_API_STATUS CDN_API_HDMITX_ForceColorDepth_blocking(unsigned char force, + unsigned char val); + +/** + * \brief send HDMI_TX_TX_READ_EVENTS command + */ +CDN_API_STATUS CDN_API_HDMITX_ReadEvents(uint32_t *events); + +/** + * blocking version of #CDN_API_HDMITX_ReadEvents + */ +CDN_API_STATUS CDN_API_HDMITX_ReadEvents_blocking(uint32_t *events); + +/** + * \brief get current HPD status + */ +CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus(uint8_t *hpd_sts); + +/** + * \brief blocking version of #CDN_API_HDMITX_GetHpdStatus + */ +CDN_API_STATUS CDN_API_HDMITX_GetHpdStatus_blocking(uint8_t *hpd_sts); + +#endif + diff --git a/drivers/video/nxp/hdp/API_Infoframe.c b/drivers/video/nxp/hdp/API_Infoframe.c new file mode 100644 index 00000000000..acd9612d4a5 --- /dev/null +++ b/drivers/video/nxp/hdp/API_Infoframe.c @@ -0,0 +1,157 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_Infoframe.c + * + ****************************************************************************** + */ + +#include "API_Infoframe.h" +#include "address.h" +#include "source_pif.h" +#include "externs.h" +#ifndef __UBOOT__ +#include +#include +#include +#else +#include +#include +#endif +#include "util.h" + +#define BANK_OFFSET 0x0 + +/* Redefined because of compiler warnings about 32 bit shift left */ +#ifdef F_DATA_WR +#undef F_DATA_WR +#define F_DATA_WR(a_) ((uint32_t)(a_)) +#endif + +static CDN_API_STATUS infoframeSet(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type, + unsigned char active_idle) +{ + unsigned int idx; + unsigned int activeIdleBit = (0 == active_idle) ? 0 : 0x20000; + /*invalidate entry */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_REG << 2), + activeIdleBit | F_PKT_ALLOC_ADDRESS(entry_id))) + return CDN_ERR; + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_WR_EN << 2), + F_PKT_ALLOC_WR_EN(1))) + return CDN_ERR; + + /*flush fifo 1 */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_FIFO1_FLUSH << 2), + F_FIFO1_FLUSH(1))) + return CDN_ERR; + + /*write packet into memory */ + for (idx = 0; idx < packet_len; idx++) + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_DATA_WR << 2), + F_DATA_WR(packet[idx]))) + return CDN_ERR; + + /*write entry id */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_WR_ADDR << 2), + F_WR_ADDR(entry_id))) + return CDN_ERR; + + /*write request */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_WR_REQ << 2), + F_HOST_WR(1))) + return CDN_ERR; + + /*update entry */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_REG << 2), + activeIdleBit | F_TYPE_VALID(1) | + F_PACKET_TYPE(packet_type) | + F_PKT_ALLOC_ADDRESS(entry_id))) + return CDN_ERR; + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_WR_EN << 2), + F_PKT_ALLOC_WR_EN(1))) + return CDN_ERR; + + return CDN_OK; +} + +CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type) +{ + return infoframeSet(entry_id, packet_len, packet, packet_type, 1); +} + +CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type) +{ + return infoframeSet(entry_id, packet_len, packet, packet_type, 0); +} + +CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id) +{ + /*invalidate entry */ + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_REG << 2), + 0x20000 | F_PKT_ALLOC_ADDRESS(entry_id))) + return CDN_ERR; + if (cdn_apb_write(BANK_OFFSET | ADDR_SOURCE_PIF | + (SOURCE_PIF_PKT_ALLOC_WR_EN << 2), + F_PKT_ALLOC_WR_EN(1))) + return CDN_ERR; + + return CDN_OK; +} + diff --git a/drivers/video/nxp/hdp/API_Infoframe.h b/drivers/video/nxp/hdp/API_Infoframe.h new file mode 100644 index 00000000000..a384bb2a600 --- /dev/null +++ b/drivers/video/nxp/hdp/API_Infoframe.h @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * API_Infoframe.h + * + ****************************************************************************** + */ + +#ifndef API_INFOFRAME_H +# define API_INFOFRAME_H + +/** + * \addtogroup INFO_FRAME_API + * \{ + */ + +# include "API_General.h" + +CDN_API_STATUS cdn_api_infoframeset(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type); +CDN_API_STATUS cdn_api_infoframesetnoactiveidle(unsigned char entry_id, + unsigned char packet_len, + unsigned int *packet, + unsigned char packet_type); +CDN_API_STATUS cdn_api_infoframeremove(unsigned char entry_id); + +#endif + diff --git a/drivers/video/nxp/hdp/Makefile b/drivers/video/nxp/hdp/Makefile new file mode 100644 index 00000000000..07d22104750 --- /dev/null +++ b/drivers/video/nxp/hdp/Makefile @@ -0,0 +1,48 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_VIDEO_NXP_HDP) += \ + API_General.o \ + test_base_sw.o \ + API_AVI.o \ + API_Infoframe.o \ + util.o \ + vic_table.o \ + edid_parser.o \ + API_AFE.o \ + API_HDMITX.o \ + API_AFE_t28hpc_hdmitx.o + +# common objects +#obj-y += \ +# API_General.o API_AVI.o API_Infoframe.o \ +# util.o vic_table.o test_base_sw.o \ +# avgen_drv.o edid_parser.o \ +# API_AFE.o + +#DP objects +# API_DPTX.o \ +# API_AFE_mcu2_dp.o\ +# mhdp_firmware.o + +#hdmi objects +#obj-y += \ +# API_HDMITX.o \ +# API_HDCP.o \ +# API_AFE_t28hpc_hdmitx.o +# + +# USE for QM +# blob/API_AFE_mcu1_dp.o +# blob/API_AFE_ss28fdsoi_kiran_hdmitx.o +# blob/ss28fdsoi_hdmitx_table.o +# blob/hdmitx_firmware.o +# blob/mhdp_firmware.o + +# Use for mscale +# API_AFE_mcu2_dp.o () +# API_AFE_t28hpc_hdmitx.c +# diff --git a/drivers/video/nxp/hdp/address.h b/drivers/video/nxp/hdp/address.h new file mode 100644 index 00000000000..1909d3e49f3 --- /dev/null +++ b/drivers/video/nxp/hdp/address.h @@ -0,0 +1,78 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + ****************************************************************************** + * + * address.h + * + ****************************************************************************** + */ + +#ifndef ADDRESS_H_ +# define ADDRESS_H_ + +# define ADDR_IMEM 0x10000 +# define ADDR_DMEM 0x20000 +# define ADDR_CIPHER 0x60000 +# define BASE_CIPHER 0x600 +# define ADDR_APB_CFG 0x00000 +# define BASE_APB_CFG 0x000 +# define ADDR_SOURCE_AIF_DECODER 0x30000 +# define BASE_SOURCE_AIF_DECODER 0x300 +# define ADDR_SOURCE_AIF_SMPL2PCKT 0x30080 +# define BASE_SOURCE_AIF_SMPL2PCKT 0x300 +# define ADDR_AIF_ENCODER 0x30000 +# define BASE_AIF_ENCODER 0x300 +# define ADDR_SOURCE_PIF 0x30800 +# define BASE_SOURCE_PIF 0x308 +# define ADDR_SINK_PIF 0x30800 +# define BASE_SINK_PIF 0x308 +# define ADDR_APB_CFG 0x00000 +# define BASE_APB_CFG 0x000 +# define ADDR_SOURCE_CSC 0x40000 +# define BASE_SOURCE_CSC 0x400 +# define ADDR_UCPU_CFG 0x00000 +# define BASE_UCPU_CFG 0x000 +# define ADDR_SOURCE_CAR 0x00900 +# define BASE_SOURCE_CAR 0x009 +# define ADDR_SINK_CAR 0x00900 +# define BASE_SINK_CAR 0x009 +# define ADDR_CLOCK_METERS 0x00A00 +# define BASE_CLOCK_METERS 0x00A +# define ADDR_SOURCE_VIF 0x00b00 +# define BASE_SOURCE_VIF 0x00b +# define ADDR_SINK_MHL_HD 0x01000 +# define ADDR_SINK_VIDEO_HD 0x01800 +# define BASE_SINK_MHL_HD 0x010 +# define ADDR_SINK_CORE 0x07800 +# define BASE_SINK_CORE 0x078 +# define ADDR_DPTX_PHY 0x02000 +# define BASE_DPTX_PHY 0x020 +# define ADDR_DPTX_HPD 0x02100 +# define BASE_DPTX_HPD 0x021 +# define ADDR_DPTX_FRAMER 0x02200 +# define BASE_DPTX_FRAMER 0x022 +# define ADDR_DPTX_STREAM 0x02200 +# define BASE_DPTX_STREAM 0x022 +# define ADDR_DPTX_GLBL 0x02300 +# define BASE_DPTX_GLBL 0x023 +# define ADDR_DPTX_HDCP 0x02400 +# define BASE_DPTX_HDCP 0x024 +# define ADDR_DP_AUX 0x02800 +# define BASE_DP_AUX 0x028 +# define ADDR_CRYPTO 0x05800 +# define BASE_CRYPTO 0x058 +# define ADDR_CIPHER 0x60000 +# define BASE_CIPHER 0x600 +# define ADDR_SOURCE_MHL_HD 0x01000 + +# define ADDR_AFE (0x20000 * 4) +# define ADDR_SOURCD_PHY (0x800) + +#endif diff --git a/drivers/video/nxp/hdp/apb_cfg.h b/drivers/video/nxp/hdp/apb_cfg.h new file mode 100644 index 00000000000..5e5c007ae18 --- /dev/null +++ b/drivers/video/nxp/hdp/apb_cfg.h @@ -0,0 +1,155 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * apb_cfg.h + * + ****************************************************************************** + */ + +#ifndef APB_CFG_H_ +#define APB_CFG_H_ + +/* register APB_CTRL */ +#define APB_CTRL 0 +#define F_APB_XT_RESET(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_APB_XT_RESET_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_APB_DRAM_PATH(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_APB_DRAM_PATH_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_APB_IRAM_PATH(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_APB_IRAM_PATH_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) + +/* register XT_INT_CTRL */ +#define XT_INT_CTRL 1 +#define F_XT_INT_POLARITY(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_XT_INT_POLARITY_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) + +/* register MAILBOX_FULL_ADDR */ +#define MAILBOX_FULL_ADDR 2 +#define F_MAILBOX_FULL(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_MAILBOX_FULL_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register MAILBOX_EMPTY_ADDR */ +#define MAILBOX_EMPTY_ADDR 3 +#define F_MAILBOX_EMPTY(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_MAILBOX_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register MAILBOX0_WR_DATA */ +#define MAILBOX0_WR_DATA 4 +#define F_MAILBOX0_WR_DATA(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_MAILBOX0_WR_DATA_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register MAILBOX0_RD_DATA */ +#define MAILBOX0_RD_DATA 5 +#define F_MAILBOX0_RD_DATA(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_MAILBOX0_RD_DATA_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register KEEP_ALIVE */ +#define KEEP_ALIVE 6 +#define F_KEEP_ALIVE_CNT(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_KEEP_ALIVE_CNT_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register VER_L */ +#define VER_L 7 +#define F_VER_LSB(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_VER_LSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register VER_H */ +#define VER_H 8 +#define F_VER_MSB(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_VER_MSB_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register VER_LIB_L_ADDR */ +#define VER_LIB_L_ADDR 9 +#define F_SW_LIB_VER_L(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_LIB_VER_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register VER_LIB_H_ADDR */ +#define VER_LIB_H_ADDR 10 +#define F_SW_LIB_VER_H(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_LIB_VER_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_DEBUG_L */ +#define SW_DEBUG_L 11 +#define F_SW_DEBUG_7_0(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_DEBUG_7_0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_DEBUG_H */ +#define SW_DEBUG_H 12 +#define F_SW_DEBUG_15_8(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_DEBUG_15_8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register MAILBOX_INT_MASK */ +#define MAILBOX_INT_MASK 13 +#define F_MAILBOX_INT_MASK(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_MAILBOX_INT_MASK_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) + +/* register MAILBOX_INT_STATUS */ +#define MAILBOX_INT_STATUS 14 +#define F_MAILBOX_INT_STATUS(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_MAILBOX_INT_STATUS_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) + +/* register SW_CLK_L */ +#define SW_CLK_L 15 +#define F_SW_CLOCK_VAL_L(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_CLOCK_VAL_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_CLK_H */ +#define SW_CLK_H 16 +#define F_SW_CLOCK_VAL_H(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_CLOCK_VAL_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_EVENTS0 */ +#define SW_EVENTS0 17 +#define F_SW_EVENTS7_0(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_EVENTS7_0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_EVENTS1 */ +#define SW_EVENTS1 18 +#define F_SW_EVENTS15_8(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_EVENTS15_8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_EVENTS2 */ +#define SW_EVENTS2 19 +#define F_SW_EVENTS23_16(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_EVENTS23_16_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register SW_EVENTS3 */ +#define SW_EVENTS3 20 +#define F_SW_EVENTS31_24(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SW_EVENTS31_24_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register XT_OCD_CTRL */ +#define XT_OCD_CTRL 24 +#define F_XT_DRESET(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_XT_DRESET_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_XT_OCDHALTONRESET(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_XT_OCDHALTONRESET_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) + +/* register XT_OCD_CTRL_RO */ +#define XT_OCD_CTRL_RO 25 +#define F_XT_XOCDMODE(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_XT_XOCDMODE_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register APB_INT_MASK */ +#define APB_INT_MASK 27 +#define F_APB_INTR_MASK(x) (((x) & ((1 << 3) - 1)) << 0) +#define F_APB_INTR_MASK_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) + +/* register APB_STATUS_MASK */ +#define APB_STATUS_MASK 28 +#define F_APB_INTR_STATUS(x) (((x) & ((1 << 3) - 1)) << 0) +#define F_APB_INTR_STATUS_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) + +#endif /*APB_CFG*/ diff --git a/drivers/video/nxp/hdp/avgen.h b/drivers/video/nxp/hdp/avgen.h new file mode 100644 index 00000000000..669a10187f1 --- /dev/null +++ b/drivers/video/nxp/hdp/avgen.h @@ -0,0 +1,253 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * avgen.h + * + ****************************************************************************** + */ + +#ifndef AVGEN_H_ +# define AVGEN_H_ + + +/* register HDMIPOL */ +# define HDMIPOL 0 +# define F_HDMI_V_H_POLARITY(x) (((x) & ((1 << 2) - 1)) << 0) +# define F_HDMI_V_H_POLARITY_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +# define F_HDMI_BITWIDTH(x) (((x) & ((1 << 2) - 1)) << 2) +# define F_HDMI_BITWIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2) + +/* register HDMI_FRONT_PORCHE_L */ +# define HDMI_FRONT_PORCHE_L 1 +# define F_HDMI_FRONT_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_FRONT_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDFP */ +# define HDFP 2 +# define F_HDMI_FRONT_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_FRONT_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDBP */ +# define HDBP 3 +# define F_HDMI_BACK_PORCHE_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_BACK_PORCHE_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_BACK_PORCHE_H */ +# define HDMI_BACK_PORCHE_H 4 +# define F_HDMI_BACK_PORCHE_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_BACK_PORCHE_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDAS */ +# define HDAS 5 +# define F_HDMI_ACTIVE_SLOT_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_ACTIVE_SLOT_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_ACTIVE_SLOT_H */ +# define HDMI_ACTIVE_SLOT_H 6 +# define F_HDMI_ACTIVE_SLOT_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_ACTIVE_SLOT_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDFL */ +# define HDFL 7 +# define F_HDMI_FRAME_LINES_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_FRAME_LINES_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_FRAME_LINES_H */ +# define HDMI_FRAME_LINES_H 8 +# define F_HDMI_FRAME_LINES_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_FRAME_LINES_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDLW */ +# define HDLW 9 +# define F_HDMI_LINE_WIDTH_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_LINE_WIDTH_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_LINE_WIDTH_H */ +# define HDMI_LINE_WIDTH_H 10 +# define F_HDMI_LINE_WIDTH_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDMI_LINE_WIDTH_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDVL */ +# define HDVL 11 +# define F_HDMI_VSYNC_LINES(x) (((x) & ((1 << 7) - 1)) << 0) +# define F_HDMI_VSYNC_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0) + +/* register HDEL */ +# define HDEL 12 +# define F_HDMI_EOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0) +# define F_HDMI_EOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0) + +/* register HDSL */ +# define HDSL 13 +# define F_HDMI_SOF_LINES(x) (((x) & ((1 << 7) - 1)) << 0) +# define F_HDMI_SOF_LINES_RD(x) (((x) & (((1 << 7) - 1) << 0)) >> 0) + +/* register HDCFUPDT */ +# define HDCFUPDT 14 +# define F_HDMI_CODE_FORMAT_UPDT(x) (((x) & ((1 << 6) - 1)) << 0) +# define F_HDMI_CODE_FORMAT_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0) + +/* register HDCF */ +# define HDCF 15 +# define F_HDMI_CODE_FORMAT(x) (((x) & ((1 << 6) - 1)) << 0) +# define F_HDMI_CODE_FORMAT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0) + +/* register HDASPACE */ +# define HDASPACE 16 +# define F_HDASPACE(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_HDASPACE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register HDMI_3D_MODE */ +# define HDMI_3D_MODE 17 +# define F_HDMI_3D_MODE(x) (((x) & ((1 << 3) - 1)) << 0) +# define F_HDMI_3D_MODE_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) + +/* register PTRNGENR */ +# define PTRNGENR 18 +# define F_PTRNGENR_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENR_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNGENR_H */ +# define PTRNGENR_H 19 +# define F_PTRNGENR_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENR_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNGENG */ +# define PTRNGENG 20 +# define F_PTRNGENG_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENG_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNEGENG_H */ +# define PTRNEGENG_H 21 +# define F_PTRNGENG_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENG_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNGENB */ +# define PTRNGENB 22 +# define F_PTRNGENB_L(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENB_L_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRGENB */ +# define PTRGENB 23 +# define F_PTRNGENB_H(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_PTRNGENB_H_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register PTRNGENFF */ +# define PTRNGENFF 30 +# define F_PTRNGENIP(x) (((x) & ((1 << 1) - 1)) << 1) +# define F_PTRNGENIP_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) + +/* register PGENCTRL */ +# define PGENCTRL 32 +# define F_PGENCF(x) (((x) & ((1 << 6) - 1)) << 1) +# define F_PGENCF_RD(x) (((x) & (((1 << 6) - 1) << 1)) >> 1) +# define F_PTRNGENSTRT(x) (((x) & ((1 << 1) - 1)) << 7) +# define F_PTRNGENSTRT_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) + +/* register PGENCTRL_H */ +# define PGENCTRL_H 33 +# define F_PTRNGENRST(x) (((x) & ((1 << 1) - 1)) << 0) +# define F_PTRNGENRST_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +# define F_PIC_SEL(x) (((x) & ((1 << 3) - 1)) << 1) +# define F_PIC_SEL_RD(x) (((x) & (((1 << 3) - 1) << 1)) >> 1) +# define F_PIC_YCBCR_SEL(x) (((x) & ((1 << 2) - 1)) << 4) +# define F_PIC_YCBCR_SEL_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4) + +/* register PGEN_COLOR_BAR_CTRL */ +# define PGEN_COLOR_BAR_CTRL 34 +# define F_PGEN_NUM_BAR(x) (((x) & ((1 << 3) - 1)) << 0) +# define F_PGEN_NUM_BAR_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) + +/* register PGEN_COLOR_BAR_CONTROL_H */ +# define PGEN_COLOR_BAR_CONTROL_H 35 +# define F_PGEN_COLOR_UPDT(x) (((x) & ((1 << 6) - 1)) << 0) +# define F_PGEN_COLOR_UPDT_RD(x) (((x) & (((1 << 6) - 1) << 0)) >> 0) + +/* register GEN_AUDIO_CONTROL */ +# define GEN_AUDIO_CONTROL 36 +# define F_AUDIO_START(x) (((x) & ((1 << 1) - 1)) << 1) +# define F_AUDIO_START_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +# define F_AUDIO_RESET(x) (((x) & ((1 << 1) - 1)) << 2) +# define F_AUDIO_RESET_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) + +/* register SPDIF_CTRL_A */ +# define SPDIF_CTRL_A 37 +# define F_SPDIF_SOURCE_NUM(x) (((x) & ((1 << 4) - 1)) << 0) +# define F_SPDIF_SOURCE_NUM_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +# define F_SPDIF_CH_NUM(x) (((x) & ((1 << 4) - 1)) << 4) +# define F_SPDIF_CH_NUM_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4) + +/* register SPDIF_CTRL_A_H */ +# define SPDIF_CTRL_A_H 38 +# define F_SPDIF_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 0) +# define F_SPDIF_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +# define F_SPDIF_CLK_ACCUR(x) (((x) & ((1 << 2) - 1)) << 4) +# define F_SPDIF_CLK_ACCUR_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4) +# define F_SPDIF_VALID(x) (((x) & ((1 << 1) - 1)) << 6) +# define F_SPDIF_VALID_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) + +/* register SPDIF_CTRL_B */ +# define SPDIF_CTRL_B 39 +# define F_SPDIF_WORD_LENGTH(x) (((x) & ((1 << 4) - 1)) << 0) +# define F_SPDIF_WORD_LENGTH_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +# define F_SPDIF_ORG_SMP_FREQ(x) (((x) & ((1 << 4) - 1)) << 4) +# define F_SPDIF_ORG_SMP_FREQ_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4) + +/* register SPDIF_CTRL_B_H */ +# define SPDIF_CTRL_B_H 40 +# define F_CATEGORY_MODE(x) (((x) & ((1 << 8) - 1)) << 0) +# define F_CATEGORY_MODE_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) + +/* register AUDIO_DIV_EN */ +# define AUDIO_DIV_EN 45 +# define F_AGEN_60958_I2S(x) (((x) & ((1 << 1) - 1)) << 1) +# define F_AGEN_60958_I2S_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +# define F_AGEN_PRL_SUBFRAME(x) (((x) & ((1 << 1) - 1)) << 2) +# define F_AGEN_PRL_SUBFRAME_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +# define F_AGEN_SAMPLES_DATA(x) (((x) & ((1 << 1) - 1)) << 3) +# define F_AGEN_SAMPLES_DATA_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) + +#endif /*AVGEN */ + diff --git a/drivers/video/nxp/hdp/avgen_drv.c b/drivers/video/nxp/hdp/avgen_drv.c new file mode 100644 index 00000000000..89acafe340c --- /dev/null +++ b/drivers/video/nxp/hdp/avgen_drv.c @@ -0,0 +1,306 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * avgen_drv.c + * + ****************************************************************************** + */ + +#include "mhl_hdtx_top.h" +#include "address.h" +#include "avgen.h" +#include "avgen_drv.h" +#include "util.h" +#include "externs.h" + +#define ADDR_AVGEN 0x80000 + +CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol, + VIC_PXL_ENCODING_FORMAT format) +{ + /*CDN_API_STATUS ret; */ + /*GENERAL_Read_Register_response resp; */ + unsigned int pixelClockFreq = CDN_API_Get_PIXEL_FREQ_KHZ_ClosetVal + (vic_table[vicMode][PIXEL_FREQ_KHZ], protocol); + unsigned int v_h_polarity = + ((vic_table[vicMode][HSYNC_POL] == ACTIVE_LOW) ? 0 : 1) + + ((vic_table[vicMode][VSYNC_POL] == ACTIVE_LOW) ? 0 : 2); + unsigned int front_porche_l = vic_table[vicMode][FRONT_PORCH] - 256 * + ((unsigned int)vic_table[vicMode][FRONT_PORCH] / 256); + unsigned int front_porche_h = vic_table[vicMode][FRONT_PORCH] / 256; + unsigned int back_porche_l = vic_table[vicMode][BACK_PORCH] - 256 * + ((unsigned int)vic_table[vicMode][BACK_PORCH] / 256); + unsigned int back_porche_h = vic_table[vicMode][BACK_PORCH] / 256; + unsigned int active_slot_l = vic_table[vicMode][H_BLANK] - 256 * + ((unsigned int)vic_table[vicMode][H_BLANK] / 256); + unsigned int active_slot_h = vic_table[vicMode][H_BLANK] / 256; + unsigned int frame_lines_l = vic_table[vicMode][V_TOTAL] - 256 * + ((unsigned int)vic_table[vicMode][V_TOTAL] / 256); + unsigned int frame_lines_h = vic_table[vicMode][V_TOTAL] / 256; + unsigned int line_width_l = vic_table[vicMode][H_TOTAL] - 256 * + ((unsigned int)vic_table[vicMode][H_TOTAL] / 256); + unsigned int line_width_h = vic_table[vicMode][H_TOTAL] / 256; + unsigned int vsync_lines = vic_table[vicMode][VSYNC]; + unsigned int eof_lines = vic_table[vicMode][TYPE_EOF]; + unsigned int sof_lines = vic_table[vicMode][SOF]; + unsigned int interlace_progressive = + (vic_table[vicMode][I_P] == INTERLACED) ? 2 : 0; + unsigned int set_vif_clock = 0; + + /*needed for HDMI /////////////////////////////// */ + /*unsigned int hblank = vic_table[vicMode][H_BLANK]; */ + /*unsigned int hactive = vic_table[vicMode][H_TOTAL]-hblank; */ + /*unsigned int vblank = vsync_lines+eof_lines+sof_lines; */ + /*unsigned int vactive = vic_table[vicMode][V_TOTAL]-vblank; */ + /*unsigned int hfront = vic_table[vicMode][FRONT_PORCH]; */ + /*unsigned int hback = vic_table[vicMode][BACK_PORCH]; */ + /*unsigned int vfront = eof_lines; */ + /*unsigned int hsync = hblank-hfront-hback; */ + /*unsigned int vsync = vsync_lines; */ + /*unsigned int vback = sof_lines; */ + unsigned int set_CLK_SEL = 0; + unsigned int set_REF_CLK_SEL = 0; + unsigned int set_pll_CLK_IN = 0; + unsigned int set_pll_clkfbout_l = 0; + unsigned int set_pll_clkfbout_h = 0; + unsigned int set_pll_CLKOUT5_L = 0; + unsigned int set_pll_CLKOUT5_H = 0; + unsigned int set_pll2_CLKIN = 0; + unsigned int set_pll2_CLKFBOUT_L = 0; + unsigned int set_pll2_CLKFBOUT_H = 0; + unsigned int set_pll2_CLKOUT5_L = 0; + unsigned int set_pll2_CLKOUT5_H = 0; + /*///////////////////////////////////////////////// */ + + cdn_apb_write(0x1c00C6 << 2, + (int)(vic_table[vicMode][PIXEL_FREQ_KHZ] * 1000)); + cdn_apb_write(0x1c00C6 << 2, (int)(pixelClockFreq)); + + if ((int)(pixelClockFreq) == 25) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 4; + set_REF_CLK_SEL = 0; + set_pll_CLK_IN = 65; + set_pll_clkfbout_l = 4292; + set_pll_clkfbout_h = 128; + set_pll_CLKOUT5_L = 4422; + set_pll_CLKOUT5_H = 128; + set_pll2_CLKIN = 12289; + set_pll2_CLKFBOUT_L = 4356; + set_pll2_CLKFBOUT_H = 0; + set_pll2_CLKOUT5_L = 4552; + set_pll2_CLKOUT5_H = 128; + } else { + set_vif_clock = 0x300; + } + } else if ((int)pixelClockFreq == 27000) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 5; + set_REF_CLK_SEL = 0; + set_pll_CLK_IN = 49217; + set_pll_clkfbout_l = 4226; + set_pll_clkfbout_h = 0; + set_pll_CLKOUT5_L = 4422; + set_pll_CLKOUT5_H = 128; + } else { + set_vif_clock = 0x301; + } + } else if ((int)pixelClockFreq == 54000) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 5; + set_REF_CLK_SEL = 0; + set_pll_CLK_IN = 4096; + set_pll_clkfbout_l = 4226; + set_pll_clkfbout_h = 0; + set_pll_CLKOUT5_L = 4422; + set_pll_CLKOUT5_H = 128; + } else { + set_vif_clock = 0x302; + } + } else if (pixelClockFreq == 74250) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 1; + set_pll_CLK_IN = 74; + } else { + set_vif_clock = 0x303; + } + } else if (pixelClockFreq == 148500) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 0; + set_pll_CLK_IN = 148; + } else { + set_vif_clock = 0x304; + } + } else if ((int)pixelClockFreq == 108000) { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 5; + set_REF_CLK_SEL = 2; + set_pll_CLK_IN = 8258; + set_pll_clkfbout_l = 4616; + set_pll_clkfbout_h = 0; + set_pll_CLKOUT5_L = 4422; + set_pll_CLKOUT5_H = 128; + } else { + set_vif_clock = 0x305; + } + } else { + if (protocol == CDN_HDMITX_TYPHOON) { + set_CLK_SEL = 1; + set_pll_CLK_IN = pixelClockFreq; + } else { + set_vif_clock = 0; + } + } + unsigned int start_pgen = 128; + /*unsigned int temp; */ + if (protocol == CDN_HDMITX_TYPHOON) { + if (cdn_apb_write(0x0c0001 << 2, + ((0) + (2 * set_CLK_SEL) + (16 * 0) + + (32 * 0) + (64 * 3) + (65536 * 3) + + (1048576 * set_REF_CLK_SEL)))) + return CDN_ERR; + if (cdn_apb_write(0x1c00C6 << 2, set_pll_CLK_IN)) + return CDN_ERR; + if (cdn_apb_write(0x1c00CC << 2, set_pll_clkfbout_l)) + return CDN_ERR; + if (cdn_apb_write(0x1c00CD << 2, set_pll_clkfbout_h)) + return CDN_ERR; + if (cdn_apb_write(0x1c00CE << 2, set_pll_CLKOUT5_L)) + return CDN_ERR; + if (cdn_apb_write(0x1c00CF << 2, set_pll_CLKOUT5_H)) + return CDN_ERR; + if (cdn_apb_write(0x1c0086 << 2, set_pll2_CLKIN)) + return CDN_ERR; + if (cdn_apb_write(0x1c008C << 2, set_pll2_CLKFBOUT_L)) + return CDN_ERR; + if (cdn_apb_write(0x1c008D << 2, set_pll2_CLKFBOUT_H)) + return CDN_ERR; + if (cdn_apb_write(0x1c008E << 2, set_pll2_CLKOUT5_L)) + return CDN_ERR; + if (cdn_apb_write(0x1c008F << 2, set_pll2_CLKOUT5_H)) + return CDN_ERR; + if (cdn_apb_write(0x0c0001 << 2, + ((1) + (2 * set_CLK_SEL) + (16 * 0) + + (32 * 0) + (64 * 3) + (65536 * 3) + + (1048576 * set_REF_CLK_SEL)))) + return CDN_ERR; + } + + if (cdn_apb_write((ADDR_AVGEN + HDMIPOL) << 2, v_h_polarity)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_FRONT_PORCHE_L) << 2, + front_porche_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDFP) << 2, front_porche_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDBP) << 2, back_porche_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_BACK_PORCHE_H) << 2, + back_porche_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDAS) << 2, active_slot_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_ACTIVE_SLOT_H) << 2, + active_slot_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDFL) << 2, frame_lines_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_FRAME_LINES_H) << 2, + frame_lines_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDLW) << 2, line_width_l)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDMI_LINE_WIDTH_H) << 2, line_width_h)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDVL) << 2, vsync_lines)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDEL) << 2, eof_lines)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + HDSL) << 2, sof_lines)) + return CDN_ERR; + if (cdn_apb_write((ADDR_AVGEN + PTRNGENFF) << 2, interlace_progressive)) + return CDN_ERR; + + if (protocol == CDN_HDMITX_TYPHOON) { + switch (format) { + case PXL_RGB: + + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2, + F_PIC_SEL(1) | F_PIC_YCBCR_SEL(0))) + return CDN_ERR; + break; + + case YCBCR_4_4_4: + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2, + F_PIC_SEL(2) | F_PIC_YCBCR_SEL(0))) + return CDN_ERR; + + break; + + case YCBCR_4_2_2: + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2, + F_PIC_SEL(2) | F_PIC_YCBCR_SEL(1))) + return CDN_ERR; + + break; + + case YCBCR_4_2_0: + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL_H) << 2, + F_PIC_SEL(2) | F_PIC_YCBCR_SEL(2))) + return CDN_ERR; + + break; + case Y_ONLY: + /*not exist in hdmi */ + break; + } + } else { + if (set_vif_clock != 0) + if (cdn_apb_write(0xC0006 << 2, set_vif_clock)) + return CDN_ERR; + } + + if (cdn_apb_write((ADDR_AVGEN + PGENCTRL) << 2, start_pgen)) + return CDN_ERR; + + return CDN_OK; +} + diff --git a/drivers/video/nxp/hdp/avgen_drv.h b/drivers/video/nxp/hdp/avgen_drv.h new file mode 100644 index 00000000000..1f8c76b4682 --- /dev/null +++ b/drivers/video/nxp/hdp/avgen_drv.h @@ -0,0 +1,69 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * avgen_drv.h + * + ****************************************************************************** + */ + +#ifndef AVGEN_DRV_H_ +# define AVGEN_DRV_H_ + +#ifndef __UBOOT__ +# include +#else +#include +#endif + +# include "vic_table.h" +# include "API_General.h" +# include "defs.h" + +/** + * \brief set avgen according to mode and vic table, user that doesnt have + * cadence AVGEN, need to implement this function on user + * platform + */ +CDN_API_STATUS CDN_API_AVGEN_Set(VIC_MODES vicMode, CDN_PROTOCOL_TYPE protocol, + VIC_PXL_ENCODING_FORMAT format); + +#endif + diff --git a/drivers/video/nxp/hdp/defs.h b/drivers/video/nxp/hdp/defs.h new file mode 100644 index 00000000000..4a6361e4fa2 --- /dev/null +++ b/drivers/video/nxp/hdp/defs.h @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * Copyright (C) 2015-2016 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * defs.h + * + ****************************************************************************** + */ + +#ifndef _DEFS_H_ +#define _DEFS_H_ + +typedef enum { + CDN_DPTX , + CDN_HDMITX_TYPHOON, + CDN_HDMITX_KIRAN, +} CDN_PROTOCOL_TYPE; + +#endif /*_DEFS_H_ */ + diff --git a/drivers/video/nxp/hdp/edid_parser.c b/drivers/video/nxp/hdp/edid_parser.c new file mode 100644 index 00000000000..9cb361105ae --- /dev/null +++ b/drivers/video/nxp/hdp/edid_parser.c @@ -0,0 +1,617 @@ +/****************************************************************************** + * + * Copyright (C) 2015-2016 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * edid_parser.c + * + ****************************************************************************** + */ + +#include "edid_parser.h" + +static EDID_PARSER_RESULT edid_parse_dtd(S_DTD_DATA *descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_DTD; + descriptor->header.tag = 0; + + descriptor->pixel_clock = raw_data[raw_data_index]; + descriptor->pixel_clock += + (unsigned short)raw_data[raw_data_index + 1] << 8; + + descriptor->horizontal_addressable_video = raw_data[raw_data_index + 2]; + descriptor->horizontal_addressable_video += + ((unsigned short)raw_data[raw_data_index + 4] & 0xF0) << 4; + descriptor->horizontal_blanking = raw_data[raw_data_index + 3]; + descriptor->horizontal_blanking += + ((unsigned short)raw_data[raw_data_index + 4] & 0x0F) << 8; + + descriptor->vertical_addressable_video = raw_data[raw_data_index + 5]; + descriptor->vertical_addressable_video += + ((unsigned short)raw_data[raw_data_index + 7] & 0xF0) << 4; + descriptor->vertical_blanking = raw_data[raw_data_index + 6]; + descriptor->vertical_blanking += + ((unsigned short)raw_data[raw_data_index + 7] & 0x0F) << 8; + + descriptor->horizontal_front_porch = raw_data[raw_data_index + 8]; + descriptor->horizontal_front_porch += + ((unsigned short)raw_data[raw_data_index + 11] & 0xC0) << 2; + descriptor->horizontal_sync_pulse_width = raw_data[raw_data_index + 9]; + descriptor->horizontal_sync_pulse_width += + ((unsigned short)raw_data[raw_data_index + 11] & 0x30) << 4; + + descriptor->vertical_front_porch = + (raw_data[raw_data_index + 10] & 0xF0) >> 4; + descriptor->vertical_front_porch += + (raw_data[raw_data_index + 11] & 0x0C) << 2; + descriptor->vertical_sync_pulse_width = + raw_data[raw_data_index + 10] & 0x0F; + descriptor->vertical_sync_pulse_width += + (raw_data[raw_data_index + 11] & 0x03) << 4; + + descriptor->horizontal_addressable_video_image_size = + raw_data[raw_data_index + 12]; + descriptor->horizontal_addressable_video_image_size += + ((unsigned short)raw_data[raw_data_index + 14] & 0xF0) << 4; + descriptor->vertical_addressable_video_image_size = + raw_data[raw_data_index + 13]; + descriptor->vertical_addressable_video_image_size += + ((unsigned short)raw_data[raw_data_index + 14] & 0x0F) << 8; + + descriptor->horizontal_border = raw_data[raw_data_index + 15]; + descriptor->vertical_border = raw_data[raw_data_index + 16]; + + descriptor->signal_features = raw_data[raw_data_index + 17]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_serial_number(S_SERIAL_NUMBER_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + descriptor->header.type = DESCRIPTOR_TYPE_SERIAL_NUMBER; + descriptor->header.tag = 0xFF; + + int idx; + for (idx = 0; idx < 13; idx++) + descriptor->serial_number[idx] = + raw_data[raw_data_index + 5 + idx]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_data_string(S_DATA_STRING_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + descriptor->header.type = DESCRIPTOR_TYPE_DATA_STRING; + descriptor->header.tag = 0xFE; + int idx; + for (idx = 0; idx < 13; idx++) + descriptor->data_string[idx] = + raw_data[raw_data_index + 5 + idx]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_range_limits(S_RANGE_LIMITS_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_RANGE_LIMITS; + descriptor->header.tag = 0xFD; + + descriptor->offset_flags = raw_data[raw_data_index + 4]; + descriptor->min_vertical_rate = raw_data[raw_data_index + 5]; + descriptor->max_vertical_rate = raw_data[raw_data_index + 6]; + descriptor->min_horizontal_rate = raw_data[raw_data_index + 7]; + descriptor->max_horizontal_rate = raw_data[raw_data_index + 8]; + descriptor->max_pixel_clock = raw_data[raw_data_index + 9]; + + switch (raw_data[raw_data_index + 10]) { + case 0x00: + descriptor->type = VIDEO_TIMING_DEFAULT_GTF; + break; + case 0x01: + descriptor->type = VIDEO_TIMING_RANGE_LIMITS_ONLY; + break; + case 0x02: + descriptor->type = VIDEO_TIMING_SECONDARY_GTF; + S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *timing_type_gtf = + (S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF *) + descriptor->suport_flags; + timing_type_gtf->start_break_frequency = + raw_data[raw_data_index + 12]; + timing_type_gtf->c = raw_data[raw_data_index + 13]; + timing_type_gtf->m = raw_data[raw_data_index + 14]; + timing_type_gtf->m += + (unsigned short)raw_data[raw_data_index + 15] << 8; + timing_type_gtf->k = raw_data[raw_data_index + 16]; + timing_type_gtf->j = raw_data[raw_data_index + 17]; + break; + case 0x04: + descriptor->type = VIDEO_TIMING_CVT; + S_RANGE_LIMITS_VIDEO_TIMING_CVT *timing_type_cvt = + (S_RANGE_LIMITS_VIDEO_TIMING_CVT *)descriptor-> + suport_flags; + timing_type_cvt->cvt_version = raw_data[raw_data_index + 11]; + timing_type_cvt->additional_pixel_clock_precision = + raw_data[raw_data_index + 12] >> 2; + timing_type_cvt->max_active_pixels = + raw_data[raw_data_index + 13]; + timing_type_cvt->max_active_pixels += + (unsigned short)(raw_data[raw_data_index + 12] & 0x03) + << 8; + timing_type_cvt->supported_ar = + raw_data[raw_data_index + 14] >> 3; + timing_type_cvt->preferred_ar = + raw_data[raw_data_index + 15] >> 5; + timing_type_cvt->blanking_support = + (raw_data[raw_data_index + 15] & 0x18) >> 3; + timing_type_cvt->supported_scalling = + raw_data[raw_data_index + 16] >> 4; + timing_type_cvt->preferred_vertical_refresh_rate = + raw_data[raw_data_index + 17]; + break; + } + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_product_name(S_PRODUCT_NAME_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_PRODUCT_NAME; + descriptor->header.tag = 0xFC; + int idx; + for (idx = 0; idx < 13; idx++) + descriptor->product_name[idx] = + raw_data[raw_data_index + 5 + idx]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_color_point(S_COLOR_POINT_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_COLOR_POINT; + descriptor->header.tag = 0xFB; + descriptor->white_point_index_1 = raw_data[raw_data_index + 5]; + descriptor->white_x_1 = (raw_data[raw_data_index + 6] & 0x0C) >> 2; + descriptor->white_x_1 += + (unsigned short)raw_data[raw_data_index + 7] << 2; + descriptor->white_y_1 = raw_data[raw_data_index + 6] & 0x03; + descriptor->white_y_1 += + (unsigned short)raw_data[raw_data_index + 8] << 2; + descriptor->gamma_1 = raw_data[raw_data_index + 9]; + + descriptor->white_point_index_2 = raw_data[raw_data_index + 10]; + descriptor->white_x_2 = (raw_data[raw_data_index + 11] & 0x0C) >> 2; + descriptor->white_x_2 += + (unsigned short)raw_data[raw_data_index + 12] << 2; + descriptor->white_y_2 = raw_data[raw_data_index + 11] & 0x03; + descriptor->white_y_2 += + (unsigned short)raw_data[raw_data_index + 13] << 2; + descriptor->gamma_2 = raw_data[raw_data_index + 14]; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_standard_timing(S_STANDARD_TIMING_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_STANDARD_TIMING; + descriptor->header.tag = 0xFA; + int idx; + for (idx = 0; idx < 6; idx++) { + descriptor->standard_timings[idx] = + raw_data[raw_data_index + 5 + 2 * idx]; + descriptor->standard_timings[idx] += + (unsigned short)raw_data[raw_data_index + 5 + 2 * idx + + 1]; + } + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_color_management(S_COLOR_MANAGEMENT_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_COLOR_MANAGEMENT; + descriptor->header.tag = 0xF9; + + descriptor->version = raw_data[raw_data_index + 5]; + + descriptor->red_a3 = raw_data[raw_data_index + 6]; + descriptor->red_a3 += (unsigned short)raw_data[raw_data_index + 7] << 8; + descriptor->red_a2 = raw_data[raw_data_index + 8]; + descriptor->red_a2 += (unsigned short)raw_data[raw_data_index + 9] << 8; + + descriptor->green_a3 = raw_data[raw_data_index + 10]; + descriptor->green_a3 += + (unsigned short)raw_data[raw_data_index + 11] << 8; + descriptor->green_a2 = raw_data[raw_data_index + 12]; + descriptor->green_a2 += + (unsigned short)raw_data[raw_data_index + 13] << 8; + + descriptor->blue_a3 = raw_data[raw_data_index + 14]; + descriptor->blue_a3 += + (unsigned short)raw_data[raw_data_index + 15] << 8; + descriptor->blue_a2 = raw_data[raw_data_index + 16]; + descriptor->blue_a2 += + (unsigned short)raw_data[raw_data_index + 17] << 8; + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_cvt_timing_codes(S_CVT_TIMING_CODES_DATA * + descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_CVT_TIMING_CODES; + descriptor->header.tag = 0xF8; + descriptor->version = raw_data[raw_data_index + 5]; + + int idx; + for (idx = 0; idx < 4; idx++) { + descriptor->addressable_lines[idx] = + raw_data[raw_data_index + 6 + idx * 3]; + descriptor->addressable_lines[idx] += + (unsigned short)(raw_data[raw_data_index + 7 + idx * 3] + & 0xF0) << 4; + descriptor->aspect_ratio[idx] = + (raw_data[raw_data_index + 7 + idx * 3] & 0x0C) >> 2; + descriptor->preferred_vertical_rate[idx] = + (raw_data[raw_data_index + 8 + idx * 3] & 0x60) >> 5; + descriptor->supported_vertical_rate_and_blanking[idx] = + raw_data[raw_data_index + 8 + idx * 3] & 0x1F; + } + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT +edid_parse_established_timings_3(S_ESTABLISHED_TIMINGS_3_DATA *descriptor, + unsigned char *raw_data) +{ + unsigned int raw_data_index = 0; + + descriptor->header.type = DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3; + descriptor->header.tag = 0xF7; + descriptor->version = raw_data[raw_data_index + 5]; + int idx; + for (idx = 0; idx < 6; idx++) { + descriptor->established_timings[idx] = + raw_data[raw_data_index + 6 + idx]; + } + + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT edid_parse_dummy(S_DUMMY_DATA *descriptor, + unsigned char *raw_data) +{ + descriptor->header.type = DESCRIPTOR_TYPE_DUMMY; + descriptor->header.tag = 0x10; + return EDID_PARSER_SUCCESS; +} + +static EDID_PARSER_RESULT +edid_parse_manufacturer_specific(S_MANUFACTURER_SPECIFIC_DATA *descriptor, + unsigned char *raw_data, unsigned char tag) +{ + descriptor->header.type = DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC; + descriptor->header.tag = tag; + + return EDID_PARSER_SUCCESS; +} + +EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data, + unsigned int len) +{ + unsigned int raw_data_index = 0; + unsigned char sum = 0; + /*CHECK SUM OF BYTES IN BLOCK0 */ + for (raw_data_index = 0; raw_data_index < EDID_LENGTH; raw_data_index++) + sum += raw_data[raw_data_index]; + + if (sum != 0) + return EDID_PARSER_ERROR; + + /*READ HEADER */ + for (raw_data_index = 0; raw_data_index < EDID_HEADER_LENGTH; + raw_data_index++) + edid->header[raw_data_index] = raw_data[raw_data_index]; + + /*READ VENDOR & PRODUCT IDENTIFICATION */ + /*manufacturer name */ + edid->manufacturer_name[0] = ((raw_data[8] & 0x7C) >> 2) + 0x40; + edid->manufacturer_name[1] = + ((raw_data[8] & 0x03) << 3) + ((raw_data[9] & 0xE0) >> 5) + + 0x40; + edid->manufacturer_name[2] = ((raw_data[9] & 0x1F)) + 0x40; + edid->manufacturer_name[3] = 0; + + /*product code */ + edid->product_code = (raw_data[10]); + edid->product_code += ((unsigned short)raw_data[11]) << 8; + + /*serial number */ + edid->serial_number = raw_data[12]; + edid->serial_number += (unsigned int)raw_data[13] << 8; + edid->serial_number += (unsigned int)raw_data[14] << 16; + edid->serial_number += (unsigned int)raw_data[15] << 24; + + /*week of manufacture */ + edid->week = raw_data[16]; + + /*year of manufacture */ + edid->year = raw_data[17]; + + /*EDID STRUCTURE VERSION & REVISION */ + edid->edid_version = ((unsigned short)raw_data[18] << 8) + raw_data[19]; + + /*BASIC DISPLAY PARAMETERS AND FEATURES */ + /*video input definition */ + edid->video_input_definition = raw_data[20]; + + /*horizontal screen size */ + edid->horizontal_size = raw_data[21]; + + /*vertical screen size */ + edid->vertical_size = raw_data[22]; + + /*display transfer characteristic */ + edid->gamma = raw_data[23]; + + /*feature support */ + edid->feature_support = raw_data[24]; + + /*COLOR CHARACTERISTIC */ + /*red */ + edid->chromacity_coorditates_red_x = (raw_data[25] & 0xC0) >> 6; + edid->chromacity_coorditates_red_x += (unsigned short)raw_data[27] << 2; + edid->chromacity_coorditates_red_y = (raw_data[25] & 0x30) >> 4; + edid->chromacity_coorditates_red_y += (unsigned short)raw_data[28] << 2; + + /*green */ + edid->chromacity_coorditates_green_x = (raw_data[25] & 0x0C) >> 2; + edid->chromacity_coorditates_green_x += + (unsigned short)raw_data[29] << 2; + edid->chromacity_coorditates_green_y = (raw_data[25] & 0x03); + edid->chromacity_coorditates_green_y += + (unsigned short)raw_data[30] << 2; + + /*blue */ + edid->chromacity_coorditates_blue_x = (raw_data[26] & 0xC0) >> 6; + edid->chromacity_coorditates_blue_x += + (unsigned short)raw_data[31] << 2; + edid->chromacity_coorditates_blue_y = (raw_data[26] & 0x30) >> 4; + edid->chromacity_coorditates_blue_y += + (unsigned short)raw_data[32] << 2; + + /*blue */ + edid->chromacity_coorditates_white_x = (raw_data[26] & 0x0C) >> 2; + edid->chromacity_coorditates_white_x += + (unsigned short)raw_data[33] << 2; + edid->chromacity_coorditates_white_y = (raw_data[26] & 0x03); + edid->chromacity_coorditates_white_y += + (unsigned short)raw_data[34] << 2; + + /*ESTABLISHED TIMINGS */ + edid->established_timing_1 = raw_data[35]; + edid->established_timing_2 = raw_data[36]; + edid->manufacturer_timing = raw_data[37]; + + /*STANDARD TIMINGS */ + for (raw_data_index = 0; raw_data_index < 8; raw_data_index++) { + edid->standard_timings[raw_data_index] = + raw_data[38 + (2 * raw_data_index)]; + edid->standard_timings[raw_data_index] += + (unsigned short)raw_data[38 + (2 * raw_data_index + 1)]; + } + /*extensions */ + edid->extensions = raw_data[126]; + + /*DESCRIPTORS */ + unsigned int descriptor_index; + raw_data_index = 54; + for (descriptor_index = 0; descriptor_index < 4; descriptor_index++) { + if (raw_data[raw_data_index] == 0 && + raw_data[raw_data_index + 1] == 0) { + /*display descriptor found */ + unsigned char tag = raw_data[raw_data_index + 3]; + if (tag == 0xFF) { + /*display product serial number */ + S_SERIAL_NUMBER_DATA *descriptor = + (S_SERIAL_NUMBER_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_serial_number + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFE) { + /*alphanumeric data string */ + S_DATA_STRING_DATA *descriptor = + (S_DATA_STRING_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_data_string + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFD) { + /*display range limits */ + S_RANGE_LIMITS_DATA *descriptor = + (S_RANGE_LIMITS_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_range_limits + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFC) { + /*display product name */ + S_PRODUCT_NAME_DATA *descriptor = + (S_PRODUCT_NAME_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_product_name + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFB) { + /*color point data */ + S_COLOR_POINT_DATA *descriptor = + (S_COLOR_POINT_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_color_point + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xFA) { + /*standard timing identifications */ + S_STANDARD_TIMING_DATA *descriptor = + (S_STANDARD_TIMING_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_standard_timing + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xF9) { + /*display color management (DCM) */ + S_COLOR_MANAGEMENT_DATA *descriptor = + (S_COLOR_MANAGEMENT_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_color_management + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xF8) { + /*CVT 3 byte timing codes */ + S_CVT_TIMING_CODES_DATA *descriptor = + (S_CVT_TIMING_CODES_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_cvt_timing_codes + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0xF7) { + /*established timings III */ + S_ESTABLISHED_TIMINGS_3_DATA *descriptor = + (S_ESTABLISHED_TIMINGS_3_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_established_timings_3 + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag == 0x10) { + /*dummy */ + S_DUMMY_DATA *descriptor = + (S_DUMMY_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_dummy + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + + } else if (tag <= 0x0F) { + /*manufacturer specific data */ + S_MANUFACTURER_SPECIFIC_DATA *descriptor = + (S_MANUFACTURER_SPECIFIC_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_manufacturer_specific + (descriptor, raw_data + raw_data_index, + tag) != EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + } + } else { + /*detailed timing definition */ + S_DTD_DATA *descriptor = + (S_DTD_DATA *)edid-> + descriptors[descriptor_index]; + if (edid_parse_dtd + (descriptor, + raw_data + raw_data_index) != + EDID_PARSER_SUCCESS) + return EDID_PARSER_ERROR; + } + raw_data_index += 18; + } + + return EDID_PARSER_SUCCESS; +} diff --git a/drivers/video/nxp/hdp/edid_parser.h b/drivers/video/nxp/hdp/edid_parser.h new file mode 100644 index 00000000000..13eb0b1882b --- /dev/null +++ b/drivers/video/nxp/hdp/edid_parser.h @@ -0,0 +1,297 @@ +/****************************************************************************** + * + * Copyright (C) 2015-2016 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * edid_parser.h + * + ****************************************************************************** + */ + +#ifndef EDID_PARSER_H +#define EDID_PARSER_H + +#define MAX_DESCRIPTOR_LENGTH 36 +#define MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH 12 +#define EDID_HEADER_LENGTH 8 +#define EDID_LENGTH 128 + +typedef enum { + EDID_PARSER_SUCCESS, + EDID_PARSER_ERROR, +} EDID_PARSER_RESULT; + +typedef enum { + DESCRIPTOR_TYPE_DTD, + DESCRIPTOR_TYPE_SERIAL_NUMBER, + DESCRIPTOR_TYPE_DATA_STRING, + DESCRIPTOR_TYPE_RANGE_LIMITS, + DESCRIPTOR_TYPE_PRODUCT_NAME, + DESCRIPTOR_TYPE_COLOR_POINT, + DESCRIPTOR_TYPE_STANDARD_TIMING, + DESCRIPTOR_TYPE_COLOR_MANAGEMENT, + DESCRIPTOR_TYPE_CVT_TIMING_CODES, + DESCRIPTOR_TYPE_ESTABLISHED_TIMINGS_3, + DESCRIPTOR_TYPE_DUMMY, + DESCRIPTOR_TYPE_MANUFACTURER_SPECIFIC +} EDID_DESCRIPTOR_TYPE; + +typedef enum { + VIDEO_TIMING_DEFAULT_GTF, + VIDEO_TIMING_RANGE_LIMITS_ONLY, + VIDEO_TIMING_SECONDARY_GTF, + VIDEO_TIMING_CVT, +} RANGE_LIMITS_VIDEO_TIMING_TYPE; + +/** + * \brief Common descriptor header structure + */ +typedef struct { + EDID_DESCRIPTOR_TYPE type; + unsigned char tag; + +} S_DESCRIPTOR_HEADER_DATA; +/** + * \brief Detailed Timing Descriptor (DTD) structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned short pixel_clock; + unsigned short horizontal_addressable_video; + unsigned short horizontal_blanking; + unsigned short vertical_addressable_video; + unsigned short vertical_blanking; + unsigned short horizontal_front_porch; + unsigned short horizontal_sync_pulse_width; + unsigned short vertical_front_porch; + unsigned short vertical_sync_pulse_width; + unsigned short horizontal_addressable_video_image_size; + unsigned short vertical_addressable_video_image_size; + unsigned char horizontal_border; + unsigned char vertical_border; + unsigned char signal_features; +} S_DTD_DATA; + +/** + * \brief Serial Number Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char serial_number[13]; + +} S_SERIAL_NUMBER_DATA; + +/** + * \brief Data String Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + char data_string[13]; + +} S_DATA_STRING_DATA; + +/** + * \brief Range Limits Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char offset_flags; + unsigned char min_vertical_rate; + unsigned char max_vertical_rate; + unsigned char min_horizontal_rate; + unsigned char max_horizontal_rate; + unsigned char max_pixel_clock; + RANGE_LIMITS_VIDEO_TIMING_TYPE type; + unsigned char suport_flags[MAX_RANGE_LIMITS_VIDEO_TIMING_LENGTH]; +} S_RANGE_LIMITS_DATA; + +/** + * \brief Range Limits Secondary GTF Flags structure + */ +typedef struct { + unsigned char start_break_frequency; + unsigned char c; + unsigned short m; + unsigned char k; + unsigned char j; + +} S_RANGE_LIMITS_VIDEO_TIMING_SECONDARY_GTF; + +/** + * \brief Range Limits CVT Flags structure + */ +typedef struct { + unsigned char cvt_version; + unsigned char additional_pixel_clock_precision; + unsigned short max_active_pixels; + unsigned char supported_ar; + unsigned char preferred_ar; + unsigned char blanking_support; + unsigned char supported_scalling; + unsigned char preferred_vertical_refresh_rate; +} S_RANGE_LIMITS_VIDEO_TIMING_CVT; + +/** + * \brief Product Name Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + char product_name[13]; + +} S_PRODUCT_NAME_DATA; + +/** + * \brief Color point Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char white_point_index_1; + unsigned short white_x_1; + unsigned short white_y_1; + unsigned char gamma_1; + unsigned char white_point_index_2; + unsigned short white_x_2; + unsigned short white_y_2; + unsigned char gamma_2; +} S_COLOR_POINT_DATA; + +/** + * \brief Standard Timing Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned short standard_timings[6]; +} S_STANDARD_TIMING_DATA; + +/** + * \brief Color Management Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char version; + unsigned short red_a3; + unsigned short red_a2; + unsigned short green_a3; + unsigned short green_a2; + unsigned short blue_a3; + unsigned short blue_a2; +} S_COLOR_MANAGEMENT_DATA; + +/** + * \brief CVT 3 Byte Code Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char version; + unsigned short addressable_lines[4]; + unsigned char aspect_ratio[4]; + unsigned char preferred_vertical_rate[4]; + unsigned char supported_vertical_rate_and_blanking[4]; + +} S_CVT_TIMING_CODES_DATA; + +/** + * \brief Established Timings 3 Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char version; + unsigned char established_timings[6]; +} S_ESTABLISHED_TIMINGS_3_DATA; + +/** + * \brief Dummy Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; +} S_DUMMY_DATA; + +/** + * \brief Manufacturer Specific Descriptor structure + */ +typedef struct { + S_DESCRIPTOR_HEADER_DATA header; + unsigned char desc_data[18]; +} S_MANUFACTURER_SPECIFIC_DATA; + +/** + * \brief CEA-861 extension structure + */ +typedef struct { + unsigned char revision; + unsigned char underscan; + unsigned char audio; +} S_CEA861_DATA; + +/** + * \brief Extended Display Identification Data (EDID) structure + */ +typedef struct { + unsigned char header[8]; + char manufacturer_name[4]; + unsigned short product_code; + unsigned int serial_number; + unsigned char week; + unsigned short year; + unsigned short edid_version; + unsigned char video_input_definition; + unsigned char horizontal_size; + unsigned char vertical_size; + unsigned char gamma; + unsigned char feature_support; + unsigned short chromacity_coorditates_red_x; + unsigned short chromacity_coorditates_red_y; + unsigned short chromacity_coorditates_green_x; + unsigned short chromacity_coorditates_green_y; + unsigned short chromacity_coorditates_blue_x; + unsigned short chromacity_coorditates_blue_y; + unsigned short chromacity_coorditates_white_x; + unsigned short chromacity_coorditates_white_y; + unsigned char established_timing_1; + unsigned char established_timing_2; + unsigned char manufacturer_timing; + unsigned short standard_timings[8]; + unsigned char descriptors[4][MAX_DESCRIPTOR_LENGTH]; + unsigned char extensions; +} S_EDID_DATA; + +EDID_PARSER_RESULT edid_parse(S_EDID_DATA *edid, unsigned char *raw_data, + unsigned int len); + +#endif /* EDID_PARSER_H */ diff --git a/drivers/video/nxp/hdp/externs.h b/drivers/video/nxp/hdp/externs.h new file mode 100644 index 00000000000..4a722c64b14 --- /dev/null +++ b/drivers/video/nxp/hdp/externs.h @@ -0,0 +1,54 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + ****************************************************************************** + * + * externs.h + * + ****************************************************************************** + */ + +#ifndef EXTERNS_H_ +#define EXTERNS_H_ + +#ifndef __UBOOT__ +#include + +#else +#include +#endif +/** + * \addtogroup UTILS + * \{ + */ +/** + * \brief read from apb + * \param addr - address to read + * \param value - pointer to store value + * \return non-zero value if error + */ +/*extern int cdn_bus_read(unsigned int addr, unsigned int* value);*/ + +/** + * \brief write to apb + * \param addr - address to write + * \param value - value to write + * \return non-zero if error + */ +/*extern int cdn_bus_write(unsigned int addr, unsigned int value);*/ + +u32 cdn_apb_read(u32 addr, u32 *value); +u32 cdn_sapb_read(u32 addr, u32 *value); +u32 cdn_apb_write(u32 addr, u32 value); +u32 cdn_sapb_write(u32 addr, u32 value); +u32 hdp_rx_apb_read(u32 addr, u32 *value); +u32 hdp_rx_sapb_read(u32 addr, u32 *value); +u32 hdp_rx_apb_write(u32 addr, u32 value); +u32 hdp_rx_sapb_write(u32 addr, u32 value); +#endif diff --git a/drivers/video/nxp/hdp/general_handler.h b/drivers/video/nxp/hdp/general_handler.h new file mode 100644 index 00000000000..24b1346c7e1 --- /dev/null +++ b/drivers/video/nxp/hdp/general_handler.h @@ -0,0 +1,132 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + ****************************************************************************** + * + * general_handler.h + * + ****************************************************************************** + */ + +#ifndef GENERAL_HANDLER_H +#define GENERAL_HANDLER_H + +/** + * \file + * \brief general handler, checks available messages, receives + * it from mailbox, handles requests and sends response + * to the host + */ +#define DP_TX_MAIL_HANDLER_REQUEST_BUFFER_LEN 256 + +/** + * \brief opcode defines host->controller + */ +#define GENERAL_MAIN_CONTROL 0x01 +#define GENERAL_TEST_ECHO 0x02 +#define GENERAL_BUS_SETTINGS 0x03 +#define GENERAL_TEST_ACCESS 0x04 + +#define GENERAL_WRITE_REGISTER 0x05 +#define GENERAL_WRITE_FIELD 0x06 +#define GENERAL_READ_REGISTER 0x07 +#define GENERAL_GET_HPD_STATE 0x11 + +#define GENERAL_TEST_TRNG_SIMPLE 0xF0 + +#define GENERAL_MAIN_CONTROL_SET_ACTIVE_BIT 0 +#define GENERAL_MAIN_CONTROL_SET_ALT_CIPHER_ADDR 1 +#define GENERAL_MAIN_CONTROL_SET_FAST_HDCP_DELAYS 2 + +#define GENERAL_BUS_SETTINGS_DPCD_BUS_BIT 0 +#define GENERAL_BUS_SETTINGS_DPCD_BUS_LOCK_BIT 1 +#define GENERAL_BUS_SETTINGS_HDCP_BUS_BIT 2 +#define GENERAL_BUS_SETTINGS_HDCP_BUS_LOCK_BIT 3 +#define GENERAL_BUS_SETTINGS_CAPB_OWNER_BIT 4 +#define GENERAL_BUS_SETTINGS_CAPB_OWNER_LOCK_BIT 5 + +/** + * \brief opcode defines controller->host + */ + +#define GENERAL_MAIN_CONTROL_RESP 0x01 +#define GENERAL_TEST_ECHO_RESP 0x02 +#define GENERAL_BUS_SETTINGS_RESP 0x03 + +#define GENERAL_READ_REGISTER_RESP 0x07 + +#define GENERAL_BUS_SETTINGS_RESP_DPCD_BUS_BIT 0 +#define GENERAL_BUS_SETTINGS_RESP_HDCP_BUS_BIT 1 +#define GENERAL_BUS_SETTINGS_RESP_CAPB_OWNER_BIT 2 + +#define GENERAL_BUS_SETTINGS_RESP_SUCCESS 0 +#define GENERAL_BUS_SETTINGS_RESP_LOCK_ERROR 1 + +typedef struct { + unsigned char dpcd_locked; + unsigned char hdcp_locked; + unsigned char capb_locked; + unsigned char active_mode; +} S_GENERAL_HANDLER_DATA; + +/** + * \brief event id sent to the host + */ +typedef enum { + EVENT_ID_DPTX_HPD = 0, + EVENT_ID_HDMI_TX_HPD = 0, + EVENT_ID_HDMI_RX_5V = 0, + + EVENT_ID_DPTX_TRAINING = 1, + EVENT_ID_HDMI_RX_SCDC_CHANGE = 1, + + EVENT_ID_RESERVE0 = 2, + EVENT_ID_RESERVE1 = 3, + + EVENT_ID_HDCPTX_STATUS = 4, + EVENT_ID_HDCPRX_STATUS = 4, + + EVENT_ID_HDCPTX_IS_KM_STORED = 5, + EVENT_ID_HDCPTX_STORE_KM = 6, + EVENT_ID_HDCPTX_IS_RECEIVER_ID_VALID = 7, + EVENT_ID_HDMITX_READ_REQUEST = 8, +} EVENT_ID; + +/** + * \brief convert bank id and register number to address and write to ptr + */ + +#define select_reg_old(bank, reg_no, ptr) \ +do { \ + ptr = 0; \ + if ((bank == 0x22) || (bank == 0x20) || (bank == 0x0b) || \ + (bank == 0x09) || (bank == 0x0A)) \ + ptr = (unsigned int *)(bank << 8 | reg_no); \ +} while (0) + +#define select_reg(bank, reg_no, ptr) \ + ptr = (unsigned int *)(bank << 8 | reg_no) + +#define select_reg4(pmsb, p2, p3, plsb, ptr) \ + ptr = (unsigned int *)((pmsb << 24) | (p2 << 16) | \ + (p3 << 8) | (plsb << 0)) + +#define EVENTS_DPTX_CNT 2 +#define EVENTS_HDCPTX_CNT 4 + +void general_handler_set_active_mode(void); +void general_handler_set_standby_mode(void); + +/** + * \brief request sending en event to the host + * \param [in] eventId + * \param [in] eventCode + */ + +#endif /* GENERAL_HANDLER_H */ diff --git a/drivers/video/nxp/hdp/hdmi.h b/drivers/video/nxp/hdp/hdmi.h new file mode 100644 index 00000000000..a8989829f26 --- /dev/null +++ b/drivers/video/nxp/hdp/hdmi.h @@ -0,0 +1,124 @@ +/****************************************************************************** + * + * Copyright (C) 2015-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * hdmi.h + * + ****************************************************************************** + */ + +#ifndef _HDMI__ +#define _HDMI__ +/* ONLY ENUMS AND #DEFINES IN THIS FILE * + * THIS FILE WILL BE USED IN HOST'S API */ + +#define EDID_SLAVE_ADDRESS 0x50 +#define EDID_SEGMENT_SLAVE_ADDRESS 0x30 +#define SCDC_SLAVE_ADDRESS 0x54 + +typedef enum { + HDMI_TX_READ, + HDMI_TX_WRITE, + HDMI_TX_UPDATE_READ, + HDMI_TX_EDID, + HDMI_TX_EVENTS, + HDMI_TX_HPD_STATUS, + HDMI_TX_DEBUG_ECHO = 0xAA, + HDMI_TX_TEST = 0xBB, + HDMI_TX_EDID_INTERNAL = 0xF0, +} HDMI_TX_OPCODE; + +typedef enum { + HDMI_I2C_ACK, + HDMI_I2C_NACK, + HDMI_I2C_TO, + HDMI_I2C_ARB_LOST, + HDMI_I2C_RRTO, + HDMI_I2C_RRT, + /** when i2c hardware didn't respond after some time */ + HDMI_I2C_HW_TO, + HDMI_I2C_ERR /*unspecified error */ +} HDMI_I2C_STATUS; + +typedef enum { + HDMI_RX_SET_EDID, + HDMI_RX_SCDC_SET, + HDMI_RX_SCDC_GET, + HDMI_RX_READ_EVENTS, + HDMI_RX_SET_HPD, + + HDMI_RX_DEBUG_ECHO = 0xAA, + HDMI_RX_TEST = 0xBB, +} HDMI_RX_OPCODE; + +typedef enum { + HDMI_SCDC_SINK_VER, + HDMI_SCDC_SOURCE_VER, +} HDMI_SCDC_FIELD; + +/*/////////////////////////////////////// */ +/*/////////////////////////////////////// */ +typedef struct { + unsigned char sink_ver; + unsigned char manufacturer_oui_1; + unsigned char manufacturer_oui_2; + unsigned char manufacturer_oui_3; + unsigned char devId[8]; + unsigned char hardware_major_rev; + unsigned char hardware_minor_rev; + unsigned char software_major_rev; + unsigned char software_minor_rev; + unsigned char manufacturerSpecific[34]; +} S_HDMI_SCDC_SET_MSG; + +typedef struct { + unsigned char source_ver; + unsigned char TMDS_Config; + unsigned char config_0; + unsigned char manufacturerSpecific[34]; +} S_HDMI_SCDC_GET_MSG; + +/*hpd events location */ +#define HDMI_RX_EVENT_5V_HIGH 0 +#define HDMI_RX_EVENT_5V_LOW 1 +#define HDMI_TX_EVENT_reserved 2 +#define HDMI_RX_EVENT_5V_VAL 3 + +#endif /*_HDMI__ */ diff --git a/drivers/video/nxp/hdp/mhl_hdtx_top.h b/drivers/video/nxp/hdp/mhl_hdtx_top.h new file mode 100644 index 00000000000..ee105f82489 --- /dev/null +++ b/drivers/video/nxp/hdp/mhl_hdtx_top.h @@ -0,0 +1,220 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * mhl_hdtx_top.h + * + ****************************************************************************** + */ + +#ifndef MHL_HDTX_TOP_H_ +#define MHL_HDTX_TOP_H_ + +/* register SCHEDULER_H_SIZE */ +#define SCHEDULER_H_SIZE 0 +#define F_H_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_H_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_H_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_H_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register SCHEDULER_V_SIZE */ +#define SCHEDULER_V_SIZE 1 +#define F_V_BLANK_SIZE(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_V_BLANK_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_V_ACTIVE_SIZE(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_V_ACTIVE_SIZE_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register SCHEDULER_KEEP_OUT */ +#define SCHEDULER_KEEP_OUT 2 +#define F_HKEEP_OUT(x) (((x) & ((1 << 9) - 1)) << 0) +#define F_HKEEP_OUT_RD(x) (((x) & (((1 << 9) - 1) << 0)) >> 0) +#define F_VKEEP_OUT_START(x) (((x) & ((1 << 11) - 1)) << 9) +#define F_VKEEP_OUT_START_RD(x) (((x) & (((1 << 11) - 1) << 9)) >> 9) +#define F_VKEEP_OUT_ZONE(x) (((x) & ((1 << 8) - 1)) << 20) +#define F_VKEEP_OUT_ZONE_RD(x) (((x) & (((1 << 8) - 1) << 20)) >> 20) + +/* register HDTX_SIGNAL_FRONT_WIDTH */ +#define HDTX_SIGNAL_FRONT_WIDTH 3 +#define F_HFRONT(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_HFRONT_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_VFRONT(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_VFRONT_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register HDTX_SIGNAL_SYNC_WIDTH */ +#define HDTX_SIGNAL_SYNC_WIDTH 4 +#define F_HSYNC(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_HSYNC_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_VSYNC(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_VSYNC_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register HDTX_SIGNAL_BACK_WIDTH */ +#define HDTX_SIGNAL_BACK_WIDTH 5 +#define F_HBACK(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_HBACK_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_VBACK(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_VBACK_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register HDTX_CONTROLLER */ +#define HDTX_CONTROLLER 6 +#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_HDMI_MODE_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2) +#define F_VIF_DATA_WIDTH_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2) +#define F_AUTO_MODE(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_AUTO_MODE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_IL_PROG(x) (((x) & ((1 << 2) - 1)) << 5) +#define F_IL_PROG_RD(x) (((x) & (((1 << 2) - 1) << 5)) >> 5) +#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7) +#define F_PIC_3D_RD(x) (((x) & (((1 << 4) - 1) << 7)) >> 7) +#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11) +#define F_BCH_EN_RD(x) (((x) & (((1 << 1) - 1) << 11)) >> 11) +#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12) +#define F_GCP_EN_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12) +#define F_SET_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 13) +#define F_SET_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13) +#define F_CLEAR_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 14) +#define F_CLEAR_AVMUTE_RD(x) (((x) & (((1 << 1) - 1) << 14)) >> 14) +#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15) +#define F_DATA_EN_RD(x) (((x) & (((1 << 1) - 1) << 15)) >> 15) +#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16) +#define F_HDMI_ENCODING_RD(x) (((x) & (((1 << 2) - 1) << 16)) >> 16) +#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18) +#define F_HDMI2_PREAMBLE_EN_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18) +#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19) +#define F_HDMI2_CTRL_IL_MODE_RD(x) (((x) & (((1 << 1) - 1) << 19)) >> 19) + +/* register HDTX_HDCP */ +#define HDTX_HDCP 7 +#define F_HDTX_HDCP_SELECT(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_HDTX_HDCP_SELECT_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_ENC_BIT(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_ENC_BIT_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_HDCP_ENABLE_1P1_FEATURES(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_HDCP_ENABLE_1P1_FEATURES_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_HDCP_DELAY_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_HDCP_DELAY_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_HDCP_DELAY_FIFO_SW_START(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_HDCP_DELAY_FIFO_SW_START_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_HDCP_DOUBLE_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_HDCP_DOUBLE_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_HDCP_SINGLE_FIFO_SW_RST(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_HDCP_SINGLE_FIFO_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_HDCP_DELAY_FIFO_AFULL_THR(x) (((x) & ((1 << 4) - 1)) << 8) +#define F_HDCP_DELAY_FIFO_AFULL_THR_RD(x) (((x) & (((1 << 4) - 1) << 8)) >> 8) +#define F_HDCP_CTRL_SW_RST(x) (((x) & ((1 << 1) - 1)) << 12) +#define F_HDCP_CTRL_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12) +#define F_HDCP_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 13) +#define F_HDCP_CTRL_IL_MODE_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13) + +/* register HDTX_HPD */ +#define HDTX_HPD 8 +#define F_HPD_VALID_WIDTH(x) (((x) & ((1 << 12) - 1)) << 0) +#define F_HPD_VALID_WIDTH_RD(x) (((x) & (((1 << 12) - 1) << 0)) >> 0) +#define F_HPD_GLITCH_WIDTH(x) (((x) & ((1 << 8) - 1)) << 12) +#define F_HPD_GLITCH_WIDTH_RD(x) (((x) & (((1 << 8) - 1) << 12)) >> 12) + +/* register HDTX_CLOCK_REG_0 */ +#define HDTX_CLOCK_REG_0 9 +#define F_DATA_REGISTER_VAL_0(x) (((x) & ((1 << 20) - 1)) << 0) +#define F_DATA_REGISTER_VAL_0_RD(x) (((x) & (((1 << 20) - 1) << 0)) >> 0) + +/* register HDTX_CLOCK_REG_1 */ +#define HDTX_CLOCK_REG_1 10 +#define F_DATA_REGISTER_VAL_1(x) (((x) & ((1 << 20) - 1)) << 0) +#define F_DATA_REGISTER_VAL_1_RD(x) (((x) & (((1 << 20) - 1) << 0)) >> 0) + +/* register HPD_PLUG_IN */ +#define HPD_PLUG_IN 11 +#define F_FILTER_HPD(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_FILTER_HPD_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register HDCP_IN */ +#define HDCP_IN 12 +#define F_HDCP_ESS_STATE(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_HDCP_ESS_STATE_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +#define F_HDCP_DOUBLE_FIFO_WFULL(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_HDCP_DOUBLE_FIFO_WFULL_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_HDCP_DOUBLE_FIFO_REMPTY(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_HDCP_DOUBLE_FIFO_REMPTY_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_HDCP_DOUBLE_FIFO_OVERRUN(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_HDCP_DOUBLE_FIFO_OVERRUN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_HDCP_DOUBLE_FIFO_UNDERRUN(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_HDCP_DOUBLE_FIFO_UNDERRUN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_HDCP_DELAY_FIFO_EMPTY(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_HDCP_DELAY_FIFO_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_HDCP_DELAY_FIFO_FULL(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_HDCP_DELAY_FIFO_FULL_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) +#define F_HDCP_SINGLE_FIFO_WFULL(x) (((x) & ((1 << 2) - 1)) << 10) +#define F_HDCP_SINGLE_FIFO_WFULL_RD(x) (((x) & (((1 << 2) - 1) << 10)) >> 10) +#define F_HDCP_SINGLE_FIFO_REMPTY(x) (((x) & ((1 << 2) - 1)) << 12) +#define F_HDCP_SINGLE_FIFO_REMPTY_RD(x) (((x) & (((1 << 2) - 1) << 12)) >> 12) +#define F_HDCP_SINGLE_FIFO_OVERRUN(x) (((x) & ((1 << 2) - 1)) << 14) +#define F_HDCP_SINGLE_FIFO_OVERRUN_RD(x) (((x) & (((1 << 2) - 1) << 14)) >> 14) +#define F_HDCP_SINGLE_FIFO_UNDERRUN(x) (((x) & ((1 << 2) - 1)) << 16) +#define F_HDCP_SINGLE_FIFO_UNDERRUN_RD(x) (((x) & (((1 << 2) - 1) << 16)) >> 16) + +/* register GCP_FORCE_COLOR_DEPTH_CODING */ +#define GCP_FORCE_COLOR_DEPTH_CODING 13 +#define F_COLOR_DEPTH_VAL(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_COLOR_DEPTH_VAL_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +#define F_COLOR_DEPTH_FORCE(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_COLOR_DEPTH_FORCE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_DEFAULT_PHASE_VAL(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_DEFAULT_PHASE_VAL_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) + +/* register SSCP_POSITIONING */ +#define SSCP_POSITIONING 14 +#define F_SSCP_ROW_VAL(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_SSCP_ROW_VAL_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) +#define F_SSCP_COL_VAL(x) (((x) & ((1 << 16) - 1)) << 16) +#define F_SSCP_COL_VAL_RD(x) (((x) & (((1 << 16) - 1) << 16)) >> 16) + +/* register HDCP_WIN_OF_OPP_POSITION */ +#define HDCP_WIN_OF_OPP_POSITION 15 +#define F_HDCP_WIN_OF_OPP_START(x) (((x) & ((1 << 10) - 1)) << 0) +#define F_HDCP_WIN_OF_OPP_START_RD(x) (((x) & (((1 << 10) - 1) << 0)) >> 0) +#define F_HDCP_WIN_OF_OPP_SIZE(x) (((x) & ((1 << 6) - 1)) << 10) +#define F_HDCP_WIN_OF_OPP_SIZE_RD(x) (((x) & (((1 << 6) - 1) << 10)) >> 10) + +#endif /*MHL_HDTX_TOP */ diff --git a/drivers/video/nxp/hdp/opcodes.h b/drivers/video/nxp/hdp/opcodes.h new file mode 100644 index 00000000000..dc2fde85d68 --- /dev/null +++ b/drivers/video/nxp/hdp/opcodes.h @@ -0,0 +1,85 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * opcodes.h + * + ****************************************************************************** + */ + +#ifndef OPCODES_H_ +# define OPCODES_H_ + +# define DP_TX_MAIL_HANDLER_H +# define DP_TX_MAIL_HANDLER_REQUEST_BUFFER_LEN 256 +# define DPTX_SET_POWER_MNG 0x00 +# define DPTX_SET_HOST_CAPABILITIES 0x01 +# define DPTX_GET_EDID 0x02 +# define DPTX_READ_DPCD 0x03 +# define DPTX_WRITE_DPCD 0x04 +# define DPTX_ENABLE_EVENT 0x05 +# define DPTX_WRITE_REGISTER 0x06 +# define DPTX_READ_REGISTER 0x07 +# define DPTX_WRITE_FIELD 0x08 +# define DPTX_TRAINING_CONTROL 0x09 +# define DPTX_READ_EVENT 0x0A +# define DPTX_READ_LINK_STAT 0x0B +# define DPTX_SET_VIDEO 0x0C +# define DPTX_SET_AUDIO 0x0D +# define DPTX_GET_LAST_AUX_STAUS 0x0E +# define DPTX_SET_LINK_BREAK_POINT 0x0F +# define DPTX_FORCE_LANES 0x10 +# define DPTX_HPD_STATE 0x11 +# define DPTX_DBG_SET 0xF0 +# define DP_TX_OPCODE_READ_I2C_REQUEST 0xA5 +# define DP_TX_OPCODE_WRITE_I2C_REQUEST 0xA6 +# define DP_TX_OPCODE_MESSAGE_FILTER 0xA7 +# define DPTX_EDID_RESP 0x02 +# define DPTX_DPCD_READ_RESP 0x03 +# define DPTX_DPCD_WRITE_RESP 0x04 +# define DPTX_READ_EVENT_RESP 0x0A +# define DPTX_READ_REGISTER_RESP 0x07 +# define DP_TX_OPCODE_MESSAGE 0x10 +# define DP_TX_OPCODE_READ_I2C_RESPONSE 0x50 +# define DP_TX_OPCODE_WRITE_I2C_RESPONSE 0x60 +# define DP_TX_OPCODE_LOOPBACK_TEST 0xFE +# define DP_TX_OPCODE_BIT_TEST 0xFF +# define DP_TX_EVENT_ENABLE_HPD_BIT 0x00 +# define DP_TX_EVENT_ENABLE_TRAINING_BIT 0x01 +# define DP_TX_EVENT_CODE_HPD_HIGH 0x01 +# define DP_TX_EVENT_CODE_HPD_LOW 0x02 +# define DP_TX_EVENT_CODE_HPD_PULSE 0x04 +# define DP_TX_EVENT_CODE_HPD_STATE_HIGH 0x08 +# define DP_TX_EVENT_CODE_HPD_STATE_LOW 0x00 +# define DP_TX_EVENT_CODE_TRAINING_FULL_STARTED 0x01 +# define DP_TX_EVENT_CODE_TRAINING_FAST_STARTED 0x02 +# define DP_TX_EVENT_CODE_TRAINING_FINISHED_CR 0x04 +# define DP_TX_EVENT_CODE_TRAINING_FINISHED_EQ 0x08 +# define DP_TX_EVENT_CODE_TRAINING_FINISHED_FAST 0x10 +# define DP_TX_EVENT_CODE_TRAINING_FAILED_CR 0x20 +# define DP_TX_EVENT_CODE_TRAINING_FAILED_EQ 0x40 +# define DP_TX_EVENT_CODE_TRAINING_FAILED_FAST 0x80 +# define MB_MODULE_ID_DP_TX 0x01 +# define MB_MODULE_ID_DP_RX 0x02 +# define MB_MODULE_ID_HDMI_TX 0x03 +# define MB_MODULE_ID_HDMI_RX 0x04 +# define MB_MODULE_ID_MHL_TX 0x05 +# define MB_MODULE_ID_MHL_RX 0x06 +# define MB_MODULE_ID_HDCP_TX 0x07 +# define MB_MODULE_ID_HDCP_RX 0x08 +# define MB_MODULE_ID_HDCP_GENERAL 0x09 +# define MB_MODULE_ID_GENERAL 0x0A +# define MB_MODULE_ID 1 + +#endif diff --git a/drivers/video/nxp/hdp/source_car.h b/drivers/video/nxp/hdp/source_car.h new file mode 100644 index 00000000000..1a5f85f8aaa --- /dev/null +++ b/drivers/video/nxp/hdp/source_car.h @@ -0,0 +1,179 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * source_car.h + * + ****************************************************************************** + */ + +#ifndef SOURCE_CAR_H_ +#define SOURCE_CAR_H_ + +/* register SOURCE_HDTX_CAR */ +#define SOURCE_HDTX_CAR 0 +#define F_HDTX_PIXEL_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HDTX_PIXEL_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_HDTX_PIXEL_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_HDTX_PIXEL_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_HDTX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_HDTX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_HDTX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_HDTX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_HDTX_PHY_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_HDTX_PHY_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_HDTX_PHY_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_HDTX_PHY_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_HDTX_PHY_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_HDTX_PHY_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_HDTX_PHY_CHAR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_HDTX_PHY_CHAR_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) + +/* register SOURCE_DPTX_CAR */ +#define SOURCE_DPTX_CAR 1 +#define F_CFG_DPTX_VIF_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_CFG_DPTX_VIF_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_CFG_DPTX_VIF_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_CFG_DPTX_VIF_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_DPTX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_DPTX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_DPTX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_DPTX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_SOURCE_AUX_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_SOURCE_AUX_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_SOURCE_AUX_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_SOURCE_AUX_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_DPTX_PHY_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_DPTX_PHY_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_DPTX_PHY_CHAR_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_DPTX_PHY_CHAR_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_DPTX_PHY_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_DPTX_PHY_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_DPTX_PHY_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_DPTX_PHY_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) +#define F_DPTX_FRMR_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 10) +#define F_DPTX_FRMR_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 10)) >> 10) +#define F_DPTX_FRMR_DATA_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 11) +#define F_DPTX_FRMR_DATA_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 11)) >> 11) + +/* register SOURCE_PHY_CAR */ +#define SOURCE_PHY_CAR 2 +#define F_SOURCE_PHY_DATA_OUT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_PHY_DATA_OUT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_DATA_OUT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_PHY_DATA_OUT_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_SOURCE_PHY_CHAR_OUT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_SOURCE_PHY_CHAR_OUT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register SOURCE_CEC_CAR */ +#define SOURCE_CEC_CAR 3 +#define F_SOURCE_CEC_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_CEC_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_CEC_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_CEC_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) + +/* register SOURCE_CBUS_CAR */ +#define SOURCE_CBUS_CAR 4 +#define F_SOURCE_CBUS_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_CBUS_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_CBUS_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_CBUS_SYS_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) + +/* register SOURCE_PKT_CAR */ +#define SOURCE_PKT_CAR 6 +#define F_SOURCE_PKT_DATA_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_PKT_DATA_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_PKT_DATA_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_PKT_DATA_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_SOURCE_PKT_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_SOURCE_PKT_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_SOURCE_PKT_SYS_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_SOURCE_PKT_SYS_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register SOURCE_AIF_CAR */ +#define SOURCE_AIF_CAR 7 +#define F_SOURCE_AIF_PKT_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_AIF_PKT_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_AIF_PKT_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_AIF_PKT_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_SOURCE_AIF_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_SOURCE_AIF_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_SOURCE_AIF_SYS_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_SOURCE_AIF_SYS_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_SPDIF_CDR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_SPDIF_CDR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_SPDIF_CDR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_SPDIF_CDR_CLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_SPDIF_MCLK_EN(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_SPDIF_MCLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_SPDIF_MCLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_SPDIF_MCLK_RSTN_EN_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) + +/* register SOURCE_CIPHER_CAR */ +#define SOURCE_CIPHER_CAR 8 +#define F_SOURCE_CIPHER_CHAR_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_CIPHER_CHAR_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_CIPHER_CHAR_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_CIPHER_CHAR_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_SOURCE_CIPHER_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_SOURCE_CIPHER_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register SOURCE_CRYPTO_CAR */ +#define SOURCE_CRYPTO_CAR 9 +#define F_SOURCE_CRYPTO_SYS_CLK_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SOURCE_CRYPTO_SYS_CLK_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_SOURCE_CRYPTO_SYS_CLK_RSTN_EN(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_SOURCE_CRYPTO_SYS_CLK_RSTN_EN_RD(x) \ + (((x) & (((1 << 1) - 1) << 1)) >> 1) + +#endif /*SOURCE_CAR */ diff --git a/drivers/video/nxp/hdp/source_phy.h b/drivers/video/nxp/hdp/source_phy.h new file mode 100644 index 00000000000..540809db971 --- /dev/null +++ b/drivers/video/nxp/hdp/source_phy.h @@ -0,0 +1,181 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * source_phy.h + * + ****************************************************************************** + */ + +#ifndef SOURCE_PHY_H_ +#define SOURCE_PHY_H_ + +/* register SHIFT_PATTERN_IN_3_0 */ +#define SHIFT_PATTERN_IN_3_0 0 +#define F_SOURCE_PHY_SHIFT_PATTERN0(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SOURCE_PHY_SHIFT_PATTERN0_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_SHIFT_PATTERN1(x) (((x) & ((1 << 8) - 1)) << 8) +#define F_SOURCE_PHY_SHIFT_PATTERN1_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_SHIFT_PATTERN2(x) (((x) & ((1 << 8) - 1)) << 16) +#define F_SOURCE_PHY_SHIFT_PATTERN2_RD(x) (((x) & (((1 << 8) - 1) << 16)) >> 16) +#define F_SOURCE_PHY_SHIFT_PATTERN3(x) (((x) & ((1 << 8) - 1)) << 24) +#define F_SOURCE_PHY_SHIFT_PATTERN3_RD(x) (((x) & (((1 << 8) - 1) << 24)) >> 24) + +/* register SHIFT_PATTERN_IN_4_7 */ +#define SHIFT_PATTERN_IN_4_7 1 +#define F_SOURCE_PHY_SHIFT_PATTERN4(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SOURCE_PHY_SHIFT_PATTERN4_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_SHIFT_PATTERN5(x) (((x) & ((1 << 8) - 1)) << 8) +#define F_SOURCE_PHY_SHIFT_PATTERN5_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_SHIFT_PATTERN6(x) (((x) & ((1 << 8) - 1)) << 16) +#define F_SOURCE_PHY_SHIFT_PATTERN6_RD(x) (((x) & (((1 << 8) - 1) << 16)) >> 16) +#define F_SOURCE_PHY_SHIFT_PATTERN7(x) (((x) & ((1 << 8) - 1)) << 24) +#define F_SOURCE_PHY_SHIFT_PATTERN7_RD(x) (((x) & (((1 << 8) - 1) << 24)) >> 24) + +/* register SHIFT_PATTERN_IN9_8 */ +#define SHIFT_PATTERN_IN9_8 2 +#define F_SOURCE_PHY_SHIFT_PATTERN8(x) (((x) & ((1 << 8) - 1)) << 0) +#define F_SOURCE_PHY_SHIFT_PATTERN8_RD(x) (((x) & (((1 << 8) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_SHIFT_PATTERN9(x) (((x) & ((1 << 8) - 1)) << 8) +#define F_SOURCE_PHY_SHIFT_PATTERN9_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_SHIFT_LOAD(x) (((x) & ((1 << 1) - 1)) << 16) +#define F_SOURCE_PHY_SHIFT_LOAD_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16) +#define F_SOURCE_PHY_SHIFT_EN(x) (((x) & ((1 << 1) - 1)) << 17) +#define F_SOURCE_PHY_SHIFT_EN_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17) +#define F_SOURCE_PHY_SHIFT_REPETITION(x) (((x) & ((1 << 3) - 1)) << 18) +#define F_SOURCE_PHY_SHIFT_REPETITION_RD(x) \ + (((x) & (((1 << 3) - 1) << 18)) >> 18) + +/* register PRBS_CNTRL */ +#define PRBS_CNTRL 3 +#define F_SOURCE_PHY_PRBS0_MODE(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_SOURCE_PHY_PRBS0_MODE_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_PRBS0_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 2) +#define F_SOURCE_PHY_PRBS0_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2) +#define F_SOURCE_PHY_PRBS1_MODE(x) (((x) & ((1 << 2) - 1)) << 4) +#define F_SOURCE_PHY_PRBS1_MODE_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4) +#define F_SOURCE_PHY_PRBS1_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 6) +#define F_SOURCE_PHY_PRBS1_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 6)) >> 6) +#define F_SOURCE_PHY_PRBS2_MODE(x) (((x) & ((1 << 2) - 1)) << 8) +#define F_SOURCE_PHY_PRBS2_MODE_RD(x) (((x) & (((1 << 2) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_PRBS2_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 10) +#define F_SOURCE_PHY_PRBS2_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 10)) >> 10) +#define F_SOURCE_PHY_PRBS3_MODE(x) (((x) & ((1 << 2) - 1)) << 12) +#define F_SOURCE_PHY_PRBS3_MODE_RD(x) (((x) & (((1 << 2) - 1) << 12)) >> 12) +#define F_SOURCE_PHY_PRBS3_OUT_MODE(x) (((x) & ((1 << 2) - 1)) << 14) +#define F_SOURCE_PHY_PRBS3_OUT_MODE_RD(x) (((x) & (((1 << 2) - 1) << 14)) >> 14) + +/* register PRBS_ERR_INSERTION */ +#define PRBS_ERR_INSERTION 4 +#define F_ADD_ERROR0(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_ADD_ERROR0_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_NUMBER_OF_ERRORS0(x) (((x) & ((1 << 5) - 1)) << 1) +#define F_NUMBER_OF_ERRORS0_RD(x) (((x) & (((1 << 5) - 1) << 1)) >> 1) +#define F_ADD_ERROR1(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_ADD_ERROR1_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_NUMBER_OF_ERRORS1(x) (((x) & ((1 << 5) - 1)) << 7) +#define F_NUMBER_OF_ERRORS1_RD(x) (((x) & (((1 << 5) - 1) << 7)) >> 7) +#define F_ADD_ERROR2(x) (((x) & ((1 << 1) - 1)) << 12) +#define F_ADD_ERROR2_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12) +#define F_NUMBER_OF_ERRORS2(x) (((x) & ((1 << 5) - 1)) << 13) +#define F_NUMBER_OF_ERRORS2_RD(x) (((x) & (((1 << 5) - 1) << 13)) >> 13) +#define F_ADD_ERROR3(x) (((x) & ((1 << 1) - 1)) << 18) +#define F_ADD_ERROR3_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18) +#define F_NUMBER_OF_ERRORS3(x) (((x) & ((1 << 5) - 1)) << 19) +#define F_NUMBER_OF_ERRORS3_RD(x) (((x) & (((1 << 5) - 1) << 19)) >> 19) + +/* register LANES_CONFIG */ +#define LANES_CONFIG 5 +#define F_SOURCE_PHY_LANE0_SWAP(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_SOURCE_PHY_LANE0_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_LANE1_SWAP(x) (((x) & ((1 << 2) - 1)) << 2) +#define F_SOURCE_PHY_LANE1_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 2)) >> 2) +#define F_SOURCE_PHY_LANE2_SWAP(x) (((x) & ((1 << 2) - 1)) << 4) +#define F_SOURCE_PHY_LANE2_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 4)) >> 4) +#define F_SOURCE_PHY_LANE3_SWAP(x) (((x) & ((1 << 2) - 1)) << 6) +#define F_SOURCE_PHY_LANE3_SWAP_RD(x) (((x) & (((1 << 2) - 1) << 6)) >> 6) +#define F_SOURCE_PHY_LANE0_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_SOURCE_PHY_LANE0_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_LANE1_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_SOURCE_PHY_LANE1_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) +#define F_SOURCE_PHY_LANE2_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 10) +#define F_SOURCE_PHY_LANE2_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 10)) >> 10) +#define F_SOURCE_PHY_LANE3_LSB_MSB(x) (((x) & ((1 << 1) - 1)) << 11) +#define F_SOURCE_PHY_LANE3_LSB_MSB_RD(x) (((x) & (((1 << 1) - 1) << 11)) >> 11) +#define F_SOURCE_PHY_AUX_SPARE(x) (((x) & ((1 << 4) - 1)) << 12) +#define F_SOURCE_PHY_AUX_SPARE_RD(x) (((x) & (((1 << 4) - 1) << 12)) >> 12) +#define F_SOURCE_PHY_LANE0_POLARITY(x) (((x) & ((1 << 1) - 1)) << 16) +#define F_SOURCE_PHY_LANE0_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16) +#define F_SOURCE_PHY_LANE1_POLARITY(x) (((x) & ((1 << 1) - 1)) << 17) +#define F_SOURCE_PHY_LANE1_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17) +#define F_SOURCE_PHY_LANE2_POLARITY(x) (((x) & ((1 << 1) - 1)) << 18) +#define F_SOURCE_PHY_LANE2_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 18)) >> 18) +#define F_SOURCE_PHY_LANE3_POLARITY(x) (((x) & ((1 << 1) - 1)) << 19) +#define F_SOURCE_PHY_LANE3_POLARITY_RD(x) (((x) & (((1 << 1) - 1) << 19)) >> 19) +#define F_SOURCE_PHY_DATA_DEL_EN(x) (((x) & ((1 << 1) - 1)) << 20) +#define F_SOURCE_PHY_DATA_DEL_EN_RD(x) (((x) & (((1 << 1) - 1) << 20)) >> 20) +#define F_SOURCE_PHY_COMB_BYPASS(x) (((x) & ((1 << 1) - 1)) << 21) +#define F_SOURCE_PHY_COMB_BYPASS_RD(x) (((x) & (((1 << 1) - 1) << 21)) >> 21) +#define F_SOURCE_PHY_20_10(x) (((x) & ((1 << 1) - 1)) << 22) +#define F_SOURCE_PHY_20_10_RD(x) (((x) & (((1 << 1) - 1) << 22)) >> 22) + +/* register PHY_DATA_SEL */ +#define PHY_DATA_SEL 6 +#define F_SOURCE_PHY_DATA_SEL(x) (((x) & ((1 << 3) - 1)) << 0) +#define F_SOURCE_PHY_DATA_SEL_RD(x) (((x) & (((1 << 3) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_MHDP_SEL(x) (((x) & ((1 << 2) - 1)) << 3) +#define F_SOURCE_PHY_MHDP_SEL_RD(x) (((x) & (((1 << 2) - 1) << 3)) >> 3) + +/* register LANES_DEL_VAL */ +#define LANES_DEL_VAL 7 +#define F_SOURCE_PHY_LANE0_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_SOURCE_PHY_LANE0_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +#define F_SOURCE_PHY_LANE1_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 4) +#define F_SOURCE_PHY_LANE1_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 4)) >> 4) +#define F_SOURCE_PHY_LANE2_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 8) +#define F_SOURCE_PHY_LANE2_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 8)) >> 8) +#define F_SOURCE_PHY_LANE3_DEL_VAL(x) (((x) & ((1 << 4) - 1)) << 12) +#define F_SOURCE_PHY_LANE3_DEL_VAL_RD(x) (((x) & (((1 << 4) - 1) << 12)) >> 12) + +#endif /*SOURCE_PHY */ diff --git a/drivers/video/nxp/hdp/source_pif.h b/drivers/video/nxp/hdp/source_pif.h new file mode 100644 index 00000000000..b9cbe16659d --- /dev/null +++ b/drivers/video/nxp/hdp/source_pif.h @@ -0,0 +1,174 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * source_pif.h + * + ****************************************************************************** + */ + +#ifndef SOURCE_PIF_H_ +#define SOURCE_PIF_H_ + +/* register SOURCE_PIF_WR_ADDR */ +#define SOURCE_PIF_WR_ADDR 0 +#define F_WR_ADDR(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_WR_ADDR_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_WR_REQ */ +#define SOURCE_PIF_WR_REQ 1 +#define F_HOST_WR(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HOST_WR_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_RD_ADDR */ +#define SOURCE_PIF_RD_ADDR 2 +#define F_RD_ADDR(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_RD_ADDR_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_RD_REQ */ +#define SOURCE_PIF_RD_REQ 3 +#define F_HOST_RD(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HOST_RD_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_DATA_WR */ +#define SOURCE_PIF_DATA_WR 4 +/*# define F_DATA_WR(x) (((x) & ((1 << 32) - 1)) << 0) */ +/*# define F_DATA_WR_RD(x) (((x) & (((1 << 32) - 1) << 0)) >> 0) */ +#define F_DATA_WR(x) (((x) & 0xffffffff) << 0) +#define F_DATA_WR_RD(x) (((x) & 0xffffffff) >> 0) + +/* register SOURCE_PIF_DATA_RD */ +#define SOURCE_PIF_DATA_RD 5 +#define F_FIFO2_DATA_OUT(x) (((x) & ((1 << 32) - 1)) << 0) +#define F_FIFO2_DATA_OUT_RD(x) (((x) & (((1 << 32) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_FIFO1_FLUSH */ +#define SOURCE_PIF_FIFO1_FLUSH 6 +#define F_FIFO1_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_FIFO1_FLUSH_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_FIFO2_FLUSH */ +#define SOURCE_PIF_FIFO2_FLUSH 7 +#define F_FIFO2_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_FIFO2_FLUSH_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_STATUS */ +#define SOURCE_PIF_STATUS 8 +#define F_SOURCE_PKT_MEM_CTRL_FSM_STATE(x) (((x) & ((1 << 2) - 1)) << 0) +#define F_SOURCE_PKT_MEM_CTRL_FSM_STATE_RD(x) \ + (((x) & (((1 << 2) - 1) << 0)) >> 0) +#define F_FIFO1_FULL(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_FIFO1_FULL_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_FIFO2_EMPTY(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_FIFO2_EMPTY_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register SOURCE_PIF_INTERRUPT_SOURCE */ +#define SOURCE_PIF_INTERRUPT_SOURCE 9 +#define F_HOST_WR_DONE_INT(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HOST_WR_DONE_INT_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_HOST_RD_DONE_INT(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_HOST_RD_DONE_INT_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_NONVALID_TYPE_REQUESTED_INT(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_NONVALID_TYPE_REQUESTED_INT_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_PSLVERR(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_PSLVERR_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_ALLOC_WR_DONE(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_ALLOC_WR_DONE_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_ALLOC_WR_ERROR(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_ALLOC_WR_ERROR_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_FIFO1_OVERFLOW(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_FIFO1_OVERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_FIFO1_UNDERFLOW(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_FIFO1_UNDERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_FIFO2_OVERFLOW(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_FIFO2_OVERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_FIFO2_UNDERFLOW(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_FIFO2_UNDERFLOW_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) + +/* register SOURCE_PIF_INTERRUPT_MASK */ +#define SOURCE_PIF_INTERRUPT_MASK 10 +#define F_HOST_WR_DONE_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_HOST_WR_DONE_INT_MASK_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_HOST_RD_DONE_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_HOST_RD_DONE_INT_MASK_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_NONVALID_TYPE_REQUESTED_INT_MASK(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_NONVALID_TYPE_REQUESTED_INT_MASK_RD(x) \ + (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_PSLVERR_MASK(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_PSLVERR_MASK_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) +#define F_ALLOC_WR_DONE_MASK(x) (((x) & ((1 << 1) - 1)) << 4) +#define F_ALLOC_WR_DONE_MASK_RD(x) (((x) & (((1 << 1) - 1) << 4)) >> 4) +#define F_ALLOC_WR_ERROR_MASK(x) (((x) & ((1 << 1) - 1)) << 5) +#define F_ALLOC_WR_ERROR_MASK_RD(x) (((x) & (((1 << 1) - 1) << 5)) >> 5) +#define F_FIFO1_OVERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 6) +#define F_FIFO1_OVERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 6)) >> 6) +#define F_FIFO1_UNDERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 7) +#define F_FIFO1_UNDERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 7)) >> 7) +#define F_FIFO2_OVERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 8) +#define F_FIFO2_OVERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 8)) >> 8) +#define F_FIFO2_UNDERFLOW_MASK(x) (((x) & ((1 << 1) - 1)) << 9) +#define F_FIFO2_UNDERFLOW_MASK_RD(x) (((x) & (((1 << 1) - 1) << 9)) >> 9) + +/* register SOURCE_PIF_PKT_ALLOC_REG */ +#define SOURCE_PIF_PKT_ALLOC_REG 11 +#define F_PKT_ALLOC_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0) +#define F_PKT_ALLOC_ADDRESS_RD(x) (((x) & (((1 << 4) - 1) << 0)) >> 0) +#define F_PACKET_TYPE(x) (((x) & ((1 << 8) - 1)) << 8) +#define F_PACKET_TYPE_RD(x) (((x) & (((1 << 8) - 1) << 8)) >> 8) +#define F_TYPE_VALID(x) (((x) & ((1 << 1) - 1)) << 16) +#define F_TYPE_VALID_RD(x) (((x) & (((1 << 1) - 1) << 16)) >> 16) +#define F_ACTIVE_IDLE_TYPE(x) (((x) & ((1 << 1) - 1)) << 17) +#define F_ACTIVE_IDLE_TYPE_RD(x) (((x) & (((1 << 1) - 1) << 17)) >> 17) + +/* register SOURCE_PIF_PKT_ALLOC_WR_EN */ +#define SOURCE_PIF_PKT_ALLOC_WR_EN 12 +#define F_PKT_ALLOC_WR_EN(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_PKT_ALLOC_WR_EN_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +/* register SOURCE_PIF_SW_RESET */ +#define SOURCE_PIF_SW_RESET 13 +#define F_SW_RST(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_SW_RST_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +#endif /*SOURCE_PIF */ diff --git a/drivers/video/nxp/hdp/source_vif.h b/drivers/video/nxp/hdp/source_vif.h new file mode 100644 index 00000000000..a9b6c00154f --- /dev/null +++ b/drivers/video/nxp/hdp/source_vif.h @@ -0,0 +1,93 @@ +/****************************************************************************** + * + * Copyright (C) 2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * source_vif.h + * + ****************************************************************************** + */ + +#ifndef SOURCE_VIF_H_ +#define SOURCE_VIF_H_ + +/* register BND_HSYNC2VSYNC */ +#define BND_HSYNC2VSYNC 0 +#define F_IP_DTCT_WIN(x) (((x) & ((1 << 12) - 1)) << 0) +#define F_IP_DTCT_WIN_RD(x) (((x) & (((1 << 12) - 1) << 0)) >> 0) +#define F_IP_DET_EN(x) (((x) & ((1 << 1) - 1)) << 12) +#define F_IP_DET_EN_RD(x) (((x) & (((1 << 1) - 1) << 12)) >> 12) +#define F_IP_VIF_BYPASS(x) (((x) & ((1 << 1) - 1)) << 13) +#define F_IP_VIF_BYPASS_RD(x) (((x) & (((1 << 1) - 1) << 13)) >> 13) + +/* register HSYNC2VSYNC_F1_L1 */ +#define HSYNC2VSYNC_F1_L1 1 +#define F_IP_DTCT_HSYNC2VSYNC_F1(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_IP_DTCT_HSYNC2VSYNC_F1_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) + +/* register HSYNC2VSYNC_F2_L1 */ +#define HSYNC2VSYNC_F2_L1 2 +#define F_IP_DTCT_HSYNC2VSYNC_F2(x) (((x) & ((1 << 16) - 1)) << 0) +#define F_IP_DTCT_HSYNC2VSYNC_F2_RD(x) (((x) & (((1 << 16) - 1) << 0)) >> 0) + +/* register HSYNC2VSYNC_STATUS */ +#define HSYNC2VSYNC_STATUS 3 +#define F_IP_DTCT_ERR(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_IP_DTCT_ERR_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) +#define F_IP_DCT_IP(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_IP_DCT_IP_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_IP_DTCT_VJITTER(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_IP_DTCT_VJITTER_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_IP_DTCT_HJITTER(x) (((x) & ((1 << 1) - 1)) << 3) +#define F_IP_DTCT_HJITTER_RD(x) (((x) & (((1 << 1) - 1) << 3)) >> 3) + +/* register HSYNC2VSYNC_POL_CTRL */ +#define HSYNC2VSYNC_POL_CTRL 4 +#define F_VPOL(x) (((x) & ((1 << 1) - 1)) << 2) +#define F_VPOL_RD(x) (((x) & (((1 << 1) - 1) << 2)) >> 2) +#define F_HPOL(x) (((x) & ((1 << 1) - 1)) << 1) +#define F_HPOL_RD(x) (((x) & (((1 << 1) - 1) << 1)) >> 1) +#define F_VIF_AUTO_MODE(x) (((x) & ((1 << 1) - 1)) << 0) +#define F_VIF_AUTO_MODE_RD(x) (((x) & (((1 << 1) - 1) << 0)) >> 0) + +#endif /*SOURCE_VIF */ diff --git a/drivers/video/nxp/hdp/test_base_sw.c b/drivers/video/nxp/hdp/test_base_sw.c new file mode 100644 index 00000000000..bd44712057f --- /dev/null +++ b/drivers/video/nxp/hdp/test_base_sw.c @@ -0,0 +1,217 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + ****************************************************************************** + * + * test_base_sw.c + * + ****************************************************************************** + */ + +#ifndef __UBOOT__ +#include +#include +#include +#else +#include +#include +#include + +#ifdef CONFIG_ARCH_IMX8M +/* mscale */ +#define HDMI_BASE 0x32c00000 +#define HDMI_PHY_BASE 0x32c80000 +#define HDMI_SEC_BASE 0x32e40000 +#endif +#ifdef CONFIG_ARCH_IMX8 +/* QM */ +#define HDMI_BASE 0x56268000 +#define HDMI_SEC_BASE 0x56269000 +#define HDMI_OFFSET_ADDR 0x56261008 +#define HDMI_SEC_OFFSET_ADDR 0x5626100c + +#define HDMI_RX_BASE 0x58268000 +#define HDMI_RX_SEC_BASE 0x58269000 +#define HDMI_RX_OFFSET_ADDR 0x58261004 +#define HDMI_RX_SEC_OFFSET_ADDR 0x58261008 +#endif + +#ifdef CONFIG_ARCH_LS1028A +#define HDMI_BASE 0xf200000 +#endif +#endif + +#ifdef CONFIG_ARCH_IMX8M +int cdn_apb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + u64 tmp_addr = addr + HDMI_BASE; + + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int cdn_apb_write(unsigned int addr, unsigned int value) +{ + u64 tmp_addr = addr + HDMI_BASE; + + __raw_writel(value, tmp_addr); + return 0; +} + +int cdn_sapb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + u64 tmp_addr = addr + HDMI_SEC_BASE; + + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int cdn_sapb_write(unsigned int addr, unsigned int value) +{ + u64 tmp_addr = addr + HDMI_SEC_BASE; + + __raw_writel(value, tmp_addr); + return 0; +} + +void cdn_sleep(uint32_t ms) +{ + mdelay(ms); +} + +void cdn_usleep(uint32_t us) +{ + udelay(us); +} +#endif +#ifdef CONFIG_ARCH_IMX8 +int cdn_apb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + u64 tmp_addr = (addr & 0xfff) + HDMI_BASE; + + __raw_writel(addr >> 12, HDMI_OFFSET_ADDR); + + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int cdn_apb_write(unsigned int addr, unsigned int value) +{ + u64 tmp_addr = (addr & 0xfff) + HDMI_BASE; + + __raw_writel(addr >> 12, HDMI_OFFSET_ADDR); + __raw_writel(value, tmp_addr); + + return 0; +} + +int cdn_sapb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + u64 tmp_addr = (addr & 0xfff) + HDMI_SEC_BASE; + + __raw_writel(addr >> 12, HDMI_SEC_OFFSET_ADDR); + + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int cdn_sapb_write(unsigned int addr, unsigned int value) +{ + u64 tmp_addr = (addr & 0xfff) + HDMI_SEC_BASE; + + __raw_writel(addr >> 12, HDMI_SEC_OFFSET_ADDR); + __raw_writel(value, tmp_addr); + + return 0; +} + +int hdp_rx_apb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + u64 tmp_addr = (addr & 0xfff) + HDMI_RX_BASE; + + __raw_writel(addr >> 12, HDMI_RX_OFFSET_ADDR); + + temp = __raw_readl(tmp_addr); + + *value = temp; + return 0; +} + +int hdp_rx_apb_write(unsigned int addr, unsigned int value) +{ + u64 tmp_addr = (addr & 0xfff) + HDMI_RX_BASE; + + __raw_writel(addr >> 12, HDMI_RX_OFFSET_ADDR); + + __raw_writel(value, tmp_addr); + + return 0; +} + +int hdp_rx_sapb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + u64 tmp_addr = (addr & 0xfff) + HDMI_RX_SEC_BASE; + + __raw_writel(addr >> 12, HDMI_RX_SEC_OFFSET_ADDR); + + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int hdp_rx_sapb_write(unsigned int addr, unsigned int value) +{ + u64 tmp_addr = (addr & 0xfff) + HDMI_RX_SEC_BASE; + + __raw_writel(addr >> 12, HDMI_RX_SEC_OFFSET_ADDR); + __raw_writel(value, tmp_addr); + + return 0; +} + +void cdn_sleep(uint32_t ms) +{ + mdelay(ms); +} + +void cdn_usleep(uint32_t us) +{ + udelay(us); +} +#endif + +#ifdef CONFIG_ARCH_LS1028A +int cdn_apb_read(unsigned int addr, unsigned int *value) +{ + unsigned int temp; + u64 tmp_addr = addr + HDMI_BASE; + + temp = __raw_readl(tmp_addr); + *value = temp; + return 0; +} + +int cdn_apb_write(unsigned int addr, unsigned int value) +{ + u64 tmp_addr = addr + HDMI_BASE; + + __raw_writel(value, tmp_addr); + return 0; +} +#endif diff --git a/drivers/video/nxp/hdp/util.c b/drivers/video/nxp/hdp/util.c new file mode 100644 index 00000000000..e74aaa509cc --- /dev/null +++ b/drivers/video/nxp/hdp/util.c @@ -0,0 +1,329 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * Copyright 2017-2018 NXP + * + ****************************************************************************** + * + * util.c + * + ****************************************************************************** + */ + +#include "util.h" +#include "API_General.h" +#include "externs.h" +#ifndef __UBOOT__ +#include +#endif +#include "apb_cfg.h" +#include "opcodes.h" +#ifndef __UBOOT__ +#include + +#endif +state_struct state; + +int cdn_bus_read(unsigned int addr, unsigned int *value) +{ + return state.bus_type ? + cdn_sapb_read(addr, value) : cdn_apb_read(addr, value); +} + +int cdn_bus_write(unsigned int addr, unsigned int value) +{ + return state.bus_type ? + cdn_sapb_write(addr, value) : cdn_apb_write(addr, value); +} + +void internal_itobe(int val, volatile unsigned char *dest, int bytes) +{ + int i; + for (i = bytes - 1; i >= 0; --i) { + dest[i] = (unsigned char)val; + val >>= 8; + } +} + +uint32_t internal_betoi(volatile uint8_t const *src, uint8_t bytes) +{ + uint32_t ret = 0; + int i; + + if (bytes > sizeof(ret)) { + printf("Warning. Read request for payload larger then supported.\n"); + bytes = sizeof(ret); + } + + for (i = 0; i < bytes; ++i) { + ret <<= 8; + ret |= (unsigned int)src[i]; + } + + return ret; +} + +unsigned int internal_mkmsg(volatile unsigned char *dest, int valno, ...) +{ + va_list vl; + unsigned int len = 0; + va_start(vl, valno); + len = internal_vmkmsg(dest, valno, vl); + va_end(vl); + return len; +} + +unsigned int internal_vmkmsg(volatile unsigned char *dest, int valno, + va_list vl) +{ + unsigned int len = 0; + int i; + for (i = 0; i < valno; ++i) { + int size = va_arg(vl, int); + if (size > 0) { + internal_itobe(va_arg(vl, int), dest, size); + dest += size; + len += size; + } else { + memcpy((void *)dest, va_arg(vl, void *), -size); + dest -= size; + len -= size; + } + } + return len; +} + +void internal_tx_mkfullmsg(unsigned char module, unsigned char opcode, + int valno, ...) +{ + va_list vl; + va_start(vl, valno); + internal_vtx_mkfullmsg(module, opcode, valno, vl); + va_end(vl); +} + +void internal_vtx_mkfullmsg(unsigned char module, unsigned char opcode, + int valno, va_list vl) +{ + unsigned int len = + internal_vmkmsg(state.txbuffer + INTERNAL_CMD_HEAD_SIZE, valno, vl); + internal_mbox_tx_enable(module, opcode, len); + state.txenable = 1; + state.running = 1; +} + +void internal_readmsg(int valno, ...) +{ + va_list vl; + va_start(vl, valno); + internal_vreadmsg(valno, vl); + va_end(vl); +} + +void internal_vreadmsg(int valno, va_list vl) +{ + uint8_t *src = state.rxbuffer + INTERNAL_CMD_HEAD_SIZE; + size_t i; + + for (i = 0; i < (size_t) valno; ++i) { + int size = va_arg(vl, int); + void *ptr = va_arg(vl, void *); + + if (!ptr) { + src += size; + } else if (!size) { + *((unsigned char **)ptr) = src; + } else if (size > 0) { + switch ((size_t) size) { + case sizeof(uint8_t): + *((uint8_t *)ptr) = internal_betoi(src, size); + break; + case sizeof(uint16_t): + *((uint16_t *)ptr) = internal_betoi(src, size); + break; + case 3: /* 3-byte value (e.g. DPCD address) + can be safely converted from BE.*/ + case sizeof(uint32_t): + *((uint32_t *)ptr) = internal_betoi(src, size); + break; + default: + printf("Warning. Unsupported variable size.\n"); + memcpy(ptr, src, size); + }; + + src += size; + } else { + memcpy(ptr, src, -size); + src -= size; + } + } +} + +INTERNAL_MBOX_STATUS mailbox_write(unsigned char val) +{ + INTERNAL_MBOX_STATUS ret; + unsigned int full; + if (cdn_bus_read(MAILBOX_FULL_ADDR << 2, &full)) { + ret.tx_status = CDN_TX_APB_ERROR; + return ret; + } + if (full) { + ret.tx_status = CDN_TX_FULL; + return ret; + } + if (cdn_bus_write(MAILBOX0_WR_DATA << 2, val)) { + ret.tx_status = CDN_TX_APB_ERROR; + return ret; + } + ret.tx_status = CDN_TX_WRITE; + return ret; +} + +INTERNAL_MBOX_STATUS mailbox_read(volatile unsigned char *val) +{ + INTERNAL_MBOX_STATUS ret; + unsigned int empty; + unsigned int rd; + if (cdn_bus_read(MAILBOX_EMPTY_ADDR << 2, &empty)) { + ret.rx_status = CDN_RX_APB_ERROR; + return ret; + } + if (empty) { + ret.rx_status = CDN_RX_EMPTY; + return ret; + } + if (cdn_bus_read(MAILBOX0_RD_DATA << 2, &rd)) { + ret.rx_status = CDN_RX_APB_ERROR; + return ret; + } + *val = (unsigned char)rd; + ret.rx_status = CDN_RX_READ; + return ret; +} + +INTERNAL_MBOX_STATUS internal_mbox_tx_process(void) +{ + unsigned int txcount = 0; + unsigned int length = + (unsigned int)state.txbuffer[2] << 8 | (unsigned int)state. + txbuffer[3]; + INTERNAL_MBOX_STATUS ret = {.txend = 0 }; + ret.tx_status = CDN_TX_NOTHING; + INTERNAL_MBOX_STATUS tx_ret; + if (!state.txenable) + return ret; + while ((tx_ret.tx_status = + mailbox_write(state.txbuffer[state.txi]).tx_status) == + CDN_TX_WRITE) { + txcount++; + if (++state.txi >= length + 4) { + state.txenable = 0; + state.txi = 0; + ret.txend = 1; + break; + } + } + if (txcount && tx_ret.tx_status == CDN_TX_FULL) + ret.tx_status = CDN_TX_WRITE; + else + ret.tx_status = tx_ret.tx_status; + return ret; +} + +INTERNAL_MBOX_STATUS internal_mbox_rx_process(void) +{ + unsigned int rxcount = 0; + INTERNAL_MBOX_STATUS ret = { 0, 0, 0, 0 }; + INTERNAL_MBOX_STATUS rx_ret; + while ((rx_ret.rx_status = + mailbox_read(state.rxbuffer + state.rxi).rx_status) == + CDN_RX_READ) { + rxcount++; + if (++state.rxi >= 4 + + ((unsigned int)state.rxbuffer[2] << 8 | + (unsigned int)state.rxbuffer[3])) { /* end of message */ + state.rxi = 0; + ret.rxend = 1; + state.rxenable = 0; + break; + } + } + ret.rx_status = rxcount ? CDN_RX_READ : CDN_RX_EMPTY; + return ret; +} + +unsigned int internal_apb_available(void) +{ + return !(state.rxenable || state.txenable); +} + +void internal_mbox_tx_enable(unsigned char module, unsigned char opcode, + unsigned short length) +{ + state.txbuffer[0] = opcode; + state.txbuffer[1] = module; + state.txbuffer[2] = (unsigned char)(length >> 8); + state.txbuffer[3] = (unsigned char)length; + state.txenable = 1; +} + +CDN_API_STATUS internal_test_rx_head(unsigned char module, unsigned char opcode) +{ + if (opcode != state.rxbuffer[0]) + return CDN_BAD_OPCODE; + if (module != state.rxbuffer[1]) + return CDN_BAD_MODULE; + return CDN_OK; +} + +CDN_API_STATUS internal_test_rx_head_match(void) +{ + return internal_test_rx_head(state.txbuffer[1], state.txbuffer[0]); +} + +void print_fw_ver(void) +{ + unsigned short ver, verlib; + cdn_api_general_getcurversion(&ver, &verlib); + printf("FIRMWARE VERSION: %d, LIB VERSION: %d\n", ver, verlib); +} + +unsigned short internal_get_msg_len(void) +{ + return ((unsigned short)state.rxbuffer[2] << 8) | (unsigned short)state. + rxbuffer[3]; +} diff --git a/drivers/video/nxp/hdp/util.h b/drivers/video/nxp/hdp/util.h new file mode 100644 index 00000000000..6ad0b489abb --- /dev/null +++ b/drivers/video/nxp/hdp/util.h @@ -0,0 +1,256 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + * + ****************************************************************************** + * + * util.h + * + ****************************************************************************** + */ + +#ifndef UTIL_H_ +#define UTIL_H_ + +#include "API_General.h" +#ifndef __UBOOT__ +#include +#include +#else +#include +#endif +/** + * \addtogroup UTILS + * \{ + */ +#define INTERNAL_CMD_HEAD_SIZE 4 + +/** + * \brief expands to blocking function body + * \param x - function call + */ +#define internal_block_function(x) \ +do { \ + CDN_API_STATUS ret; \ + do { \ + ret = x; \ + } while (ret == CDN_BSY || ret == CDN_STARTED); \ + return ret; \ +} while (0) + +/** + * \brief write message and write response (if any), non-blocking way. + * Also sets state.running = 0 + */ +#define INTERNAL_PROCESS_MESSAGES \ +do { \ + if (state.txenable && !internal_mbox_tx_process().txend) \ + return CDN_BSY; \ + if (state.rxenable && !internal_mbox_rx_process().rxend) \ + return CDN_BSY; \ + state.running = 0; \ +} while (0) + +#define internal_opcode_ok_or_return(module, opcode) \ +do { \ + CDN_API_STATUS ret = internal_test_rx_head(module, opcode); \ + if (ret != CDN_OK) \ + return ret; \ +} while (0) + +#define internal_opcode_match_or_return() \ +do { \ + CDN_API_STATUS ret = internal_test_rx_head_match(); \ + if (ret != CDN_OK) \ + return ret; \ +} while (0) + +/* + * macro for simple tx only command, command format as in mkfullmsg + * (with count) + */ +#define internal_macro_command_tx(module, opcode, bustype, command...) \ +do { \ + if (!state.running) { \ + internal_tx_mkfullmsg(module, opcode, command); \ + state.bus_type = bustype; \ + return CDN_STARTED; \ + } \ + INTERNAL_PROCESS_MESSAGES; \ +} while (0) + +/* + * macro for command with response with matching opcode, command format as in + * mkfullmsg (with count) + */ +#define internal_macro_command_txrx(module, opcode, bustype, command...) \ +do { \ + if (!state.running) { \ + internal_tx_mkfullmsg(module, opcode, command); \ + state.bus_type = bustype; \ + state.rxenable = 1; \ + return CDN_STARTED; \ + } \ + INTERNAL_PROCESS_MESSAGES; \ + internal_opcode_match_or_return(); \ +} while (0) + +typedef struct { + /** apb write status */ + enum tx_status_enum { + /** one or more bytes written */ + CDN_TX_WRITE = 0, + /** nothing to write */ + CDN_TX_NOTHING = 1, + /** mailbox full, 0 bytes written */ + CDN_TX_FULL = 2, + /** APB error while writing */ + CDN_TX_APB_ERROR = 3 + } tx_status:3; + /** apb read status */ + enum rx_status_enum { + /** 1 or more bytes read */ + CDN_RX_READ = 0, + /** mailbox empty, 0 bytes read */ + CDN_RX_EMPTY = 1, + /** apb error while reading */ + CDN_RX_APB_ERROR = 2 + } rx_status:2; + /** indicates end of currenly recived message */ + unsigned char rxend:1; + /** end of tx message reached */ + unsigned char txend:1; +} INTERNAL_MBOX_STATUS; + +/** + * \brief put val into dest in big endian format + * \param val - value to put + * \param dest - place to put value + * \param bytes - true size of val in bytes. for example if + * bytes = 2 val is treated as short int + */ +void internal_itobe(int val, volatile unsigned char *dest, int bytes); + +/** + * \brief read big endian value from src and return it + * \param src - source to read from + * \param bytes - size of read value + * \return result + */ +u32 internal_betoi(volatile u8 const *src, u8 bytes); + +/** + * \brief create message from size and value pairs; also sets + * state.running and state.txEnable + * \param dest - pointer to write message to + * \param valNo - number of values to write + * \param ... - pairs of size and value, each value is written + * after another. if size is positive value, value is + * written with #internal_itobe, if size is negative, + * value is treated as src pointer for memcpy + * + * example: + * + * unsigned short x = 0xAABB; + * + * internal_mkmsg(dest, 3, 1, 1, 2, 3, -2, &x); + * + * will write 01 00 03 AA BB to dest + */ +unsigned int internal_mkmsg(volatile unsigned char *dest, int valno, ...); +unsigned int internal_vmkmsg(volatile unsigned char *dest, int valno, + va_list vl); + +/** + * \brief setup message header in txBuffer, set txEnable = 1 + */ +void internal_mbox_tx_enable(unsigned char module, unsigned char opcode, + unsigned short length); + +/** + * \brief write from txBuffer to mailbox until full or end of message. + * + * when txEnable == 0 writes nothing + * when write reaches end of message set txEnable = 0 + */ + +/** + * \brief combination of #internal_mkmsg and #internal_mbox_tx_enable + * + * #internal_mkmsg dest and #internal_mbox_tx_enable length are determined + * automatically this function also sets state.txEnable = 1 and + * state.running + */ +void internal_tx_mkfullmsg(unsigned char module, unsigned char opcode, + int valno, ...); +void internal_vtx_mkfullmsg(unsigned char module, unsigned char opcode, + int valno, va_list vl); + +/** + * \brief read from state.txBuffer and store results in specified pointers + * \param valNo - numbero of values to read + * \param ... - pairs of size and ptr + * + * this function is similar to #internal_mkmsg - + * + * when size is positive read value using #internal_betoi + * when size is negative mempcy from txBuffer to ptr -size bytes + * when size is 0 write to ptr address of current position in rxbuffer + * when ptr is NULL ignore size bytes (if size is negative this + * will rewind buffer) + */ +void internal_readmsg(int valno, ...); +void internal_vreadmsg(int valno, va_list vl); + +INTERNAL_MBOX_STATUS internal_mbox_tx_process(void); +/** + * \brief read to rxBuffer from mailbox until empty or end of message + * + * when rxEnable == 0 reads nothing + * when end of message reached sets rxEnable = 0 + */ +INTERNAL_MBOX_STATUS internal_mbox_rx_process(void); + +/** + * \brief check if apb is available + * \return !(rxEnable && txEable) + */ +unsigned int internal_apb_available(void); + +/** + * \brief test if parameters match module and opcode in rxBuffer + * \return CDN_OK or CDN_BAD_OPCODE or CDN_BAD_MODULE + */ +CDN_API_STATUS internal_test_rx_head(unsigned char module, + unsigned char opcode); + +CDN_API_STATUS internal_test_rx_head_match(void); + +/** + * \brief print current fw and lib version + */ +void print_fw_ver(void); + +typedef struct { + unsigned char txbuffer[1024]; + unsigned char rxbuffer[1024]; + unsigned int txi; /* iterators */ + unsigned int rxi; + unsigned char txenable; /*data readt to send*/ + unsigned char rxenable; + unsigned char running; + CDN_BUS_TYPE bus_type; + unsigned int tmp; +} state_struct; + +extern state_struct state; +extern int cdn_bus_read(unsigned int addr, unsigned int *value); +extern int cdn_bus_write(unsigned int addr, unsigned int value); +unsigned short internal_get_msg_len(void); + +#endif diff --git a/drivers/video/nxp/hdp/vic_table.c b/drivers/video/nxp/hdp/vic_table.c new file mode 100644 index 00000000000..c4984008189 --- /dev/null +++ b/drivers/video/nxp/hdp/vic_table.c @@ -0,0 +1,68 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * vic_table.c + * + ****************************************************************************** + */ +#include "vic_table.h" + +const unsigned int vic_table[VIC_MODE_COUNT][27] = { + {858, 720, 138, 62, 16, 60, 525, 480, 45, 6, 9, 30, 59, 27000, + PROGRESSIVE, ACTIVE_LOW, ACTIVE_LOW, 1, 65535, 1, 46, 65535, 65535, 3, + 8, 0}, + {1650, 1280, 370, 40, 110, 220, 750, 720, 30, 5, 5, 20, 60, 74250, + PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 1, 65535, 1, 31, 65535, 65535, + 4, 8, 0}, + {2200, 1920, 280, 44, 88, 148, 1125, 1080, 45, 5, 4, + 36, 60, 148500, PROGRESSIVE, ACTIVE_HIGH, + ACTIVE_HIGH, 1, 65535, 1, 46, 65535, 65535, 16, 8, 0}, + {4400, 3840, 560, 88, 176, 296, 2250, 2160, 90, 10, 8, 72, 60, + 594000, PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 4, 266, 262, 22, 525, + 285, 97, 8, 0}, + {4400, 3840, 560, 88, 176, 296, 2250, 2160, 90, 10, 8, 72, 30, + 297000, PROGRESSIVE, ACTIVE_HIGH, ACTIVE_HIGH, 4, 266, 262, 22, 525, + 285, 95, 8, 0}, +}; diff --git a/drivers/video/nxp/hdp/vic_table.h b/drivers/video/nxp/hdp/vic_table.h new file mode 100644 index 00000000000..dce88347b7e --- /dev/null +++ b/drivers/video/nxp/hdp/vic_table.h @@ -0,0 +1,140 @@ +/****************************************************************************** + * + * Copyright (C) 2016-2017 Cadence Design Systems, Inc. + * All rights reserved worldwide. + * + * Copyright 2017-2018 NXP + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software without + * specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF + * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. THE SOFTWARE IS PROVIDED "AS IS", + * WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED + * TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE + * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + ****************************************************************************** + * + * This file was auto-generated. Do not edit it manually. + * + ****************************************************************************** + * + * vic_table.h + * + ****************************************************************************** + */ + +#ifndef VIC_TABLE_H_ +#define VIC_TABLE_H_ + +#define PROGRESSIVE 0 +#define INTERLACED 1 + +#define ACTIVE_LOW 0 +#define ACTIVE_HIGH 1 + +typedef enum { + H_TOTAL, + H_ACTIVE, + H_BLANK, + HSYNC, + FRONT_PORCH, + BACK_PORCH, + /* H_FREQ_KHZ, */ + V_TOTAL, + V_ACTIVE, + V_BLANK, + VSYNC, + TYPE_EOF, + SOF, + V_FREQ_HZ, + PIXEL_FREQ_KHZ, + I_P, + HSYNC_POL, + VSYNC_POL, + START_OF_F0, + START_OF_F1, + VSYNC_START_INTERLACED_F0, + VSYNC_END_INTERLACED_F0, + VSYNC_START_INTERLACED_F1, + VSYNC_END_INTERLACED_F1, + VIC, + VIC_R3_0, + VIC_PR, +} MSA_PARAM; + +typedef enum { + NUM_OF_LANES_1 = 1, + NUM_OF_LANES_2 = 2, + NUM_OF_LANES_4 = 4, +} VIC_NUM_OF_LANES; + +typedef enum { + RATE_1_6 = 162, + RATE_2_7 = 270, + RATE_5_4 = 540, + RATE_8_1 = 810, +} VIC_SYMBOL_RATE; + +typedef enum { + PXL_RGB = 0x1, + YCBCR_4_4_4 = 0x2, + YCBCR_4_2_2 = 0x4, + YCBCR_4_2_0 = 0x8, + Y_ONLY = 0x10, +} VIC_PXL_ENCODING_FORMAT; + +typedef enum { + BCS_6 = 0x1, + BCS_8 = 0x2, + BCS_10 = 0x4, + BCS_12 = 0x8, + BCS_16 = 0x10, +} VIC_COLOR_DEPTH; + +typedef enum { + STEREO_VIDEO_LEFT = 0x0, + STEREO_VIDEO_RIGHT = 0x1, +} STEREO_VIDEO_ATTR; + +typedef enum { + BT_601 = 0x0, + BT_709 = 0x1, +} BT_TYPE; + +typedef enum { + VIC_MODE_3_59_94Hz, + VIC_MODE_4_60Hz, + VIC_MODE_16_60Hz, + VIC_MODE_97_60Hz, + VIC_MODE_95_30Hz, + VIC_MODE_COUNT +} VIC_MODES; + +extern const unsigned int vic_table[VIC_MODE_COUNT][27]; + +#endif diff --git a/drivers/video/nxp/imx/Kconfig b/drivers/video/nxp/imx/Kconfig new file mode 100644 index 00000000000..c02014826f8 --- /dev/null +++ b/drivers/video/nxp/imx/Kconfig @@ -0,0 +1,98 @@ + +config VIDEO_IPUV3 + bool "i.MX IPUv3 Core video support" + depends on DM_VIDEO && (MX5 || MX6) + help + This enables framebuffer driver for i.MX processors working + on the IPUv3(Image Processing Unit) internal graphic processor. + +config VIDEO_IMXDPUV1 + bool "i.MX DPU V1 display support" + default n + depends on IMX8 && DM_VIDEO + select VIDEO_LINK + help + Support for IMXDPU V1 display controller for i.MX8 processors. + +config VIDEO_IMX8_LVDS + bool "i.MX8 LDVS bridge support" + default n + depends on IMX8 && DM_VIDEO + select DISPLAY + select VIDEO_LINK + help + Support for i.MX8 LDVS bridge controller for i.MX8 processors. + +config VIDEO_IMX_HDP_LOAD + bool "i.MX8 HDMI/DP firmware loading" + default n + depends on IMX8QM + select VIDEO_NXP_HDP + help + Support for HDMI/DP firmware loading for i.MX8QM processors. The + firmware is copied from system memory to the HDMI/DP IRAM and + DRAM memory. + +config VIDEO_IMX8M_DCSS + bool "i.MX8M DCSS controller" + default n + depends on IMX8M && DM_VIDEO + select VIDEO_LINK + help + Support for DCSS on i.MX8MQ processors. + +config VIDEO_IMX8M_HDMI + bool "i.MX8M HDMI Splash screen" + default n + depends on IMX8M && DM_VIDEO + select DISPLAY + select VIDEO_LINK + select VIDEO_NXP_HDP + help + Support for HDMI on i.MX8MQ processors. + +config VIDEO_SEC_MIPI_DSI + bool + select VIDEO_MIPI_DSI + help + Enables the common driver code for the Samsung + MIPI DSI block found in SoCs from various vendors. + As this does not provide any functionality by itself (but + rather requires a SoC-specific glue driver to call it), it + can not be enabled from the configuration menu. + +config VIDEO_NW_MIPI_DSI + bool + select VIDEO_MIPI_DSI + help + Enables the common driver code for the Northwest + MIPI DSI block found in SoCs from various vendors. + As this does not provide any functionality by itself (but + rather requires a SoC-specific glue driver to call it), it + can not be enabled from the configuration menu. + +config VIDEO_IMX_SEC_DSI + bool "Enable IMX SEC DSI video support" + select VIDEO_BRIDGE + select VIDEO_SEC_MIPI_DSI + select VIDEO_LINK + help + This option enables support DSI internal bridge which can be used on + devices which have DSI devices connected. + +config VIDEO_IMX_NW_DSI + bool "Enable IMX Northwest DSI video support" + select VIDEO_BRIDGE + select VIDEO_NW_MIPI_DSI + select VIDEO_LINK + help + This option enables support DSI internal bridge which can be used on + devices which have DSI devices connected. + +config VIDEO_IMX_LCDIFV3 + bool "i.MX LCDIFv3 support" + depends on DM_VIDEO && IMX8MP + select VIDEO_LINK + help + Support for i.MX8MP LCDIFv3 controller. + diff --git a/drivers/video/nxp/imx/Makefile b/drivers/video/nxp/imx/Makefile new file mode 100644 index 00000000000..b9e1695a65b --- /dev/null +++ b/drivers/video/nxp/imx/Makefile @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o +obj-$(CONFIG_VIDEO_IMXDPUV1) += imxdpuv1.o imx8_dc.o +obj-$(CONFIG_VIDEO_IMX8_LVDS) += imx8_lvds.o +obj-$(CONFIG_VIDEO_IMX8M_DCSS) += imx8m_dcss.o +obj-$(CONFIG_VIDEO_SEC_MIPI_DSI) += sec_mipi_dsim.o +obj-$(CONFIG_VIDEO_IMX_SEC_DSI) += sec_dsim_imx.o +obj-$(CONFIG_VIDEO_IMX_LCDIFV3) += imx_lcdifv3.o +obj-$(CONFIG_VIDEO_NW_MIPI_DSI) += mipi_dsi_northwest.o +obj-$(CONFIG_VIDEO_IMX_NW_DSI) += nw_dsi_imx.o +obj-y += hdmi/ diff --git a/drivers/video/nxp/imx/hdmi/Makefile b/drivers/video/nxp/imx/hdmi/Makefile new file mode 100644 index 00000000000..40942da3a40 --- /dev/null +++ b/drivers/video/nxp/imx/hdmi/Makefile @@ -0,0 +1,8 @@ +# +# Copyright 2017-2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_VIDEO_IMX_HDP_LOAD) += hdp_load.o hdprx_load.o +obj-$(CONFIG_VIDEO_IMX8M_HDMI) += imx8m_hdmi.o diff --git a/drivers/video/nxp/imx/hdmi/hdp.c b/drivers/video/nxp/imx/hdmi/hdp.c new file mode 100644 index 00000000000..d84716ac63d --- /dev/null +++ b/drivers/video/nxp/imx/hdmi/hdp.c @@ -0,0 +1,46 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int do_hdp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) + return 0; + + if (strncmp(argv[1], "colorbar", 8) == 0) { + GraphicDevice *gdev; + struct video_mode_settings *vm; + + gdev = imx8m_get_gd(); + vm = imx8m_get_gmode(); + imx8m_show_gmode(); + + imx8m_create_color_bar( + (void *)((uint64_t)gdev->frameAdrs), + vm); + printf("colorbar test\n"); + } else if (strncmp(argv[1], "stop", 4) == 0) { + imx8_hdmi_disable(); + printf("stopping hdmi\n"); + } else { + printf("test error argc %d\n", argc); + } + + return 0; +} +/***************************************************/ + +U_BOOT_CMD( + hdp, CONFIG_SYS_MAXARGS, 1, do_hdp, + "hdmi/dp display test commands", + "[] ...\n" + "colorbar - display a colorbar pattern\n" + ); diff --git a/drivers/video/nxp/imx/hdmi/hdp_load.c b/drivers/video/nxp/imx/hdmi/hdp_load.c new file mode 100644 index 00000000000..be6b118e39f --- /dev/null +++ b/drivers/video/nxp/imx/hdmi/hdp_load.c @@ -0,0 +1,118 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "API_General.h" +#include "scfw_utils.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ON 1 +#define OFF 0 + +static void display_set_power(int onoff) +{ + SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_DC_0, onoff); + SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_HDMI, onoff); +} + +static void display_set_clocks(void) +{ + const sc_pm_clock_rate_t pll = 800000000; + const sc_pm_clock_rate_t hdmi_core_clock = pll / 4; /* 200 Mhz */ + const sc_pm_clock_rate_t hdmi_bus_clock = pll / 8; /* 100 Mhz */ + + SC_PM_SET_RESOURCE_POWER_MODE(-1, + SC_R_HDMI_PLL_0, SC_PM_PW_MODE_OFF); + SC_PM_SET_CLOCK_RATE(-1, + SC_R_HDMI_PLL_0, SC_PM_CLK_PLL, pll); + SC_PM_SET_RESOURCE_POWER_MODE(-1, + SC_R_HDMI_PLL_0, SC_PM_PW_MODE_ON); + + /* HDMI DI Bus Clock */ + SC_PM_SET_CLOCK_RATE(-1, + SC_R_HDMI, SC_PM_CLK_MISC4, hdmi_bus_clock); + /* HDMI DI Core Clock */ + SC_PM_SET_CLOCK_RATE(-1, + SC_R_HDMI, SC_PM_CLK_MISC2, hdmi_core_clock); +} + +static void display_enable_clocks(int enable) +{ + SC_PM_CLOCK_ENABLE(-1, SC_R_HDMI_PLL_0, SC_PM_CLK_PLL, enable); + SC_PM_CLOCK_ENABLE(-1, SC_R_HDMI, SC_PM_CLK_MISC2, enable); + SC_PM_CLOCK_ENABLE(-1, SC_R_HDMI, SC_PM_CLK_MISC4, enable); + if (enable == OFF) + SC_PM_SET_RESOURCE_POWER_MODE(-1, + SC_R_HDMI_PLL_0, SC_PM_PW_MODE_OFF); +} + +int do_hdp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) + return 0; + + if (strncmp(argv[1], "tracescfw", 9) == 0) { + g_debug_scfw = 1; + printf("Enabled SCFW API tracing\n"); + } else if (strncmp(argv[1], "load", 4) == 0) { + unsigned long address = 0; + unsigned long offset = 0x2000; + const int iram_size = 0x10000; + const int dram_size = 0x8000; + const char *s; + + if (argc > 2) { + address = simple_strtoul(argv[2], NULL, 0); + if (argc > 3) + offset = simple_strtoul(argv[3], NULL, 0); + } else { + printf("Missing address\n"); + } + + printf("Loading hdp firmware from 0x%016lx offset 0x%016lx\n", + address, offset); + display_set_power(SC_PM_PW_MODE_ON); + display_set_clocks(); + display_enable_clocks(ON); + cdn_api_loadfirmware((unsigned char *)(address + offset), + iram_size, + (unsigned char *)(address + offset + + iram_size), + dram_size); + + s = env_get("hdp_authenticate_fw"); + if (s && !strcmp(s, "yes")) + SC_MISC_AUTH(-1, SC_SECO_AUTH_HDMI_TX_FW, 0); + + display_enable_clocks(OFF); + printf("Loading hdp firmware Complete\n"); + + /* do not turn off hdmi power or firmware load will be lost */ + } else { + printf("test error argc %d\n", argc); + } + + return 0; +} + +/***************************************************/ +U_BOOT_CMD( + hdp, CONFIG_SYS_MAXARGS, 1, do_hdp, + "load hdmi firmware ", + "[] ...\n" + "hdpload [address] []\n" + " address - address where the binary image starts\n" + " - IRAM offset in the binary image (8192 default)\n" + "\n" + " if \"hdp_authenticate_fw\" is set to \"yes\", the seco\n" + " will authenticate the firmware and load HDCP keys.\n" + "\n" + "tracescfw - Trace SCFW API calls for video commands\n" + ); diff --git a/drivers/video/nxp/imx/hdmi/hdprx_load.c b/drivers/video/nxp/imx/hdmi/hdprx_load.c new file mode 100644 index 00000000000..a1b332ff467 --- /dev/null +++ b/drivers/video/nxp/imx/hdmi/hdprx_load.c @@ -0,0 +1,83 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "API_General.h" +#include "scfw_utils.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define ON 1 +#define OFF 0 + +static void hdmi_rx_set_power(int onoff) +{ + SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_ISI_CH0, onoff); + SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_HDMI_RX, onoff); + SC_PM_SET_RESOURCE_POWER_MODE(-1, SC_R_HDMI_RX_BYPASS, onoff); +} + +int do_hdprx(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) + return 0; + + if (strncmp(argv[1], "tracescfw", 9) == 0) { + g_debug_scfw = 1; + printf("Enabled SCFW API tracing\n"); + } else if (strncmp(argv[1], "load", 4) == 0) { + unsigned long address = 0; + unsigned long offset = 0x2000; + const int iram_size = 0x10000; + const int dram_size = 0x8000; + const char *s; + + if (argc > 2) { + address = simple_strtoul(argv[2], NULL, 0); + if (argc > 3) + offset = simple_strtoul(argv[3], NULL, 0); + } else { + printf("Missing address\n"); + } + + printf("Loading hdprx firmware from 0x%016lx offset 0x%016lx\n", + address, offset); + hdmi_rx_set_power(SC_PM_PW_MODE_ON); + hdp_rx_loadfirmware((unsigned char *)(address + offset), + iram_size, + (unsigned char *)(address + offset + + iram_size), + dram_size); + + s = env_get("hdprx_authenticate_fw"); + if (s && !strcmp(s, "yes")) + SC_MISC_AUTH(-1, SC_SECO_AUTH_HDMI_RX_FW, 0); + printf("Loading hdp rx firmware Complete\n"); + /* do not turn off hdmi power or firmware load will be lost */ + } else { + printf("test error argc %d\n", argc); + } + + return 0; +} + +/***************************************************/ +U_BOOT_CMD( + hdprx, CONFIG_SYS_MAXARGS, 1, do_hdprx, + "load hdmi rx firmware ", + "[] ...\n" + "hdpload [address] []\n" + " address - address where the binary image starts\n" + " - IRAM offset in the binary image (8192 default)\n" + "\n" + " if \"hdprx_authenticate_fw\" is set to \"yes\", the seco\n" + " will authenticate the firmware and load HDCP keys.\n" + "\n" + "tracescfw - Trace SCFW API calls for video commands\n" + ); diff --git a/drivers/video/nxp/imx/hdmi/imx8m_hdmi.c b/drivers/video/nxp/imx/hdmi/imx8m_hdmi.c new file mode 100644 index 00000000000..5af6036d402 --- /dev/null +++ b/drivers/video/nxp/imx/hdmi/imx8m_hdmi.c @@ -0,0 +1,312 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "API_General.h" +#include "vic_table.h" +#include "API_HDMITX.h" +#include "apb_cfg.h" +#include "externs.h" +#include "API_AVI.h" +#include "address.h" +#include "source_car.h" +#include "source_phy.h" +#include "API_AFE.h" +#include "source_vif.h" +#include "general_handler.h" +#include "mhl_hdtx_top.h" +#include "API_AFE_t28hpc_hdmitx.h" + +struct imx8m_hdmi_priv { + fdt_addr_t base; + struct display_timing timings; + int vic; + bool hpol; + bool vpol; +}; + +static int imx8m_hdmi_set_vic_mode(int vic, + struct imx8m_hdmi_priv *priv) +{ + uint32_t pixel_clock_kHz; + uint32_t frame_rate_Hz; + uint32_t frame_rate_frac_Hz; + uint32_t cea_vic; + char iflag; + + if (vic >= VIC_MODE_COUNT) { + debug("%s(): unsupported VIC\n", __func__); + return -1; + } + + priv->timings.hfront_porch.typ = vic_table[vic][FRONT_PORCH]; + priv->timings.hback_porch.typ = vic_table[vic][BACK_PORCH]; + priv->timings.hsync_len.typ = vic_table[vic][HSYNC]; + priv->timings.vfront_porch.typ = vic_table[vic][TYPE_EOF]; + priv->timings.vback_porch.typ = vic_table[vic][SOF]; + priv->timings.vsync_len.typ = vic_table[vic][VSYNC]; + priv->timings.hactive.typ = vic_table[vic][H_ACTIVE]; + priv->timings.vactive.typ = vic_table[vic][V_ACTIVE]; + + priv->hpol = vic_table[vic][HSYNC_POL] != 0; + priv->vpol = vic_table[vic][VSYNC_POL] != 0; + + cea_vic = vic_table[vic][VIC]; + if (vic_table[vic][I_P] != 0) + iflag = 'i'; + else + iflag = 'p'; + pixel_clock_kHz = vic_table[vic][PIXEL_FREQ_KHZ]; + frame_rate_Hz = vic_table[vic][V_FREQ_HZ] * 1000; + frame_rate_frac_Hz = frame_rate_Hz % 1000; + frame_rate_Hz /= 1000; + + priv->timings.pixelclock.typ = pixel_clock_kHz * 1000; + + debug("Cadence VIC %3d, CEA VIC %3d: %4d x %4d %c @ %3d.%03d [%6d kHz] Vpol=%d Hpol=%d\n", + vic, cea_vic, priv->timings.hactive.typ, priv->timings.vactive.typ, iflag, frame_rate_Hz, + frame_rate_frac_Hz, pixel_clock_kHz, priv->vpol, priv->hpol); + + debug(" mode timing fp sync bp h:%3d %3d %3d v:%3d %3d %3d\n", + priv->timings.hfront_porch.typ, priv->timings.hsync_len.typ, priv->timings.hback_porch.typ, + priv->timings.vfront_porch.typ, priv->timings.vsync_len.typ, priv->timings.vback_porch.typ); + + return 0; +} + +static int imx8m_hdmi_init(int vic, + int encoding, + int color_depth, + bool pixel_clk_from_phy) +{ + int ret; + uint32_t character_freq_khz; + + uint8_t echo_msg[] = "echo test"; + uint8_t echo_resp[sizeof(echo_msg) + 1]; + + /*================================================================== */ + /* Parameterization: */ + /*================================================================== */ + + /* VIC Mode - index from vic_table (see API_SRC/vic_table.c) */ + VIC_MODES vic_mode = vic; + + /* Pixel Encodeing Format */ + /* PXL_RGB = 0x1, */ + /* YCBCR_4_4_4 = 0x2, */ + /* YCBCR_4_2_2 = 0x4, */ + /* YCBCR_4_2_0 = 0x8, */ + /* Y_ONLY = 0x10, */ + VIC_PXL_ENCODING_FORMAT format = encoding; + /*VIC_PXL_ENCODING_FORMAT format = 1; */ + + /* B/W Balance Type: 0 no data, 1 IT601, 2 ITU709 */ + BT_TYPE bw_type = 0; + + /* bpp (bits per subpixel) - 8 24bpp, 10 30bpp, 12 36bpp, 16 48bpp */ + uint8_t bps = color_depth; + + /* Set HDMI TX Mode */ + /* Mode = 0 - DVI, 1 - HDMI1.4, 2 HDMI 2.0 */ + HDMI_TX_MAIL_HANDLER_PROTOCOL_TYPE ptype = 1; + + if (vic_mode == VIC_MODE_97_60Hz) + ptype = 2; + + /*================================================================== */ + /* Parameterization done */ + /*================================================================== */ + cdn_api_init(); + debug("CDN_API_Init completed\n"); + + ret = cdn_api_checkalive(); + debug("CDN_API_CheckAlive returned ret = %d\n", ret); + + if (ret) + return -EPERM; + + ret = cdn_api_general_test_echo_ext_blocking(echo_msg, + echo_resp, + sizeof(echo_msg), + CDN_BUS_TYPE_APB); + debug("_General_Test_Echo_Ext_blocking - (ret = %d echo_resp = %s)\n", + ret, echo_resp); + + /* Configure PHY */ + character_freq_khz = phy_cfg_t28hpc(4, vic_mode, bps, + format, pixel_clk_from_phy); + debug("phy_cfg_t28hpc (character_freq_mhz = %d)\n", + character_freq_khz); + + hdmi_tx_t28hpc_power_config_seq(4); + + /* Set the lane swapping */ + ret = cdn_api_general_write_register_blocking + (ADDR_SOURCD_PHY + (LANES_CONFIG << 2), + F_SOURCE_PHY_LANE0_SWAP(0) | F_SOURCE_PHY_LANE1_SWAP(1) | + F_SOURCE_PHY_LANE2_SWAP(2) | F_SOURCE_PHY_LANE3_SWAP(3) | + F_SOURCE_PHY_COMB_BYPASS(0) | F_SOURCE_PHY_20_10(1)); + + debug("_General_Write_Register_blocking LANES_CONFIG ret = %d\n", ret); + + ret = CDN_API_HDMITX_Init_blocking(); + debug("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret); + + ret = CDN_API_HDMITX_Init_blocking(); + debug("CDN_API_STATUS CDN_API_HDMITX_Init_blocking ret = %d\n", ret); + + ret = CDN_API_HDMITX_Set_Mode_blocking(ptype, character_freq_khz); + debug("CDN_API_HDMITX_Set_Mode_blocking ret = %d\n", ret); + + ret = cdn_api_set_avi(vic_mode, format, bw_type); + debug("cdn_api_set_avi ret = %d\n", ret); + + ret = CDN_API_HDMITX_SetVic_blocking(vic_mode, bps, format); + debug("CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret); + + + udelay(20000); + + return 0; +} + +static int imx8m_hdmi_update_timings(struct udevice *dev) +{ + struct imx8m_hdmi_priv *priv = dev_get_priv(dev); + + /* map the resolution to a VIC index in the vic table*/ + if ((priv->timings.hactive.typ == 1280) && (priv->timings.vactive.typ == 720)) + priv->vic = 1; /* 720p60 */ + else if ((priv->timings.hactive.typ == 1920) && (priv->timings.vactive.typ == 1080)) + priv->vic = 2; /* 1080p60 */ + else if ((priv->timings.hactive.typ == 3840) && (priv->timings.vactive.typ == 2160)) + priv->vic = 3; /* 2160p60 */ + else + priv->vic = 0; /* 480p60 */ + + return imx8m_hdmi_set_vic_mode(priv->vic, priv); +} + +static void imx8m_hdmi_disable(void) +{ + int ret; + GENERAL_READ_REGISTER_RESPONSE resp; + + resp.val = 0; + ret = cdn_api_general_read_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + &resp); + if (ret != CDN_OK) { + printf("%s(): dn_api_general_read_register_blocking failed\n", + __func__); + } + + resp.val &= ~F_DATA_EN(1); /* disable HDMI */ + + ret = cdn_api_general_write_register_blocking(ADDR_SOURCE_MHL_HD + + (HDTX_CONTROLLER << 2), + resp.val); + if (ret != CDN_OK) { + printf("%s(): dn_api_general_write_register_blocking failed\n", + __func__); + return; + } +} + +static int imx8m_hdmi_read_timing(struct udevice *dev, struct display_timing *timing) +{ + struct imx8m_hdmi_priv *priv = dev_get_priv(dev); + + if (timing) { + memcpy(timing, &priv->timings, sizeof(struct display_timing)); + + if (priv->hpol) + timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH; + + if (priv->vpol) + timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH; + + return 0; + } + + return -EINVAL; +} + +static int imx8m_hdmi_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing) +{ + struct imx8m_hdmi_priv *priv = dev_get_priv(dev); + int ret; + + ret = imx8m_hdmi_init(priv->vic, 1, 8, true); + if (ret) { + printf("HDMI enable failed, ret %d!\n", ret); + return ret; + } + + return 0; +} + +static int imx8m_hdmi_probe(struct udevice *dev) +{ + struct imx8m_hdmi_priv *priv = dev_get_priv(dev); + int ret; + + printf("%s\n", __func__); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = video_link_get_display_timings(&priv->timings); + if (ret) { + printf("decode display timing error %d\n", ret); + return ret; + } + + imx8m_hdmi_update_timings(dev); + + return 0; +} + +static int imx8m_hdmi_remove(struct udevice *dev) +{ + imx8m_hdmi_disable(); + + return 0; +} + +struct dm_display_ops imx8m_hdmi_ops = { + .read_timing = imx8m_hdmi_read_timing, + .enable = imx8m_hdmi_enable, +}; + +static const struct udevice_id imx8m_hdmi_ids[] = { + { .compatible = "fsl,imx8mq-hdmi" }, + { } +}; + +U_BOOT_DRIVER( imx8m_hdmi) = { + .name = " imx8m_hdmi", + .id = UCLASS_DISPLAY, + .of_match = imx8m_hdmi_ids, + .bind = dm_scan_fdt_dev, + .probe = imx8m_hdmi_probe, + .remove = imx8m_hdmi_remove, + .ops = & imx8m_hdmi_ops, + .priv_auto = sizeof(struct imx8m_hdmi_priv), +}; diff --git a/drivers/video/nxp/imx/hdmi/scfw_utils.h b/drivers/video/nxp/imx/hdmi/scfw_utils.h new file mode 100644 index 00000000000..bf11872ab17 --- /dev/null +++ b/drivers/video/nxp/imx/hdmi/scfw_utils.h @@ -0,0 +1,102 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _SCFW_UTILS_H_ +#define _SCFW_UTILS_H_ + +#include +#include + +static int g_debug_scfw; /* set to one to turn on SCFW API tracing */ + +#define SC_PM_SET_CLOCK_PARENT(__ipcHndl__, __res__, __clk__, __parent__) \ +do { \ + char _res_str[] = #__res__;\ + char _clk_str[] = #__clk__;\ + sc_err_t _ret;\ + if (g_debug_scfw) \ + printf("(%4d) sc_pm_set_clock_parent %s:%s -> %d\n",\ + __LINE__, _res_str, _clk_str, __parent__);\ + _ret = sc_pm_set_clock_parent(__ipcHndl__,\ + __res__, __clk__, __parent__);\ + if (_ret != SC_ERR_NONE) \ + printf("(%d)>> sc_pm_set_clock_parent failed! %s:%s -> %d (error = %d)\n",\ + __LINE__, _res_str, _clk_str, __parent__, _ret);\ +} while (0) + +#define SC_PM_SET_CLOCK_RATE(__ipcHndl__, __res__, __clk__, __rate__) \ +do { \ + char _res_str[] = #__res__;\ + char _clk_str[] = #__clk__;\ + sc_err_t _ret;\ + sc_pm_clock_rate_t _actual = __rate__;\ + if (g_debug_scfw) \ + printf("(%4d) sc_pm_set_clock_rate %s:%s -> %d\n",\ + __LINE__, _res_str, _clk_str, __rate__);\ + _ret = sc_pm_set_clock_rate(__ipcHndl__, __res__, __clk__, &_actual);\ + if (_ret != SC_ERR_NONE)\ + printf("(%4d)>> sc_pm_set_clock_rate failed! %s:%s -> %d (error = %d)\n",\ + __LINE__, _res_str, _clk_str, __rate__, _ret);\ + if (_actual != __rate__)\ + printf("(%4d)>> Actual rate for %s:%s is %d instead of %d\n", \ + __LINE__, _res_str, _clk_str, _actual, __rate__); \ +} while (0) + +#define SC_PM_CLOCK_ENABLE(__ipcHndl__, __res__, __clk__, __enable__) \ +do { \ + char _res_str[] = #__res__;\ + char _clk_str[] = #__clk__;\ + sc_err_t _ret;\ + if (g_debug_scfw) \ + printf("(%4d) sc_pm_clock_enable %s:%s -> %d\n",\ + __LINE__, _res_str, _clk_str, __enable__);\ + _ret = sc_pm_clock_enable(__ipcHndl__,\ + __res__, __clk__, __enable__, false);\ + if (_ret != SC_ERR_NONE)\ + printf("(%4d)>> sc_pm_clock_enable failed! %s:%s -> %d (error = %d)\n",\ + __LINE__, _res_str, _clk_str, __enable__, _ret);\ +} while (0) \ + +#define SC_MISC_SET_CONTROL(__ipcHndl__, __res__, __clk__, __value__) \ +do { \ + char _res_str[] = #__res__; \ + char _clk_str[] = #__clk__; \ + sc_err_t _ret; \ + if (g_debug_scfw) \ + printf("(%4d) sc_misc_set_control %s:%s -> %d\n",\ + __LINE__, _res_str, _clk_str, __value__);\ + _ret = sc_misc_set_control(__ipcHndl__, \ + __res__, __clk__, __value__); \ + if (_ret != SC_ERR_NONE) \ + printf("(%4d)>> sc_misc_set_control failed! %s:%s -> %d (error = %d)\n", \ + __LINE__, _res_str, _clk_str, __value__, _ret); \ +} while (0) + +#define SC_PM_SET_RESOURCE_POWER_MODE(__ipcHndl__, __res__, __enable__) \ +do { \ + char _res_str[] = #__res__; \ + sc_err_t _ret; \ + if (g_debug_scfw) \ + printf("(%4d) sc_pm_set_resource_power_mode %s -> %d\n",\ + __LINE__, _res_str, __enable__);\ + _ret = sc_pm_set_resource_power_mode(__ipcHndl__, __res__, __enable__);\ + if (_ret != SC_ERR_NONE) \ + printf("(%4d)>> sc_pm_set_resource_power_mode failed! %s -> %d (error = %d)\n", \ + __LINE__, _res_str, __enable__, _ret);\ +} while (0) + +#define SC_MISC_AUTH(__ipcHndl__, __cmd__, __addr__) \ +do { \ + sc_err_t _ret; \ + if (g_debug_scfw) \ + printf("(%4d) sc_misc_seco_authenticate -> cmd %d addr %d\n",\ + __LINE__, __cmd__, __addr__);\ + _ret = sc_seco_authenticate(__ipcHndl__, __cmd__, __addr__); \ + if (_ret != SC_ERR_NONE) \ + printf("(%4d)>> sc_misc_seco_authenticate cmd %d addr %d (error = %d)\n", \ + __LINE__, __cmd__, __addr__, _ret); \ +} while (0) + +#endif /*_SCFW_UTILS_H_ */ diff --git a/drivers/video/nxp/imx/imx8_dc.c b/drivers/video/nxp/imx/imx8_dc.c new file mode 100644 index 00000000000..9da34c6f3d2 --- /dev/null +++ b/drivers/video/nxp/imx/imx8_dc.c @@ -0,0 +1,426 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define FLAG_COMBO BIT(1) + +struct imx8_dc_priv { + /*struct udevice *bridge;*/ + struct udevice *panel; + struct udevice *disp_dev; + struct imxdpuv1_videomode mode; + + u32 gpixfmt; + u32 dpu_id; + u32 disp_id; +}; + +static int imx8_dc_soc_setup(struct udevice *dev, sc_pm_clock_rate_t pixel_clock) +{ + sc_err_t err; + sc_rsrc_t dc_rsrc, pll0_rsrc, pll1_rsrc; + sc_pm_clock_rate_t pll_clk; + const char *pll1_pd_name; + u32 dc_lpcg; + struct imx8_dc_priv *priv = dev_get_priv(dev); + + int dc_id = priv->dpu_id; + + struct power_domain pd; + int ret; + + debug("%s, dc_id %d\n", __func__, dc_id); + + if (dc_id == 0) { + dc_rsrc = SC_R_DC_0; + pll0_rsrc = SC_R_DC_0_PLL_0; + pll1_rsrc = SC_R_DC_0_PLL_1; + pll1_pd_name = "dc0_pll1"; + dc_lpcg = DC_0_LPCG; + } else { + dc_rsrc = SC_R_DC_1; + pll0_rsrc = SC_R_DC_1_PLL_0; + pll1_rsrc = SC_R_DC_1_PLL_1; + pll1_pd_name = "dc1_pll1"; + dc_lpcg = DC_1_LPCG; + } + + if (!power_domain_lookup_name(pll1_pd_name, &pd)) { + ret = power_domain_on(&pd); + if (ret) { + printf("%s Power up failed! (error = %d)\n", pll1_pd_name, ret); + return -EIO; + } + } else { + printf("%s lookup failed!\n", pll1_pd_name); + return -EIO; + } + + /* Setup the pll1/2 and DISP0/1 clock */ + if (pixel_clock >= 40000000) + pll_clk = 1188000000; + else + pll_clk = 675000000; + + err = sc_pm_set_clock_rate(-1, pll0_rsrc, SC_PM_CLK_PLL, &pll_clk); + if (err != SC_ERR_NONE) { + printf("PLL0 set clock rate failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(-1, pll1_rsrc, SC_PM_CLK_PLL, &pll_clk); + if (err != SC_ERR_NONE) { + printf("PLL1 set clock rate failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_parent(-1, dc_rsrc, SC_PM_CLK_MISC0, 2); + if (err != SC_ERR_NONE) { + printf("DISP0 set clock parent failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_parent(-1, dc_rsrc, SC_PM_CLK_MISC1, 3); + if (err != SC_ERR_NONE) { + printf("DISP0 set clock parent failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(-1, dc_rsrc, SC_PM_CLK_MISC0, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("DISP0 set clock rate failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(-1, dc_rsrc, SC_PM_CLK_MISC1, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("DISP1 set clock rate failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(-1, pll0_rsrc, SC_PM_CLK_PLL, true, false); + if (err != SC_ERR_NONE) { + printf("PLL0 clock enable failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(-1, pll1_rsrc, SC_PM_CLK_PLL, true, false); + if (err != SC_ERR_NONE) { + printf("PLL1 clock enable failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(-1, dc_rsrc, SC_PM_CLK_MISC0, true, false); + if (err != SC_ERR_NONE) { + printf("DISP0 clock enable failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(-1, dc_rsrc, SC_PM_CLK_MISC1, true, false); + if (err != SC_ERR_NONE) { + printf("DISP1 clock enable failed! (error = %d)\n", err); + return -EIO; + } + + lpcg_all_clock_on(dc_lpcg); + + err = sc_misc_set_control(-1, dc_rsrc, SC_C_PXL_LINK_MST1_ADDR, 0); + if (err != SC_ERR_NONE) { + printf("DC Set control fSC_C_PXL_LINK_MST1_ADDR ailed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(-1, dc_rsrc, SC_C_PXL_LINK_MST1_ENB, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST1_ENB failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(-1, dc_rsrc, SC_C_PXL_LINK_MST1_VLD, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST1_VLD failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(-1, dc_rsrc, SC_C_PXL_LINK_MST2_ADDR, 0); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST2_ADDR ailed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(-1, dc_rsrc, SC_C_PXL_LINK_MST2_ENB, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST2_ENB failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(-1, dc_rsrc, SC_C_PXL_LINK_MST2_VLD, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_PXL_LINK_MST2_VLD failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(-1, dc_rsrc, SC_C_SYNC_CTRL0, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_SYNC_CTRL0 failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(-1, dc_rsrc, SC_C_SYNC_CTRL1, 1); + if (err != SC_ERR_NONE) { + printf("DC Set control SC_C_SYNC_CTRL1 failed! (error = %d)\n", err); + return -EIO; + } + + return 0; +} + +static int imx8_dc_video_init(struct udevice *dev) +{ + imxdpuv1_channel_params_t channel; + imxdpuv1_layer_t layer; + struct imx8_dc_priv *priv = dev_get_priv(dev); + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + int8_t imxdpuv1_id = priv->dpu_id; + + debug("%s\n", __func__); + + if (imxdpuv1_id != 0 || (imxdpuv1_id == 1 && !is_imx8qm())) { + printf("%s(): invalid imxdpuv1_id %d", __func__, imxdpuv1_id); + return -ENODEV; + } + + imxdpuv1_init(imxdpuv1_id); + imxdpuv1_disp_enable_frame_gen(imxdpuv1_id, 0, IMXDPUV1_FALSE); + imxdpuv1_disp_enable_frame_gen(imxdpuv1_id, 1, IMXDPUV1_FALSE); + + imxdpuv1_disp_setup_frame_gen(imxdpuv1_id, priv->disp_id, + (const struct imxdpuv1_videomode *)&priv->mode, + 0x3ff, 0, 0, 1, IMXDPUV1_DISABLE); + imxdpuv1_disp_init(imxdpuv1_id, priv->disp_id); + imxdpuv1_disp_setup_constframe(imxdpuv1_id, + priv->disp_id, 0, 0, 0xff, 0); /* blue */ + + if (priv->disp_id == 0) + channel.common.chan = IMXDPUV1_CHAN_VIDEO_0; + else + channel.common.chan = IMXDPUV1_CHAN_VIDEO_1; + channel.common.src_pixel_fmt = priv->gpixfmt; + channel.common.dest_pixel_fmt = priv->gpixfmt; + channel.common.src_width = priv->mode.hlen; + channel.common.src_height = priv->mode.vlen; + + channel.common.clip_width = 0; + channel.common.clip_height = 0; + channel.common.clip_top = 0; + channel.common.clip_left = 0; + + channel.common.dest_width = priv->mode.hlen; + channel.common.dest_height = priv->mode.vlen; + channel.common.dest_top = 0; + channel.common.dest_left = 0; + channel.common.stride = + priv->mode.hlen * imxdpuv1_bytes_per_pixel(IMXDPUV1_PIX_FMT_BGRA32); + channel.common.disp_id = priv->disp_id; + channel.common.const_color = 0; + channel.common.use_global_alpha = 0; + channel.common.use_local_alpha = 0; + imxdpuv1_init_channel(imxdpuv1_id, &channel); + + imxdpuv1_init_channel_buffer(imxdpuv1_id, + channel.common.chan, + priv->mode.hlen * imxdpuv1_bytes_per_pixel(IMXDPUV1_PIX_FMT_RGB32), + IMXDPUV1_ROTATE_NONE, + (dma_addr_t)plat->base, + 0, + 0); + + layer.enable = IMXDPUV1_TRUE; + layer.secondary = get_channel_blk(channel.common.chan); + + if (priv->disp_id == 0) { + layer.stream = IMXDPUV1_DISPLAY_STREAM_0; + layer.primary = IMXDPUV1_ID_CONSTFRAME0; + } else { + layer.stream = IMXDPUV1_DISPLAY_STREAM_1; + layer.primary = IMXDPUV1_ID_CONSTFRAME1; + } + + imxdpuv1_disp_setup_layer( + imxdpuv1_id, &layer, IMXDPUV1_LAYER_0, 1); + imxdpuv1_disp_set_layer_global_alpha( + imxdpuv1_id, IMXDPUV1_LAYER_0, 0xff); + + imxdpuv1_disp_set_layer_position( + imxdpuv1_id, IMXDPUV1_LAYER_0, 0, 0); + imxdpuv1_disp_set_chan_position( + imxdpuv1_id, channel.common.chan, 0, 0); + + imxdpuv1_disp_enable_frame_gen(imxdpuv1_id, priv->disp_id, IMXDPUV1_ENABLE); + + debug("IMXDPU display start ...\n"); + + return 0; +} + +static int imx8_dc_get_timings_from_display(struct udevice *dev, + struct display_timing *timings) +{ + struct imx8_dc_priv *priv = dev_get_priv(dev); + int err; + + priv->disp_dev = video_link_get_next_device(dev); + if (!priv->disp_dev || + device_get_uclass_id(priv->disp_dev) != UCLASS_DISPLAY) { + + printf("fail to find display device\n"); + return -ENODEV; + } + + debug("disp_dev %s\n", priv->disp_dev->name); + + err = video_link_get_display_timings(timings); + if (err) + return err; + + return 0; +} + +static int imx8_dc_probe(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct imx8_dc_priv *priv = dev_get_priv(dev); + ulong flag = dev_get_driver_data(dev); + + struct display_timing timings; + u32 fb_start, fb_end; + int ret; + + debug("%s() plat: base 0x%lx, size 0x%x\n", + __func__, plat->base, plat->size); + + priv->dpu_id = dev_seq(dev); + + ret = imx8_dc_get_timings_from_display(dev, &timings); + if (ret) + return ret; + + priv->mode.pixelclock = timings.pixelclock.typ; + priv->mode.hlen = timings.hactive.typ; + priv->mode.hbp = timings.hback_porch.typ; + priv->mode.hfp = timings.hfront_porch.typ; + + priv->mode.vlen = timings.vactive.typ; + priv->mode.vbp = timings.vback_porch.typ; + priv->mode.vfp = timings.vfront_porch.typ; + + priv->mode.hsync = timings.hsync_len.typ; + priv->mode.vsync = timings.vsync_len.typ; + priv->mode.flags = IMXDPUV1_MODE_FLAGS_HSYNC_POL | IMXDPUV1_MODE_FLAGS_VSYNC_POL | IMXDPUV1_MODE_FLAGS_DE_POL; + + priv->gpixfmt = IMXDPUV1_PIX_FMT_BGRA32; + + imx8_dc_soc_setup(dev, priv->mode.pixelclock); + + if (flag & FLAG_COMBO) /* QXP has one DC which contains 2 LVDS/MIPI_DSI combo */ + priv->disp_id = dev_seq(priv->disp_dev->parent); + else + priv->disp_id = 1; /* QM has two DCs each contains one LVDS as secondary display output */ + + debug("dpu %u, disp_id %u, pixelclock %u, hlen %u, vlen %u\n", + priv->dpu_id, priv->disp_id, priv->mode.pixelclock, priv->mode.hlen, priv->mode.vlen); + + + display_enable(priv->disp_dev, 32, NULL); + + + ret = imx8_dc_video_init(dev); + if (ret) { + dev_err(dev, "imx8_dc_video_init fail %d\n", ret); + return ret; + } + + uc_priv->bpix = VIDEO_BPP32; + uc_priv->xsize = priv->mode.hlen; + uc_priv->ysize = priv->mode.vlen; + + /* Enable dcache for the frame buffer */ + fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); + fb_end = plat->base + plat->size; + fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); + mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, + DCACHE_WRITEBACK); + video_set_flush_dcache(dev, true); + + return ret; +} + +static int imx8_dc_bind(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + /* Max size supported by LCDIF, because in bind, we can't probe panel */ + plat->size = 1920 * 1080 *4; + + return 0; +} + +static int imx8_dc_remove(struct udevice *dev) +{ + struct imx8_dc_priv *priv = dev_get_priv(dev); + + debug("%s\n", __func__); + + imxdpuv1_disp_enable_frame_gen(priv->dpu_id, + priv->disp_id, IMXDPUV1_DISABLE); + + return 0; +} + +static const struct udevice_id imx8_dc_ids[] = { + { .compatible = "fsl,imx8qm-dpu" }, + { .compatible = "fsl,imx8qxp-dpu", .data = FLAG_COMBO, }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx8_dc) = { + .name = "imx8_dc", + .id = UCLASS_VIDEO, + .of_match = imx8_dc_ids, + .bind = imx8_dc_bind, + .probe = imx8_dc_probe, + .remove = imx8_dc_remove, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto = sizeof(struct imx8_dc_priv), +}; diff --git a/drivers/video/nxp/imx/imx8_lvds.c b/drivers/video/nxp/imx/imx8_lvds.c new file mode 100644 index 00000000000..076e3eb82e9 --- /dev/null +++ b/drivers/video/nxp/imx/imx8_lvds.c @@ -0,0 +1,315 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define FLAG_COMBO BIT(1) + +#define LDB_PHY_OFFSET 0x1000 +#define MIPI_PHY_OFFSET 0x8000 + +struct imx8_ldb_priv { + struct regmap *gpr; + struct udevice *conn_dev; + u32 ldb_id; + struct display_timing timings; +}; + +static int imx8_ldb_soc_setup(struct udevice *dev, sc_pm_clock_rate_t pixel_clock) +{ + sc_err_t err; + sc_rsrc_t lvds_rsrc, mipi_rsrc; + const char *pd_name; + struct imx8_ldb_priv *priv = dev_get_priv(dev); + ulong flag = dev_get_driver_data(dev); + int lvds_id = priv->ldb_id; + + struct power_domain pd; + int ret; + + debug("%s\n", __func__); + + if (lvds_id == 0) { + lvds_rsrc = SC_R_LVDS_0; + mipi_rsrc = SC_R_MIPI_0; + pd_name = "lvds0_power_domain"; + } else { + lvds_rsrc = SC_R_LVDS_1; + mipi_rsrc = SC_R_MIPI_1; + pd_name = "lvds1_power_domain"; + } + /* Power up LVDS */ + if (!power_domain_lookup_name(pd_name, &pd)) { + ret = power_domain_on(&pd); + if (ret) { + printf("%s Power up failed! (error = %d)\n", pd_name, ret); + return -EIO; + } + } else { + printf("%s lookup failed!\n", pd_name); + return -EIO; + } + + /* Setup clocks */ + err = sc_pm_set_clock_rate(-1, lvds_rsrc, SC_PM_CLK_BYPASS, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(-1, lvds_rsrc, SC_PM_CLK_PER, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_set_clock_rate(-1, lvds_rsrc, SC_PM_CLK_PHY, &pixel_clock); + if (err != SC_ERR_NONE) { + printf("LVDS set rate SC_PM_CLK_BYPASS failed! (error = %d)\n", err); + return -EIO; + } + + if (flag & FLAG_COMBO) { + /* For QXP, there is only one DC, and two pixel links to each LVDS with a mux provided. + * We connect LVDS0 to pixel link 0, lVDS1 to pixel link 1 from DC + */ + + /* Configure to LVDS mode not MIPI DSI */ + err = sc_misc_set_control(-1, mipi_rsrc, SC_C_MODE, 1); + if (err != SC_ERR_NONE) { + printf("LVDS sc_misc_set_control SC_C_MODE failed! (error = %d)\n", err); + return -EIO; + } + + /* Configure to LVDS mode with single channel */ + err = sc_misc_set_control(-1, mipi_rsrc, SC_C_DUAL_MODE, 0); + if (err != SC_ERR_NONE) { + printf("LVDS sc_misc_set_control SC_C_DUAL_MODE failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_misc_set_control(-1, mipi_rsrc, SC_C_PXL_LINK_SEL, lvds_id); + if (err != SC_ERR_NONE) { + printf("LVDS sc_misc_set_control SC_C_PXL_LINK_SEL failed! (error = %d)\n", err); + return -EIO; + } + } + + err = sc_pm_clock_enable(-1, lvds_rsrc, SC_PM_CLK_BYPASS, true, false); + if (err != SC_ERR_NONE) { + printf("LVDS enable clock SC_PM_CLK_BYPASS failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(-1, lvds_rsrc, SC_PM_CLK_PER, true, false); + if (err != SC_ERR_NONE) { + printf("LVDS enable clock SC_PM_CLK_PER failed! (error = %d)\n", err); + return -EIO; + } + + err = sc_pm_clock_enable(-1, lvds_rsrc, SC_PM_CLK_PHY, true, false); + if (err != SC_ERR_NONE) { + printf("LVDS enable clock SC_PM_CLK_PHY failed! (error = %d)\n", err); + return -EIO; + } + + return 0; +} + +void imx8_ldb_configure(struct udevice *dev) +{ + uint32_t mode; + uint32_t phy_setting; + struct imx8_ldb_priv *priv = dev_get_priv(dev); + ulong flag = dev_get_driver_data(dev); + + if (flag & FLAG_COMBO) { + mode = + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_MODE, LVDS_CTRL_CH0_MODE__DI0) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_DATA_WIDTH, LVDS_CTRL_CH0_DATA_WIDTH__24BIT) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_BIT_MAP, LVDS_CTRL_CH0_BIT_MAP__JEIDA); + + phy_setting = 0x4 << 5 | 0x4 << 2 | 1 << 1 | 0x1; + regmap_write(priv->gpr, LDB_PHY_OFFSET + LVDS_PHY_CTRL, phy_setting); + regmap_write(priv->gpr, LDB_PHY_OFFSET + LVDS_CTRL, mode); + regmap_write(priv->gpr, LDB_PHY_OFFSET + MIPIv2_CSR_TX_ULPS, 0); + regmap_write(priv->gpr, LDB_PHY_OFFSET + MIPIv2_CSR_PXL2DPI, MIPI_CSR_PXL2DPI_24_BIT); + + /* Power up PLL in MIPI DSI PHY */ + regmap_write(priv->gpr, MIPI_PHY_OFFSET + DPHY_PD_PLL, 0); + regmap_write(priv->gpr, MIPI_PHY_OFFSET + DPHY_PD_TX, 0); + } else { + mode = + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_MODE, LVDS_CTRL_CH0_MODE__DI0) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_DATA_WIDTH, LVDS_CTRL_CH0_DATA_WIDTH__24BIT) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_BIT_MAP, LVDS_CTRL_CH0_BIT_MAP__JEIDA) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_CH0_10BIT_ENABLE, LVDS_CTRL_CH0_10BIT_ENABLE__10BIT) | + IMX_LVDS_SET_FIELD(LVDS_CTRL_DI0_DATA_WIDTH, LVDS_CTRL_DI0_DATA_WIDTH__USE_30BIT); + + regmap_write(priv->gpr, LDB_PHY_OFFSET + LVDS_CTRL, mode); + + phy_setting = + LVDS_PHY_CTRL_RFB_MASK | + LVDS_PHY_CTRL_CH0_EN_MASK | + (0 << LVDS_PHY_CTRL_M_SHIFT) | + (0x04 << LVDS_PHY_CTRL_CCM_SHIFT) | + (0x04 << LVDS_PHY_CTRL_CA_SHIFT); + regmap_write(priv->gpr, LDB_PHY_OFFSET + LVDS_PHY_CTRL, phy_setting); + } +} + +int imx8_ldb_read_timing(struct udevice *dev, struct display_timing *timing) +{ + struct imx8_ldb_priv *priv = dev_get_priv(dev); + + if (dev->plat_ == NULL) + return -EINVAL; + + if (timing) { + memcpy(timing, &priv->timings, sizeof(struct display_timing)); + return 0; + } + + return -EINVAL; +} + +int imx8_ldb_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing) +{ + struct imx8_ldb_priv *priv = dev_get_priv(dev); + int ret; + + if (dev->plat_ == NULL) { + imx8_ldb_soc_setup(dev, timing->pixelclock.typ); + imx8_ldb_configure(dev); + } else { + + display_enable(dev->parent, panel_bpp, &priv->timings); + + if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) { + if (priv->conn_dev && + device_get_uclass_id(priv->conn_dev) == UCLASS_VIDEO_BRIDGE) { + ret = video_bridge_set_backlight(priv->conn_dev, 80); + if (ret) { + dev_err(dev, "fail to set backlight\n"); + return ret; + } + } + } + } + + return 0; +} + +static int imx8_ldb_probe(struct udevice *dev) +{ + struct imx8_ldb_priv *priv = dev_get_priv(dev); + int ret; + + debug("%s\n", __func__); + + if (dev->plat_ == NULL) { + + priv->gpr = syscon_regmap_lookup_by_phandle(dev, "gpr"); + if (IS_ERR(priv->gpr)) { + printf("fail to get gpr regmap\n"); + return PTR_ERR(priv->gpr); + } + + /* Require to add alias in DTB */ + priv->ldb_id = dev_seq(dev); + + debug("ldb_id %u\n", priv->ldb_id); + } else { + priv->conn_dev = video_link_get_next_device(dev); + if (!priv->conn_dev) { + debug("can't find next device in video link\n"); + } + + ret = video_link_get_display_timings(&priv->timings); + if (ret) { + printf("decode display timing error %d\n", ret); + return ret; + } + + if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) { + if (priv->conn_dev && + device_get_uclass_id(priv->conn_dev) == UCLASS_VIDEO_BRIDGE) { + ret = video_bridge_attach(priv->conn_dev); + if (ret) { + dev_err(dev, "fail to attach bridge\n"); + return ret; + } + + ret = video_bridge_set_active(priv->conn_dev, true); + if (ret) { + dev_err(dev, "fail to active bridge\n"); + return ret; + } + } + } + } + + return 0; +} + +static int imx8_ldb_bind(struct udevice *dev) +{ + ofnode lvds_ch_node; + int ret = 0; + + lvds_ch_node = ofnode_find_subnode(dev_ofnode(dev), "lvds-channel@0"); + if (ofnode_valid(lvds_ch_node)) { + ret = device_bind(dev, dev->driver, "lvds-channel@0", (void *)1, + lvds_ch_node, NULL); + if (ret) + printf("Error binding driver '%s': %d\n", dev->driver->name, + ret); + } + + return ret; +} + +struct dm_display_ops imx8_ldb_ops = { + .read_timing = imx8_ldb_read_timing, + .enable = imx8_ldb_enable, +}; + +static const struct udevice_id imx8_ldb_ids[] = { + { .compatible = "fsl,imx8qm-ldb" }, + { .compatible = "fsl,imx8qxp-ldb", .data = FLAG_COMBO, }, + { } +}; + +U_BOOT_DRIVER(imx8_ldb) = { + .name = "imx8_ldb", + .id = UCLASS_DISPLAY, + .of_match = imx8_ldb_ids, + .bind = imx8_ldb_bind, + .probe = imx8_ldb_probe, + .ops = &imx8_ldb_ops, + .priv_auto = sizeof(struct imx8_ldb_priv), +}; diff --git a/drivers/video/nxp/imx/imx8m_dcss.c b/drivers/video/nxp/imx/imx8m_dcss.c new file mode 100644 index 00000000000..6315471a900 --- /dev/null +++ b/drivers/video/nxp/imx/imx8m_dcss.c @@ -0,0 +1,534 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef DEBUG +#define reg32_write(addr, val) \ +do { \ + debug("%s():%d 0x%08x -> 0x%08x\n", __func__, __LINE__, \ + (unsigned int)addr, (unsigned int)val); \ + __raw_writel(val, addr); \ +} while (0) +#else +#define reg32_write(addr, val) __raw_writel(val, addr) +#endif + +#define reg32_read(addr) __raw_readl(addr) + +#define reg32setbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) | (1<<(bitpos)))) +#define reg32clearbit(addr, bitpos) \ + reg32_write((addr), (reg32_read((addr)) & ~(1<<(bitpos)))) + +#define reg32_read_tst(addr, val, mask) \ +do { \ + u32 temp = reg32_read((addr)); \ + if ((temp & (mask)) == ((val) & (mask))) \ + debug("%s():%d 0x%08x -> 0x%08x\n", \ + __func__, __LINE__, addr, val); \ + else \ + debug("%s():%d 0x%08x -> 0x%08x instead of 0x%08x\n", \ + __func__, __LINE__, addr, temp, val); \ +} while (0) + + +struct imx8m_dcss_priv { + struct udevice *disp_dev; + struct display_timing timings; + + bool hpol; /* horizontal pulse polarity */ + bool vpol; /* vertical pulse polarity */ + bool enabled; + + fdt_addr_t addr; +}; + +__weak int imx8m_dcss_clock_init(u32 pixclk) +{ + return 0; +} + +__weak int imx8m_dcss_power_init(void) +{ + return 0; +} + +static void imx8m_dcss_reset(struct udevice *dev) +{ + struct imx8m_dcss_priv *priv = dev_get_priv(dev); + u32 temp; + + /* DCSS reset */ + reg32_write(priv->addr + 0x2f000, 0xffffffff); + + /* DCSS clock selection */ + reg32_write(priv->addr + 0x2f010, 0x1); + temp = reg32_read(priv->addr + 0x2f010); + debug("%s(): DCSS clock control 0x%08x\n", __func__, temp); +} + +static void imx8m_dcss_init(struct udevice *dev) +{ + struct imx8m_dcss_priv *priv = dev_get_priv(dev); + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + debug("%s() ...\n", __func__); + + /* DTRC-CHAN2/3 */ + reg32_write(priv->addr + 0x160c8, 0x00000002); + reg32_write(priv->addr + 0x170c8, 0x00000002); + + /* CHAN1_DPR */ + reg32_write(priv->addr + 0x180c0, (unsigned int)plat->base); + reg32_write(priv->addr + 0x18090, 0x00000002); + reg32_write(priv->addr + 0x180a0, priv->timings.hactive.typ); + reg32_write(priv->addr + 0x180b0, priv->timings.vactive.typ); + reg32_write(priv->addr + 0x18110, + (unsigned int)plat->base + priv->timings.hactive.typ * priv->timings.vactive.typ); + reg32_write(priv->addr + 0x180f0, 0x00000280); + reg32_write(priv->addr + 0x18100, 0x000000f0); + reg32_write(priv->addr + 0x18070, ((priv->timings.hactive.typ * 4) << 16)); + reg32_write(priv->addr + 0x18050, 0x000e4203); + reg32_write(priv->addr + 0x18050, 0x000e4203); + reg32_write(priv->addr + 0x18200, 0x00000038); + reg32_write(priv->addr + 0x18000, 0x00000004); + reg32_write(priv->addr + 0x18000, 0x00000005); + + /* SCALER */ + reg32_write(priv->addr + 0x1c008, 0x00000000); + reg32_write(priv->addr + 0x1c00c, 0x00000000); + reg32_write(priv->addr + 0x1c010, 0x00000002); + reg32_write(priv->addr + 0x1c014, 0x00000002); + reg32_write(priv->addr + 0x1c018, + ((priv->timings.vactive.typ - 1) << 16 | (priv->timings.hactive.typ - 1))); + reg32_write(priv->addr + 0x1c01c, + ((priv->timings.vactive.typ - 1) << 16 | (priv->timings.hactive.typ - 1))); + reg32_write(priv->addr + 0x1c020, + ((priv->timings.vactive.typ - 1) << 16 | (priv->timings.hactive.typ - 1))); + reg32_write(priv->addr + 0x1c024, + ((priv->timings.vactive.typ - 1) << 16 | (priv->timings.hactive.typ - 1))); + reg32_write(priv->addr + 0x1c028, 0x00000000); + reg32_write(priv->addr + 0x1c02c, 0x00000000); + reg32_write(priv->addr + 0x1c030, 0x00000000); + reg32_write(priv->addr + 0x1c034, 0x00000000); + reg32_write(priv->addr + 0x1c038, 0x00000000); + reg32_write(priv->addr + 0x1c03c, 0x00000000); + reg32_write(priv->addr + 0x1c040, 0x00000000); + reg32_write(priv->addr + 0x1c044, 0x00000000); + reg32_write(priv->addr + 0x1c048, 0x00000000); + reg32_write(priv->addr + 0x1c04c, 0x00002000); + reg32_write(priv->addr + 0x1c050, 0x00000000); + reg32_write(priv->addr + 0x1c054, 0x00002000); + reg32_write(priv->addr + 0x1c058, 0x00000000); + reg32_write(priv->addr + 0x1c05c, 0x00002000); + reg32_write(priv->addr + 0x1c060, 0x00000000); + reg32_write(priv->addr + 0x1c064, 0x00002000); + reg32_write(priv->addr + 0x1c080, 0x00000000); + reg32_write(priv->addr + 0x1c0c0, 0x00040000); + reg32_write(priv->addr + 0x1c100, 0x00000000); + reg32_write(priv->addr + 0x1c084, 0x00000000); + reg32_write(priv->addr + 0x1c0c4, 0x00000000); + reg32_write(priv->addr + 0x1c104, 0x00000000); + reg32_write(priv->addr + 0x1c088, 0x00000000); + reg32_write(priv->addr + 0x1c0c8, 0x00000000); + reg32_write(priv->addr + 0x1c108, 0x00000000); + reg32_write(priv->addr + 0x1c08c, 0x00000000); + reg32_write(priv->addr + 0x1c0cc, 0x00000000); + reg32_write(priv->addr + 0x1c10c, 0x00000000); + reg32_write(priv->addr + 0x1c090, 0x00000000); + reg32_write(priv->addr + 0x1c0d0, 0x00000000); + reg32_write(priv->addr + 0x1c110, 0x00000000); + reg32_write(priv->addr + 0x1c094, 0x00000000); + reg32_write(priv->addr + 0x1c0d4, 0x00000000); + reg32_write(priv->addr + 0x1c114, 0x00000000); + reg32_write(priv->addr + 0x1c098, 0x00000000); + reg32_write(priv->addr + 0x1c0d8, 0x00000000); + reg32_write(priv->addr + 0x1c118, 0x00000000); + reg32_write(priv->addr + 0x1c09c, 0x00000000); + reg32_write(priv->addr + 0x1c0dc, 0x00000000); + reg32_write(priv->addr + 0x1c11c, 0x00000000); + reg32_write(priv->addr + 0x1c0a0, 0x00000000); + reg32_write(priv->addr + 0x1c0e0, 0x00000000); + reg32_write(priv->addr + 0x1c120, 0x00000000); + reg32_write(priv->addr + 0x1c0a4, 0x00000000); + reg32_write(priv->addr + 0x1c0e4, 0x00000000); + reg32_write(priv->addr + 0x1c124, 0x00000000); + reg32_write(priv->addr + 0x1c0a8, 0x00000000); + reg32_write(priv->addr + 0x1c0e8, 0x00000000); + reg32_write(priv->addr + 0x1c128, 0x00000000); + reg32_write(priv->addr + 0x1c0ac, 0x00000000); + reg32_write(priv->addr + 0x1c0ec, 0x00000000); + reg32_write(priv->addr + 0x1c12c, 0x00000000); + reg32_write(priv->addr + 0x1c0b0, 0x00000000); + reg32_write(priv->addr + 0x1c0f0, 0x00000000); + reg32_write(priv->addr + 0x1c130, 0x00000000); + reg32_write(priv->addr + 0x1c0b4, 0x00000000); + reg32_write(priv->addr + 0x1c0f4, 0x00000000); + reg32_write(priv->addr + 0x1c134, 0x00000000); + reg32_write(priv->addr + 0x1c0b8, 0x00000000); + reg32_write(priv->addr + 0x1c0f8, 0x00000000); + reg32_write(priv->addr + 0x1c138, 0x00000000); + reg32_write(priv->addr + 0x1c0bc, 0x00000000); + reg32_write(priv->addr + 0x1c0fc, 0x00000000); + reg32_write(priv->addr + 0x1c13c, 0x00000000); + reg32_write(priv->addr + 0x1c140, 0x00000000); + reg32_write(priv->addr + 0x1c180, 0x00040000); + reg32_write(priv->addr + 0x1c1c0, 0x00000000); + reg32_write(priv->addr + 0x1c144, 0x00000000); + reg32_write(priv->addr + 0x1c184, 0x00000000); + reg32_write(priv->addr + 0x1c1c4, 0x00000000); + reg32_write(priv->addr + 0x1c148, 0x00000000); + reg32_write(priv->addr + 0x1c188, 0x00000000); + reg32_write(priv->addr + 0x1c1c8, 0x00000000); + reg32_write(priv->addr + 0x1c14c, 0x00000000); + reg32_write(priv->addr + 0x1c18c, 0x00000000); + reg32_write(priv->addr + 0x1c1cc, 0x00000000); + reg32_write(priv->addr + 0x1c150, 0x00000000); + reg32_write(priv->addr + 0x1c190, 0x00000000); + reg32_write(priv->addr + 0x1c1d0, 0x00000000); + reg32_write(priv->addr + 0x1c154, 0x00000000); + reg32_write(priv->addr + 0x1c194, 0x00000000); + reg32_write(priv->addr + 0x1c1d4, 0x00000000); + reg32_write(priv->addr + 0x1c158, 0x00000000); + reg32_write(priv->addr + 0x1c198, 0x00000000); + reg32_write(priv->addr + 0x1c1d8, 0x00000000); + reg32_write(priv->addr + 0x1c15c, 0x00000000); + reg32_write(priv->addr + 0x1c19c, 0x00000000); + reg32_write(priv->addr + 0x1c1dc, 0x00000000); + reg32_write(priv->addr + 0x1c160, 0x00000000); + reg32_write(priv->addr + 0x1c1a0, 0x00000000); + reg32_write(priv->addr + 0x1c1e0, 0x00000000); + reg32_write(priv->addr + 0x1c164, 0x00000000); + reg32_write(priv->addr + 0x1c1a4, 0x00000000); + reg32_write(priv->addr + 0x1c1e4, 0x00000000); + reg32_write(priv->addr + 0x1c168, 0x00000000); + reg32_write(priv->addr + 0x1c1a8, 0x00000000); + reg32_write(priv->addr + 0x1c1e8, 0x00000000); + reg32_write(priv->addr + 0x1c16c, 0x00000000); + reg32_write(priv->addr + 0x1c1ac, 0x00000000); + reg32_write(priv->addr + 0x1c1ec, 0x00000000); + reg32_write(priv->addr + 0x1c170, 0x00000000); + reg32_write(priv->addr + 0x1c1b0, 0x00000000); + reg32_write(priv->addr + 0x1c1f0, 0x00000000); + reg32_write(priv->addr + 0x1c174, 0x00000000); + reg32_write(priv->addr + 0x1c1b4, 0x00000000); + reg32_write(priv->addr + 0x1c1f4, 0x00000000); + reg32_write(priv->addr + 0x1c178, 0x00000000); + reg32_write(priv->addr + 0x1c1b8, 0x00000000); + reg32_write(priv->addr + 0x1c1f8, 0x00000000); + reg32_write(priv->addr + 0x1c17c, 0x00000000); + reg32_write(priv->addr + 0x1c1bc, 0x00000000); + reg32_write(priv->addr + 0x1c1fc, 0x00000000); + reg32_write(priv->addr + 0x1c300, 0x00000000); + reg32_write(priv->addr + 0x1c340, 0x00000000); + reg32_write(priv->addr + 0x1c380, 0x00000000); + reg32_write(priv->addr + 0x1c304, 0x00000000); + reg32_write(priv->addr + 0x1c344, 0x00000000); + reg32_write(priv->addr + 0x1c384, 0x00000000); + reg32_write(priv->addr + 0x1c308, 0x00000000); + reg32_write(priv->addr + 0x1c348, 0x00000000); + reg32_write(priv->addr + 0x1c388, 0x00000000); + reg32_write(priv->addr + 0x1c30c, 0x00000000); + reg32_write(priv->addr + 0x1c34c, 0x00000000); + reg32_write(priv->addr + 0x1c38c, 0x00000000); + reg32_write(priv->addr + 0x1c310, 0x00000000); + reg32_write(priv->addr + 0x1c350, 0x00000000); + reg32_write(priv->addr + 0x1c390, 0x00000000); + reg32_write(priv->addr + 0x1c314, 0x00000000); + reg32_write(priv->addr + 0x1c354, 0x00000000); + reg32_write(priv->addr + 0x1c394, 0x00000000); + reg32_write(priv->addr + 0x1c318, 0x00000000); + reg32_write(priv->addr + 0x1c358, 0x00000000); + reg32_write(priv->addr + 0x1c398, 0x00000000); + reg32_write(priv->addr + 0x1c31c, 0x00000000); + reg32_write(priv->addr + 0x1c35c, 0x00000000); + reg32_write(priv->addr + 0x1c39c, 0x00000000); + reg32_write(priv->addr + 0x1c320, 0x00000000); + reg32_write(priv->addr + 0x1c360, 0x00000000); + reg32_write(priv->addr + 0x1c3a0, 0x00000000); + reg32_write(priv->addr + 0x1c324, 0x00000000); + reg32_write(priv->addr + 0x1c364, 0x00000000); + reg32_write(priv->addr + 0x1c3a4, 0x00000000); + reg32_write(priv->addr + 0x1c328, 0x00000000); + reg32_write(priv->addr + 0x1c368, 0x00000000); + reg32_write(priv->addr + 0x1c3a8, 0x00000000); + reg32_write(priv->addr + 0x1c32c, 0x00000000); + reg32_write(priv->addr + 0x1c36c, 0x00000000); + reg32_write(priv->addr + 0x1c3ac, 0x00000000); + reg32_write(priv->addr + 0x1c330, 0x00000000); + reg32_write(priv->addr + 0x1c370, 0x00000000); + reg32_write(priv->addr + 0x1c3b0, 0x00000000); + reg32_write(priv->addr + 0x1c334, 0x00000000); + reg32_write(priv->addr + 0x1c374, 0x00000000); + reg32_write(priv->addr + 0x1c3b4, 0x00000000); + reg32_write(priv->addr + 0x1c338, 0x00000000); + reg32_write(priv->addr + 0x1c378, 0x00000000); + reg32_write(priv->addr + 0x1c3b8, 0x00000000); + reg32_write(priv->addr + 0x1c33c, 0x00000000); + reg32_write(priv->addr + 0x1c37c, 0x00000000); + reg32_write(priv->addr + 0x1c3bc, 0x00000000); + reg32_write(priv->addr + 0x1c200, 0x00000000); + reg32_write(priv->addr + 0x1c240, 0x00000000); + reg32_write(priv->addr + 0x1c280, 0x00000000); + reg32_write(priv->addr + 0x1c204, 0x00000000); + reg32_write(priv->addr + 0x1c244, 0x00000000); + reg32_write(priv->addr + 0x1c284, 0x00000000); + reg32_write(priv->addr + 0x1c208, 0x00000000); + reg32_write(priv->addr + 0x1c248, 0x00000000); + reg32_write(priv->addr + 0x1c288, 0x00000000); + reg32_write(priv->addr + 0x1c20c, 0x00000000); + reg32_write(priv->addr + 0x1c24c, 0x00000000); + reg32_write(priv->addr + 0x1c28c, 0x00000000); + reg32_write(priv->addr + 0x1c210, 0x00000000); + reg32_write(priv->addr + 0x1c250, 0x00000000); + reg32_write(priv->addr + 0x1c290, 0x00000000); + reg32_write(priv->addr + 0x1c214, 0x00000000); + reg32_write(priv->addr + 0x1c254, 0x00000000); + reg32_write(priv->addr + 0x1c294, 0x00000000); + reg32_write(priv->addr + 0x1c218, 0x00000000); + reg32_write(priv->addr + 0x1c258, 0x00000000); + reg32_write(priv->addr + 0x1c298, 0x00000000); + reg32_write(priv->addr + 0x1c21c, 0x00000000); + reg32_write(priv->addr + 0x1c25c, 0x00000000); + reg32_write(priv->addr + 0x1c29c, 0x00000000); + reg32_write(priv->addr + 0x1c220, 0x00000000); + reg32_write(priv->addr + 0x1c260, 0x00000000); + reg32_write(priv->addr + 0x1c2a0, 0x00000000); + reg32_write(priv->addr + 0x1c224, 0x00000000); + reg32_write(priv->addr + 0x1c264, 0x00000000); + reg32_write(priv->addr + 0x1c2a4, 0x00000000); + reg32_write(priv->addr + 0x1c228, 0x00000000); + reg32_write(priv->addr + 0x1c268, 0x00000000); + reg32_write(priv->addr + 0x1c2a8, 0x00000000); + reg32_write(priv->addr + 0x1c22c, 0x00000000); + reg32_write(priv->addr + 0x1c26c, 0x00000000); + reg32_write(priv->addr + 0x1c2ac, 0x00000000); + reg32_write(priv->addr + 0x1c230, 0x00000000); + reg32_write(priv->addr + 0x1c270, 0x00000000); + reg32_write(priv->addr + 0x1c2b0, 0x00000000); + reg32_write(priv->addr + 0x1c234, 0x00000000); + reg32_write(priv->addr + 0x1c274, 0x00000000); + reg32_write(priv->addr + 0x1c2b4, 0x00000000); + reg32_write(priv->addr + 0x1c238, 0x00000000); + reg32_write(priv->addr + 0x1c278, 0x00000000); + reg32_write(priv->addr + 0x1c2b8, 0x00000000); + reg32_write(priv->addr + 0x1c23c, 0x00000000); + reg32_write(priv->addr + 0x1c27c, 0x00000000); + reg32_write(priv->addr + 0x1c2bc, 0x00000000); + reg32_write(priv->addr + 0x1c2bc, 0x00000000); + reg32_write(priv->addr + 0x1c000, 0x00000011); + + /* SUBSAM */ + reg32_write(priv->addr + 0x1b070, 0x21612161); + reg32_write(priv->addr + 0x1b080, 0x03ff0000); + reg32_write(priv->addr + 0x1b090, 0x03ff0000); + + reg32_write(priv->addr + 0x1b010, + (((priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vsync_len.typ + + priv->timings.vactive.typ -1) << 16) | + (priv->timings.hfront_porch.typ + priv->timings.hback_porch.typ + priv->timings.hsync_len.typ + + priv->timings.hactive.typ - 1))); + reg32_write(priv->addr + 0x1b020, + (((priv->timings.hsync_len.typ - 1) << 16) | priv->hpol << 31 | (priv->timings.hfront_porch.typ + + priv->timings.hback_porch.typ + priv->timings.hsync_len.typ + priv->timings.hactive.typ -1))); + reg32_write(priv->addr + 0x1b030, + (((priv->timings.vfront_porch.typ + priv->timings.vsync_len.typ - 1) << 16) | priv->vpol << 31 | (priv->timings.vfront_porch.typ - 1))); + reg32_write(priv->addr + 0x1b040, + ((1 << 31) | ((priv->timings.vsync_len.typ +priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ) << 16) | + (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ - 1))); + reg32_write(priv->addr + 0x1b050, + (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vactive.typ -1) << 16) | + (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ + priv->timings.hactive.typ - 1))); + + /* subsample mode 0 bypass 444, 1 422, 2 420 */ + reg32_write(priv->addr + 0x1b060, 0x0000000); + + reg32_write(priv->addr + 0x1b000, 0x00000001); + + /* DTG */ + /*reg32_write(priv->addr + 0x20000, 0xff000484); */ + /* disable local alpha */ + reg32_write(priv->addr + 0x20000, 0xff005084); + reg32_write(priv->addr + 0x20004, + (((priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vsync_len.typ + priv->timings.vactive.typ - + 1) << 16) | (priv->timings.hfront_porch.typ + priv->timings.hback_porch.typ + priv->timings.hsync_len.typ + + priv->timings.hactive.typ - 1))); + reg32_write(priv->addr + 0x20008, + (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ - + 1) << 16) | (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ - 1))); + reg32_write(priv->addr + 0x2000c, + (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vactive.typ - + 1) << 16) | (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ + priv->timings.hactive.typ - 1))); + reg32_write(priv->addr + 0x20010, + (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ - + 1) << 16) | (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ - 1))); + reg32_write(priv->addr + 0x20014, + (((priv->timings.vsync_len.typ + priv->timings.vfront_porch.typ + priv->timings.vback_porch.typ + priv->timings.vactive.typ - + 1) << 16) | (priv->timings.hsync_len.typ + priv->timings.hback_porch.typ + priv->timings.hactive.typ - 1))); + reg32_write(priv->addr + 0x20028, 0x000b000a); + + /* disable local alpha */ + reg32_write(priv->addr + 0x20000, 0xff005184); + + debug("leaving %s() ...\n", __func__); +} + +static void imx8m_display_shutdown(struct udevice *dev) +{ + struct imx8m_dcss_priv *priv = dev_get_priv(dev); + + /* stop the DCSS modules in use */ + /* dtg */ + reg32_write(priv->addr + 0x20000, 0); + /* scaler */ + reg32_write(priv->addr + 0x1c000, 0); + reg32_write(priv->addr + 0x1c400, 0); + reg32_write(priv->addr + 0x1c800, 0); + /* dpr */ + reg32_write(priv->addr + 0x18000, 0); + reg32_write(priv->addr + 0x19000, 0); + reg32_write(priv->addr + 0x1a000, 0); + /* sub-sampler*/ + reg32_write(priv->addr + 0x1b000, 0); +} + +static int imx8m_dcss_get_timings_from_display(struct udevice *dev, + struct display_timing *timings) +{ + struct imx8m_dcss_priv *priv = dev_get_priv(dev); + int err; + + priv->disp_dev = video_link_get_next_device(dev); + if (!priv->disp_dev || + device_get_uclass_id(priv->disp_dev) != UCLASS_DISPLAY) { + + printf("fail to find display device\n"); + return -ENODEV; + } + + debug("disp_dev %s\n", priv->disp_dev->name); + + err = video_link_get_display_timings(timings); + if (err) + return err; + + if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH) + priv->hpol = true; + + if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH) + priv->vpol = true; + + return 0; +} + +static int imx8m_dcss_probe(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct imx8m_dcss_priv *priv = dev_get_priv(dev); + + u32 fb_start, fb_end; + int ret; + + debug("%s() plat: base 0x%lx, size 0x%x\n", + __func__, plat->base, plat->size); + + priv->addr = dev_read_addr(dev); + if (priv->addr == FDT_ADDR_T_NONE) + return -EINVAL; + + ret = imx8m_dcss_get_timings_from_display(dev, &priv->timings); + if (ret) + return ret; + + debug("pixelclock %u, hlen %u, vlen %u\n", + priv->timings.pixelclock.typ, priv->timings.hactive.typ, priv->timings.vactive.typ); + + imx8m_dcss_power_init(); + + imx8m_dcss_clock_init(priv->timings.pixelclock.typ); + + imx8m_dcss_reset(dev); + + if (display_enable(priv->disp_dev, 32, NULL) == 0) { + imx8m_dcss_init(dev); + priv->enabled = true; + } + + uc_priv->bpix = VIDEO_BPP32; + uc_priv->xsize = priv->timings.hactive.typ; + uc_priv->ysize = priv->timings.vactive.typ; + + /* Enable dcache for the frame buffer */ + fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); + fb_end = plat->base + plat->size; + fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); + mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, + DCACHE_WRITEBACK); + video_set_flush_dcache(dev, true); + + return ret; +} + +static int imx8m_dcss_bind(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + debug("%s\n", __func__); + + /* Max size supported by LCDIF, because in bind, we can't probe panel */ + plat->size = 1920 * 1080 *4; + + return 0; +} + +static int imx8m_dcss_remove(struct udevice *dev) +{ + struct imx8m_dcss_priv *priv = dev_get_priv(dev); + + debug("%s\n", __func__); + + if (priv->enabled) { + device_remove(priv->disp_dev, DM_REMOVE_NORMAL); + imx8m_display_shutdown(dev); + } + + return 0; +} + +static const struct udevice_id imx8m_dcss_ids[] = { + { .compatible = "nxp,imx8mq-dcss" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx8m_dcss) = { + .name = "imx8m_dcss", + .id = UCLASS_VIDEO, + .of_match = imx8m_dcss_ids, + .bind = imx8m_dcss_bind, + .probe = imx8m_dcss_probe, + .remove = imx8m_dcss_remove, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto = sizeof(struct imx8m_dcss_priv), +}; diff --git a/drivers/video/nxp/imx/imx_lcdifv3.c b/drivers/video/nxp/imx/imx_lcdifv3.c new file mode 100644 index 00000000000..1eb99387774 --- /dev/null +++ b/drivers/video/nxp/imx/imx_lcdifv3.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "../../videomodes.h" +#include +#include +#include +#include +#include +#include "lcdifv3-regs.h" +#include +#include +#include +#include + +#define PS2KHZ(ps) (1000000000UL / (ps)) +#define HZ2PS(hz) (1000000000UL / ((hz) / 1000)) + +struct lcdifv3_priv { + fdt_addr_t reg_base; + struct udevice *disp_dev; + + u32 thres_low_mul; + u32 thres_low_div; + u32 thres_high_mul; + u32 thres_high_div; +}; + +static int lcdifv3_set_pix_fmt(struct lcdifv3_priv *priv, unsigned int format) +{ + uint32_t ctrldescl0_5 = 0; + + ctrldescl0_5 = readl((ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5)); + + WARN_ON(ctrldescl0_5 & CTRLDESCL0_5_SHADOW_LOAD_EN); + + ctrldescl0_5 &= ~(CTRLDESCL0_5_BPP(0xf) | CTRLDESCL0_5_YUV_FORMAT(0x3)); + + switch (format) { + case GDF_16BIT_565RGB: + ctrldescl0_5 |= CTRLDESCL0_5_BPP(BPP16_RGB565); + break; + case GDF_32BIT_X888RGB: + ctrldescl0_5 |= CTRLDESCL0_5_BPP(BPP32_ARGB8888); + break; + default: + printf("unsupported pixel format: %u\n", format); + return -EINVAL; + } + + writel(ctrldescl0_5, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5)); + + return 0; +} + + +static void lcdifv3_set_mode(struct lcdifv3_priv *priv, + struct ctfb_res_modes *mode) +{ + u32 disp_size, hsyn_para, vsyn_para, vsyn_hsyn_width, ctrldescl0_1; + + /* config display timings */ + disp_size = DISP_SIZE_DELTA_Y(mode->yres) | + DISP_SIZE_DELTA_X(mode->xres); + writel(disp_size, (ulong)(priv->reg_base + LCDIFV3_DISP_SIZE)); + + hsyn_para = HSYN_PARA_BP_H(mode->left_margin) | + HSYN_PARA_FP_H(mode->right_margin); + writel(hsyn_para, (ulong)(priv->reg_base + LCDIFV3_HSYN_PARA)); + + vsyn_para = VSYN_PARA_BP_V(mode->upper_margin) | + VSYN_PARA_FP_V(mode->lower_margin); + writel(vsyn_para, (ulong)(priv->reg_base + LCDIFV3_VSYN_PARA)); + + vsyn_hsyn_width = VSYN_HSYN_WIDTH_PW_V(mode->vsync_len) | + VSYN_HSYN_WIDTH_PW_H(mode->hsync_len); + writel(vsyn_hsyn_width, (ulong)(priv->reg_base + LCDIFV3_VSYN_HSYN_WIDTH)); + + /* config layer size */ + /* TODO: 32bits alignment for width */ + ctrldescl0_1 = CTRLDESCL0_1_HEIGHT(mode->yres) | + CTRLDESCL0_1_WIDTH(mode->xres); + writel(ctrldescl0_1, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_1)); + + /* Polarities */ + writel(CTRL_INV_HS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + writel(CTRL_INV_VS, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + + /* SEC MIPI DSI specific */ + writel(CTRL_INV_PXCK, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + writel(CTRL_INV_DE, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + +} + +static void lcdifv3_set_bus_fmt(struct lcdifv3_priv *priv) +{ + uint32_t disp_para = 0; + + disp_para = readl((ulong)(priv->reg_base + LCDIFV3_DISP_PARA)); + disp_para &= DISP_PARA_LINE_PATTERN(0xf); + + /* Fixed to 24 bits output */ + disp_para |= DISP_PARA_LINE_PATTERN(LP_RGB888_OR_YUV444); + + /* config display mode: default is normal mode */ + disp_para &= DISP_PARA_DISP_MODE(3); + disp_para |= DISP_PARA_DISP_MODE(0); + writel(disp_para, (ulong)(priv->reg_base + LCDIFV3_DISP_PARA)); +} + +static void lcdifv3_enable_plane_panic(struct lcdifv3_priv *priv) +{ + u32 panic_thres, thres_low, thres_high; + + /* apb clock has been enabled */ + + /* As suggestion, the thres_low should be 1/3 FIFO, + * and thres_high should be 2/3 FIFO (The FIFO size + * is 8KB = 512 * 128bit). + * threshold = n * 128bit (n: 0 ~ 511) + */ + thres_low = DIV_ROUND_UP(511 * priv->thres_low_mul, + priv->thres_low_div); + thres_high = DIV_ROUND_UP(511 * priv->thres_high_mul, + priv->thres_high_div); + + panic_thres = PANIC0_THRES_PANIC_THRES_LOW(thres_low) | + PANIC0_THRES_PANIC_THRES_HIGH(thres_high); + + writel(panic_thres, priv->reg_base + LCDIFV3_PANIC0_THRES); + + /* Enable Panic: + * + * As designed, the panic won't trigger an irq, + * so it is unnecessary to handle this as an irq + * and NoC + QoS modules will handle panic + * automatically. + */ + writel(INT_ENABLE_D1_PLANE_PANIC_EN, + priv->reg_base + LCDIFV3_INT_ENABLE_D1); +} + +static void lcdifv3_enable_controller(struct lcdifv3_priv *priv) +{ + u32 disp_para, ctrldescl0_5; + + disp_para = readl((ulong)(priv->reg_base + LCDIFV3_DISP_PARA)); + ctrldescl0_5 = readl((ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5)); + + /* disp on */ + disp_para |= DISP_PARA_DISP_ON; + writel(disp_para, (ulong)(priv->reg_base + LCDIFV3_DISP_PARA)); + + /* enable shadow load */ + ctrldescl0_5 |= CTRLDESCL0_5_SHADOW_LOAD_EN; + writel(ctrldescl0_5, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5)); + + /* enable layer dma */ + ctrldescl0_5 |= CTRLDESCL0_5_EN; + writel(ctrldescl0_5, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5)); +} + +static void lcdifv3_disable_controller(struct lcdifv3_priv *priv) +{ + u32 disp_para, ctrldescl0_5; + + disp_para = readl((ulong)(priv->reg_base + LCDIFV3_DISP_PARA)); + ctrldescl0_5 = readl((ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5)); + + /* dma off */ + ctrldescl0_5 &= ~CTRLDESCL0_5_EN; + writel(ctrldescl0_5, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_5)); + + /* disp off */ + disp_para &= ~DISP_PARA_DISP_ON; + writel(disp_para, (ulong)(priv->reg_base + LCDIFV3_DISP_PARA)); +} + +static void lcdifv3_init(struct udevice *dev, + struct ctfb_res_modes *mode, unsigned int format) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + struct lcdifv3_priv *priv = dev_get_priv(dev); + int ret; + + /* Kick in the LCDIF clock */ + mxs_set_lcdclk(priv->reg_base, PS2KHZ(mode->pixclock)); + + writel(CTRL_SW_RESET, (ulong)(priv->reg_base + LCDIFV3_CTRL_CLR)); + + /* enable plane FIFO panic */ + lcdifv3_enable_plane_panic(priv); + + lcdifv3_set_mode(priv, mode); + + lcdifv3_set_bus_fmt(priv); + + ret = lcdifv3_set_pix_fmt(priv, format); + if (ret) { + printf("Fail to init lcdifv3, wrong format %u\n", format); + return; + } + + /* Set fb address to primary layer */ + writel(plat->base, (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL_LOW0_4)); + + writel(CTRLDESCL0_3_P_SIZE(1) |CTRLDESCL0_3_T_SIZE(1) | CTRLDESCL0_3_PITCH(mode->xres * 4), + (ulong)(priv->reg_base + LCDIFV3_CTRLDESCL0_3)); + + lcdifv3_enable_controller(priv); +} + +void lcdifv3_power_down(struct lcdifv3_priv *priv) +{ + int timeout = 1000000; + + /* Disable LCDIF during VBLANK */ + writel(INT_STATUS_D0_VS_BLANK, + (ulong)(priv->reg_base + LCDIFV3_INT_STATUS_D0)); + while (--timeout) { + if (readl((ulong)(priv->reg_base + LCDIFV3_INT_STATUS_D0)) & + INT_STATUS_D0_VS_BLANK) + break; + udelay(1); + } + + lcdifv3_disable_controller(priv); +} + +static int lcdifv3_of_get_timings(struct udevice *dev, + struct display_timing *timings) +{ + int ret = 0; + struct lcdifv3_priv *priv = dev_get_priv(dev); + + priv->disp_dev = video_link_get_next_device(dev); + if (!priv->disp_dev || + (device_get_uclass_id(priv->disp_dev) != UCLASS_VIDEO_BRIDGE + && device_get_uclass_id(priv->disp_dev) != UCLASS_DISPLAY)) { + + printf("fail to find output device\n"); + return -ENODEV; + } + + debug("disp_dev %s\n", priv->disp_dev->name); + + ret = video_link_get_display_timings(timings); + if (ret) { + printf("fail to get display timings\n"); + return ret; + } + + return ret; +} + +static int lcdifv3_check_thres_value(u32 mul, u32 div) +{ + if (!div) + return -EINVAL; + + if (mul > div) + return -EINVAL; + + return 0; +} + +static void lcdifv3_of_parse_thres(struct udevice *dev) +{ + int ret; + u32 thres_low[2], thres_high[2]; + struct lcdifv3_priv *priv = dev_get_priv(dev); + + + /* default 'thres-low' value: FIFO * 1/3; + * default 'thres-high' value: FIFO * 2/3. + */ + priv->thres_low_mul = 1; + priv->thres_low_div = 3; + priv->thres_high_mul = 2; + priv->thres_high_div = 3; + + ret = dev_read_u32_array(dev, "thres-low", thres_low, 2); + if (!ret) { + /* check the value effectiveness */ + ret = lcdifv3_check_thres_value(thres_low[0], thres_low[1]); + if (!ret) { + priv->thres_low_mul = thres_low[0]; + priv->thres_low_div = thres_low[1]; + } + } + + ret = dev_read_u32_array(dev, "thres-high", thres_high, 2); + if (!ret) { + /* check the value effectiveness */ + ret = lcdifv3_check_thres_value(thres_high[0], thres_high[1]); + if (!ret) { + priv->thres_high_mul = thres_high[0]; + priv->thres_high_div = thres_high[1]; + } + } +} + + +static int lcdifv3_video_probe(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct lcdifv3_priv *priv = dev_get_priv(dev); + + struct ctfb_res_modes mode; + struct display_timing timings; + + u32 fb_start, fb_end; + int ret; + + debug("%s() plat: base 0x%lx, size 0x%x\n", + __func__, plat->base, plat->size); + + priv->reg_base = dev_read_addr(dev); + if (priv->reg_base == FDT_ADDR_T_NONE) { + dev_err(dev, "lcdif base address is not found\n"); + return -EINVAL; + } + + ret = lcdifv3_of_get_timings(dev, &timings); + if (ret) + return ret; + + lcdifv3_of_parse_thres(dev); + + if (priv->disp_dev) { +#if IS_ENABLED(CONFIG_VIDEO_BRIDGE) + if (device_get_uclass_id(priv->disp_dev) == UCLASS_VIDEO_BRIDGE) { + ret = video_bridge_attach(priv->disp_dev); + if (ret) { + dev_err(dev, "fail to attach bridge\n"); + return ret; + } + + ret = video_bridge_set_backlight(priv->disp_dev, 80); + if (ret) { + dev_err(dev, "fail to set backlight\n"); + return ret; + } + } +#endif + } + + mode.xres = timings.hactive.typ; + mode.yres = timings.vactive.typ; + mode.left_margin = timings.hback_porch.typ; + mode.right_margin = timings.hfront_porch.typ; + mode.upper_margin = timings.vback_porch.typ; + mode.lower_margin = timings.vfront_porch.typ; + mode.hsync_len = timings.hsync_len.typ; + mode.vsync_len = timings.vsync_len.typ; + mode.pixclock = HZ2PS(timings.pixelclock.typ); + + lcdifv3_init(dev, &mode, GDF_32BIT_X888RGB); + + uc_priv->bpix = VIDEO_BPP32; /* only support 32 BPP now */ + uc_priv->xsize = mode.xres; + uc_priv->ysize = mode.yres; + + /* Enable dcache for the frame buffer */ + fb_start = plat->base & ~(MMU_SECTION_SIZE - 1); + fb_end = plat->base + plat->size; + fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT); + mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start, + DCACHE_WRITEBACK); + video_set_flush_dcache(dev, true); + gd->fb_base = plat->base; + + return ret; +} + +static int lcdifv3_video_bind(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + /* Max size supported by LCDIF, because in bind, we can't probe panel */ + plat->size = 1920 * 1080 *4 * 2; + + return 0; +} + +static int lcdifv3_video_remove(struct udevice *dev) +{ + struct lcdifv3_priv *priv = dev_get_priv(dev); + + debug("%s\n", __func__); + + if (priv->disp_dev) + device_remove(priv->disp_dev, DM_REMOVE_NORMAL); + + lcdifv3_power_down(priv); + + return 0; +} + +static const struct udevice_id lcdifv3_video_ids[] = { + { .compatible = "fsl,imx8mp-lcdif1" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(lcdifv3_video) = { + .name = "lcdifv3_video", + .id = UCLASS_VIDEO, + .of_match = lcdifv3_video_ids, + .bind = lcdifv3_video_bind, + .probe = lcdifv3_video_probe, + .remove = lcdifv3_video_remove, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE, + .priv_auto = sizeof(struct lcdifv3_priv), +}; diff --git a/drivers/video/nxp/imx/imxdpuv1.c b/drivers/video/nxp/imx/imxdpuv1.c new file mode 100644 index 00000000000..26025e1453a --- /dev/null +++ b/drivers/video/nxp/imx/imxdpuv1.c @@ -0,0 +1,6214 @@ +/* + * Copyright 2015-2017 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include "imxdpuv1_private.h" +#include "imxdpuv1_registers.h" +#include "imxdpuv1_events.h" + +#include "imxdpuv1_be.h" + +#define ptr_to_uint32(__ptr__) ((uint32_t)((uint64_t)(__ptr__))) + +/* Private data*/ +static struct imxdpuv1_soc imxdpuv1_array[IMXDPUV1_MAX_NUM]; + +typedef struct { + uint8_t len; + uint8_t buffers; +} imxdpuv1_burst_entry_t; + +static const imxdpuv1_burst_entry_t burst_param[] = { + { 0, 0 }, /* IMXDPUV1_SCAN_DIR_UNKNOWN */ + { 8, 32 }, /* IMXDPUV1_SCAN_DIR_LEFT_RIGHT_DOWN */ + { 16, 16 }, /* IMXDPUV1_SCAN_DIR_HORIZONTAL */ + { 8, 32 }, /* IMXDPUV1_SCAN_DIR_VERTICAL possibly 8/32 here */ + { 8, 32 }, /* IMXDPUV1_SCAN_DIR_FREE */ +}; + +typedef struct { + uint32_t extdst; + uint32_t sub; +} trigger_entry_t; + +static const trigger_entry_t trigger_list[IMXDPUV1_SHDLD_IDX_MAX] = { + /* IMXDPUV1_SHDLD_* extdst, sub */ + /* _DISP0 */{ 1, 0 }, + /* _DISP1 */{ 1, 0 }, + /* _CONST0 */{ IMXDPUV1_SHDLD_CONSTFRAME0, 0 }, + /* _CONST1 */{ IMXDPUV1_SHDLD_CONSTFRAME1, 0 }, + /* _CHAN_00 */{ IMXDPUV1_SHDLD_FETCHDECODE2, 0 }, + /* _CHAN_01 */{ IMXDPUV1_SHDLD_FETCHDECODE0, 0 }, + /* _CHAN_02 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_1 }, + /* _CHAN_03 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_2 }, + /* _CHAN_04 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_3 }, + /* _CHAN_05 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_4 }, + /* _CHAN_06 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_5 }, + /* _CHAN_07 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_6 }, + /* _CHAN_08 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_7 }, + /* _CHAN_09 */{ IMXDPUV1_SHDLD_FETCHLAYER0, IMXDPUV1_SUB_8 }, + /* _CHAN_10 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_1 << 16 }, + /* _CHAN_11 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_2 << 16 }, + /* _CHAN_12 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_3 << 16 }, + /* _CHAN_13 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_4 << 16 }, + /* _CHAN_14 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_5 << 16 }, + /* _CHAN_15 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_6 << 16 }, + /* _CHAN_16 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_7 << 16 }, + /* _CHAN_17 */{ IMXDPUV1_SHDLD_FETCHWARP2, IMXDPUV1_SUB_8 << 16 }, + /* _CHAN_18 */{ IMXDPUV1_SHDLD_FETCHDECODE3, 0 }, + /* _CHAN_19 */{ IMXDPUV1_SHDLD_FETCHDECODE1, 0 }, + /* _CHAN_20 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_1 << 8 }, + /* _CHAN_21 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_2 << 8 }, + /* _CHAN_22 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_3 << 8 }, + /* _CHAN_23 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_4 << 8 }, + /* _CHAN_24 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_5 << 8 }, + /* _CHAN_25 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_6 << 8 }, + /* _CHAN_26 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_7 << 8 }, + /* _CHAN_27 */{ IMXDPUV1_SHDLD_FETCHLAYER1, IMXDPUV1_SUB_8 << 8 }, + /* _CHAN_28 */{ IMXDPUV1_SHDLD_FETCHECO0, 0 }, + /* _CHAN_29 */{ IMXDPUV1_SHDLD_FETCHECO1, 0 }, + /* _CHAN_30 */{ IMXDPUV1_SHDLD_FETCHECO2, 0 } +}; + +#ifdef ENABLE_IMXDPUV1_TRACE_REG +uint32_t _imxdpuv1_read(struct imxdpuv1_soc *imxdpu, uint32_t offset, char *file, + int line) +{ + uint32_t val = 0; + val = __raw_readl(imxdpu->base + offset); + IMXDPUV1_TRACE_REG("%s:%d R reg 0x%08x --> val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)val); + return val; +} + +void _imxdpuv1_write(struct imxdpuv1_soc *imxdpu, uint32_t offset, uint32_t value, + char *file, int line) +{ + __raw_writel(value, imxdpu->base + offset); + IMXDPUV1_TRACE_REG("%s:%d W reg 0x%08x <-- val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)value); +} + +#endif + +void _imxdpuv1_write_block(struct imxdpuv1_soc *imxdpu, uint32_t offset, + void *values, uint32_t cnt, char *file, int line) +{ + int i; + uint32_t *dest = (uint32_t *)(imxdpu->base + offset); + uint32_t *src = (uint32_t *)values; + IMXDPUV1_TRACE_REG("%s:%d W reg 0x%08x <-- cnt 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)cnt); + for (i = 0; i < cnt; i++) { + dest[i] = src[i]; + IMXDPUV1_TRACE_REG("%s:%d WB reg 0x%08x <-- val 0x%08x\n", file, line, + (uint32_t) ((uint64_t)(&dest[i])), (uint32_t)(src[i])); + + } +} + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_READ +uint32_t _imxdpuv1_read_irq(struct imxdpuv1_soc *imxdpu, uint32_t offset, + char *file, int line) +{ + uint32_t val = 0; + val = __raw_readl(imxdpu->base + offset); + IMXDPUV1_TRACE_IRQ("%s:%d IRQ R reg 0x%08x --> val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)val); + return val; +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_WRITE +void _imxdpuv1_write_irq(struct imxdpuv1_soc *imxdpu, uint32_t offset, + uint32_t value, char *file, int line) +{ + __raw_writel(value, imxdpu->base + offset); + IMXDPUV1_TRACE_IRQ("%s:%d IRQ W reg 0x%08x <-- val 0x%08x\n", file, line, + (uint32_t)offset, (uint32_t)value); +} +#endif + +/* static prototypes */ +int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan); +static int imxdpuv1_disp_start_shadow_loads(int8_t imxdpuv1_id, int8_t disp); +void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id); +static bool imxdpuv1_is_yuv(uint32_t fmt); +bool imxdpuv1_is_rgb(uint32_t fmt); + +/*! + * Returns IMXDPUV1_TRUE for a valid channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + + if ((chan_idx >= IMXDPUV1_CHAN_IDX_IN_FIRST) && + (chan_idx < IMXDPUV1_CHAN_IDX_IN_MAX)) + return IMXDPUV1_TRUE; + if ((chan_idx >= IMXDPUV1_CHAN_IDX_OUT_FIRST) && + (chan_idx < IMXDPUV1_CHAN_IDX_OUT_MAX)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid store channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_store_chan(imxdpuv1_chan_t chan) +{ +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_STORE4) || (blk_id == IMXDPUV1_ID_STORE4)) + return IMXDPUV1_TRUE; +#endif + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_eco_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHECO0) || + (blk_id == IMXDPUV1_ID_FETCHECO1) || + (blk_id == IMXDPUV1_ID_FETCHECO2)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch decode channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_decode_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHDECODE0) || + (blk_id == IMXDPUV1_ID_FETCHDECODE1) +#ifdef IMXDPUV1_VERSION_0 + || (blk_id == IMXDPUV1_ID_FETCHDECODE2) + || (blk_id == IMXDPUV1_ID_FETCHDECODE3) +#endif + ) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE if a fetch channel has an eco fetch + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int has_fetch_eco_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHDECODE0) || + (blk_id == IMXDPUV1_ID_FETCHDECODE1) || + (blk_id == IMXDPUV1_ID_FETCHWARP2)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch warp channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_warp_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHWARP2)) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid fetch layer channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_layer_chan(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHLAYER0) +#ifdef IMXDPUV1_VERSION_0 + || (blk_id == IMXDPUV1_ID_FETCHLAYER1) +#endif + ) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns IMXDPUV1_TRUE for a valid layer sub1 channel + * + * @param channel to test + * + * @return This function returns IMXDPUV1_TRUE on success or + * IMXDPUV1_FALSE if the test fails. + */ +static int is_fetch_layer_sub_chan1(imxdpuv1_chan_t chan) +{ + imxdpuv1_id_t blk_id = get_channel_blk(chan); + if ((blk_id == IMXDPUV1_ID_FETCHLAYER0) || +#ifdef IMXDPUV1_VERSION_0 + (blk_id == IMXDPUV1_ID_FETCHLAYER1) || +#endif + (blk_id == IMXDPUV1_ID_FETCHWARP2)) + if (get_channel_sub(chan) == IMXDPUV1_SUB_1) + return IMXDPUV1_TRUE; + return IMXDPUV1_FALSE; +} + +/*! + * Returns subindex of a channel + * + * @param channel + * + * @return returns the subindex of a channel + */ +static int imxdpuv1_get_channel_subindex(imxdpuv1_chan_t chan) +{ + switch (get_channel_sub(chan)) { + case IMXDPUV1_SUB_2: + return 1; + case IMXDPUV1_SUB_3: + return 2; + case IMXDPUV1_SUB_4: + return 3; + case IMXDPUV1_SUB_5: + return 4; + case IMXDPUV1_SUB_6: + return 5; + case IMXDPUV1_SUB_7: + return 6; + case IMXDPUV1_SUB_8: + return 7; + case IMXDPUV1_SUB_1: + case IMXDPUV1_SUBWINDOW_NONE: + default: + return 0; + } +} + +/*! + * Returns returns the eco channel for a channel index + * + * @param chan + * + * @return returns number of bits per pixel or zero + * if the format is not matched. + */ +imxdpuv1_chan_t imxdpuv1_get_eco(imxdpuv1_chan_t chan) +{ + switch (get_eco_idx(chan)) { + case get_channel_idx(IMXDPUV1_CHAN_28): + return IMXDPUV1_CHAN_28; + case get_channel_idx(IMXDPUV1_CHAN_29): + return IMXDPUV1_CHAN_29; + case get_channel_idx(IMXDPUV1_CHAN_30): + return IMXDPUV1_CHAN_30; + default: + return 0; + } +} +/*! + * Returns the start address offset for a given block ID + * + * @param block id + * + * @return This function returns the address offset if the block id + * matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID + * is returned. + */ +uint32_t id2blockoffset(imxdpuv1_id_t block_id) +{ + switch (block_id) { + /*case IMXDPUV1_ID_NONE: return IMXDPUV1_NONE_LOCKUNLOCK; */ + case IMXDPUV1_ID_FETCHDECODE9: + return IMXDPUV1_FETCHDECODE9_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FETCHPERSP9: + return IMXDPUV1_FETCHPERSP9_LOCKUNLOCK; +#else + case IMXDPUV1_ID_FETCHWARP9: + return IMXDPUV1_FETCHWARP9_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_FETCHECO9: + return IMXDPUV1_FETCHECO9_LOCKUNLOCK; + case IMXDPUV1_ID_ROP9: + return IMXDPUV1_ROP9_LOCKUNLOCK; + case IMXDPUV1_ID_CLUT9: + return IMXDPUV1_CLUT9_LOCKUNLOCK; + case IMXDPUV1_ID_MATRIX9: + return IMXDPUV1_MATRIX9_LOCKUNLOCK; + case IMXDPUV1_ID_HSCALER9: + return IMXDPUV1_HSCALER9_LOCKUNLOCK; + case IMXDPUV1_ID_VSCALER9: + return IMXDPUV1_VSCALER9_LOCKUNLOCK; + case IMXDPUV1_ID_FILTER9: + return IMXDPUV1_FILTER9_LOCKUNLOCK; + case IMXDPUV1_ID_BLITBLEND9: + return IMXDPUV1_BLITBLEND9_LOCKUNLOCK; + case IMXDPUV1_ID_STORE9: + return IMXDPUV1_STORE9_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME0: + return IMXDPUV1_CONSTFRAME0_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST0: + return IMXDPUV1_EXTDST0_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME4: + return IMXDPUV1_CONSTFRAME4_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST4: + return IMXDPUV1_EXTDST4_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME1: + return IMXDPUV1_CONSTFRAME1_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST1: + return IMXDPUV1_EXTDST1_LOCKUNLOCK; + case IMXDPUV1_ID_CONSTFRAME5: + return IMXDPUV1_CONSTFRAME5_LOCKUNLOCK; + case IMXDPUV1_ID_EXTDST5: + return IMXDPUV1_EXTDST5_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_EXTSRC4: + return IMXDPUV1_EXTSRC4_LOCKUNLOCK; + case IMXDPUV1_ID_STORE4: + return IMXDPUV1_STORE4_LOCKUNLOCK; + case IMXDPUV1_ID_EXTSRC5: + return IMXDPUV1_EXTSRC5_LOCKUNLOCK; + case IMXDPUV1_ID_STORE5: + return IMXDPUV1_STORE5_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE2: + return IMXDPUV1_FETCHDECODE2_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE3: + return IMXDPUV1_FETCHDECODE3_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_FETCHWARP2: + return IMXDPUV1_FETCHWARP2_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHECO2: + return IMXDPUV1_FETCHECO2_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE0: + return IMXDPUV1_FETCHDECODE0_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHECO0: + return IMXDPUV1_FETCHECO0_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHDECODE1: + return IMXDPUV1_FETCHDECODE1_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHECO1: + return IMXDPUV1_FETCHECO1_LOCKUNLOCK; + case IMXDPUV1_ID_FETCHLAYER0: + return IMXDPUV1_FETCHLAYER0_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FETCHLAYER1: + return IMXDPUV1_FETCHLAYER1_LOCKUNLOCK; + case IMXDPUV1_ID_GAMMACOR4: + return IMXDPUV1_GAMMACOR4_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_MATRIX4: + return IMXDPUV1_MATRIX4_LOCKUNLOCK; + case IMXDPUV1_ID_HSCALER4: + return IMXDPUV1_HSCALER4_LOCKUNLOCK; + case IMXDPUV1_ID_VSCALER4: + return IMXDPUV1_VSCALER4_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM4: + return IMXDPUV1_HISTOGRAM4_CONTROL; + case IMXDPUV1_ID_GAMMACOR5: + return IMXDPUV1_GAMMACOR5_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_MATRIX5: + return IMXDPUV1_MATRIX5_LOCKUNLOCK; + case IMXDPUV1_ID_HSCALER5: + return IMXDPUV1_HSCALER5_LOCKUNLOCK; + case IMXDPUV1_ID_VSCALER5: + return IMXDPUV1_VSCALER5_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM5: + return IMXDPUV1_HISTOGRAM5_CONTROL; +#endif + case IMXDPUV1_ID_LAYERBLEND0: + return IMXDPUV1_LAYERBLEND0_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND1: + return IMXDPUV1_LAYERBLEND1_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND2: + return IMXDPUV1_LAYERBLEND2_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND3: + return IMXDPUV1_LAYERBLEND3_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_LAYERBLEND4: + return IMXDPUV1_LAYERBLEND4_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND5: + return IMXDPUV1_LAYERBLEND5_LOCKUNLOCK; + case IMXDPUV1_ID_LAYERBLEND6: + return IMXDPUV1_LAYERBLEND6_LOCKUNLOCK; + case IMXDPUV1_ID_EXTSRC0: + return IMXDPUV1_EXTSRC0_LOCKUNLOCK; + case IMXDPUV1_ID_EXTSRC1: + return IMXDPUV1_EXTSRC1_LOCKUNLOCK; +#endif + case IMXDPUV1_ID_DISENGCFG: + return IMXDPUV1_DISENGCFG_LOCKUNLOCK0; + case IMXDPUV1_ID_FRAMEGEN0: + return IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + case IMXDPUV1_ID_MATRIX0: + return IMXDPUV1_MATRIX0_LOCKUNLOCK; + case IMXDPUV1_ID_GAMMACOR0: + return IMXDPUV1_GAMMACOR0_LOCKUNLOCK; + case IMXDPUV1_ID_DITHER0: + return IMXDPUV1_DITHER0_LOCKUNLOCK; + case IMXDPUV1_ID_TCON0: + return IMXDPUV1_TCON0_LOCKUNLOCK; + case IMXDPUV1_ID_SIG0: + return IMXDPUV1_SIG0_LOCKUNLOCK; + case IMXDPUV1_ID_FRAMEGEN1: + return IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + case IMXDPUV1_ID_MATRIX1: + return IMXDPUV1_MATRIX1_LOCKUNLOCK; + case IMXDPUV1_ID_GAMMACOR1: + return IMXDPUV1_GAMMACOR1_LOCKUNLOCK; + case IMXDPUV1_ID_DITHER1: + return IMXDPUV1_DITHER1_LOCKUNLOCK; + case IMXDPUV1_ID_TCON1: + return IMXDPUV1_TCON1_LOCKUNLOCK; + case IMXDPUV1_ID_SIG1: + return IMXDPUV1_SIG1_LOCKUNLOCK; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FRAMECAP4: + return IMXDPUV1_FRAMECAP4_LOCKUNLOCK; + case IMXDPUV1_ID_FRAMECAP5: + return IMXDPUV1_FRAMECAP5_LOCKUNLOCK; +#endif + default: + return IMXDPUV1_OFFSET_INVALID; + } +} + +/*! + * Returns the start address offset for the dynamic configuraiton for + * a given block ID + * + * @param block id + * + * @return This function returns the address offset if the block id + * matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID + * is returned. + */ +uint32_t id2dynamicoffset(imxdpuv1_id_t block_id) +{ + switch (block_id) { + case IMXDPUV1_ID_FETCHDECODE9: + return IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC; + +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_FETCHPERSP9: + return IMXDPUV1_PIXENGCFG_FETCHPERSP9_DYNAMIC; +#else + case IMXDPUV1_ID_FETCHWARP9: + return IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC; +#endif + case IMXDPUV1_ID_ROP9: + return IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC; + case IMXDPUV1_ID_CLUT9: + return IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC; + case IMXDPUV1_ID_MATRIX9: + return IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC; + case IMXDPUV1_ID_HSCALER9: + return IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC; + case IMXDPUV1_ID_VSCALER9: + return IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC; + case IMXDPUV1_ID_FILTER9: + return IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC; + case IMXDPUV1_ID_BLITBLEND9: + return IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC; + case IMXDPUV1_ID_STORE9: + return IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC; + case IMXDPUV1_ID_EXTDST0: + return IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC; + case IMXDPUV1_ID_EXTDST4: + return IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC; + case IMXDPUV1_ID_EXTDST1: + return IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_EXTDST5: + return IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC; + case IMXDPUV1_ID_STORE4: + return IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC; + case IMXDPUV1_ID_STORE5: + return IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE2: + return IMXDPUV1_PIXENGCFG_FETCHDECODE2_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE3: + return IMXDPUV1_PIXENGCFG_FETCHDECODE3_DYNAMIC; +#endif + case IMXDPUV1_ID_FETCHWARP2: + return IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE0: + return IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC; + case IMXDPUV1_ID_FETCHDECODE1: + return IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_GAMMACOR4: + return IMXDPUV1_PIXENGCFG_GAMMACOR4_DYNAMIC; +#endif + case IMXDPUV1_ID_MATRIX4: + return IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC; + case IMXDPUV1_ID_HSCALER4: + return IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC; + case IMXDPUV1_ID_VSCALER4: + return IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM4: + return IMXDPUV1_PIXENGCFG_HISTOGRAM4_DYNAMIC; + case IMXDPUV1_ID_GAMMACOR5: + return IMXDPUV1_PIXENGCFG_GAMMACOR5_DYNAMIC; +#endif + case IMXDPUV1_ID_MATRIX5: + return IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC; + case IMXDPUV1_ID_HSCALER5: + return IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC; + case IMXDPUV1_ID_VSCALER5: + return IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_HISTOGRAM5: + return IMXDPUV1_PIXENGCFG_HISTOGRAM5_DYNAMIC; +#endif + case IMXDPUV1_ID_LAYERBLEND0: + return IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND1: + return IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND2: + return IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND3: + return IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC; +#ifdef IMXDPUV1_VERSION_0 + case IMXDPUV1_ID_LAYERBLEND4: + return IMXDPUV1_PIXENGCFG_LAYERBLEND4_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND5: + return IMXDPUV1_PIXENGCFG_LAYERBLEND5_DYNAMIC; + case IMXDPUV1_ID_LAYERBLEND6: + return IMXDPUV1_PIXENGCFG_LAYERBLEND6_DYNAMIC; +#endif + default: + return IMXDPUV1_OFFSET_INVALID; + } +} + +/*! + * Returns the start address offset for a given shadow index + * + * @param block id + * + * @return This function returns the address offset if the shadow + * index matches a valid block. Otherwise, IMXDPUV1_OFFSET_INVALID + * is returned. + */ +imxdpuv1_chan_t shadowindex2channel(imxdpuv1_shadow_load_index_t shadow_index) +{ + switch (shadow_index) { + case IMXDPUV1_SHDLD_IDX_CHAN_00: + return IMXDPUV1_CHAN_00; + case IMXDPUV1_SHDLD_IDX_CHAN_01: + return IMXDPUV1_CHAN_01; + case IMXDPUV1_SHDLD_IDX_CHAN_02: + return IMXDPUV1_CHAN_02; + case IMXDPUV1_SHDLD_IDX_CHAN_03: + return IMXDPUV1_CHAN_03; + case IMXDPUV1_SHDLD_IDX_CHAN_04: + return IMXDPUV1_CHAN_04; + case IMXDPUV1_SHDLD_IDX_CHAN_05: + return IMXDPUV1_CHAN_05; + case IMXDPUV1_SHDLD_IDX_CHAN_06: + return IMXDPUV1_CHAN_06; + case IMXDPUV1_SHDLD_IDX_CHAN_07: + return IMXDPUV1_CHAN_07; + case IMXDPUV1_SHDLD_IDX_CHAN_08: + return IMXDPUV1_CHAN_08; + case IMXDPUV1_SHDLD_IDX_CHAN_09: + return IMXDPUV1_CHAN_09; + case IMXDPUV1_SHDLD_IDX_CHAN_10: + return IMXDPUV1_CHAN_10; + case IMXDPUV1_SHDLD_IDX_CHAN_11: + return IMXDPUV1_CHAN_11; + case IMXDPUV1_SHDLD_IDX_CHAN_12: + return IMXDPUV1_CHAN_12; + case IMXDPUV1_SHDLD_IDX_CHAN_13: + return IMXDPUV1_CHAN_13; + case IMXDPUV1_SHDLD_IDX_CHAN_14: + return IMXDPUV1_CHAN_14; + case IMXDPUV1_SHDLD_IDX_CHAN_15: + return IMXDPUV1_CHAN_15; + case IMXDPUV1_SHDLD_IDX_CHAN_16: + return IMXDPUV1_CHAN_16; + case IMXDPUV1_SHDLD_IDX_CHAN_17: + return IMXDPUV1_CHAN_17; + case IMXDPUV1_SHDLD_IDX_CHAN_18: + return IMXDPUV1_CHAN_18; + case IMXDPUV1_SHDLD_IDX_CHAN_19: + return IMXDPUV1_CHAN_19; + case IMXDPUV1_SHDLD_IDX_CHAN_20: + return IMXDPUV1_CHAN_20; + case IMXDPUV1_SHDLD_IDX_CHAN_21: + return IMXDPUV1_CHAN_21; + case IMXDPUV1_SHDLD_IDX_CHAN_22: + return IMXDPUV1_CHAN_22; + case IMXDPUV1_SHDLD_IDX_CHAN_23: + return IMXDPUV1_CHAN_23; + case IMXDPUV1_SHDLD_IDX_CHAN_24: + return IMXDPUV1_CHAN_24; + case IMXDPUV1_SHDLD_IDX_CHAN_25: + return IMXDPUV1_CHAN_25; + case IMXDPUV1_SHDLD_IDX_CHAN_26: + return IMXDPUV1_CHAN_26; + case IMXDPUV1_SHDLD_IDX_CHAN_27: + return IMXDPUV1_CHAN_27; + case IMXDPUV1_SHDLD_IDX_CHAN_28: + return IMXDPUV1_CHAN_28; + case IMXDPUV1_SHDLD_IDX_CHAN_29: + return IMXDPUV1_CHAN_29; + case IMXDPUV1_SHDLD_IDX_CHAN_30: + return IMXDPUV1_CHAN_30; + default: + return IMXDPUV1_CHANNEL_INVALID; + } +} + + +/*! + * This function returns the pointer to the imxdpu structutre + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns the pointer to the imxdpu structutre + * return a NULL pointer for a failure. + */ +struct imxdpuv1_soc *imxdpuv1_get_soc(int8_t imxdpuv1_id) +{ + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return NULL; + } + return &(imxdpuv1_array[imxdpuv1_id]); +} + +/*! + * This function enables the interrupt for the specified interrupt line. + * The interrupt lines are defined in imxdpuv1_events.h. + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to enable interrupt for. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_enable_irq(int8_t imxdpuv1_id, uint32_t irq) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + if (irq == 0) + panic("Trying to enable irq 0!"); +#endif + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_clear_irq(imxdpuv1_id, irq); + if (irq < IMXDPUV1_INTERRUPT_MAX) { + if (irq < 32) { + imxdpu->enabled_int[0] |= INTSTAT0_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, + imxdpu->enabled_int[0]); + } else if (irq < 64) { + imxdpu->enabled_int[1] |= INTSTAT1_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, + imxdpu->enabled_int[1]); +#ifdef IMXDPUV1_VERSION_0 + } else { + imxdpu->enabled_int[2] |= INTSTAT2_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, + imxdpu->enabled_int[2]); +#endif + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function disables the interrupt for the specified interrupt line.g + * The interrupt lines are defined in imxdpuv1_events.h. + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to disable interrupt for. + * + */ +int imxdpuv1_disable_irq(int8_t imxdpuv1_id, uint32_t irq) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (irq < IMXDPUV1_INTERRUPT_MAX) { + if (irq < 32) { + imxdpu->enabled_int[0] &= ~INTSTAT0_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, + imxdpu->enabled_int[0]); + } else if (irq < 64) { + imxdpu->enabled_int[1] &= ~INTSTAT1_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, + imxdpu->enabled_int[1]); +#ifdef IMXDPUV1_VERSION_0 + } else { + imxdpu->enabled_int[2] &= ~INTSTAT2_BIT(irq); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, + imxdpu->enabled_int[2]); +#endif + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function clears all interrupts. + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_clear_all_irqs(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2_USERINTERRUPTCLEAR2_MASK); +#endif +#if 1 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR0, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR1, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR2, + IMXDPUV1_COMCTRL_INTERRUPTCLEAR2_INTERRUPTCLEAR2_MASK); +#endif +#endif + return ret; +} + +/*! + * This function disables all interrupts. + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_disable_all_irqs(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, 0); + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, 0); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, 0); +#endif + +#if 1 + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE0, 0); + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE1, 0); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, IMXDPUV1_COMCTRL_INTERRUPTENABLE2, 0); +#endif +#endif + + imxdpu->enabled_int[0] = 0; + imxdpu->enabled_int[1] = 0; +#ifdef IMXDPUV1_VERSION_0 + imxdpu->enabled_int[2] = 0; +#endif + return ret; +} + +/*! + * This function clears the interrupt for the specified interrupt line. + * The interrupt lines are defined in ipu_irq_line enum. + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to clear interrupt for. + * + */ +int imxdpuv1_clear_irq(int8_t imxdpuv1_id, uint32_t irq) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (irq < IMXDPUV1_INTERRUPT_MAX) { + if (irq < 32) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0, + 1U << irq); + } + if (irq < 64) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1, + 1U << (irq - 32)); +#ifdef IMXDPUV1_VERSION_0 + } else { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2, + 1U << (irq - 64)); +#endif + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function initializes the imxdpu interrupts + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_init_irqs(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_disable_all_irqs(imxdpuv1_id); + imxdpuv1_clear_all_irqs(imxdpuv1_id); + + /* Set all irq to user mode */ + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK); + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2_USERINTERRUPTMASK2_MASK); +#endif + /* enable needed interupts */ + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST0_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST1_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ); + +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_SHDLOAD_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_SEQCOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_SEQCOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_STORE5_FRAMECOMPLETE_IRQ); +#endif + /* enable the frame interrupts as IMXDPUV1_IRQF_ONESHOT */ + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_FRAMEGEN0_INT0_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_FRAMEGEN1_INT0_IRQ); + + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_COMCTRL_SW0_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_COMCTRL_SW1_IRQ); + + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ); + imxdpuv1_enable_irq(imxdpuv1_id, IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ); + + IMXDPUV1_TRACE("%s() enabled_int[0] 0x%08x\n", __func__, + imxdpu->enabled_int[0]); + IMXDPUV1_TRACE("%s() enabled_int[1] 0x%08x\n", __func__, + imxdpu->enabled_int[1]); +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_TRACE("%s() enabled_int[2] 0x%08x\n", __func__, + imxdpu->enabled_int[2]); +#endif + return ret; +} + +/*! + * This function checks pending shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_check_shadow_loads(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + uint32_t addr_extdst = IMXDPUV1_OFFSET_INVALID; /* address for extdst */ + uint32_t extdst = 0; + uint32_t extdst_stat = 0; + uint32_t fgen = 1; + uint32_t fgen_stat = 0; + uint32_t sub = 0; + uint32_t sub_stat = 0; + uint32_t stat; + + int32_t i; + + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + stat = imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0); + if (disp == 0) { + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST; + if (stat & IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ) { + fgen = 0; + } + } else if (disp == 1) { + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST; + if (stat & IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ) { + fgen = 0; + } + } else { + return -EINVAL; + } + + sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE)) & 0xff; +#ifdef IMXDPUV1_VERSION_0 + sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE) << 8) & 0xff00; +#endif + sub |= (imxdpuv1_read(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE) << 16) & 0xff0000; + extdst = imxdpuv1_read(imxdpu, addr_extdst); + + /* this loop may need to be optimized */ + for (i = 0; i < IMXDPUV1_SHDLD_IDX_CHAN_00; i++) { + if (imxdpu->shadow_load_state[disp][i].state.complete) { + if (imxdpu->shadow_load_state[disp][i].state.trys > 0) { + IMXDPUV1_TRACE_IRQ + ("shadow index complete after retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } else { + IMXDPUV1_TRACE_IRQ("shadow index complete: index %d\n", i); + } + imxdpu->shadow_load_state[disp][i].word = 0; + } else if (imxdpu->shadow_load_state[disp][i].state.processing) { + if (i > IMXDPUV1_SHDLD_IDX_CONST1) { + if (!(extdst & trigger_list[i].extdst) && !fgen) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + extdst_stat |= trigger_list[i].extdst; + fgen_stat |= 1 << i; + } + } else if (!(extdst & trigger_list[i].extdst)) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + imxdpu->shadow_load_state[disp][i].state.trys++; + extdst |= trigger_list[i].extdst; + IMXDPUV1_TRACE_IRQ + ("shadow index retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } + } + } + + + for (i = IMXDPUV1_SHDLD_IDX_CHAN_00; i < IMXDPUV1_SHDLD_IDX_MAX; i++) { + if (imxdpu->shadow_load_state[disp][i].state.complete) { + + if (imxdpu->shadow_load_state[disp][i].state.trys > 0) { + IMXDPUV1_TRACE_IRQ + ("shadow index complete after retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } else { + IMXDPUV1_TRACE_IRQ("shadow index complete: index %d\n", i); + } + imxdpu->shadow_load_state[disp][i].word = 0; + } else if (imxdpu->shadow_load_state[disp][i].state.processing) { + /* fetch layer and fetchwarp */ + if ((trigger_list[i].extdst != 0) && + (trigger_list[i].sub != 0)) { + if (!(extdst & trigger_list[i].extdst) && + !(sub & trigger_list[i].sub)) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + extdst_stat |= trigger_list[i].extdst; + sub_stat |= trigger_list[i].sub; + } + } else if (!(extdst & trigger_list[i].extdst)) { + imxdpu->shadow_load_state[disp][i]. + state.complete = 1; + } else { + imxdpu->shadow_load_state[disp][i].state.trys++; + extdst_stat |= trigger_list[i].extdst; + IMXDPUV1_TRACE_IRQ + ("shadow index retry: index %d trys %d\n", + i, + imxdpu->shadow_load_state[disp][i]. + state.trys); + } + } + } + + if ((extdst_stat == 0) && (sub_stat == 0) && (fgen_stat == 0)) { + /* clear interrupt */ + IMXDPUV1_TRACE_IRQ("shadow requests are complete.\n"); + } else { + IMXDPUV1_TRACE_IRQ + ("shadow requests are not complete: extdst 0x%08x, sub 0x%08x, fgen 0x%08x\n", + extdst, sub, fgen); + IMXDPUV1_TRACE_IRQ + ("shadow requests are not complete: extdst_stat 0x%08x, sub_stat 0x%08x, fgen_stat 0x%08x\n", + extdst_stat, sub_stat, fgen_stat); + } + + return ret; +} + +/*! + * This function starts pending shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +static int imxdpuv1_disp_start_shadow_loads(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + uint32_t addr_extdst; /* address for extdst */ + uint32_t addr_fgen; /* address for frame generator */ + uint32_t extdst = 0; + uint32_t fgen = 0; + uint32_t sub = 0; + int32_t i; + + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + addr_fgen = IMXDPUV1_FRAMEGEN0_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST; + + } else if (disp == 1) { + addr_fgen = IMXDPUV1_FRAMEGEN1_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST; + } else { + return -EINVAL; + } + + /* this loop may need to be optimized */ + for (i = 0; i < IMXDPUV1_SHDLD_IDX_CHAN_00; i++) { + if (imxdpu->shadow_load_state[disp][i].state.request && + (imxdpu->shadow_load_state[disp][i].state.processing == 0)) { + imxdpu->shadow_load_state[disp][i].state.processing = 1; + extdst |= trigger_list[i].extdst; + /* only trigger frame generator for const frames*/ + if (i >= IMXDPUV1_SHDLD_IDX_CONST0) { + fgen |= 1; + } + } + } + for (i = IMXDPUV1_SHDLD_IDX_CHAN_00; i < IMXDPUV1_SHDLD_IDX_MAX; i++) { + if (imxdpu->shadow_load_state[disp][i].state.request && + (imxdpu->shadow_load_state[disp][i].state.processing == 0)) { + imxdpu->shadow_load_state[disp][i].state.processing = 1; + /*todo: need a completion handler */ + extdst |= trigger_list[i].extdst; + sub |= trigger_list[i].sub; + } + } + + if (sub) { + IMXDPUV1_TRACE_IRQ("Fetch layer shadow request 0x%08x\n", sub); + if (sub & 0xff) { /* FETCHLAYER0 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE, + sub & 0xff); + } +#ifdef IMXDPUV1_VERSION_0 + if (sub & 0xff00) { /* FETCHLAYER1 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE, + (sub >> 8) & 0xff); + } +#endif + if (sub & 0xff0000) { /* FETCHWARP2 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE, + (sub >> 16) & 0xff); + } + } + + if (extdst) { + IMXDPUV1_TRACE_IRQ("Extdst shadow request 0x%08x\n", extdst); + imxdpuv1_write(imxdpu, addr_extdst, extdst); + } + + if (fgen) { + IMXDPUV1_TRACE_IRQ("Fgen shadow request 0x%08x\n", fgen); + imxdpuv1_write(imxdpu, addr_fgen, fgen); + } + + return ret; +} + +/*! + * This function handles the VYNC interrupt for a display + * + * @param imxdpu imxdpu instance + * @param disp display index + * + */ +static void imxdpuv1_disp_vsync_handler(int8_t imxdpuv1_id, int8_t disp) +{ + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + if (!((disp == 0) || (disp == 1))) + return; + + /* send notifications + shadow load finished + */ + + imxdpuv1_disp_start_shadow_loads(imxdpuv1_id, disp); + imxdpuv1_disp_update_fgen_status(imxdpuv1_id, disp); + + return; + +} + +/*! + * This function calls a register handler for an interrupt + * + * @param imxdpu imxdpu instance + * @param irq interrupt line + * + */ +static void imxdpuv1_handle_registered_irq(int8_t imxdpuv1_id, int8_t irq) +{ + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if ((irq < 0) || (irq >= IMXDPUV1_INTERRUPT_MAX)) + return; + + if (imxdpu->irq_list[irq].handler == NULL) + return; + + imxdpu->irq_list[irq].handler(irq, imxdpu->irq_list[irq].data); + + if ((imxdpu->irq_list[irq].flags & IMXDPUV1_IRQF_ONESHOT) != 0) { + imxdpuv1_disable_irq(imxdpuv1_id, irq); + imxdpuv1_clear_irq(imxdpuv1_id, irq); + } + return; + +} + +/* todo: this irq handler assumes all irq are ORed together. + The irqs may be grouped so this function can be + optimized if that is the case*/ +/*! + * This function processes all IRQs for the IMXDPU + * + * @param data pointer to the imxdpu structure + * + */ +int imxdpuv1_handle_irq(int32_t imxdpuv1_id) +{ + uint32_t int_stat[3]; + uint32_t int_temp[3]; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + IMXDPUV1_TRACE_IRQ("%s(): invalid imxdpuv1_id\n", __func__); +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + panic("wrong imxdpuv1_id"); +#endif + return IMXDPUV1_FALSE; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpu->irq_count++; + +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + { + uint32_t int_enable0; + int_enable0 = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0); + if (int_enable0 & 1) { + panic("IRQ0 enabled\n"); + } + if (imxdpu->enabled_int[0] & 1) { + panic("IRQ0 in enabled_int is set\n"); + } + } +#endif + /* Get and clear interrupt status */ + int_temp[0] = + imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0); + int_stat[0] = imxdpu->enabled_int[0] & int_temp[0]; + int_temp[1] = + imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1); + int_stat[1] = imxdpu->enabled_int[1] & int_temp[1]; +#ifdef IMXDPUV1_VERSION_0 +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + /* Enable this (IMXDPUV1_ENABLE_INTSTAT2) if intstat2 interrupts + are needed */ + int_temp[2] = + imxdpuv1_read_irq(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS2); + int_stat[2] = imxdpu->enabled_int[2] & int_temp[2]; +#endif +#endif + /* No interrupts are pending */ + if ((int_temp[0] == 0) && (int_temp[1] == 0) +#ifdef IMXDPUV1_VERSION_0 +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + && (int_temp[2] == 0) +#endif +#endif + ) { + } + + /* No enabled interrupts are pending */ + if ((int_stat[0] == 0) && (int_stat[1] == 0) +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + && (int_stat[2] == 0) +#endif + ) { + IMXDPUV1_TRACE_IRQ + ("Error: No enabled interrupts, 0x%08x 0x%08x\n", + int_temp[0] & ~imxdpu->enabled_int[0], + int_temp[1] & ~imxdpu->enabled_int[1]); +#ifdef DEBUG_IMXDPUV1_IRQ_ERROR + panic("no enabled IMXDPU interrupts"); +#endif + + return IMXDPUV1_FALSE; + } + + /* Clear the enabled interrupts */ + if (int_stat[0]) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0, + int_stat[0]); + } + if (int_stat[1]) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1, + int_stat[1]); + } +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + if (int_stat[2]) { + imxdpuv1_write_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR2, + int_stat[2]); + } +#endif + +#ifdef IMXDPUV1_ENABLE_INTSTAT2 + if (int_stat[1] != 0) { + /* add int_stat[2] if needed */ + } +#endif +#ifdef IMXDPUV1_VERSION_0 + /* now handle the interrupts that are pending */ + if (int_stat[0] != 0) { + if (int_stat[0] & 0xff) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SHDLOAD_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SEQCOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SEQCOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0); + + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ); + } + } + if (int_stat[0] & 0xff00) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST1_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT( + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE4_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ_CAPTURE("IMXDPUV1_STORE4_SHDLOAD_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE4_SHDLOAD_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ_CAPTURE( + "IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE4_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE4_SEQCOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ_CAPTURE( + "IMXDPUV1_STORE4_SEQCOMPLETE_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE4_SEQCOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_HISTOGRAM4_VALID_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_HISTOGRAM4_VALID_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_HISTOGRAM4_VALID_IRQ); + } + } + if (int_stat[0] & 0xff000000) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_HISTOGRAM5_VALID_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_HISTOGRAM5_VALID_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_HISTOGRAM5_VALID_IRQ); + } + if (int_stat[1] & + INTSTAT0_BIT(IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ)) { + IMXDPUV1_PRINT + ("IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ irq\n"); + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN0_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 0); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN0_INT0_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT1_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN0_INT1_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN0_INT1_IRQ); + } + } + } + + if (int_stat[1] != 0) { + if (int_stat[1] & 0xff) { + + } + if (int_stat[1] & 0xff00) { + if (int_stat[1] & + INTSTAT1_BIT(IMXDPUV1_FRAMEGEN1_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN1_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN1_INT0_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + if (int_stat[0] & + INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW0_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW0_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW0_IRQ); + } + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW2_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW2_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW2_IRQ); + } + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW3_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW3_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW3_IRQ); + } + + } + } +#else + /* now handle the interrupts that are pending */ + if (int_stat[0] != 0) { + if (int_stat[0] & 0xff) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SHDLOAD_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_STORE9_SEQCOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_STORE9_SEQCOMPLETE_IRQ irq\n"); + imxdpuv1_be_irq_handler(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_STORE9_SEQCOMPLETE_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ + ("IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 0); + + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ); + } + } + if (int_stat[0] & 0xff00) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_EXTDST1_SHDLOAD_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_SHDLOAD_IRQ irq\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_SHDLOAD_IRQ); + } + if (int_stat[0] & + INTSTAT0_BIT( + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ\n"); + /* todo: move */ + imxdpuv1_disp_check_shadow_loads(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + if (int_stat[0] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN0_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN0_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 0); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN0_INT0_IRQ); + } + + } + if (int_stat[0] & 0xff000000) { + if (int_stat[1] & + INTSTAT0_BIT(IMXDPUV1_FRAMEGEN1_INT0_IRQ)) { + IMXDPUV1_TRACE_IRQ( + "IMXDPUV1_FRAMEGEN1_INT0_IRQ\n"); + imxdpuv1_disp_vsync_handler(imxdpuv1_id, 1); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_FRAMEGEN1_INT0_IRQ); + } + } + } + + if (int_stat[1] != 0) { + if (int_stat[1] & 0xff) { + if (int_stat[0] & + INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW0_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW0_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW0_IRQ); + } + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW2_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW2_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW2_IRQ); + } + } + if (int_stat[1] & 0xff00) { + if (int_stat[1] & INTSTAT1_BIT(IMXDPUV1_COMCTRL_SW3_IRQ)) { + IMXDPUV1_TRACE_IRQ("IMXDPUV1_COMCTRL_SW3_IRQ\n"); + imxdpuv1_handle_registered_irq(imxdpuv1_id, + IMXDPUV1_COMCTRL_SW3_IRQ); + } + } + if (int_stat[0] & 0xff0000) { + /* Reserved for command sequencer debug */ + } + } +#endif + return IMXDPUV1_TRUE; +} + +/*! + * This function registers an interrupt handler function for the specified + * irq line. The interrupt lines are defined in imxdpuv1_events.h + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to get status for. + * + * @param handler Input parameter for address of the handler + * function. + * + * @param irq_flags Flags for interrupt mode. Currently not used. + * + * @param devname Input parameter for string name of driver + * registering the handler. + * + * @param data Input parameter for pointer of data to be + * passed to the handler. + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_request_irq(int8_t imxdpuv1_id, + uint32_t irq, + int (*handler)(int, void *), + uint32_t irq_flags, const char *devname, void *data) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (imxdpu->irq_list[irq].handler != NULL) { + IMXDPUV1_TRACE("handler already installed on irq %d\n", irq); + ret = -EINVAL; + goto out; + } + + imxdpu->irq_list[irq].handler = handler; + imxdpu->irq_list[irq].flags = irq_flags; + imxdpu->irq_list[irq].data = data; + imxdpu->irq_list[irq].name = devname; + + /* Clear and enable the IRQ */ + imxdpuv1_clear_irq(imxdpuv1_id, irq); + /* Don't enable if a one shot */ + if ((imxdpu->irq_list[irq].flags & IMXDPUV1_IRQF_ONESHOT) == 0) + imxdpuv1_enable_irq(imxdpuv1_id, irq); +out: + return ret; +} + +/*! + * This function unregisters an interrupt handler for the specified interrupt + * line. The interrupt lines are defined in imxdpuv1_events.h + * + * @param imxdpu imxdpu instance + * @param irq Interrupt line to get status for. + * + * @param data Input parameter for pointer of data to be passed + * to the handler. This must match value passed to + * ipu_request_irq(). + * + */ +int imxdpuv1_free_irq(int8_t imxdpuv1_id, uint32_t irq, void *data) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpuv1_disable_irq(imxdpuv1_id, irq); + imxdpuv1_clear_irq(imxdpuv1_id, irq); + if (imxdpu->irq_list[irq].data == data) + memset(&imxdpu->irq_list[irq], 0, sizeof(imxdpu->irq_list[irq])); + + return ret; +} + +/*! + * This function un-initializes the imxdpu interrupts + * + * @param imxdpu imxdpu instance + * + */ +int imxdpuv1_uninit_interrupts(int8_t imxdpuv1_id) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + imxdpu->enabled_int[0] = 0; + imxdpu->enabled_int[1] = 0; +#ifdef IMXDPUV1_VERSION_0 + imxdpu->enabled_int[2] = 0; +#endif + imxdpuv1_clear_all_irqs(imxdpuv1_id); + + /* Set all interrupt to user mode */ + imxdpuv1_write(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK); + imxdpuv1_write(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK2_USERINTERRUPTMASK2_MASK); +#endif + /* Set all interrupts to user mode. this will to change to + enable panic mode */ + imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0, 0); + imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1, 0); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_COMCTRL_USERINTERRUPTENABLE2, 0); +#endif + /* enable needed interupts */ + return ret; +} + +/*! + * This function initializes the imxdpu and the required data structures + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +/* todo: replace with probe function or call from probe + use device tree as needed */ +int imxdpuv1_init(int8_t imxdpuv1_id) +{ + int ret = 0; + int i; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + /* todo: add resource mapping for xrdc, layers, blit, display, ... */ + + /* imxdpuv1_id starts from 0 */ + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + + /* Map the channels to display streams + todo: + make this mapping dynamic + add channel features + map capture channels + */ + for (i = IMXDPUV1_CHAN_IDX_IN_FIRST; i < IMXDPUV1_CHAN_IDX_MAX; i++) { + if (i <= IMXDPUV1_CHAN_IDX_17) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0; + else if (i < IMXDPUV1_CHAN_IDX_IN_MAX) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 1; + else if (i < IMXDPUV1_CHAN_IDX_OUT_FIRST) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0; + else if (i < IMXDPUV1_CHAN_IDX_OUT_MAX) + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 1; + else + imxdpuv1_array[imxdpuv1_id].chan_data[i].disp_id = 0; + } + + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + imxdpu->irq_count = 0; + + if (imxdpuv1_id == 0) { + imxdpu->base = (void __iomem *)IMXDPUV1_REGS_BASE_PHY0; + IMXDPUV1_TRACE("%s(): virtual base address is 0x%p (0x%08x physical)\n", + __func__, imxdpu->base, IMXDPUV1_REGS_BASE_PHY0); + + } else if (imxdpuv1_id == 1) { + imxdpu->base = (void __iomem *)IMXDPUV1_REGS_BASE_PHY1; + IMXDPUV1_TRACE("%s(): virtual base address is 0x%p (0x%08x physical)\n", + __func__, imxdpu->base, IMXDPUV1_REGS_BASE_PHY1); + + } else { + return -ENOMEM; + } + + /* todo: may need to check resource allocaiton/ownership for these */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7, + IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE, + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY0, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY0_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY1, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY1_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY2, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY2_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY3, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY3_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY4, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY4_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY5, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY5_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY6, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY6_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_LAYERPROPERTY7, + IMXDPUV1_FETCHLAYER1_LAYERPROPERTY7_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE, + IMXDPUV1_FETCHLAYER1_TRIGGERENABLE_RESET_VALUE); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY0, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY1, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY2, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY3, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY4, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY5, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY6, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_LAYERPROPERTY7, + IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_VALUE); + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE, + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_VALUE); + + /* Initial StaticControl configuration - reset values */ + /* IMXDPUV1_FETCHDECODE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE9_STATICCONTROL, + IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_FETCHPERSP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHPERSP9_STATICCONTROL, + IMXDPUV1_FETCHPERSP9_STATICCONTROL_RESET_VALUE); +#else + /* IMXDPUV1_FETCHPERSP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP9_STATICCONTROL, + IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_VALUE); +#endif + + /* IMXDPUV1_FETCHECO9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_ROP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_ROP9_STATICCONTROL, + IMXDPUV1_ROP9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_CLUT9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_STATICCONTROL, + IMXDPUV1_CLUT9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_MATRIX9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_MATRIX9_STATICCONTROL, + IMXDPUV1_MATRIX9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_HSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_HSCALER9_STATICCONTROL, + IMXDPUV1_HSCALER9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_VSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_VSCALER9_STATICCONTROL, + IMXDPUV1_VSCALER9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FILTER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FILTER9_STATICCONTROL, + IMXDPUV1_FILTER9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_BLITBLEND9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_BLITBLEND9_STATICCONTROL, + IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_STORE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE9_STATICCONTROL, + IMXDPUV1_STORE9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_CONSTFRAME0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME0_STATICCONTROL, + IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST0_STATICCONTROL, + IMXDPUV1_EXTDST0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST4_STATICCONTROL, + IMXDPUV1_EXTDST4_STATICCONTROL_RESET_VALUE); + + /* todo: IMXDPUV1_CONSTFRAME4_STATICCONTROL */ + + /* IMXDPUV1_CONSTFRAME1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME1_STATICCONTROL, + IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST1_STATICCONTROL, + IMXDPUV1_EXTDST1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTDST5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST5_STATICCONTROL, + IMXDPUV1_EXTDST5_STATICCONTROL_RESET_VALUE); + + /* todo: IMXDPUV1_CONSTFRAME5_STATICCONTROL */ +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_EXTSRC4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC4_STATICCONTROL, + IMXDPUV1_EXTSRC4_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_STORE4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE4_STATICCONTROL, + IMXDPUV1_STORE4_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_EXTSRC5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC5_STATICCONTROL, + IMXDPUV1_EXTSRC5_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_STORE5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE5_STATICCONTROL, + IMXDPUV1_STORE5_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE2_STATICCONTROL, + IMXDPUV1_FETCHDECODE2_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE3_STATICCONTROL, + IMXDPUV1_FETCHDECODE3_STATICCONTROL_RESET_VALUE); +#endif + /* IMXDPUV1_FETCHWARP2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_STATICCONTROL, + IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHECO2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE0_STATICCONTROL, + IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHECO0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO0_STATICCONTROL, + IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHDECODE1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE1_STATICCONTROL, + IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_FETCHECO1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO1_STATICCONTROL, + IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_VALUE); + + /* todo: IMXDPUV1_MATRIX5_STATICCONTROL */ + /* todo: IMXDPUV1_HSCALER5_STATICCONTROL */ + /* todo: IMXDPUV1_VSCALER5_STATICCONTROL */ + /* IMXDPUV1_LAYERBLEND0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND0_STATICCONTROL, + IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND1_STATICCONTROL, + IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND2_STATICCONTROL, + IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND3_STATICCONTROL, + IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_LAYERBLEND4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND5_STATICCONTROL, + IMXDPUV1_LAYERBLEND5_STATICCONTROL_RESET_VALUE); + + /* IMXDPUV1_LAYERBLEND6_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND6_STATICCONTROL, + IMXDPUV1_LAYERBLEND6_STATICCONTROL_RESET_VALUE); +#endif + /* Dynamic config */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHPERSP9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#else + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC, + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC, + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE2_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE3_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_GAMMACOR4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HISTOGRAM4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_GAMMACOR5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_HISTOGRAM5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#endif + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_DYNAMIC, + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL, + IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_CLKEN, + IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC)); +#endif + /* Static configuration - reset values */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_STATIC, + IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_STATIC, + IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_VALUE); +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_STATIC, + IMXDPUV1_PIXENGCFG_STORE4_STATIC_RESET_VALUE); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_STATIC, + IMXDPUV1_PIXENGCFG_STORE5_STATIC_RESET_VALUE); +#endif + /* Static configuration - initial settings */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE9_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE, + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET, + IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE, + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__AUTO) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET, + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); + + /* todo: IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_OFFSET */ + + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE, + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__AUTO) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET, + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); + + /* todo: IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_OFFSET */ +#ifdef IMXDPUV1_VERSION_0 + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_STATIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_POWERDOWN, + IMXDPUV1_FALSE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SYNC_MODE, + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SYNC_MODE__SINGLE) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SW_RESET, + IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_SW_RESET__OPERATION) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_STORE4_STATIC_STORE4_DIV, + IMXDPUV1_PIXENGCFG_DIVIDER_RESET)); +#endif + /* todo: IMXDPUV1_PIXENGCFG_STORE4_STATIC */ + /* Static Control configuration */ + /* IMXDPUV1_FETCHDECODE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_FETCHPERSP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHPERSP9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHPERSP9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHPERSP9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#else + /* IMXDPUV1_FETCHWARP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#endif + /* IMXDPUV1_FETCHECO9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_ROP9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_ROP9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_ROP9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_CLUT9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_STATICCONTROL_SHDEN, 1)); + + imxdpuv1_write(imxdpu, IMXDPUV1_CLUT9_UNSHADOWEDCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN, + IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__ENABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN, + IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__ENABLE) + | IMXDPUV1_SET_FIELD(IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN, + IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__ENABLE)); + + /* IMXDPUV1_MATRIX9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_MATRIX9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_HSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_HSCALER9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_VSCALER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_VSCALER9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_FILTER9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FILTER9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FILTER9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_BLITBLEND9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_BLITBLEND9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_STORE9_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1)); + + /* IMXDPUV1_CONSTFRAME0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_EXTDST0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE, + IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__EXTERNAL)); + + /* todo: IMXDPUV1_CONSTFRAME4_STATICCONTROL */ + /* todo: IMXDPUV1_EXTDST4_STATICCONTROL */ + + /* IMXDPUV1_CONSTFRAME1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_CONSTFRAME1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN, 1)); + + /* IMXDPUV1_EXTDST1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTDST1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE, + IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__EXTERNAL)); + + /* todo: IMXDPUV1_CONSTFRAME5_STATICCONTROL */ + /* todo: IMXDPUV1_EXTDST5_STATICCONTROL */ +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_EXTSRC4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL, + IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL__LOCAL)); + + /* IMXDPUV1_STORE4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE4_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE4_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1)); + + /* IMXDPUV1_EXTSRC5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_EXTSRC5_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC5_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC5_STATICCONTROL_STARTSEL, + IMXDPUV1_EXTSRC5_STATICCONTROL_STARTSEL__LOCAL)); + + /* IMXDPUV1_STORE5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_STORE5_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE5_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE5_STATICCONTROL_BASEADDRESSAUTOUPDATE, 1)); + + /* IMXDPUV1_FETCHDECODE2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE2_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE2_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE2_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHDECODE3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE3_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE3_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE3_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); +#endif + /* IMXDPUV1_FETCHWARP2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY, 0)); + + /* IMXDPUV1_FETCHECO2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO9_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHDECODE0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE, + 0)); + + /* IMXDPUV1_FETCHECO0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHDECODE1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHDECODE1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHECO1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHECO1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0)); + + /* IMXDPUV1_FETCHLAYER0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY, 0)); +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_FETCHLAYER1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHLAYER1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER1_STATICCONTROL_BASEADDRESSAUTOUPDATE, 0) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHLAYER1_STATICCONTROL_SHDLDREQSTICKY, 0)); + + /* IMXDPUV1_GAMMACOR4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR4_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR4_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR4_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR4_STATICCONTROL_REDWRITEENABLE, 1)); +#endif + /* todo: IMXDPUV1_MATRIX4_STATICCONTROL */ + /* todo: IMXDPUV1_HSCALER4_STATICCONTROL */ + /* todo: IMXDPUV1_VSCALER4_STATICCONTROL */ +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_GAMMACOR5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR5_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR5_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR5_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR5_STATICCONTROL_REDWRITEENABLE, 1)); +#endif + /* todo: IMXDPUV1_MATRIX5_STATICCONTROL */ + /* todo: IMXDPUV1_HSCALER5_STATICCONTROL */ + /* todo: IMXDPUV1_VSCALER5_STATICCONTROL */ + + /* IMXDPUV1_LAYERBLEND0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND0_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND1_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND2_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND2_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND3_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND3_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__BOTH)); + +#ifdef IMXDPUV1_VERSION_0 + /* IMXDPUV1_LAYERBLEND4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND4_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND4_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND4_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND5_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND5_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND5_STATICCONTROL_SHDTOKSEL__BOTH)); + + /* IMXDPUV1_LAYERBLEND6_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_LAYERBLEND6_STATICCONTROL, + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDEN, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDLDSEL, + IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDLDSEL__SECONDARY) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDTOKSEL, + IMXDPUV1_LAYERBLEND6_STATICCONTROL_SHDTOKSEL__BOTH)); +#endif + /* todo: IMXDPUV1_EXTSRC0_STATICCONTROL */ + /* todo: IMXDPUV1_EXTSRC1_STATICCONTROL */ + /* todo: IMXDPUV1_MATRIX0_STATICCONTROL */ + /* IMXDPUV1_GAMMACOR0_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR0_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE, 1)); + /* todo: IMXDPUV1_SIG0_STATICCONTROL */ + /* todo: IMXDPUV1_MATRIX1_STATICCONTROL */ + /* IMXDPUV1_GAMMACOR1_STATICCONTROL */ + imxdpuv1_write(imxdpu, IMXDPUV1_GAMMACOR1_STATICCONTROL, + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE, 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE, 1)); + /* IMXDPUV1_SIG1_STATICCONTROL */ + + imxdpuv1_init_irqs(imxdpuv1_id); + + return ret; +} + +int imxdpuv1_init_sync_panel(int8_t imxdpuv1_id, + int8_t disp, + uint32_t pixel_fmt, struct imxdpuv1_videomode mode) +{ + int ret = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + return ret; +} + +int imxdpuv1_uninit_sync_panel(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + return ret; +} + +int imxdpuv1_reset_disp_panel(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + return ret; +} + +/*! + * This function initializes the display + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_init(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + struct imxdpuv1_videomode *mode; + int reg = 0; + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + mode = &imxdpu->video_mode[disp]; + /*imxdpuv1_disp_dump_mode(&imxdpu->video_mode[disp]);*/ + + if (disp == 0) { +#ifdef IMXDPUV1_TCON0_MAP_24BIT_0_23 + /* Static 24-bit TCON bit mapping for FPGA */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT7_4, 0x1d1c1b1a); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT3_0, 0x19181716); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT15_12, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT11_8, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT23_20, 0x09080706); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT19_16, 0x05040302); +#else + /* tcon mapping + * RR RRRR RRRR GGGG GGGG GGBB BBBB BBBB + * 98 7654 3210 9876 5432 1098 7654 3210 + * bits + * 00 0000 0000 1111 1111 1122 2222 2222 + * 98 7654 3210 8765 5432 1098 7654 3210 + */ + /* 30-bit timing controller setup */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT31_28, 0x00000908); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT27_24, 0x07060504); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT23_20, 0x03020100); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT19_16, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT15_12, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT11_8, 0x0b0a1d1c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT7_4, 0x1b1a1918); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON0_MAPBIT3_0, 0x17161514); + +#endif + + /* set data enable polarity */ + if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__HIGH); + else + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0, + IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__LOW); + + imxdpuv1_write(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL0, reg); + /* printf("polreg=0x%x\n", imxdpuv1_read(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL0)); */ + + } else if (disp == 1) { +#ifdef IMXDPUV1_TCON1_MAP_24BIT_0_23 + /* Static TCON bit mapping */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT7_4, 0x1d1c1b1a); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT3_0, 0x19181716); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT15_12, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT11_8, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT23_20, 0x09080706); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT19_16, 0x05040302); +#else + /* tcon mapping + * RR RRRR RRRR GGGG GGGG GGBB BBBB BBBB + * 98 7654 3210 9876 5432 1098 7654 3210 + * bits + * 00 0000 0000 1111 1111 1122 2222 2222 + * 98 7654 3210 8765 5432 1098 7654 3210 + */ + /* 30-bit timing controller setup */ + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT31_28, 0x00000908); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT27_24, 0x07060504); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT23_20, 0x03020100); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT19_16, 0x13121110); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT15_12, 0x0f0e0d0c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT11_8, 0x0b0a1d1c); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT7_4, 0x1b1a1918); + imxdpuv1_write(imxdpu, IMXDPUV1_TCON1_MAPBIT3_0, 0x17161514); +#endif + /* set data enable polarity */ + if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__HIGH); + else + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__LOW); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__HIGH); + else + reg |= IMXDPUV1_SET_FIELD( + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1, + IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__LOW); + + imxdpuv1_write(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL1, reg); + /* printf("polreg=0x%x\n", imxdpuv1_read(imxdpu, IMXDPUV1_DISENGCFG_POLARITYCTRL1)); */ + + } else { + return -EINVAL; + } + /* todo: initialize prefetch */ + + return ret; +} + +int imxdpuv1_disp_setup_tcon_bypass_mode( + int8_t imxdpuv1_id, + int8_t disp, + const struct imxdpuv1_videomode *mode) +{ + struct imxdpuv1_soc *imxdpu; + uint32_t b_off; /* block offset for tcon generator */ + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_TCON0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_TCON1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_TCON_CTRL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE, + IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__BALANCED) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE, + IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION, + 0x140)); + /* setup hsync */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0POSON_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0, mode->hlen + mode->hfp)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0MASKON_OFFSET, 0xffff); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0, mode->hlen + mode->hfp + mode->hsync)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG0MASKOFF_OFFSET, 0xffff); + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX0SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0, 2)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX0FCTTABLE_OFFSET, 1); + + /* Setup Vsync */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1POSON_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1, mode->hlen + mode->hfp + mode->hsync) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1, mode->vlen + mode->vfp - 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1MASKON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1, mode->hlen + mode->hfp + mode->hsync)| + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1, mode->vlen + mode->vfp + mode->vsync - 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG1MASKOFF_OFFSET, 0); + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX1SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0, 3)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX1FCTTABLE_OFFSET, 1); + + /* data enable horizontal */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2POSON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2MASKON_OFFSET, 0xffff); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2, mode->hlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG2MASKOFF_OFFSET, 0xffff); + /* data enable vertical */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3POSON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3MASKON_OFFSET, 0x7fff0000); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3, mode->vlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG3MASKOFF_OFFSET, 0x7fff0000); + + /* use both SPG2 and SPG3 to generate data enable */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX2SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0, 4)| + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1, 5)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX2FCTTABLE_OFFSET, 8); + + /* shadow load trigger (aka kachunk) */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4POSON_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4, 10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4, mode->vlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4MASKON_OFFSET, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4POSOFF_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4, 26) | + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4, mode->vlen)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SPG4MASKOFF_OFFSET, 0); + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX3SIGS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0, 6)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_TCON0_SMX3FCTTABLE_OFFSET, 2); + + return 0; +} + +/*! + * This function sets up the frame generator + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param enable state to set frame generator to + * @param mode to set the display to + * @param cc_red constant color red + * @param cc_green constant color green + * @param cc_blue constant color blue + * @param cc_alpha constant color alpha +* + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_frame_gen( + int8_t imxdpuv1_id, + int8_t disp, + const struct imxdpuv1_videomode *mode, + uint16_t cc_red, /* 10 bits */ + uint16_t cc_green, /* 10 bits */ + uint16_t cc_blue, /* 10 bits */ + uint8_t cc_alpha, + bool test_mode_enable) +{ /* 1 bits, yes 1 bit */ + int ret = 0; + uint32_t b_off; /* block offset for frame generator */ + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + /* todo: + add video mode sanity check here + check if LRSYNC is required + */ + + if (mode->flags & IMXDPUV1_MODE_FLAGS_LRSYNC) { + /* todo: here we need to use two outputs to make one */ + if (disp == 0) { + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE, + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__MASTER); + } else { + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE, + IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_CYC); + } + } else { + reg = IMXDPUV1_SET_FIELD( + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE, + IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__OFF); + } + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGSTCTRL_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG1_HACT, mode->hlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL, + (mode->hlen + mode->hfp + mode->hbp + mode->hsync - 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_HTCFG1_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC, + mode->hsync - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP, + mode->hbp + mode->hsync - 1) | + /* shadow enable */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_HTCFG2_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG1_VACT, mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL, + (mode->vlen + mode->vfp + mode->vbp + mode->vsync - + 1)); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_VTCFG1_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC, + mode->vsync - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP, + mode->vbp + mode->vsync - 1) | + /* shadow enable */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_VTCFG2_OFFSET, reg); + + /* Interupt at position (0, vlen - 3) for end of frame interrupt */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW, + mode->vlen - 3) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT0CONFIG_OFFSET, reg); + + /* Interupt at position 1, mode->vlen */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW, + mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT1CONFIG_OFFSET, reg); + + /* Interupt at position 2, mode->vlen */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL, 2) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW, + mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT2CONFIG_OFFSET, reg); + + /* Interupt at position 3, mode->vlen */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL, 3) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW, + mode->vlen) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_INT3CONFIG_OFFSET, reg); + + /* todo: these need to be checked + _SKICKCOL for verification: =(FW - 40) , for ref driver = 1 ? + _SKICKROW for verif. =(FH - 1), ref driver = vlen-2 + */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL, + mode->hlen - 40) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW, + mode->vlen + 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_SKICKCONFIG_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_PACFG_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX, 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY, 1); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_SACFG_OFFSET, reg); + + if (IMXDPUV1_ENABLE == test_mode_enable) { + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM, + IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__TEST); + } else { + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM, + IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA, 0); + } + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGINCTRL_OFFSET, reg); + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC, + IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__CONSTCOL) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC, 0); + imxdpuv1_write(imxdpu, b_off + + IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_OFFSET, reg); + + /* Set the constant color - ARGB 1-10-10-10 */ + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCRED, cc_red) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE, cc_blue) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN, cc_green) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA, cc_alpha); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGCCR_OFFSET, reg); + + + imxdpuv1_disp_setup_tcon_bypass_mode(imxdpuv1_id, disp, mode); + + /* save the mode */ + imxdpu->video_mode[disp] = *mode; + + /* imxdpuv1_disp_dump_mode(&imxdpu->video_mode[disp]); */ + + return ret; +} + +/*! + * This function updates the frame generator status + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_update_fgen_status(int8_t imxdpuv1_id, int8_t disp) +{ + int ret = 0; + uint32_t b_off; /* block offset for frame generator */ + uint32_t reg; + uint32_t temp; + struct imxdpuv1_soc *imxdpu; + static uint32_t fcount[IMXDPUV1_NUM_DI_MAX] = { 0, 0 }; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + /* todo: + add video mode sanity check here + check if LRSYNC is required + */ + + reg = imxdpuv1_read_irq(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_OFFSET); + IMXDPUV1_TRACE_IRQ("DISP %d: findex %d, lindex %d\n", disp, + IMXDPUV1_GET_FIELD + (IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX, reg), + IMXDPUV1_GET_FIELD + (IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX, reg)); + + temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX, reg); + if (temp != fcount[disp]) { + fcount[disp] = temp; + /* Just increment we assume this is called one per frame */ + imxdpu->fgen_stats[disp].frame_count++; + } + + reg = imxdpuv1_read_irq(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGCHSTAT_OFFSET); + temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT, reg); + + /* Sync status bits should be set */ + if ((temp != imxdpu->fgen_stats[disp].sec_sync_state) && (temp == 1)) { + imxdpu->fgen_stats[disp].sec_sync_count++; + IMXDPUV1_TRACE_IRQ("DISP %d: sec in sync\n", disp); + } + if ((temp != imxdpu->fgen_stats[disp].sec_sync_state) && (temp == 0)) { + IMXDPUV1_TRACE_IRQ("DISP %d: sec out of sync\n", disp); + } + imxdpu->fgen_stats[disp].sec_sync_state = temp; + temp = IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT, reg); + + /* Sync status bits should be set */ + if ((temp != imxdpu->fgen_stats[disp].prim_sync_state) && + (temp == 1)) { + imxdpu->fgen_stats[disp].prim_sync_count++; + IMXDPUV1_TRACE_IRQ("DISP %d: prim in sync\n", disp); + } + if ((temp != imxdpu->fgen_stats[disp].prim_sync_state) && + (temp == 0)) { + IMXDPUV1_TRACE_IRQ("DISP %d: prim out of sync\n", disp); + } + imxdpu->fgen_stats[disp].prim_sync_state = temp; + + /* primary fifo bit should be clear if in use (panic stream) */ + if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY, reg)) { + IMXDPUV1_TRACE_IRQ("DISP %d: primary fifo empty\n", disp); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET, + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_MASK); + imxdpu->fgen_stats[disp].prim_fifo_empty_count++; + } + /* secondary fifo and skew error bits should be clear + if in use (content stream) */ + if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY, reg) || + IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR, reg)) { + if (IMXDPUV1_GET_FIELD(IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY, reg)) { + IMXDPUV1_TRACE_IRQ("DISP %d: secondary fifo empty\n", + disp); + imxdpu->fgen_stats[disp].sec_fifo_empty_count++; + } + if (IMXDPUV1_GET_FIELD + (IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR, reg)) { + IMXDPUV1_TRACE_IRQ("DISP %d: secondary skew error\n", + disp); + imxdpu->fgen_stats[disp].skew_error_count++; + } + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET, + IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_MASK); + } + return ret; +} +/*! + * This function sets up the frame capture + * + * @param imxdpuv1_id id of the diplay unit + * @param src_id id of the capture source block + * @param dest_id id of the capture dest block + * @param sync_count number of valid required to aquire sync + * @param cap_mode mode of the video input + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_setup_frame( + int8_t imxdpuv1_id, + int8_t src_id, + int8_t dest_id, + int8_t sync_count, + const struct imxdpuv1_videomode *cap_mode) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + uint32_t b_off_frame; /* block offset for capture source */ + uint32_t b_off_extsrc; /* block offset for extsrc */ + + int8_t cap_id; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (src_id == IMXDPUV1_ID_FRAMECAP4) { + cap_id = 0; + b_off_frame = IMXDPUV1_FRAMECAP4_LOCKUNLOCK; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMECAP5) { + cap_id = 1; + b_off_frame = IMXDPUV1_FRAMECAP5_LOCKUNLOCK; + b_off_extsrc = IMXDPUV1_EXTSRC5_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP0) { + cap_id = 0; + b_off_frame = IMXDPUV1_FRAMEDUMP0_CONTROL; + b_off_extsrc = IMXDPUV1_EXTSRC0_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP1) { + cap_id = 1; + b_off_frame = IMXDPUV1_FRAMEDUMP1_CONTROL; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else { + return -EINVAL; + } + + if (dest_id == IMXDPUV1_ID_STORE4) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC_STORE4_SRC_SEL__EXTSRC4); + } else if (dest_id == IMXDPUV1_ID_STORE5) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC_STORE5_SRC_SEL__EXTSRC5); + } else if (dest_id == IMXDPUV1_ID_EXTDST0) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, + IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC4); + } else if (dest_id == IMXDPUV1_ID_EXTDST1) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, + IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC5); + } else { + return -EINVAL; + } + + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_STATICCONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL, + IMXDPUV1_EXTSRC4_STATICCONTROL_STARTSEL__LOCAL) | + IMXDPUV1_EXTSRC4_STATICCONTROL_SHDEN_MASK); + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_CONSTANTCOLOR_OFFSET, 0); + + if (cap_mode->format == IMXDPUV1_PIX_FMT_BGR24) { + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSRED, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSGREEN, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSBLUE, 0x8)); + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE, 0x00)); + + /* fixme: handle all cases for control */ + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_YUVCONVERSIONMODE, + IMXDPUV1_EXTSRC4_CONTROL_YUVCONVERSIONMODE__ITU601) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE, + IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE__YUV422) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_YUV422UPSAMPLINGMODE, + IMXDPUV1_EXTSRC4_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE) | + IMXDPUV1_EXTSRC4_CONTROL_CLIPWINDOWENABLE_MASK); + + } else if (cap_mode->format == IMXDPUV1_PIX_FMT_YUYV) { + + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_OFFSET, + + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSRED, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSGREEN, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTBITS_COMPONENTBITSBLUE, 0x8)); + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE, 0x0)); + + /* fixme: handle all cases for control */ + imxdpuv1_write(imxdpu, + b_off_extsrc + IMXDPUV1_EXTSRC4_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE, + IMXDPUV1_EXTSRC4_CONTROL_RASTERMODE__YUV422) | + IMXDPUV1_EXTSRC4_CONTROL_CLIPWINDOWENABLE_MASK); + + } else { + IMXDPUV1_PRINT("%s(): invalid capture interface format\n", __func__); + return -EINVAL; + } + + + if ((src_id == IMXDPUV1_ID_FRAMECAP4) || (src_id == IMXDPUV1_ID_FRAMECAP5)) { + /* setup cature */ + uint8_t capture_interface_mode; + /* Fixme: change these mode bits to an enumeration */ + if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_32BIT) != 0) { + capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ENHSVS_32BIT; + } else if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_BT656_10BIT) != 0) { + capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ITU656_10BIT; + } else if ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_BT656_8BIT) != 0) { + capture_interface_mode = IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1__ITU656_8BIT; + } else { + return -EINVAL; + } + + if (cap_id == 0) { + imxdpuv1_write(imxdpu, IMXDPUV1_CAPENGCFG_CAPTUREINPUT0, + IMXDPUV1_SET_FIELD(IMXDPUV1_CAPENGCFG_CAPTUREINPUT0_CAPTUREMODE0, + capture_interface_mode)); + } else { + imxdpuv1_write(imxdpu, IMXDPUV1_CAPENGCFG_CAPTUREINPUT1, + IMXDPUV1_SET_FIELD(IMXDPUV1_CAPENGCFG_CAPTUREINPUT1_CAPTUREMODE1, + capture_interface_mode)); + } + + imxdpuv1_write(imxdpu, b_off_frame + IMXDPUV1_FRAMECAP4_FDR_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_HEIGHT, cap_mode->vlen - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_WIDTH, cap_mode->hlen - 1)); + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_FDR1_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_FDR_HEIGHT, cap_mode->vlen1 - 1)); + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_SCR_OFFSET, sync_count); + + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_KCR_OFFSET, 0); + if ((cap_mode->clip_height != 0) && (cap_mode->clip_width != 0)) { + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWHEIGHT, cap_mode->clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWWIDTH, cap_mode->clip_width - 1)); + + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWXOFFSET, cap_mode->clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWYOFFSET, cap_mode->clip_top)); + } + + imxdpuv1_write(imxdpu, + b_off_frame + IMXDPUV1_FRAMECAP4_SPR_OFFSET, + + /* low is active low, high is active high */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLHS, + ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) != 0)) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLVS, + ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) != 0)) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_SPR_POLEN, + ((cap_mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) == 0)) + ); + + + /* fixme: may need to move this mapping */ + if (src_id == IMXDPUV1_ID_FRAMECAP4) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE4_DYNAMIC_STORE4_SRC_SEL__EXTSRC4); + } else if (src_id == IMXDPUV1_ID_FRAMECAP5) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC, + IMXDPUV1_PIXENGCFG_STORE5_DYNAMIC_STORE5_SRC_SEL__EXTSRC5); + } + } + + if ((src_id == IMXDPUV1_ID_FRAMEDUMP0) || (src_id == IMXDPUV1_ID_FRAMEDUMP1)) { + /* todo */ + } + + /* save the mode */ + imxdpu->capture_mode[cap_id] = *cap_mode; + /* imxdpuv1_disp_dump_mode(cap_mode); */ + return ret; +#endif +} + +/*! + * This function sets up the frame capture + * + * @param imxdpuv1_id id of the diplay unit + * @param cap id of the capture inpute + * @param sync_count number of valid required to aquire sync + * @param cap_mode mode of the video input + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_setup_crop( + int8_t imxdpuv1_id, + int8_t src_id, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + uint32_t b_off_extsrc; /* block offset for extsrc */ +#if 0 + uint32_t b_off_dest; /* block offset for destination */ +#endif + int8_t cap_id; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (src_id == IMXDPUV1_ID_FRAMECAP4) { + cap_id = 0; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMECAP5) { + cap_id = 1; + b_off_extsrc = IMXDPUV1_EXTSRC5_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP0) { + cap_id = 0; + b_off_extsrc = IMXDPUV1_EXTSRC0_LOCKUNLOCK; + } else if (src_id == IMXDPUV1_ID_FRAMEDUMP1) { + cap_id = 1; + b_off_extsrc = IMXDPUV1_EXTSRC4_LOCKUNLOCK; + } else { + return -EINVAL; + } + + if ((src_id == IMXDPUV1_ID_FRAMECAP4) || (src_id == IMXDPUV1_ID_FRAMECAP5)) { + if ((clip_height != 0) && (clip_width != 0)) { + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWHEIGHT, clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWDIMENSION_CLIPWINDOWWIDTH, clip_width - 1)); + + imxdpuv1_write(imxdpu, b_off_extsrc + IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWXOFFSET, clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_EXTSRC4_CLIPWINDOWOFFSET_CLIPWINDOWYOFFSET, clip_top)); + /* save the clip data */ + imxdpu->capture_mode[cap_id].clip_height = clip_height; + imxdpu->capture_mode[cap_id].clip_width = clip_width; + imxdpu->capture_mode[cap_id].clip_top = clip_top; + imxdpu->capture_mode[cap_id].clip_left = clip_left; + } + } + + if ((src_id == IMXDPUV1_ID_FRAMEDUMP0) || (src_id == IMXDPUV1_ID_FRAMEDUMP1)) { + /* todo */ + } + /* imxdpuv1_disp_dump_mode(&imxdpu->video_mode[cap_id]); */ + return ret; +#endif +} +/*! + * This function enables the frame capture + * + * @param imxdpuv1_id id of the display unit + * @param cap id of the capture output pipe + * @param enable state to set frame generator to + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_enable(int8_t imxdpuv1_id, int8_t cap, bool enable) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + uint32_t b_off; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (cap == 0) { + b_off = IMXDPUV1_FRAMECAP4_LOCKUNLOCK; + } else { + return -EINVAL; + } + + if (enable) { + /* imxdpuv1_dump_pixencfg_status(imxdpuv1_id); */ + printf("%s(): %s:%d stubbed feature\n", __func__, __FILE__, __LINE__); + /* imxdpuv1_dump_pixencfg_status(imxdpuv1_id); */ + } + reg = enable ? IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_CTR_CEN, 1) : + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMECAP4_CTR_CEN, 0); + + + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMECAP4_CTR_OFFSET, reg); + + return ret; +#endif +} + +/*! + * This function triggers a shadow load + * + * @param imxdpuv1_id id of the diplay unit + * @param dest_id id of the capture dest block + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_cap_request_shadow_load(int8_t imxdpuv1_id, int8_t dest_id, uint32_t mask) +{ +#ifndef IMXDPUV1_VERSION_0 + return -EINVAL; +#else + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + switch (dest_id) { + case IMXDPUV1_ID_STORE4: + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE4_REQUEST, + mask); + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE4_TRIGGER, + IMXDPUV1_PIXENGCFG_STORE4_TRIGGER_STORE4_SYNC_TRIGGER_MASK); + break; + case IMXDPUV1_ID_STORE5: + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE5_REQUEST, + mask); + imxdpuv1_write(imxdpu, + IMXDPUV1_PIXENGCFG_STORE5_TRIGGER, + IMXDPUV1_PIXENGCFG_STORE5_TRIGGER_STORE5_SYNC_TRIGGER_MASK); + break; + + default: + return -EINVAL; + + } + return ret; +#endif +} + +/*! + * This function requests a shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param shadow_load_idx index of the shadow load requested + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_request_shadow_load(int8_t imxdpuv1_id, + int8_t disp, + imxdpuv1_shadow_load_index_t shadow_load_idx) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s(): imxdpuv1_id %d, disp %d, shadow_load_idx %d\n", + __func__, imxdpuv1_id, disp, shadow_load_idx); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + /* trigger configuration of the pipeline */ + + if ((disp == 0) || (disp == 1)) { + /* last request was complete or no request in progress, + then start a new request */ + if (imxdpu->shadow_load_state[disp][shadow_load_idx].word == 0) { + imxdpu->shadow_load_state[disp][shadow_load_idx].state. + request = IMXDPUV1_TRUE; + } else { /* check ifg the request is busy */ + IMXDPUV1_TRACE("%s(): shadow load not complete.", __func__); + return -EBUSY; + } + } else { + return -EINVAL; + } + + return ret; +} + +/*! + * This function force a shadow loads + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param shadow_load_idx index of the shadow load requested + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_force_shadow_load(int8_t imxdpuv1_id, + int8_t disp, + uint64_t mask) +{ + int ret = 0; + uint32_t addr_extdst; /* address for extdst */ + uint32_t addr_fgen; /* address for frame generator */ + uint32_t extdst = 0; + uint32_t fgen = 0; + uint32_t sub = 0; + struct imxdpuv1_soc *imxdpu; + int i; + uint64_t temp_mask; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!((disp == 0) || (disp == 1))) { + return -EINVAL; + } + + if (mask == 0) { + return -EINVAL; + } + + if (disp == 0) { + addr_fgen = IMXDPUV1_FRAMEGEN0_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST; + } else if (disp == 1) { + addr_fgen = IMXDPUV1_FRAMEGEN1_FGSLR; + addr_extdst = IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST; + } else { + return -EINVAL; + } + + for (i = 0; i < IMXDPUV1_SHDLD_IDX_MAX; i++) { + temp_mask = 1ULL << i; + if ((mask & temp_mask) == 0) + continue; + + extdst |= trigger_list[i].extdst; + sub |= trigger_list[i].sub; + + if ((i == IMXDPUV1_SHDLD_IDX_CONST0) || + (i == IMXDPUV1_SHDLD_IDX_CONST1)) { + fgen |= 1; + } + mask &= ~temp_mask; + } + + if (sub) { + IMXDPUV1_TRACE_IRQ("Fetch layer shadow request 0x%08x\n", sub); + if (sub & 0xff) { /* FETCHLAYER0 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER0_TRIGGERENABLE, + sub & 0xff); + } +#ifdef IMXDPUV1_VERSION_0 + if (sub & 0xff00) { /* FETCHLAYER1 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHLAYER1_TRIGGERENABLE, + (sub >> 8) & 0xff); + } +#endif + if (sub & 0xff0000) { /* FETCHWARP2 */ + imxdpuv1_write(imxdpu, IMXDPUV1_FETCHWARP2_TRIGGERENABLE, + (sub >> 16) & 0xff); + } + } + + if (extdst) { + IMXDPUV1_TRACE_IRQ("Extdst shadow request 0x%08x\n", extdst); + imxdpuv1_write(imxdpu, addr_extdst, extdst); + } + + if (fgen) { + IMXDPUV1_TRACE_IRQ("Fgen shadow request 0x%08x\n", fgen); + imxdpuv1_write(imxdpu, addr_fgen, fgen); + } + + return ret; +} + +/*! + * This function shows the frame generators status + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_show_fgen_status(int8_t imxdpuv1_id) +{ +#ifndef ENABLE_IMXDPUV1_TRACE + return 0; +#else + int ret = 0; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + IMXDPUV1_PRINT("IMXDPU %d stat fg0 fg1\n" + "prim_sync_state: %10d %10d\n" + "sec_sync_state: %10d %10d\n" + "prim_sync_count: %10d %10d\n" + "sec_sync_count: %10d %10d\n" + "skew_error_count: %10d %10d\n" + "prim_fifo_empty_count: %10d %10d\n" + "sec_fifo_empty_count: %10d %10d\n" + "frame_count: %10d %10d\n" + "irq_count: %10u\n\n", + imxdpuv1_id, + imxdpu->fgen_stats[0].prim_sync_state, + imxdpu->fgen_stats[1].prim_sync_state, + imxdpu->fgen_stats[0].sec_sync_state, + imxdpu->fgen_stats[1].sec_sync_state, + imxdpu->fgen_stats[0].prim_sync_count, + imxdpu->fgen_stats[1].prim_sync_count, + imxdpu->fgen_stats[0].sec_sync_count, + imxdpu->fgen_stats[1].sec_sync_count, + imxdpu->fgen_stats[0].skew_error_count, + imxdpu->fgen_stats[1].skew_error_count, + imxdpu->fgen_stats[0].prim_fifo_empty_count, + imxdpu->fgen_stats[1].prim_fifo_empty_count, + imxdpu->fgen_stats[0].sec_fifo_empty_count, + imxdpu->fgen_stats[1].sec_fifo_empty_count, + imxdpu->fgen_stats[0].frame_count, + imxdpu->fgen_stats[1].frame_count, + imxdpu->irq_count); + + return ret; +#endif +} + +/*! + * This function enables the frame generator + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param enable state to set frame generator to + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_enable_frame_gen(int8_t imxdpuv1_id, int8_t disp, bool enable) +{ + int ret = 0; + uint32_t b_off; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (disp == 0) { + b_off = IMXDPUV1_FRAMEGEN0_LOCKUNLOCK; + } else if (disp == 1) { + b_off = IMXDPUV1_FRAMEGEN1_LOCKUNLOCK; + } else { + return -EINVAL; + } + + imxdpuv1_disp_start_shadow_loads(imxdpuv1_id, disp); + + reg = enable ? IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN, 1) : + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN, 0); + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_FRAMEGEN0_FGENABLE_OFFSET, reg); + + return ret; +} + +/*! + * This function sets up the constframe generator + * + * @param imxdpuv1_id id of the diplay unit + * @param disp id of the diplay output pipe + * @param bg_red background red + * @param bg_green background green + * @param bg_blue background blue + * @param bg_alpha background alpha + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_constframe( + int8_t imxdpuv1_id, + int8_t disp, + uint8_t bg_red, + uint8_t bg_green, + uint8_t bg_blue, + uint8_t bg_alpha) +{ + int ret = 0; + uint32_t b_off; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_shadow_load_index_t shadow_idx; + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* todo: add constfram4 and constframe5 */ + if (disp == 0) { + b_off = IMXDPUV1_CONSTFRAME0_LOCKUNLOCK; + shadow_idx = IMXDPUV1_SHDLD_IDX_CONST0; + } else if (disp == 1) { + b_off = IMXDPUV1_CONSTFRAME1_LOCKUNLOCK; + shadow_idx = IMXDPUV1_SHDLD_IDX_CONST1; + } else { + return -EINVAL; + } + + if (imxdpu->video_mode[disp].flags & IMXDPUV1_MODE_FLAGS_LRSYNC) { + /* todo: need to handle sync display case */ + } + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT, + imxdpu->video_mode[disp].vlen - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH, + imxdpu->video_mode[disp].hlen - 1); + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_OFFSET, reg); + + /* todo: add linear light correction if needed */ + imxdpuv1_write(imxdpu, b_off + IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTRED, bg_red) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTGREEN, bg_green) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTBLUE, bg_blue) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_CONSTALPHA, bg_alpha)); + + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, disp, shadow_idx); + + /* todo: add linear light correction if needed */ + return ret; +} + +/*! + * This function sets up a layer + * + * @param imxdpuv1_id id of the diplay unit + * @param layer layer data to use + * @param layer_idx layer index to use + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_layer(int8_t imxdpuv1_id, + const imxdpuv1_layer_t *layer, + imxdpuv1_layer_idx_t layer_idx, + bool is_top_layer) +{ + int ret = 0; + uint32_t dynamic_offset; + uint32_t static_offset; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + IMXDPUV1_TRACE("%s(): enable %d, primary %d, secondary %d, stream 0x%08x\n", __func__, + layer->enable, + layer->primary, + layer->secondary, + layer->stream); + imxdpu->blend_layer[layer_idx] = *layer; + + dynamic_offset = id2dynamicoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (dynamic_offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + static_offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (static_offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + reg = + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL, + imxdpu->blend_layer[layer_idx].primary) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL, + imxdpu->blend_layer[layer_idx].secondary) | + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN, + IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__AUTOMATIC); + imxdpuv1_write(imxdpu, dynamic_offset, reg); + + if (imxdpu->blend_layer[layer_idx].stream & IMXDPUV1_DISPLAY_STREAM_0) { + + IMXDPUV1_TRACE("%s(): IMXDPUV1_DISPLAY_STREAM_0\n", __func__); + if (is_top_layer) { + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL, + layer_idx + IMXDPUV1_ID_LAYERBLEND0); + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC, reg); + } + + /* trigger configuration of the pipeline */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER, + IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_MASK); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, 0, + IMXDPUV1_SHDLD_IDX_DISP0); + } + if (imxdpu->blend_layer[layer_idx].stream & IMXDPUV1_DISPLAY_STREAM_1) { + IMXDPUV1_TRACE_IRQ("%s(): IMXDPUV1_DISPLAY_STREAM_1\n", __func__); + if (is_top_layer) { + reg = + IMXDPUV1_SET_FIELD(IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL, + layer_idx + IMXDPUV1_ID_LAYERBLEND0); + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC, reg); + + } + /* trigger configuration of the pipeline */ + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER, + IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_MASK); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, 1, + IMXDPUV1_SHDLD_IDX_DISP1); + } + + /* todo: add code to disable a layer */ + return ret; +} + +/*! + * This function sets global alpha for a blend layer + * + * @param imxdpuv1_id id of the diplay unit + * @param layer_idx layer index to use + * @param alpha global alpha + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_layer_global_alpha(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + uint8_t alpha) +{ + int ret = 0; + uint32_t offset; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* update imxdpu */ + + offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA, + alpha) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA) + | IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC, + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE); + imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_BLENDCONTROL_OFFSET, + reg); + + reg = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_CONTROL_MODE, + IMXDPUV1_LAYERBLEND0_CONTROL_MODE__BLEND) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE, + IMXDPUV1_DISABLE); + + imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_CONTROL_OFFSET, reg); + + return ret; +} + +/*! + * This function sets the position of the a blend layer secondary input + * + * @param imxdpuv1_id id of the diplay unit + * @param layer_idx layer index to use + * @param x x position + * @param y y position + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_layer_position(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + int16_t x, int16_t y) +{ + int ret = 0; + uint32_t offset; + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* update imxdpu */ + + offset = id2blockoffset(layer_idx + IMXDPUV1_ID_LAYERBLEND0); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + reg = IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_POSITION_XPOS, x) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERBLEND0_POSITION_YPOS, y); + imxdpuv1_write(imxdpu, offset + IMXDPUV1_LAYERBLEND0_POSITION_OFFSET, reg); + + return ret; +} + +/*! + * This function sets the position of the a channel (window) layer + * + * @param imxdpuv1_id id of the diplay unit + * @param layer_idx layer index to use + * @param x x position + * @param y y position + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_chan_position(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, int16_t x, int16_t y) +{ + int ret = 0; + uint32_t offset; + int idx; + int sub_idx; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + /* update imxdpu */ + + offset = id2blockoffset(get_channel_blk(chan)); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + idx = get_channel_idx(chan); + if ((idx >= IMXDPUV1_CHAN_IDX_IN_MAX) || (idx < 0)) { + return -EINVAL; + } + + sub_idx = imxdpuv1_get_channel_subindex(chan); + + imxdpu->chan_data[idx].dest_top = y; + imxdpu->chan_data[idx].dest_left = x; + + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0, + imxdpu->chan_data[idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0, + imxdpu->chan_data[idx].dest_top); + + if (is_fetch_layer_chan(chan) || is_fetch_warp_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer or warp\n", __func__); + imxdpuv1_write(imxdpu, + offset + IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET + + ((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)), + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0); + + } else if (is_fetch_decode_chan(chan)) { + if (imxdpu->chan_data[idx].use_eco_fetch) { + imxdpuv1_disp_set_chan_position(imxdpuv1_id, + imxdpuv1_get_eco(chan), + x, y); + } + imxdpuv1_write(imxdpu, + offset + IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET, + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0); + } else if (is_fetch_eco_chan(chan)) { + imxdpuv1_write(imxdpu, + offset + IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET, + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0); + } else { + return -EINVAL; + } + + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[idx].disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + idx); + + return ret; +} + +/*! + * This function sets the source and destination crop + * position of the a channel (window) layer + * + * @param imxdpuv1_id id of the diplay unit + * @param chan chan to use + * @param clip_top source y position + * @param clip_left source x position + * @param clip_width source width + * @param clip_height source height + * @param dest_top destination y + * @param dest_left destination x + * @param dest_width destination width + * @param dest_height destination height + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_set_chan_crop( + int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height) +{ + int ret = 0; + uint32_t offset; + int idx; + int sub_idx; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + offset = id2blockoffset(get_channel_blk(chan)); + if (offset == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + idx = get_channel_idx(chan); + if ((idx >= IMXDPUV1_CHAN_IDX_IN_MAX) || (idx < 0)) { + return -EINVAL; + } + + sub_idx = imxdpuv1_get_channel_subindex(chan); + + imxdpu->chan_data[idx].dest_top = dest_top; + imxdpu->chan_data[idx].dest_left = dest_left; + imxdpu->chan_data[idx].dest_width = IMXDPUV1_MIN(dest_width, clip_width); + imxdpu->chan_data[idx].dest_height = IMXDPUV1_MIN(dest_height, clip_height); + imxdpu->chan_data[idx].clip_top = clip_top; + imxdpu->chan_data[idx].clip_left = clip_left; + imxdpu->chan_data[idx].clip_width = IMXDPUV1_MIN(dest_width, clip_width); + imxdpu->chan_data[idx].clip_height = IMXDPUV1_MIN(dest_height, clip_height); + + /* Need to check more cases here */ + if ((imxdpu->chan_data[idx].clip_height != 0) && + (imxdpu->chan_data[idx].clip_width != 0)) { + imxdpu->chan_data[idx].fetch_layer_prop.layerproperty0 |= + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + IMXDPUV1_ENABLE); + imxdpu->chan_data[idx].fetch_layer_prop.clipwindowdimensions0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT, + imxdpu->chan_data[idx].clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH, + imxdpu->chan_data[idx].clip_width - 1); + } else { + imxdpu->chan_data[idx].fetch_layer_prop.layerproperty0 &= + ~IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_MASK; + imxdpu->chan_data[idx].fetch_layer_prop.clipwindowdimensions0 = 0; + } + imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_XOFFSET, + imxdpu->chan_data[idx].dest_left - imxdpu->chan_data[idx].clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_YOFFSET, + imxdpu->chan_data[idx].dest_top - imxdpu->chan_data[idx].clip_top); + imxdpu->chan_data[idx].fetch_layer_prop.clipwindowoffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_XOFFSET, + imxdpu->chan_data[idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_YOFFSET, + imxdpu->chan_data[idx].dest_top); + + if (is_fetch_layer_chan(chan) || is_fetch_warp_chan(chan)) { + imxdpuv1_write_block(imxdpu, + offset + + IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET + + ((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)), + (void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0, + 5); + + } else if (is_fetch_decode_chan(chan)) { + if (imxdpu->chan_data[idx].use_eco_fetch) { + imxdpuv1_disp_set_chan_crop(imxdpuv1_id, + imxdpuv1_get_eco(chan), + clip_top, + clip_left, + clip_width, + clip_height, + dest_top, + dest_left, + dest_width, + dest_height); + } + imxdpuv1_write_block(imxdpu, + offset + + IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET, + (void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0, + 5); + } else if (is_fetch_eco_chan(chan)) { + imxdpuv1_write_block(imxdpu, + offset + IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET, + (void *)&imxdpu->chan_data[idx].fetch_layer_prop.layeroffset0, + 5); + + } else { + return -EINVAL; + } + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[idx].disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + idx); + + return ret; +} + +/*! + * This function sets initializes a channel and buffer + * + * @param imxdpuv1_id id of the diplay unit + * @param chan chan to use + * @param src_pixel_fmt source pixel format + * @param clip_top source y position + * @param clip_left source x position + * @param clip_width source width + * @param clip_height source height + * @param stride stride of the buffer + * @param disp_id display id + * @param dest_top destination y + * @param dest_left destination x + * @param dest_width destination width + * @param dest_height destination height + * @param const_color constant color for clip region + * @param disp_addr display buffer physical address + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_disp_setup_channel(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t src_pixel_fmt, + uint16_t src_width, + uint16_t src_height, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + uint16_t stride, + uint8_t disp_id, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height, + uint32_t const_color, + bool use_global_alpha, + bool use_local_alpha, + unsigned int disp_addr) +{ + int ret = 0; + imxdpuv1_channel_params_t channel; + uint32_t uv_offset = 0; + + IMXDPUV1_TRACE("%s(): " + "imxdpuv1_id %d\n" + "chan_t chan %x\n" + "src_pixel_fmt 0x%x\n" + "src_width %d\n" + "src_height %d\n" + "clip_top %d\n" + "clip_left %d\n" + "clip_width %d\n" + "clip_height %d\n" + "stride %d\n" + "disp_id %d\n" + "dest_top %d\n" + "dest_left %d\n" + "dest_width %d\n" + "dest_height %d\n" + "const_color 0x%x\n" + "disp_addr 0x%x\n", + __func__, + imxdpuv1_id, + chan, + src_pixel_fmt, + src_width, + src_height, + clip_top, + clip_left, + clip_width, + clip_height, + stride, + disp_id, + dest_top, + dest_left, + dest_width, + dest_height, + const_color, + disp_addr); + + channel.common.chan = chan; + channel.common.src_pixel_fmt = src_pixel_fmt; + channel.common.src_width = src_width; + channel.common.src_height = src_height; + channel.common.clip_top = clip_top; + channel.common.clip_left = clip_left; + channel.common.clip_width = clip_width; + channel.common.clip_height = clip_height; + channel.common.stride = stride; + channel.common.disp_id = disp_id; + channel.common.dest_top = dest_top; + channel.common.dest_left = dest_left; + channel.common.dest_width = dest_width; + channel.common.dest_height = dest_height; + channel.common.const_color = const_color; + channel.common.use_global_alpha = use_global_alpha; + channel.common.use_local_alpha = use_local_alpha; + + if (imxdpuv1_get_planes(src_pixel_fmt) == 2) { + uv_offset = src_width * src_height; /* works for NV12 and NV16*/ + } + ret = imxdpuv1_init_channel(imxdpuv1_id, &channel); + + ret = imxdpuv1_init_channel_buffer(imxdpuv1_id, channel.common.chan, channel.common.stride, IMXDPUV1_ROTATE_NONE, + disp_addr, + uv_offset, + 0); + + ret = imxdpuv1_disp_set_chan_crop(imxdpuv1_id, + channel.common.chan, + channel.common.clip_top, + channel.common.clip_left, + channel.common.clip_width, + channel.common.clip_height, + channel.common.dest_top, + channel.common.dest_left, + channel.common.dest_width, + channel.common.dest_height); + +#ifdef DEBUG + { + imxdpuv1_chan_t eco_chan; + imxdpuv1_dump_channel(imxdpuv1_id, channel.common.chan); + eco_chan = imxdpuv1_get_eco(channel.common.chan); + if (eco_chan != 0) { + imxdpuv1_dump_channel(imxdpuv1_id, eco_chan); + } + } +#endif + return ret; +} + +/*! + * This function prints the video mode passed as a parameter + * + * @param *mode pointer to video mode struct to show + */ +void imxdpuv1_disp_dump_mode(const struct imxdpuv1_videomode *mode) +{ + IMXDPUV1_PRINT("%s():\n", __func__); + IMXDPUV1_PRINT("\thlen %4d\n", mode->hlen); + IMXDPUV1_PRINT("\thfp %4d\n", mode->hfp); + IMXDPUV1_PRINT("\thbp %4d\n", mode->hbp); + IMXDPUV1_PRINT("\thsync %4d\n", mode->hsync); + IMXDPUV1_PRINT("\tvlen %4d\n", mode->vlen); + IMXDPUV1_PRINT("\tvfp %4d\n", mode->vfp); + IMXDPUV1_PRINT("\tvbp %4d\n", mode->vbp); + IMXDPUV1_PRINT("\tvsync %4d\n", mode->vsync); + IMXDPUV1_PRINT("\tvlen1 %4d\n", mode->vlen1); + IMXDPUV1_PRINT("\tvfp1 %4d\n", mode->vfp1); + IMXDPUV1_PRINT("\tvbp1 %4d\n", mode->vbp1); + IMXDPUV1_PRINT("\tvsync1 %4d\n", mode->vsync1); + + IMXDPUV1_PRINT("\tflags 0x%08x:\n", mode->flags); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_HSYNC_POL) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_HSYNC_POL is high\n"); + else + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_HSYNC_POL is low\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_VSYNC_POL) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_VSYNC_POL is high\n"); + else + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_VSYNC_POL is low\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_DE_POL) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_DE_POL is high\n"); + else + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_DE_POL is low\n"); + + if (mode->flags & IMXDPUV1_MODE_FLAGS_INTERLACED) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_INTERLACED is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_LRSYNC) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_LRSYNC is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_SPLIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_SPLIT is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_32BIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_32BIT is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_BT656_10BIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_BT656_10BIT is set\n"); + if (mode->flags & IMXDPUV1_MODE_FLAGS_BT656_8BIT) + IMXDPUV1_PRINT("\t\tIMXDPUV1_MODE_FLAGS_BT656_8BIT is set\n"); +} + +/*! + * Returns the bytes per pixel + * + * @param pixel format + * + * @return returns number of bytes per pixel or zero + * if the format is not matched. + */ +int imxdpuv1_bytes_per_pixel(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + /* todo add NV12, and NV16 */ + case IMXDPUV1_PIX_FMT_NV12: + return 1; /* luma */ + + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + return 2; + break; + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + return 3; + break; + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_AYUV: + return 4; + break; + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + return 0; + } +} + +/*! + * Returns the number of bits per color component for the color + * component bits register + * + * @param pixel format + * + * @return Returns the number of bits per color component for + * the color component bits register. + */ +uint32_t imxdpuv1_get_colorcomponentbits(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + /* todo add NV12, NV16, YUYV, and UYVY */ + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + return + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x00); + case IMXDPUV1_PIX_FMT_NV12: + return + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x00); + + case IMXDPUV1_PIX_FMT_RGB565: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 5) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 11) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0); + + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_RGB32: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x0); + + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_AYUV: + return + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x08); + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format 0x%08x", __func__, fmt); + return 0; + } + return 0; +} + +/*! + * Returns the number of planes for the pixel format + * + * @param pixel format + * + * @return returns number of bytes per pixel or zero + * if the format is not matched. + */ +uint32_t imxdpuv1_get_planes(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_NV12: + return 2; + + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_ARGB32: + return 1; + default: + return 0; + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + } +} + +/*! + * Returns the color component bit position shifts + * + * @param pixel format + * + * @return returns the register setting for the + * colorcomponentshift register + * + */ +uint32_t imxdpuv1_get_colorcomponentshift(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + + case IMXDPUV1_PIX_FMT_NV12: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + + case IMXDPUV1_PIX_FMT_RGB565: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 5) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 6) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 5) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0); + case IMXDPUV1_PIX_FMT_YUYV: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + case IMXDPUV1_PIX_FMT_UYVY: + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + /* 0xaaRRGGBB */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x18); + case IMXDPUV1_PIX_FMT_AYUV: + /* 0xVVUUYYAA */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x18) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00); + + case IMXDPUV1_PIX_FMT_ABGR32: + /* 0xRRGGBBAA */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x18) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00); + + case IMXDPUV1_PIX_FMT_ARGB32: + /* 0xBBGGRRAA */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x18) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x00); + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + /* 0xaaBBGGRR or 0xaaUUVVYY */ + return IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x00) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x08) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x10) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x18); + default: + return 0; + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + } +} + +/*! + * Returns true is the format has local alpha + * + * @param pixel format + * + * @return Returns true is the format has local alpha + */ +uint32_t imxdpuv1_has_localalpha(uint32_t fmt) +{ + IMXDPUV1_TRACE("%s():\n", __func__); + switch (fmt) { + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_RGBA32: + return IMXDPUV1_TRUE; + default: + return IMXDPUV1_FALSE; + } +} + +/*! + * Returns the bits per pixel + * + * @param pixel format + * + * @return returns number of bits per pixel or zero + * if the format is not matched. + */ +int imxdpuv1_bits_per_pixel(uint32_t fmt) +{ + int ret = 0; + switch (fmt) { + case IMXDPUV1_PIX_FMT_NV12: + ret = 8; + break; + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_YVYU: + ret = 16; + break; + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + case IMXDPUV1_PIX_FMT_YUV444: + ret = 24; + break; + + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_AYUV: + ret = 32; + break; + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format\n", __func__); + ret = 1; + break; + } + IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret); + + return ret; +} + +/*! + * Tests for YUV + * + * @param pixel format + * + * @return returns true if the format is YUV. + */ +static bool imxdpuv1_is_yuv(uint32_t fmt) +{ + int ret = IMXDPUV1_FALSE; + switch (fmt) { + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_NV12: + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_YUV444: + ret = IMXDPUV1_TRUE; + break; + case IMXDPUV1_PIX_FMT_GENERIC_32: + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + ret = IMXDPUV1_FALSE; + break; + + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + ret = IMXDPUV1_FALSE; + break; + } + IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret); + + return ret; +} + +/*! + * Tests for RGB formats + * + * @param pixel format + * + * @return returns true if the format is any supported RGB + */ +bool imxdpuv1_is_rgb(uint32_t fmt) +{ + int ret = IMXDPUV1_FALSE; + switch (fmt) { + case IMXDPUV1_PIX_FMT_AYUV: + case IMXDPUV1_PIX_FMT_NV12: + case IMXDPUV1_PIX_FMT_NV16: + case IMXDPUV1_PIX_FMT_YUYV: + case IMXDPUV1_PIX_FMT_UYVY: + case IMXDPUV1_PIX_FMT_YUV444: + case IMXDPUV1_PIX_FMT_GENERIC_32: + ret = IMXDPUV1_FALSE; + break; + case IMXDPUV1_PIX_FMT_BGR32: + case IMXDPUV1_PIX_FMT_BGRA32: + case IMXDPUV1_PIX_FMT_RGB32: + case IMXDPUV1_PIX_FMT_RGBA32: + case IMXDPUV1_PIX_FMT_ABGR32: + case IMXDPUV1_PIX_FMT_ARGB32: + case IMXDPUV1_PIX_FMT_RGB565: + case IMXDPUV1_PIX_FMT_BGR24: + case IMXDPUV1_PIX_FMT_RGB24: + ret = IMXDPUV1_TRUE; + break; + + default: + IMXDPUV1_TRACE("%s(): unsupported pixel format", __func__); + ret = IMXDPUV1_FALSE; + break; + } + IMXDPUV1_TRACE("%s(): fmt 0x%08x, ret %d\n", __func__, fmt, ret); + + return ret; +} + +/*! + * Intializes buffers to be used for a channel + * + * @param imxdpuv1_id id of the diplay unit + * @param chan channel to use for this buffer + * @param stride total width in the buffer in pixels + * @param rot_mode rotatation mode + * @param phyaddr_0 buffer 0 address + * @param u_offset U offset + * @param v_offset V offset + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_init_channel_buffer( + int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t stride, + imxdpuv1_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, + uint32_t u_offset, + uint32_t v_offset) +{ + int ret = 0; + uint32_t b_off; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + int sub_idx = imxdpuv1_get_channel_subindex(chan); + bool enable_clip = IMXDPUV1_FALSE; + bool enable_buffer = IMXDPUV1_TRUE; + uint8_t enable_yuv = IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__OFF; + uint8_t input_select = IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__INACTIVE; + uint32_t fwidth; + uint32_t fheight; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + + b_off = id2blockoffset(get_channel_blk(chan)); + if (b_off == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0; + imxdpu->chan_data[chan_idx].u_offset = u_offset; + imxdpu->chan_data[chan_idx].v_offset = v_offset; + + /* update stride if provided */ + if (stride != 0) { + /* todo: check stride range */ + imxdpu->chan_data[chan_idx].stride = stride; + } + + /* common fetch setup */ + if (!is_store_chan(chan)) { + /* default horizontal scan + * todo: add support for vertical and warp scans + */ + if (sub_idx == 0) { + imxdpuv1_write(imxdpu, + b_off + + IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_OFFSET, + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH, + burst_param[IMXDPUV1_BURST_HORIZONTAL]. + len) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS, + burst_param[IMXDPUV1_BURST_HORIZONTAL].buffers)); + } + /* todo: Add range checking here */ + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0; + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferattributes0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_BITSPERPIXEL, + imxdpuv1_bits_per_pixel( + imxdpu->chan_data[chan_idx].src_pixel_fmt)) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_STRIDE, + imxdpu->chan_data[chan_idx].stride - 1); + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferdimension0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINECOUNT, + imxdpu->chan_data[chan_idx].src_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINEWIDTH, + imxdpu->chan_data[chan_idx].src_width - 1); + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 = + imxdpuv1_get_colorcomponentbits( + imxdpu->chan_data[chan_idx].src_pixel_fmt); + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 = + imxdpuv1_get_colorcomponentshift( + imxdpu->chan_data[chan_idx].src_pixel_fmt); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.layeroffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_XOFFSET, + imxdpu->chan_data[chan_idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYER_YOFFSET, + imxdpu->chan_data[chan_idx].dest_top); + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowoffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_XOFFSET, + imxdpu->chan_data[chan_idx].clip_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_YOFFSET, + imxdpu->chan_data[chan_idx].clip_top); + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT, + imxdpu->chan_data[chan_idx].clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH, + imxdpu->chan_data[chan_idx].clip_width - 1); + if ((imxdpu->chan_data[chan_idx].clip_height != 0) && + (imxdpu->chan_data[chan_idx].clip_width != 0)) { + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_HEIGHT, + imxdpu->chan_data[chan_idx].clip_height - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_CLIP_WIDTH, + imxdpu->chan_data[chan_idx].clip_width - 1); + + enable_clip = IMXDPUV1_ENABLE; + } else { + imxdpu->chan_data[chan_idx].fetch_layer_prop.clipwindowdimensions0 = 0; + } + + imxdpu->chan_data[chan_idx].fetch_layer_prop.constantcolor0 = + imxdpu->chan_data[chan_idx].const_color; + + if (imxdpu->chan_data[chan_idx].phyaddr_0 == 0) { + enable_buffer = IMXDPUV1_FALSE; + } + if (imxdpuv1_is_yuv(imxdpu->chan_data[chan_idx].src_pixel_fmt)) { + /* TODO: need to get correct encoding range */ + enable_yuv = IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601; + } + } + + + if (is_fetch_decode_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch decode channel\n", __func__); + if (imxdpu->chan_data[chan_idx].use_eco_fetch) { + input_select = IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COMPPACK; + if (chan == IMXDPUV1_CHAN_01) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHECO0)); + } else if (chan == IMXDPUV1_CHAN_19) { + imxdpuv1_write(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC, + IMXDPUV1_SET_FIELD( + IMXDPUV1_PIXENGCFG_SRC_SEL, + IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHECO1)); + } + imxdpuv1_init_channel_buffer(imxdpuv1_id, + imxdpuv1_get_eco(chan), + stride, + rot_mode, + phyaddr_0, + u_offset, v_offset); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 = + (0x08 << IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT); + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 = + (0x00 << IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT); + + } /* else need to handle Alpha, Warp, CLUT ... */ + + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE, + enable_yuv) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE, + imxdpu->chan_data[chan_idx].use_global_alpha) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE, + imxdpu->chan_data[chan_idx].use_local_alpha); + + /* todo: handle all cases for control register */ + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE, + IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE) | + IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK | /* needed ?*/ + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR, 1) | /*needed for clip */ + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT, input_select)); /*needed for eco */ + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT, + imxdpu->chan_data[chan_idx].dest_height - + 1 /*fheight-1 */) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH, + imxdpu->chan_data[chan_idx].dest_width - + 1 /*fwidth-1 */)); + + imxdpuv1_write_block(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET, + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + } else if (is_fetch_layer_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer channel\n", __func__); + /* here the frame is shared for all sub layers so we use + the video mode dimensions. + fetch layer sub 1 must be setup first + todo: add a check so that any sub layer can set this */ + if (is_fetch_layer_sub_chan1(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer sub channel 1\n", + __func__); + fwidth = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].hlen; + fheight = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].vlen; + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_CONTROL_OFFSET, + IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK | /* needed ?*/ + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR, 1) + ); /*needed for eco */ + + imxdpuv1_write(imxdpu, + b_off + + IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT, + /*imxdpu->chan_data[chan_idx].dest_height-1 */ + fheight - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH, + /*imxdpu->chan_data[chan_idx].dest_width-1 */ + fwidth - 1)); + } + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE, + enable_yuv) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE, + imxdpu->chan_data[chan_idx].use_global_alpha) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE, + imxdpu->chan_data[chan_idx].use_local_alpha); + + imxdpuv1_write_block(imxdpu, + b_off + + IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET + + ((IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx)), + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + } else if (is_fetch_warp_chan(chan)) { + /* here the frame is shared for all sub layers so we use + the video mode dimensions. + fetch layer sub 1 must be setup first + todo: add a check so that any sub layer can set this */ + if (is_fetch_layer_sub_chan1(chan)) { + IMXDPUV1_TRACE("%s(): fetch layer sub channel 1\n", + __func__); + fwidth = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].hlen; + fheight = + imxdpuv1_array[imxdpuv1_id]. + video_mode[imxdpuv1_array[imxdpuv1_id]. + chan_data[chan_idx].disp_id].vlen; + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_CONTROL_OFFSET, 0x700); + + imxdpuv1_write(imxdpu, + b_off + + IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEHEIGHT, + /*imxdpu->chan_data[chan_idx].dest_height-1 */ + fheight - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FRAMEWIDTH, + /*imxdpu->chan_data[chan_idx].dest_width-1 */ + fwidth - 1)); + } + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE, + enable_yuv) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE, + imxdpu->chan_data[chan_idx].use_global_alpha) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE, + imxdpu->chan_data[chan_idx].use_local_alpha); + + imxdpuv1_write_block(imxdpu, + b_off + + IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET + + (IMXDPUV1_SUBCHAN_LAYER_OFFSET * sub_idx), + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + } else if (is_fetch_eco_chan(chan)) { + IMXDPUV1_TRACE("%s(): fetch eco setup\n", __func__); + if (imxdpu->chan_data[chan_idx].src_pixel_fmt == IMXDPUV1_PIX_FMT_NV12) { + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0 + u_offset; + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferattributes0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_BITSPERPIXEL, 16) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_ATTR_STRIDE, + imxdpu->chan_data[chan_idx].stride - 1); + + /* chroma resolution*/ + imxdpu->chan_data[chan_idx].fetch_layer_prop.sourcebufferdimension0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINECOUNT, + imxdpu->chan_data[chan_idx].src_height / 2 - 1) | + IMXDPUV1_SET_FIELD(IMXDPUV1_BUFF_DIMEN_LINEWIDTH, + imxdpu->chan_data[chan_idx].src_width / 2 - 1); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentbits0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSGREEN0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSBLUE0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_BITSALPHA0, 0x0); + + imxdpu->chan_data[chan_idx].fetch_layer_prop.colorcomponentshift0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTRED0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTGREEN0, 0x0) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTBLUE0, 0x8) | + IMXDPUV1_SET_FIELD(IMXDPUV1_COLOR_SHIFTALPHA0, 0x0); + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip); + + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHECO0_FRAMERESAMPLING_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX, 0x2) | + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY, 0x2) + ); + + /* todo: handle all cases for control register */ + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHECO0_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR, 1)); + + /* luma resolution */ + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_OFFSET, + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT, + imxdpu->chan_data[chan_idx].dest_height - + 1 /*fheight-1 */) | + IMXDPUV1_SET_FIELD + (IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH, + imxdpu->chan_data[chan_idx].dest_width - + 1 /*fwidth-1 */)); + + } /* else need to handle Alpha, Warp, CLUT ... */ + + imxdpu->chan_data[chan_idx].fetch_layer_prop.layerproperty0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE, + enable_buffer) | + IMXDPUV1_SET_FIELD(IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE, + enable_clip); + + imxdpuv1_write_block(imxdpu, + b_off + IMXDPUV1_FETCHECO0_BASEADDRESS0_OFFSET, + (void *)&imxdpu->chan_data[chan_idx]. + fetch_layer_prop, + sizeof(fetch_layer_setup_t) / 4); + + imxdpuv1_disp_request_shadow_load(imxdpuv1_id, + imxdpu->chan_data[chan_idx]. + disp_id, + IMXDPUV1_SHDLD_IDX_CHAN_00 + + chan_idx); + + } else if (is_store_chan(chan)) { + imxdpu->chan_data[chan_idx].store_layer_prop.baseaddress0 = phyaddr_0; + imxdpu->chan_data[chan_idx].store_layer_prop.destbufferattributes0 = + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL, + imxdpuv1_bits_per_pixel( + imxdpu->chan_data[chan_idx].dest_pixel_fmt)) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE, + imxdpu->chan_data[chan_idx].stride-1); + imxdpu->chan_data[chan_idx].store_layer_prop.destbufferdimension0 = + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT, + imxdpu->chan_data[chan_idx].dest_height - 1) | + IMXDPUV1_SET_FIELD( + IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH, + imxdpu->chan_data[chan_idx].dest_width - 1); + imxdpu->chan_data[chan_idx].store_layer_prop.colorcomponentbits0 = + imxdpuv1_get_colorcomponentbits( + imxdpu->chan_data[chan_idx].dest_pixel_fmt); + imxdpu->chan_data[chan_idx].store_layer_prop.colorcomponentshift0 = + imxdpuv1_get_colorcomponentshift( + imxdpu->chan_data[chan_idx].dest_pixel_fmt); + imxdpu->chan_data[chan_idx].store_layer_prop.frameoffset0 = + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET, + -imxdpu->chan_data[chan_idx].dest_left) | + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET, + -imxdpu->chan_data[chan_idx].dest_top); + + + imxdpuv1_write_block(imxdpu, + b_off + IMXDPUV1_STORE9_BASEADDRESS_OFFSET, + (void *)&imxdpu->chan_data[chan_idx]. + store_layer_prop, + sizeof(store_layer_setup_t) / 4); + + if ((imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_YUYV) || + (imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_YVYU) || + (imxdpu->chan_data[chan_idx].dest_pixel_fmt == IMXDPUV1_PIX_FMT_UYVY)) { + imxdpuv1_write(imxdpu, + b_off + IMXDPUV1_STORE9_CONTROL_OFFSET, + IMXDPUV1_SET_FIELD(IMXDPUV1_STORE9_CONTROL_RASTERMODE, + IMXDPUV1_STORE9_CONTROL_RASTERMODE__YUV422)); + } + + } + + /* imxdpuv1_dump_channel(imxdpuv1_id, chan); */ + + return ret; +} + +/*! + * Intializes a channel + * + * @param imxdpuv1_id id of the diplay unit + * @param chan channel to update + * @param phyaddr_0 physical address + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int32_t imxdpuv1_update_channel_buffer( + int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + dma_addr_t phyaddr_0) +{ + int ret = 0; + uint32_t b_off; /* block offset for frame generator */ + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + + IMXDPUV1_TRACE_IRQ("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + + b_off = id2blockoffset(get_channel_blk(chan)); + if (b_off == IMXDPUV1_OFFSET_INVALID) { + return -EINVAL; + } + + if (imxdpu->chan_data[chan_idx].use_eco_fetch == IMXDPUV1_FALSE) { + imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0; + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = phyaddr_0; + } +#ifdef IMXDPUV1_VERSION_0 + if (is_store_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): store channel\n", __func__); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_STORE4_BASEADDRESS_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + + /* fixme: need to handle all pipline elements */ + imxdpuv1_write_irq(imxdpu, IMXDPUV1_PIXENGCFG_STORE4_REQUEST, 1); + + return ret; + } +#endif + if (is_fetch_decode_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch decode channel\n", __func__); + if (imxdpu->chan_data[chan_idx].use_eco_fetch) { + imxdpuv1_update_channel_buffer(imxdpuv1_id, + imxdpuv1_get_eco(chan), + phyaddr_0); + } + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_MASK); + } else if (is_fetch_layer_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch layer channel\n", __func__); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_MASK); + } else if (is_fetch_warp_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch warp channel\n", __func__); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET, + get_channel_sub(chan)); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_MASK); + } else if (is_fetch_eco_chan(chan)) { + IMXDPUV1_TRACE_IRQ("%s(): fetch eco channel\n", __func__); + + imxdpu->chan_data[chan_idx].phyaddr_0 = phyaddr_0 + imxdpu->chan_data[chan_idx].u_offset; + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0 = imxdpu->chan_data[chan_idx].phyaddr_0; + + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET, + imxdpu->chan_data[chan_idx].fetch_layer_prop.baseaddress0); + imxdpuv1_write_irq(imxdpu, + b_off + IMXDPUV1_FETCHECO0_CONTROLTRIGGER_OFFSET, + IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_MASK); + } + + return ret; +} + +/*! + * Intializes a channel + * + * @param imxdpuv1_id id of the diplay unit + * @param params pointer to channel parameters + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_init_channel(int8_t imxdpuv1_id, imxdpuv1_channel_params_t *params) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_t chan = params->common.chan; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + /* here we use the video mode for channel frame width, todo: we may need to + add a paramter for this */ + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + imxdpu->chan_data[chan_idx].chan = chan; + + memset(&imxdpu->chan_data[chan_idx].fetch_layer_prop, 0, + sizeof(fetch_layer_setup_t)); + imxdpu->chan_data[chan_idx].use_eco_fetch = IMXDPUV1_FALSE; + + if (is_fetch_decode_chan(chan)) { + IMXDPUV1_TRACE("%s(): decode channel setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_decode.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_decode.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_decode.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_decode.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_decode.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_decode.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_decode.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_decode.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_decode.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_decode.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_decode.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_decode.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_decode.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_decode.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_decode.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_decode.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_decode.disp_id; + + if (imxdpu->chan_data[chan_idx].use_video_proc == + IMXDPUV1_TRUE) { + imxdpu->chan_data[chan_idx].h_scale_factor = + params->fetch_decode.h_scale_factor; + imxdpu->chan_data[chan_idx].h_phase = + params->fetch_decode.h_phase; + imxdpu->chan_data[chan_idx].v_scale_factor = + params->fetch_decode.v_scale_factor; + imxdpu->chan_data[chan_idx].v_phase[0][0] = + params->fetch_decode.v_phase[0][0]; + imxdpu->chan_data[chan_idx].v_phase[0][1] = + params->fetch_decode.v_phase[0][1]; + imxdpu->chan_data[chan_idx].v_phase[1][0] = + params->fetch_decode.v_phase[1][0]; + imxdpu->chan_data[chan_idx].v_phase[1][1] = + params->fetch_decode.v_phase[1][1]; + } + + if (imxdpuv1_get_planes(imxdpu->chan_data[chan_idx].src_pixel_fmt) == 2) { + if (has_fetch_eco_chan(chan)) { + imxdpuv1_channel_params_t temp_params = *params; + + imxdpu->chan_data[chan_idx].use_eco_fetch = IMXDPUV1_TRUE; + temp_params.fetch_decode.chan = imxdpuv1_get_eco(params->fetch_decode.chan); + imxdpuv1_init_channel(imxdpuv1_id, &temp_params); + } else { + return -EINVAL; + } + } + } else if (is_fetch_layer_chan(chan)) { + IMXDPUV1_TRACE("%s(): layer channel setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_layer.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_layer.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_layer.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_layer.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_layer.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_layer.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_layer.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_layer.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_layer.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_layer.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_layer.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_layer.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_layer.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_layer.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_layer.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_layer.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_layer.disp_id; + + } else if (is_fetch_warp_chan(chan)) { + IMXDPUV1_TRACE("%s(): warp channel setup\n", __func__); + + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_warp.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_warp.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_warp.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_warp.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_warp.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_warp.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_warp.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_warp.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_warp.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_warp.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_warp.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_warp.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_warp.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_warp.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_warp.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_warp.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_warp.disp_id; + + } else if (is_fetch_eco_chan(chan)) { + + IMXDPUV1_TRACE("%s(): fetch eco channel setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->fetch_decode.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->fetch_decode.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->fetch_decode.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->fetch_decode.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->fetch_decode.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->fetch_decode.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->fetch_decode.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->fetch_decode.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->fetch_decode.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->fetch_decode.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->fetch_decode.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->fetch_decode.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->fetch_decode.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->fetch_decode.const_color; + imxdpu->chan_data[chan_idx].use_global_alpha = + params->fetch_decode.use_global_alpha; + imxdpu->chan_data[chan_idx].use_local_alpha = + params->fetch_decode.use_local_alpha; + imxdpu->chan_data[chan_idx].disp_id = + params->fetch_decode.disp_id; + + if (imxdpu->chan_data[chan_idx].use_video_proc == + IMXDPUV1_TRUE) { + imxdpu->chan_data[chan_idx].h_scale_factor = + params->fetch_decode.h_scale_factor; + imxdpu->chan_data[chan_idx].h_phase = + params->fetch_decode.h_phase; + imxdpu->chan_data[chan_idx].v_scale_factor = + params->fetch_decode.v_scale_factor; + imxdpu->chan_data[chan_idx].v_phase[0][0] = + params->fetch_decode.v_phase[0][0]; + imxdpu->chan_data[chan_idx].v_phase[0][1] = + params->fetch_decode.v_phase[0][1]; + imxdpu->chan_data[chan_idx].v_phase[1][0] = + params->fetch_decode.v_phase[1][0]; + imxdpu->chan_data[chan_idx].v_phase[1][1] = + params->fetch_decode.v_phase[1][1]; + } + + } else if (is_store_chan(chan)) { + IMXDPUV1_TRACE("%s(): store setup\n", __func__); + imxdpu->chan_data[chan_idx].src_pixel_fmt = + params->store.src_pixel_fmt; + imxdpu->chan_data[chan_idx].src_width = + params->store.src_width; + imxdpu->chan_data[chan_idx].src_height = + params->store.src_height; + imxdpu->chan_data[chan_idx].clip_top = + params->store.clip_top; + imxdpu->chan_data[chan_idx].clip_left = + params->store.clip_left; + imxdpu->chan_data[chan_idx].clip_width = + params->store.clip_width; + imxdpu->chan_data[chan_idx].clip_height = + params->store.clip_height; + imxdpu->chan_data[chan_idx].stride = + params->store.stride; + imxdpu->chan_data[chan_idx].dest_pixel_fmt = + params->store.dest_pixel_fmt; + imxdpu->chan_data[chan_idx].dest_top = + params->store.dest_top; + imxdpu->chan_data[chan_idx].dest_left = + params->store.dest_left; + imxdpu->chan_data[chan_idx].dest_width = + params->store.dest_width; + imxdpu->chan_data[chan_idx].dest_height = + params->store.dest_height; + imxdpu->chan_data[chan_idx].const_color = + params->store.const_color; + imxdpu->chan_data[chan_idx].source_id = + params->store.capture_id; + + if (imxdpu->chan_data[chan_idx].use_video_proc == + IMXDPUV1_TRUE) { + imxdpu->chan_data[chan_idx].h_scale_factor = + params->store.h_scale_factor; + imxdpu->chan_data[chan_idx].h_phase = + params->store.h_phase; + imxdpu->chan_data[chan_idx].v_scale_factor = + params->store.v_scale_factor; + imxdpu->chan_data[chan_idx].v_phase[0][0] = + params->store.v_phase[0][0]; + imxdpu->chan_data[chan_idx].v_phase[0][1] = + params->store.v_phase[0][1]; + imxdpu->chan_data[chan_idx].v_phase[1][0] = + params->store.v_phase[1][0]; + imxdpu->chan_data[chan_idx].v_phase[1][1] = + params->store.v_phase[1][1]; + } + + } else { + IMXDPUV1_TRACE("%s(): ERROR, invalid channel type!\n", __func__); + return -EINVAL; + } + + /* imxdpuv1_dump_channel(imxdpuv1_id, chan); */ + + return ret; +} + +/*! + * Dumps the fetch layer properties structure for a channel. + * + * @param layer id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_fetch_layer(fetch_layer_setup_t *layer) +{ + IMXDPUV1_PRINT("baseaddress 0x%08x\n" + "sourcebufferattributes 0x%08x\n" + "sourcebufferdimension h %d w %d\n" + "colorcomponentbits 0x%08x\n" + "colorcomponentshift 0x%08x\n" + "layeroffset y(top) %d x(left) %d\n" + "clipwindowoffset y(top) %d x(left) %d\n" + "clipwindowdimensions h %d w %d\n" + "constantcolor 0x%08x\n" + "layerproperty 0x%08x\n", + layer->baseaddress0, + layer->sourcebufferattributes0, + layer->sourcebufferdimension0 >> 16, + layer->sourcebufferdimension0 & 0x3fff, + layer->colorcomponentbits0, layer->colorcomponentshift0, + layer->layeroffset0 >> 16, layer->layeroffset0 & 0x3fff, + layer->clipwindowoffset0 >> 16, + layer->clipwindowoffset0 & 0x3fff, + layer->clipwindowdimensions0 >> 16, + layer->clipwindowdimensions0 & 0x3fff, + layer->constantcolor0, layer->layerproperty0); + return; +} +/*! + * Dumps the store layer properties structure for a channel. + * + * @param layer id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_store_layer(store_layer_setup_t *layer) +{ + IMXDPUV1_TRACE( + "baseaddress0 0x%08x\n" + "destbufferattributes0 0x%08x\n" + "destbufferdimension0 h %d w %d\n" + "frameoffset0 %d\n" + "colorcomponentbits0 0x%08x\n" + "colorcomponentshift0 0x%08x\n", + layer->baseaddress0, + layer->destbufferattributes0, + layer->destbufferdimension0 >> 16, layer->destbufferdimension0 & 0x3fff, + layer->frameoffset0, + layer->colorcomponentbits0, + layer->colorcomponentshift0); + return; +} + +/*! + * Dumps the pixel engine configuration status + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_layerblend(int8_t imxdpuv1_id) +{ + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS); + IMXDPUV1_TRACE("LAYERBLEND0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND0_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS); + IMXDPUV1_PRINT("LAYERBLEND1_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND1_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS); + IMXDPUV1_PRINT("LAYERBLEND2_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND2_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS); + IMXDPUV1_PRINT("LAYERBLEND3_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND3_LOCKSTATUS: 0x%08x\n", reg); +#ifdef IMXDPUV1_VERSION_0 + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_STATUS); + IMXDPUV1_PRINT("LAYERBLEND4_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND4_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND4_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_STATUS); + IMXDPUV1_PRINT("LAYERBLEND5_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND5_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND5_LOCKSTATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_STATUS); + IMXDPUV1_PRINT("LAYERBLEND6_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_LAYERBLEND6_LOCKSTATUS); + IMXDPUV1_PRINT("LAYERBLEND6_LOCKSTATUS: 0x%08x\n", reg); +#endif + return; +} + +/*! + * Dumps the pixel engine configuration status + * + * @param imxdpuv1_id id of the diplay unit + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id) +{ + uint32_t reg; + struct imxdpuv1_soc *imxdpu; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST); + IMXDPUV1_PRINT("EXTDST0_REQUEST: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST); + IMXDPUV1_PRINT("EXTDST1_REQUEST: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST); + IMXDPUV1_PRINT("EXTDST4_REQUEST: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST); + IMXDPUV1_PRINT("EXTDST5_REQUEST: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST0_STATUS); + IMXDPUV1_PRINT("EXTDST0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST1_STATUS); + IMXDPUV1_PRINT("EXTDST1_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST4_STATUS); + IMXDPUV1_PRINT("EXTDST4_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_EXTDST5_STATUS); + IMXDPUV1_PRINT("EXTDST5_STATUS: 0x%08x\n", reg); +#ifdef IMXDPUV1_VERSION_0 + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE2_STATUS); + IMXDPUV1_PRINT("FETCHDECODE2_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE3_STATUS); + IMXDPUV1_PRINT("FETCHDECODE3_STATUS: 0x%08x\n", reg); +#endif + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS); + IMXDPUV1_PRINT("FETCHWARP2_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS); + IMXDPUV1_PRINT("FETCHECO2_STATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS); + IMXDPUV1_PRINT("FETCHDECODE0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS); + IMXDPUV1_PRINT("FETCHECO0_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS); + IMXDPUV1_PRINT("FETCHDECODE1_STATUS: 0x%08x\n", reg); + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS); + IMXDPUV1_PRINT("FETCHECO1_STATUS: 0x%08x\n", reg); + + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS); + IMXDPUV1_PRINT("FETCHLAYER0_STATUS: 0x%08x\n", reg); +#ifdef IMXDPUV1_VERSION_0 + reg = imxdpuv1_read(imxdpu, IMXDPUV1_PIXENGCFG_FETCHLAYER1_STATUS); + IMXDPUV1_PRINT("FETCHLAYER1_STATUS: 0x%08x\n", reg); +#endif + return; +} + +/*! + * Dumps the channel data + * + * @param imxdpuv1_id id of the diplay unit + * @param chan channel to dump + * + * @return This function returns 0 on success or negative error code on + * fail. + */ +int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan) +{ + int ret = 0; + struct imxdpuv1_soc *imxdpu; + imxdpuv1_chan_idx_t chan_idx = get_channel_idx(chan); + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return -EINVAL; + } + + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + if (!is_chan(chan)) { + return -EINVAL; + } + if (is_store_chan(chan)) { + IMXDPUV1_PRINT("chan_id 0x%x\n" + "src_pixel_fmt 0x%08x\n" + "src_width %d\n" + "src_height %d\n" + "clip_top %d(0x%04x)\n" + "clip_left %d(0x%04x)\n" + "clip_width %d\n" + "clip_height %d\n" + "stride %d\n" + "dest_pixel_fmt 0x%08x\n" + "dest_top %d(0x%04x)\n" + "dest_left %d(0x%04x)\n" + "dest_width %d\n" + "dest_height %d\n", + (uint32_t)imxdpu->chan_data[chan_idx].chan, + imxdpu->chan_data[chan_idx].src_pixel_fmt, + imxdpu->chan_data[chan_idx].src_width, + imxdpu->chan_data[chan_idx].src_height, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_width, + imxdpu->chan_data[chan_idx].clip_height, + imxdpu->chan_data[chan_idx].stride, + imxdpu->chan_data[chan_idx].dest_pixel_fmt, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_width, + imxdpu->chan_data[chan_idx].dest_height); + + IMXDPUV1_PRINT( + "use_video_proc %d\n" + "use_eco_fetch %d\n" + "interlaced %d\n" + "phyaddr_0 0x%08x\n" + "rot_mode %d\n" + "in_use %d\n" + "use_global_alpha %d\n" + "use_local_alpha %d\n", + imxdpu->chan_data[chan_idx].use_video_proc, + imxdpu->chan_data[chan_idx].use_eco_fetch, + imxdpu->chan_data[chan_idx].interlaced, + ptr_to_uint32(imxdpu->chan_data[chan_idx].phyaddr_0), + imxdpu->chan_data[chan_idx].rot_mode, + imxdpu->chan_data[chan_idx].in_use, + imxdpu->chan_data[chan_idx].use_global_alpha, + imxdpu->chan_data[chan_idx].use_local_alpha + ); + + imxdpuv1_dump_store_layer(&imxdpu->chan_data[chan_idx].store_layer_prop); + + } else { + IMXDPUV1_PRINT("chan_id 0x%x\n" + "src_pixel_fmt 0x%08x\n" + "src_width %d\n" + "src_height %d\n" + "clip_top %d(0x%04x)\n" + "clip_left %d(0x%04x)\n" + "clip_width %d\n" + "clip_height %d\n" + "stride %d\n" + "dest_pixel_fmt 0x%08x\n" + "dest_top %d(0x%04x)\n" + "dest_left %d(0x%04x)\n" + "dest_width %d\n" + "dest_height %d\n", + (uint32_t)imxdpu->chan_data[chan_idx].chan, + imxdpu->chan_data[chan_idx].src_pixel_fmt, + imxdpu->chan_data[chan_idx].src_width, + imxdpu->chan_data[chan_idx].src_height, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_top, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_left, + imxdpu->chan_data[chan_idx].clip_width, + imxdpu->chan_data[chan_idx].clip_height, + imxdpu->chan_data[chan_idx].stride, + imxdpu->chan_data[chan_idx].dest_pixel_fmt, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_top, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_left, + imxdpu->chan_data[chan_idx].dest_width, + imxdpu->chan_data[chan_idx].dest_height); + + + IMXDPUV1_PRINT( + "use_video_proc %d\n" + "use_eco_fetch %d\n" + "interlaced %d\n" + "phyaddr_0 0x%08x\n" + "u_offset 0x%08x\n" + "v_offset 0x%08x\n" + "rot_mode %d\n" + "in_use %d\n" + "use_global_alpha %d\n" + "use_local_alpha %d\n", + imxdpu->chan_data[chan_idx].use_video_proc, + imxdpu->chan_data[chan_idx].use_eco_fetch, + imxdpu->chan_data[chan_idx].interlaced, + ptr_to_uint32(imxdpu->chan_data[chan_idx].phyaddr_0), + imxdpu->chan_data[chan_idx].u_offset, + imxdpu->chan_data[chan_idx].v_offset, + imxdpu->chan_data[chan_idx].rot_mode, + imxdpu->chan_data[chan_idx].in_use, + imxdpu->chan_data[chan_idx].use_global_alpha, + imxdpu->chan_data[chan_idx].use_local_alpha + ); + + imxdpuv1_dump_fetch_layer(&imxdpu->chan_data[chan_idx].fetch_layer_prop); + } + return ret; +} + +/*! + * Shows the interrupt status registers + * + * @param id of the diplay unit + * + */ +void imxdpuv1_dump_int_stat(int8_t imxdpuv1_id) +{ + int i; + struct imxdpuv1_soc *imxdpu; + uint32_t reg; + + IMXDPUV1_TRACE("%s()\n", __func__); + + if (!((imxdpuv1_id >= 0) && (imxdpuv1_id < IMXDPUV1_MAX_NUM))) { + return; + } + + imxdpu = &imxdpuv1_array[imxdpuv1_id]; + + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTMASK0 + + (i * 4)); + IMXDPUV1_PRINT("USERINTERRUPTMASK%d: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0 + + (i * 4)); + IMXDPUV1_PRINT("USERINTERRUPTENABLE%d: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0 + + (i * 4)); + IMXDPUV1_PRINT("USERINTERRUPTSTATUS%d: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTENABLE0 + (i * 4)); + IMXDPUV1_PRINT("INTERRUPTENABLE%i: 0x%08x\n", i, reg); + } + for (i = 0; i < 3; i++) { + reg = imxdpuv1_read_irq(imxdpu, + IMXDPUV1_COMCTRL_INTERRUPTSTATUS0 + (i * 4)); + IMXDPUV1_PRINT("INTERRUPTSTATUS%i: 0x%08x\n", i, reg); + } +} diff --git a/drivers/video/nxp/imx/imxdpuv1_be.h b/drivers/video/nxp/imx/imxdpuv1_be.h new file mode 100644 index 00000000000..a004bf82447 --- /dev/null +++ b/drivers/video/nxp/imx/imxdpuv1_be.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMXDPUV1_BE_H +#define IMXDPUV1_BE_H + +struct fetch_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t burst_buf; + uint32_t buf_address; + uint32_t buf_attributes; + uint32_t buf_dimension; + uint32_t color_bits; + uint32_t color_shift; + uint32_t layer_offset; + uint32_t clip_offset; + uint32_t clip_dimension; + uint32_t const_color; + uint32_t layer_property; + uint32_t frame_dimension; + uint32_t frame_resample; +}; + +struct store_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t burst_buf; + uint32_t buf_address; + uint32_t buf_attributes; + uint32_t buf_dimension; + uint32_t frame_offset; + uint32_t color_bits; + uint32_t color_shift; +}; +struct rop_unit { + uint32_t in_pipeline; + uint32_t control; +}; +struct matrix_unit { + uint32_t in_pipeline; + uint32_t control; +}; +struct hscaler_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t setup1; + uint32_t setup2; +}; +struct vscaler_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t setup1; + uint32_t setup2; + uint32_t setup3; + uint32_t setup4; + uint32_t setup5; +}; +struct blitblend_unit { + uint32_t in_pipeline; + uint32_t control; + uint32_t const_color; + uint32_t red_func; + uint32_t green_func; + uint32_t blue_func; + uint32_t alpha_func; + uint32_t blend_mode1; + uint32_t blend_mode2; +}; +struct engcfg_unit { + uint32_t fetchpersp9_dynamic; + uint32_t fetchdecode9_dynamic; + uint32_t rop9_dynamic; + uint32_t matrix9_dynamic; + uint32_t hscaler9_dynamic; + uint32_t vscaler9_dynamic; + uint32_t blitblend9_dynamic; + uint32_t store9_dynamic; +}; + +struct be_blit_cfg { + struct fetch_unit fetch_decode; + struct fetch_unit fetch_persp; + struct fetch_unit fetch_eco; + struct store_unit store; + struct rop_unit rop; + struct matrix_unit matrix; + struct hscaler_unit hscaler; + struct vscaler_unit vscaler; + struct blitblend_unit blitblend; + struct engcfg_unit engcfg; +}; + +/* PRIVATE DATA */ +struct imxdpuv1_info { + /*reg */ + void __iomem *base; +}; + +#define IMXDPUV1_IOC_MAGIC 'i' +#define IMXDPUV1_IOC_BLIT _IOW(IMXDPUV1_IOC_MAGIC, 1, struct be_blit_cfg) +#define IMXDPUV1_IOC_WAIT _IO(IMXDPUV1_IOC_MAGIC, 2) + +void imxdpuv1_be_irq_handler(int8_t imxdpuv1_id, int8_t irq); +int imxdpuv1_be_init(int8_t imxdpuv1_id, void __iomem *imxdpuv1_base); +int imxdpuv1_be_blit(struct imxdpuv1_info *imxdpu, struct be_blit_cfg *cfg); +int imxdpuv1_be_wait_shadow_load(struct imxdpuv1_info *imxdpu); +int imxdpuv1_be_wait_complete(struct imxdpuv1_info *imxdpu); +int imxdpuv1_be_load(struct imxdpuv1_info *imxdpu, void __user *p); +int imxdpuv1_be_wait(struct imxdpuv1_info *imxdpu); + +#endif diff --git a/drivers/video/nxp/imx/imxdpuv1_private.h b/drivers/video/nxp/imx/imxdpuv1_private.h new file mode 100644 index 00000000000..b874c38b47e --- /dev/null +++ b/drivers/video/nxp/imx/imxdpuv1_private.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Instance: imxdpuv1_private.h */ +#ifndef IMXDPUV1_PRIVATE_H +#define IMXDPUV1_PRIVATE_H + +#include +#include + +#include +#include "imxdpuv1.h" + +typedef enum { + IMXDPUV1_BURST_UNKNOWN = 0, + IMXDPUV1_BURST_LEFT_RIGHT_DOWN, + IMXDPUV1_BURST_HORIZONTAL, + IMXDPUV1_BURST_VERTICAL, + IMXDPUV1_BURST_FREE, +} imxdpuv1_burst_t; + +#define INTSTAT0_BIT(__bit__) (1U<<(__bit__)) +#define INTSTAT1_BIT(__bit__) (1U<<((__bit__)-32)) +#define INTSTAT2_BIT(__bit__) (1U<<((__bit__)-64)) + +struct imxdpuv1_irq_node { + int(*handler) (int, void *); + const char *name; + void *data; + uint32_t flags; +}; + +/* Generic definitions that are common to many registers */ +#define IMXDPUV1_COLOR_BITSALPHA0_MASK 0xFU +#define IMXDPUV1_COLOR_BITSALPHA0_SHIFT 0U +#define IMXDPUV1_COLOR_BITSBLUE0_MASK 0xF00U +#define IMXDPUV1_COLOR_BITSBLUE0_SHIFT 8U +#define IMXDPUV1_COLOR_BITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_COLOR_BITSGREEN0_SHIFT 16U +#define IMXDPUV1_COLOR_BITSRED0_MASK 0xF000000U +#define IMXDPUV1_COLOR_BITSRED0_SHIFT 24U + +#define IMXDPUV1_COLOR_SHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_COLOR_SHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_COLOR_SHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_COLOR_SHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_COLOR_SHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_COLOR_SHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_COLOR_SHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_COLOR_SHIFTRED0_SHIFT 24U + +#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU +#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U +#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U +#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U +#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U +#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U +#define IMXDPUV1_COLOR_CONSTRED_MASK 0xFF000000U +#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U + +/* these are common for fetch but not store */ +#define IMXDPUV1_BUFF_ATTR_STRIDE_MASK 0xFFFFU +#define IMXDPUV1_BUFF_ATTR_STRIDE_SHIFT 0U +#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_MASK 0x3F0000U +#define IMXDPUV1_BUFF_ATTR_BITSPERPIXEL_SHIFT 16U + +#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_SHIFT 16U +#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_BUFF_DIMEN_LINEWIDTH_SHIFT 0U +#define IMXDPUV1_BUFF_DIMEN_LINECOUNT_MASK 0x3FFF0000U + +#define IMXDPUV1_LAYER_XOFFSET_MASK 0x7FFFU +#define IMXDPUV1_LAYER_XOFFSET_SHIFT 0U +#define IMXDPUV1_LAYER_XSBIT_MASK 0x4000U +#define IMXDPUV1_LAYER_XSBIT_SHIFT 0U + +#define IMXDPUV1_LAYER_YOFFSET_MASK 0x7FFF0000U +#define IMXDPUV1_LAYER_YOFFSET_SHIFT 16U +#define IMXDPUV1_LAYER_YSBIT_MASK 0x4000U +#define IMXDPUV1_LAYER_YSBIT_SHIFT 16U + +#define IMXDPUV1_CLIP_XOFFSET_MASK 0x7FFFU +#define IMXDPUV1_CLIP_XOFFSET_SHIFT 0U +#define IMXDPUV1_CLIP_YOFFSET_MASK 0x7FFF0000U +#define IMXDPUV1_CLIP_YOFFSET_SHIFT 16U + +#define IMXDPUV1_CLIP_WIDTH_MASK 0x3FFFU +#define IMXDPUV1_CLIP_WIDTH_SHIFT 0U +#define IMXDPUV1_CLIP_HEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CLIP_HEIGHT_SHIFT 16U + +#define IMXDPUV1_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_EMPTYFRAME_SHIFT 31U + +#define IMXDPUV1_PIXENGCFG_SRC_SEL__DISABLE 0U +#define IMXDPUV1_PIXENGCFG_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_SRC_SEL_SHIFT 0U + +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_PRIM_SEL__DISABLE 0U + +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL_SHIFT 8U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND_SEC_SEL__DISABLE 0U + +#define IMXDPUV1_PIXENGCFG_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_CLKEN_SHIFT 24U +/* Field Value: _CLKEN__DISABLE, Clock for block is disabled */ +#define IMXDPUV1_PIXENGCFG_CLKEN__DISABLE 0U +/* Field Value: _CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_CLKEN__AUTOMATIC 0x1U +/* Field Value: _CLKEN__FULL, Clock for block is without gating */ +#define IMXDPUV1_PIXENGCFG_CLKEN__FULL 0x3U + + +/* Register: IMXDPUV1_LayerProperty0 Common Bits */ +#define IMXDPUV1_LAYERPROPERTY_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_LAYERPROPERTY_RESET_VALUE 0x80000100U +#define IMXDPUV1_LAYERPROPERTY_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_MASK 0x1U +#define IMXDPUV1_LAYERPROPERTY_PALETTEENABLE_SHIFT 0U +#define IMXDPUV1_LAYERPROPERTY_TILEMODE_MASK 0x30U +#define IMXDPUV1_LAYERPROPERTY_TILEMODE_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_LAYERPROPERTY_TILEMODE__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_MASK 0x100U +#define IMXDPUV1_LAYERPROPERTY_ALPHASRCENABLE_SHIFT 8U +#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_MASK 0x200U +#define IMXDPUV1_LAYERPROPERTY_ALPHACONSTENABLE_SHIFT 9U +#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_MASK 0x400U +#define IMXDPUV1_LAYERPROPERTY_ALPHAMASKENABLE_SHIFT 10U +#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_MASK 0x800U +#define IMXDPUV1_LAYERPROPERTY_ALPHATRANSENABLE_SHIFT 11U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_MASK 0x1000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHASRCENABLE_SHIFT 12U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_MASK 0x2000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHACONSTENABLE_SHIFT 13U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_MASK 0x4000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHAMASKENABLE_SHIFT 14U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_MASK 0x8000U +#define IMXDPUV1_LAYERPROPERTY_RGBALPHATRANSENABLE_SHIFT 15U +#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_MASK 0x10000U +#define IMXDPUV1_LAYERPROPERTY_PREMULCONSTRGB_SHIFT 16U +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_MASK 0x60000U +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_LAYERPROPERTY_YUVCONVERSIONMODE__ITU709 0x3U +#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_MASK 0x100000U +#define IMXDPUV1_LAYERPROPERTY_GAMMAREMOVEENABLE_SHIFT 20U +#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_MASK 0x40000000U +#define IMXDPUV1_LAYERPROPERTY_CLIPWINDOWENABLE_SHIFT 30U +#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_MASK 0x80000000U +#define IMXDPUV1_LAYERPROPERTY_SOURCEBUFFERENABLE_SHIFT 31U + +typedef struct { + /* Source buffer base address of layer 0. */ + uint32_t baseaddress0; + /* Source buffer attributes for layer 0. */ + uint32_t sourcebufferattributes0; + /* Source buffer dimension of layer 0. */ + uint32_t sourcebufferdimension0; + /* Size of color components for RGB, YUV and index formats (layer 0). */ + uint32_t colorcomponentbits0; + /* Bit position of color components for RGB, YUV and index + formats (layer 0). */ + uint32_t colorcomponentshift0; + /* Position of layer 0 within the destination frame. */ + uint32_t layeroffset0; + /* Clip window position for layer 0. */ + uint32_t clipwindowoffset0; + /* Clip window size for layer 0. */ + uint32_t clipwindowdimensions0; + /* Constant color for layer 0. */ + uint32_t constantcolor0; + /* Common properties of layer 0. */ + uint32_t layerproperty0; +} fetch_layer_setup_t; + +typedef struct { + /* Destination buffer base address of layer 0. */ + uint32_t baseaddress0; + /* Destination buffer attributes for layer 0. */ + uint32_t destbufferattributes0; + /* Source buffer dimension of layer 0. */ + uint32_t destbufferdimension0; + /* Frame offset of layer 0. */ + uint32_t frameoffset0; + /* Size of color components for RGB, YUV and index formats (layer 0). */ + uint32_t colorcomponentbits0; + /* Bit position of color components for RGB, YUV and index + formats (layer 0). */ + uint32_t colorcomponentshift0; +} store_layer_setup_t; + +typedef enum { + IMXDPUV1_SHDLD_IDX_DISP0 = (0), + IMXDPUV1_SHDLD_IDX_DISP1 = (1), + IMXDPUV1_SHDLD_IDX_CONST0 = (2), /* IMXDPUV1_ID_CONSTFRAME0 */ + IMXDPUV1_SHDLD_IDX_CONST1 = (3), /* IMXDPUV1_ID_CONSTFRAME1 */ + IMXDPUV1_SHDLD_IDX_CHAN_00 = (4), /* IMXDPUV1_ID_FETCHDECODE2 */ + IMXDPUV1_SHDLD_IDX_CHAN_01 = (5), /* IMXDPUV1_ID_FETCHDECODE0 */ + IMXDPUV1_SHDLD_IDX_CHAN_02 = (6), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_03 = (7), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_04 = (8), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_05 = (9), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_06 = (10), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_07 = (11), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_08 = (12), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_09 = (13), /* IMXDPUV1_ID_FETCHLAYER0 */ + IMXDPUV1_SHDLD_IDX_CHAN_10 = (14), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_11 = (15), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_12 = (16), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_13 = (17), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_14 = (18), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_15 = (19), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_16 = (20), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_17 = (21), /* IMXDPUV1_ID_FETCHWARP2 */ + IMXDPUV1_SHDLD_IDX_CHAN_18 = (22), /* IMXDPUV1_ID_FETCHDECODE3 */ + IMXDPUV1_SHDLD_IDX_CHAN_19 = (23), /* IMXDPUV1_ID_FETCHDECODE1 */ + IMXDPUV1_SHDLD_IDX_CHAN_20 = (24), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_21 = (25), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_22 = (26), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_23 = (27), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_24 = (28), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_25 = (29), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_26 = (30), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_27 = (31), /* IMXDPUV1_ID_FETCHLAYER1*/ + IMXDPUV1_SHDLD_IDX_CHAN_28 = (32), /* IMXDPUV1_ID_FETCHECO0*/ + IMXDPUV1_SHDLD_IDX_CHAN_29 = (33), /* IMXDPUV1_ID_FETCHECO1*/ + IMXDPUV1_SHDLD_IDX_CHAN_30 = (34), /* IMXDPUV1_ID_FETCHECO2*/ + IMXDPUV1_SHDLD_IDX_MAX = (35), +} imxdpuv1_shadow_load_index_t; + +typedef struct { + bool prim_sync_state; + bool sec_sync_state; + uint32_t prim_sync_count; + uint32_t sec_sync_count; + uint32_t skew_error_count; + uint32_t prim_fifo_empty_count; + uint32_t sec_fifo_empty_count; + uint32_t frame_count; +} frame_gen_stats_t; + +/*! + * Definition of IMXDPU channel structure + */ +typedef struct { + int8_t disp_id; /* Iris instance id of "owner" */ + + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + int16_t src_top; + int16_t src_left; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint16_t const_color; + + uint32_t h_scale_factor; /* downscaling out/in */ + uint32_t h_phase; + uint32_t v_scale_factor; /* downscaling out/in */ + uint32_t v_phase[2][2]; + + bool use_video_proc; + bool interlaced; + bool use_eco_fetch; + bool use_global_alpha; + bool use_local_alpha; + + /* note: dma_addr_t changes for 64-bit arch */ + dma_addr_t phyaddr_0; + + uint32_t u_offset; + uint32_t v_offset; + + uint8_t blend_layer; + uint8_t destination_stream; + uint8_t source_id; + + imxdpuv1_rotate_mode_t rot_mode; + + /* todo add features sub-windows, upscaling, warping */ + fetch_layer_setup_t fetch_layer_prop; + store_layer_setup_t store_layer_prop; + + bool in_use; + + /* todo: add channel features */ +} chan_private_t; + +typedef union { + struct { + uint8_t request; + uint8_t processing; + uint8_t complete; + uint8_t trys; + } state; + uint32_t word; +} imxdpuv1_shadow_state_t; + +/* PRIVATE DATA */ +struct imxdpuv1_soc { + int8_t devtype; + int8_t online; + uint32_t enabled_int[3]; + struct imxdpuv1_irq_node irq_list[IMXDPUV1_INTERRUPT_MAX]; + + struct device *dev; + struct imxdpuv1_videomode video_mode[IMXDPUV1_NUM_DI]; + struct imxdpuv1_videomode capture_mode[IMXDPUV1_NUM_CI]; + frame_gen_stats_t fgen_stats[IMXDPUV1_NUM_DI]; + uint32_t irq_count; + + + /* + * Bypass reset to avoid display channel being + * stopped by probe since it may starts to work + * in bootloader. + */ + int8_t bypass_reset; + + /* todo: need to decide where the locking is implemented */ + + /*clk*/ + + /*irq*/ + + /*reg*/ + void __iomem *base; + + /*use count*/ + imxdpuv1_layer_t blend_layer[IMXDPUV1_LAYER_MAX]; + chan_private_t chan_data[IMXDPUV1_CHAN_IDX_MAX]; + + uint8_t shadow_load_pending[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX]; + imxdpuv1_shadow_state_t shadow_load_state[IMXDPUV1_NUM_DI][IMXDPUV1_SHDLD_IDX_MAX]; +}; + + + +/* PRIVATE FUNCTIONS */ +#ifdef ENABLE_IMXDPUV1_TRACE_REG +uint32_t _imxdpuv1_read(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line); +#define imxdpuv1_read(_inst_, _offset_) _imxdpuv1_read(_inst_, _offset_, __FILE__, __LINE__) +#else +static inline uint32_t imxdpuv1_read(struct imxdpuv1_soc *dpu, uint32_t offset) +{ + return __raw_readl(dpu->base + offset); +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_READ +uint32_t _imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, u32 offset, char *file, int line); +#define imxdpuv1_read_irq(_inst_, _offset_) _imxdpuv1_read_irq(_inst_, _offset_, __FILE__, __LINE__) +#else +static inline uint32_t imxdpuv1_read_irq(struct imxdpuv1_soc *dpu, uint32_t offset) +{ + return __raw_readl(dpu->base + offset); +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_REG +void _imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line); +#define imxdpuv1_write(_inst_, _value_, _offset_) _imxdpuv1_write(_inst_, _value_, _offset_, __FILE__, __LINE__) +#else +static inline void imxdpuv1_write(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value) +{ + __raw_writel(value, dpu->base + offset); +} +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ_WRITE +void _imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t value, uint32_t offset, char *file, int line); +#define imxdpuv1_write_irq(_inst_, _value_, _offset_) _imxdpuv1_write_irq(_inst_, _value_, _offset_, __FILE__, __LINE__) +#else +static inline void imxdpuv1_write_irq(struct imxdpuv1_soc *dpu, uint32_t offset, uint32_t value) +{ + __raw_writel(value, dpu->base + offset); +} +#endif + +void _imxdpuv1_write_block(struct imxdpuv1_soc *imxdpu, uint32_t offset, void *values, uint32_t cnt, char *file, int line); +#define imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_) _imxdpuv1_write_block(_inst_, _values_, _offset_, _cnt_, __FILE__, __LINE__) + +/* mapping of RGB, Tcon, or static values to output */ +#define IMXDPUV1_TCON_MAPBIT__RGB(_x_) ((_x_)) +#define IMXDPUV1_TCON_MAPBIT__Tsig(_x_) ((_x_) + 30) +#define IMXDPUV1_TCON_MAPBIT__HIGH 42U +#define IMXDPUV1_TCON_MAPBIT__LOW 43U + +/* these match the bit definitions for the shadlow load + request registers + */ +typedef enum { + IMXDPUV1_SHLDREQID_FETCHDECODE9 = 0, + IMXDPUV1_SHLDREQID_FETCHPERSP9, + IMXDPUV1_SHLDREQID_FETCHECO9, + IMXDPUV1_SHLDREQID_CONSTFRAME0, + IMXDPUV1_SHLDREQID_CONSTFRAME4, + IMXDPUV1_SHLDREQID_CONSTFRAME1, + IMXDPUV1_SHLDREQID_CONSTFRAME5, +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_SHLDREQID_EXTSRC4, + IMXDPUV1_SHLDREQID_EXTSRC5, + IMXDPUV1_SHLDREQID_FETCHDECODE2, + IMXDPUV1_SHLDREQID_FETCHDECODE3, +#endif + IMXDPUV1_SHLDREQID_FETCHWARP2, + IMXDPUV1_SHLDREQID_FETCHECO2, + IMXDPUV1_SHLDREQID_FETCHDECODE0, + IMXDPUV1_SHLDREQID_FETCHECO0, + IMXDPUV1_SHLDREQID_FETCHDECODE1, + IMXDPUV1_SHLDREQID_FETCHECO1, + IMXDPUV1_SHLDREQID_FETCHLAYER0, +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_SHLDREQID_FETCHLAYER1, + IMXDPUV1_SHLDREQID_EXTSRC0, + IMXDPUV1_SHLDREQID_EXTSRC1 +#endif +} imxdpuv1_shadow_load_req_t; + +#define IMXDPUV1_PIXENGCFG_DIVIDER_RESET 0x80 + +#endif /* IMXDPUV1_PRIVATE_H */ + diff --git a/drivers/video/imx/ipu.h b/drivers/video/nxp/imx/ipu.h similarity index 100% rename from drivers/video/imx/ipu.h rename to drivers/video/nxp/imx/ipu.h diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/nxp/imx/ipu_common.c similarity index 100% rename from drivers/video/imx/ipu_common.c rename to drivers/video/nxp/imx/ipu_common.c diff --git a/drivers/video/imx/ipu_disp.c b/drivers/video/nxp/imx/ipu_disp.c similarity index 99% rename from drivers/video/imx/ipu_disp.c rename to drivers/video/nxp/imx/ipu_disp.c index 45069897faf..db0e818f300 100644 --- a/drivers/video/imx/ipu_disp.c +++ b/drivers/video/nxp/imx/ipu_disp.c @@ -890,6 +890,11 @@ int32_t ipu_init_sync_panel(int disp, uint32_t pixel_clk, clk_set_parent(g_pixel_clk[disp], g_ipu_clk); } rounded_pixel_clk = clk_round_rate(g_pixel_clk[disp], pixel_clk); + if (rounded_pixel_clk == 0) { + debug("IPU_DISP: get round rate error\n"); + return -EINVAL; + } + clk_set_rate(g_pixel_clk[disp], rounded_pixel_clk); udelay(5000); /* Get integer portion of divider */ diff --git a/drivers/video/imx/ipu_regs.h b/drivers/video/nxp/imx/ipu_regs.h similarity index 100% rename from drivers/video/imx/ipu_regs.h rename to drivers/video/nxp/imx/ipu_regs.h diff --git a/drivers/video/nxp/imx/lcdifv3-regs.h b/drivers/video/nxp/imx/lcdifv3-regs.h new file mode 100644 index 00000000000..b902e03644d --- /dev/null +++ b/drivers/video/nxp/imx/lcdifv3-regs.h @@ -0,0 +1,150 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#ifndef __LCDIFV3_REGS_H +#define __LCDIFV3_REGS_H + +/* regs offset */ +#define LCDIFV3_CTRL 0x00 +#define LCDIFV3_CTRL_SET 0x04 +#define LCDIFV3_CTRL_CLR 0x08 +#define LCDIFV3_CTRL_TOG 0x0c +#define LCDIFV3_DISP_PARA 0x10 +#define LCDIFV3_DISP_SIZE 0x14 +#define LCDIFV3_HSYN_PARA 0x18 +#define LCDIFV3_VSYN_PARA 0x1c +#define LCDIFV3_VSYN_HSYN_WIDTH 0x20 +#define LCDIFV3_INT_STATUS_D0 0x24 +#define LCDIFV3_INT_ENABLE_D0 0x28 +#define LCDIFV3_INT_STATUS_D1 0x30 +#define LCDIFV3_INT_ENABLE_D1 0x34 + +#define LCDIFV3_CTRLDESCL0_1 0x200 +#define LCDIFV3_CTRLDESCL0_3 0x208 +#define LCDIFV3_CTRLDESCL_LOW0_4 0x20c +#define LCDIFV3_CTRLDESCL_HIGH0_4 0x210 +#define LCDIFV3_CTRLDESCL0_5 0x214 +#define LCDIFV3_CSC0_CTRL 0x21c +#define LCDIFV3_CSC0_COEF0 0x220 +#define LCDIFV3_CSC0_COEF1 0x224 +#define LCDIFV3_CSC0_COEF2 0x228 +#define LCDIFV3_CSC0_COEF3 0x22c +#define LCDIFV3_CSC0_COEF4 0x230 +#define LCDIFV3_CSC0_COEF5 0x234 +#define LCDIFV3_PANIC0_THRES 0x238 + +/* reg bit manipulation */ +#define REG_MASK(e, s) (((1 << ((e) - (s) + 1)) - 1) << (s)) +#define REG_PUT(x, e, s) (((x) << (s)) & REG_MASK(e, s)) +#define REG_GET(x, e, s) (((x) & REG_MASK(e, s)) >> (s)) + +/* regs bit fields */ +#define CTRL_SW_RESET BIT(31) +#define CTRL_FETCH_START_OPTION(x) REG_PUT((x), 9, 8) + #define FPV 0 + #define PWV 1 + #define BPV 2 + #define RESV 3 +#define CTRL_NEG BIT(4) +#define CTRL_INV_PXCK BIT(3) +#define CTRL_INV_DE BIT(2) +#define CTRL_INV_VS BIT(1) +#define CTRL_INV_HS BIT(0) + +#define DISP_PARA_DISP_ON BIT(31) +#define DISP_PARA_SWAP_EN BIT(30) +#define DISP_PARA_LINE_PATTERN(x) REG_PUT((x), 29, 26) + /* line pattern formats (output) */ + #define LP_RGB888_OR_YUV444 0x0 + #define LP_RBG888 0x1 + #define LP_GBR888 0x2 + #define LP_GRB888_OR_UYV444 0x3 + #define LP_BRG888 0x4 + #define LP_BGR888 0x5 + #define LP_RGB555 0x6 + #define LP_RGB565 0x7 + #define LP_YUYV_16_0 0x8 + #define LP_UYVY_16_0 0x9 + #define LP_YVYU_16_0 0xa + #define LP_VYUY_16_0 0xb + #define LP_YUYV_23_8 0xc + #define LP_UYVY_23_8 0xd + #define LP_YVYU_23_8 0xe + #define LP_VYUY_23_8 0xf + +#define DISP_PARA_DISP_MODE(x) REG_PUT((x), 25, 24) +#define DISP_PARA_BGND_R(x) REG_PUT((x), 23, 16) +#define DISP_PARA_BGND_G(x) REG_PUT((x), 15, 8) +#define DISP_PARA_BGND_B(x) REG_PUT((x), 7, 0) + +#define DISP_SIZE_DELTA_Y(x) REG_PUT((x), 31, 16) +#define DISP_SIZE_DELTA_X(x) REG_PUT((x), 15, 0) + +#define HSYN_PARA_BP_H(x) REG_PUT((x), 31, 16) +#define HSYN_PARA_FP_H(x) REG_PUT((x), 15, 0) + +#define VSYN_PARA_BP_V(x) REG_PUT((x), 31, 16) +#define VSYN_PARA_FP_V(x) REG_PUT((x), 15, 0) + +#define VSYN_HSYN_WIDTH_PW_V(x) REG_PUT((x), 31, 16) +#define VSYN_HSYN_WIDTH_PW_H(x) REG_PUT((x), 15, 0) + +#define INT_STATUS_D0_FIFO_EMPTY BIT(24) +#define INT_STATUS_D0_DMA_DONE BIT(16) +#define INT_STATUS_D0_DMA_ERR BIT(8) +#define INT_STATUS_D0_VS_BLANK BIT(2) +#define INT_STATUS_D0_UNDERRUN BIT(1) +#define INT_STATUS_D0_VSYNC BIT(0) + +#define INT_ENABLE_D0_FIFO_EMPTY_EN BIT(24) +#define INT_ENABLE_D0_DMA_DONE_EN BIT(16) +#define INT_ENABLE_D0_DMA_ERR_EN BIT(8) +#define INT_ENABLE_D0_VS_BLANK_EN BIT(2) +#define INT_ENABLE_D0_UNDERRUN_EN BIT(1) +#define INT_ENABLE_D0_VSYNC_EN BIT(0) + +#define INT_STATUS_D1_PLANE_PANIC BIT(0) +#define INT_ENABLE_D1_PLANE_PANIC_EN BIT(0) + +#define CTRLDESCL0_1_HEIGHT(x) REG_PUT((x), 31, 16) +#define CTRLDESCL0_1_WIDTH(x) REG_PUT((x), 15, 0) +#define CTRLDESCL0_3_STATE_CLEAR_VSYNC BIT(23) +#define CTRLDESCL0_3_P_SIZE(x) REG_PUT((x), 22, 20) +#define CTRLDESCL0_3_T_SIZE(x) REG_PUT((x), 17, 16) +#define CTRLDESCL0_3_PITCH(x) REG_PUT((x), 15, 0) +//#define CTRLDESCL_LOW0_4_ADDR_LOW(x) REG_PUT((x), 31, 0) +#define CTRLDESCL_HIGH0_4_ADDR_HIGH(x) REG_PUT((x), 3, 0) +#define CTRLDESCL0_5_EN BIT(31) /* enable layer for DMA */ +#define CTRLDESCL0_5_SHADOW_LOAD_EN BIT(30) +#define CTRLDESCL0_5_BPP(x) REG_PUT((x), 27, 24) + /* layer encoding formats (input) */ + #define BPP16_RGB565 0x4 + #define BPP16_ARGB1555 0x5 + #define BPP16_ARGB4444 0x6 + #define BPP16_YCbCr422 0x7 + #define BPP24_RGB888 0x8 + #define BPP32_ARGB8888 0x9 + #define BPP32_ABGR8888 0xa +#define CTRLDESCL0_5_YUV_FORMAT(x) REG_PUT((x), 15, 14) + +#define CSC0_CTRL_CSC_MODE(x) REG_PUT((x), 2, 1) +#define CSC0_CTRL_BYPASS BIT(0) +#define CSC0_COEF0_A2(x) REG_PUT((x), 26, 16) +#define CSC0_COEF0_A1(x) REG_PUT((x), 10, 0) +#define CSC0_COEF1_B1(x) REG_PUT((x), 26, 16) +#define CSC0_COEF1_A3(x) REG_PUT((x), 10, 0) +#define CSC0_COEF2_B3(x) REG_PUT((x), 26, 16) +#define CSC0_COEF2_B2(x) REG_PUT((x), 10, 0) +#define CSC0_COEF3_C2(x) REG_PUT((x), 26, 16) +#define CSC0_COEF3_C1(x) REG_PUT((x), 10, 0) +#define CSC0_COEF4_D1(x) REG_PUT((x), 24, 16) +#define CSC0_COEF4_C3(x) REG_PUT((x), 10, 0) +#define CSC0_COEF5_D3(x) REG_PUT((x), 24, 16) +#define CSC0_COEF5_D2(x) REG_PUT((x), 8, 0) + +#define PANIC0_THRES_PANIC_THRES_LOW(x) REG_PUT((x), 24, 16) +#define PANIC0_THRES_PANIC_THRES_HIGH(x) REG_PUT((x), 8, 0) + +#endif /* __LCDIFV3_REGS_H */ diff --git a/drivers/video/nxp/imx/mipi_dsi_northwest.c b/drivers/video/nxp/imx/mipi_dsi_northwest.c new file mode 100644 index 00000000000..399fd8f9c89 --- /dev/null +++ b/drivers/video/nxp/imx/mipi_dsi_northwest.c @@ -0,0 +1,896 @@ +/* + * Copyright 2016-2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "mipi_dsi_northwest_regs.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MIPI_LCD_SLEEP_MODE_DELAY (120) +#define MIPI_FIFO_TIMEOUT 250000 /* 250ms */ +#define PS2KHZ(ps) (1000000000UL / (ps)) + +#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \ +{ \ + typeof(divisor) __d = divisor; \ + unsigned long long _tmp = (x) + (__d) / 2; \ + do_div(_tmp, __d); \ + _tmp; \ +} \ +) + +enum mipi_dsi_mode { + DSI_COMMAND_MODE, + DSI_VIDEO_MODE +}; + +#define DSI_LP_MODE 0 +#define DSI_HS_MODE 1 + +enum mipi_dsi_payload { + DSI_PAYLOAD_CMD, + DSI_PAYLOAD_VIDEO, +}; + +/* + * mipi-dsi northwest driver information structure, holds useful data for the driver. + */ +struct mipi_dsi_northwest_info { + void __iomem *mmio_base; + struct mipi_dsi_device *device; + struct mipi_dsi_host dsi_host; + struct display_timing timings; + struct regmap *sim; + + uint32_t max_data_lanes; + uint32_t max_data_rate; + uint32_t pll_ref; +}; + +struct pll_divider { + unsigned int cm; /* multiplier */ + unsigned int cn; /* predivider */ + unsigned int co; /* outdivider */ +}; + +/** + * 'CM' value to 'CM' reigister config value map + * 'CM' = [16, 255]; + */ +static unsigned int cm_map_table[240] = { + 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, /* 16 ~ 23 */ + 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff, /* 24 ~ 31 */ + + 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, /* 32 ~ 39 */ + 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, /* 40 ~ 47 */ + + 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, /* 48 ~ 55 */ + 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, /* 56 ~ 63 */ + + 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, /* 64 ~ 71 */ + 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, /* 72 ~ 79 */ + + 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, /* 80 ~ 87 */ + 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, /* 88 ~ 95 */ + + 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, /* 96 ~ 103 */ + 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, /* 104 ~ 111 */ + + 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, /* 112 ~ 119 */ + 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, /* 120 ~ 127 */ + + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* 128 ~ 135 */ + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, /* 136 ~ 143 */ + + 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* 144 ~ 151 */ + 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, /* 152 ~ 159 */ + + 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, /* 160 ~ 167 */ + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, /* 168 ~ 175 */ + + 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, /* 176 ~ 183 */ + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, /* 184 ~ 191 */ + + 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, /* 192 ~ 199 */ + 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, /* 200 ~ 207 */ + + 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, /* 208 ~ 215 */ + 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, /* 216 ~ 223 */ + + 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, /* 224 ~ 231 */ + 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, /* 232 ~ 239 */ + + 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, /* 240 ~ 247 */ + 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f /* 248 ~ 255 */ +}; + +/** + * map 'CN' value to 'CN' reigister config value + * 'CN' = [1, 32]; + */ +static unsigned int cn_map_table[32] = { + 0x1f, 0x00, 0x10, 0x18, 0x1c, 0x0e, 0x07, 0x13, /* 1 ~ 8 */ + 0x09, 0x04, 0x02, 0x11, 0x08, 0x14, 0x0a, 0x15, /* 9 ~ 16 */ + 0x1a, 0x1d, 0x1e, 0x0f, 0x17, 0x1b, 0x0d, 0x16, /* 17 ~ 24 */ + 0x0b, 0x05, 0x12, 0x19, 0x0c, 0x06, 0x03, 0x01 /* 25 ~ 32 */ +}; + +/** + * map 'CO' value to 'CO' reigister config value + * 'CO' = { 1, 2, 4, 8 }; + */ +static unsigned int co_map_table[4] = { + 0x0, 0x1, 0x2, 0x3 +}; + +unsigned long gcd(unsigned long a, unsigned long b) +{ + unsigned long r = a | b; + + if (!a || !b) + return r; + + /* Isolate lsbit of r */ + r &= -r; + + while (!(b & r)) + b >>= 1; + if (b == r) + return r; + + for (;;) { + while (!(a & r)) + a >>= 1; + if (a == r) + return r; + if (a == b) + return a; + + if (a < b) + swap(a, b); + a -= b; + a >>= 1; + if (a & r) + a += b; + a >>= 1; + } +} + +static void mipi_dsi_set_mode(struct mipi_dsi_northwest_info *mipi_dsi, + uint8_t mode); +static int mipi_dsi_dcs_cmd(struct mipi_dsi_northwest_info *mipi_dsi, + u8 cmd, const u32 *param, int num); + +static void mipi_dsi_set_mode(struct mipi_dsi_northwest_info *mipi_dsi, + uint8_t mode) +{ + switch (mode) { + case DSI_LP_MODE: + writel(0x1, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK); + break; + case DSI_HS_MODE: + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK); + break; + default: + printf("invalid dsi mode\n"); + return; + } + + mdelay(1); +} + +static int mipi_dsi_dphy_init(struct mipi_dsi_northwest_info *mipi_dsi) +{ + uint32_t time_out = 100; + uint32_t lock; + uint32_t req_bit_clk; + uint32_t bpp; + + int i, best_div = -1; + int64_t delta; + uint64_t least_delta = ~0U; + uint64_t limit, div_result; + uint64_t denominator, numerator, divisor; + uint64_t norm_denom, norm_num, split_denom; + struct pll_divider div = { 0 }; + + regmap_update_bits(mipi_dsi->sim, SIM_SOPT1, MIPI_ISO_DISABLE, MIPI_ISO_DISABLE); + + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->device->format); + + /* req_bit_clk is PLL out, clk_byte is 1/8th of the req_bit_clk + * We need meet clk_byte_freq >= dpi_pclk_freq * DPI_pixel_size / ( 8 * (cfg_num_lanes + 1)) + */ + + req_bit_clk = mipi_dsi->timings.pixelclock.typ; + req_bit_clk = req_bit_clk * bpp; + + switch (mipi_dsi->device->lanes) { + case 1: + break; + case 2: + req_bit_clk = req_bit_clk >> 1; + break; + case 4: + req_bit_clk = req_bit_clk >> 2; + break; + default: + printf("requested data lane num is invalid\n"); + return -EINVAL; + } + + debug("req_bit_clk %u\n", req_bit_clk); + + /* The max rate for PLL out is 800Mhz */ + if (req_bit_clk > mipi_dsi->max_data_rate) + return -EINVAL; + + /* calc CM, CN and CO according to PHY PLL formula: + * + * 'PLL out bitclk = refclk * CM / (CN * CO);' + * + * Let: + * 'numerator = bitclk / divisor'; + * 'denominator = refclk / divisor'; + * Then: + * 'numerator / denominator = CM / (CN * CO)'; + * + * CM is in [16, 255] + * CN is in [1, 32] + * CO is in { 1, 2, 4, 8 }; + */ + divisor = gcd(mipi_dsi->pll_ref, req_bit_clk); + WARN_ON(divisor == 1); + + div_result = req_bit_clk; + do_div(div_result, divisor); + numerator = div_result; + + div_result = mipi_dsi->pll_ref; + do_div(div_result, divisor); + denominator = div_result; + + /* denominator & numerator out of range check */ + if (DIV_ROUND_CLOSEST_ULL(numerator, denominator) > 255 || + DIV_ROUND_CLOSEST_ULL(denominator, numerator) > 32 * 8) + return -EINVAL; + + /* Normalization: reduce or increase + * numerator to [16, 255] + * denominator to [1, 32 * 8] + * Reduce normalization result is 'approximiate' + * Increase nomralization result is 'precise' + */ + if (numerator > 255 || denominator > 32 * 8) { + /* approximate */ + if (likely(numerator > denominator)) { + /* 'numerator > 255'; + * 'limit' should meet below conditions: + * a. '(numerator / limit) >= 16' + * b. '(denominator / limit) >= 1' + */ + limit = min(denominator, + DIV_ROUND_CLOSEST_ULL(numerator, 16)); + + /* Let: + * norm_num = numerator / i; + * norm_denom = denominator / i; + * + * So: + * delta = numerator * norm_denom - + * denominator * norm_num + */ + for (i = 2; i <= limit; i++) { + norm_num = DIV_ROUND_CLOSEST_ULL(numerator, i); + if (norm_num > 255) + continue; + + norm_denom = DIV_ROUND_CLOSEST_ULL(denominator, i); + + /* 'norm_num <= 255' && 'norm_num > norm_denom' + * so, 'norm_denom < 256' + */ + delta = numerator * norm_denom - + denominator * norm_num; + delta = abs(delta); + if (delta < least_delta) { + least_delta = delta; + best_div = i; + } else if (delta == least_delta) { + /* choose better one IF: + * 'norm_denom' derived from last 'best_div' + * needs later split, i.e, 'norm_denom > 32'. + */ + if (DIV_ROUND_CLOSEST_ULL(denominator, best_div) > 32) { + least_delta = delta; + best_div = i; + } + } + } + } else { + /* 'denominator > 32 * 8'; + * 'limit' should meet below conditions: + * a. '(numerator / limit >= 16' + * b. '(denominator / limit >= 1': obviously. + */ + limit = DIV_ROUND_CLOSEST_ULL(numerator, 16); + if (!limit || + DIV_ROUND_CLOSEST_ULL(denominator, limit) > 32 * 8) + return -EINVAL; + + for (i = 2; i <= limit; i++) { + norm_denom = DIV_ROUND_CLOSEST_ULL(denominator, i); + if (norm_denom > 32 * 8) + continue; + + norm_num = DIV_ROUND_CLOSEST_ULL(numerator, i); + + /* 'norm_denom <= 256' && 'norm_num < norm_denom' + * so, 'norm_num <= 255' + */ + delta = numerator * norm_denom - + denominator * norm_num; + delta = abs(delta); + if (delta < least_delta) { + least_delta = delta; + best_div = i; + } else if (delta == least_delta) { + if (DIV_ROUND_CLOSEST_ULL(denominator, best_div) > 32) { + least_delta = delta; + best_div = i; + } + } + } + } + + numerator = DIV_ROUND_CLOSEST_ULL(numerator, best_div); + denominator = DIV_ROUND_CLOSEST_ULL(denominator, best_div); + } else if (numerator < 16) { + /* precise */ + + /* 'limit' should meet below conditions: + * a. 'denominator * limit <= 32 * 8' + * b. '16 <= numerator * limit <= 255' + * Choose 'limit' to be the least value + * which makes 'numerator * limit' to be + * in [16, 255]. + */ + limit = min(256 / (uint32_t)denominator, + 255 / (uint32_t)numerator); + if (limit == 1 || limit < DIV_ROUND_UP_ULL(16, numerator)) + return -EINVAL; + + /* choose the least available value for 'limit' */ + limit = DIV_ROUND_UP_ULL(16, numerator); + numerator = numerator * limit; + denominator = denominator * limit; + + WARN_ON(numerator < 16 || denominator > 32 * 8); + } + + div.cm = cm_map_table[numerator - 16]; + + /* split 'denominator' to 'CN' and 'CO' */ + if (denominator > 32) { + /* traverse four possible values of 'CO' + * there must be some value of 'CO' can be used + */ + least_delta = ~0U; + for (i = 0; i < 4; i++) { + split_denom = DIV_ROUND_CLOSEST_ULL(denominator, 1 << i); + if (split_denom > 32) + continue; + + /* calc deviation to choose the best one */ + delta = denominator - split_denom * (1 << i); + delta = abs(delta); + if (delta < least_delta) { + least_delta = delta; + div.co = co_map_table[i]; + div.cn = cn_map_table[split_denom - 1]; + } + } + } else { + div.co = co_map_table[1 >> 1]; + div.cn = cn_map_table[denominator - 1]; + } + + debug("cn 0x%x, cm 0x%x, co 0x%x\n", div.cn, div.cm, div.co); + + writel(div.cn, mipi_dsi->mmio_base + DPHY_CN); + writel(div.cm, mipi_dsi->mmio_base + DPHY_CM); + writel(div.co, mipi_dsi->mmio_base + DPHY_CO); + + writel(0x25, mipi_dsi->mmio_base + DPHY_TST); + writel(0x0, mipi_dsi->mmio_base + DPHY_PD_PLL); + + while (!(lock = readl(mipi_dsi->mmio_base + DPHY_LOCK))) { + udelay(10); + time_out--; + if (time_out == 0) { + printf("cannot get the dphy lock = 0x%x\n", lock); + return -EINVAL; + } + } + debug("%s: dphy lock = 0x%x\n", __func__, lock); + + writel(0x0, mipi_dsi->mmio_base + DPHY_LOCK_BYP); + writel(0x1, mipi_dsi->mmio_base + DPHY_RTERM_SEL); + writel(0x0, mipi_dsi->mmio_base + DPHY_AUTO_PD_EN); + writel(0x1, mipi_dsi->mmio_base + DPHY_RXLPRP); + writel(0x1, mipi_dsi->mmio_base + DPHY_RXCDRP); + writel(0x0, mipi_dsi->mmio_base + DPHY_M_PRG_HS_PREPARE); + writel(0x0, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_PREPARE); + writel(0x9, mipi_dsi->mmio_base + DPHY_M_PRG_HS_ZERO); + writel(0x20, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_ZERO); + writel(0x5, mipi_dsi->mmio_base + DPHY_M_PRG_HS_TRAIL); + writel(0x5, mipi_dsi->mmio_base + DPHY_MC_PRG_HS_TRAIL); + writel(0x0, mipi_dsi->mmio_base + DPHY_PD_DPHY); + + regmap_update_bits(mipi_dsi->sim, SIM_SOPT1CFG, DSI_PLL_EN, DSI_PLL_EN); + return 0; +} + +static int mipi_dsi_host_init(struct mipi_dsi_northwest_info *mipi_dsi) +{ + uint32_t lane_num; + + switch (mipi_dsi->device->lanes) { + case 1: + lane_num = 0x0; + break; + case 2: + lane_num = 0x1; + break; + default: + /* Invalid lane num */ + return -EINVAL; + } + + writel(lane_num, mipi_dsi->mmio_base + HOST_CFG_NUM_LANES); + writel(0x1, mipi_dsi->mmio_base + HOST_CFG_NONCONTINUOUS_CLK); + writel(0x1, mipi_dsi->mmio_base + HOST_CFG_T_PRE); + writel(52, mipi_dsi->mmio_base + HOST_CFG_T_POST); + writel(13, mipi_dsi->mmio_base + HOST_CFG_TX_GAP); + writel(0x1, mipi_dsi->mmio_base + HOST_CFG_AUTOINSERT_EOTP); + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_EXTRA_CMDS_AFTER_EOTP); + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_HTX_TO_COUNT); + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_LRX_H_TO_COUNT); + writel(0x0, mipi_dsi->mmio_base + HOST_CFG_BTA_H_TO_COUNT); + writel(0x3A98, mipi_dsi->mmio_base + HOST_CFG_TWAKEUP); + + return 0; +} + +static int mipi_dsi_dpi_init(struct mipi_dsi_northwest_info *mipi_dsi) +{ + uint32_t color_coding, pixel_fmt; + int bpp; + struct display_timing *timings = &(mipi_dsi->timings); + + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->device->format); + if (bpp < 0) + return -EINVAL; + + writel(timings->hactive.typ, mipi_dsi->mmio_base + DPI_PIXEL_PAYLOAD_SIZE); + writel(timings->hactive.typ, mipi_dsi->mmio_base + DPI_PIXEL_FIFO_SEND_LEVEL); + + switch (bpp) { + case 24: + color_coding = 5; + pixel_fmt = 3; + break; + case 16: + case 18: + default: + /* Not supported */ + return -EINVAL; + } + writel(color_coding, mipi_dsi->mmio_base + DPI_INTERFACE_COLOR_CODING); + writel(pixel_fmt, mipi_dsi->mmio_base + DPI_PIXEL_FORMAT); + writel(0x0, mipi_dsi->mmio_base + DPI_VSYNC_POLARITY); + writel(0x0, mipi_dsi->mmio_base + DPI_HSYNC_POLARITY); + writel(0x2, mipi_dsi->mmio_base + DPI_VIDEO_MODE); + + writel(timings->hfront_porch.typ * (bpp >> 3), mipi_dsi->mmio_base + DPI_HFP); + writel(timings->hback_porch.typ * (bpp >> 3), mipi_dsi->mmio_base + DPI_HBP); + writel(timings->hsync_len.typ * (bpp >> 3), mipi_dsi->mmio_base + DPI_HSA); + writel(0x0, mipi_dsi->mmio_base + DPI_ENABLE_MULT_PKTS); + + writel(timings->vback_porch.typ, mipi_dsi->mmio_base + DPI_VBP); + writel(timings->vfront_porch.typ, mipi_dsi->mmio_base + DPI_VFP); + writel(0x1, mipi_dsi->mmio_base + DPI_BLLP_MODE); + writel(0x0, mipi_dsi->mmio_base + DPI_USE_NULL_PKT_BLLP); + + writel(timings->vactive.typ - 1, mipi_dsi->mmio_base + DPI_VACTIVE); + + writel(0x0, mipi_dsi->mmio_base + DPI_VC); + + return 0; +} + +static void mipi_dsi_init_interrupt(struct mipi_dsi_northwest_info *mipi_dsi) +{ + /* disable all the irqs */ + writel(0xffffffff, mipi_dsi->mmio_base + HOST_IRQ_MASK); + writel(0x7, mipi_dsi->mmio_base + HOST_IRQ_MASK2); +} + +static int mipi_display_enter_sleep(struct mipi_dsi_northwest_info *mipi_dsi) +{ + int err; + + err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_SET_DISPLAY_OFF, + NULL, 0); + if (err) + return -EINVAL; + mdelay(50); + + err = mipi_dsi_dcs_cmd(mipi_dsi, MIPI_DCS_ENTER_SLEEP_MODE, + NULL, 0); + if (err) + printf("MIPI DSI DCS Command sleep in error!\n"); + + mdelay(MIPI_LCD_SLEEP_MODE_DELAY); + + return err; +} + +static void mipi_dsi_wr_tx_header(struct mipi_dsi_northwest_info *mipi_dsi, + u8 di, u8 data0, u8 data1, u8 mode, u8 need_bta) +{ + uint32_t pkt_control = 0; + uint16_t word_count = 0; + + word_count = data0 | (data1 << 8); + pkt_control = HOST_PKT_CONTROL_WC(word_count) | + HOST_PKT_CONTROL_VC(0) | + HOST_PKT_CONTROL_DT(di) | + HOST_PKT_CONTROL_HS_SEL(mode) | + HOST_PKT_CONTROL_BTA_TX(need_bta); + + debug("pkt_control = %x\n", pkt_control); + writel(pkt_control, mipi_dsi->mmio_base + HOST_PKT_CONTROL); +} + +static void mipi_dsi_wr_tx_data(struct mipi_dsi_northwest_info *mipi_dsi, + uint32_t tx_data) +{ + writel(tx_data, mipi_dsi->mmio_base + HOST_TX_PAYLOAD); +} + +static void mipi_dsi_long_data_wr(struct mipi_dsi_northwest_info *mipi_dsi, + const uint8_t *data0, uint32_t data_size) +{ + uint32_t data_cnt = 0, payload = 0; + + /* in case that data count is more than 4 */ + for (data_cnt = 0; data_cnt < data_size; data_cnt += 4) { + /* + * after sending 4bytes per one time, + * send remainder data less then 4. + */ + if ((data_size - data_cnt) < 4) { + if ((data_size - data_cnt) == 3) { + payload = data0[data_cnt] | + (data0[data_cnt + 1] << 8) | + (data0[data_cnt + 2] << 16); + debug("count = 3 payload = %x, %x %x %x\n", + payload, data0[data_cnt], data0[data_cnt + 1], data0[data_cnt + 2]); + } else if ((data_size - data_cnt) == 2) { + payload = data0[data_cnt] | + (data0[data_cnt + 1] << 8); + debug("count = 2 payload = %x, %x %x\n", + payload, data0[data_cnt], data0[data_cnt + 1]); + } else if ((data_size - data_cnt) == 1) { + payload = data0[data_cnt]; + debug("count = 1 payload = %x, %x\n", + payload, data0[data_cnt]); + } + + mipi_dsi_wr_tx_data(mipi_dsi, payload); + } else { + payload = data0[data_cnt] | + (data0[data_cnt + 1] << 8) | + (data0[data_cnt + 2] << 16) | + (data0[data_cnt + 3] << 24); + + debug("count = 4 payload = %x, %x %x %x %x\n", + payload, *(u8 *)(data0 + data_cnt), + data0[data_cnt + 1], + data0[data_cnt + 2], + data0[data_cnt + 3]); + + mipi_dsi_wr_tx_data(mipi_dsi, payload); + } + } +} + +static int wait_for_pkt_done(struct mipi_dsi_northwest_info *mipi_dsi, unsigned long timeout) +{ + uint32_t irq_status; + + do { + irq_status = readl(mipi_dsi->mmio_base + HOST_IRQ_STATUS); + if (irq_status & HOST_IRQ_STATUS_TX_PKT_DONE) + return timeout; + + udelay(1); + } while (--timeout); + + return 0; +} + +static int mipi_dsi_pkt_write(struct mipi_dsi_northwest_info *mipi_dsi, + u8 data_type, const u8 *buf, int len) +{ + int ret = 0; + const uint8_t *data = (const uint8_t *)buf; + + debug("mipi_dsi_pkt_write data_type 0x%x, buf 0x%x, len %u\n", data_type, (u32)buf, len); + + if (len == 0) + /* handle generic long write command */ + mipi_dsi_wr_tx_header(mipi_dsi, data_type, data[0], data[1], DSI_LP_MODE, 0); + else { + /* handle generic long write command */ + mipi_dsi_long_data_wr(mipi_dsi, data, len); + mipi_dsi_wr_tx_header(mipi_dsi, data_type, len & 0xff, + (len & 0xff00) >> 8, DSI_LP_MODE, 0); + } + + /* send packet */ + writel(0x1, mipi_dsi->mmio_base + HOST_SEND_PACKET); + ret = wait_for_pkt_done(mipi_dsi, MIPI_FIFO_TIMEOUT); + + if (!ret) { + printf("wait tx done timeout!\n"); + return -ETIMEDOUT; + } + + return 0; +} + +#define DSI_CMD_BUF_MAXSIZE (128) + +static int mipi_dsi_dcs_cmd(struct mipi_dsi_northwest_info *mipi_dsi, + u8 cmd, const u32 *param, int num) +{ + int err = 0; + u32 buf[DSI_CMD_BUF_MAXSIZE]; + + switch (cmd) { + case MIPI_DCS_EXIT_SLEEP_MODE: + case MIPI_DCS_ENTER_SLEEP_MODE: + case MIPI_DCS_SET_DISPLAY_ON: + case MIPI_DCS_SET_DISPLAY_OFF: + buf[0] = cmd; + buf[1] = 0x0; + err = mipi_dsi_pkt_write(mipi_dsi, + MIPI_DSI_DCS_SHORT_WRITE, (u8 *)buf, 0); + break; + + default: + printf("MIPI DSI DCS Command:0x%x Not supported!\n", cmd); + break; + } + + return err; +} + +static void reset_dsi_domains(struct mipi_dsi_northwest_info *mipi_dsi, bool reset) +{ + /* escape domain */ + regmap_update_bits(mipi_dsi->sim, SIM_SOPT1CFG, + DSI_RST_ESC_N, (reset ? 0 : DSI_RST_ESC_N)); + /* byte domain */ + regmap_update_bits(mipi_dsi->sim, SIM_SOPT1CFG, + DSI_RST_BYTE_N, (reset ? 0 : DSI_RST_BYTE_N)); + + /* dpi domain */ + regmap_update_bits(mipi_dsi->sim, SIM_SOPT1CFG, + DSI_RST_DPI_N, (reset ? 0 : DSI_RST_DPI_N)); +} + +static void mipi_dsi_shutdown(struct mipi_dsi_northwest_info *mipi_dsi) +{ + mipi_display_enter_sleep(mipi_dsi); + + writel(0x1, mipi_dsi->mmio_base + DPHY_PD_PLL); + writel(0x1, mipi_dsi->mmio_base + DPHY_PD_DPHY); + + enable_mipi_dsi_clk(false); + + reset_dsi_domains(mipi_dsi, true); +} + +static inline struct mipi_dsi_northwest_info *host_to_dsi(struct mipi_dsi_host *host) +{ + return container_of(host, struct mipi_dsi_northwest_info, dsi_host); +} + +static int mipi_dsi_northwest_host_attach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct mipi_dsi_northwest_info *mipi_dsi = host_to_dsi(host); + int ret; + + /* Assert resets */ + reset_dsi_domains(mipi_dsi, true); + + /* Enable mipi relevant clocks */ + enable_mipi_dsi_clk(true); + + ret = mipi_dsi_dphy_init(mipi_dsi); + if (ret < 0) + return ret; + + ret = mipi_dsi_host_init(mipi_dsi); + if (ret < 0) + return ret; + + ret = mipi_dsi_dpi_init(mipi_dsi); + if (ret < 0) + return ret; + + /* Deassert resets */ + reset_dsi_domains(mipi_dsi, false); + + /* display_en */ + regmap_update_bits(mipi_dsi->sim, SIM_SOPT1CFG, DSI_SD, 0); + + /* normal cm */ + regmap_update_bits(mipi_dsi->sim, SIM_SOPT1CFG, DSI_CM, 0); + mdelay(20); + + /* Disable all interrupts, since we use polling */ + mipi_dsi_init_interrupt(mipi_dsi); + + return 0; +} + +static ssize_t mipi_dsi_northwest_host_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + struct mipi_dsi_northwest_info *dsi = host_to_dsi(host); + + if (!msg) + return -EINVAL; + + /* do some minimum sanity checking */ + if (!mipi_dsi_packet_format_is_short(msg->type) && + !mipi_dsi_packet_format_is_long(msg->type)) + return -EINVAL; + +#ifdef DEBUG + int i = 0; + u8 *p = msg->tx_buf; + + printf("sec_mipi_dsi_host_transfer\n"); + for (i; i < msg->tx_len; i++) { + printf("0x%.2x ", *(u8 *)p); + p++; + } + printf("\n"); +#endif + + if (mipi_dsi_packet_format_is_long(msg->type)) { + return mipi_dsi_pkt_write(dsi, msg->type, msg->tx_buf, msg->tx_len); + } else { + return mipi_dsi_pkt_write(dsi, msg->type, msg->tx_buf, 0); + } +} + + +static const struct mipi_dsi_host_ops mipi_dsi_northwest_host_ops = { + .attach = mipi_dsi_northwest_host_attach, + .transfer = mipi_dsi_northwest_host_transfer, +}; + +static int mipi_dsi_northwest_init(struct udevice *dev, + struct mipi_dsi_device *device, + struct display_timing *timings, + unsigned int max_data_lanes, + const struct mipi_dsi_phy_ops *phy_ops) +{ + struct mipi_dsi_northwest_info *dsi = dev_get_priv(dev); + int ret; + + dsi->max_data_lanes = max_data_lanes; + dsi->device = device; + dsi->dsi_host.ops = &mipi_dsi_northwest_host_ops; + device->host = &dsi->dsi_host; + + dsi->timings = *timings; + dsi->mmio_base = (void *)dev_read_addr(device->dev); + if ((fdt_addr_t)dsi->mmio_base == FDT_ADDR_T_NONE) { + dev_err(device->dev, "dsi dt register address error\n"); + return -EINVAL; + } + + ret = dev_read_u32(device->dev, "max-data-rate", &dsi->max_data_rate); + if (ret) { + dev_err(device->dev, "fail to get max-data-rate\n"); + return -EINVAL; + } + + ret = dev_read_u32(device->dev, "phy-ref-clkfreq", &dsi->pll_ref); + if (ret) { + dev_err(device->dev, "fail to get phy-ref-clkfreq\n"); + return -EINVAL; + } + + dsi->sim = syscon_regmap_lookup_by_phandle(device->dev, "sim"); + if (IS_ERR(dsi->sim)) { + dev_err(device->dev, "fail to get sim regmap\n"); + return PTR_ERR(dsi->sim); + } + + return 0; +} + +static int mipi_dsi_northwest_enable(struct udevice *dev) +{ + struct mipi_dsi_northwest_info *mipi_dsi = dev_get_priv(dev); + + /* Enter the HS mode for video stream */ + mipi_dsi_set_mode(mipi_dsi, DSI_HS_MODE); + + return 0; +} + +static int mipi_dsi_northwest_disable(struct udevice *dev) +{ + struct mipi_dsi_northwest_info *mipi_dsi = dev_get_priv(dev); + + mipi_dsi_shutdown(mipi_dsi); + return 0; +} + +struct dsi_host_ops mipi_dsi_northwest_ops = { + .init = mipi_dsi_northwest_init, + .enable = mipi_dsi_northwest_enable, + .disable = mipi_dsi_northwest_disable, +}; + +static int mipi_dsi_northwest_probe(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id mipi_dsi_northwest_ids[] = { + { .compatible = "northwest,mipi-dsi" }, + { } +}; + +U_BOOT_DRIVER(mipi_dsi_northwest) = { + .name = "mipi_dsi_northwest", + .id = UCLASS_DSI_HOST, + .of_match = mipi_dsi_northwest_ids, + .probe = mipi_dsi_northwest_probe, + .remove = mipi_dsi_northwest_disable, + .ops = &mipi_dsi_northwest_ops, + .priv_auto = sizeof(struct mipi_dsi_northwest_info), +}; diff --git a/drivers/video/nxp/imx/mipi_dsi_northwest_regs.h b/drivers/video/nxp/imx/mipi_dsi_northwest_regs.h new file mode 100644 index 00000000000..6493403a0c4 --- /dev/null +++ b/drivers/video/nxp/imx/mipi_dsi_northwest_regs.h @@ -0,0 +1,142 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#ifndef __MIPI_DSI_NORTHWEST_REGS_H +#define __MIPI_DSI_NORTHWEST_REGS_H + +/* ---------------------------- register offsets --------------------------- */ + +/* sim */ +#define SIM_SOPT1 0x0 +#define MIPI_ISO_DISABLE 0x8 + +#define SIM_SOPT1CFG 0x4 +#define DSI_RST_DPI_N 0x80000000 +#define DSI_RST_ESC_N 0x40000000 +#define DSI_RST_BYTE_N 0x20000000 +#define DSI_SD 0x200 +#define DSI_CM 0x100 +#define DSI_PLL_EN 0x80 + +/* dphy */ +#define DPHY_PD_DPHY 0x300 +#define DPHY_M_PRG_HS_PREPARE 0x304 +#define DPHY_MC_PRG_HS_PREPARE 0x308 +#define DPHY_M_PRG_HS_ZERO 0x30c +#define DPHY_MC_PRG_HS_ZERO 0x310 +#define DPHY_M_PRG_HS_TRAIL 0x314 +#define DPHY_MC_PRG_HS_TRAIL 0x318 +#define DPHY_PD_PLL 0x31c +#define DPHY_TST 0x320 +#define DPHY_CN 0x324 +#define DPHY_CM 0x328 +#define DPHY_CO 0x32c +#define DPHY_LOCK 0x330 +#define DPHY_LOCK_BYP 0x334 +#define DPHY_RTERM_SEL 0x338 +#define DPHY_AUTO_PD_EN 0x33c +#define DPHY_RXLPRP 0x340 +#define DPHY_RXCDRP 0x344 + +/* host */ +#define HOST_CFG_NUM_LANES 0x0 +#define HOST_CFG_NONCONTINUOUS_CLK 0x4 +#define HOST_CFG_T_PRE 0x8 +#define HOST_CFG_T_POST 0xc +#define HOST_CFG_TX_GAP 0x10 +#define HOST_CFG_AUTOINSERT_EOTP 0x14 +#define HOST_CFG_EXTRA_CMDS_AFTER_EOTP 0x18 +#define HOST_CFG_HTX_TO_COUNT 0x1c +#define HOST_CFG_LRX_H_TO_COUNT 0x20 +#define HOST_CFG_BTA_H_TO_COUNT 0x24 +#define HOST_CFG_TWAKEUP 0x28 +#define HOST_CFG_STATUS_OUT 0x2c +#define HOST_RX_ERROR_STATUS 0x30 + +/* dpi */ +#define DPI_PIXEL_PAYLOAD_SIZE 0x200 +#define DPI_PIXEL_FIFO_SEND_LEVEL 0x204 +#define DPI_INTERFACE_COLOR_CODING 0x208 +#define DPI_PIXEL_FORMAT 0x20c +#define DPI_VSYNC_POLARITY 0x210 +#define DPI_HSYNC_POLARITY 0x214 +#define DPI_VIDEO_MODE 0x218 +#define DPI_HFP 0x21c +#define DPI_HBP 0x220 +#define DPI_HSA 0x224 +#define DPI_ENABLE_MULT_PKTS 0x228 +#define DPI_VBP 0x22c +#define DPI_VFP 0x230 +#define DPI_BLLP_MODE 0x234 +#define DPI_USE_NULL_PKT_BLLP 0x238 +#define DPI_VACTIVE 0x23c +#define DPI_VC 0x240 + +/* apb pkt */ +#define HOST_TX_PAYLOAD 0x280 + +#define HOST_PKT_CONTROL 0x284 +#define HOST_PKT_CONTROL_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_CONTROL_VC(x) (((x) & 0x3) << 16) +#define HOST_PKT_CONTROL_DT(x) (((x) & 0x3f) << 18) +#define HOST_PKT_CONTROL_HS_SEL(x) (((x) & 0x1) << 24) +#define HOST_PKT_CONTROL_BTA_TX(x) (((x) & 0x1) << 25) +#define HOST_PKT_CONTROL_BTA_NO_TX(x) (((x) & 0x1) << 26) + +#define HOST_SEND_PACKET 0x288 +#define HOST_PKT_STATUS 0x28c +#define HOST_PKT_FIFO_WR_LEVEL 0x290 +#define HOST_PKT_FIFO_RD_LEVEL 0x294 +#define HOST_PKT_RX_PAYLOAD 0x298 + +#define HOST_PKT_RX_PKT_HEADER 0x29c +#define HOST_PKT_RX_PKT_HEADER_WC(x) (((x) & 0xffff) << 0) +#define HOST_PKT_RX_PKT_HEADER_DT(x) (((x) & 0x3f) << 16) +#define HOST_PKT_RX_PKT_HEADER_VC(x) (((x) & 0x3) << 22) + +#define HOST_IRQ_STATUS 0x2a0 +#define HOST_IRQ_STATUS_SM_NOT_IDLE (1 << 0) +#define HOST_IRQ_STATUS_TX_PKT_DONE (1 << 1) +#define HOST_IRQ_STATUS_DPHY_DIRECTION (1 << 2) +#define HOST_IRQ_STATUS_TX_FIFO_OVFLW (1 << 3) +#define HOST_IRQ_STATUS_TX_FIFO_UDFLW (1 << 4) +#define HOST_IRQ_STATUS_RX_FIFO_OVFLW (1 << 5) +#define HOST_IRQ_STATUS_RX_FIFO_UDFLW (1 << 6) +#define HOST_IRQ_STATUS_RX_PKT_HDR_RCVD (1 << 7) +#define HOST_IRQ_STATUS_RX_PKT_PAYLOAD_DATA_RCVD (1 << 8) +#define HOST_IRQ_STATUS_HOST_BTA_TIMEOUT (1 << 29) +#define HOST_IRQ_STATUS_LP_RX_TIMEOUT (1 << 30) +#define HOST_IRQ_STATUS_HS_TX_TIMEOUT (1 << 31) + +#define HOST_IRQ_STATUS2 0x2a4 +#define HOST_IRQ_STATUS2_SINGLE_BIT_ECC_ERR (1 << 0) +#define HOST_IRQ_STATUS2_MULTI_BIT_ECC_ERR (1 << 1) +#define HOST_IRQ_STATUS2_CRC_ERR (1 << 2) + +#define HOST_IRQ_MASK 0x2a8 +#define HOST_IRQ_MASK_SM_NOT_IDLE_MASK (1 << 0) +#define HOST_IRQ_MASK_TX_PKT_DONE_MASK (1 << 1) +#define HOST_IRQ_MASK_DPHY_DIRECTION_MASK (1 << 2) +#define HOST_IRQ_MASK_TX_FIFO_OVFLW_MASK (1 << 3) +#define HOST_IRQ_MASK_TX_FIFO_UDFLW_MASK (1 << 4) +#define HOST_IRQ_MASK_RX_FIFO_OVFLW_MASK (1 << 5) +#define HOST_IRQ_MASK_RX_FIFO_UDFLW_MASK (1 << 6) +#define HOST_IRQ_MASK_RX_PKT_HDR_RCVD_MASK (1 << 7) +#define HOST_IRQ_MASK_RX_PKT_PAYLOAD_DATA_RCVD_MASK (1 << 8) +#define HOST_IRQ_MASK_HOST_BTA_TIMEOUT_MASK (1 << 29) +#define HOST_IRQ_MASK_LP_RX_TIMEOUT_MASK (1 << 30) +#define HOST_IRQ_MASK_HS_TX_TIMEOUT_MASK (1 << 31) + +#define HOST_IRQ_MASK2 0x2ac +#define HOST_IRQ_MASK2_SINGLE_BIT_ECC_ERR_MASK (1 << 0) +#define HOST_IRQ_MASK2_MULTI_BIT_ECC_ERR_MASK (1 << 1) +#define HOST_IRQ_MASK2_CRC_ERR_MASK (1 << 2) + +/* ------------------------------------- end -------------------------------- */ + +#endif diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/nxp/imx/mxc_ipuv3_fb.c similarity index 99% rename from drivers/video/imx/mxc_ipuv3_fb.c rename to drivers/video/nxp/imx/mxc_ipuv3_fb.c index 6cdbbafafb2..3c2293d4d4c 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/nxp/imx/mxc_ipuv3_fb.c @@ -23,7 +23,7 @@ #include #include #include -#include "../videomodes.h" +#include "../../videomodes.h" #include "ipu.h" #include "mxcfb.h" #include "ipu_regs.h" diff --git a/drivers/video/imx/mxcfb.h b/drivers/video/nxp/imx/mxcfb.h similarity index 100% rename from drivers/video/imx/mxcfb.h rename to drivers/video/nxp/imx/mxcfb.h diff --git a/drivers/video/nxp/imx/nw_dsi_imx.c b/drivers/video/nxp/imx/nw_dsi_imx.c new file mode 100644 index 00000000000..5daf86d4e42 --- /dev/null +++ b/drivers/video/nxp/imx/nw_dsi_imx.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct nw_dsi_imx_priv { + struct mipi_dsi_device device; + struct udevice *panel; + struct udevice *dsi_host; + unsigned int data_lanes; +}; + +static int nw_dsi_imx_attach(struct udevice *dev) +{ + struct nw_dsi_imx_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + struct mipi_dsi_panel_plat *mplat; + struct display_timing timings; + int ret; + + priv->panel = video_link_get_next_device(dev); + if (!priv->panel || + device_get_uclass_id(priv->panel) != UCLASS_PANEL) { + dev_err(dev, "get panel device error\n"); + return -ENODEV; + } + + mplat = dev_get_plat(priv->panel); + mplat->device = &priv->device; + + ret = video_link_get_display_timings(&timings); + if (ret) { + dev_err(dev, "decode display timing error %d\n", ret); + return ret; + } + + ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host); + if (ret) { + dev_err(dev, "No video dsi host detected %d\n", ret); + return ret; + } + + ret = dsi_host_init(priv->dsi_host, device, &timings, + priv->data_lanes, + NULL); + if (ret) { + dev_err(dev, "failed to initialize mipi dsi host\n"); + return ret; + } + + return 0; +} + +static int nw_dsi_imx_set_backlight(struct udevice *dev, int percent) +{ + struct nw_dsi_imx_priv *priv = dev_get_priv(dev); + int ret; + + ret = panel_enable_backlight(priv->panel); + if (ret) { + dev_err(dev, "panel %s enable backlight error %d\n", + priv->panel->name, ret); + return ret; + } + + ret = dsi_host_enable(priv->dsi_host); + if (ret) { + dev_err(dev, "failed to enable mipi dsi host\n"); + return ret; + } + + return 0; +} + +static int nw_dsi_imx_probe(struct udevice *dev) +{ + struct nw_dsi_imx_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + int ret; + + device->dev = dev; + + ret = dev_read_u32(dev, "data-lanes-num", &priv->data_lanes); + if (ret) { + printf("fail to get data lanes property %d\n", ret); + return -EINVAL; + } + + return ret; +} + +static int nw_dsi_imx_remove(struct udevice *dev) +{ + struct nw_dsi_imx_priv *priv = dev_get_priv(dev); + int ret; + + if (priv->panel) + device_remove(priv->panel, DM_REMOVE_NORMAL); + + ret = dsi_host_disable(priv->dsi_host); + if (ret) { + dev_err(dev, "failed to enable mipi dsi host\n"); + return ret; + } + + return 0; +} + +struct video_bridge_ops nw_dsi_imx_ops = { + .attach = nw_dsi_imx_attach, + .set_backlight = nw_dsi_imx_set_backlight, +}; + +static const struct udevice_id nw_dsi_imx_ids[] = { + { .compatible = "fsl,imx7ulp-mipi-dsi" }, + { } +}; + +U_BOOT_DRIVER(nw_dsi_imx) = { + .name = "nw_dsi_imx", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = nw_dsi_imx_ids, + .bind = dm_scan_fdt_dev, + .remove = nw_dsi_imx_remove, + .probe = nw_dsi_imx_probe, + .ops = &nw_dsi_imx_ops, + .priv_auto = sizeof(struct nw_dsi_imx_priv), +}; diff --git a/drivers/video/nxp/imx/sec_dsim_imx.c b/drivers/video/nxp/imx/sec_dsim_imx.c new file mode 100644 index 00000000000..644dafb2992 --- /dev/null +++ b/drivers/video/nxp/imx/sec_dsim_imx.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* fixed phy ref clk rate */ +#define PHY_REF_CLK 27000000 + +struct imx_sec_dsim_priv { + struct mipi_dsi_device device; + void __iomem *base; + struct udevice *panel; + struct udevice *dsi_host; + struct reset_ctl_bulk soft_resetn; + struct reset_ctl_bulk clk_enable; + struct reset_ctl_bulk mipi_reset; +}; + +#if IS_ENABLED(CONFIG_DM_RESET) +static int sec_dsim_rstc_reset(struct reset_ctl_bulk *rstc, bool assert) +{ + int ret; + + if (!rstc) + return 0; + + ret = assert ? reset_assert_bulk(rstc) : + reset_deassert_bulk(rstc); + + return ret; +} + +static int sec_dsim_of_parse_resets(struct udevice *dev) +{ + int ret; + ofnode parent, child; + struct ofnode_phandle_args args; + struct reset_ctl_bulk rstc; + const char *compat; + uint32_t rstc_num = 0; + + struct imx_sec_dsim_priv *priv = dev_get_priv(dev); + + ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0, + 0, &args); + if (ret) + return ret; + + parent = args.node; + ofnode_for_each_subnode(child, parent) { + compat = ofnode_get_property(child, "compatible", NULL); + if (!compat) + continue; + + ret = reset_get_bulk_nodev(child, &rstc); + if (ret) + continue; + + if (!of_compat_cmp("dsi,soft-resetn", compat, 0)) { + priv->soft_resetn = rstc; + rstc_num++; + } else if (!of_compat_cmp("dsi,clk-enable", compat, 0)) { + priv->clk_enable = rstc; + rstc_num++; + } else if (!of_compat_cmp("dsi,mipi-reset", compat, 0)) { + priv->mipi_reset = rstc; + rstc_num++; + } else + dev_warn(dev, "invalid dsim reset node: %s\n", compat); + } + + if (!rstc_num) { + dev_err(dev, "no invalid reset control exists\n"); + return -EINVAL; + } + + return 0; +} +#endif + +static int imx_sec_dsim_attach(struct udevice *dev) +{ + struct imx_sec_dsim_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + struct mipi_dsi_panel_plat *mplat; + struct display_timing timings; + int ret; + + priv->panel = video_link_get_next_device(dev); + if (!priv->panel || + device_get_uclass_id(priv->panel) != UCLASS_PANEL) { + dev_err(dev, "get panel device error\n"); + return -ENODEV; + } + + mplat = dev_get_plat(priv->panel); + mplat->device = &priv->device; + + ret = video_link_get_display_timings(&timings); + if (ret) { + dev_err(dev, "decode display timing error %d\n", ret); + return ret; + } + + ret = uclass_get_device(UCLASS_DSI_HOST, 0, &priv->dsi_host); + if (ret) { + dev_err(dev, "No video dsi host detected %d\n", ret); + return ret; + } + + ret = dsi_host_init(priv->dsi_host, device, &timings, 4, + NULL); + if (ret) { + dev_err(dev, "failed to initialize mipi dsi host\n"); + return ret; + } + + return 0; +} + +static int imx_sec_dsim_set_backlight(struct udevice *dev, int percent) +{ + struct imx_sec_dsim_priv *priv = dev_get_priv(dev); + int ret; + + ret = panel_enable_backlight(priv->panel); + if (ret) { + dev_err(dev, "panel %s enable backlight error %d\n", + priv->panel->name, ret); + return ret; + } + + ret = dsi_host_enable(priv->dsi_host); + if (ret) { + dev_err(dev, "failed to enable mipi dsi host\n"); + return ret; + } + + return 0; +} + +static int imx_sec_dsim_probe(struct udevice *dev) +{ + struct imx_sec_dsim_priv *priv = dev_get_priv(dev); + struct mipi_dsi_device *device = &priv->device; + + device->dev = dev; + +#if IS_ENABLED(CONFIG_DM_RESET) + int ret; + /* Allow to not have resets */ + ret = sec_dsim_of_parse_resets(dev); + if (!ret) { + ret = sec_dsim_rstc_reset(&priv->soft_resetn, false); + if (ret) { + dev_err(dev, "deassert soft_resetn failed\n"); + return ret; + } + + ret = sec_dsim_rstc_reset(&priv->clk_enable, true); + if (ret) { + dev_err(dev, "assert clk_enable failed\n"); + return ret; + } + + ret = sec_dsim_rstc_reset(&priv->mipi_reset, false); + if (ret) { + dev_err(dev, "deassert mipi_reset failed\n"); + return ret; + } + } +#endif + + return 0; +} + +static int imx_sec_dsim_remove(struct udevice *dev) +{ + struct imx_sec_dsim_priv *priv = dev_get_priv(dev); + int ret; + + if (priv->panel) + device_remove(priv->panel, DM_REMOVE_NORMAL); + + ret = dsi_host_disable(priv->dsi_host); + if (ret) { + dev_err(dev, "failed to enable mipi dsi host\n"); + return ret; + } + + return 0; +} + +struct video_bridge_ops imx_sec_dsim_ops = { + .attach = imx_sec_dsim_attach, + .set_backlight = imx_sec_dsim_set_backlight, +}; + +static const struct udevice_id imx_sec_dsim_ids[] = { + { .compatible = "fsl,imx8mm-mipi-dsim" }, + { .compatible = "fsl,imx8mn-mipi-dsim" }, + { .compatible = "fsl,imx8mp-mipi-dsim" }, + { } +}; + +U_BOOT_DRIVER(imx_sec_dsim) = { + .name = "imx_sec_dsim", + .id = UCLASS_VIDEO_BRIDGE, + .of_match = imx_sec_dsim_ids, + .bind = dm_scan_fdt_dev, + .remove = imx_sec_dsim_remove, + .probe = imx_sec_dsim_probe, + .ops = &imx_sec_dsim_ops, + .priv_auto = sizeof(struct imx_sec_dsim_priv), +}; diff --git a/drivers/video/nxp/imx/sec_mipi_dsim.c b/drivers/video/nxp/imx/sec_mipi_dsim.c new file mode 100644 index 00000000000..d30021e2cd2 --- /dev/null +++ b/drivers/video/nxp/imx/sec_mipi_dsim.c @@ -0,0 +1,1068 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MIPI_FIFO_TIMEOUT 250000 /* 250ms */ + +#define DRIVER_NAME "sec_mipi_dsim" + +/* dsim registers */ +#define DSIM_VERSION 0x00 +#define DSIM_STATUS 0x04 +#define DSIM_RGB_STATUS 0x08 +#define DSIM_SWRST 0x0c +#define DSIM_CLKCTRL 0x10 +#define DSIM_TIMEOUT 0x14 +#define DSIM_CONFIG 0x18 +#define DSIM_ESCMODE 0x1c +#define DSIM_MDRESOL 0x20 +#define DSIM_MVPORCH 0x24 +#define DSIM_MHPORCH 0x28 +#define DSIM_MSYNC 0x2c +#define DSIM_SDRESOL 0x30 +#define DSIM_INTSRC 0x34 +#define DSIM_INTMSK 0x38 + +/* packet */ +#define DSIM_PKTHDR 0x3c +#define DSIM_PAYLOAD 0x40 +#define DSIM_RXFIFO 0x44 +#define DSIM_FIFOTHLD 0x48 +#define DSIM_FIFOCTRL 0x4c +#define DSIM_MEMACCHR 0x50 +#define DSIM_MULTI_PKT 0x78 + +/* pll control */ +#define DSIM_PLLCTRL_1G 0x90 +#define DSIM_PLLCTRL 0x94 +#define DSIM_PLLCTRL1 0x98 +#define DSIM_PLLCTRL2 0x9c +#define DSIM_PLLTMR 0xa0 + +/* dphy */ +#define DSIM_PHYTIMING 0xb4 +#define DSIM_PHYTIMING1 0xb8 +#define DSIM_PHYTIMING2 0xbc + +/* reg bit manipulation */ +#define REG_MASK(e, s) (((1 << ((e) - (s) + 1)) - 1) << (s)) +#define REG_PUT(x, e, s) (((x) << (s)) & REG_MASK(e, s)) +#define REG_GET(x, e, s) (((x) & REG_MASK(e, s)) >> (s)) + +/* register bit fields */ +#define STATUS_PLLSTABLE BIT(31) +#define STATUS_SWRSTRLS BIT(20) +#define STATUS_TXREADYHSCLK BIT(10) +#define STATUS_ULPSCLK BIT(9) +#define STATUS_STOPSTATECLK BIT(8) +#define STATUS_GET_ULPSDAT(x) REG_GET(x, 7, 4) +#define STATUS_GET_STOPSTATEDAT(x) REG_GET(x, 3, 0) + +#define RGB_STATUS_CMDMODE_INSEL BIT(31) +#define RGB_STATUS_GET_RGBSTATE(x) REG_GET(x, 12, 0) + +#define CLKCTRL_TXREQUESTHSCLK BIT(31) +#define CLKCTRL_DPHY_SEL_1G BIT(29) +#define CLKCTRL_DPHY_SEL_1P5G (0x0 << 29) +#define CLKCTRL_ESCCLKEN BIT(28) +#define CLKCTRL_PLLBYPASS BIT(29) +#define CLKCTRL_BYTECLKSRC_DPHY_PLL REG_PUT(0, 26, 25) +#define CLKCTRL_BYTECLKEN BIT(24) +#define CLKCTRL_SET_LANEESCCLKEN(x) REG_PUT(x, 23, 19) +#define CLKCTRL_SET_ESCPRESCALER(x) REG_PUT(x, 15, 0) + +#define TIMEOUT_SET_BTAOUT(x) REG_PUT(x, 23, 16) +#define TIMEOUT_SET_LPDRTOUT(x) REG_PUT(x, 15, 0) + +#define CONFIG_NON_CONTINOUS_CLOCK_LANE BIT(31) +#define CONFIG_CLKLANE_STOP_START BIT(30) +#define CONFIG_MFLUSH_VS BIT(29) +#define CONFIG_EOT_R03 BIT(28) +#define CONFIG_SYNCINFORM BIT(27) +#define CONFIG_BURSTMODE BIT(26) +#define CONFIG_VIDEOMODE BIT(25) +#define CONFIG_AUTOMODE BIT(24) +#define CONFIG_HSEDISABLEMODE BIT(23) +#define CONFIG_HFPDISABLEMODE BIT(22) +#define CONFIG_HBPDISABLEMODE BIT(21) +#define CONFIG_HSADISABLEMODE BIT(20) +#define CONFIG_SET_MAINVC(x) REG_PUT(x, 19, 18) +#define CONFIG_SET_SUBVC(x) REG_PUT(x, 17, 16) +#define CONFIG_SET_MAINPIXFORMAT(x) REG_PUT(x, 14, 12) +#define CONFIG_SET_SUBPIXFORMAT(x) REG_PUT(x, 10, 8) +#define CONFIG_SET_NUMOFDATLANE(x) REG_PUT(x, 6, 5) +#define CONFIG_SET_LANEEN(x) REG_PUT(x, 4, 0) + +#define ESCMODE_SET_STOPSTATE_CNT(X) REG_PUT(x, 31, 21) +#define ESCMODE_FORCESTOPSTATE BIT(20) +#define ESCMODE_FORCEBTA BIT(16) +#define ESCMODE_CMDLPDT BIT(7) +#define ESCMODE_TXLPDT BIT(6) +#define ESCMODE_TXTRIGGERRST BIT(5) + +#define MDRESOL_MAINSTANDBY BIT(31) +#define MDRESOL_SET_MAINVRESOL(x) REG_PUT(x, 27, 16) +#define MDRESOL_SET_MAINHRESOL(x) REG_PUT(x, 11, 0) + +#define MVPORCH_SET_CMDALLOW(x) REG_PUT(x, 31, 28) +#define MVPORCH_SET_STABLEVFP(x) REG_PUT(x, 26, 16) +#define MVPORCH_SET_MAINVBP(x) REG_PUT(x, 10, 0) + +#define MHPORCH_SET_MAINHFP(x) REG_PUT(x, 31, 16) +#define MHPORCH_SET_MAINHBP(x) REG_PUT(x, 15, 0) + +#define MSYNC_SET_MAINVSA(x) REG_PUT(x, 31, 22) +#define MSYNC_SET_MAINHSA(x) REG_PUT(x, 15, 0) + +#define INTSRC_PLLSTABLE BIT(31) +#define INTSRC_SWRSTRELEASE BIT(30) +#define INTSRC_SFRPLFIFOEMPTY BIT(29) +#define INTSRC_SFRPHFIFOEMPTY BIT(28) +#define INTSRC_FRAMEDONE BIT(24) +#define INTSRC_LPDRTOUT BIT(21) +#define INTSRC_TATOUT BIT(20) +#define INTSRC_RXDATDONE BIT(18) +#define INTSRC_MASK (INTSRC_PLLSTABLE | \ + INTSRC_SWRSTRELEASE | \ + INTSRC_SFRPLFIFOEMPTY | \ + INTSRC_SFRPHFIFOEMPTY | \ + INTSRC_FRAMEDONE | \ + INTSRC_LPDRTOUT | \ + INTSRC_TATOUT | \ + INTSRC_RXDATDONE) + +#define INTMSK_MSKPLLSTABLE BIT(31) +#define INTMSK_MSKSWRELEASE BIT(30) +#define INTMSK_MSKSFRPLFIFOEMPTY BIT(29) +#define INTMSK_MSKSFRPHFIFOEMPTY BIT(28) +#define INTMSK_MSKFRAMEDONE BIT(24) +#define INTMSK_MSKLPDRTOUT BIT(21) +#define INTMSK_MSKTATOUT BIT(20) +#define INTMSK_MSKRXDATDONE BIT(18) + +#define PKTHDR_SET_DATA1(x) REG_PUT(x, 23, 16) +#define PKTHDR_GET_DATA1(x) REG_GET(x, 23, 16) +#define PKTHDR_SET_DATA0(x) REG_PUT(x, 15, 8) +#define PKTHDR_GET_DATA0(x) REG_GET(x, 15, 8) +#define PKTHDR_GET_WC(x) REG_GET(x, 23, 8) +#define PKTHDR_SET_DI(x) REG_PUT(x, 7, 0) +#define PKTHDR_GET_DI(x) REG_GET(x, 7, 0) +#define PKTHDR_SET_DT(x) REG_PUT(x, 5, 0) +#define PKTHDR_GET_DT(x) REG_GET(x, 5, 0) +#define PKTHDR_SET_VC(x) REG_PUT(x, 7, 6) +#define PKTHDR_GET_VC(x) REG_GET(x, 7, 6) + +#define FIFOCTRL_FULLRX BIT(25) +#define FIFOCTRL_EMPTYRX BIT(24) +#define FIFOCTRL_FULLHSFR BIT(23) +#define FIFOCTRL_EMPTYHSFR BIT(22) +#define FIFOCTRL_FULLLSFR BIT(21) +#define FIFOCTRL_EMPTYLSFR BIT(20) +#define FIFOCTRL_FULLHMAIN BIT(11) +#define FIFOCTRL_EMPTYHMAIN BIT(10) +#define FIFOCTRL_FULLLMAIN BIT(9) +#define FIFOCTRL_EMPTYLMAIN BIT(8) +#define FIFOCTRL_NINITRX BIT(4) +#define FIFOCTRL_NINITSFR BIT(3) +#define FIFOCTRL_NINITI80 BIT(2) +#define FIFOCTRL_NINITSUB BIT(1) +#define FIFOCTRL_NINITMAIN BIT(0) + +#define PLLCTRL_DPDNSWAP_CLK BIT(25) +#define PLLCTRL_DPDNSWAP_DAT BIT(24) +#define PLLCTRL_PLLEN BIT(23) +#define PLLCTRL_SET_PMS(x) REG_PUT(x, 19, 1) + +#define PHYTIMING_SET_M_TLPXCTL(x) REG_PUT(x, 15, 8) +#define PHYTIMING_SET_M_THSEXITCTL(x) REG_PUT(x, 7, 0) + +#define PHYTIMING1_SET_M_TCLKPRPRCTL(x) REG_PUT(x, 31, 24) +#define PHYTIMING1_SET_M_TCLKZEROCTL(x) REG_PUT(x, 23, 16) +#define PHYTIMING1_SET_M_TCLKPOSTCTL(x) REG_PUT(x, 15, 8) +#define PHYTIMING1_SET_M_TCLKTRAILCTL(x) REG_PUT(x, 7, 0) + +#define PHYTIMING2_SET_M_THSPRPRCTL(x) REG_PUT(x, 23, 16) +#define PHYTIMING2_SET_M_THSZEROCTL(x) REG_PUT(x, 15, 8) +#define PHYTIMING2_SET_M_THSTRAILCTL(x) REG_PUT(x, 7, 0) + +#define dsim_read(dsim, reg) readl(dsim->base + reg) +#define dsim_write(dsim, val, reg) writel(val, dsim->base + reg) + +#define MAX_MAIN_HRESOL 2047 +#define MAX_MAIN_VRESOL 2047 +#define MAX_SUB_HRESOL 1024 +#define MAX_SUB_VRESOL 1024 + +/* in KHZ */ +#define MAX_ESC_CLK_FREQ 20000 + +/* dsim all irqs index */ +#define PLLSTABLE 1 +#define SWRSTRELEASE 2 +#define SFRPLFIFOEMPTY 3 +#define SFRPHFIFOEMPTY 4 +#define SYNCOVERRIDE 5 +#define BUSTURNOVER 6 +#define FRAMEDONE 7 +#define LPDRTOUT 8 +#define TATOUT 9 +#define RXDATDONE 10 +#define RXTE 11 +#define RXACK 12 +#define ERRRXECC 13 +#define ERRRXCRC 14 +#define ERRESC3 15 +#define ERRESC2 16 +#define ERRESC1 17 +#define ERRESC0 18 +#define ERRSYNC3 19 +#define ERRSYNC2 20 +#define ERRSYNC1 21 +#define ERRSYNC0 22 +#define ERRCONTROL3 23 +#define ERRCONTROL2 24 +#define ERRCONTROL1 25 +#define ERRCONTROL0 26 + +/* Dispmix Control & GPR Registers */ +#define DISPLAY_MIX_SFT_RSTN_CSR 0x00 +#ifdef CONFIG_IMX8MN +#define MIPI_DSI_I_PRESETn_SFT_EN BIT(0) | BIT(1) +#else + #define MIPI_DSI_I_PRESETn_SFT_EN BIT(5) +#endif +#define DISPLAY_MIX_CLK_EN_CSR 0x04 + +#ifdef CONFIG_IMX8MN +#define MIPI_DSI_PCLK_SFT_EN BIT(0) +#define MIPI_DSI_CLKREF_SFT_EN BIT(1) +#else + #define MIPI_DSI_PCLK_SFT_EN BIT(8) + #define MIPI_DSI_CLKREF_SFT_EN BIT(9) +#endif +#define GPR_MIPI_RESET_DIV 0x08 + /* Clock & Data lanes reset: Active Low */ + #define GPR_MIPI_S_RESETN BIT(16) + #define GPR_MIPI_M_RESETN BIT(17) + +#define PS2KHZ(ps) (1000000000UL / (ps)) + +#define MIPI_HFP_PKT_OVERHEAD 6 +#define MIPI_HBP_PKT_OVERHEAD 6 +#define MIPI_HSA_PKT_OVERHEAD 6 + + +/* DSIM PLL configuration from spec: + * + * Fout(DDR) = (M * Fin) / (P * 2^S), so Fout / Fin = M / (P * 2^S) + * Fin_pll = Fin / P (6 ~ 12 MHz) + * S: [2:0], M: [12:3], P: [18:13], so + * TODO: 'S' is in [0 ~ 3], 'M' is in, 'P' is in [1 ~ 33] + * + */ + +struct sec_mipi_dsim { + void __iomem *base; + + /* kHz clocks */ + uint64_t pix_clk; + uint64_t bit_clk; + + unsigned int lanes; + unsigned int channel; /* virtual channel */ + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; + unsigned int pms; + unsigned int p; + unsigned int m; + unsigned int s; + + struct mipi_dsi_device *device; + uint32_t max_data_lanes; + uint64_t max_data_rate; + + struct mipi_dsi_host dsi_host; + + struct display_timing timings; +}; + +static int sec_mipi_dsim_wait_for_pkt_done(struct sec_mipi_dsim *dsim, unsigned long timeout) +{ + uint32_t intsrc; + + do { + intsrc = dsim_read(dsim, DSIM_INTSRC); + if (intsrc & INTSRC_SFRPLFIFOEMPTY) { + dsim_write(dsim, INTSRC_SFRPLFIFOEMPTY, DSIM_INTSRC); + return 0; + } + + udelay(1); + } while (--timeout); + + return -ETIMEDOUT; +} + +static int sec_mipi_dsim_wait_for_hdr_done(struct sec_mipi_dsim *dsim, unsigned long timeout) +{ + uint32_t intsrc; + + do { + intsrc = dsim_read(dsim, DSIM_INTSRC); + if (intsrc & INTSRC_SFRPHFIFOEMPTY) { + dsim_write(dsim, INTSRC_SFRPHFIFOEMPTY, DSIM_INTSRC); + return 0; + } + + udelay(1); + } while (--timeout); + + return -ETIMEDOUT; +} + + +static int sec_mipi_dsim_wait_for_rx_done(struct sec_mipi_dsim *dsim, unsigned long timeout) +{ + uint32_t intsrc; + + do { + intsrc = dsim_read(dsim, DSIM_INTSRC); + if (intsrc & INTSRC_RXDATDONE) { + dsim_write(dsim, INTSRC_RXDATDONE, DSIM_INTSRC); + return 0; + } + + udelay(1); + } while (--timeout); + + return -ETIMEDOUT; +} + +static int sec_mipi_dsim_wait_pll_stable(struct sec_mipi_dsim *dsim) +{ + uint32_t status; + ulong start; + + start = get_timer(0); /* Get current timestamp */ + + do { + status = dsim_read(dsim, DSIM_STATUS); + if (status & STATUS_PLLSTABLE) + return 0; + } while (get_timer(0) < (start + 100)); /* Wait 100ms */ + + return -ETIMEDOUT; +} + +static int sec_mipi_dsim_config_pll(struct sec_mipi_dsim *dsim) +{ + int ret; + uint32_t pllctrl = 0, status, data_lanes_en, stop; + + dsim_write(dsim, 0x8000, DSIM_PLLTMR); + + /* TODO: config dp/dn swap if requires */ + + pllctrl |= PLLCTRL_SET_PMS(dsim->pms) | PLLCTRL_PLLEN; + dsim_write(dsim, pllctrl, DSIM_PLLCTRL); + + ret = sec_mipi_dsim_wait_pll_stable(dsim); + if (ret) { + printf("wait for pll stable time out\n"); + return ret; + } + + /* wait for clk & data lanes to go to stop state */ + mdelay(1); + + data_lanes_en = (0x1 << dsim->lanes) - 1; + status = dsim_read(dsim, DSIM_STATUS); + if (!(status & STATUS_STOPSTATECLK)) { + printf("clock is not in stop state\n"); + return -EBUSY; + } + + stop = STATUS_GET_STOPSTATEDAT(status); + if ((stop & data_lanes_en) != data_lanes_en) { + printf("one or more data lanes is not in stop state\n"); + return -EBUSY; + } + + return 0; +} + +static void sec_mipi_dsim_set_main_mode(struct sec_mipi_dsim *dsim) +{ + uint32_t bpp, hfp_wc, hbp_wc, hsa_wc, wc; + uint32_t mdresol = 0, mvporch = 0, mhporch = 0, msync = 0; + struct display_timing *timings = &dsim->timings; + + mdresol |= MDRESOL_SET_MAINVRESOL(timings->vactive.typ) | + MDRESOL_SET_MAINHRESOL(timings->hactive.typ); + dsim_write(dsim, mdresol, DSIM_MDRESOL); + + mvporch |= MVPORCH_SET_MAINVBP(timings->vback_porch.typ) | + MVPORCH_SET_STABLEVFP(timings->vfront_porch.typ) | + MVPORCH_SET_CMDALLOW(0x0); + dsim_write(dsim, mvporch, DSIM_MVPORCH); + + bpp = mipi_dsi_pixel_format_to_bpp(dsim->format); + + + wc = DIV_ROUND_UP(timings->hfront_porch.typ* (bpp >> 3), + dsim->lanes); + hfp_wc = wc > MIPI_HFP_PKT_OVERHEAD ? + wc - MIPI_HFP_PKT_OVERHEAD : timings->hfront_porch.typ; + wc = DIV_ROUND_UP(timings->hback_porch.typ * (bpp >> 3), + dsim->lanes); + hbp_wc = wc > MIPI_HBP_PKT_OVERHEAD ? + wc - MIPI_HBP_PKT_OVERHEAD : timings->hback_porch.typ; + + mhporch |= MHPORCH_SET_MAINHFP(hfp_wc) | + MHPORCH_SET_MAINHBP(hbp_wc); + + dsim_write(dsim, mhporch, DSIM_MHPORCH); + + wc = DIV_ROUND_UP(timings->hsync_len.typ * (bpp >> 3), + dsim->lanes); + hsa_wc = wc > MIPI_HSA_PKT_OVERHEAD ? + wc - MIPI_HSA_PKT_OVERHEAD : timings->hsync_len.typ; + + msync |= MSYNC_SET_MAINVSA(timings->vsync_len.typ) | + MSYNC_SET_MAINHSA(hsa_wc); + + debug("hfp_wc %u hbp_wc %u hsa_wc %u\n", hfp_wc, hbp_wc, hsa_wc); + + dsim_write(dsim, msync, DSIM_MSYNC); +} + +static void sec_mipi_dsim_config_dpi(struct sec_mipi_dsim *dsim) +{ + uint32_t config = 0, rgb_status = 0, data_lanes_en; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) + rgb_status &= ~RGB_STATUS_CMDMODE_INSEL; + else + rgb_status |= RGB_STATUS_CMDMODE_INSEL; + + dsim_write(dsim, rgb_status, DSIM_RGB_STATUS); + + if (dsim->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) + config |= CONFIG_CLKLANE_STOP_START; + + if (dsim->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH) + config |= CONFIG_MFLUSH_VS; + + /* disable EoT packets in HS mode */ + if (dsim->mode_flags & MIPI_DSI_MODE_EOT_PACKET) + config |= CONFIG_EOT_R03; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) { + config |= CONFIG_VIDEOMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + config |= CONFIG_BURSTMODE; + + else if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + config |= CONFIG_SYNCINFORM; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) + config |= CONFIG_AUTOMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) + config |= CONFIG_HSEDISABLEMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HFP) + config |= CONFIG_HFPDISABLEMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HBP) + config |= CONFIG_HBPDISABLEMODE; + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO_HSA) + config |= CONFIG_HSADISABLEMODE; + } + + config |= CONFIG_SET_MAINVC(dsim->channel); + + if (dsim->mode_flags & MIPI_DSI_MODE_VIDEO) { + switch (dsim->format) { + case MIPI_DSI_FMT_RGB565: + config |= CONFIG_SET_MAINPIXFORMAT(0x4); + break; + case MIPI_DSI_FMT_RGB666_PACKED: + config |= CONFIG_SET_MAINPIXFORMAT(0x5); + break; + case MIPI_DSI_FMT_RGB666: + config |= CONFIG_SET_MAINPIXFORMAT(0x6); + break; + case MIPI_DSI_FMT_RGB888: + config |= CONFIG_SET_MAINPIXFORMAT(0x7); + break; + default: + config |= CONFIG_SET_MAINPIXFORMAT(0x7); + break; + } + } + + /* config data lanes number and enable lanes */ + data_lanes_en = (0x1 << dsim->lanes) - 1; + config |= CONFIG_SET_NUMOFDATLANE(dsim->lanes - 1); + config |= CONFIG_SET_LANEEN(0x1 | data_lanes_en << 1); + + debug("DSIM config 0x%x\n", config); + + dsim_write(dsim, config, DSIM_CONFIG); +} + +static void sec_mipi_dsim_config_cmd_lpm(struct sec_mipi_dsim *dsim, + bool enable) +{ + uint32_t escmode; + + escmode = dsim_read(dsim, DSIM_ESCMODE); + + if (enable) + escmode |= ESCMODE_CMDLPDT; + else + escmode &= ~ESCMODE_CMDLPDT; + + dsim_write(dsim, escmode, DSIM_ESCMODE); +} + +static void sec_mipi_dsim_config_dphy(struct sec_mipi_dsim *dsim) +{ + uint32_t phytiming = 0, phytiming1 = 0, phytiming2 = 0, timeout = 0; + + /* TODO: add a PHY timing table arranged by the pll Fout */ + + phytiming |= PHYTIMING_SET_M_TLPXCTL(6) | + PHYTIMING_SET_M_THSEXITCTL(11); + dsim_write(dsim, phytiming, DSIM_PHYTIMING); + + phytiming1 |= PHYTIMING1_SET_M_TCLKPRPRCTL(7) | + PHYTIMING1_SET_M_TCLKZEROCTL(38) | + PHYTIMING1_SET_M_TCLKPOSTCTL(13) | + PHYTIMING1_SET_M_TCLKTRAILCTL(8); + dsim_write(dsim, phytiming1, DSIM_PHYTIMING1); + + phytiming2 |= PHYTIMING2_SET_M_THSPRPRCTL(8) | + PHYTIMING2_SET_M_THSZEROCTL(13) | + PHYTIMING2_SET_M_THSTRAILCTL(11); + dsim_write(dsim, phytiming2, DSIM_PHYTIMING2); + + timeout |= TIMEOUT_SET_BTAOUT(0xf) | + TIMEOUT_SET_LPDRTOUT(0xf); + dsim_write(dsim, 0xf000f, DSIM_TIMEOUT); +} + +static void sec_mipi_dsim_write_pl_to_sfr_fifo(struct sec_mipi_dsim *dsim, + const void *payload, + size_t length) +{ + uint32_t pl_data; + + if (!length) + return; + + while (length >= 4) { + pl_data = get_unaligned_le32(payload); + dsim_write(dsim, pl_data, DSIM_PAYLOAD); + payload += 4; + length -= 4; + } + + pl_data = 0; + switch (length) { + case 3: + pl_data |= ((u8 *)payload)[2] << 16; + case 2: + pl_data |= ((u8 *)payload)[1] << 8; + case 1: + pl_data |= ((u8 *)payload)[0]; + dsim_write(dsim, pl_data, DSIM_PAYLOAD); + break; + } +} + +static void sec_mipi_dsim_write_ph_to_sfr_fifo(struct sec_mipi_dsim *dsim, + void *header, + bool use_lpm) +{ + uint32_t pkthdr; + + pkthdr = PKTHDR_SET_DATA1(((u8 *)header)[2]) | /* WC MSB */ + PKTHDR_SET_DATA0(((u8 *)header)[1]) | /* WC LSB */ + PKTHDR_SET_DI(((u8 *)header)[0]); /* Data ID */ + + dsim_write(dsim, pkthdr, DSIM_PKTHDR); +} + +static int sec_mipi_dsim_read_pl_from_sfr_fifo(struct sec_mipi_dsim *dsim, + void *payload, + size_t length) +{ + uint8_t data_type; + uint16_t word_count = 0; + uint32_t fifoctrl, ph, pl; + + fifoctrl = dsim_read(dsim, DSIM_FIFOCTRL); + + if (WARN_ON(fifoctrl & FIFOCTRL_EMPTYRX)) + return -EINVAL; + + ph = dsim_read(dsim, DSIM_RXFIFO); + data_type = PKTHDR_GET_DT(ph); + switch (data_type) { + case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: + dev_err(dsim->device->dev, "peripheral report error: (0-7)%x, (8-15)%x\n", + PKTHDR_GET_DATA0(ph), PKTHDR_GET_DATA1(ph)); + return -EPROTO; + case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: + case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: + if (!WARN_ON(length < 2)) { + ((u8 *)payload)[1] = PKTHDR_GET_DATA1(ph); + word_count++; + } + /* fall through */ + case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: + case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: + ((u8 *)payload)[0] = PKTHDR_GET_DATA0(ph); + word_count++; + length = word_count; + break; + case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: + case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: + word_count = PKTHDR_GET_WC(ph); + if (word_count > length) { + dev_err(dsim->device->dev, "invalid receive buffer length\n"); + return -EINVAL; + } + + length = word_count; + + while (word_count >= 4) { + pl = dsim_read(dsim, DSIM_RXFIFO); + ((u8 *)payload)[0] = pl & 0xff; + ((u8 *)payload)[1] = (pl >> 8) & 0xff; + ((u8 *)payload)[2] = (pl >> 16) & 0xff; + ((u8 *)payload)[3] = (pl >> 24) & 0xff; + payload += 4; + word_count -= 4; + } + + if (word_count > 0) { + pl = dsim_read(dsim, DSIM_RXFIFO); + + switch (word_count) { + case 3: + ((u8 *)payload)[2] = (pl >> 16) & 0xff; + case 2: + ((u8 *)payload)[1] = (pl >> 8) & 0xff; + case 1: + ((u8 *)payload)[0] = pl & 0xff; + break; + } + } + + break; + default: + return -EINVAL; + } + + return length; +} + +static void sec_mipi_dsim_init_fifo_pointers(struct sec_mipi_dsim *dsim) +{ + uint32_t fifoctrl, fifo_ptrs; + + fifoctrl = dsim_read(dsim, DSIM_FIFOCTRL); + + fifo_ptrs = FIFOCTRL_NINITRX | + FIFOCTRL_NINITSFR | + FIFOCTRL_NINITI80 | + FIFOCTRL_NINITSUB | + FIFOCTRL_NINITMAIN; + + fifoctrl &= ~fifo_ptrs; + dsim_write(dsim, fifoctrl, DSIM_FIFOCTRL); + udelay(500); + + fifoctrl |= fifo_ptrs; + dsim_write(dsim, fifoctrl, DSIM_FIFOCTRL); + udelay(500); +} + + +static void sec_mipi_dsim_config_clkctrl(struct sec_mipi_dsim *dsim) +{ + uint32_t clkctrl = 0, data_lanes_en; + uint64_t byte_clk, esc_prescaler; + + clkctrl |= CLKCTRL_TXREQUESTHSCLK; + + /* using 1.5Gbps PHY */ + clkctrl |= CLKCTRL_DPHY_SEL_1P5G; + + clkctrl |= CLKCTRL_ESCCLKEN; + + clkctrl &= ~CLKCTRL_PLLBYPASS; + + clkctrl |= CLKCTRL_BYTECLKSRC_DPHY_PLL; + + clkctrl |= CLKCTRL_BYTECLKEN; + + data_lanes_en = (0x1 << dsim->lanes) - 1; + clkctrl |= CLKCTRL_SET_LANEESCCLKEN(0x1 | data_lanes_en << 1); + + /* calculate esc prescaler from byte clock: + * EscClk = ByteClk / EscPrescaler; + */ + byte_clk = dsim->bit_clk >> 3; + esc_prescaler = DIV_ROUND_UP_ULL(byte_clk, MAX_ESC_CLK_FREQ); + + clkctrl |= CLKCTRL_SET_ESCPRESCALER(esc_prescaler); + + debug("DSIM clkctrl 0x%x\n", clkctrl); + + dsim_write(dsim, clkctrl, DSIM_CLKCTRL); +} + +static void sec_mipi_dsim_set_standby(struct sec_mipi_dsim *dsim, + bool standby) +{ + uint32_t mdresol = 0; + + mdresol = dsim_read(dsim, DSIM_MDRESOL); + + if (standby) + mdresol |= MDRESOL_MAINSTANDBY; + else + mdresol &= ~MDRESOL_MAINSTANDBY; + + dsim_write(dsim, mdresol, DSIM_MDRESOL); +} + +static void sec_mipi_dsim_disable_clkctrl(struct sec_mipi_dsim *dsim) +{ + uint32_t clkctrl; + + clkctrl = dsim_read(dsim, DSIM_CLKCTRL); + + clkctrl &= ~CLKCTRL_TXREQUESTHSCLK; + + clkctrl &= ~CLKCTRL_ESCCLKEN; + + clkctrl &= ~CLKCTRL_BYTECLKEN; + + dsim_write(dsim, clkctrl, DSIM_CLKCTRL); +} + +static void sec_mipi_dsim_disable_pll(struct sec_mipi_dsim *dsim) +{ + uint32_t pllctrl; + + pllctrl = dsim_read(dsim, DSIM_PLLCTRL); + + pllctrl &= ~PLLCTRL_PLLEN; + + dsim_write(dsim, pllctrl, DSIM_PLLCTRL); +} + +static inline struct sec_mipi_dsim *host_to_dsi(struct mipi_dsi_host *host) +{ + return container_of(host, struct sec_mipi_dsim, dsi_host); +} + +static int sec_mipi_dsim_bridge_clk_set(struct sec_mipi_dsim *dsim_host) +{ + int bpp; + uint64_t pix_clk, bit_clk; + + bpp = mipi_dsi_pixel_format_to_bpp(dsim_host->format); + if (bpp < 0) + return -EINVAL; + + pix_clk = dsim_host->timings.pixelclock.typ; + bit_clk = DIV_ROUND_UP_ULL(pix_clk * bpp, dsim_host->lanes); + +#if 0 + if (bit_clk > dsim_host->max_data_rate) { + printf("request bit clk freq exceeds lane's maximum value\n"); + return -EINVAL; + } +#endif + + dsim_host->pix_clk = DIV_ROUND_UP_ULL(pix_clk, 1000); + dsim_host->bit_clk = DIV_ROUND_UP_ULL(bit_clk, 1000); + + if (dsim_host->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { + /* TODO: add PMS calculate and check + * Only support '1080p@60Hz' for now, + * add other modes support later + */ + dsim_host->pms = 0x4210; + } + + debug("%s: bitclk %llu pixclk %llu\n", __func__, dsim_host->bit_clk, dsim_host->pix_clk); + + return 0; +} + +static int sec_mipi_dsim_bridge_prepare(struct sec_mipi_dsim *dsim_host) +{ + int ret; + + /* At this moment, the dsim bridge's preceding encoder has + * already been enabled. So the dsim can be configed here + */ + + /* config main display mode */ + sec_mipi_dsim_set_main_mode(dsim_host); + + /* config dsim dpi */ + sec_mipi_dsim_config_dpi(dsim_host); + + /* config dsim pll */ + ret = sec_mipi_dsim_config_pll(dsim_host); + if (ret) { + printf("dsim pll config failed: %d\n", ret); + return ret; + } + + /* config dphy timings */ + sec_mipi_dsim_config_dphy(dsim_host); + + sec_mipi_dsim_init_fifo_pointers(dsim_host); + + /* config esc clock, byte clock and etc */ + sec_mipi_dsim_config_clkctrl(dsim_host); + + /* enable data transfer of dsim */ + sec_mipi_dsim_set_standby(dsim_host, true); + + return 0; +} + +static int sec_mipi_dsim_host_attach(struct mipi_dsi_host *host, + struct mipi_dsi_device *device) +{ + struct sec_mipi_dsim *dsi = host_to_dsi(host); + + if (!device->lanes || device->lanes > dsi->max_data_lanes) { + printf("invalid data lanes number\n"); + return -EINVAL; + } + + if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO) || + !((device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) || + (device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))) { + printf("unsupported dsi mode\n"); + return -EINVAL; + } + + if (device->format != MIPI_DSI_FMT_RGB888 && + device->format != MIPI_DSI_FMT_RGB565 && + device->format != MIPI_DSI_FMT_RGB666 && + device->format != MIPI_DSI_FMT_RGB666_PACKED) { + printf("unsupported pixel format: %#x\n", device->format); + return -EINVAL; + } + + dsi->lanes = device->lanes; + dsi->channel = device->channel; + dsi->format = device->format; + dsi->mode_flags = device->mode_flags; + + debug("lanes %u, channel %u, format 0x%x, mode_flags 0x%lx\n", dsi->lanes, + dsi->channel, dsi->format, dsi->mode_flags); + + sec_mipi_dsim_bridge_clk_set(dsi); + sec_mipi_dsim_bridge_prepare(dsi); + + return 0; +} + +static ssize_t sec_mipi_dsi_host_transfer(struct mipi_dsi_host *host, + const struct mipi_dsi_msg *msg) +{ + struct sec_mipi_dsim *dsim = host_to_dsi(host); + int ret, nb_bytes; + bool use_lpm; + struct mipi_dsi_packet packet; + +#ifdef DEBUG + int i = 0; + u8 *p = msg->tx_buf; + + printf("sec_mipi_dsi_host_transfer\n"); + for (i; i < msg->tx_len; i++) { + printf("0x%.2x ", *(u8 *)p); + p++; + } + printf("\n"); +#endif + + ret = mipi_dsi_create_packet(&packet, msg); + if (ret) { + dev_err(dsim->device->dev, "failed to create dsi packet: %d\n", ret); + return ret; + } + + /* config LPM for CMD TX */ + use_lpm = msg->flags & MIPI_DSI_MSG_USE_LPM ? true : false; + sec_mipi_dsim_config_cmd_lpm(dsim, use_lpm); + + if (packet.payload_length) { /* Long Packet case */ + /* write packet payload */ + sec_mipi_dsim_write_pl_to_sfr_fifo(dsim, + packet.payload, + packet.payload_length); + + /* write packet header */ + sec_mipi_dsim_write_ph_to_sfr_fifo(dsim, + packet.header, + use_lpm); + + ret = sec_mipi_dsim_wait_for_pkt_done(dsim, MIPI_FIFO_TIMEOUT); + if (ret) { + dev_err(dsim->device->dev, "wait tx done timeout!\n"); + return -EBUSY; + } + } else { + /* write packet header */ + sec_mipi_dsim_write_ph_to_sfr_fifo(dsim, + packet.header, + use_lpm); + + ret = sec_mipi_dsim_wait_for_hdr_done(dsim, MIPI_FIFO_TIMEOUT); + if (ret) { + dev_err(dsim->device->dev, "wait pkthdr tx done time out\n"); + return -EBUSY; + } + } + + /* read packet payload */ + if (unlikely(msg->rx_buf)) { + ret = sec_mipi_dsim_wait_for_rx_done(dsim, + MIPI_FIFO_TIMEOUT); + if (ret) { + dev_err(dsim->device->dev, "wait rx done time out\n"); + return -EBUSY; + } + + ret = sec_mipi_dsim_read_pl_from_sfr_fifo(dsim, + msg->rx_buf, + msg->rx_len); + if (ret < 0) + return ret; + nb_bytes = msg->rx_len; + } else { + nb_bytes = packet.size; + } + + return nb_bytes; + +} + + +static const struct mipi_dsi_host_ops sec_mipi_dsim_host_ops = { + .attach = sec_mipi_dsim_host_attach, + .transfer = sec_mipi_dsi_host_transfer, +}; + +static int sec_mipi_dsim_init(struct udevice *dev, + struct mipi_dsi_device *device, + struct display_timing *timings, + unsigned int max_data_lanes, + const struct mipi_dsi_phy_ops *phy_ops) +{ + struct sec_mipi_dsim *dsi = dev_get_priv(dev); + + dsi->max_data_lanes = max_data_lanes; + dsi->device = device; + dsi->dsi_host.ops = &sec_mipi_dsim_host_ops; + device->host = &dsi->dsi_host; + + dsi->base = (void *)dev_read_addr(device->dev); + if ((fdt_addr_t)dsi->base == FDT_ADDR_T_NONE) { + dev_err(device->dev, "dsi dt register address error\n"); + return -EINVAL; + } + + dsi->timings = *timings; + + return 0; +} + +static int sec_mipi_dsim_enable(struct udevice *dev) +{ + return 0; +} + +static int sec_mipi_dsim_disable(struct udevice *dev) +{ + uint32_t intsrc; + struct sec_mipi_dsim *dsim_host = dev_get_priv(dev); + + /* disable data transfer of dsim */ + sec_mipi_dsim_set_standby(dsim_host, false); + + /* disable esc clock & byte clock */ + sec_mipi_dsim_disable_clkctrl(dsim_host); + + /* disable dsim pll */ + sec_mipi_dsim_disable_pll(dsim_host); + + /* Clear all intsrc */ + intsrc = dsim_read(dsim_host, DSIM_INTSRC); + dsim_write(dsim_host, intsrc, DSIM_INTSRC); + + return 0; +} + +struct dsi_host_ops sec_mipi_dsim_ops = { + .init = sec_mipi_dsim_init, + .enable = sec_mipi_dsim_enable, + .disable = sec_mipi_dsim_disable, +}; + +static int sec_mipi_dsim_probe(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id sec_mipi_dsim_ids[] = { + { .compatible = "samsung,sec-mipi-dsi" }, + { } +}; + +U_BOOT_DRIVER(sec_mipi_dsim) = { + .name = "sec_mipi_dsim", + .id = UCLASS_DSI_HOST, + .of_match = sec_mipi_dsim_ids, + .probe = sec_mipi_dsim_probe, + .remove = sec_mipi_dsim_disable, + .ops = &sec_mipi_dsim_ops, + .priv_auto = sizeof(struct sec_mipi_dsim), +}; diff --git a/drivers/video/nxp/layerscape/Kconfig b/drivers/video/nxp/layerscape/Kconfig new file mode 100644 index 00000000000..5521ffa8389 --- /dev/null +++ b/drivers/video/nxp/layerscape/Kconfig @@ -0,0 +1,10 @@ + +config VIDEO_LS_HDP_LOAD + bool "NXP Layerscape HDMI/DP firmware loading" + default n + depends on VIDEO + select VIDEO_NXP_HDP + help + Support for HDMI/DP firmware loading for NXP Layerscape processors. The + firmware is copied from system memory to the HDMI/DP IRAM and + DRAM memory. diff --git a/drivers/video/nxp/layerscape/Makefile b/drivers/video/nxp/layerscape/Makefile new file mode 100644 index 00000000000..f95b00117c4 --- /dev/null +++ b/drivers/video/nxp/layerscape/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 NXP + +obj-$(CONFIG_VIDEO_LS_HDP_LOAD) += hdp_load.o diff --git a/drivers/video/nxp/layerscape/hdp_load.c b/drivers/video/nxp/layerscape/hdp_load.c new file mode 100644 index 00000000000..141ff0697c7 --- /dev/null +++ b/drivers/video/nxp/layerscape/hdp_load.c @@ -0,0 +1,59 @@ +/* + * Copyright 2017-2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include "API_General.h" + +DECLARE_GLOBAL_DATA_PTR; + +int do_hdp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + if (argc < 2) + return 0; + + if (strncmp(argv[1], "load", 4) == 0) { + unsigned long address = 0; + unsigned long offset = 0x2000; + const int iram_size = 0x10000; + const int dram_size = 0x8000; + + if (argc > 2) { + address = simple_strtoul(argv[2], NULL, 0); + if (argc > 3) + offset = simple_strtoul(argv[3], NULL, 0); + } else { + printf("Missing address\n"); + } + + printf("Loading hdp firmware from 0x%016lx offset 0x%016lx\n", + address, offset); + cdn_api_loadfirmware((unsigned char *)(address + offset), + iram_size, + (unsigned char *)(address + offset + + iram_size), + dram_size); + printf("Loading hdp firmware Complete\n"); + /* do not turn off hdmi power or firmware load will be lost */ + } else { + printf("test error argc %d\n", argc); + } + + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + hdp, CONFIG_SYS_MAXARGS, 1, do_hdp, + "load hdmi firmware ", + "[] ...\n" + "hdpload [address] []\n" + " address - address where the binary image starts\n" + " - IRAM offset in the binary image (8192 default)\n" + ); diff --git a/drivers/video/raydium-rm67191.c b/drivers/video/raydium-rm67191.c new file mode 100644 index 00000000000..546cb514f10 --- /dev/null +++ b/drivers/video/raydium-rm67191.c @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define CMD_TABLE_LEN 2 +typedef u8 cmd_set_table[CMD_TABLE_LEN]; + +/* Write Manufacture Command Set Control */ +#define WRMAUCCTR 0xFE + +struct rm67191_panel_priv { + struct gpio_desc reset; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; +}; + +/* Manufacturer Command Set pages (CMD2) */ +static const cmd_set_table manufacturer_cmd_set[] = { + {0xFE, 0x0B}, + {0x28, 0x40}, + {0x29, 0x4F}, + {0xFE, 0x0E}, + {0x4B, 0x00}, + {0x4C, 0x0F}, + {0x4D, 0x20}, + {0x4E, 0x40}, + {0x4F, 0x60}, + {0x50, 0xA0}, + {0x51, 0xC0}, + {0x52, 0xE0}, + {0x53, 0xFF}, + {0xFE, 0x0D}, + {0x18, 0x08}, + {0x42, 0x00}, + {0x08, 0x41}, + {0x46, 0x02}, + {0x72, 0x09}, + {0xFE, 0x0A}, + {0x24, 0x17}, + {0x04, 0x07}, + {0x1A, 0x0C}, + {0x0F, 0x44}, + {0xFE, 0x04}, + {0x00, 0x0C}, + {0x05, 0x08}, + {0x06, 0x08}, + {0x08, 0x08}, + {0x09, 0x08}, + {0x0A, 0xE6}, + {0x0B, 0x8C}, + {0x1A, 0x12}, + {0x1E, 0xE0}, + {0x29, 0x93}, + {0x2A, 0x93}, + {0x2F, 0x02}, + {0x31, 0x02}, + {0x33, 0x05}, + {0x37, 0x2D}, + {0x38, 0x2D}, + {0x3A, 0x1E}, + {0x3B, 0x1E}, + {0x3D, 0x27}, + {0x3F, 0x80}, + {0x40, 0x40}, + {0x41, 0xE0}, + {0x4F, 0x2F}, + {0x50, 0x1E}, + {0xFE, 0x06}, + {0x00, 0xCC}, + {0x05, 0x05}, + {0x07, 0xA2}, + {0x08, 0xCC}, + {0x0D, 0x03}, + {0x0F, 0xA2}, + {0x32, 0xCC}, + {0x37, 0x05}, + {0x39, 0x83}, + {0x3A, 0xCC}, + {0x41, 0x04}, + {0x43, 0x83}, + {0x44, 0xCC}, + {0x49, 0x05}, + {0x4B, 0xA2}, + {0x4C, 0xCC}, + {0x51, 0x03}, + {0x53, 0xA2}, + {0x75, 0xCC}, + {0x7A, 0x03}, + {0x7C, 0x83}, + {0x7D, 0xCC}, + {0x82, 0x02}, + {0x84, 0x83}, + {0x85, 0xEC}, + {0x86, 0x0F}, + {0x87, 0xFF}, + {0x88, 0x00}, + {0x8A, 0x02}, + {0x8C, 0xA2}, + {0x8D, 0xEA}, + {0x8E, 0x01}, + {0x8F, 0xE8}, + {0xFE, 0x06}, + {0x90, 0x0A}, + {0x92, 0x06}, + {0x93, 0xA0}, + {0x94, 0xA8}, + {0x95, 0xEC}, + {0x96, 0x0F}, + {0x97, 0xFF}, + {0x98, 0x00}, + {0x9A, 0x02}, + {0x9C, 0xA2}, + {0xAC, 0x04}, + {0xFE, 0x06}, + {0xB1, 0x12}, + {0xB2, 0x17}, + {0xB3, 0x17}, + {0xB4, 0x17}, + {0xB5, 0x17}, + {0xB6, 0x11}, + {0xB7, 0x08}, + {0xB8, 0x09}, + {0xB9, 0x06}, + {0xBA, 0x07}, + {0xBB, 0x17}, + {0xBC, 0x17}, + {0xBD, 0x17}, + {0xBE, 0x17}, + {0xBF, 0x17}, + {0xC0, 0x17}, + {0xC1, 0x17}, + {0xC2, 0x17}, + {0xC3, 0x17}, + {0xC4, 0x0F}, + {0xC5, 0x0E}, + {0xC6, 0x00}, + {0xC7, 0x01}, + {0xC8, 0x10}, + {0xFE, 0x06}, + {0x95, 0xEC}, + {0x8D, 0xEE}, + {0x44, 0xEC}, + {0x4C, 0xEC}, + {0x32, 0xEC}, + {0x3A, 0xEC}, + {0x7D, 0xEC}, + {0x75, 0xEC}, + {0x00, 0xEC}, + {0x08, 0xEC}, + {0x85, 0xEC}, + {0xA6, 0x21}, + {0xA7, 0x05}, + {0xA9, 0x06}, + {0x82, 0x06}, + {0x41, 0x06}, + {0x7A, 0x07}, + {0x37, 0x07}, + {0x05, 0x06}, + {0x49, 0x06}, + {0x0D, 0x04}, + {0x51, 0x04}, +}; + +static const struct display_timing default_timing = { + .pixelclock.typ = 132000000, + .hactive.typ = 1080, + .hfront_porch.typ = 20, + .hback_porch.typ = 34, + .hsync_len.typ = 2, + .vactive.typ = 1920, + .vfront_porch.typ = 10, + .vback_porch.typ = 4, + .vsync_len.typ = 2, + .flags = DISPLAY_FLAGS_HSYNC_LOW | + DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_LOW | + DISPLAY_FLAGS_PIXDATA_NEGEDGE, +}; + + +static u8 color_format_from_dsi_format(enum mipi_dsi_pixel_format format) +{ + switch (format) { + case MIPI_DSI_FMT_RGB565: + return 0x55; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + return 0x66; + case MIPI_DSI_FMT_RGB888: + return 0x77; + default: + return 0x77; /* for backward compatibility */ + } +}; + +static int rad_panel_push_cmd_list(struct mipi_dsi_device *device) +{ + size_t i; + const u8 *cmd; + size_t count = sizeof(manufacturer_cmd_set) / CMD_TABLE_LEN; + int ret = 0; + + for (i = 0; i < count ; i++) { + cmd = manufacturer_cmd_set[i]; + ret = mipi_dsi_generic_write(device, cmd, CMD_TABLE_LEN); + if (ret < 0) + return ret; + } + + return ret; +}; + +static int rm67191_enable(struct udevice *dev) +{ + struct rm67191_panel_priv *priv = dev_get_priv(dev); + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *dsi = plat->device; + u8 color_format = color_format_from_dsi_format(priv->format); + u16 brightness; + int ret; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + ret = rad_panel_push_cmd_list(dsi); + if (ret < 0) { + printf("Failed to send MCS (%d)\n", ret); + return -EIO; + } + + /* Select User Command Set table (CMD1) */ + ret = mipi_dsi_generic_write(dsi, (u8[]){ WRMAUCCTR, 0x00 }, 2); + if (ret < 0) + return -EIO; + + /* Software reset */ + ret = mipi_dsi_dcs_soft_reset(dsi); + if (ret < 0) { + printf("Failed to do Software Reset (%d)\n", ret); + return -EIO; + } + + /* Wait 80ms for panel out of reset */ + mdelay(80); + + /* Set DSI mode */ + ret = mipi_dsi_generic_write(dsi, (u8[]){ 0xC2, 0x0B }, 2); + if (ret < 0) { + printf("Failed to set DSI mode (%d)\n", ret); + return -EIO; + } + + /* Set tear ON */ + ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + if (ret < 0) { + printf("Failed to set tear ON (%d)\n", ret); + return -EIO; + } + + /* Set tear scanline */ + ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x380); + if (ret < 0) { + printf("Failed to set tear scanline (%d)\n", ret); + return -EIO; + } + + /* Set pixel format */ + ret = mipi_dsi_dcs_set_pixel_format(dsi, color_format); + if (ret < 0) { + printf("Failed to set pixel format (%d)\n", ret); + return -EIO; + } + + + /* Set display brightness */ + brightness = 255; /* Max brightness */ + ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, &brightness, 2); + if (ret < 0) { + printf("Failed to set display brightness (%d)\n", + ret); + return -EIO; + } + + /* Exit sleep mode */ + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret < 0) { + printf("Failed to exit sleep mode (%d)\n", ret); + return -EIO; + } + + mdelay(5); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret < 0) { + printf("Failed to set display ON (%d)\n", ret); + return -EIO; + } + + return 0; +} + +static int rm67191_panel_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + ret = mipi_dsi_attach(device); + if (ret < 0) + return ret; + + return rm67191_enable(dev); +} + +static int rm67191_panel_get_display_timing(struct udevice *dev, + struct display_timing *timings) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + struct rm67191_panel_priv *priv = dev_get_priv(dev); + + memcpy(timings, &default_timing, sizeof(*timings)); + + /* fill characteristics of DSI data link */ + if (device) { + device->lanes = priv->lanes; + device->format = priv->format; + device->mode_flags = priv->mode_flags; + } + + return 0; +} + +static int rm67191_panel_probe(struct udevice *dev) +{ + struct rm67191_panel_priv *priv = dev_get_priv(dev); + int ret; + u32 video_mode; + + priv->format = MIPI_DSI_FMT_RGB888; + priv->mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO; + + ret = dev_read_u32(dev, "video-mode", &video_mode); + if (!ret) { + switch (video_mode) { + case 0: + /* burst mode */ + priv->mode_flags |= MIPI_DSI_MODE_VIDEO_BURST; + break; + case 1: + /* non-burst mode with sync event */ + break; + case 2: + /* non-burst mode with sync pulse */ + priv->mode_flags |= MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + break; + default: + dev_warn(dev, "invalid video mode %d\n", video_mode); + break; + } + } + + ret = dev_read_u32(dev, "dsi-lanes", &priv->lanes); + if (ret) { + printf("Failed to get dsi-lanes property (%d)\n", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset, + GPIOD_IS_OUT); + if (ret) { + printf("Warning: cannot get reset GPIO\n"); + if (ret != -ENOENT) + return ret; + } + + /* reset panel */ + ret = dm_gpio_set_value(&priv->reset, true); + if (ret) + printf("reset gpio fails to set true\n"); + mdelay(100); + ret = dm_gpio_set_value(&priv->reset, false); + if (ret) + printf("reset gpio fails to set true\n"); + mdelay(100); + + return 0; +} + +static int rm67191_panel_disable(struct udevice *dev) +{ + struct rm67191_panel_priv *priv = dev_get_priv(dev); + + dm_gpio_set_value(&priv->reset, true); + + return 0; +} + +static const struct panel_ops rm67191_panel_ops = { + .enable_backlight = rm67191_panel_enable_backlight, + .get_display_timing = rm67191_panel_get_display_timing, +}; + +static const struct udevice_id rm67191_panel_ids[] = { + { .compatible = "raydium,rm67191" }, + { } +}; + +U_BOOT_DRIVER(rm67191_panel) = { + .name = "rm67191_panel", + .id = UCLASS_PANEL, + .of_match = rm67191_panel_ids, + .ops = &rm67191_panel_ops, + .probe = rm67191_panel_probe, + .remove = rm67191_panel_disable, + .plat_auto = sizeof(struct mipi_dsi_panel_plat), + .priv_auto = sizeof(struct rm67191_panel_priv), +}; diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c index 373668d28bf..4d58cd856cd 100644 --- a/drivers/video/raydium-rm68200.c +++ b/drivers/video/raydium-rm68200.c @@ -256,8 +256,18 @@ static int rm68200_panel_enable_backlight(struct udevice *dev) static int rm68200_panel_get_display_timing(struct udevice *dev, struct display_timing *timings) { + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + memcpy(timings, &default_timing, sizeof(*timings)); + /* fill characteristics of DSI data link */ + if (device) { + device->lanes = plat->lanes; + device->format = plat->format; + device->mode_flags = plat->mode_flags; + } + return 0; } @@ -321,6 +331,15 @@ static int rm68200_panel_probe(struct udevice *dev) return 0; } +static int rm68200_panel_disable(struct udevice *dev) +{ + struct rm68200_panel_priv *priv = dev_get_priv(dev); + + dm_gpio_set_value(&priv->reset, true); + + return 0; +} + static const struct panel_ops rm68200_panel_ops = { .enable_backlight = rm68200_panel_enable_backlight, .get_display_timing = rm68200_panel_get_display_timing, @@ -338,6 +357,7 @@ U_BOOT_DRIVER(rm68200_panel) = { .ops = &rm68200_panel_ops, .of_to_plat = rm68200_panel_of_to_plat, .probe = rm68200_panel_probe, + .remove = rm68200_panel_disable, .plat_auto = sizeof(struct mipi_dsi_panel_plat), .priv_auto = sizeof(struct rm68200_panel_priv), }; diff --git a/drivers/video/startek-ili9881c.c b/drivers/video/startek-ili9881c.c new file mode 100644 index 00000000000..e9777536f76 --- /dev/null +++ b/drivers/video/startek-ili9881c.c @@ -0,0 +1,511 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * Copyright 2021 CompuLab LTD. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LCD_XSIZE_TFT 720 +#define LCD_YSIZE_TFT 1280 +#define PCLOCK 62000 +#define LCD_VBPD 20 +#define LCD_VFPD 10 +#define LCD_VSPW 10 +#define LCD_HBPD 30 +#define LCD_HFPD 10 +#define LCD_HSPW 20 + +enum ili9881c_op { + ILI9881C_SWITCH_PAGE, + ILI9881C_COMMAND, +}; + +struct ili9881c_instr { + enum ili9881c_op op; + + union arg { + struct cmd { + u8 cmd; + u8 data; + } cmd; + u8 page; + } arg; +}; + +#define ILI9881C_SWITCH_PAGE_INSTR(_page) \ + { \ + .op = ILI9881C_SWITCH_PAGE, \ + .arg = { \ + .page = (_page), \ + }, \ + } + +#define ILI9881C_COMMAND_INSTR(_cmd, _data) \ + { \ + .op = ILI9881C_COMMAND, \ + .arg = { \ + .cmd = { \ + .cmd = (_cmd), \ + .data = (_data), \ + }, \ + }, \ + } + +static const struct ili9881c_instr ili9881c_init[] = { + ILI9881C_SWITCH_PAGE_INSTR(3), + ILI9881C_COMMAND_INSTR(0x01, 0x00), + ILI9881C_COMMAND_INSTR(0x02, 0x00), + ILI9881C_COMMAND_INSTR(0x03, 0x72), + ILI9881C_COMMAND_INSTR(0x04, 0x00), + ILI9881C_COMMAND_INSTR(0x05, 0x00), + ILI9881C_COMMAND_INSTR(0x06, 0x09), + ILI9881C_COMMAND_INSTR(0x07, 0x00), + ILI9881C_COMMAND_INSTR(0x08, 0x00), + ILI9881C_COMMAND_INSTR(0x09, 0x01), + ILI9881C_COMMAND_INSTR(0x0a, 0x00), + ILI9881C_COMMAND_INSTR(0x0b, 0x00), + ILI9881C_COMMAND_INSTR(0x0c, 0x01), + ILI9881C_COMMAND_INSTR(0x0d, 0x00), + ILI9881C_COMMAND_INSTR(0x0e, 0x00), + ILI9881C_COMMAND_INSTR(0x0f, 0x00), + ILI9881C_COMMAND_INSTR(0x10, 0x00), + ILI9881C_COMMAND_INSTR(0x11, 0x00), + ILI9881C_COMMAND_INSTR(0x12, 0x00), + ILI9881C_COMMAND_INSTR(0x13, 0x00), + ILI9881C_COMMAND_INSTR(0x14, 0x00), + ILI9881C_COMMAND_INSTR(0x15, 0x00), + ILI9881C_COMMAND_INSTR(0x16, 0x00), + ILI9881C_COMMAND_INSTR(0x17, 0x00), + ILI9881C_COMMAND_INSTR(0x18, 0x00), + ILI9881C_COMMAND_INSTR(0x19, 0x00), + ILI9881C_COMMAND_INSTR(0x1a, 0x00), + ILI9881C_COMMAND_INSTR(0x1b, 0x00), + ILI9881C_COMMAND_INSTR(0x1c, 0x00), + ILI9881C_COMMAND_INSTR(0x1d, 0x00), + ILI9881C_COMMAND_INSTR(0x1e, 0x40), + ILI9881C_COMMAND_INSTR(0x1f, 0x80), + ILI9881C_COMMAND_INSTR(0x20, 0x05), + ILI9881C_COMMAND_INSTR(0x20, 0x05), + ILI9881C_COMMAND_INSTR(0x21, 0x02), + ILI9881C_COMMAND_INSTR(0x22, 0x00), + ILI9881C_COMMAND_INSTR(0x23, 0x00), + ILI9881C_COMMAND_INSTR(0x24, 0x00), + ILI9881C_COMMAND_INSTR(0x25, 0x00), + ILI9881C_COMMAND_INSTR(0x26, 0x00), + ILI9881C_COMMAND_INSTR(0x27, 0x00), + ILI9881C_COMMAND_INSTR(0x28, 0x33), + ILI9881C_COMMAND_INSTR(0x29, 0x02), + ILI9881C_COMMAND_INSTR(0x2a, 0x00), + ILI9881C_COMMAND_INSTR(0x2b, 0x00), + ILI9881C_COMMAND_INSTR(0x2c, 0x00), + ILI9881C_COMMAND_INSTR(0x2d, 0x00), + ILI9881C_COMMAND_INSTR(0x2e, 0x00), + ILI9881C_COMMAND_INSTR(0x2f, 0x00), + ILI9881C_COMMAND_INSTR(0x30, 0x00), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x32, 0x00), + ILI9881C_COMMAND_INSTR(0x32, 0x00), + ILI9881C_COMMAND_INSTR(0x33, 0x00), + ILI9881C_COMMAND_INSTR(0x34, 0x04), + ILI9881C_COMMAND_INSTR(0x35, 0x00), + ILI9881C_COMMAND_INSTR(0x36, 0x00), + ILI9881C_COMMAND_INSTR(0x37, 0x00), + ILI9881C_COMMAND_INSTR(0x38, 0x3C), + ILI9881C_COMMAND_INSTR(0x39, 0x00), + ILI9881C_COMMAND_INSTR(0x3a, 0x40), + ILI9881C_COMMAND_INSTR(0x3b, 0x40), + ILI9881C_COMMAND_INSTR(0x3c, 0x00), + ILI9881C_COMMAND_INSTR(0x3d, 0x00), + ILI9881C_COMMAND_INSTR(0x3e, 0x00), + ILI9881C_COMMAND_INSTR(0x3f, 0x00), + ILI9881C_COMMAND_INSTR(0x40, 0x00), + ILI9881C_COMMAND_INSTR(0x41, 0x00), + ILI9881C_COMMAND_INSTR(0x42, 0x00), + ILI9881C_COMMAND_INSTR(0x43, 0x00), + ILI9881C_COMMAND_INSTR(0x44, 0x00), + ILI9881C_COMMAND_INSTR(0x50, 0x01), + ILI9881C_COMMAND_INSTR(0x51, 0x23), + ILI9881C_COMMAND_INSTR(0x52, 0x45), + ILI9881C_COMMAND_INSTR(0x53, 0x67), + ILI9881C_COMMAND_INSTR(0x54, 0x89), + ILI9881C_COMMAND_INSTR(0x55, 0xab), + ILI9881C_COMMAND_INSTR(0x56, 0x01), + ILI9881C_COMMAND_INSTR(0x57, 0x23), + ILI9881C_COMMAND_INSTR(0x58, 0x45), + ILI9881C_COMMAND_INSTR(0x59, 0x67), + ILI9881C_COMMAND_INSTR(0x5a, 0x89), + ILI9881C_COMMAND_INSTR(0x5b, 0xab), + ILI9881C_COMMAND_INSTR(0x5c, 0xcd), + ILI9881C_COMMAND_INSTR(0x5d, 0xef), + ILI9881C_COMMAND_INSTR(0x5e, 0x11), + ILI9881C_COMMAND_INSTR(0x5f, 0x01), + ILI9881C_COMMAND_INSTR(0x60, 0x00), + ILI9881C_COMMAND_INSTR(0x61, 0x15), + ILI9881C_COMMAND_INSTR(0x62, 0x14), + ILI9881C_COMMAND_INSTR(0x63, 0x0E), + ILI9881C_COMMAND_INSTR(0x64, 0x0F), + ILI9881C_COMMAND_INSTR(0x65, 0x0C), + ILI9881C_COMMAND_INSTR(0x66, 0x0D), + ILI9881C_COMMAND_INSTR(0x67, 0x06), + ILI9881C_COMMAND_INSTR(0x68, 0x02), + ILI9881C_COMMAND_INSTR(0x69, 0x07), + ILI9881C_COMMAND_INSTR(0x6a, 0x02), + ILI9881C_COMMAND_INSTR(0x6b, 0x02), + ILI9881C_COMMAND_INSTR(0x6c, 0x02), + ILI9881C_COMMAND_INSTR(0x6d, 0x02), + ILI9881C_COMMAND_INSTR(0x6e, 0x02), + ILI9881C_COMMAND_INSTR(0x6f, 0x02), + ILI9881C_COMMAND_INSTR(0x70, 0x02), + ILI9881C_COMMAND_INSTR(0x71, 0x02), + ILI9881C_COMMAND_INSTR(0x72, 0x02), + ILI9881C_COMMAND_INSTR(0x73, 0x02), + ILI9881C_COMMAND_INSTR(0x74, 0x02), + ILI9881C_COMMAND_INSTR(0x75, 0x01), + ILI9881C_COMMAND_INSTR(0x76, 0x00), + ILI9881C_COMMAND_INSTR(0x77, 0x14), + ILI9881C_COMMAND_INSTR(0x78, 0x15), + ILI9881C_COMMAND_INSTR(0x79, 0x0E), + ILI9881C_COMMAND_INSTR(0x7a, 0x0F), + ILI9881C_COMMAND_INSTR(0x7b, 0x0C), + ILI9881C_COMMAND_INSTR(0x7c, 0x0D), + ILI9881C_COMMAND_INSTR(0x7d, 0x06), + ILI9881C_COMMAND_INSTR(0x7e, 0x02), + ILI9881C_COMMAND_INSTR(0x7f, 0x07), + ILI9881C_COMMAND_INSTR(0x80, 0x02), + ILI9881C_COMMAND_INSTR(0x81, 0x02), + ILI9881C_COMMAND_INSTR(0x83, 0x02), + ILI9881C_COMMAND_INSTR(0x84, 0x02), + ILI9881C_COMMAND_INSTR(0x85, 0x02), + ILI9881C_COMMAND_INSTR(0x86, 0x02), + ILI9881C_COMMAND_INSTR(0x87, 0x02), + ILI9881C_COMMAND_INSTR(0x88, 0x02), + ILI9881C_COMMAND_INSTR(0x89, 0x02), + ILI9881C_COMMAND_INSTR(0x8A, 0x02), + ILI9881C_SWITCH_PAGE_INSTR(0x4), + ILI9881C_COMMAND_INSTR(0x6C, 0x15), + ILI9881C_COMMAND_INSTR(0x6E, 0x2A), + ILI9881C_COMMAND_INSTR(0x6F, 0x33), + ILI9881C_COMMAND_INSTR(0x3A, 0x94), + ILI9881C_COMMAND_INSTR(0x8D, 0x15), + ILI9881C_COMMAND_INSTR(0x87, 0xBA), + ILI9881C_COMMAND_INSTR(0x26, 0x76), + ILI9881C_COMMAND_INSTR(0xB2, 0xD1), + ILI9881C_COMMAND_INSTR(0xB5, 0x06), + ILI9881C_SWITCH_PAGE_INSTR(0x1), + ILI9881C_COMMAND_INSTR(0x22, 0x0A), + ILI9881C_COMMAND_INSTR(0x31, 0x00), + ILI9881C_COMMAND_INSTR(0x53, 0x90), + ILI9881C_COMMAND_INSTR(0x55, 0xA2), + ILI9881C_COMMAND_INSTR(0x50, 0xB7), + ILI9881C_COMMAND_INSTR(0x51, 0xB7), + ILI9881C_COMMAND_INSTR(0x60, 0x22), + ILI9881C_COMMAND_INSTR(0x61, 0x00), + ILI9881C_COMMAND_INSTR(0x62, 0x19), + ILI9881C_COMMAND_INSTR(0x63, 0x10), + ILI9881C_COMMAND_INSTR(0xA0, 0x08), + ILI9881C_COMMAND_INSTR(0xA1, 0x1A), + ILI9881C_COMMAND_INSTR(0xA2, 0x27), + ILI9881C_COMMAND_INSTR(0xA3, 0x15), + ILI9881C_COMMAND_INSTR(0xA4, 0x17), + ILI9881C_COMMAND_INSTR(0xA5, 0x2A), + ILI9881C_COMMAND_INSTR(0xA6, 0x1E), + ILI9881C_COMMAND_INSTR(0xA7, 0x1F), + ILI9881C_COMMAND_INSTR(0xA8, 0x8B), + ILI9881C_COMMAND_INSTR(0xA9, 0x1B), + ILI9881C_COMMAND_INSTR(0xAA, 0x27), + ILI9881C_COMMAND_INSTR(0xAB, 0x78), + ILI9881C_COMMAND_INSTR(0xAC, 0x18), + ILI9881C_COMMAND_INSTR(0xAD, 0x18), + ILI9881C_COMMAND_INSTR(0xAE, 0x4C), + ILI9881C_COMMAND_INSTR(0xAF, 0x21), + ILI9881C_COMMAND_INSTR(0xB0, 0x27), + ILI9881C_COMMAND_INSTR(0xB1, 0x54), + ILI9881C_COMMAND_INSTR(0xB2, 0x67), + ILI9881C_COMMAND_INSTR(0xB3, 0x39), + ILI9881C_COMMAND_INSTR(0xC0, 0x08), + ILI9881C_COMMAND_INSTR(0xC1, 0x1A), + ILI9881C_COMMAND_INSTR(0xC2, 0x27), + ILI9881C_COMMAND_INSTR(0xC3, 0x15), + ILI9881C_COMMAND_INSTR(0xC4, 0x17), + ILI9881C_COMMAND_INSTR(0xC5, 0x2A), + ILI9881C_COMMAND_INSTR(0xC6, 0x1E), + ILI9881C_COMMAND_INSTR(0xC7, 0x1F), + ILI9881C_COMMAND_INSTR(0xC8, 0x8B), + ILI9881C_COMMAND_INSTR(0xC9, 0x1B), + ILI9881C_COMMAND_INSTR(0xCA, 0x27), + ILI9881C_COMMAND_INSTR(0xCB, 0x78), + ILI9881C_COMMAND_INSTR(0xCC, 0x18), + ILI9881C_COMMAND_INSTR(0xCD, 0x18), + ILI9881C_COMMAND_INSTR(0xCE, 0x4C), + ILI9881C_COMMAND_INSTR(0xCF, 0x21), + ILI9881C_COMMAND_INSTR(0xD0, 0x27), + ILI9881C_COMMAND_INSTR(0xD1, 0x54), + ILI9881C_COMMAND_INSTR(0xD2, 0x67), + ILI9881C_COMMAND_INSTR(0xD3, 0x39), + ILI9881C_SWITCH_PAGE_INSTR(0), + ILI9881C_COMMAND_INSTR(0x35, 0x00), + ILI9881C_COMMAND_INSTR(0x3A, 0x7), +}; + +struct ili9881c_panel_priv { + struct gpio_desc reset; + unsigned int lanes; + enum mipi_dsi_pixel_format format; + unsigned long mode_flags; +}; + +static const struct display_timing default_timing = { + .pixelclock.typ = ( 61776000 << 1 ), + .hactive.typ = LCD_XSIZE_TFT, + .hfront_porch.typ = LCD_HFPD, + .hback_porch.typ = LCD_HBPD, + .hsync_len.typ = LCD_HSPW, + .vactive.typ = LCD_YSIZE_TFT, + .vfront_porch.typ = LCD_VFPD, + .vback_porch.typ = LCD_VBPD, + .vsync_len.typ = LCD_VSPW, + .flags = DISPLAY_FLAGS_HSYNC_LOW | + DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_LOW, +}; + +static u8 color_format_from_dsi_format(enum mipi_dsi_pixel_format format) +{ + switch (format) { + case MIPI_DSI_FMT_RGB565: + return 0x55; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + return 0x66; + case MIPI_DSI_FMT_RGB888: + return 0x77; + default: + return 0x77; /* for backward compatibility */ + } +}; + +static int ili9881c_switch_page(struct mipi_dsi_device *dsi, u8 page) +{ + u8 buf[4] = { 0xff, 0x98, 0x81, page }; + int ret; + + ret = mipi_dsi_dcs_write_buffer(dsi, buf, sizeof(buf)); + if (ret < 0) + return ret; + + return 0; +} + +static int ili9881c_send_cmd_data(struct mipi_dsi_device *dsi, u8 cmd, u8 data) +{ + u8 buf[2] = { cmd, data }; + int ret; + + ret = mipi_dsi_dcs_write_buffer(dsi, buf, sizeof(buf)); + if (ret < 0) + return ret; + + return 0; +} + +static int ili9881c_enable(struct udevice *dev) +{ + struct ili9881c_panel_priv *priv = dev_get_priv(dev); + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *dsi = plat->device; + u8 color_format = color_format_from_dsi_format(priv->format); + int ret; + unsigned int i; + + dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + for (i = 0; i < ARRAY_SIZE(ili9881c_init); i++) { + const struct ili9881c_instr *instr = &ili9881c_init[i]; + + if (instr->op == ILI9881C_SWITCH_PAGE) + ret = ili9881c_switch_page(dsi, instr->arg.page); + else if (instr->op == ILI9881C_COMMAND) + ret = ili9881c_send_cmd_data(dsi, instr->arg.cmd.cmd, + instr->arg.cmd.data); + + if (ret) { + dev_warn(dev, "%s %d Failed command # = [ 0x%x ]; ret = [ %d ]\n",__func__,__LINE__,i,ret); + return ret; + } + } + + /* The default value is 4-lane mode + * Issue if 2-lane required + */ + if (dsi->lanes == 2) { + ret = ili9881c_switch_page(dsi, 1); + if (ret) + return ret; + + ret = ili9881c_send_cmd_data(dsi, 0xB7, 0x03); + if (ret) + return ret; + + ret = ili9881c_switch_page(dsi, 0); + if (ret) + return ret; + } + + ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); + if (ret) + return ret; + + /* Set tear scanline */ + ret = mipi_dsi_dcs_set_tear_scanline(dsi, 0x380); + if (ret < 0) { + dev_warn(dev, "Failed to set tear scanline (%d)\n", ret); + return ret; + } + + /* Set pixel format */ + ret = mipi_dsi_dcs_set_pixel_format(dsi, color_format); + if (ret < 0) { + dev_warn(dev, "Failed to set pixel format (%d)\n", ret); + return ret; + } + + ret = mipi_dsi_dcs_set_display_brightness(dsi, 0xffff); + if (ret < 0) { + dev_warn(dev, "Failed to set display brightness (%d)\n", ret); + return ret; + } + + ret = mipi_dsi_dcs_exit_sleep_mode(dsi); + if (ret) { + dev_warn(dev, "Failed to exit sleep mode (%d)\n", ret); + return ret; + } + mdelay(120); + + ret = mipi_dsi_dcs_set_display_on(dsi); + if (ret) { + dev_warn(dev, "Failed to set display on (%d)\n", ret); + return ret; + } + mdelay(20); + + dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + dev_dbg(dev,"Set %d-lane mode ; Color %d\n",dsi->lanes,color_format); + + return 0; +} + +static int ili9881c_panel_enable_backlight(struct udevice *dev) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + int ret; + + ret = mipi_dsi_attach(device); + if (ret < 0) + return ret; + + ret = ili9881c_enable(dev); + if (ret) { + video_link_shut_down(); + return ret; + } +} + +static int ili9881c_panel_get_display_timing(struct udevice *dev, + struct display_timing *timings) +{ + struct mipi_dsi_panel_plat *plat = dev_get_plat(dev); + struct mipi_dsi_device *device = plat->device; + struct ili9881c_panel_priv *priv = dev_get_priv(dev); + + memcpy(timings, &default_timing, sizeof(*timings)); + + /* fill characteristics of DSI data link */ + if (device) { + device->lanes = priv->lanes; + device->format = priv->format; + device->mode_flags = priv->mode_flags; + } + + return 0; +} + +static int ili9881c_panel_probe(struct udevice *dev) +{ + struct ili9881c_panel_priv *priv = dev_get_priv(dev); + int ret; + + priv->format = MIPI_DSI_FMT_RGB888; + priv->mode_flags = MIPI_DSI_MODE_VIDEO_SYNC_PULSE; + priv->mode_flags |= MIPI_DSI_MODE_VIDEO; + + ret = dev_read_u32(dev, "dsi-lanes", &priv->lanes); + if (ret) { + dev_warn(dev, "Failed to get dsi-lanes property (%d)\n", ret); + return ret; + } + + ret = gpio_request_by_name(dev, "reset-gpio", 0, &priv->reset, + GPIOD_IS_OUT); + if (ret) { + dev_warn(dev, "Warning: cannot get reset GPIO\n"); + if (ret != -ENOENT) + return ret; + } + + /* reset panel */ + ret = dm_gpio_set_value(&priv->reset, true); + if (ret) + dev_warn(dev, "reset gpio fails to set true\n"); + + mdelay(100); + + ret = dm_gpio_set_value(&priv->reset, false); + if (ret) + dev_warn(dev, "reset gpio fails to set true\n"); + + mdelay(100); + + return 0; +} + +static int ili9881c_panel_disable(struct udevice *dev) +{ + struct ili9881c_panel_priv *priv = dev_get_priv(dev); + + dm_gpio_set_value(&priv->reset, true); + + return 0; +} + +static const struct panel_ops ili9881c_panel_ops = { + .enable_backlight = ili9881c_panel_enable_backlight, + .get_display_timing = ili9881c_panel_get_display_timing, +}; + +static const struct udevice_id ili9881c_panel_ids[] = { + { .compatible = "startek,ili9881c" }, + { } +}; + +U_BOOT_DRIVER(ili9881c_panel) = { + .name = "ili9881c_panel", + .id = UCLASS_PANEL, + .of_match = ili9881c_panel_ids, + .ops = &ili9881c_panel_ops, + .probe = ili9881c_panel_probe, + .remove = ili9881c_panel_disable, + .priv_auto = sizeof(struct ili9881c_panel_priv), +}; diff --git a/drivers/video/video_link.c b/drivers/video/video_link.c new file mode 100644 index 00000000000..72ef1a0f64f --- /dev/null +++ b/drivers/video/video_link.c @@ -0,0 +1,534 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +struct of_endpoint { + unsigned int port; + unsigned int id; + ofnode local_node; +}; + +#define MAX_LINKS 3 +#define MAX_LINK_DEVICES 5 + +struct video_link { + struct udevice *link_devs[MAX_LINK_DEVICES]; + int dev_num; +}; + +struct video_link video_links[MAX_LINKS]; +struct video_link temp_stack; +ulong video_links_num = 0; +ulong curr_video_link = 0; +bool video_off = false; + +ofnode ofnode_get_child_by_name(ofnode parent, const char *name) +{ + ofnode child; + const char *child_name; + + for (child = ofnode_first_subnode(parent); + ofnode_valid(child); + child = ofnode_next_subnode(child)) { + + child_name = ofnode_get_name(child); + + if (!strncmp(child_name, name, strlen(name))) { + break; + } + + } + return child; +} + +ofnode ofnode_graph_get_next_endpoint(ofnode parent, + ofnode prev) +{ + ofnode endpoint; + ofnode port; + const char *name; + + + if (!ofnode_valid(prev)) { + ofnode node; + + node = ofnode_find_subnode(parent, "ports"); + if (ofnode_valid(node)) + parent = node; + + port = ofnode_get_child_by_name(parent, "port"); + if (!ofnode_valid(port)) { + debug("no port node found in 0x%lx\n", parent.of_offset); + return ofnode_null(); + } + + endpoint = ofnode_first_subnode(port); + if (ofnode_valid(endpoint)) { + debug("get next endpoint %s\n", ofnode_get_name(endpoint)); + return endpoint; + } + } else { + port = ofnode_get_parent(prev); + endpoint = ofnode_next_subnode(prev); + if (ofnode_valid(endpoint)) { + debug("get next endpoint %s\n", ofnode_get_name(endpoint)); + return endpoint; + } + } + + debug("port %s\n", ofnode_get_name(port)); + + while (1) { + do { + port = ofnode_next_subnode(port); + if (!ofnode_valid(port)) + return ofnode_null(); + + name = ofnode_get_name(port); + } while (strncmp(name, "port", 4)); + + /* + * Now that we have a port node, get the next endpoint by + * getting the next child. If the previous endpoint is NULL this + * will return the first child. + */ + endpoint = ofnode_first_subnode(port); + if (ofnode_valid(endpoint)) { + debug("get next endpoint %s\n", ofnode_get_name(endpoint)); + return endpoint; + } + } + + return ofnode_null(); +} + +#define for_each_endpoint_of_node(parent, child) \ + for (child = ofnode_graph_get_next_endpoint(parent, ofnode_null()); ofnode_valid(child); \ + child = ofnode_graph_get_next_endpoint(parent, child)) + + +int ofnode_graph_get_endpoint_count(ofnode node) +{ + ofnode endpoint; + int num = 0; + + for_each_endpoint_of_node(node, endpoint) + num++; + + return num; +} + +int ofnode_graph_parse_endpoint(ofnode node, + struct of_endpoint *endpoint) +{ + ofnode port_node = ofnode_get_parent(node); + + memset(endpoint, 0, sizeof(*endpoint)); + + endpoint->local_node = node; + /* + * It doesn't matter whether the two calls below succeed. + * If they don't then the default value 0 is used. + */ + ofnode_read_u32(port_node, "reg", &endpoint->port); + ofnode_read_u32(node, "reg", &endpoint->id); + + return 0; +} + +ofnode ofnode_graph_get_endpoint_by_regs( + const ofnode parent, int port_reg, int reg) +{ + struct of_endpoint endpoint; + ofnode node; + + for_each_endpoint_of_node(parent, node) { + ofnode_graph_parse_endpoint(node, &endpoint); + if (((port_reg == -1) || (endpoint.port == port_reg)) && + ((reg == -1) || (endpoint.id == reg))) { + debug("get node %s\n", ofnode_get_name(node)); + + return node; + } + } + + return ofnode_null(); +} + +ofnode ofnode_graph_get_remote_endpoint(ofnode node) +{ + ofnode remote; + u32 phandle; + int ret; + + ret = ofnode_read_u32(node, "remote-endpoint", &phandle); + if (ret) { + printf("required remote-endpoint property isn't provided\n"); + return ofnode_null(); + } + + remote = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(remote)) { + printf("failed to find remote-endpoint\n"); + return ofnode_null(); + } + + return remote; +} + +ofnode ofnode_graph_get_port_parent(ofnode node) +{ + unsigned int depth; + + if (!ofnode_valid(node)) + return ofnode_null(); + + /* + * Preserve usecount for passed in node as of_get_next_parent() + * will do of_node_put() on it. + */ + + /* Walk 3 levels up only if there is 'ports' node. */ + for (depth = 3; depth && ofnode_valid(node); depth--) { + node = ofnode_get_parent(node); + const char *name = ofnode_get_name(node); + if (depth == 2 && strcmp(name, "ports")) + break; + } + return node; +} + +ofnode ofnode_graph_get_remote_port_parent(ofnode node) +{ + ofnode np, pp; + + /* Get remote endpoint node. */ + np = ofnode_graph_get_remote_endpoint(node); + + pp = ofnode_graph_get_port_parent(np); + + return pp; +} + +int find_device_by_ofnode(ofnode node, struct udevice **pdev) +{ + int ret; + + if (!ofnode_is_available(node)) + return -2; + + ret = uclass_find_device_by_ofnode(UCLASS_DISPLAY, node, pdev); + if (!ret) + return 0; + + ret = uclass_find_device_by_ofnode(UCLASS_DSI_HOST, node, pdev); + if (!ret) + return 0; + + ret = uclass_find_device_by_ofnode(UCLASS_VIDEO_BRIDGE, node, pdev); + if (!ret) + return 0; + + ret = uclass_find_device_by_ofnode(UCLASS_PANEL, node, pdev); + if (!ret) + return 0; + + return -1; +} + +static void video_link_stack_push(struct udevice *dev) +{ + if (temp_stack.dev_num < MAX_LINK_DEVICES) { + temp_stack.link_devs[temp_stack.dev_num] = dev; + temp_stack.dev_num++; + } +} + +static void video_link_stack_pop(void) +{ + if (temp_stack.dev_num > 0) { + temp_stack.link_devs[temp_stack.dev_num] = NULL; + temp_stack.dev_num--; + } +} + +static int duplicate_video_link(void) +{ + if (video_links_num < MAX_LINKS) { + video_links[video_links_num] = temp_stack; + video_links_num++; + + debug("duplicate links num %lu, temp_stack num %d\n", + video_links_num, temp_stack.dev_num); + return 0; + } + + return -ENODEV; +} + +static void video_link_add_node(struct udevice *peer_dev, struct udevice *dev, ofnode dev_node) +{ + int ret = 0; + ofnode remote, endpoint_node; + struct udevice *remote_dev; + bool find = false; + + debug("endpoint cnt %d\n", ofnode_graph_get_endpoint_count(dev_node)); + + video_link_stack_push(dev); + + for_each_endpoint_of_node(dev_node, endpoint_node) { + remote = ofnode_graph_get_remote_port_parent(endpoint_node); + if (!ofnode_valid(remote)) + continue; + + debug("remote %s\n", ofnode_get_name(remote)); + ret = find_device_by_ofnode(remote, &remote_dev); + if (!ret) { + debug("remote dev %s\n", remote_dev->name); + + if (peer_dev && peer_dev == remote_dev) + continue; + + /* it is possible that ofnode of remote_dev is not equal to remote */ + video_link_add_node(dev, remote_dev, remote); + + find = true; + } + } + + /* leaf node or no valid new endpoint, now copy the entire stack to a new video link */ + if (!find) { + ret = duplicate_video_link(); + if (ret) + printf("video link is full\n"); + } + + video_link_stack_pop(); +} + +struct udevice *video_link_get_next_device(struct udevice *curr_dev) +{ + int i, ret; + + if (video_off) + return NULL; + + if (curr_video_link >= video_links_num) { + printf("current video link is not correct\n"); + return NULL; + } + + for (i = 0; i < video_links[curr_video_link].dev_num; i++) { + if (video_links[curr_video_link].link_devs[i] == curr_dev) { + if ((i + 1) < video_links[curr_video_link].dev_num) { + ret = device_probe(video_links[curr_video_link].link_devs[i + 1]); + if (ret) { + printf("probe device is failed, ret %d\n", ret); + return NULL; + } + + return video_links[curr_video_link].link_devs[i + 1]; + } else { + debug("fail to find next device, already last one\n"); + return NULL; + } + } + } + + return NULL; +} + +struct udevice *video_link_get_video_device(void) +{ + int ret; + if (video_off) + return NULL; + + if (curr_video_link >= video_links_num) + return NULL; + + if (video_links[curr_video_link].dev_num == 0) + return NULL; + + ret = device_probe(video_links[curr_video_link].link_devs[0]); + if (ret) { + printf("probe video device failed, ret %d\n", ret); + return NULL; + } + + return video_links[curr_video_link].link_devs[0]; +} + +int video_link_get_display_timings(struct display_timing *timings) +{ + int i = 0; + int ret; + struct udevice *dev; + + if (video_off) + return -EPERM; + + if (curr_video_link >= video_links_num) + return -ENODEV; + + if (video_links[curr_video_link].dev_num == 0) + return -ENODEV; + + for (i = video_links[curr_video_link].dev_num - 1; i >= 0 ; i--) { + dev = video_links[curr_video_link].link_devs[i]; + if (device_get_uclass_id(dev) == UCLASS_PANEL) { + ret = device_probe(video_links[curr_video_link].link_devs[i]); + if (ret) { + printf("fail to probe panel device %s\n", dev->name); + return ret; + } + + ret = panel_get_display_timing(dev, timings); + if (ret) { + ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timings); + if (ret) { + printf("fail to get panel timing %s\n", dev->name); + return ret; + } + } + + return 0; + } else if (device_get_uclass_id(dev) == UCLASS_DISPLAY || + device_get_uclass_id(dev) == UCLASS_VIDEO) { + + ret = ofnode_decode_display_timing(dev_ofnode(dev), 0, timings); + if (!ret) + return 0; + } + } + + return -EINVAL; +} + +static void list_videolink(bool current_only) +{ + ulong index = 0; + int j; + bool match; + + /* dump the link */ + debug("video link number: %lu\n", video_links_num); + + for (index = 0; index < video_links_num; index ++) { + match = false; + if (curr_video_link == index) + match = true; + else if (current_only) + continue; + + printf("[%c]-Video Link %lu", (match)? '*':' ', index); + + if (match) { + struct udevice *video_dev = video_link_get_video_device(); + if (video_dev) { + printf(" (%u x %u)", video_get_xsize(video_dev), + video_get_ysize(video_dev)); + } + } + + printf("\n"); + + for (j = 0; j < video_links[index].dev_num; j++) { + printf("\t[%d] %s, %s\n", j, video_links[index].link_devs[j]->name, + dev_get_uclass_name(video_links[index].link_devs[j])); + } + } +} + +static int do_videolink(struct cmd_tbl * cmdtp, int flag, int argc, char * const argv[]) +{ + char cmd = 'l'; + int ret = 0; + + if (argc > 1) + cmd = argv[1][0]; + + switch (cmd) { + case 'l': /* list */ + list_videolink(false); + break; + default: + ret = CMD_RET_USAGE; + break; + } + + return ret; +} + +int video_link_init(void) +{ + struct udevice *dev; + ulong env_id; + int off; + memset(&video_links, 0, sizeof(video_links)); + memset(&temp_stack, 0, sizeof(temp_stack)); + + for (uclass_find_first_device(UCLASS_VIDEO, &dev); + dev; + uclass_find_next_device(&dev)) { + + video_link_add_node(NULL, dev, dev_ofnode(dev)); + } + + if (video_links_num == 0) { + printf("Fail to setup video link\n"); + return -ENODEV; + } + + /* Read the env variable for default video link */ + off = env_get_yesno("video_off"); + if (off == 1) { + video_off = true; + return 0; + } + + env_id = env_get_ulong("video_link", 10, 0); + if (env_id < video_links_num) + curr_video_link = env_id; + + list_videolink(true); + + return 0; +} + +int video_link_shut_down(void) +{ + struct udevice *video_dev = video_link_get_video_device(); + + if (video_dev) + device_remove(video_dev, DM_REMOVE_NORMAL); + + return 0; +} + +#ifdef CONFIG_SYS_LONGHELP +static char video_link_help_text[] = + "list \n" + " - show video link info, set video_link variable to select link"; +#endif + +U_BOOT_CMD( + videolink, 5, 1, do_videolink, + "list and select video link", video_link_help_text +); diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 602ccbe41c0..aa76a8f2d23 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -9,6 +9,19 @@ config WATCHDOG this option if you want to service enabled watchdog by U-Boot. Disable this option if you want U-Boot to start watchdog but never service it. +config WATCHDOG_AUTOSTART + bool "Automatically start watchdog timer" + depends on WDT + default y + help + Automatically start watchdog timer and start servicing it during + init phase. Enabled by default. Disable this option if you want + to compile U-Boot with CONFIG_WDT support but do not want to + activate watchdog, like when CONFIG_WDT option is disabled. You + would be able to start watchdog manually by 'wdt' command. Useful + when you want to have support for 'wdt' command but do not want + to have watchdog enabled by default. + config WATCHDOG_TIMEOUT_MSECS int "Watchdog timeout in msec" default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6 diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 5e0a096ce50..1ecfa02f3c9 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -48,7 +48,7 @@ void __attribute__((weak)) reset_cpu(ulong addr) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; - imx_watchdog_expire_now(wdog, true); + imx_watchdog_expire_now(wdog, false); } #endif diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c index 7533fc612c7..323132787f8 100644 --- a/drivers/watchdog/ulp_wdog.c +++ b/drivers/watchdog/ulp_wdog.c @@ -33,6 +33,8 @@ struct wdog_regs { #define WDGCS1_WDGE (1<<7) #define WDGCS1_WDGUPDATE (1<<5) +#define WDGCS2_RCS (1<<2) +#define WDGCS2_ULK (1<<3) #define WDGCS2_FLG (1<<6) #define WDG_BUS_CLK (0x0) @@ -52,8 +54,10 @@ void hw_watchdog_reset(void) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(REFRESH_WORD0, &wdog->cnt); - writel(REFRESH_WORD1, &wdog->cnt); + dmb(); + __raw_writel(REFRESH_WORD0, &wdog->cnt); + __raw_writel(REFRESH_WORD1, &wdog->cnt); + dmb(); } void hw_watchdog_init(void) @@ -61,8 +65,13 @@ void hw_watchdog_init(void) u8 val; struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(UNLOCK_WORD0, &wdog->cnt); - writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + __raw_writel(UNLOCK_WORD0, &wdog->cnt); + __raw_writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + + /* Wait WDOG Unlock */ + while (!(readb(&wdog->cs2) & WDGCS2_ULK)); val = readb(&wdog->cs2); val |= WDGCS2_FLG; @@ -74,6 +83,9 @@ void hw_watchdog_init(void) writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter running */ + /* Wait WDOG reconfiguration */ + while (!(readb(&wdog->cs2) & WDGCS2_RCS)); + hw_watchdog_reset(); } @@ -81,8 +93,13 @@ void reset_cpu(ulong addr) { struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; - writel(UNLOCK_WORD0, &wdog->cnt); - writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + __raw_writel(UNLOCK_WORD0, &wdog->cnt); + __raw_writel(UNLOCK_WORD1, &wdog->cnt); + dmb(); + + /* Wait WDOG Unlock */ + while (!(readb(&wdog->cs2) & WDGCS2_ULK)); hw_watchdog_set_timeout(5); /* 5ms timeout */ writel(0, &wdog->win); @@ -90,6 +107,9 @@ void reset_cpu(ulong addr) writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */ writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */ + /* Wait WDOG reconfiguration */ + while (!(readb(&wdog->cs2) & WDGCS2_RCS)); + hw_watchdog_reset(); while (1); diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index 28f7918c467..01e5fa47e8c 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -50,6 +50,11 @@ int initr_watchdog(void) 4 * reset_period) / 4; } + if (!CONFIG_IS_ENABLED(WATCHDOG_AUTOSTART)) { + printf("WDT: Not starting\n"); + return 0; + } + wdt_start(gd->watchdog_dev, timeout * 1000, 0); gd->flags |= GD_FLG_WDT_READY; printf("WDT: Started with%s servicing (%ds timeout)\n", diff --git a/env/Kconfig b/env/Kconfig index b473d7cfe1e..a989a59455c 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -19,7 +19,7 @@ config ENV_IS_NOWHERE !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ - !ENV_IS_IN_UBI + !ENV_IS_IN_UBI && !ENV_IS_IN_SATA help Define this if you don't want to or can't have an environment stored on a storage medium. In this case the environment will still exist @@ -291,6 +291,20 @@ config ENV_IS_IN_REMOTE local device can get the environment from remote memory space by SRIO or PCIE links. +config ENV_IS_IN_SATA + bool "Environment is in SATA disk" + depends on !CHAIN_OF_TRUST + help + Define this if you have a SATA disk device which you + want to use for the environment. + + - CONFIG_ENV_OFFSET: + - CONFIG_ENV_SIZE: + + These two #defines specify the offset and size of the + environment area within the SATA disk. CONFIG_ENV_OFFSET must be + aligned to an disk sector boundary. + config ENV_IS_IN_SPI_FLASH bool "Environment is in SPI flash" depends on !CHAIN_OF_TRUST && SPI @@ -516,7 +530,7 @@ config ENV_ADDR_REDUND config ENV_OFFSET hex "Environment offset" depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \ - ENV_IS_IN_SPI_FLASH + ENV_IS_IN_SPI_FLASH || ENV_IS_IN_SATA default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH default 0x88000 if ARCH_SUNXI diff --git a/env/eeprom.c b/env/eeprom.c index ba168014e24..1f36917a00f 100644 --- a/env/eeprom.c +++ b/env/eeprom.c @@ -70,7 +70,7 @@ static int eeprom_bus_write(unsigned dev_addr, unsigned offset, int env_eeprom_get_char(int index) { uchar c; - unsigned int off = CONFIG_ENV_OFFSET; + unsigned int off = env_get_offset(CONFIG_ENV_OFFSET); #ifdef CONFIG_ENV_OFFSET_REDUND if (gd->env_valid == ENV_REDUND) @@ -85,7 +85,7 @@ int env_eeprom_get_char(int index) static int env_eeprom_load(void) { char buf_env[CONFIG_ENV_SIZE]; - unsigned int off = CONFIG_ENV_OFFSET; + unsigned int off = env_get_offset(CONFIG_ENV_OFFSET); #ifdef CONFIG_ENV_OFFSET_REDUND ulong len, crc[2], crc_tmp; @@ -95,7 +95,7 @@ static int env_eeprom_load(void) eeprom_init(-1); /* prepare for EEPROM read/write */ - off_env[0] = CONFIG_ENV_OFFSET; + off_env[0] = env_get_offset(CONFIG_ENV_OFFSET); off_env[1] = CONFIG_ENV_OFFSET_REDUND; for (i = 0; i < 2; i++) { @@ -157,7 +157,7 @@ static int env_eeprom_load(void) /* read old CRC */ eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, - CONFIG_ENV_OFFSET + offsetof(env_t, crc), + env_get_offset(CONFIG_ENV_OFFSET) + offsetof(env_t, crc), (uchar *)&crc, sizeof(ulong)); new = 0; @@ -167,7 +167,7 @@ static int env_eeprom_load(void) int n = (len > sizeof(rdbuf)) ? sizeof(rdbuf) : len; eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, - CONFIG_ENV_OFFSET + off, rdbuf, n); + env_get_offset(CONFIG_ENV_OFFSET) + off, rdbuf, n); new = crc32(new, rdbuf, n); len -= n; off += n; @@ -180,7 +180,7 @@ static int env_eeprom_load(void) } #endif /* CONFIG_ENV_OFFSET_REDUND */ - off = CONFIG_ENV_OFFSET; + off = env_get_offset(CONFIG_ENV_OFFSET); #ifdef CONFIG_ENV_OFFSET_REDUND if (gd->env_valid == ENV_REDUND) off = CONFIG_ENV_OFFSET_REDUND; @@ -196,7 +196,7 @@ static int env_eeprom_save(void) { env_t env_new; int rc; - unsigned int off = CONFIG_ENV_OFFSET; + unsigned int off = env_get_offset(CONFIG_ENV_OFFSET); #ifdef CONFIG_ENV_OFFSET_REDUND unsigned int off_red = CONFIG_ENV_OFFSET_REDUND; char flag_obsolete = ENV_REDUND_OBSOLETE; @@ -209,7 +209,7 @@ static int env_eeprom_save(void) #ifdef CONFIG_ENV_OFFSET_REDUND if (gd->env_valid == ENV_VALID) { off = CONFIG_ENV_OFFSET_REDUND; - off_red = CONFIG_ENV_OFFSET; + off_red = env_get_offset(CONFIG_ENV_OFFSET); } env_new.flags = ENV_REDUND_ACTIVE; diff --git a/env/env.c b/env/env.c index caefa33e1d4..75a4e97cd03 100644 --- a/env/env.c +++ b/env/env.c @@ -391,3 +391,10 @@ int env_select(const char *name) return -ENODEV; } + +#ifndef ENV_IS_EMBEDDED +__weak long long env_get_offset(long long defautl_offset) +{ + return defautl_offset; +} +#endif diff --git a/env/mmc.c b/env/mmc.c index 9b226be1d5b..10434ccf3be 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -81,7 +81,7 @@ static inline s64 mmc_offset(int copy) return val; } - defvalue = CONFIG_ENV_OFFSET; + defvalue = env_get_offset(CONFIG_ENV_OFFSET); propname = dt_prop.offset; #if defined(CONFIG_ENV_OFFSET_REDUND) @@ -95,7 +95,7 @@ static inline s64 mmc_offset(int copy) #else static inline s64 mmc_offset(int copy) { - s64 offset = CONFIG_ENV_OFFSET; + s64 offset = env_get_offset(CONFIG_ENV_OFFSET); #if defined(CONFIG_ENV_OFFSET_REDUND) if (copy) diff --git a/env/nand.c b/env/nand.c index be82e97d69c..a7e5d59a61c 100644 --- a/env/nand.c +++ b/env/nand.c @@ -154,7 +154,7 @@ static int writeenv(size_t offset, u_char *buf) struct nand_env_location { const char *name; - const nand_erase_options_t erase_opts; + nand_erase_options_t erase_opts; }; static int erase_and_write_env(const struct nand_env_location *location, @@ -183,25 +183,17 @@ static int env_nand_save(void) int ret = 0; ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); int env_idx = 0; - static const struct nand_env_location location[] = { - { - .name = "NAND", - .erase_opts = { - .length = CONFIG_ENV_RANGE, - .offset = CONFIG_ENV_OFFSET, - }, - }, + static struct nand_env_location location[2] = {0}; + + location[0].name = "NAND"; + location[0].erase_opts.length = CONFIG_ENV_RANGE; + location[0].erase_opts.offset = env_get_offset(CONFIG_ENV_OFFSET); + #ifdef CONFIG_ENV_OFFSET_REDUND - { - .name = "redundant NAND", - .erase_opts = { - .length = CONFIG_ENV_RANGE, - .offset = CONFIG_ENV_OFFSET_REDUND, - }, - }, + location[1].name = "redundant NAND"; + location[1].erase_opts.length = CONFIG_ENV_RANGE; + location[1].erase_opts.offset = CONFIG_ENV_OFFSET_REDUND; #endif - }; - if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE) return 1; @@ -328,7 +320,7 @@ static int env_nand_load(void) goto done; } - read1_fail = readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1); + read1_fail = readenv(env_get_offset(CONFIG_ENV_OFFSET), (u_char *) tmp_env1); read2_fail = readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2); ret = env_import_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2, @@ -367,7 +359,7 @@ static int env_nand_load(void) } #endif - ret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf); + ret = readenv(env_get_offset(CONFIG_ENV_OFFSET), (u_char *)buf); if (ret) { env_set_default("readenv() failed", 0); return -EIO; diff --git a/env/sata.c b/env/sata.c index 9442cfcaf3c..586395b301b 100644 --- a/env/sata.c +++ b/env/sata.c @@ -15,6 +15,9 @@ #include #include #include +#ifdef CONFIG_DM_SCSI +#include +#endif #if defined(CONFIG_ENV_OFFSET_REDUND) #error ENV REDUND not supported @@ -49,12 +52,19 @@ static int env_sata_save(void) struct blk_desc *sata = NULL; int env_sata, ret; +#ifndef CONFIG_DM_SCSI if (sata_initialize()) return 1; env_sata = sata_get_env_dev(); sata = sata_get_dev(env_sata); +#else + scsi_scan(false); + env_sata = sata_get_env_dev(); + + sata = blk_get_dev("scsi", env_sata); +#endif if (sata == NULL) { printf("Unknown SATA(%d) device for environment!\n", env_sata); @@ -66,7 +76,7 @@ static int env_sata_save(void) return 1; printf("Writing to SATA(%d)...", env_sata); - if (write_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, (u_char *)env_new)) { + if (write_env(sata, CONFIG_ENV_SIZE, env_get_offset(CONFIG_ENV_OFFSET), (u_char *)env_new)) { puts("failed\n"); return 1; } @@ -89,24 +99,32 @@ static inline int read_env(struct blk_desc *sata, unsigned long size, return (n == blk_cnt) ? 0 : -1; } -static void env_sata_load(void) +static int env_sata_load(void) { ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); struct blk_desc *sata = NULL; int env_sata; +#ifndef CONFIG_DM_SCSI if (sata_initialize()) return -EIO; env_sata = sata_get_env_dev(); sata = sata_get_dev(env_sata); +#else + scsi_scan(false); + env_sata = sata_get_env_dev(); + + sata = blk_get_dev("scsi", env_sata); +#endif + if (sata == NULL) { printf("Unknown SATA(%d) device for environment!\n", env_sata); return -EIO; } - if (read_env(sata, CONFIG_ENV_SIZE, CONFIG_ENV_OFFSET, buf)) { + if (read_env(sata, CONFIG_ENV_SIZE, env_get_offset(CONFIG_ENV_OFFSET), buf)) { env_set_default(NULL, 0); return -EIO; } diff --git a/env/sf.c b/env/sf.c index 88ec1108b68..97aad5364f4 100644 --- a/env/sf.c +++ b/env/sf.c @@ -86,9 +86,9 @@ static int env_sf_save(void) if (gd->env_valid == ENV_VALID) { env_new_offset = CONFIG_ENV_OFFSET_REDUND; - env_offset = CONFIG_ENV_OFFSET; + env_offset = env_get_offset(CONFIG_ENV_OFFSET); } else { - env_new_offset = CONFIG_ENV_OFFSET; + env_new_offset = env_get_offset(CONFIG_ENV_OFFSET); env_offset = CONFIG_ENV_OFFSET_REDUND; } @@ -167,7 +167,7 @@ static int env_sf_load(void) if (ret) goto out; - read1_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET, + read1_fail = spi_flash_read(env_flash, env_get_offset(CONFIG_ENV_OFFSET), CONFIG_ENV_SIZE, tmp_env1); read2_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, tmp_env2); @@ -198,7 +198,7 @@ static int env_sf_save(void) /* Is the sector larger than the env (i.e. embedded) */ if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) { saved_size = CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SIZE; - saved_offset = CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE; + saved_offset = env_get_offset(CONFIG_ENV_OFFSET) + CONFIG_ENV_SIZE; saved_buffer = malloc(saved_size); if (!saved_buffer) goto done; @@ -216,13 +216,13 @@ static int env_sf_save(void) sector = DIV_ROUND_UP(CONFIG_ENV_SIZE, CONFIG_ENV_SECT_SIZE); puts("Erasing SPI flash..."); - ret = spi_flash_erase(env_flash, CONFIG_ENV_OFFSET, + ret = spi_flash_erase(env_flash, env_get_offset(CONFIG_ENV_OFFSET), sector * CONFIG_ENV_SECT_SIZE); if (ret) goto done; puts("Writing to SPI flash..."); - ret = spi_flash_write(env_flash, CONFIG_ENV_OFFSET, + ret = spi_flash_write(env_flash, env_get_offset(CONFIG_ENV_OFFSET), CONFIG_ENV_SIZE, &env_new); if (ret) goto done; @@ -260,7 +260,7 @@ static int env_sf_load(void) goto out; ret = spi_flash_read(env_flash, - CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, buf); + env_get_offset(CONFIG_ENV_OFFSET), CONFIG_ENV_SIZE, buf); if (ret) { env_set_default("spi_flash_read() failed", 0); goto err_read; diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 8ff2f6def08..2b429e42728 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -824,7 +824,15 @@ static int new_dir_table(fat_itr *itr) int dir_oldclust = itr->clust; unsigned int bytesperclust = mydata->clust_size * mydata->sect_size; - dir_newclust = find_empty_cluster(mydata); + if (mydata->fatsize == 32) { + dir_newclust = find_empty_cluster(mydata); + } else { + dir_newclust = itr->clust + 1; + if (dir_newclust > 1) { + printf("error: fail to get empty clust for directory entry\n"); + return -1; + } + } /* * Flush before updating FAT to ensure valid directory structure @@ -836,13 +844,10 @@ static int new_dir_table(fat_itr *itr) if (flush_dir(itr)) return -EIO; - set_fatent_value(mydata, dir_oldclust, dir_newclust); - if (mydata->fatsize == 32) + if (mydata->fatsize == 32) { + set_fatent_value(mydata, dir_oldclust, dir_newclust); set_fatent_value(mydata, dir_newclust, 0xffffff8); - else if (mydata->fatsize == 16) - set_fatent_value(mydata, dir_newclust, 0xfff8); - else if (mydata->fatsize == 12) - set_fatent_value(mydata, dir_newclust, 0xff8); + } if (flush_dirty_fat_buffer(mydata) < 0) return -EIO; diff --git a/include/android_bootloader_message.h b/include/android_bootloader_message.h index 286d7ab0f31..0ba906803a3 100644 --- a/include/android_bootloader_message.h +++ b/include/android_bootloader_message.h @@ -28,10 +28,12 @@ // 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used // as bootloader_message_ab struct) // 16K - 64K Used by uncrypt and recovery to store wipe_package for A/B devices +// 32K - 64K System space, used for miscellanious AOSP features. See below. // Note that these offsets are admitted by bootloader,recovery and uncrypt, so they // are not configurable without changing all of them. static const size_t BOOTLOADER_MESSAGE_OFFSET_IN_MISC = 0; static const size_t WIPE_PACKAGE_OFFSET_IN_MISC = 16 * 1024; +static const size_t SYSTEM_SPACE_SIZE_IN_MISC = 32 * 1024; /* Bootloader Message (2-KiB) * @@ -145,8 +147,16 @@ struct slot_metadata { // 1 if this slot is corrupted from a dm-verity corruption, 0 // otherwise. uint8_t verity_corrupted : 1; +#ifdef CONFIG_DUAL_BOOTLOADER + // 1 if the bootloader has been verified in spl stage, 0 otherwise. + // this is needed for dual bootloader case. + uint8_t bootloader_verified : 1; + // Reserved for further use. + uint8_t reserved : 6; +#else // Reserved for further use. uint8_t reserved : 7; +#endif } __attribute__((packed)); /* Bootloader Control AB @@ -172,8 +182,17 @@ struct bootloader_control { uint8_t reserved0[2]; // Per-slot information. Up to 4 slots. struct slot_metadata slot_info[4]; +#ifdef CONFIG_DUAL_BOOTLOADER + //Last boot slot + uint8_t last_boot; + //spl recovery mode + bool spl_recovery; + // Reserved for further use. + uint8_t reserved1[6]; +#else // Reserved for further use. uint8_t reserved1[8]; +#endif // CRC32 of all 28 bytes preceding this field (little endian // format). uint32_t crc32_le; @@ -187,6 +206,17 @@ static_assert(sizeof(struct bootloader_control) == #endif #endif /* __UBOOT__ */ +typedef struct misc_virtual_ab_message { + uint8_t version; + uint32_t magic; + uint8_t merge_status; // IBootControl 1.1, MergeStatus enum. + uint8_t source_slot; // Slot number when merge_status was written. + uint8_t reserved[57]; +} __attribute__((packed)) misc_virtual_ab_message; + +#define MISC_VIRTUAL_AB_MESSAGE_VERSION 2 +#define MISC_VIRTUAL_AB_MAGIC_HEADER 0x56740AB0 + #ifndef __UBOOT__ #ifdef __cplusplus diff --git a/include/android_image.h b/include/android_image.h index 54d25af0684..fb435035d68 100644 --- a/include/android_image.h +++ b/include/android_image.h @@ -20,8 +20,26 @@ #define ANDR_BOOT_ARGS_SIZE 512 #define ANDR_BOOT_EXTRA_ARGS_SIZE 1024 +#define ANDR_VENDOR_BOOT_MAGIC "VNDRBOOT" +#define ANDR_VENDOR_BOOT_MAGIC_SIZE 8 +#define ANDR_VENDOR_BOOT_ARGS_SIZE 2048 +#define ANDR_VENDOR_BOOT_NAME_SIZE 16 + /* The bootloader expects the structure of andr_img_hdr with header * version 0 to be as follows: */ +/* Boot metric variables (in millisecond) */ +struct boot_metric +{ + u32 bll_1; /* 1th bootloader load duration */ + u32 ble_1; /* 1th bootloader exec duration */ + u32 kl; /* kernel image load duration */ + u32 kd; /* kernel image decompress duration */ + u32 avb; /* avb verify boot.img duration */ + u32 odt; /* overlay device tree duration */ + u32 sw; /* system wait for UI interaction duration*/ +}; +typedef struct boot_metric boot_metric; + struct andr_img_hdr { /* Must be ANDR_BOOT_MAGIC. */ char magic[ANDR_BOOT_MAGIC_SIZE]; @@ -67,22 +85,85 @@ struct andr_img_hdr { u64 dtb_addr; /* physical load address for DTB image */ } __attribute__((packed)); +struct boot_img_hdr_v3 { + // Must be BOOT_MAGIC. + uint8_t magic[ANDR_BOOT_MAGIC_SIZE]; + + uint32_t kernel_size; /* size in bytes */ + uint32_t ramdisk_size; /* size in bytes */ + + // Operating system version and security patch level. + // For version "A.B.C" and patch level "Y-M-D": + // (7 bits for each of A, B, C; 7 bits for (Y-2000), 4 bits for M) + // os_version = A[31:25] B[24:18] C[17:11] (Y-2000)[10:4] M[3:0] + uint32_t os_version; + +#if __cplusplus + void SetOsVersion(unsigned major, unsigned minor, unsigned patch) { + os_version &= ((1 << 11) - 1); + os_version |= (((major & 0x7f) << 25) | ((minor & 0x7f) << 18) | ((patch & 0x7f) << 11)); + } + + void SetOsPatchLevel(unsigned year, unsigned month) { + os_version &= ~((1 << 11) - 1); + os_version |= (((year - 2000) & 0x7f) << 4) | ((month & 0xf) << 0); + } +#endif + + uint32_t header_size; + + uint32_t reserved[4]; + + // Version of the boot image header. + uint32_t header_version; + + uint8_t cmdline[ANDR_BOOT_ARGS_SIZE + ANDR_BOOT_EXTRA_ARGS_SIZE]; +} __attribute__((packed)); + +struct vendor_boot_img_hdr_v3 { + // Must be ANDR_VENDOR_BOOT_MAGIC. + uint8_t magic[ANDR_VENDOR_BOOT_MAGIC_SIZE]; + + // Version of the vendor boot image header. + uint32_t header_version; + + uint32_t page_size; /* flash page size we assume */ + + uint32_t kernel_addr; /* physical load addr */ + uint32_t ramdisk_addr; /* physical load addr */ + + uint32_t vendor_ramdisk_size; /* size in bytes */ + + uint8_t cmdline[ANDR_VENDOR_BOOT_ARGS_SIZE]; + + uint32_t tags_addr; /* physical addr for kernel tags (if required) */ + uint8_t name[ANDR_VENDOR_BOOT_NAME_SIZE]; /* asciiz product name */ + + uint32_t header_size; + + uint32_t dtb_size; /* size in bytes for DTB image */ + uint64_t dtb_addr; /* physical load address for DTB image */ +} __attribute__((packed)); + /* When a boot header is of version 0, the structure of boot image is as * follows: * * +-----------------+ * | boot header | 1 page * +-----------------+ - * | kernel | n pages + * | kernel | i pages * +-----------------+ * | ramdisk | m pages * +-----------------+ - * | second stage | o pages + * | second stage | n pages + * +-----------------+ + * | recovery dtbo | o pages * +-----------------+ * - * n = (kernel_size + page_size - 1) / page_size + * i = (kernel_size + page_size - 1) / page_size * m = (ramdisk_size + page_size - 1) / page_size - * o = (second_size + page_size - 1) / page_size + * n = (second_size + page_size - 1) / page_size + * o = (recovery_dtbo_size + page_size - 1) / page_size * * 0. all entities are page_size aligned in flash * 1. kernel and ramdisk are required (size != 0) @@ -136,4 +217,61 @@ struct andr_img_hdr { * else: jump to kernel_addr */ +/* When the boot image header has a version of 3, the structure of the boot + * image is as follows: + * + * +---------------------+ + * | boot header | 4096 bytes + * +---------------------+ + * | kernel | m pages + * +---------------------+ + * | ramdisk | n pages + * +---------------------+ + * + * m = (kernel_size + 4096 - 1) / 4096 + * n = (ramdisk_size + 4096 - 1) / 4096 + * + * Note that in version 3 of the boot image header, page size is fixed at 4096 bytes. + * + * The structure of the vendor boot image (introduced with version 3 and + * required to be present when a v3 boot image is used) is as follows: + * + * +---------------------+ + * | vendor boot header | o pages + * +---------------------+ + * | vendor ramdisk | p pages + * +---------------------+ + * | dtb | q pages + * +---------------------+ + + * o = (2112 + page_size - 1) / page_size + * p = (vendor_ramdisk_size + page_size - 1) / page_size + * q = (dtb_size + page_size - 1) / page_size + * + * 0. all entities in the boot image are 4096-byte aligned in flash, all + * entities in the vendor boot image are page_size (determined by the vendor + * and specified in the vendor boot image header) aligned in flash + * 1. kernel, ramdisk, vendor ramdisk, and DTB are required (size != 0) + * 2. load the kernel and DTB at the specified physical address (kernel_addr, + * dtb_addr) + * 3. load the vendor ramdisk at ramdisk_addr + * 4. load the generic ramdisk immediately following the vendor ramdisk in + * memory + * 5. set up registers for kernel entry as required by your architecture + * 6. if the platform has a second stage bootloader jump to it (must be + * contained outside boot and vendor boot partitions), otherwise + * jump to kernel_addr + */ +struct header_image { + uint32_t code0; /* Executable code */ + uint32_t code1; /* Executable code */ + uint64_t text_offset; /* Image load offset, LE */ + uint64_t image_size; /* Effective Image size, LE */ + uint64_t res1; /* reserved */ + uint64_t res2; /* reserved */ + uint64_t res3; /* reserved */ + uint64_t res4; /* reserved */ + uint32_t magic; /* Magic number */ + uint32_t res5; +}; #endif diff --git a/include/command.h b/include/command.h index 747f8f80958..1498fc25417 100644 --- a/include/command.h +++ b/include/command.h @@ -203,6 +203,10 @@ int do_env_set_efi(struct cmd_tbl *cmdtp, int flag, int argc, int setexpr_regex_sub(char *data, uint data_size, char *nbuf, uint nbuf_size, const char *r, const char *s, bool global); +#ifdef CONFIG_CMD_READ +int do_raw_read(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +#endif + /* * Error codes that commands return to cmd_process(). We use the standard 0 * and 1 for success and failure, but add one more case - failure with a diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index af7e3e49fdd..1bda7704c9e 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -14,6 +14,8 @@ #undef CONFIG_DM_SERIAL #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_DM_USB #endif #undef CONFIG_DM_STDIO diff --git a/include/configs/compulab-imx8m-plus.h b/include/configs/compulab-imx8m-plus.h new file mode 100644 index 00000000000..6a5f824f6d2 --- /dev/null +++ b/include/configs/compulab-imx8m-plus.h @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 CompuLab + */ + +#ifndef __COMPULAB_IMX8M_PLUS +#define __COMPULAB_IMX8M_PLUS + +#include +#include + +#include "imx_env.h" + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + +#define CONFIG_SPL_MAX_SIZE (152 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#define SPL_STACK_ADDR 0x96dff0 +#define SHARED_DDR_INFO SPL_STACK_ADDR +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK SPL_STACK_ADDR +#define CONFIG_SPL_BSS_START_ADDR 0x96e000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_4K /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_256K /* 256 KB */ + +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_REMAKE_ELF + +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include +#else +#define BOOTENV +#endif + +#ifndef MACHINE_EXTRA_ENV_SETTINGS +#define MACHINE_EXTRA_ENV_SETTINGS +#endif + +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_mmcboot=setenv fdtfile ucm-imx8m-plus-root.dtb;" \ + "setenv jh_clk clk_ignore_unused mem=2048MB; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=setenv fdtfile ucm-imx8m-plus-root.dtb; setenv jh_clk clk_ignore_unused mem=2048MB; run netboot; \0 " + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + JAILHOUSE_ENV \ + BOOTENV \ + MACHINE_EXTRA_ENV_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ + "stdin=serial,usbkbd\0" \ + "autoload=off\0" \ + "scriptaddr=0x43500000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "bsp_script=boot.scr\0" \ + "image=Image\0" \ + "splashimage=0x50000000\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "fdto_addr_r=0x43800000\0" \ + "fdt_addr=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "emmc_root=/dev/mmcblk2p2\0" \ + "sd_root=/dev/mmcblk1p2\0" \ + "usb_root=/dev/sda2\0" \ + "usb_dev=0\0" \ + "boot_part=1\0" \ + "root_opt=rootwait rw\0" \ + "emmc_ul=setenv iface mmc; setenv dev ${emmc_dev}; setenv part ${boot_part};" \ + "setenv bootargs console=${console} root=${emmc_root} ${root_opt};\0" \ + "sd_ul=setenv iface mmc; setenv dev ${sd_dev}; setenv part ${boot_part};" \ + "setenv bootargs console=${console} root=${sd_root} ${root_opt};\0" \ + "usb_ul=usb start; setenv iface usb; setenv dev ${usb_dev}; setenv part ${boot_part};" \ + "setenv bootargs console=${console} root=${usb_root} ${root_opt};\0" \ + "ulbootscript=load ${iface} ${dev}:${part} ${scriptaddr} ${bsp_script};\0" \ + "ulrunbootscript=echo Running bootscript from ${iface} ${dev}:${part} ...; " \ + "source ${scriptaddr}\0" \ + "ulimage=load ${iface} ${dev}:${part} ${loadaddr} ${image}\0" \ + "ulfdt=if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "load ${iface} ${dev}:${part} ${fdt_addr_r} ${fdtfile}; " \ + "if itest.s x != x${fdtofile}; then " \ + "load ${iface} ${dev}:${part} ${fdto_addr_r} ${fdtofile};" \ + "fdt addr ${fdt_addr_r}; fdt resize 0x8000; fdt apply ${fdto_addr_r};" \ + "else " \ + "true;" \ + "fi;" \ + "fi;\0" \ + "bootlist=usb_ul sd_ul emmc_ul\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "for src in ${bootlist}; do " \ + "echo Running ${src} ...; " \ + "run ${src}; " \ + "env exist boot_opt && env exists bootargs && setenv bootargs ${bootargs} ${boot_opt}; " \ + "if run ulbootscript; then " \ + "run ulrunbootscript; " \ + "fi; " \ + "if run ulimage; then " \ + "if run ulfdt; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "if test ${boot_fdt} != yes; then " \ + "booti ${loadaddr}; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "done; " +#endif + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +/* Totally 6GB DDR */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#endif /* CONFIG_NAND_MXS */ + +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#ifdef CONFIG_SYS_PROMPT +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT CONFIG_SYS_BOARD"=> " +#endif diff --git a/include/configs/cpl-imx8m-mini.h b/include/configs/cpl-imx8m-mini.h new file mode 100644 index 00000000000..fe7c1d79d39 --- /dev/null +++ b/include/configs/cpl-imx8m-mini.h @@ -0,0 +1,275 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CPL_IMX8M_MINI_H +#define __CPL_IMX8M_MINI_H + +#include +#include +#include "imx_env.h" + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x912000 + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_BD71837 + +#endif /*ifdef CONFIG_SPL_BUILD*/ + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_REMAKE_ELF + +#define CONFIG_BOARD_POSTCLK_INIT + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#undef CONFIG_CMD_IMLS + +#undef CONFIG_CMD_CRC32 +#undef CONFIG_BOOTM_NETBSD + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=1\0" \ + "sd_dev=0\0" \ + "bootcmd_mfg=run mfgtool_args; if iminfo ${initrd_addr}; then "\ + "booti ${loadaddr} ${initrd_addr} ${fdt_addr};"\ + "else echo \"Run fastboot ...\"; fastboot 0; fi\0" \ +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "autoload=off\0" \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=yes\0" \ + "fdt_file="CONFIG_DEFAULT_FDT"\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "root_opt=rootwait rw\0" \ + "emmc_ul=setenv iface mmc; setenv dev 2; setenv part 1;" \ + "setenv bootargs console=${console} root=/dev/mmcblk2p2 ${root_opt};\0" \ + "sd_ul=setenv iface mmc; setenv dev 1; setenv part 1;" \ + "setenv bootargs console=${console} root=/dev/mmcblk1p2 ${root_opt};\0" \ + "usb_ul=usb start; setenv iface usb; setenv dev 0; setenv part 1;" \ + "setenv bootargs console=${console} root=/dev/sda2 ${root_opt};\0" \ + "ulbootscript=load ${iface} ${dev}:${part} ${loadaddr} ${script};\0" \ + "ulimage=load ${iface} ${dev}:${part} ${loadaddr} ${image}\0" \ + "ulfdt=if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "load ${iface} ${dev}:${part} ${fdt_addr} ${fdt_file}; fi;\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" +#define CONFIG_BOOTCOMMAND \ + "for src in sd_ul usb_ul emmc_ul; do " \ + "run ${src}; " \ + "if run ulbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run ulimage; then " \ + "if run ulfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} != yes; then " \ + "booti ${loadaddr}; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "done; " \ + "usb start; ums 0 mmc ${mmcdev};" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_SYS_MMC_ENV_PART 1 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024) + (16*1024)) * 1024) + +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_SIZE 0 /* Memory chip autodetection */ +#define PHYS_SDRAM_2_SIZE 0 /* Memory chip autodetection */ +#define CONFIG_NR_DRAM_BANKS 4 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define MEMTEST_DIVIDER 2 +#define MEMTEST_NUMERATOR 1 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_IMX_BOOTAUX + +/* USDHC */ +#define CONFIG_FSL_USDHC + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* EEPROM */ +#define CONFIG_ENV_EEPROM_IS_ON_I2C +#define CONFIG_SYS_I2C_EEPROM_BUS 1 +#define CONFIG_SYS_I2C_SLAVE 0x00 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_SIZE 256 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_RM67191 +#endif + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_OF_BOARD_SETUP + +#endif diff --git a/include/configs/imx8dxl_evk.h b/include/configs/imx8dxl_evk.h new file mode 100644 index 00000000000..1a933b50643 --- /dev/null +++ b/include/configs/imx8dxl_evk.h @@ -0,0 +1,361 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __IMX8DXL_EVK_H +#define __IMX8DXL_EVK_H + +#include +#include + +#include "imx_env.h" + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (128 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ + +/* + * 0x08081000 - 0x08180FFF is for m4_0 xip image, + * So 3rd container image may start from 0x8181000 + */ +#define CONFIG_SYS_UBOOT_BASE 0x08181000 + +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0x8000000) /*Put the FIT out of first 128MB boot area */ +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_IDENT + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +/* + * The memory layout on stack: DATA section save + gd + early malloc + * the idea is re-use the early malloc (CONFIG_SYS_MALLOC_F_LEN) with + * CONFIG_SYS_SPL_MALLOC_START + */ +#define CONFIG_SPL_STACK 0x822ffff0 +#define CONFIG_SPL_BSS_START_ADDR 0x82280000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x82200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x82200000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_CMD_READ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 + +#define CONFIG_PCIE_IMX +#define CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +#define JAILHOUSE_ENV \ + "jh_mmcboot=" \ + "setenv fdt_file imx8dxl-evk-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run mmcboot; \0" \ + "jh_netboot=" \ + "setenv fdt_file imx8dxl-evk-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run netboot; \0" + +#define XEN_BOOT_ENV \ + "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=1024M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x9e000000\0" \ + "dom0fdt_file=imx8dxl-evk-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "setenv bootargs ${xenhyper_bootargs};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ + +/* Initial environment variables */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "bootargs=console=ttyLP0,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0"\ + "console=ttyLP0,115200 earlycon\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "fdt_addr=0x83000000\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + XEN_BOOT_ENV \ + JAILHOUSE_ENV\ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "splashimage=0x9e000000\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file=undefined\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_BOOTCOMMAND \ + "nand read ${loadaddr} 0x9000000 0x2000000;"\ + "nand read ${fdt_addr} 0xB000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr}" +#else +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" +#endif + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* USDHC2 for SD */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 + +/* total DDR is 1GB */ +#if defined(CONFIG_TARGET_IMX8DXL_DDR3_EVK) +#define PHYS_SDRAM_1_SIZE 0x20000000 +#else +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +#endif + +#define PHYS_SDRAM_2_SIZE 0x00000000 + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#define CONFIG_SERIAL_TAG + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +#endif + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +/* Networking */ +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC +#define CONFIG_FEC_MXC_PHYADDR 0x1 + +#define DWC_NET_PHYADDR 0 + +#define CONFIG_ETHPRIME "eth1" +#define PHY_ANEG_TIMEOUT 20000 + +#if defined(CONFIG_DM_VIDEO) +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LINK +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#endif /* __IMX8DXL_EVK_H */ diff --git a/include/configs/imx8dxl_phantom_mek.h b/include/configs/imx8dxl_phantom_mek.h new file mode 100644 index 00000000000..b799ff84f0d --- /dev/null +++ b/include/configs/imx8dxl_phantom_mek.h @@ -0,0 +1,303 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __IMX8DXL_PHANTOM_MEK_H +#define __IMX8DXL_PHANTOM_MEK_H + +#include +#include + +#include "imx_env.h" + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (192 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ + +/* + * 0x08081000 - 0x08180FFF is for m4_0 xip image, + * So 3rd container image may start from 0x8181000 + */ +#define CONFIG_SYS_UBOOT_BASE 0x08181000 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +/* + * The memory layout on stack: DATA section save + gd + early malloc + * the idea is re-use the early malloc (CONFIG_SYS_MALLOC_F_LEN) with + * CONFIG_SYS_SPL_MALLOC_START + */ +#define CONFIG_SPL_STACK 0x013fff0 +#define CONFIG_SPL_BSS_START_ADDR 0x00130000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x82200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x00138000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_CMD_READ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 + +#define CONFIG_PCIE_IMX +#define CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +#define JAILHOUSE_ENV \ + "jh_mmcboot=" \ + "setenv fdt_file imx8qxp-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run mmcboot; \0" \ + "jh_netboot=" \ + "setenv fdt_file imx8qxp-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run netboot; \0" + +#define XEN_BOOT_ENV \ + "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=1024M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x9e000000\0" \ + "dom0fdt_file=imx8qxp-mek-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "setenv bootargs ${xenhyper_bootargs};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + XEN_BOOT_ENV \ + JAILHOUSE_ENV\ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file=undefined\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "run boot_os; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "run boot_os; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* USDHC1 is for eMMC, USDHC2 is for SD. However SD can't boot due to pinmux in ROM */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 + +/* total DDR is 1GB */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#define CONFIG_SERIAL_TAG + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +/* Networking */ +#define IMX_FEC_BASE 0x5B050000 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth1" + +#define CONFIG_FEC_XCV_TYPE RGMII +#define PHY_ANEG_TIMEOUT 20000 + + +#endif /* __IMX8DXL_PHANTOM_MEK_H */ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index fd9a6cbb8c2..f5bcdd245e6 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -9,12 +9,13 @@ #include #include #include +#include "imx_env.h" #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) #define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (0x300 + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET) #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) @@ -26,35 +27,176 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 +#define CONFIG_MALLOC_F_ADDR 0x912000 /* For RAW image gives a error info not panic */ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#if defined(CONFIG_IMX8M_LPDDR4) && defined(CONFIG_TARGET_IMX8MM_EVK) +#define CONFIG_POWER_PCA9450 +#else +#define CONFIG_POWER_BD71837 #endif -#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_I2C + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DMA +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_IDENT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ + +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) +#endif + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_REMAKE_ELF +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define IMX_FEC_BASE 0x30BE0000 +#endif + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" +#endif + +#ifdef CONFIG_DISTRO_DEFAULTS #define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ func(MMC, mmc, 1) \ - func(MMC, mmc, 2) \ - func(DHCP, dhcp, na) + func(MMC, mmc, 2) #include +#else +#define BOOTENV #endif +/* + * Another approach is add the clocks for inmates into clks_init_on + * in clk-imx8mm.c, then clk_ingore_unused could be removed. + */ +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_mmcboot=mw 0x303d0518 0xff; setenv fdtfile imx8mm-evk-root.dtb;" \ + "setenv jh_clk clk_ignore_unused mem=1340MB; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=mw 0x303d0518 0xff; setenv fdtfile imx8mm-evk-root.dtb; setenv jh_clk clk_ignore_unused mem=1340MB; run netboot; \0 " + + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + /* Initial environment variables */ +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "splashimage=0x50000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ + "nand read ${fdt_addr_r} 0x7000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr_r}" + +#else #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ BOOTENV \ + JAILHOUSE_ENV \ "scriptaddr=0x43500000\0" \ - "kernel_addr_r=0x40880000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "bsp_script=boot.scr\0" \ "image=Image\0" \ + "splashimage=0x50000000\0" \ "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ "boot_fit=no\0" \ - "fdt_file=imx8mm-evk.dtb\0" \ - "initrd_addr=0x43800000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" +#endif /* Link Definitions */ #define CONFIG_LOADADDR 0x40480000 @@ -68,6 +210,13 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ /* Size of malloc() pool */ @@ -86,22 +235,70 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_IMX_BOOTAUX + /* USDHC */ #define CONFIG_FSL_USDHC +#ifdef CONFIG_TARGET_IMX8MM_DDR4_EVK +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else #define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#endif +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_FSL_FSPI +#define FSL_FSPI_FLASH_SIZE SZ_32M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x30bb0000 +#define FSPI0_AMBA_BASE 0x0 +#define CONFIG_FSPI_QUAD_SUPPORT + +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#endif /* CONFIG_NAND_MXS */ + #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_ETHPRIME "FEC" +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_USBD_HS -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#define FEC_QUIRK_ENET_MAC +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE -#define IMX_FEC_BASE 0x30BE0000 +#endif + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#ifdef CONFIG_ANDROID_SUPPORT +#include "imx8mm_evk_android.h" +#endif #endif diff --git a/include/configs/imx8mm_evk_android.h b/include/configs/imx8mm_evk_android.h new file mode 100644 index 00000000000..102af08b361 --- /dev/null +++ b/include/configs/imx8mm_evk_android.h @@ -0,0 +1,78 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8MM_EVK_ANDROID_H +#define IMX8MM_EVK_ANDROID_H + +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "splashimage=0x50000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Enable mcu firmware flash */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC +#define ANDROID_MCU_FIRMWARE_START 0x500000 +#define ANDROID_MCU_FIRMWARE_SIZE 0x40000 +#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000 +#endif + +#ifdef CONFIG_DUAL_BOOTLOADER +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +#ifdef CONFIG_IMX_TRUSTY_OS +#define BOOTLOADER_RBIDX_OFFSET 0x3FE000 +#define BOOTLOADER_RBIDX_START 0x3FF000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#endif + +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x1FFF +#define NS_ARCH_ARM64 1 + +#ifdef CONFIG_ID_ATTESTATION +#define ATTESTATION_ID_BRAND "Android" +#define ATTESTATION_ID_DEVICE "evk_8mm" +#define ATTESTATION_ID_MANUFACTURER "nxp" +#define ATTESTATION_ID_MODEL "EVK_8MM" +#ifdef CONFIG_ATTESTATION_ID_PRODUCT +#undef CONFIG_ATTESTATION_ID_PRODUCT +#endif +#define CONFIG_ATTESTATION_ID_PRODUCT "evk_8mm" +#endif + +#endif + +/* Enable CONFIG_IMX8M_1G_MEMORY to config 1GB ddr */ +#ifdef CONFIG_IMX8M_1G_MEMORY +#undef PHYS_SDRAM_SIZE +#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ +#endif + +#ifdef CONFIG_IMX8M_4G_LPDDR4 +#undef PHYS_SDRAM_SIZE +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1GB */ +#endif + +#endif /* IMX8MM_EVK_ANDROID_H */ diff --git a/include/configs/imx8mm_val.h b/include/configs/imx8mm_val.h new file mode 100644 index 00000000000..f638953b892 --- /dev/null +++ b/include/configs/imx8mm_val.h @@ -0,0 +1,231 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8MM_VAL_H +#define __IMX8MM_VAL_H + +#include +#include +#include +#include "imx_env.h" + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (0x300 + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET) +#define CONFIG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_STACK 0x920000 +#define CONFIG_SPL_BSS_START_ADDR 0x910000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x912000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_BD71837 + +#define CONFIG_SYS_I2C +#endif + + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_REMAKE_ELF +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 + + +#define IMX_FEC_BASE 0x30BE0000 + +#ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 3 +#else +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_XCV_TYPE RGMII +#endif + +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +/* USDHC */ +#define CONFIG_FSL_USDHC + +#ifdef CONFIG_TARGET_IMX8MM_DDR3L_VAL +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_FSL_FSPI +#define FSL_FSPI_FLASH_SIZE SZ_32M +#define FSL_FSPI_FLASH_NUM 1 +#define FSPI0_BASE_ADDR 0x30bb0000 +#define FSPI0_AMBA_BASE 0x0 +#define CONFIG_FSPI_QUAD_SUPPORT + +#define CONFIG_SYS_FSL_FSPI_AHB +#endif + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#endif /* CONFIG_NAND_MXS */ + +#define CONFIG_SYS_I2C_SPEED 100000 + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#endif diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index 596e255ca6d..ff65b80999c 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -9,19 +9,20 @@ #include #include #include +#include "imx_env.h" #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE (148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K +#define CONFIG_SPL_MAX_SIZE (208 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x980000 -#define CONFIG_SPL_BSS_START_ADDR 0x950000 +#define CONFIG_SPL_STACK 0x95dff0 +#define CONFIG_SPL_BSS_START_ADDR 0x95e000 #define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ @@ -29,40 +30,115 @@ /* For RAW image gives a error info not panic */ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DMA +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_IDENT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ + +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) +#endif + +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_REMAKE_ELF +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define IMX_FEC_BASE 0x30BE0000 #endif +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include +#else +#define BOOTENV +#endif + +/* + * Another approach is add the clocks for inmates into clks_init_on + * in clk-imx8mm.c, then clk_ingore_unused could be removed. + */ +#ifdef CONFIG_TARGET_IMX8MN_DDR4_EVK +#define JH_ROOT_DTB "imx8mn-ddr4-evk-root.dtb" +#else +#define JH_ROOT_DTB "imx8mn-evk-root.dtb" +#endif + +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_root_dtb=" JH_ROOT_DTB "\0" \ + "jh_mmcboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb};" \ + "setenv jh_clk clk_ignore_unused mem=1340MB; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=mw 0x303d0518 0xff; setenv fdtfile ${jh_root_dtb}; setenv jh_clk clk_ignore_unused mem=1340MB; run netboot; \0 " + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ + CONFIG_MFG_ENV_SETTINGS \ + JAILHOUSE_ENV \ + BOOTENV \ + "scriptaddr=0x43500000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "bsp_script=boot.scr\0" \ "image=Image\0" \ + "splashimage=0x50000000\0" \ "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ "boot_fit=no\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "bootm_size=0x10000000\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ "bootm ${loadaddr}; " \ "else " \ "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "fi;\0" \ - "netargs=setenv bootargs console=${console} " \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ @@ -76,15 +152,14 @@ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ "bootm ${loadaddr}; " \ "else " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ @@ -95,18 +170,25 @@ "fi; " \ "fi;" + /* Link Definitions */ #define CONFIG_LOADADDR 0x40480000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 #define CONFIG_SYS_INIT_SP_OFFSET \ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ /* Size of malloc() pool */ @@ -114,7 +196,12 @@ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define PHYS_SDRAM 0x40000000 + +#ifdef CONFIG_TARGET_IMX8MN_DDR3_EVK +#define PHYS_SDRAM_SIZE 0x40000000 /* 1GB DDR */ +#else #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#endif #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR @@ -125,6 +212,8 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_IMX_BOOTAUX + /* USDHC */ #define CONFIG_FSL_USDHC @@ -133,6 +222,46 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#endif /* CONFIG_NAND_MXS */ + #define CONFIG_SYS_I2C_SPEED 100000 +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#ifdef CONFIG_ANDROID_SUPPORT +#include "imx8mn_evk_android.h" +#endif + #endif diff --git a/include/configs/imx8mn_evk_android.h b/include/configs/imx8mn_evk_android.h new file mode 100644 index 00000000000..b53d9140c5b --- /dev/null +++ b/include/configs/imx8mn_evk_android.h @@ -0,0 +1,65 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8MN_EVK_ANDROID_H +#define IMX8MN_EVK_ANDROID_H + +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "splashimage=0x50000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Enable mcu firmware flash */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC +#define ANDROID_MCU_FIRMWARE_START 0x500000 +#define ANDROID_MCU_FIRMWARE_SIZE 0x40000 +#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000 +#endif + +#ifdef CONFIG_DUAL_BOOTLOADER +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +#ifdef CONFIG_IMX_TRUSTY_OS +#define BOOTLOADER_RBIDX_OFFSET 0x3FE000 +#define BOOTLOADER_RBIDX_START 0x3FF000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#endif + +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x1FFF +#define NS_ARCH_ARM64 1 + +#ifdef CONFIG_ID_ATTESTATION +#define ATTESTATION_ID_BRAND "Android" +#define ATTESTATION_ID_DEVICE "evk_8mn" +#define ATTESTATION_ID_MANUFACTURER "nxp" +#define ATTESTATION_ID_MODEL "EVK_8MN" +#ifdef CONFIG_ATTESTATION_ID_PRODUCT +#undef CONFIG_ATTESTATION_ID_PRODUCT +#endif +#define CONFIG_ATTESTATION_ID_PRODUCT "evk_8mn" +#endif + +#endif + +#endif /* IMX8MN_EVK_ANDROID_H */ diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 61a5c6fb79c..10e87f349d8 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -9,6 +9,7 @@ #include #include #include +#include "imx_env.h" #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) @@ -19,66 +20,172 @@ #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) #ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_STACK 0x960000 -#define CONFIG_SPL_BSS_START_ADDR 0x0098FC00 -#define CONFIG_SPL_BSS_MAX_SIZE 0x400 /* 1 KB */ +#define CONFIG_SPL_STACK 0x96dff0 +#define CONFIG_SPL_BSS_START_ADDR 0x96e000 +#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ +/* For RAW image gives a error info not panic */ #define CONFIG_SPL_ABORT_ON_RAW_IMAGE -#undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC -#undef CONFIG_DM_PMIC_PFUZE100 +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DMA +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_IDENT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PCA9450 - -#define CONFIG_SYS_I2C +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) +#endif #endif +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_REMAKE_ELF +/* ENET Config */ +/* ENET1 */ + #if defined(CONFIG_CMD_NET) #define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 1 -#define FEC_QUIRK_ENET_MAC #define DWC_NET_PHYADDR 1 -#ifdef CONFIG_DWC_ETH_QOS -#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ -#endif #define PHY_ANEG_TIMEOUT 20000 #endif -#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_DISTRO_DEFAULTS #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 2) + func(USB, usb, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) #include +#else +#define BOOTENV +#endif + + +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_mmcboot=setenv fdtfile imx8mp-evk-root.dtb;" \ + "setenv jh_clk clk_ignore_unused mem=2048MB; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=setenv fdtfile imx8mp-evk-root.dtb; setenv jh_clk clk_ignore_unused mem=2048MB; run netboot; \0 " + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" #endif /* Initial environment variables */ +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "splashimage=0x50000000\0" \ + "fdt_addr_r=0x43000000\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "bootargs=console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ + "nand read ${fdt_addr_r} 0x7000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr_r}" + +#else #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + JAILHOUSE_ENV \ BOOTENV \ "scriptaddr=0x43500000\0" \ - "kernel_addr_r=0x40880000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "bsp_script=boot.scr\0" \ "image=Image\0" \ - "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ + "splashimage=0x50000000\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ "fdt_addr=0x43000000\0" \ "boot_fdt=try\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fit=no\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ + "bootm ${loadaddr}; " \ + "else " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" +#endif /* Link Definitions */ #define CONFIG_LOADADDR 0x40480000 @@ -92,6 +199,11 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ /* Size of malloc() pool */ @@ -102,7 +214,11 @@ #define PHYS_SDRAM 0x40000000 #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ #define PHYS_SDRAM_2 0x100000000 +#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ +#else #define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */ +#endif #define CONFIG_MXC_UART_BASE UART2_BASE_ADDR @@ -113,13 +229,54 @@ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_IMX_BOOTAUX #define CONFIG_FSL_USDHC +#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else #define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#endif /* CONFIG_NAND_MXS */ + #define CONFIG_SYS_I2C_SPEED 100000 +/* USB configs */ +#ifndef CONFIG_SPL_BUILD + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#ifdef CONFIG_ANDROID_SUPPORT +#include "imx8mp_evk_android.h" +#endif + #endif diff --git a/include/configs/imx8mp_evk_android.h b/include/configs/imx8mp_evk_android.h new file mode 100644 index 00000000000..8796b3da316 --- /dev/null +++ b/include/configs/imx8mp_evk_android.h @@ -0,0 +1,65 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8MP_EVK_ANDROID_H +#define IMX8MP_EVK_ANDROID_H + +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "splashimage=0x50000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Enable mcu firmware flash */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC +#define ANDROID_MCU_FIRMWARE_START 0x500000 +#define ANDROID_MCU_FIRMWARE_SIZE 0x40000 +#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000 +#endif + +#ifdef CONFIG_DUAL_BOOTLOADER +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +#ifdef CONFIG_IMX_TRUSTY_OS +#define BOOTLOADER_RBIDX_OFFSET 0x3FE000 +#define BOOTLOADER_RBIDX_START 0x3FF000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#endif + +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x1FFF +#define NS_ARCH_ARM64 1 + +#ifdef CONFIG_ID_ATTESTATION +#define ATTESTATION_ID_BRAND "Android" +#define ATTESTATION_ID_DEVICE "evk_8mp" +#define ATTESTATION_ID_MANUFACTURER "nxp" +#define ATTESTATION_ID_MODEL "EVK_8MP" +#ifdef CONFIG_ATTESTATION_ID_PRODUCT +#undef CONFIG_ATTESTATION_ID_PRODUCT +#endif +#define CONFIG_ATTESTATION_ID_PRODUCT "evk_8mp" +#endif + +#endif + +#endif /* IMX8MP_EVK_ANDROID_H */ diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 1861ebad18b..647850cd2e6 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -9,26 +9,19 @@ #include #include #include +#include "imx_env.h" #define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) -#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SPL_MAX_SIZE (148 * 1024) #define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (0x300 + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET) #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_WATCHDOG_SUPPORT -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" #define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_BSS_START_ADDR 0x00180000 #define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ #define CONFIG_SYS_SPL_MALLOC_START 0x42200000 @@ -45,11 +38,6 @@ #undef CONFIG_DM_PMIC_PFUZE100 #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_POWER #define CONFIG_POWER_I2C @@ -61,42 +49,116 @@ /* ENET Config */ /* ENET1 */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_MII +#if defined(CONFIG_FEC_MXC) #define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 -#define CONFIG_FEC_MXC #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 -#define FEC_QUIRK_ENET_MAC -#define CONFIG_PHY_GIGE #define IMX_FEC_BASE 0x30BE0000 #endif -#ifndef CONFIG_SPL_BUILD +#ifdef CONFIG_DISTRO_DEFAULTS #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(DHCP, dhcp, na) + func(USB, usb, 0) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) #include +#else +#define BOOTENV #endif +/* + * Another approach is add the clocks for inmates into clks_init_on + * in clk-imx8mq.c, then clk_ingore_unused could be removed. + */ +#define JAILHOUSE_ENV \ + "jh_clk= \0 " \ + "jh_mmcboot=setenv fdtfile imx8mq-evk-root.dtb; " \ + "setenv jh_clk clk_ignore_unused mem=2000M; " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run jh_netboot; fi; \0" \ + "jh_netboot=setenv fdtfile imx8mq-evk-root.dtb; setenv jh_clk clk_ignore_unused mem=2000M; run netboot; \0 " + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=1\0" \ + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ BOOTENV \ + JAILHOUSE_ENV \ "scriptaddr=0x43500000\0" \ - "kernel_addr_r=0x40880000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "bsp_script=boot.scr\0" \ "image=Image\0" \ + "splashimage=0x50000000\0" \ "console=ttymxc0,115200\0" \ + "fdt_addr_r=0x43000000\0" \ "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ "boot_fdt=try\0" \ - "fdt_file=imx8mq-evk.dtb\0" \ - "initrd_addr=0x43800000\0" \ + "fdtfile=imx8mq-evk.dtb\0" \ "bootm_size=0x10000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bsp_script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs ${jh_clk} console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "booti ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" \ + "bsp_bootcmd=echo Running BSP bootcmd ...; " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi;" /* Link Definitions */ #define CONFIG_LOADADDR 0x40480000 @@ -122,8 +184,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE_ADDR /* Monitor Command Prompt */ -#undef CONFIG_SYS_PROMPT -#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE @@ -137,15 +198,44 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 -#define CONFIG_MXC_GPIO - /* I2C Configs */ #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_OF_SYSTEM_SETUP +/* USB configs */ +#ifndef CONFIG_SPL_BUILD + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#define CONFIG_CMD_READ + +#endif + +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +#define CONFIG_USBD_HS +#define CONFIG_USB_GADGET_VBUS_DRAW 2 #ifndef CONFIG_SPL_BUILD #define CONFIG_DM_PMIC #endif +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#ifdef CONFIG_ANDROID_SUPPORT +#include "imx8mq_evk_android.h" +#endif + #endif diff --git a/include/configs/imx8mq_evk_android.h b/include/configs/imx8mq_evk_android.h new file mode 100644 index 00000000000..8647a5b3969 --- /dev/null +++ b/include/configs/imx8mq_evk_android.h @@ -0,0 +1,65 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8MQ_EVK_ANDROID_H +#define IMX8MQ_EVK_ANDROID_H + +#define FSL_FASTBOOT_FB_DEV "mmc" + +#ifdef CONFIG_SYS_MALLOC_LEN +#undef CONFIG_SYS_MALLOC_LEN +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) +#endif + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "splashimage=0x50000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +/* Enable mcu firmware flash */ +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +#define ANDROID_MCU_FRIMWARE_DEV_TYPE DEV_MMC +#define ANDROID_MCU_FIRMWARE_START 0x500000 +#define ANDROID_MCU_FIRMWARE_SIZE 0x40000 +#define ANDROID_MCU_FIRMWARE_HEADER_STACK 0x20020000 +#endif + +#ifdef CONFIG_DUAL_BOOTLOADER +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +#ifdef CONFIG_IMX_TRUSTY_OS +#define BOOTLOADER_RBIDX_OFFSET 0x1E000 +#define BOOTLOADER_RBIDX_START 0x1F000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#endif + +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x1FFF +#define NS_ARCH_ARM64 1 + +#ifdef CONFIG_ID_ATTESTATION +#define ATTESTATION_ID_BRAND "Android" +#define ATTESTATION_ID_DEVICE "evk_8mq" +#define ATTESTATION_ID_MANUFACTURER "nxp" +#define ATTESTATION_ID_MODEL "EVK_8MQ" +#ifdef CONFIG_ATTESTATION_ID_PRODUCT +#undef CONFIG_ATTESTATION_ID_PRODUCT +#endif +#define CONFIG_ATTESTATION_ID_PRODUCT "evk_8mq" +#endif + +#endif + +#endif /* IMX8MQ_EVK_ANDROID_H */ diff --git a/include/configs/imx8mq_val.h b/include/configs/imx8mq_val.h new file mode 100644 index 00000000000..9328d6c0526 --- /dev/null +++ b/include/configs/imx8mq_val.h @@ -0,0 +1,256 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8M_VAL_H +#define __IMX8M_VAL_H + +#include +#include +#include +#include "imx_env.h" + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + +#define CONFIG_SPL_MAX_SIZE (148 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (0x300 + CONFIG_SECONDARY_BOOT_SECTOR_OFFSET) + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_MALLOC_F_ADDR 0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_DMA +#define CONFIG_SPL_NAND_MXS +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_IDENT +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000000 /* Put the FIT out of first 64MB boot area */ + +/* Set a redundant offset in nand FIT mtdpart. The new uuu will burn full boot image (not only FIT part) to the mtdpart, so we check both two offsets */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND \ + (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8400) +#endif + +#endif /* CONFIG_SPL_BUILD*/ + +#define CONFIG_REMAKE_ELF + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_FEC_MXC) +#define CONFIG_ETHPRIME "FEC" +#define PHY_ANEG_TIMEOUT 20000 + +#define FEC_QUIRK_ENET_MAC + +#define IMX_FEC_BASE 0x30BE0000 + +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_FEC_MXC_PHYADDR 3 +#else +#define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_FEC_XCV_TYPE RGMII +#endif + +#endif + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0"\ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ + "bootargs=console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x5000000 0x2000000;"\ + "nand read ${fdt_addr} 0x7000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr}" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=Image\0" \ + "console=ttymxc0,115200\0" \ + "fdt_addr=0x43000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" +#endif + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#ifdef CONFIG_TARGET_IMX8MQ_DDR3L_VAL +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR3L for two rank */ +#else +#define PHYS_SDRAM_SIZE 0xc0000000 /* 3GB */ +#define PHYS_SDRAM_2 0x100000000 +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1GB */ +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x20000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#endif /* CONFIG_NAND_MXS */ + +/* USB configs */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_CMD_USB + +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#endif diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 99e73a9446b..e90b2508dbd 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -9,74 +9,204 @@ #include #include #include +#include "imx_env.h" #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SPL_MAX_SIZE (192 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */ + +/* + * 0x08081000 - 0x08180FFF is for m4_0 xip image, + * 0x08181000 - 0x008280FFF is for m4_1 xip image + * So 3rd container image may start from 0x8281000 + */ +#define CONFIG_SYS_UBOOT_BASE 0x08281000 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_STACK 0x013fff0 +#define CONFIG_SPL_BSS_START_ADDR 0x00130000 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY +#define CONFIG_SERIAL_LPUART_BASE 0x5a080000 /* use UART2 */ +#define CONFIG_SYS_SPL_MALLOC_START 0xC2200000 +#else #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CONFIG_SYS_SPL_MALLOC_START 0x82200000 +#endif +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_MALLOC_F_ADDR 0x00138000 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE #define CONFIG_SPL_ABORT_ON_RAW_IMAGE -#define CONFIG_OF_EMBED +#endif + +#ifdef CONFIG_TARGET_IMX8QM_MEK_A53_ONLY +#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M) +#define IMX_HDMITX_FIRMWARE_SIZE 0x20000 +#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000 #endif #define CONFIG_REMAKE_ELF +#define CONFIG_CMD_READ + /* Flat Device Tree Definitions */ #define CONFIG_OF_BOARD_SETUP #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ +#ifndef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY +#define CONFIG_PCIE_IMX +#define CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC +#define PHY_ANEG_TIMEOUT 20000 + +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */ +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE 0x5B040000 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE 0x5B050000 +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_ETHPRIME "eth1" +#endif + #ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else #define AHAB_ENV "sec_boot=no\0" #endif + +#define JAILHOUSE_ENV \ + "jh_mmcboot=" \ + "setenv fdt_file imx8qm-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run mmcboot; \0" \ + "jh_netboot=" \ + "setenv fdt_file imx8qm-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run netboot; \0" + +#define XEN_BOOT_ENV \ + "domu-android-auto=no\0" \ + "xenhyper_bootargs=console=dtuart dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x9e000000\0" \ + "dom0fdt_file=imx8qm-mek-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "if test ${domu-android-auto} = yes; then; " \ + "fdt set /domu/doma android-auto <1>;" \ + "fdt rm /gpio@5d090000 power-domains;" \ + "fi;" \ + "setenv bootargs ${xenhyper_bootargs};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY +#define HDP_LOAD_ENV +#define INITRD_ADDR_ENV "initrd_addr=0xC3100000\0" +#else +#define HDP_LOAD_ENV \ + "if run loadhdp; then; hdp load ${hdp_addr}; fi;" +#define INITRD_ADDR_ENV "initrd_addr=0x83100000\0" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + INITRD_ADDR_ENV \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + XEN_BOOT_ENV \ + JAILHOUSE_ENV\ AHAB_ENV \ "script=boot.scr\0" \ "image=Image\0" \ - "panel=NULL\0" \ - "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ - "fdt_addr=0x83000000\0" \ + SPLASH_IMAGE_ADDR \ + CONFIG_CONSOLE \ + FDT_ADDR \ "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ "boot_fdt=try\0" \ - "fdt_file=undefined\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ + FDT_FILE \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot} " \ + "cpufreq.default_governor=SCHEDUTIL\0" \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "hdp_addr=0x9c000000\0" \ + "hdprx_addr=0x9c800000\0" \ + "hdp_file=hdmitxfw.bin\0" \ + "hdprx_file=hdmirxfw.bin\0" \ + "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \ + "loadhdprx=fatload mmc ${mmcdev}:${mmcpart} ${hdprx_addr} ${hdprx_file}\0" \ "boot_os=booti ${loadaddr} - ${fdt_addr};\0" \ "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ "auth_os=auth_cntr ${cntr_addr}\0" \ "mmcboot=echo Booting from mmc ...; " \ + HDP_LOAD_ENV \ "run mmcargs; " \ "if test ${sec_boot} = yes; then " \ "if run auth_os; then " \ @@ -95,9 +225,10 @@ "echo wait for boot; " \ "fi;" \ "fi;\0" \ - "netargs=setenv bootargs console=${console} " \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon " \ "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ + "cpufreq.default_governor=SCHEDUTIL\0" \ "netboot=echo Booting from net ...; " \ "run netargs; " \ "if test ${ip_dyn} = yes; then " \ @@ -105,6 +236,7 @@ "else " \ "setenv get_cmd tftp; " \ "fi; " \ + "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ "if test ${sec_boot} = yes; then " \ "${get_cmd} ${cntr_addr} ${cntr_file}; " \ "if run auth_os; then " \ @@ -116,7 +248,7 @@ "${get_cmd} ${loadaddr} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ + "run boot_os; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ @@ -145,33 +277,135 @@ "else booti ${loadaddr} - ${fdt_addr}; fi" /* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#ifdef CONFIG_TARGET_IMX8QM_MEK_A72_ONLY + #define CONFIG_LOADADDR 0xC0280000 + #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_INIT_SP_ADDR 0xC0200000 +#else + #define CONFIG_LOADADDR 0x80280000 + #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 +#endif -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 +#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) + #define FDT_ADDR "fdt_addr=0xC3000000\0" + #define FDT_FILE "fdt_file=imx8qm-mek-cockpit-a72.dtb\0" +#elif defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) + #define FDT_ADDR "fdt_addr=0x83000000\0" + #define FDT_FILE "fdt_file=imx8qm-mek-cockpit-a53.dtb\0" +#else + #define FDT_ADDR "fdt_addr=0x83000000\0" + #define FDT_FILE "fdt_file=undefined\0" +#endif -/* Default environment is in SD */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) + #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ + #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#elif defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) + #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#else + #define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ + #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#endif #define CONFIG_SYS_FSL_USDHC_NUM 2 +#if defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) +#define CONFIG_CONSOLE "console=ttyLP2\0" +#define SPLASH_IMAGE_ADDR "splashimage=0xde000000\0" +#else +#define CONFIG_CONSOLE "console=ttyLP0\0" +#define SPLASH_IMAGE_ADDR "splashimage=0x9e000000\0" +#endif + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) +#define CONFIG_NR_DRAM_BANKS 4 +#if defined(CONFIG_TARGET_IMX8QM_MEK_A53_ONLY) +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ +#elif defined(CONFIG_TARGET_IMX8QM_MEK_A72_ONLY) +#define CONFIG_SYS_SDRAM_BASE 0xC0000000 +#define PHYS_SDRAM_1 0xC0000000 +#define PHYS_SDRAM_2 0x900000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ +#else #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ #define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ +#endif /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ -/* Networking */ -#define CONFIG_FEC_XCV_TYPE RGMII +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_SERIAL_TAG + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "imx8qm_mek_android.h" +#elif defined (CONFIG_ANDROID_AUTO_SUPPORT) +#include "imx8qm_mek_android_auto.h" +#elif defined(CONFIG_IMX8_TRUSTY_XEN) +#include "imx8qm_mek_trusty_xen.h" +#endif + #endif /* __IMX8QM_MEK_H */ diff --git a/include/configs/imx8qm_mek_android.h b/include/configs/imx8qm_mek_android.h new file mode 100644 index 00000000000..196b3414e85 --- /dev/null +++ b/include/configs/imx8qm_mek_android.h @@ -0,0 +1,46 @@ +/* + * Copyright 2021 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QM_MEK_ANDROID_H +#define IMX8QM_MEK_ANDROID_H + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define FSL_FASTBOOT_FB_DEV "mmc" + +#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M) +#define IMX_HDMITX_FIRMWARE_SIZE 0x20000 +#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000 + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "splashimage=0x9e000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NS_ARCH_ARM64 1 +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF +#define AVB_RPMB + +#ifdef CONFIG_ID_ATTESTATION +#define ATTESTATION_ID_BRAND "Android" +#define ATTESTATION_ID_DEVICE "mek_8q" +#define ATTESTATION_ID_MANUFACTURER "nxp" +#define ATTESTATION_ID_MODEL "MEK-MX8Q" +#ifdef CONFIG_ATTESTATION_ID_PRODUCT +#undef CONFIG_ATTESTATION_ID_PRODUCT +#endif +#define CONFIG_ATTESTATION_ID_PRODUCT "mek_8q" +#endif + +#endif + +#endif /* IMX8QM_MEK_ANDROID_H */ diff --git a/include/configs/imx8qm_mek_android_auto.h b/include/configs/imx8qm_mek_android_auto.h new file mode 100644 index 00000000000..4cc1bbcfa70 --- /dev/null +++ b/include/configs/imx8qm_mek_android_auto.h @@ -0,0 +1,61 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QM_MEK_ANDROID_AUTO_H +#define IMX8QM_MEK_ANDROID_AUTO_H + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_SKIP_RESOURCE_CHECKING + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#ifndef CONFIG_MXC_USB_PORTSC +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif +#endif + +#define FSL_FASTBOOT_FB_DEV "mmc" + +#define IMX_HDMI_FIRMWARE_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_64M) +#define IMX_HDMITX_FIRMWARE_SIZE 0x20000 +#define IMX_HDMIRX_FIRMWARE_SIZE 0x20000 + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#define NS_ARCH_ARM64 1 +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF + +#ifdef CONFIG_ID_ATTESTATION +#define ATTESTATION_ID_BRAND "Android" +#define ATTESTATION_ID_DEVICE "mek_8q" +#define ATTESTATION_ID_MANUFACTURER "nxp" +#define ATTESTATION_ID_MODEL "MEK-MX8Q" +#endif + +#endif + +#ifdef CONFIG_DUAL_BOOTLOADER +#define BOOTLOADER_RBIDX_OFFSET 0x3FE000 +#define BOOTLOADER_RBIDX_START 0x3FF000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x801F8000 +#endif + +#if defined(CONFIG_XEN) +#include "imx8qm_mek_android_auto_xen.h" +#endif + +#endif /* IMX8QM_MEK_ANDROID_AUTO_H */ diff --git a/include/configs/imx8qm_mek_android_auto_xen.h b/include/configs/imx8qm_mek_android_auto_xen.h new file mode 100644 index 00000000000..9b8c357f981 --- /dev/null +++ b/include/configs/imx8qm_mek_android_auto_xen.h @@ -0,0 +1,50 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QM_MEK_ANDROID_AUTO_XEN_H +#define IMX8QM_MEK_ANDROID_AUTO_XEN_H + +#undef CONFIG_SYS_SDRAM_BASE +#undef CONFIG_NR_DRAM_BANKS +#undef PHYS_SDRAM_1 +#undef PHYS_SDRAM_2 +#undef PHYS_SDRAM_1_SIZE +#undef PHYS_SDRAM_2_SIZE + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x200000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x60000000 /* 1536 MB */ + +#undef CONFIG_LOADADDR +#define CONFIG_LOADADDR 0x80080000 +#undef CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SYS_INIT_SP_ADDR 0x81200000 + +#undef CONFIG_REQUIRE_SERIAL_CONSOLE +#undef CONFIG_IMX_SMMU + +#undef CONFIG_FASTBOOT_USB_DEV +#define CONFIG_FASTBOOT_USB_DEV 0 /* Use OTG port, not typec port */ + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SPL_BSS_START_ADDR +#undef CONFIG_SYS_SPL_MALLOC_START +#undef CONFIG_MALLOC_F_ADDR +#undef CONFIG_SPL_TEXT_BASE +#undef CONFIG_SPL_STACK + +#define CONFIG_MALLOC_F_ADDR 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SPL_BSS_START_ADDR 0x80300000 +#define CONFIG_SPL_STACK 0x80400000 + +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x80500000 +#endif + +#endif /* IMX8QM_MEK_ANDROID_AUTO_XEN_H */ diff --git a/include/configs/imx8qm_val.h b/include/configs/imx8qm_val.h new file mode 100644 index 00000000000..6bf41145a65 --- /dev/null +++ b/include/configs/imx8qm_val.h @@ -0,0 +1,316 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2017-2019 NXP + */ + +#ifndef __IMX8QM_VAL_H +#define __IMX8QM_VAL_H + +#include +#include +#include +#include "imx_env.h" + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (192 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (flash.bin_offset + 2Mb)/sector_size */ +#define CONFIG_SYS_UBOOT_BASE 0x08281000 + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +/* + * The memory layout on stack: DATA section save + gd + early malloc + * the idea is re-use the early malloc (CONFIG_SYS_MALLOC_F_LEN) with + * CONFIG_SYS_SPL_MALLOC_START + */ +#define CONFIG_SPL_STACK 0x013fff0 +#define CONFIG_SPL_BSS_START_ADDR 0x00130000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x82200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x00138000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_CMD_READ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 +#define USDHC3_BASE_ADDR 0x5B030000 + +#define CONFIG_PCIE_IMX +#define CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC +#define PHY_ANEG_TIMEOUT 20000 + +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */ +#define CONFIG_ETHPRIME "eth0" + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "m4_1_image=m4_1.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \ + + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" +#endif + +#define XEN_BOOT_ENV \ + "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=2048M dom0_max_vcpus=2 dom0_vcpus_pin=true hmp-unsafe=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x9e000000\0" \ + "dom0fdt_file=imx8qm-lpddr4-arm2-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "setenv bootargs ${xenhyper_bootargs};" \ + "scu_rm dtb ${fdt_addr};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ + + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + XEN_BOOT_ENV \ + M4_BOOT_ENV \ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "hdp_addr=0x9c000000\0" \ + "hdp_file=dpfw.bin\0" \ + "loadhdp=fatload mmc ${mmcdev}:${mmcpart} ${hdp_addr} ${hdp_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "if run loadhdp; then; hdp load ${hdp_addr}; fi;" \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if ${get_cmd} ${hdp_addr} ${hdp_file}; then; hdp load ${hdp_addr}; fi;" \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, eMMC0 is for eMMC, USDHC1 is for SD on CPU board, USDHC2 is for SD on base board + * On DDR4 board, eMMC0 and USDHC1 is mux for NAND, USDHC2 is for SD + */ +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_VAL +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC1 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC1 */ +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +#else + +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 1 + +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 6GB, DDR4 board total DDR is 4GB */ +#ifdef CONFIG_TARGET_IMX8QM_LPDDR4_VAL +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ +#else +#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */ +#endif + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#define CONFIG_SERIAL_TAG + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#endif /* __IMX8QM_VAL_H */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index a7d623a9b9e..8e5e48026e8 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -10,30 +10,39 @@ #include #include +#include "imx_env.h" + #ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SPL_MAX_SIZE (192 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ + +/* + * 0x08081000 - 0x08180FFF is for m4_0 xip image, + * So 3rd container image may start from 0x8181000 + */ +#define CONFIG_SYS_UBOOT_BASE 0x08181000 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 +#define CONFIG_SPL_STACK 0x013fff0 +#define CONFIG_SPL_BSS_START_ADDR 0x00130000 #define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x82200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 +#define CONFIG_MALLOC_F_ADDR 0x00138000 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE #define CONFIG_SPL_ABORT_ON_RAW_IMAGE -#define CONFIG_OF_EMBED #endif #define CONFIG_REMAKE_ELF +#define CONFIG_CMD_READ + /* Flat Device Tree Definitions */ #define CONFIG_OF_BOARD_SETUP @@ -41,6 +50,10 @@ #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 +#define CONFIG_PCIE_IMX +#define CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW + #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #ifdef CONFIG_AHAB_BOOT @@ -49,24 +62,81 @@ #define AHAB_ENV "sec_boot=no\0" #endif +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +#define JAILHOUSE_ENV \ + "jh_mmcboot=" \ + "setenv fdt_file imx8qxp-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run mmcboot; \0" \ + "jh_netboot=" \ + "setenv fdt_file imx8qxp-mek-root.dtb;"\ + "setenv boot_os 'scu_rm dtb ${fdt_addr}; booti ${loadaddr} - ${fdt_addr};'; " \ + "run netboot; \0" + +#define XEN_BOOT_ENV \ + "xenhyper_bootargs=console=dtuart dtuart=/serial@5a060000 dom0_mem=1024M dom0_max_vcpus=2 dom0_vcpus_pin=true\0" \ + "xenlinux_bootargs= \0" \ + "xenlinux_console=hvc0 earlycon=xen\0" \ + "xenlinux_addr=0x9e000000\0" \ + "dom0fdt_file=imx8qxp-mek-dom0.dtb\0" \ + "xenboot_common=" \ + "${get_cmd} ${loadaddr} xen;" \ + "${get_cmd} ${fdt_addr} ${dom0fdt_file};" \ + "${get_cmd} ${xenlinux_addr} ${image};" \ + "fdt addr ${fdt_addr};" \ + "fdt resize 256;" \ + "fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; " \ + "fdt set /chosen/module@0 bootargs \"${bootargs} ${xenlinux_bootargs}\"; " \ + "setenv bootargs ${xenhyper_bootargs};" \ + "booti ${loadaddr} - ${fdt_addr};" \ + "\0" \ + "xennetboot=" \ + "setenv get_cmd dhcp;" \ + "setenv console ${xenlinux_console};" \ + "run netargs;" \ + "run xenboot_common;" \ + "\0" \ + "xenmmcboot=" \ + "setenv get_cmd \"fatload mmc ${mmcdev}:${mmcpart}\";" \ + "setenv console ${xenlinux_console};" \ + "run mmcargs;" \ + "run xenboot_common;" \ + "\0" \ + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + XEN_BOOT_ENV \ + JAILHOUSE_ENV\ AHAB_ENV \ "script=boot.scr\0" \ "image=Image\0" \ - "panel=NULL\0" \ + "splashimage=0x9e000000\0" \ "console=ttyLP0\0" \ "fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ "boot_fdt=try\0" \ "fdt_file=undefined\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot}\0 " \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ @@ -94,7 +164,7 @@ "echo wait for boot; " \ "fi;" \ "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ @@ -150,7 +220,13 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 -/* Default environment is in SD */ +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 @@ -164,9 +240,26 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 + +#ifdef CONFIG_TARGET_IMX8DX_MEK +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ +#else #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ /* LPDDR4 board total DDR is 3GB */ #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ +#endif + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ @@ -175,12 +268,58 @@ #define CONFIG_PCA953X #endif +#define CONFIG_SERIAL_TAG + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE + +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + /* Networking */ +#define CONFIG_FEC_ENET_DEV 0 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE 0x5B040000 +#define CONFIG_FEC_MXC_PHYADDR 0x0 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE 0x5B050000 +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_ETHPRIME "eth1" +#endif + #define CONFIG_FEC_XCV_TYPE RGMII +#define PHY_ANEG_TIMEOUT 20000 + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif -/* Misc configuration */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#if defined(CONFIG_ANDROID_SUPPORT) +#include "imx8qxp_mek_android.h" +#elif defined (CONFIG_ANDROID_AUTO_SUPPORT) +#include "imx8qxp_mek_android_auto.h" +#endif #endif /* __IMX8QXP_MEK_H */ diff --git a/include/configs/imx8qxp_mek_android.h b/include/configs/imx8qxp_mek_android.h new file mode 100644 index 00000000000..9310e307e08 --- /dev/null +++ b/include/configs/imx8qxp_mek_android.h @@ -0,0 +1,44 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QXP_MEK_ANDROID_H +#define IMX8QXP_MEK_ANDROID_H + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define FSL_FASTBOOT_FB_DEV "mmc" + +#define CONFIG_FASTBOOT_USB_DEV 1 + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "splashimage=0x9e000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#ifdef CONFIG_IMX_TRUSTY_OS +#define AVB_RPMB +#define NS_ARCH_ARM64 1 +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF + +#ifdef CONFIG_ID_ATTESTATION +#define ATTESTATION_ID_BRAND "Android" +#define ATTESTATION_ID_DEVICE "mek_8q" +#define ATTESTATION_ID_MANUFACTURER "nxp" +#define ATTESTATION_ID_MODEL "MEK-MX8Q" +#ifdef CONFIG_ATTESTATION_ID_PRODUCT +#undef CONFIG_ATTESTATION_ID_PRODUCT +#endif +#define CONFIG_ATTESTATION_ID_PRODUCT "mek_8q" +#endif + +#endif + +#endif /* IMX8QXP_MEK_ANDROID_H */ diff --git a/include/configs/imx8qxp_mek_android_auto.h b/include/configs/imx8qxp_mek_android_auto.h new file mode 100644 index 00000000000..339464967d2 --- /dev/null +++ b/include/configs/imx8qxp_mek_android_auto.h @@ -0,0 +1,53 @@ +/* + * Copyright 2020 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMX8QXP_MEK_ANDROID_AUTO_H +#define IMX8QXP_MEK_ANDROID_AUTO_H + +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_SKIP_RESOURCE_CHECKING + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#ifndef CONFIG_MXC_USB_PORTSC +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif +#endif + +#define FSL_FASTBOOT_FB_DEV "mmc" + +#undef CONFIG_EXTRA_ENV_SETTINGS +#undef CONFIG_BOOTCOMMAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + +#ifdef CONFIG_IMX_TRUSTY_OS +#define NS_ARCH_ARM64 1 +#define AVB_RPMB +#define KEYSLOT_HWPARTITION_ID 2 +#define KEYSLOT_BLKS 0x3FFF + +#ifdef CONFIG_ID_ATTESTATION +#define ATTESTATION_ID_BRAND "Android" +#define ATTESTATION_ID_DEVICE "mek_8q" +#define ATTESTATION_ID_MANUFACTURER "nxp" +#define ATTESTATION_ID_MODEL "MEK-MX8Q" +#endif + +#endif + +#ifdef CONFIG_DUAL_BOOTLOADER +#define BOOTLOADER_RBIDX_OFFSET 0x3FE000 +#define BOOTLOADER_RBIDX_START 0x3FF000 +#define BOOTLOADER_RBIDX_LEN 0x08 +#define BOOTLOADER_RBIDX_INITVAL 0 +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x801F8000 +#endif + +#endif /* IMX8QXP_MEK_ANDROID_AUTO_H */ diff --git a/include/configs/imx8qxp_val.h b/include/configs/imx8qxp_val.h new file mode 100644 index 00000000000..3841bf5e610 --- /dev/null +++ b/include/configs/imx8qxp_val.h @@ -0,0 +1,306 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8QXP_VAL_H +#define __IMX8QXP_VAL_H + +#include +#include +#include + +#include "imx_env.h" + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_MAX_SIZE (192 * 1024) +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) + +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0x8000000) /*Put the FIT out of first 128MB boot area */ +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_IDENT + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +/* + * The memory layout on stack: DATA section save + gd + early malloc + * the idea is re-use the early malloc (CONFIG_SYS_MALLOC_F_LEN) with + * CONFIG_SYS_SPL_MALLOC_START + */ +#define CONFIG_SPL_STACK 0x013fff0 +#define CONFIG_SPL_BSS_START_ADDR 0x00130000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x82200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 +#define CONFIG_MALLOC_F_ADDR 0x00138000 + +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE + +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ + +#endif + +#define CONFIG_REMAKE_ELF + +#define CONFIG_CMD_READ + +/* Flat Device Tree Definitions */ +#define CONFIG_OF_BOARD_SETUP + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5B010000 +#define USDHC2_BASE_ADDR 0x5B020000 + +#define CONFIG_PCIE_IMX +#define CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_FEC_XCV_TYPE RGMII +#define PHY_ANEG_TIMEOUT 20000 + +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */ +#define CONFIG_ETHPRIME "eth0" + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x83100000\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=1\0" \ + +/* Initial environment variables */ +#ifdef CONFIG_NAND_BOOT +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "bootargs=console=ttyLP0,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0"\ + "console=ttyLP0,115200 earlycon\0" \ + "mtdparts=" MFG_NAND_PARTITION "\0" \ + "fdt_addr=0x83000000\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + AHAB_ENV \ + "script=boot.scr\0" \ + "image=Image\0" \ + "panel=NULL\0" \ + "console=ttyLP0\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "cntr_addr=0x98000000\0" \ + "cntr_file=os_cntr_signed.bin\0" \ + "boot_fdt=try\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} earlycon root=${mmcroot}\0 " \ + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ + "auth_os=auth_cntr ${cntr_addr}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${sec_boot} = yes; then " \ + "if run auth_os; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "echo wait for boot; " \ + "fi;" \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} earlycon " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if test ${sec_boot} = yes; then " \ + "${get_cmd} ${cntr_addr} ${cntr_file}; " \ + "if run auth_os; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo ERR: failed to authenticate; " \ + "fi; " \ + "else " \ + "${get_cmd} ${loadaddr} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "booti ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "else " \ + "booti; " \ + "fi;" \ + "fi;\0" +#endif + +#ifdef CONFIG_NAND_BOOT +#define CONFIG_BOOTCOMMAND \ + "nand read ${loadaddr} 0x9000000 0x2000000;"\ + "nand read ${fdt_addr} 0xB000000 0x100000;"\ + "booti ${loadaddr} - ${fdt_addr}" +#else +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if test ${sec_boot} = yes; then " \ + "if run loadcntr; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else booti ${loadaddr} - ${fdt_addr}; fi" +#endif + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x80280000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + + +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board + */ +#ifdef CONFIG_TARGET_IMX8X_17X17_VAL +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#if defined(CONFIG_TARGET_IMX8QXP_DDR3_VAL) || defined(CONFIG_TARGET_IMX8X_17X17_VAL) +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB totally */ +#define PHYS_SDRAM_2_SIZE 0x00000000 +#else +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ +/* LPDDR4 board total DDR is 3GB */ +#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ +#endif + +/* Serial */ +#define CONFIG_BAUDRATE 115200 + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_CMD_PCA953X +#define CONFIG_CMD_PCA953X_INFO +#endif + +#define CONFIG_SERIAL_TAG + +#ifdef CONFIG_NAND_MXS +#define CONFIG_CMD_NAND_TRIMFFS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +#endif + +/* USB Config */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USBD_HS + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_USB_FUNCTION_MASS_STORAGE +#endif + +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* USB OTG controller configs */ +#ifdef CONFIG_USB_EHCI_HCD +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#endif /* __IMX8QXP_VAL_H */ diff --git a/include/configs/imx_env.h b/include/configs/imx_env.h new file mode 100644 index 00000000000..7eed730d64d --- /dev/null +++ b/include/configs/imx_env.h @@ -0,0 +1,49 @@ +/* Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX_COMMON_CONFIG_H +#define __IMX_COMMON_CONFIG_H + +#ifdef CONFIG_ARM64 + #define MFG_BOOT_CMD "booti " +#else + #define MFG_BOOT_CMD "bootz " +#endif + +#ifdef CONFIG_USB_PORT_AUTO + #define FASTBOOT_CMD "echo \"Run fastboot ...\"; fastboot auto; " +#else + #define FASTBOOT_CMD "echo \"Run fastboot ...\"; fastboot 0; " +#endif + +/* define the nandfit partiton environment for uuu */ +#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MQ) || \ + defined(CONFIG_IMX8QM) || defined(CONFIG_IMX8QXP) || \ + defined(CONFIG_IMX8DXL) || defined(CONFIG_IMX8MN) || \ + defined(CONFIG_IMX8MP) +#define MFG_NAND_FIT_PARTITION "nandfit_part=yes\0" +#else +#define MFG_NAND_FIT_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "clk_ignore_unused "\ + "\0" \ + "kboot="MFG_BOOT_CMD"\0"\ + "bootcmd_mfg=run mfgtool_args;" \ + "if iminfo ${initrd_addr}; then " \ + "if test ${tee} = yes; then " \ + "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \ + "else " \ + MFG_BOOT_CMD "${loadaddr} ${initrd_addr} ${fdt_addr}; " \ + "fi; " \ + "else " \ + FASTBOOT_CMD \ + "fi;\0" \ + MFG_NAND_FIT_PARTITION \ + +#endif diff --git a/include/configs/iot-gate-imx8.h b/include/configs/iot-gate-imx8.h new file mode 100644 index 00000000000..b3d6082a667 --- /dev/null +++ b/include/configs/iot-gate-imx8.h @@ -0,0 +1,15 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __UCM_IMX8M_MINI_H +#define __UCM_IMX8M_MINI_H + +#include "cpl-imx8m-mini.h" + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "ucm-imx8m-mini_android.h" +#endif +#endif diff --git a/include/configs/iot-gate-imx8plus.h b/include/configs/iot-gate-imx8plus.h new file mode 100644 index 00000000000..32e86e64f03 --- /dev/null +++ b/include/configs/iot-gate-imx8plus.h @@ -0,0 +1,33 @@ +/* + * Copyright 2021 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IOT_GATE_IMX8PLUS_H +#define __IOT_GATE_IMX8PLUS_H + +#define MACHINE_EXTRA_ENV_SETTINGS \ + "boot_opt=net.ifnames=0\0" + +#include "compulab-imx8m-plus.h" + +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth0" /* Set eqos to primary since we use its MDIO */ + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR -1 +#define FEC_QUIRK_ENET_MAC + +#ifdef CONFIG_DWC_ETH_QOS +#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ +#define DWC_NET_PHYADDR -1 +#endif + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#endif diff --git a/include/configs/iotdin-imx8p.h b/include/configs/iotdin-imx8p.h new file mode 100644 index 00000000000..75e5e1c5626 --- /dev/null +++ b/include/configs/iotdin-imx8p.h @@ -0,0 +1,33 @@ +/* + * Copyright 2024 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IOTDIN_IMX8P_H +#define __IOTDIN_IMX8P_H + +#define MACHINE_EXTRA_ENV_SETTINGS \ + "boot_opt=net.ifnames=0\0" + +#include "compulab-imx8m-plus.h" + +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth0" /* Set eqos to primary since we use its MDIO */ + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR -1 +#define FEC_QUIRK_ENET_MAC + +#ifdef CONFIG_DWC_ETH_QOS +#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ +#define DWC_NET_PHYADDR -1 +#endif + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#endif diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 9f2b8999cdb..959adfc35eb 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP */ #ifndef __LX2_COMMON_H @@ -103,7 +103,14 @@ /* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ +#define I2C_MUX_PCA_ADDR_SEC 0x75 /* Secondary Mux*/ #define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_SEC 0xF + +/* QSFP+/SFP+ I2C MUX related */ +#define I2C_MUX_CH_QSFP 0x8 +#define I2C_MUX_CH_SFP1 0xC +#define I2C_MUX_CH_SFP2 0xD /* RTC */ #define RTC @@ -118,6 +125,10 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 +/* QSFP/SFP module EEPROMs */ +#define I2C_SFP_EEPROM_ADDR 0x50 +#define I2C_SFP_EEPROM_ADDR_LEN 1 + /* Qixis */ #define CONFIG_FSL_QIXIS #define CONFIG_QIXIS_I2C_ACCESS @@ -164,6 +175,8 @@ #ifndef __ASSEMBLY__ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); +int select_i2c_ch_pca9547(unsigned char ch); +int select_i2c_ch_pca9547_sec(unsigned char ch); #endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index ea1b1635fe9..748cfd26397 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018-2020 NXP + * Copyright 2018-2021 NXP */ #ifndef __LX2_QDS_H @@ -31,6 +31,16 @@ u8 qixis_esdhc_detect_quirk(void); #if defined(CONFIG_FSL_MC_ENET) #define CONFIG_MII #define CONFIG_ETHPRIME "DPMAC17@rgmii-id" + +#define INPHI_PHY_ADDR1 0x0 +#define INPHI_PHY_ADDR2 0x1 +#ifdef CONFIG_SD_BOOT +#define IN112525_FW_ADDR 0x980000 +#else +#define IN112525_FW_ADDR 0x20980000 +#endif +#define IN112525_FW_LENGTH 0x40000 + #endif /* EEPROM */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 097f1224c90..8a90f8f3eb2 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018,2020 NXP + * Copyright 2018-2021 NXP */ #ifndef __LX2_RDB_H @@ -21,6 +21,20 @@ #if defined(CONFIG_FSL_MC_ENET) #define CONFIG_MII #define CONFIG_ETHPRIME "DPMAC1@xgmii" +#define AQR113C_PHY_ADDR1 0x0 +#define AQR113C_PHY_ADDR2 0x08 + +#define INPHI_PHY_ADDR1 0x0 +#ifdef CONFIG_SD_BOOT +#define IN112525_FW_ADDR 0x980000 +#else +#define IN112525_FW_ADDR 0x20980000 +#endif +#define IN112525_FW_LENGTH 0x40000 + +#define RGMII_PHY_ADDR1 0x01 +#define RGMII_PHY_ADDR2 0x02 + #endif /* EMC2305 */ diff --git a/include/configs/mcm-imx8m-mini.h b/include/configs/mcm-imx8m-mini.h new file mode 100644 index 00000000000..602091a7825 --- /dev/null +++ b/include/configs/mcm-imx8m-mini.h @@ -0,0 +1,15 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MCM_IMX8M_MINI_H +#define __MCM_IMX8M_MINI_H + +#include "cpl-imx8m-mini.h" + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mcm-imx8m-mini_android.h" +#endif +#endif diff --git a/include/configs/mcm-imx8m-plus.h b/include/configs/mcm-imx8m-plus.h new file mode 100644 index 00000000000..f45c239ff37 --- /dev/null +++ b/include/configs/mcm-imx8m-plus.h @@ -0,0 +1,33 @@ +/* + * Copyright 2021 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MCM_IMX8M_PLUS_H +#define __MCM_IMX8M_PLUS_H + +#include "compulab-imx8m-plus.h" + +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth1" /* Set eqos to primary since we use its MDIO */ + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR -1 +#define FEC_QUIRK_ENET_MAC + +#ifdef CONFIG_DWC_ETH_QOS +#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ +#define DWC_NET_PHYADDR -1 +#endif + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mcm-imx8m-plus_android.h" +#endif +#endif diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 83895ab9d0e..339f2d99aee 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* + * Copyright (C) 2012-2016 Freescale Semiconductor, Inc. * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright 2018 NXP */ #ifndef __MX6_COMMON_H @@ -43,20 +45,30 @@ #if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ defined(CONFIG_MX6SX) || \ defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#define CONFIG_LOADADDR 0x82000000 +#define CONFIG_LOADADDR 0x80800000 #else #define CONFIG_LOADADDR 0x12000000 #endif #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* NET PHY */ +#define PHY_ANEG_TIMEOUT 20000 /* MMC */ +#define CONFIG_SUPPORT_EMMC_BOOT #ifdef CONFIG_SPL_BUILD #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #endif +#ifdef CONFIG_IMX_OPTEE +#define TEE_ENV "tee=yes\0" +#else +#define TEE_ENV "tee=no\0" +#endif #endif diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h index 83c09ead271..239f368c9f1 100644 --- a/include/configs/mx6qarm2.h +++ b/include/configs/mx6qarm2.h @@ -10,6 +10,8 @@ #include "mx6_common.h" +#define CONFIG_IMX_THERMAL + /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) @@ -24,19 +26,23 @@ #define CONFIG_FEC_XCV_TYPE RGMII #define CONFIG_FEC_MXC_PHYADDR 0 +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc3\0" \ - "fdt_file=imx6q-arm2.dtb\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdt_addr=0x18000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=1\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ @@ -103,6 +109,10 @@ /* Miscellaneous configurable options */ /* Physical Memory Map */ +#if defined(CONFIG_MX6DQ_POP_LPDDR2) +#define PHYS_SDRAM_0 MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_1 MMDC1_ARB_BASE_ADDR +#endif #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM @@ -115,6 +125,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* Environment organization */ +#define CONFIG_MMCROOT "/dev/mmcblk3p2" /* SDHC4 */ /* USB Configs */ #ifdef CONFIG_CMD_USB diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index ac579f3338a..bbf21b7675a 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Configuration settings for the Freescale i.MX6Q SabreSD board. */ @@ -9,15 +10,50 @@ #define __MX6QSABRE_COMMON_CONFIG_H #include - #include "mx6_common.h" +#include "imx_env.h" /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "eth0" + +#define CONFIG_PHY_ATHEROS + +#ifdef CONFIG_MX6S +#define SYS_NOSMP "nosmp" +#else +#define SYS_NOSMP +#endif + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=8000000.nor:1m(boot),-(rootfs)\\;gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)" +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x12C00000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=3\0"\ + "sd_dev=2\0" \ + "weim_uboot=0x08001000\0"\ + "weim_base=0x08000000\0"\ + "spi_bus=0\0"\ + "spi_uboot=0x400\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ + #ifdef CONFIG_SUPPORT_EMMC_BOOT #define EMMC_ENV \ "emmcdev=2\0" \ @@ -38,11 +74,112 @@ #define EMMC_ENV "" #endif +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#if defined(CONFIG_NAND_BOOT) + /* + * The dts also enables the WEIN NOR which is mtd0. + * So the partions' layout for NAND is: + * mtd1: 16M (uboot) + * mtd2: 16M (kernel) + * mtd3: 16M (dtb) + * mtd4: left (rootfs) + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "fdt_addr=0x18000000\0" \ + "tee_addr=0x20000000\0" \ + "fdt_high=0xffffffff\0" \ + "splashimage=0x28000000\0" \ + "console=" CONSOLE_DEV "\0" \ + "bootargs=console=" CONSOLE_DEV ",115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x4000000 0x400000;"\ + "bootm ${tee_addr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#elif defined(CONFIG_SATA_BOOT) + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "image=zImage\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x18000000\0" \ + "fdt_high=0xffffffff\0" \ + "splashimage=0x28000000\0" \ + "tee_addr=0x20000000\0" \ + "tee_file=undefined\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ + "setenv fdt_file imx6qp-sabreauto.dtb; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ + "setenv fdt_file imx6q-sabreauto.dtb; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ + "setenv fdt_file imx6dl-sabreauto.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ + "setenv fdt_file imx6qp-sabresd.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ + "setenv fdt_file imx6q-sabresd.dtb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ + "setenv fdt_file imx6dl-sabresd.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ + "fi;\0" \ + "findtee="\ + "if test $tee_file = undefined; then " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ + "setenv tee_file uTee-6qpauto; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ + "setenv tee_file uTee-6qauto; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ + "setenv tee_file uTee-6dlauto; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ + "setenv tee_file uTee-6qpsdb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ + "setenv tee_file uTee-6qsdb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ + "setenv tee_file uTee-6dlsdb; fi; " \ + "if test $tee_file = undefined; then " \ + "echo WARNING: Could not determine tee to use; fi; " \ + "fi;\0" \ + "bootargs=console=" CONSOLE_DEV ",115200 \0"\ + "bootargs_sata=setenv bootargs ${bootargs} " \ + "root=/dev/sda2 rootwait rw \0" \ + "bootcmd_sata=run bootargs_sata; scsi scan; " \ + "run findfdt; run findtee;" \ + "fatload scsi 0:1 ${loadaddr} ${image}; " \ + "fatload scsi 0:1 ${fdt_addr} ${fdt_file}; " \ + "if test ${tee} = yes; then " \ + "fatload scsi 0:1 ${tee_addr} ${tee_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "fi \0"\ + "bootcmd=run bootcmd_sata \0" + +#else + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ "image=zImage\0" \ - "fdtfile=undefined\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x18000000\0" \ + "tee_addr=0x20000000\0" \ + "tee_file=undefined\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "console=" CONSOLE_DEV "\0" \ @@ -52,10 +189,12 @@ "dfu_alt_info=spl raw 0x400\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ + "splashimage=0x28000000\0" \ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "update_sd_firmware=" \ "if test ${ip_dyn} = yes; then " \ "setenv get_cmd dhcp; " \ @@ -70,8 +209,9 @@ "fi; " \ "fi\0" \ EMMC_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ + "smp=" SYS_NOSMP "\0"\ + "mmcargs=setenv bootargs console=${console},${baudrate} ${smp} " \ + "root=${mmcroot}\0" \ "loadbootscript=" \ "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \ "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \ @@ -79,25 +219,30 @@ "source\0" \ "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \ "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \ - "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} || " \ + "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdt_file}\0" \ + "loadtee=load mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file} || " \ + "load mmc ${mmcdev}:${mmcpart} ${tee_addr} boot/${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ + "else " \ + "bootz; " \ + "fi;" \ "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ + "netargs=setenv bootargs console=${console},${baudrate} ${smp} " \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ @@ -108,39 +253,63 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "findfdt="\ - "if test $fdtfile = undefined; then " \ + "if test $fdt_file = undefined; then " \ "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabreauto.dtb; fi; " \ + "setenv fdt_file imx6qp-sabreauto.dtb; fi; " \ "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabreauto.dtb; fi; " \ + "setenv fdt_file imx6q-sabreauto.dtb; fi; " \ "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabreauto.dtb; fi; " \ + "setenv fdt_file imx6dl-sabreauto.dtb; fi; " \ "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabresd.dtb; fi; " \ + "setenv fdt_file imx6qp-sabresd.dtb; fi; " \ "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabresd.dtb; fi; " \ + "setenv fdt_file imx6q-sabresd.dtb; fi; " \ "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabresd.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ + "setenv fdt_file imx6dl-sabresd.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ "echo WARNING: Could not determine dtb to use; fi; " \ "fi;\0" \ + "findtee="\ + "if test $tee_file = undefined; then " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ + "setenv tee_file uTee-6qpauto; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ + "setenv tee_file uTee-6qauto; fi; " \ + "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ + "setenv tee_file uTee-6dlauto; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ + "setenv tee_file uTee-6qpsdb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ + "setenv tee_file uTee-6qsdb; fi; " \ + "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ + "setenv tee_file uTee-6dlsdb; fi; " \ + "if test $tee_file = undefined; then " \ + "echo WARNING: Could not determine tee to use; fi; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "run findfdt;" \ + "run findtee;" \ "mmc dev ${mmcdev};" \ "if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -152,6 +321,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif #define CONFIG_ARP_TIMEOUT 200UL @@ -167,14 +337,72 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Environment organization */ +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#endif + +#ifdef CONFIG_NAND_MXS + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif + +#if defined(CONFIG_ENV_IS_IN_MMC) +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#elif defined(CONFIG_ENV_IS_IN_FLASH) +#elif defined(CONFIG_ENV_IS_IN_NAND) +#elif defined(CONFIG_ENV_IS_IN_SATA) +#define CONFIG_SYS_SATA_ENV_DEV 0 +#endif + +/* I2C Configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif /* Framebuffer */ +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#if defined(CONFIG_ANDROID_SUPPORT) +#include "mx6sabreandroid_common.h" +#else #define CONFIG_USBD_HS +#endif /* CONFIG_ANDROID_SUPPORT */ #endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 11896777182..a156e48dea8 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Configuration settings for the Freescale i.MX6Q SabreAuto board. */ @@ -15,17 +16,31 @@ #define CONFIG_MACH_TYPE 3529 #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ +#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) +#ifdef CONFIG_MX6S +#undef PHYS_SDRAM_SIZE +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#endif + +#include "mx6sabre_common.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC3 */ +/*Since the pin conflicts on EIM D18, disable the USB host if the NOR flash is enabled */ +#ifdef CONFIG_USB /* USB Configs */ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0 +#if !defined(CONFIG_DM_PCA953X) && defined(CONFIG_SYS_I2C) #define CONFIG_PCA953X #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } - -#include "mx6sabre_common.h" +#endif +#endif /* Falcon Mode */ #ifdef CONFIG_SPL_OS_BOOT @@ -39,37 +54,4 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ #endif -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#endif - -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - #endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index e8f52cee202..f2fd459ef8f 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * Configuration settings for the Freescale i.MX6Q SabreSD board. */ @@ -15,6 +16,15 @@ #define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONSOLE_DEV "ttymxc0" +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* SDHC3 */ + +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QP) +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#elif defined(CONFIG_MX6DL) +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) +#elif defined(CONFIG_MX6S) +#define PHYS_SDRAM_SIZE (512u * 1024 * 1024) +#endif #include "mx6sabre_common.h" @@ -30,26 +40,25 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 +/* + * imx6 q/dl/solo pcie would be failed to work properly in kernel, if + * the pcie module is iniialized/enumerated both in uboot and linux + * kernel. + * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism. + * it is only be RESET by the POR. So, the pcie module only be + * initialized/enumerated once in one POR. + * Set to use pcie in kernel defaultly, mask the pcie config here. + * Remove the mask freely, if the uboot pcie functions, rather than + * the kernel's, are required. + */ #ifdef CONFIG_CMD_PCI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCIE_IMX +#ifndef CONFIG_DM_PCI #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) #endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif /* USB Configs */ #ifdef CONFIG_CMD_USB @@ -59,4 +68,22 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ #endif +/*#define CONFIG_SPLASH_SCREEN*/ +/*#define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC) + /* + * Framebuffer and LCD + */ + #undef LCD_TEST_PATTERN + /* #define CONFIG_SPLASH_IS_IN_MMC 1 */ + #define LCD_BPP LCD_MONOCHROME + /* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + + #define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */ + #endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index ab32f4e151e..4c048759535 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -9,6 +9,7 @@ #define __CONFIG_H #include "mx6_common.h" +#include "imx_env.h" #ifdef CONFIG_SPL #include "imx6_spl.h" @@ -17,7 +18,7 @@ #define CONFIG_MACH_TYPE MACH_TYPE_MX6SL_EVK /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR @@ -25,48 +26,87 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* I2C Configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=1\0" \ + "spi_bus=1\0"\ + "spi_uboot=0x400\0" #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sl-evk.dtb\0" \ - "fdt_addr=0x88000000\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-6slevk\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=1\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "finduuid=part uuid mmc 1:2 uuid\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ + "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -79,21 +119,32 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" + "else " \ + "bootz; " \ + "fi;" \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file imx6sl-evk.dtb; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -120,8 +171,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Environment organization */ - /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -130,6 +179,20 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 3 +/* + * SPLASH SCREEN Configs + */ +#ifdef CONFIG_MXC_EPDC + /* + * Framebuffer and LCD + */ + #undef LCD_TEST_PATTERN + #define LCD_BPP LCD_MONOCHROME + + #define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif /* CONFIG_SPLASH_SCREEN */ + #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sll_val.h b/include/configs/mx6sll_val.h new file mode 100644 index 00000000000..ba79e3a5b1e --- /dev/null +++ b/include/configs/mx6sll_val.h @@ -0,0 +1,200 @@ +/* + * Copyright 2013-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SL EVK board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CONFIG_SYS_FSL_USDHC_NUM 3 + +/* I2C Configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + "\0" \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "epdc_waveform=epdc_splash.bin\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=1\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "usb start; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#ifdef CONFIG_LPDDR2_BOARD +#define PHYS_SDRAM_SIZE SZ_1G +#else +#define PHYS_SDRAM_SIZE SZ_2G +#endif + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#define CONFIG_IOMUX_LPSR + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + + +/*#define CONFIG_MXC_EPDC 1*/ + +/* + * EPDC SPLASH SCREEN Configs + */ +#ifdef CONFIG_MXC_EPDC + /* + * Framebuffer and LCD + */ + #define CONFIG_SPLASH_SCREEN + #define CONFIG_CMD_BMP + #undef LCD_TEST_PATTERN + #define LCD_BPP LCD_MONOCHROME + + #define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif /* CONFIG_MXC_EPDC */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index a38ce4d0977..7ec1ea8e78c 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -8,7 +8,13 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include #include "mx6_common.h" +#include "imx_env.h" + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) @@ -24,17 +30,29 @@ #define CONFIG_SYS_I2C_SPEED 100000 #endif +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=1\0"\ + "sd_dev=0\0" \ + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "epdc_waveform=epdc_splash.bin\0" \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sll-evk.dtb\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-6sllevk\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ + "splashimage=0x8c000000\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ @@ -47,20 +65,25 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -74,21 +97,32 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" + "else " \ + "bootz; " \ + "fi;" \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file imx6sll-evk.dtb; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -130,5 +164,26 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif -#include +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LINK +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + +/* + * EPDC SPLASH SCREEN Configs + */ +#ifdef CONFIG_MXC_EPDC + /* + * Framebuffer and LCD + */ + #undef LCD_TEST_PATTERN + #define LCD_BPP LCD_MONOCHROME + + #define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif /* CONFIG_MXC_EPDC */ + #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sx_17x17_val.h b/include/configs/mx6sx_17x17_val.h new file mode 100644 index 00000000000..d9ab9290446 --- /dev/null +++ b/include/configs/mx6sx_17x17_val.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX 17x17 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_17X17_VAL_CONFIG_H +#define __MX6SX_17X17_VAL_CONFIG_H + +#include "mx6sx_val.h" + +#ifdef CONFIG_MXC_SPI /* Pin conflict between SPI-NOR and SD2 */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ +#else +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 2 /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ +#endif + +#ifdef CONFIG_MXC_SPI +#undef CONFIG_SYS_FLASH_SECT_SIZE +#undef CONFIG_SYS_MAX_FLASH_SECT +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024) +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_PROTECTION +#endif + +#endif diff --git a/include/configs/mx6sx_19x19_val.h b/include/configs/mx6sx_19x19_val.h new file mode 100644 index 00000000000..7d2b820ad0d --- /dev/null +++ b/include/configs/mx6sx_19x19_val.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX 19x19 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_19X19_VAL_CONFIG_H +#define __MX6SX_19X19_VAL_CONFIG_H + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_GIS +#endif + +#include "mx6sx_val.h" + +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#endif diff --git a/include/configs/mx6sx_val.h b/include/configs/mx6sx_val.h new file mode 100644 index 00000000000..b3416bc7751 --- /dev/null +++ b/include/configs/mx6sx_val.h @@ -0,0 +1,275 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6SX VAL board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX6SX_VAL_CONFIG_H +#define __MX6SX_VAL_CONFIG_H + +#include "mx6_common.h" + +#define CONFIG_DBG_MONITOR + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_FEC_MXC +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_PHY_ATHEROS + +/* I2C configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif + +#ifdef CONFIG_IMX_BOOTAUX +#ifdef CONFIG_DM_SPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 /* Set to QSPI2 B flash at default */ +#define SF_QSPI2_B_CS_NUM 2 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000 /* Set to QSPI2 B flash at default */ +#define SF_QSPI2_B_CS_NUM 1 +#endif + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 1:${m4_qspi_cs}; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "\0" \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=Hannstar-XGA\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + UPDATE_M4_ENV \ + "panel=Hannstar-XGA\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define PHYS_SDRAM_SIZE SZ_1G + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_NOR_BOOT +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +#ifdef CONFIG_NAND_MXS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif + + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SYS_CONSOLE_BG_COL 0x00 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0 +#ifdef CONFIG_VIDEO_GIS +#define CONFIG_VIDEO_CSI +#define CONFIG_VIDEO_PXP +#define CONFIG_VIDEO_VADC +#endif +#endif + + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#ifndef CONFIG_DM_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_FLAGS 0 +/*Only enable OTG1, the OTG2 has pin conflicts with PWM and WDOG*/ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 58cc3f0ee2b..6ae3c52e3fb 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -9,25 +9,104 @@ #define __CONFIG_H #include "mx6_common.h" +#include "imx_env.h" + +#define CONFIG_DBG_MONITOR /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) #define CONFIG_MXC_UART_BASE UART1_BASE +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)" +#else +#define MFG_NAND_PARTITION "" +#endif + +#ifdef CONFIG_IMX_BOOTAUX + +/* Set to QSPI1 B flash at default */ +#ifdef CONFIG_DM_SPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000 +#define SF_QSPI1_B_CS_NUM 2 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x62000000 +#define SF_QSPI1_B_CS_NUM 1 +#endif + + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:${m4_qspi_cs}; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 0:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "sd_dev=2\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "tee_addr=0x84000000\0" \ + "panel=Hannstar-XGA\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x6000000 0x400000;"\ + "bootm ${tee_addr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#else #define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sx-sabreauto.dtb\0" \ - "fdt_addr=0x88000000\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-6sxauto\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=0\0" \ + "panel=Hannstar-XGA\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ @@ -36,20 +115,25 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -62,22 +146,32 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" + "else " \ + "bootz; " \ + "fi;" \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file imx6sx-sabreauto.dtb; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ + "run findfdt;" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ @@ -88,6 +182,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif /* Miscellaneous configurable options */ @@ -118,18 +213,15 @@ #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT /* DMA stuff, needed for GPMI/MXS NAND support */ /* Network */ - -#define CONFIG_FEC_MXC - -#define IMX_FEC_BASE ENET2_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 - +#define CONFIG_ETHPRIME "eth1" #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_SERIAL_TAG #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -139,5 +231,39 @@ #endif #define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_MMCROOT "/dev/mmcblk2p2" /* USDHC3 */ +#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC3*/ + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#ifndef CONFIG_DM_PCA953X +#define CONFIG_PCA953X +#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_GIS +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_CMD_BMP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SYS_CONSOLE_BG_COL 0x00 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0 +#ifdef CONFIG_VIDEO_GIS +#define CONFIG_VIDEO_CSI +#define CONFIG_VIDEO_PXP +#define CONFIG_VIDEO_VADC +#endif +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 036881f6ea3..3060efe3e38 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP * * Configuration settings for the Freescale i.MX6SX Sabresd board. */ @@ -11,25 +12,44 @@ #include #include "mx6_common.h" +#include "imx_env.h" + +#define CONFIG_DBG_MONITOR #ifdef CONFIG_SPL #include "imx6_spl.h" #endif /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) #define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + #ifdef CONFIG_IMX_BOOTAUX /* Set to QSPI2 B flash at default */ +#ifdef CONFIG_DM_SPI #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 +#define SF_QSPI2_B_CS_NUM 2 +#elif defined(CONFIG_MX6SX_SABRESD_REVA) +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x71000000 +#define SF_QSPI2_B_CS_NUM 1 +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x72000000 +#define SF_QSPI2_B_CS_NUM 1 +#endif +/* When using M4 fastup demo, no need these M4 env, since QSPI is used by M4 */ +#ifndef CONFIG_SYS_AUXCORE_FASTUP #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI2_B_CS_NUM)"\0" \ "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ "update_m4_from_sd=" \ - "if sf probe 1:0; then " \ + "if sf probe 1:${m4_qspi_cs}; then " \ "if run loadm4image; then " \ "setexpr fw_sz ${filesize} + 0xffff; " \ "setexpr fw_sz ${fw_sz} / 0x10000; " \ @@ -38,49 +58,69 @@ "sf write ${loadaddr} 0x0 ${filesize}; " \ "fi; " \ "fi\0" \ - "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" + "m4boot=sf probe 1:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" #else #define UPDATE_M4_ENV "" -#endif +#endif /* CONFIG_SYS_AUXCORE_FASTUP */ + +#else +#define UPDATE_M4_ENV "" +#endif /* CONFIG_IMX_BOOTAUX */ + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=3\0"\ + "sd_dev=3\0" \ #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ UPDATE_M4_ENV \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sx-sdb.dtb\0" \ - "fdt_addr=0x88000000\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=uTee-6sxsdb\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ - "mmcdev=3\0" \ + "panel=Hannstar-XGA\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ + "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -93,22 +133,29 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ + "else " \ + "bootz; " \ + "fi;" \ "fi;\0" \ "findfdt="\ - "if test test $board_rev = REVA ; then " \ - "setenv fdt_file imx6sx-sdb-reva.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file " CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "run findfdt; " \ @@ -138,23 +185,32 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* MMC Configuration */ + #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR /* I2C Configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 +#endif -/* Network */ -#define CONFIG_FEC_MXC - -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif +/* Network */ +#define CONFIG_ETHPRIME "eth0" #define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -166,19 +222,32 @@ #ifdef CONFIG_CMD_PCI #define CONFIG_PCI_SCAN_SHOW #define CONFIG_PCIE_IMX +#ifndef CONFIG_DM_PCI #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif +#endif #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_VIDEO #define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR +#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_SYS_CONSOLE_BG_COL 0x00 +#define CONFIG_SYS_CONSOLE_FG_COL 0xa0 +#endif #endif + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #endif #define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_MMCROOT "/dev/mmcblk3p2" /* USDHC4 */ +#define CONFIG_SYS_MMC_ENV_DEV 3 /*USDHC4*/ #endif /* __CONFIG_H */ diff --git a/include/configs/mx6ul_14x14_ddr3_val.h b/include/configs/mx6ul_14x14_ddr3_val.h new file mode 100644 index 00000000000..9aa8cd68a84 --- /dev/null +++ b/include/configs/mx6ul_14x14_ddr3_val.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_14X14_DDR3_VAL_CONFIG_H +#define __MX6UL_14X14_DDR3_VAL_CONFIG_H + + +#define BOOTARGS_CMA_SIZE "" + +#include "mx6ul_val.h" + +#define PHYS_SDRAM_SIZE SZ_1G + + +#ifdef CONFIG_DM_ETH +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "eth1" +#endif + +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + +#endif diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 7d36c1e4d90..014bcea6c4b 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. */ @@ -12,9 +13,23 @@ #include #include "mx6_common.h" #include +#include "imx_env.h" + +/* uncomment for BEE support, needs to enable CONFIG_CMD_FUSE */ +/* #define CONFIG_CMD_BEE */ #define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) +#ifdef CONFIG_TARGET_MX6UL_9X9_EVK +#define PHYS_SDRAM_SIZE SZ_256M +#define BOOTARGS_CMA_SIZE "cma=96M " +#else +#define PHYS_SDRAM_SIZE SZ_512M +#define BOOTARGS_CMA_SIZE "" +/* DCDC used on 14x14 EVK, no PMIC */ +#undef CONFIG_LDO_BYPASS_CHECK +#endif + /* SPL options */ #include "imx6_spl.h" @@ -46,7 +61,53 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)" +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=1\0"\ + "emmc_ack=1\0"\ + "sd_dev=1\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ + +#if defined(CONFIG_NAND_BOOT) #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "splashimage=0x8c000000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "tee_addr=0x84000000\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + BOOTARGS_CMA_SIZE \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x6000000 0x400000;"\ + "bootm ${tee_addr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ @@ -54,15 +115,17 @@ "initrd_high=0xffffffff\0" \ "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=undefined\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "splashimage=0x8c000000\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -70,22 +133,28 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ @@ -96,19 +165,34 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ + "findtee="\ + "if test $tee_file = undefined; then " \ + "if test $board_name = EVK && test $board_rev = 9X9; then " \ + "setenv tee_file uTee-6ul9x9evk; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv tee_file uTee-6ulevk; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine tee to use; fi; " \ + "fi;\0" \ "findfdt="\ "if test $fdt_file = undefined; then " \ "if test $board_name = EVK && test $board_rev = 9X9; then " \ @@ -116,11 +200,13 @@ "if test $board_name = EVK && test $board_rev = 14X14; then " \ "setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \ "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "run findfdt;" \ + "run findtee;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -132,6 +218,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif /* Miscellaneous configurable options */ @@ -151,8 +238,26 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* environment organization */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +/* NAND stuff */ +#ifdef CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + /* USB Configs */ #ifdef CONFIG_CMD_USB #define CONFIG_EHCI_HCD_INIT_AFTER_RESET @@ -161,28 +266,15 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 1 - -#if (CONFIG_FEC_ENET_DEV == 0) -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x2 #define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "eth0" -#elif (CONFIG_FEC_ENET_DEV == 1) -#define IMX_FEC_BASE ENET2_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_ETHPRIME "eth1" -#endif -#endif #ifndef CONFIG_SPL_BUILD #if defined(CONFIG_DM_VIDEO) #define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LINK #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR #endif #endif diff --git a/include/configs/mx6ul_14x14_lpddr2_val.h b/include/configs/mx6ul_14x14_lpddr2_val.h new file mode 100644 index 00000000000..3cda6a72fdb --- /dev/null +++ b/include/configs/mx6ul_14x14_lpddr2_val.h @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 LPDDR2 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_14X14_LPDDR2_VAL_CONFIG_H +#define __MX6UL_14X14_LPDDR2_VAL_CONFIG_H + +#ifdef CONFIG_MTD_NOR_FLASH +/* + * Conflicts with SD1/SD2/VIDEO/ENET + * ENET is keeped, since only RXER conflicts. + * If removed ENET, we can not boot kernel, since sd1/sd2 is disabled + * when support weimnor. + */ +#undef CONFIG_FSL_USDHC +#undef CONFIG_VIDEO +#endif + +#define BOOTARGS_CMA_SIZE "cma=96M " + +#include "mx6ul_val.h" + +#define PHYS_SDRAM_SIZE SZ_256M + + +#ifdef CONFIG_DM_ETH +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_FEC_ENET_DEV 1 /* The ENET1 has pin conflict with UART1 */ + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth1" +#endif + +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + +#endif diff --git a/include/configs/mx6ul_val.h b/include/configs/mx6ul_val.h new file mode 100644 index 00000000000..f218528159a --- /dev/null +++ b/include/configs/mx6ul_val.h @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL ARM2 common. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6UL_VAL_CONFIG_H +#define __MX6UL_VAL_CONFIG_H + + +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_BASE + +/* I2C configs */ +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 +#endif +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs) " +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ + "rdinit=/linuxrc " \ + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ + "g_mass_storage.file=/fat g_mass_storage.ro=1 " \ + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ + "g_mass_storage.iSerialNumber=\"\" "\ + MFG_NAND_PARTITION \ + "clk_ignore_unused "\ + "\0" \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=MCIMX28LCD\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=4 " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + BOOTARGS_CMA_SIZE \ + "mtdparts=gpmi-nand:64m(boot),16m(kernel),16m(dtb),1m(misc),-(rootfs)\0"\ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=MCIMX28LCD\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +/* Miscellaneous configurable options */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* NAND stuff */ +#ifdef CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif + + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#endif + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#else +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#endif + +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#endif + +#endif diff --git a/include/configs/mx6ull_ddr3_val.h b/include/configs/mx6ull_ddr3_val.h new file mode 100644 index 00000000000..b4edc44b7b8 --- /dev/null +++ b/include/configs/mx6ull_ddr3_val.h @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX6UL 14x14 DDR3 ARM2. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __MX6ULL_DDR3_VAL_CONFIG_H +#define __MX6ULL_DDR3_VAL_CONFIG_H + + +#define BOOTARGS_CMA_SIZE "" + +#include "mx6ul_val.h" + +#define CONFIG_IOMUX_LPSR + +#define PHYS_SDRAM_SIZE SZ_1G + +/* + * TSC pins conflict with I2C1 bus, so after TSC + * hardware rework, need to disable i2c1 bus, also + * need to disable PMIC and ldo bypass check. + */ +#ifdef CONFIG_MX6ULL_DDR3_VAL_TSC_REWORK +#undef CONFIG_LDO_BYPASS_CHECK +#undef CONFIG_SYS_I2C_MXC +#undef CONFIG_SYS_I2C +#undef CONFIG_CMD_I2C +#undef CONFIG_POWER_PFUZE100_I2C_ADDR +#undef CONFIG_POWER_PFUZE100 +#undef CONFIG_POWER_I2C +#undef CONFIG_POWER +#endif + +#ifdef CONFIG_DM_ETH +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_FEC_ENET_DEV 1 + +#if (CONFIG_FEC_ENET_DEV == 0) +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x1 +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "eth0" +#elif (CONFIG_FEC_ENET_DEV == 1) +#define IMX_FEC_BASE ENET2_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x2 +#define CONFIG_FEC_XCV_TYPE MII100 +#define CONFIG_ETHPRIME "eth1" +#endif + +#define CONFIG_FEC_MXC_MDIO_BASE ENET2_BASE_ADDR +#endif + + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ +#define CONFIG_SPLASH_SCREEN + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +#endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 23f6de9050c..6f53dc59ed0 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. */ @@ -13,8 +14,19 @@ #include #include "mx6_common.h" #include +#include "imx_env.h" -#define PHYS_SDRAM_SIZE SZ_512M +#define is_mx6ull_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6ULL_9X9_EVK) + +#ifdef CONFIG_TARGET_MX6ULL_9X9_EVK +#define PHYS_SDRAM_SIZE SZ_256M +#define BOOTARGS_CMA_SIZE "cma=96M " +#else +#define PHYS_SDRAM_SIZE SZ_512M +#define BOOTARGS_CMA_SIZE "" +/* DCDC used on 14x14 EVK, no PMIC */ +#undef CONFIG_LDO_BYPASS_CHECK +#endif /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) @@ -26,7 +38,7 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR /* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_SYS_USE_NAND +#ifdef CONFIG_NAND_MXS #define CONFIG_SYS_FSL_USDHC_NUM 1 #else #define CONFIG_SYS_FSL_USDHC_NUM 2 @@ -43,7 +55,53 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)" +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=1\0"\ + "emmc_ack=1\0"\ + "sd_dev=1\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "splashimage=0x8c000000\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "tee_addr=0x84000000\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:rootfs rootfstype=ubifs " \ + BOOTARGS_CMA_SIZE \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x6000000 0x400000;"\ + "bootm ${tee_addr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#else #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ @@ -51,14 +109,17 @@ "initrd_high=0xffffffff\0" \ "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "tee_file=undefined\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ + "splashimage=0x8c000000\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ "root=${mmcroot}\0" \ "loadbootscript=" \ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ @@ -66,35 +127,32 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ - "findfdt="\ - "if test $fdt_file = undefined; then " \ - "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ - "if test $board_name = EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ - "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; " \ - "fi; " \ - "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ + BOOTARGS_CMA_SIZE \ "root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ + "${usb_net_cmd}; " \ "run netargs; " \ "if test ${ip_dyn} = yes; then " \ "setenv get_cmd dhcp; " \ @@ -102,22 +160,53 @@ "setenv get_cmd tftp; " \ "fi; " \ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ + "if test $board_name = EVK && test $board_rev = 9X9; then " \ + "setenv fdt_file imx6ull-9x9-evk.dtb; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ + "if test $fdt_file = undefined; then " \ + "echo WARNING: Could not determine dtb to use; " \ + "fi; " \ + "fi;\0" \ + "findtee="\ + "if test $tee_file = undefined; then " \ + "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ + "setenv tee_file uTee-6ulzevk; fi; " \ + "if test $board_name = EVK && test $board_rev = 9X9; then " \ + "setenv tee_file uTee-6ullevk; fi; " \ + "if test $board_name = EVK && test $board_rev = 14X14; then " \ + "setenv tee_file uTee-6ullevk; fi; " \ + "if test $tee_file = undefined; then " \ + "echo WARNING: Could not determine tee to use; " \ + "fi; " \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "run findfdt;" \ + "run findtee;" \ "mmc dev ${mmcdev};" \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -129,6 +218,7 @@ "fi; " \ "fi; " \ "else run netboot; fi" +#endif /* Miscellaneous configurable options */ @@ -148,18 +238,48 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) /* environment organization */ +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_IOMUX_LPSR -#define CONFIG_SOFT_SPI +/* NAND stuff */ +#ifdef CONFIG_NAND_MXS +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 1 -#if (CONFIG_FEC_ENET_DEV == 0) -#define CONFIG_ETHPRIME "eth0" -#elif (CONFIG_FEC_ENET_DEV == 1) +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +/* USB Configs */ +#ifdef CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_ETHPRIME "eth1" + +#ifndef CONFIG_SPL_BUILD +#if defined(CONFIG_DM_VIDEO) +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LINK +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO #endif #endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h index bd779aecd7c..7922ae147b7 100644 --- a/include/configs/mx7_common.h +++ b/include/configs/mx7_common.h @@ -31,12 +31,14 @@ #define CONFIG_LOADADDR 0x80800000 /* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_MAXARGS 32 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* UART */ -/* MMC */ +/* NET PHY */ +#define PHY_ANEG_TIMEOUT 20000 #define CONFIG_ARMV7_SECURE_BASE 0x00900000 @@ -55,4 +57,10 @@ #endif #endif +#ifdef CONFIG_IMX_OPTEE +#define TEE_ENV "tee=yes\0" +#else +#define TEE_ENV "tee=no\0" +#endif + #endif diff --git a/include/configs/mx7d_12x12_ddr3_val.h b/include/configs/mx7d_12x12_ddr3_val.h new file mode 100644 index 00000000000..a1f43d1a4ee --- /dev/null +++ b/include/configs/mx7d_12x12_ddr3_val.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Configuration settings for the Freescale i.MX7D 12x12 DDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_12X12_DDR3_VAL_CONFIG_H +#define __MX7D_12X12_DDR3_VAL_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC3 */ + +#define PHYS_SDRAM_SIZE SZ_1G + + +#include "mx7d_val.h" + +#endif diff --git a/include/configs/mx7d_12x12_lpddr3_val.h b/include/configs/mx7d_12x12_lpddr3_val.h new file mode 100644 index 00000000000..76aee246817 --- /dev/null +++ b/include/configs/mx7d_12x12_lpddr3_val.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D 12x12 LPDDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_12X12_LPDDR3_VAL_CONFIG_H +#define __MX7D_12X12_LPDDR3_VAL_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#define PHYS_SDRAM_SIZE SZ_2G + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif +#define CONFIG_FEC_MXC_PHYADDR 1 + +#define CONFIG_PHY_ATHEROS + +/* ENET1 */ +#define IMX_FEC_BASE ENET_IPS_BASE_ADDR + +/* #define CONFIG_SPLASH_SCREEN*/ +/* #define CONFIG_MXC_EPDC*/ + +#include "mx7d_val.h" + +#endif diff --git a/include/configs/mx7d_19x19_ddr3_val.h b/include/configs/mx7d_19x19_ddr3_val.h new file mode 100644 index 00000000000..2ed95425d93 --- /dev/null +++ b/include/configs/mx7d_19x19_ddr3_val.h @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D 19x19 DDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_19X19_DDR3_VAL_CONFIG_H +#define __MX7D_19X19_DDR3_VAL_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +#define PHYS_SDRAM_SIZE SZ_1G + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHY_ATHEROS + +/* ENET2 */ +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR + +#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR + + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#endif + + +#include "mx7d_val.h" + +#endif diff --git a/include/configs/mx7d_19x19_lpddr3_val.h b/include/configs/mx7d_19x19_lpddr3_val.h new file mode 100644 index 00000000000..32b9e34a798 --- /dev/null +++ b/include/configs/mx7d_19x19_lpddr3_val.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D 19x19 LPDDR3 ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_19X19_LPDDR3_VAL_CONFIG_H +#define __MX7D_19X19_LPDDR3_VAL_CONFIG_H + +#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + +#ifdef CONFIG_TARGET_MX7D_19X19_LPDDR2_VAL +#define PHYS_SDRAM_SIZE SZ_512M +#else +#define PHYS_SDRAM_SIZE SZ_2G +#endif + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#ifdef CONFIG_DM_ETH +#define CONFIG_ETHPRIME "eth0" +#else +#define CONFIG_ETHPRIME "FEC" +#endif +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_PHY_ATHEROS + +/* ENET2 */ +#define IMX_FEC_BASE ENET2_IPS_BASE_ADDR + +#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR + +/* QSPI conflict with EIMNOR */ +/* FEC0 conflict with EIMNOR */ +/* ECSPI conflict with UART */ +#ifdef CONFIG_MTD_NOR_FLASH +#undef CONFIG_FEC_MXC +#endif + +#ifndef CONFIG_DM_I2C +#define CONFIG_SYS_I2C +#endif +#ifdef CONFIG_CMD_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#endif + +/* PMIC */ +#ifndef CONFIG_DM_PMIC +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE3000 +#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 +#endif + + +#include "mx7d_val.h" + +#endif diff --git a/include/configs/mx7d_val.h b/include/configs/mx7d_val.h new file mode 100644 index 00000000000..436f18478ed --- /dev/null +++ b/include/configs/mx7d_val.h @@ -0,0 +1,240 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * Configuration settings for the Freescale i.MX7D ARM2 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MX7D_VAL_CONFIG_H +#define __MX7D_VAL_CONFIG_H + +#include "mx7_common.h" +#include "imx_env.h" + + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) + +#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +/* I2C configs */ +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_LOADADDR 0x80800000 + +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x68000000 /* Set to QSPI1 B flash at default */ +#define SF_QSPI1_B_CS_NUM 2 +#define SF_QSPI1_B_BUS_NUM 0 + +#ifdef CONFIG_IMX_BOOTAUX + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "m4_qspi_cs="__stringify(SF_QSPI1_B_CS_NUM)"\0" \ + "m4_qspi_bus="__stringify(SF_QSPI1_B_BUS_NUM)"\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe ${m4_qspi_bus}:${m4_qspi_cs}; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe ${m4_qspi_bus}:${m4_qspi_cs}; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)" +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=2\0"\ + "sd_dev=0\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ + +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "panel=MCIMX28LCD\0" \ + "fdt_addr=0x83000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "bootz ${loadaddr} - ${fdt_addr}\0" + +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + UPDATE_M4_ENV \ + "epdc_waveform=epdc_splash.bin\0" \ + "panel=MCIMX28LCD\0" \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x83000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_MTD_NOR_FLASH +#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR +#define CONFIG_SYS_FLASH_SECT_SIZE (256 * 1024) +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/ +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_PROTECTION +#endif + +#ifdef CONFIG_NAND_MXS + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT + +/* DMA stuff, needed for GPMI/MXS NAND support */ +#endif + +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#ifdef CONFIG_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP +#endif + +#if defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#endif /* __CONFIG_H */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 5801da0cfac..577695bf4be 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015 Freescale Semiconductor, Inc. + * Copyright 2017-2018 NXP * * Configuration settings for the Freescale i.MX7D SABRESD board. */ @@ -9,6 +10,7 @@ #define __MX7D_SABRESD_CONFIG_H #include "mx7_common.h" +#include "imx_env.h" #define PHYS_SDRAM_SIZE SZ_1G @@ -20,6 +22,9 @@ /* MMC Config*/ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 +/* Default ETH port */ +#define CONFIG_ETHPRIME "eth0" + /* I2C configs */ #define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_SPEED 100000 @@ -27,9 +32,8 @@ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI1 A flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 +#ifdef CONFIG_FSL_QSPI #define UPDATE_M4_ENV \ "m4image=m4_qspi.bin\0" \ "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ @@ -39,26 +43,39 @@ "setexpr fw_sz ${filesize} + 0xffff; " \ "setexpr fw_sz ${fw_sz} / 0x10000; " \ "setexpr fw_sz ${fw_sz} * 0x10000; " \ - "sf erase 0x0 ${fw_sz}; " \ - "sf write ${loadaddr} 0x0 ${filesize}; " \ + "sf erase 0x100000 ${fw_sz}; " \ + "sf write ${loadaddr} 0x100000 ${filesize}; " \ "fi; " \ "fi\0" \ "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" #else +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)" ${m4image}\0" \ + "m4boot=run loadm4image; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#endif +#else #define UPDATE_M4_ENV "" #endif +#ifdef CONFIG_NAND_BOOT +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs)" +#else +#define MFG_NAND_PARTITION "" +#endif + +#define CONFIG_CMD_READ +#define CONFIG_SERIAL_TAG +#define CONFIG_FASTBOOT_USB_DEV 0 + #define CONFIG_MFG_ENV_SETTINGS \ - "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ - "rdinit=/linuxrc " \ - "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ - "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ - "g_mass_storage.iSerialNumber=\"\" "\ - "clk_ignore_unused "\ - "\0" \ - "initrd_addr=0x83800000\0" \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x86800000\0" \ "initrd_high=0xffffffff\0" \ - "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ + "emmc_dev=2\0"\ + "sd_dev=0\0" \ + "mtdparts=" MFG_NAND_PARTITION \ + "\0"\ #define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=image raw 0 0x800000;"\ @@ -66,33 +83,126 @@ "bootimg part 0 1;"\ "rootfs part 0 2\0" \ +#if defined(CONFIG_NAND_BOOT) +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ + "fdt_addr=0x83000000\0" \ + "tee_addr=0x84000000\0" \ + "fdt_high=0xffffffff\0" \ + "console=ttymxc0\0" \ + "bootargs=console=ttymxc0,115200 ubi.mtd=nandrootfs " \ + "root=ubi0:nandrootfs rootfstype=ubifs " \ + MFG_NAND_PARTITION \ + "\0" \ + "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\ + "nand read ${fdt_addr} 0x5000000 0x100000;"\ + "if test ${tee} = yes; then " \ + "nand read ${tee_addr} 0x6000000 0x400000;"\ + "bootm ${tee_addr} - ${fdt_addr};" \ + "else " \ + "bootz ${loadaddr} - ${fdt_addr};" \ + "fi\0" + +#else #define CONFIG_EXTRA_ENV_SETTINGS \ UPDATE_M4_ENV \ CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ CONFIG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ "fdt_high=0xffffffff\0" \ - "finduuid=part uuid mmc 0:1 uuid\0" \ "initrd_high=0xffffffff\0" \ - "fdtfile=imx7d-sdb.dtb\0" \ + "fdt_file=undefined\0" \ "fdt_addr=0x83000000\0" \ - "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x83100000\0" \ - "ramdiskaddr=0x83100000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) \ - func(PXE, pxe, na) - -#include + "tee_addr=0x84000000\0" \ + "tee_file=uTee-7dsdb\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "splashimage=0x8c000000\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi; " \ + "fi;\0" \ + "findfdt="\ + "if test $fdt_file = undefined; then " \ + "setenv fdt_file imx7d-sdb.dtb; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "run findfdt;" \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" +#endif #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_HZ 1000 @@ -111,16 +221,30 @@ /* environment organization */ +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#endif + +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60100000 /* Set to QSPI1 A flash, offset 1M */ +#else +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x7F8000 /* Set to TCML address */ +#endif /* - * If want to use nand, define CONFIG_NAND_MXS and rework board + * If want to use nand, define CONFIG_CMD_NAND and rework board * to support nand, since emmc has pin conflicts with nand */ #ifdef CONFIG_NAND_MXS + /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION +#define CONFIG_SYS_NAND_USE_FLASH_BBT /* DMA stuff, needed for GPMI/MXS NAND support */ #endif @@ -131,15 +255,39 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif +/* MMC Config*/ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ + /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USBD_HS - -#ifdef CONFIG_VIDEO +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_LINK #define CONFIG_VIDEO_MXS #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #endif +/* + * SPLASH SCREEN Configs + */ +#if defined(CONFIG_MXC_EPDC) +/* + * Framebuffer and LCD + */ + +#undef LCD_TEST_PATTERN +/* #define CONFIG_SPLASH_IS_IN_MMC 1 */ +#define LCD_BPP LCD_MONOCHROME +/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */ + +#define CONFIG_WAVEFORM_BUF_SIZE 0x400000 +#endif + +#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_FSL_QSPI) +#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!" +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 0c3103082cc..345dbe0fcb7 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -10,10 +10,13 @@ #include #include +#include "imx_env.h" #define CONFIG_BOARD_POSTCLK_INIT #define CONFIG_SYS_BOOTM_LEN 0x1000000 +#define CONFIG_SERIAL_TAG + #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 @@ -49,16 +52,28 @@ #define CONFIG_LOADADDR 0x60800000 +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x66800000\0" \ + "initrd_high=0xffffffff\0" \ + "emmc_dev=0\0" \ + "sd_dev=0\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + TEE_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttyLP0\0" \ + "splashimage=0x78000000\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ - "fdt_file=imx7ulp-evk.dtb\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE ".dtb\0" \ "fdt_addr=0x63000000\0" \ + "tee_addr=0x64000000\0" \ + "tee_file=uTee-7ulp\0" \ "boot_fdt=try\0" \ - "earlycon=lpuart32,0x402D0010\0" \ + "earlycon=lpuart32,0x402D0000\0" \ "ip_dyn=yes\0" \ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ @@ -72,20 +87,25 @@ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "loadtee=fatload mmc ${mmcdev}:${mmcpart} ${tee_addr} ${tee_file}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "run loadfdt; run loadtee; bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ "netargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/nfs " \ @@ -99,18 +119,24 @@ "fi; " \ "usb start; "\ "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ + "if test ${tee} = yes; then " \ + "${get_cmd} ${tee_addr} ${tee_file}; " \ + "${get_cmd} ${fdt_addr} ${fdt_file}; " \ + "bootm ${tee_addr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ "else " \ - "echo WARN: Cannot load the DT; " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ "fi; " \ + "else " \ + "bootz; " \ "fi; " \ - "else " \ - "bootz; " \ "fi;\0" \ #define CONFIG_BOOTCOMMAND \ @@ -120,6 +146,7 @@ "else " \ "if run loadimage; then " \ "run mmcboot; " \ + "else run netboot; " \ "fi; " \ "fi; " \ "fi" @@ -135,4 +162,23 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#ifdef CONFIG_IMX_OPTEE +#define TEE_ENV "tee=yes\0" +#else +#define TEE_ENV "tee=no\0" +#endif + +#ifdef CONFIG_DM_VIDEO +#define CONFIG_VIDEO_MXS +#define CONFIG_VIDEO_LOGO +#define CONFIG_BMP_16BPP +#define CONFIG_BMP_24BPP +#define CONFIG_BMP_32BPP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_val.h b/include/configs/mx7ulp_val.h new file mode 100644 index 00000000000..e1e16c36e36 --- /dev/null +++ b/include/configs/mx7ulp_val.h @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * Configuration settings for the Freescale i.MX7ULP Validationbbbb board. + */ + +#ifndef __MX7ULP_VAL_CONFIG_H +#define __MX7ULP_VAL_CONFIG_H + +#include +#include +#include "imx_env.h" + +#define CONFIG_BOARD_POSTCLK_INIT +#define CONFIG_SYS_BOOTM_LEN 0x1000000 + + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG1_RBASE + + +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ + +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +/*#define CONFIG_REVISION_TAG*/ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) + +/* UART */ +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL +#define LPUART_BASE LPUART6_RBASE +#else +#define LPUART_BASE LPUART4_RBASE +#endif + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 256 + +/* Physical Memory Map */ + +#define PHYS_SDRAM 0x60000000ul +#ifdef CONFIG_TARGET_MX7ULP_10X10_VAL +#define PHYS_SDRAM_SIZE SZ_1G /*LPDDR2 1G*/ +#else +#define PHYS_SDRAM_SIZE SZ_512M +#endif +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM + +#define CONFIG_LOADADDR 0x60800000 + +#define CONFIG_MFG_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS_DEFAULT \ + "initrd_addr=0x66800000\0" \ + "initrd_high=0xffffffff\0" \ + "sd_dev=1\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_MFG_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttyLP0\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x63000000\0" \ + "boot_fdt=try\0" \ + "earlycon=lpuart32,0x402D0000\0" \ + "ip_dyn=yes\0" \ + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* USB Configs */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) + +#endif /* __CONFIG_H */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index e0708fe5739..91f636b2c10 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -93,7 +93,9 @@ #endif #define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ + "eth2addr=00:00:11:22:33:48\0" \ "eth3addr=00:00:11:22:33:45\0" \ + "eth4addr=00:00:11:22:33:48\0" \ "eth5addr=00:00:11:22:33:46\0" \ "eth6addr=00:00:11:22:33:47\0" \ "ipaddr=1.2.3.4\0" diff --git a/include/configs/som-imx8m-plus.h b/include/configs/som-imx8m-plus.h new file mode 100644 index 00000000000..4a71b8bf9fd --- /dev/null +++ b/include/configs/som-imx8m-plus.h @@ -0,0 +1,29 @@ +/* + * Copyright 2021 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SOM_IMX8M_PLUS_H +#define __SOM_IMX8M_PLUS_H + +#include "compulab-imx8m-plus.h" + +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth0" + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR -1 +#define FEC_QUIRK_ENET_MAC + +#define DWC_NET_PHYADDR -1 +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "som-imx8m-plus_android.h" +#endif +#endif diff --git a/include/configs/ucm-imx8m-mini.h b/include/configs/ucm-imx8m-mini.h new file mode 100644 index 00000000000..b3d6082a667 --- /dev/null +++ b/include/configs/ucm-imx8m-mini.h @@ -0,0 +1,15 @@ +/* + * Copyright 2020 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __UCM_IMX8M_MINI_H +#define __UCM_IMX8M_MINI_H + +#include "cpl-imx8m-mini.h" + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "ucm-imx8m-mini_android.h" +#endif +#endif diff --git a/include/configs/ucm-imx8m-plus.h b/include/configs/ucm-imx8m-plus.h new file mode 100644 index 00000000000..fd7c996a508 --- /dev/null +++ b/include/configs/ucm-imx8m-plus.h @@ -0,0 +1,38 @@ +/* + * Copyright 2021 CompuLab + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __UCM_IMX8M_PLUS_H +#define __UCM_IMX8M_PLUS_H + +#include "compulab-imx8m-plus.h" + +#define CONFIG_IMX6_PWM_PER_CLK 66000000 + +#if defined(CONFIG_CMD_NET) +#define CONFIG_ETHPRIME "eth0" /* Set eqos to primary since we use its MDIO */ + +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR -1 +#define FEC_QUIRK_ENET_MAC + +#ifdef CONFIG_DWC_ETH_QOS +#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ +#define DWC_NET_PHYADDR -1 +#endif + +#define PHY_ANEG_TIMEOUT 20000 + +#endif + +#ifdef CONFIG_COMPULAB_DEBUG_UART1 +#undef CONFIG_MXC_UART_BASE +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR +#endif + +#if defined(CONFIG_ANDROID_SUPPORT) +#include "ucm-imx8m-plus_android.h" +#endif +#endif diff --git a/include/cortina_api.h b/include/cortina_api.h new file mode 100644 index 00000000000..ae90ae324d0 --- /dev/null +++ b/include/cortina_api.h @@ -0,0 +1,2822 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Cortina PHY drivers framework + * + * Copyright 2018-2021 NXP + * Copyright (C) 2006-2017 Inphi Corporation, Inc. All rights reserved. + */ + +#ifndef __CORTINA_API_H_ +#define __CORTINA_API_H_ + +#include +#include +#include +#include +#include +#include +#include + +/* endiannes */ +#define CS_LITTLE_ENDIAN + +/* Things that can be tweaked */ +#define CS_PRINTF(x) debug x +#define CS_FPRINTF(x) fprintf x +#define CS_FLUSH() fflush(stdout) +#define CS_SNPRINTF(x) snprintf x +#define CS_TRACE(x) debug x +#define CS_UDELAY(x) udelay((x)) +#define CS_MDELAY(x) udelay((x)*1000) + +/* Make sure endianess is defined */ +#ifdef CS_BIG_ENDIAN +# ifdef CS_LITTLE_ENDIAN +# error "CS_BIG_ENDIAN and CS_LITTLE_ENDIAN are both defined." +# endif +#else +# ifndef CS_LITTLE_ENDIAN +# error "Either CS_BIG_ENDIAN or CS_LITTLE_ENDIAN must be defined." +# endif +#endif + +/* Cortina/Inphi reference software version */ +#define CS_API_VERSION "3.10.0" +#define CS_API_BUILD_DATE "Apr 21, 2017 at 16:09:26" + +#define CS_API_VERSION_MAJOR 3 +#define CS_API_VERSION_MINOR 10 +#define CS_API_VERSION_UPDATE 0 + +#define CS_OK 0 +#define CS_ERROR -1 + +#define CS_TRUE 1 +#define CS_FALSE 0 + +#ifndef NULL +#define NULL 0 +#endif + +/* Chip family defines */ +#define CS4224_GLOBAL_CHIP_ID_LSB 0x0 +#define CS4224_GLOBAL_CHIP_ID_LSB_dft 0x3E5 +#define CS4224_GLOBAL_CHIP_ID_MSB 0x1 +#define CS4224_GLOBAL_CHIP_ID_MSB_dft 0x7003 +#define CS4224_GLOBAL_SCRATCH 0x2 +#define CS4224_GLOBAL_SCRATCH_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_SR 0x3 +#define CS4224_GLOBAL_UCODE_VERSION_SR_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_CX1 0x4 +#define CS4224_GLOBAL_UCODE_VERSION_CX1_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_KR 0x5 +#define CS4224_GLOBAL_UCODE_VERSION_KR_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_ZR 0x6 +#define CS4224_GLOBAL_UCODE_VERSION_ZR_dft 0x0 +#define CS4224_GLOBAL_UCODE_VERSION_FC 0x7 +#define CS4224_GLOBAL_UCODE_VERSION_FC_dft 0x0 +#define CS4224_GLOBAL_UCODE_TIMESTAMP0 0x8 +#define CS4224_GLOBAL_UCODE_TIMESTAMP0_dft 0x0 +#define CS4224_GLOBAL_UCODE_TIMESTAMP1 0x9 +#define CS4224_GLOBAL_UCODE_TIMESTAMP1_dft 0x0 +#define CS4224_GLOBAL_UCODE_TIMESTAMP2 0xA +#define CS4224_GLOBAL_UCODE_TIMESTAMP2_dft 0x0 +#define CS4224_GLOBAL_MPIF_SOFT_RESET 0xD +#define CS4224_GLOBAL_MPIF_SOFT_RESET_dft 0x0 +#define CS4224_GLOBAL_MDIO_CONFIG 0xF +#define CS4224_GLOBAL_MDIO_CONFIG_dft 0x50 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL 0x11 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_CTRL_dft 0x0 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS 0x12 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_STATUS_dft 0x0 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_HW 0x13 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_HW_dft 0xFFFF +#define CS4224_GLOBAL_DWNLD_CHECKSUM_SW 0x14 +#define CS4224_GLOBAL_DWNLD_CHECKSUM_SW_dft 0x0 +#define CS4224_GLOBAL_PIN_STATUS 0x16 +#define CS4224_GLOBAL_PIN_STATUS_dft 0x0 +#define CS4224_GLOBAL_BROADCAST 0x17 +#define CS4224_GLOBAL_BROADCAST_dft 0x0 +#define CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT1 0x18 +#define CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT1_dft 0x0 +#define CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT0 0x19 +#define CS4224_GLOBAL_GT_10KHZ_REF_CLK_CNT0_dft 0x3CF0 +#define CS4224_GLOBAL_SCRATCH0 0x1D +#define CS4224_GLOBAL_SCRATCH0_dft 0x0 +#define CS4224_GLOBAL_SCRATCH6 0x23 +#define CS4224_GLOBAL_SCRATCH6_dft 0x0 +#define CS4224_GLOBAL_SCRATCH7 0x24 +#define CS4224_GLOBAL_SCRATCH7_dft 0x0 +#define CS4224_GLOBAL_GLOBAL_INTERRUPT 0x26 +#define CS4224_GLOBAL_GLOBAL_INTERRUPT_dft 0x0 +#define CS4224_GLOBAL_GLOBAL_INTE 0x27 +#define CS4224_GLOBAL_GLOBAL_INTE_dft 0x0 +#define CS4224_GLOBAL_DATAPATH_INTERRUPT 0x28 +#define CS4224_GLOBAL_DATAPATH_INTERRUPT_dft 0x0 +#define CS4224_GLOBAL_DATAPATH_INTE 0x29 +#define CS4224_GLOBAL_DATAPATH_INTE_dft 0x0 +#define CS4224_GPIO_INTERR 0x100 +#define CS4224_GPIO_INTERR_dft 0x0 +#define CS4224_GPIO_GPIO1 0x106 +#define CS4224_GPIO_GPIO1_dft 0x0 +#define CS4224_GPIO_GPIO2 0x10C +#define CS4224_GPIO_GPIO2_dft 0x0 +#define CS4224_GPIO_GPIO3 0x112 +#define CS4224_GPIO_GPIO3_dft 0x0 +#define CS4224_GPIO_GPIO4 0x118 +#define CS4224_GPIO_GPIO4_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT0 0x11E +#define CS4224_GPIO_GPIO_INPUT0_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT_INT 0x124 +#define CS4224_GPIO_GPIO_INPUT_INT_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT_INTE 0x125 +#define CS4224_GPIO_GPIO_INPUT_INTE_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT_INTS 0x126 +#define CS4224_GPIO_GPIO_INPUT_INTS_dft 0x0 +#define CS4224_GPIO_GPIO_INPUT_INTZ 0x127 +#define CS4224_GPIO_GPIO_INPUT_INTZ_dft 0x0 +#define CS4224_EFUSE_GENERAL_STATUS 0x181 +#define CS4224_EFUSE_GENERAL_STATUS_dft 0x0 +#define CS4224_EFUSE_PDF_SKU 0x19F +#define CS4224_EFUSE_PDF_SKU_dft 0x0 +#define CS4224_EFUSE_PDF_MON_CAL_DATA 0x1A4 +#define CS4224_EFUSE_PDF_MON_CAL_DATA_dft 0x0 +#define CS4224_EFUSE_PDF_MON_GAIN_DATA 0x1A5 +#define CS4224_EFUSE_PDF_MON_GAIN_DATA_dft 0x0 +#define CS4224_EFUSE_PDF_MON_LUT15 0x1A6 +#define CS4224_EFUSE_PDF_MON_LUT15_dft 0x0 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA2 0x1B7 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA2_dft 0x0 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA1 0x1B8 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA1_dft 0x0 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA0 0x1B9 +#define CS4224_EFUSE_PDF_POLY_RES_CAL_DATA0_dft 0x0 +#define CS4224_MONITOR_CONTROL0 0x200 +#define CS4224_MONITOR_CONTROL0_dft 0x630C +#define CS4224_MONITOR_CONFIG_MASK 0x204 +#define CS4224_MONITOR_CONFIG_MASK_dft 0x0 +#define CS4224_MONITOR_LUT_SELECT 0x20B +#define CS4224_MONITOR_LUT_SELECT_dft 0x0 +#define CS4224_MONITOR_LUT_LOCAL_SELECT 0x20C +#define CS4224_MONITOR_LUT_LOCAL_SELECT_dft 0x0 +#define CS4224_MONITOR_LUT_APPLY 0x20D +#define CS4224_MONITOR_LUT_APPLY_dft 0x0 +#define CS4224_MONITOR_CAL_CONST_OVERRIDE_ENA 0x20E +#define CS4224_MONITOR_CAL_CONST_OVERRIDE_ENA_dft 0x0 +#define CS4224_MONITOR_CAL_OVERRIDE 0x20F +#define CS4224_MONITOR_CAL_OVERRIDE_dft 0x0 +#define CS4224_MONITOR_CAL_CONST_APPLY 0x210 +#define CS4224_MONITOR_CAL_CONST_APPLY_dft 0x0 +#define CS4224_MONITOR_STATUS_FINAL0 0x25A +#define CS4224_MONITOR_STATUS_FINAL0_dft 0x0 +#define CS4224_MONITOR_STATUS_FINAL2 0x25C +#define CS4224_MONITOR_STATUS_FINAL2_dft 0x0 +#define CS4224_MONITOR_STATUS_FINAL6 0x260 +#define CS4224_MONITOR_STATUS_FINAL6_dft 0x0 +#define CS4224_MONITOR_LUT_RANGE0 0x27B +#define CS4224_MONITOR_LUT_RANGE0_dft 0x0 +#define CS4224_MONITOR_LUT_VALUE0 0x28B +#define CS4224_MONITOR_LUT_VALUE0_dft 0x0 +#define CS4224_CLKMON_GBL_CLKSEL 0x2E0 +#define CS4224_CLKMON_GBL_CLKSEL_dft 0x7F +#define CS4224_CLKMON_GBL_CTRL 0x2E1 +#define CS4224_CLKMON_GBL_CTRL_dft 0x110 +#define CS4224_CLKMON_GBL_DURATION 0x2E2 +#define CS4224_CLKMON_GBL_DURATION_dft 0x0 +#define CS4224_CLKMON_GBL_MINTHRESH1 0x2E6 +#define CS4224_CLKMON_GBL_MINTHRESH1_dft 0x0 +#define CS4224_CLKMON_GBL_MINTHRESH0 0x2E7 +#define CS4224_CLKMON_GBL_MINTHRESH0_dft 0x0 +#define CS4224_CLKMON_GBL_MAXTHRESH1 0x2E8 +#define CS4224_CLKMON_GBL_MAXTHRESH1_dft 0x0 +#define CS4224_CLKMON_GBL_MAXTHRESH0 0x2E9 +#define CS4224_CLKMON_GBL_MAXTHRESH0_dft 0x0 +#define CS4224_MSEQ_PS_RAM_CONTROL 0x301 +#define CS4224_MSEQ_PS_RAM_CONTROL_dft 0x0 +#define CS4224_MSEQ_PS_RAM_DATA1 0x302 +#define CS4224_MSEQ_PS_RAM_DATA1_dft 0x0 +#define CS4224_MSEQ_PS_RAM_DATA0 0x303 +#define CS4224_MSEQ_PS_RAM_DATA0_dft 0x0 +#define CS4224_MSEQ_PS_INT 0x306 +#define CS4224_MSEQ_PS_INT_dft 0x0 +#define CS4224_MSEQ_PS_INTE 0x307 +#define CS4224_MSEQ_PS_INTE_dft 0x0 +#define CS4224_MSEQ_PS_INTO 0x308 +#define CS4224_MSEQ_PS_INTO_dft 0x0 +#define CS4224_MSEQ_PS_INTZ 0x309 +#define CS4224_MSEQ_PS_INTZ_dft 0x0 +#define CS4224_MSEQ_PS_MBIST_CTRL 0x30A +#define CS4224_MSEQ_PS_MBIST_CTRL_dft 0x0 +#define CS4224_MSEQ_PS_MBIST_STATUS 0x30B +#define CS4224_MSEQ_PS_MBIST_STATUS_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_SOFT_RESET 0x1000 +#define CS4224_PP_LINE_LINEMISC_SOFT_RESET_dft 0x2 +#define CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG 0x1001 +#define CS4224_PP_LINE_LINEMISC_MPIF_RESET_DOTREG_dft 0x7 +#define CS4224_PP_LINE_LINEMISC_GIGEPCS_SOFT_RESET 0x1002 +#define CS4224_PP_LINE_LINEMISC_GIGEPCS_SOFT_RESET_dft 0x3 +#define CS4224_PP_LINE_LINEMISC_FUNCEN 0x1003 +#define CS4224_PP_LINE_LINEMISC_FUNCEN_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_CLKEN 0x1004 +#define CS4224_PP_LINE_LINEMISC_CLKEN_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL 0x1007 +#define CS4224_PP_LINE_LINEMISC_MSEQCLKCTRL_dft 0x4 +#define CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL 0x100B +#define CS4224_PP_LINE_LINEMISC_DATAPATH_CTRL_dft 0xF180 +#define CS4224_PP_LINE_LINEMISC_KR_AN_PORT_ADDR 0x100C +#define CS4224_PP_LINE_LINEMISC_KR_AN_PORT_ADDR_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_AN_MODE_SEL 0x100D +#define CS4224_PP_LINE_LINEMISC_AN_MODE_SEL_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_OVERRIDE_EN 0x1010 +#define CS4224_PP_LINE_LINEMISC_OVERRIDE_EN_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_INTERRUPT 0x1011 +#define CS4224_PP_LINE_LINEMISC_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_LINEMISC_INTENABLE 0x1012 +#define CS4224_PP_LINE_LINEMISC_INTENABLE_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RX0_Config 0x1020 +#define CS4224_PP_LINE_SDS_COMMON_RX0_Config_dft 0x18 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG 0x1021 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL 0x1023 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKDIV_CTRL_dft 0x3005 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKOUT_CTRL 0x1024 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CLKOUT_CTRL_dft 0x2FF +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA 0x1027 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CPA_dft 0x77 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE 0x1029 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_IBIAS_TUNE_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE 0x102A +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_RBIAS_TUNE_dft 0x44 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_MISC 0x102D +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_MISC_dft 0x300 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE 0x102F +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_SPARE_dft 0xE0F0 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON 0x1030 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_RX_CONFIG_EYEMON_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_VCOMAX 0x1031 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_VCOMAX_dft 0xFFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_CONTROL 0x1033 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_CONTROL_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI 0x1035 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_LIMIT_HI_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_STATUS 0x1037 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_ALTCT_STATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL3 0x1039 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL3_dft 0xFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL2 0x103A +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL2_dft 0xFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL1 0x103B +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL1_dft 0xFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL0 0x103C +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPLVL0_dft 0xFF +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES04 0x103D +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES04_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES03 0x103E +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES03_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES02 0x103F +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES02_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES01 0x1040 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES01_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES00 0x1041 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES00_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES14 0x1042 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES14_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES13 0x1043 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES13_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES12 0x1044 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES12_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES11 0x1045 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES11_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES10 0x1046 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_TMPTHRES10_dft 0x19 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL00 0x1047 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL00_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL01 0x1048 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL01_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL02 0x1049 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL02_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL03 0x104A +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL03_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL10 0x104B +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL10_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL11 0x104C +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL11_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL12 0x104D +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL12_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL13 0x104E +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_BIASVAL13_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_VCOBIAS 0x104F +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_LC_VCOBIAS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_STATUS 0x1050 +#define CS4224_PP_LINE_SDS_COMMON_RXVCO0_STATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_RESOLUTION 0x1057 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_RESOLUTION_dft 0x3 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_CONTROL 0x1059 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_CONTROL_dft 0x2098 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTERRUPT 0x105B +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTSTATUS 0x105C +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTSTATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTENABLE 0x105D +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTENABLE_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTERRUPTZ 0x105E +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKD0_INTERRUPTZ_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXELST0_Control 0x106E +#define CS4224_PP_LINE_SDS_COMMON_RXELST0_Control_dft 0x2 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Cfg 0x106F +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Cfg_dft 0x2000 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Ctrl 0x1070 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Ctrl_dft 0xC +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Count1 0x1071 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Count1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Count0 0x1072 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_Count0_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_INTERRUPT 0x1073 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_INTSTATUS 0x1074 +#define CS4224_PP_LINE_SDS_COMMON_PRBSCHK0_INTSTATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_RESET 0x1077 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_RESET_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_EN 0x1078 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_EN_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR0 0x1079 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR0_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR1 0x107A +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_NUMERATOR1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_NUMERATOR0 0x107D +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_NUMERATOR0_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_NUMERATOR1 0x107E +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_NUMERATOR1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_WIDTH 0x1081 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_WIDTH_dft 0xA +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_INTDIV 0x1082 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_INTDIV_dft 0x1919 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_STAGE_EN 0x1083 +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_STAGE_EN_dft 0x408 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0 0x1084 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0_dft 0xCCCC +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1 0x1085 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1_dft 0xCC +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE2PRELOAD0 0x1086 +#define CS4224_PP_LINE_SDS_COMMON_RDIVFRAC0_STAGE2PRELOAD0_dft 0xCCCC +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE1PRELOAD0 0x1088 +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE1PRELOAD0_dft 0xCCCC +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE1PRELOAD1 0x1089 +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE1PRELOAD1_dft 0xCC +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0 0x108A +#define CS4224_PP_LINE_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0_dft 0xCCCC +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_DITHER 0x108D +#define CS4224_PP_LINE_SDS_COMMON_FRAC0_DITHER_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_TX0_Config 0x108E +#define CS4224_PP_LINE_SDS_COMMON_TX0_Config_dft 0x18 +#define CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x108F +#define CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA_dft 0x814 +#define CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x1090 +#define CS4224_PP_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH 0x1091 +#define CS4224_PP_LINE_SDS_COMMON_STX0_SQUELCH_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_STX0_MISC 0x1092 +#define CS4224_PP_LINE_SDS_COMMON_STX0_MISC_dft 0x33 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Cfg 0x1096 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Cfg_dft 0x2000 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Ctrl 0x1097 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Ctrl_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Fixed0_Pattern1 0x1098 +#define CS4224_PP_LINE_SDS_COMMON_PRBSGEN0_Fixed0_Pattern1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_TXELST0_Control 0x109D +#define CS4224_PP_LINE_SDS_COMMON_TXELST0_Control_dft 0x2 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1 0x10A1 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG1_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2 0x10A2 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG2_dft 0x40 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4 0x10A4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_CONFIG4_dft 0x81F0 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE 0x10A5 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_AGC_RTUNE_dft 0x4 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB 0x10A6 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_MSB_dft 0xD +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB 0x10A7 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DAC_ENB_LSB_dft 0xDFFF +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL1 0x10A8 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL1_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL2 0x10A9 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_DLY_CTRL2_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_BIAS1 0x10AA +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_BIAS1_dft 0x5555 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG 0x10AE +#define CS4224_PP_LINE_SDS_COMMON_SRX0_DFE_CONFIG_dft 0x441 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_MONCTRL 0x10B1 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_MONCTRL_dft 0x2000 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG 0x10B2 +#define CS4224_PP_LINE_SDS_COMMON_SRX0_VCO_CONFIG_dft 0x607 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_CONFIG 0x10B4 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_CONFIG_dft 0x10 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_TUNE 0x10B5 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVER_TUNE_dft 0x404 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVERCML_TUNE 0x10B6 +#define CS4224_PP_LINE_SDS_COMMON_STX0_DRIVERCML_TUNE_dft 0x404 +#define CS4224_PP_LINE_SDS_COMMON_Int 0x10BA +#define CS4224_PP_LINE_SDS_COMMON_Int_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_IntEn 0x10BB +#define CS4224_PP_LINE_SDS_COMMON_IntEn_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKDi 0x10C7 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKDi_dft 0x0 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKDe 0x10C8 +#define CS4224_PP_LINE_SDS_COMMON_RXLOCKDe_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR 0x1220 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_CR_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1 0x1221 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0 0x1222 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_GRAM_D0_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_PC_SHADOW 0x1223 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_PC_SHADOW_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW 0x1224 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_SHADOW_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS 0x1225 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_OPTIONS_dft 0x8 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_PC 0x1228 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_PC_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_IX 0x1229 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_IX_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_BASE3_INST 0x1233 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_BASE3_INST_dft 0x3 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_ENABLE 0x1234 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_ENABLE_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB 0x1235 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft 0x1E0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB 0x1236 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_POWER_DOWN_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_STATUS 0x1237 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_STATUS_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR 0x1238 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_BANK_SELECTOR_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_SEL 0x1239 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_SEL_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_LSB 0x123A +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_MSB 0x123B +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_IN_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB 0x123C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_MSB 0x123D +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MAIL_OUT_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MU_VALUE 0x1245 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_MU_VALUE_dft 0xF0F +#define CS4224_PP_LINE_SDS_DSP_MSEQ_LEAK_INTVL_AGC 0x1247 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_LEAK_INTVL_AGC_dft 0x40 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_LEAK_INTVL_DFE 0x1248 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_LEAK_INTVL_DFE_dft 0x40 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_INIT_SEL 0x1249 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_INIT_SEL_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_FLOAT 0x124C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_COEF_DSP_FLOAT_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ1 0x125E +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ2 0x125F +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_EQADJ2_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN0 0x1262 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN0_dft 0x1FF +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN1 0x1263 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN1_dft 0x1FF +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN2 0x1264 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_DFE_GAIN2_dft 0x1FF +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL 0x1265 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_PHSEL_dft 0x20 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_SLICER 0x1266 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_SLICER_dft 0x80 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_AGC_MISC 0x1268 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_AGC_MISC_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_AGC_GAIN 0x1269 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_CAL_RX_AGC_GAIN_dft 0x7 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_CTRL 0x126C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_CTRL_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_ZEROS_LSB 0x126D +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SNR_ZEROS_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_LSB 0x1273 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_MSB 0x1274 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_RESET_COUNT_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES 0x1275 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SERDES_dft 0x30 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_LSB 0x1280 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_MSB 0x1281 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE0_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_LSB 0x1282 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_MSB 0x1283 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE1_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_LSB 0x1284 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_MSB 0x1285 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE2_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE3_LSB 0x1286 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE3_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE3_MSB 0x1287 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE3_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_LSB 0x1288 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_MSB 0x1289 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE4_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE5_LSB 0x128A +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE5_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE5_MSB 0x128B +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE5_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_LSB 0x128C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_MSB 0x128D +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE6_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_LSB 0x128E +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_MSB 0x128F +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE7_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE8_LSB 0x1290 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE8_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE8_MSB 0x1291 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE8_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_LSB 0x1292 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_MSB 0x1293 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE9_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE10_LSB 0x1294 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE10_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE10_MSB 0x1295 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE10_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_LSB 0x1296 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_MSB 0x1297 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE11_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB 0x1298 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB 0x1299 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE12_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_LSB 0x129A +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_MSB 0x129B +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE13_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE14_LSB 0x129C +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE14_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE15_MSB 0x129F +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE15_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE16_LSB 0x12A0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE16_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_LSB 0x12A4 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_MSB 0x12A5 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE18_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE19_LSB 0x12A6 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE19_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_LSB 0x12A8 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_MSB 0x12A9 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE20_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_LSB 0x12AA +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB 0x12AB +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE21_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE22_LSB 0x12AC +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE22_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE22_MSB 0x12AD +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE22_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE23_LSB 0x12AE +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE23_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE23_MSB 0x12AF +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE23_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_LSB 0x12B0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_MSB 0x12B1 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE24_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE25_LSB 0x12B2 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE25_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE25_MSB 0x12B3 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE25_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_LSB 0x12B4 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB 0x12B5 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE26_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE27_LSB 0x12B6 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE27_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE27_MSB 0x12B7 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE27_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE28_LSB 0x12B8 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE28_LSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE28_MSB 0x12B9 +#define CS4224_PP_LINE_SDS_DSP_MSEQ_SPARE28_MSB_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE0_0 0x1320 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE0_0_dft 0xA0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE0_1 0x1321 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE0_1_dft 0xF0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE1_0 0x1324 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE1_0_dft 0xE0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE1_1 0x1325 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE1_1_dft 0xF8 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE2_0 0x1328 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE2_0_dft 0xF0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE2_1 0x1329 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE2_1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE3_0 0x132C +#define CS4224_PP_LINE_SDS_DSP_IC_DFE3_0_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE3_1 0x132D +#define CS4224_PP_LINE_SDS_DSP_IC_DFE3_1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE4_0 0x132E +#define CS4224_PP_LINE_SDS_DSP_IC_DFE4_0_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_IC_DFE4_1 0x132F +#define CS4224_PP_LINE_SDS_DSP_IC_DFE4_1_dft 0x0 +#define CS4224_PP_LINE_SDS_DSP_ENABLE 0x1343 +#define CS4224_PP_LINE_SDS_DSP_ENABLE_dft 0x4 +#define CS4224_PP_LINE_SDS_DSP_COEF_SATURATED_INT 0x1354 +#define CS4224_PP_LINE_SDS_DSP_COEF_SATURATED_INT_dft 0x0 +#define CS4224_PP_LINE_GIGEPCS_LINE_CONTROL 0x1460 +#define CS4224_PP_LINE_GIGEPCS_LINE_CONTROL_dft 0x140 +#define CS4224_PP_LINE_GIGEPCS_LINE_STATUS 0x1461 +#define CS4224_PP_LINE_GIGEPCS_LINE_STATUS_dft 0x9 +#define CS4224_PP_LINE_GIGEPCS_INT_LINE_PCS1GE_INTERRUPT 0x1480 +#define CS4224_PP_LINE_GIGEPCS_INT_LINE_PCS1GE_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_GIGEPCS_INT_LINE_PCS1GE_INTSTATUS 0x1482 +#define CS4224_PP_LINE_GIGEPCS_INT_LINE_PCS1GE_INTSTATUS_dft 0x0 +#define CS4224_PP_LINE_EGPCS_RX_MODE 0x14A0 +#define CS4224_PP_LINE_EGPCS_RX_MODE_dft 0x8003 +#define CS4224_PP_LINE_EGPCS_RX_INTERRUPT 0x14A4 +#define CS4224_PP_LINE_EGPCS_RX_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_EGPCS_RX_INTSTATUS 0x14A6 +#define CS4224_PP_LINE_EGPCS_RX_INTSTATUS_dft 0x0 +#define CS4224_PP_LINE_EGPCS_TX_MODE 0x14B0 +#define CS4224_PP_LINE_EGPCS_TX_MODE_dft 0x8001 +#define CS4224_PP_LINE_EGPCS_TX_INTERRUPT 0x14B5 +#define CS4224_PP_LINE_EGPCS_TX_INTERRUPT_dft 0x0 +#define CS4224_PP_LINE_XGPCS_TX_TXCNTRL 0x14C0 +#define CS4224_PP_LINE_XGPCS_TX_TXCNTRL_dft 0x8002 +#define CS4224_PP_LINE_XGPCS_RX_RXCNTRL 0x14E0 +#define CS4224_PP_LINE_XGPCS_RX_RXCNTRL_dft 0xD000 +#define CS4224_PP_LINE_XGPCS_RX_RXSTATUS 0x14E1 +#define CS4224_PP_LINE_XGPCS_RX_RXSTATUS_dft 0x0 +#define CS4224_PP_LINE_XGPCS_RX_RXINT 0x14E2 +#define CS4224_PP_LINE_XGPCS_RX_RXINT_dft 0x0 +#define CS4224_PP_LINE_AN_TX_ENABLE 0x1500 +#define CS4224_PP_LINE_AN_TX_ENABLE_dft 0x0 +#define CS4224_PP_LINE_AN_TX_COMPLETE_STATUS 0x1505 +#define CS4224_PP_LINE_AN_TX_COMPLETE_STATUS_dft 0x0 +#define CS4224_PP_LINE_AN_TX_AN_COMPLETE_STATUS_INT 0x1506 +#define CS4224_PP_LINE_AN_TX_AN_COMPLETE_STATUS_INT_dft 0x0 +#define CS4224_PP_LINE_AN_TX_ADV_ABILITY 0x150C +#define CS4224_PP_LINE_AN_TX_ADV_ABILITY_dft 0x0 +#define CS4224_PP_LINE_AN_TX_TECH_ABILITY_1 0x150D +#define CS4224_PP_LINE_AN_TX_TECH_ABILITY_1_dft 0x0 +#define CS4224_PP_LINE_AN_TX_BP_STATUS 0x151B +#define CS4224_PP_LINE_AN_TX_BP_STATUS_dft 0x1 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMEOUT0 0x1523 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMEOUT0_dft 0x17C8 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMER_THRES1 0x1524 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMER_THRES1_dft 0x3B9 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMER_THRES0 0x1525 +#define CS4224_PP_LINE_AN_TX_LINK_FAIL_TIMER_THRES0_dft 0xACA0 +#define CS4224_PP_LINE_AN_TX_ABILITY_DETECT_TIMER_ENABLE 0x152A +#define CS4224_PP_LINE_AN_TX_ABILITY_DETECT_TIMER_ENABLE_dft 0x0 +#define CS4224_PP_LINE_AN_TX_MAIN_INT 0x152D +#define CS4224_PP_LINE_AN_TX_MAIN_INT_dft 0x0 +#define CS4224_PP_LINE_AN_TX_MAIN_INTS 0x152F +#define CS4224_PP_LINE_AN_TX_MAIN_INTS_dft 0x0 +#define CS4224_PP_LINE_AN_TX_TX_AFIFO_INT 0x1531 +#define CS4224_PP_LINE_AN_TX_TX_AFIFO_INT_dft 0x0 +#define CS4224_PP_LINE_AN_TX_ARBITRATOR_STATE 0x1536 +#define CS4224_PP_LINE_AN_TX_ARBITRATOR_STATE_dft 0x0 +#define CS4224_PP_LINE_AN_RX_PAGE_RECEIVED 0x1545 +#define CS4224_PP_LINE_AN_RX_PAGE_RECEIVED_dft 0x0 +#define CS4224_PP_LINE_AN_RX_LP_ABILITY_1 0x1546 +#define CS4224_PP_LINE_AN_RX_LP_ABILITY_1_dft 0x0 +#define CS4224_PP_LINE_AN_RX_LP_ABILITY_2 0x1547 +#define CS4224_PP_LINE_AN_RX_LP_ABILITY_2_dft 0x0 +#define CS4224_PP_LINE_AN_RX_MAIN_INT 0x155A +#define CS4224_PP_LINE_AN_RX_MAIN_INT_dft 0x0 +#define CS4224_PP_LINE_AN_RX_RX_AFIFO_INT 0x155E +#define CS4224_PP_LINE_AN_RX_RX_AFIFO_INT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_ENABLE 0x1580 +#define CS4224_PP_LINE_TP_TX_ENABLE_dft 0x0 +#define CS4224_PP_LINE_TP_TX_TX_RX_RESET 0x1581 +#define CS4224_PP_LINE_TP_TX_TX_RX_RESET_dft 0x3 +#define CS4224_PP_LINE_TP_TX_BITSWAP 0x1583 +#define CS4224_PP_LINE_TP_TX_BITSWAP_dft 0x1 +#define CS4224_PP_LINE_TP_TX_TRAINING 0x1586 +#define CS4224_PP_LINE_TP_TX_TRAINING_dft 0x0 +#define CS4224_PP_LINE_TP_TX_TRAINING_INT 0x1588 +#define CS4224_PP_LINE_TP_TX_TRAINING_INT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_TRAINING_INTS 0x158A +#define CS4224_PP_LINE_TP_TX_TRAINING_INTS_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMEOUT1 0x158C +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMEOUT1_dft 0x950 +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMEOUT0 0x158D +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMEOUT0_dft 0x2F90 +#define CS4224_PP_LINE_TP_TX_WAIT_TIMEOUT 0x158E +#define CS4224_PP_LINE_TP_TX_WAIT_TIMEOUT_dft 0x64 +#define CS4224_PP_LINE_TP_TX_ADDITIONAL_FRAMES 0x158F +#define CS4224_PP_LINE_TP_TX_ADDITIONAL_FRAMES_dft 0x2 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_MAX_LIMIT 0x1590 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_MAX_LIMIT_dft 0x30 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_MAX_LIMIT 0x1591 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_MAX_LIMIT_dft 0x30 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_MAX_LIMIT 0x1592 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_MAX_LIMIT_dft 0x30 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_MIN_LIMIT 0x1593 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_MIN_LIMIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_MIN_LIMIT 0x1594 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_MIN_LIMIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_MIN_LIMIT 0x1595 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_MIN_LIMIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_INIT 0x1596 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_INIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_INIT 0x1597 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_INIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_INIT 0x1598 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_INIT_dft 0x0 +#define CS4224_PP_LINE_TP_TX_PRESET_COEFF_OVERRIDE 0x1599 +#define CS4224_PP_LINE_TP_TX_PRESET_COEFF_OVERRIDE_dft 0x0 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_PRESET 0x159A +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_PRESET_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_PRESET 0x159B +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_PRESET_dft 0x0 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_PRESET 0x159C +#define CS4224_PP_LINE_TP_TX_POST_COEFF_PRESET_dft 0x0 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_START 0x159D +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_START_dft 0x5 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_START 0x159E +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_START_dft 0x23 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_START 0x159F +#define CS4224_PP_LINE_TP_TX_POST_COEFF_START_dft 0x24 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF 0x15A0 +#define CS4224_PP_LINE_TP_TX_PRE_COEFF_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF 0x15A1 +#define CS4224_PP_LINE_TP_TX_MAIN_COEFF_dft 0x0 +#define CS4224_PP_LINE_TP_TX_POST_COEFF 0x15A2 +#define CS4224_PP_LINE_TP_TX_POST_COEFF_dft 0x0 +#define CS4224_PP_LINE_TP_TX_COEFF_STEP_VALUE 0x15A3 +#define CS4224_PP_LINE_TP_TX_COEFF_STEP_VALUE_dft 0x111 +#define CS4224_PP_LINE_TP_TX_LD_COEFF_UPDATE_CTRL 0x15A4 +#define CS4224_PP_LINE_TP_TX_LD_COEFF_UPDATE_CTRL_dft 0x0 +#define CS4224_PP_LINE_TP_TX_FC_OPTIONS 0x15A8 +#define CS4224_PP_LINE_TP_TX_FC_OPTIONS_dft 0x0 +#define CS4224_PP_LINE_TP_TX_ENCODER_STATE 0x15A9 +#define CS4224_PP_LINE_TP_TX_ENCODER_STATE_dft 0x0 +#define CS4224_PP_LINE_TP_TX_TRAINING_STATE 0x15AA +#define CS4224_PP_LINE_TP_TX_TRAINING_STATE_dft 0x0 +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMER_EN 0x15AF +#define CS4224_PP_LINE_TP_TX_MAX_WAIT_TIMER_EN_dft 0x1 +#define CS4224_PP_LINE_TP_RX_BITSWAP 0x15C0 +#define CS4224_PP_LINE_TP_RX_BITSWAP_dft 0x1 +#define CS4224_PP_LINE_TP_RX_REMOTE_RX_READY 0x15C1 +#define CS4224_PP_LINE_TP_RX_REMOTE_RX_READY_dft 0x113 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_INT 0x15C2 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_INT_dft 0x0 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_INTS 0x15C4 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_INTS_dft 0x0 +#define CS4224_PP_LINE_TP_RX_FM_DETECT_STATE 0x15C9 +#define CS4224_PP_LINE_TP_RX_FM_DETECT_STATE_dft 0x0 +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_STATE 0x15CA +#define CS4224_PP_LINE_TP_RX_FRAME_LOCK_STATE_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_RESET 0x1600 +#define CS4224_PP_LINE_KR_FEC_TX_RESET_dft 0x1 +#define CS4224_PP_LINE_KR_FEC_TX_STATUS 0x1602 +#define CS4224_PP_LINE_KR_FEC_TX_STATUS_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_STATS_CONTROL 0x160A +#define CS4224_PP_LINE_KR_FEC_TX_STATS_CONTROL_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_STATS_TX_BLK_TOTAL1 0x160B +#define CS4224_PP_LINE_KR_FEC_TX_STATS_TX_BLK_TOTAL1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_STATS_TX_BLK_TOTAL0 0x160C +#define CS4224_PP_LINE_KR_FEC_TX_STATS_TX_BLK_TOTAL0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_TX_INT 0x160D +#define CS4224_PP_LINE_KR_FEC_TX_INT_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_RESET 0x1640 +#define CS4224_PP_LINE_KR_FEC_RX_RESET_dft 0x1 +#define CS4224_PP_LINE_KR_FEC_RX_STATUS 0x1642 +#define CS4224_PP_LINE_KR_FEC_RX_STATUS_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_CONTROL 0x1644 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_CONTROL_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_TOTAL1 0x1645 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_TOTAL1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_TOTAL0 0x1646 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_TOTAL0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_CORR1 0x1647 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_CORR1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_CORR0 0x1648 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_CORR0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_UNCORR1 0x1649 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_UNCORR1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_UNCORR0 0x164A +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BLK_UNCORR0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ZERO_ERRS1 0x164B +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ZERO_ERRS1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ZERO_ERRS0 0x164C +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ZERO_ERRS0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ONE_ERRS1 0x164D +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ONE_ERRS1_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ONE_ERRS0 0x164E +#define CS4224_PP_LINE_KR_FEC_RX_STATS_RX_BIT_ONE_ERRS0_dft 0x0 +#define CS4224_PP_LINE_KR_FEC_RX_INT 0x165F +#define CS4224_PP_LINE_KR_FEC_RX_INT_dft 0x0 +#define CS4224_PP_LINE_MCAN_RESET 0x1680 +#define CS4224_PP_LINE_MCAN_RESET_dft 0x1 +#define CS4224_PP_HOST_HOSTMISC_SOFT_RESET 0x1800 +#define CS4224_PP_HOST_HOSTMISC_SOFT_RESET_dft 0x2 +#define CS4224_PP_HOST_HOSTMISC_MPIF_RESET_DOTREG 0x1801 +#define CS4224_PP_HOST_HOSTMISC_MPIF_RESET_DOTREG_dft 0x3 +#define CS4224_PP_HOST_HOSTMISC_GIGEPCS_SOFT_RESET 0x1802 +#define CS4224_PP_HOST_HOSTMISC_GIGEPCS_SOFT_RESET_dft 0x1 +#define CS4224_PP_HOST_HOSTMISC_FUNCEN 0x1803 +#define CS4224_PP_HOST_HOSTMISC_FUNCEN_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_CLKEN 0x1804 +#define CS4224_PP_HOST_HOSTMISC_CLKEN_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_MATE_SELECT 0x1806 +#define CS4224_PP_HOST_HOSTMISC_MATE_SELECT_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_MSEQCLKCTRL 0x1807 +#define CS4224_PP_HOST_HOSTMISC_MSEQCLKCTRL_dft 0x4 +#define CS4224_PP_HOST_HOSTMISC_OVERRIDE_EN 0x1810 +#define CS4224_PP_HOST_HOSTMISC_OVERRIDE_EN_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_INTERRUPT 0x1811 +#define CS4224_PP_HOST_HOSTMISC_INTERRUPT_dft 0x0 +#define CS4224_PP_HOST_HOSTMISC_INTENABLE 0x1812 +#define CS4224_PP_HOST_HOSTMISC_INTENABLE_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RX0_Config 0x1820 +#define CS4224_PP_HOST_SDS_COMMON_RX0_Config_dft 0x18 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG 0x1821 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CONFIG_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL 0x1823 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKDIV_CTRL_dft 0x3005 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKOUT_CTRL 0x1824 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CLKOUT_CTRL_dft 0x2FF +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CPA 0x1827 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_CPA_dft 0x77 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_IBIAS_TUNE 0x1829 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_IBIAS_TUNE_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_RBIAS_TUNE 0x182A +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_RBIAS_TUNE_dft 0x44 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_SPARE 0x182F +#define CS4224_PP_HOST_SDS_COMMON_SRX0_RX_SPARE_dft 0xE0F0 +#define CS4224_PP_HOST_SDS_COMMON_RXVCO0_CONTROL 0x1833 +#define CS4224_PP_HOST_SDS_COMMON_RXVCO0_CONTROL_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXVCO0_ALTCT_STATUS 0x1837 +#define CS4224_PP_HOST_SDS_COMMON_RXVCO0_ALTCT_STATUS_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_CONTROL 0x1859 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_CONTROL_dft 0x2098 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTERRUPT 0x185B +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTERRUPT_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTSTATUS 0x185C +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTSTATUS_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTENABLE 0x185D +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTENABLE_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTERRUPTZ 0x185E +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKD0_INTERRUPTZ_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXELST0_Control 0x186E +#define CS4224_PP_HOST_SDS_COMMON_RXELST0_Control_dft 0x2 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Cfg 0x186F +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Cfg_dft 0x2000 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Ctrl 0x1870 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Ctrl_dft 0xC +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Count1 0x1871 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Count1_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Count0 0x1872 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_Count0_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_INTERRUPT 0x1873 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_INTERRUPT_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_INTSTATUS 0x1874 +#define CS4224_PP_HOST_SDS_COMMON_PRBSCHK0_INTSTATUS_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_RESET 0x1877 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_RESET_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_EN 0x1878 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_EN_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR0 0x1879 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR0_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR1 0x187A +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_NUMERATOR1_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_NUMERATOR0 0x187D +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_NUMERATOR0_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_NUMERATOR1 0x187E +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_NUMERATOR1_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_WIDTH 0x1881 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_WIDTH_dft 0xA +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_INTDIV 0x1882 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_INTDIV_dft 0x1919 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_STAGE_EN 0x1883 +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_STAGE_EN_dft 0x408 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0 0x1884 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD0_dft 0xCCCC +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1 0x1885 +#define CS4224_PP_HOST_SDS_COMMON_RDIVFRAC0_STAGE1PRELOAD1_dft 0xCC +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE1PRELOAD0 0x1888 +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE1PRELOAD0_dft 0xCCCC +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE1PRELOAD1 0x1889 +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE1PRELOAD1_dft 0xCC +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0 0x188A +#define CS4224_PP_HOST_SDS_COMMON_COREFRAC0_STAGE2PRELOAD0_dft 0xCCCC +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_DITHER 0x188D +#define CS4224_PP_HOST_SDS_COMMON_FRAC0_DITHER_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_TX0_Config 0x188E +#define CS4224_PP_HOST_SDS_COMMON_TX0_Config_dft 0x18 +#define CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA 0x188F +#define CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA_dft 0x814 +#define CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB 0x1890 +#define CS4224_PP_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLB_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH 0x1891 +#define CS4224_PP_HOST_SDS_COMMON_STX0_SQUELCH_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_STX0_MISC 0x1892 +#define CS4224_PP_HOST_SDS_COMMON_STX0_MISC_dft 0x33 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Cfg 0x1896 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Cfg_dft 0x2000 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Ctrl 0x1897 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Ctrl_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Fixed0_Pattern1 0x1898 +#define CS4224_PP_HOST_SDS_COMMON_PRBSGEN0_Fixed0_Pattern1_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_TXELST0_Control 0x189D +#define CS4224_PP_HOST_SDS_COMMON_TXELST0_Control_dft 0x2 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1 0x18A1 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG1_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG2 0x18A2 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG2_dft 0x40 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG4 0x18A4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_CONFIG4_dft 0x81F0 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_RTUNE 0x18A5 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_AGC_RTUNE_dft 0x4 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB 0x18A6 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_MSB_dft 0xD +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB 0x18A7 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DAC_ENB_LSB_dft 0xDFFF +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG 0x18AE +#define CS4224_PP_HOST_SDS_COMMON_SRX0_DFE_CONFIG_dft 0x441 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG 0x18B2 +#define CS4224_PP_HOST_SDS_COMMON_SRX0_VCO_CONFIG_dft 0x607 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_CONFIG 0x18B4 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_CONFIG_dft 0x10 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE 0x18B5 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVER_TUNE_dft 0x404 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE 0x18B6 +#define CS4224_PP_HOST_SDS_COMMON_STX0_DRIVERCML_TUNE_dft 0x404 +#define CS4224_PP_HOST_SDS_COMMON_Int 0x18BA +#define CS4224_PP_HOST_SDS_COMMON_Int_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_IntEn 0x18BB +#define CS4224_PP_HOST_SDS_COMMON_IntEn_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKDi 0x18C7 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKDi_dft 0x0 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKDe 0x18C8 +#define CS4224_PP_HOST_SDS_COMMON_RXLOCKDe_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_CR 0x1A20 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_CR_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_D1 0x1A21 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_D1_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_D0 0x1A22 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_GRAM_D0_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_PC_SHADOW 0x1A23 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_PC_SHADOW_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_SHADOW 0x1A24 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_SHADOW_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS 0x1A25 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_OPTIONS_dft 0x8 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_PC 0x1A28 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_PC_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_IX 0x1A29 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_IX_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_BASE3_INST 0x1A33 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_BASE3_INST_dft 0x3 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_ENABLE 0x1A34 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_ENABLE_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB 0x1A35 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_POWER_DOWN_LSB_dft 0x1E0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_STATUS 0x1A37 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_STATUS_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_BANK_SELECTOR 0x1A38 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_BANK_SELECTOR_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_SEL 0x1A39 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_SEL_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_LSB 0x1A3A +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_MSB 0x1A3B +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_IN_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_LSB 0x1A3C +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_MSB 0x1A3D +#define CS4224_PP_HOST_SDS_DSP_MSEQ_MAIL_OUT_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_CAL_RX_PHSEL 0x1A65 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_CAL_RX_PHSEL_dft 0x20 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SERDES 0x1A75 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SERDES_dft 0x30 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE0_LSB 0x1A80 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE0_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE6_MSB 0x1A8D +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE6_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_LSB 0x1A98 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_MSB 0x1A99 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE12_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE14_LSB 0x1A9C +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE14_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE15_MSB 0x1A9F +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE15_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE20_MSB 0x1AA9 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE20_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE22_LSB 0x1AAC +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE22_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE22_MSB 0x1AAD +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE22_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE24_MSB 0x1AB1 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE24_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE25_LSB 0x1AB2 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE25_LSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE25_MSB 0x1AB3 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE25_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE26_MSB 0x1AB5 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE26_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE28_MSB 0x1AB9 +#define CS4224_PP_HOST_SDS_DSP_MSEQ_SPARE28_MSB_dft 0x0 +#define CS4224_PP_HOST_SDS_DSP_COEF_SATURATED_INT 0x1B54 +#define CS4224_PP_HOST_SDS_DSP_COEF_SATURATED_INT_dft 0x0 +#define CS4224_PP_HOST_GIGEPCS_INT_HOST_PCS1GE_INTERRUPT 0x1C80 +#define CS4224_PP_HOST_GIGEPCS_INT_HOST_PCS1GE_INTERRUPT_dft 0x0 +#define CS4224_PP_HOST_GIGEPCS_INT_HOST_PCS1GE_INTSTATUS 0x1C82 +#define CS4224_PP_HOST_GIGEPCS_INT_HOST_PCS1GE_INTSTATUS_dft 0x0 +#define CS4224_PP_CLKMON_ING_CLKSEL 0x1D00 +#define CS4224_PP_CLKMON_ING_CLKSEL_dft 0x7F +#define CS4224_PP_CLKMON_ING_CTRL 0x1D01 +#define CS4224_PP_CLKMON_ING_CTRL_dft 0x110 +#define CS4224_PP_CLKMON_ING_DURATION 0x1D02 +#define CS4224_PP_CLKMON_ING_DURATION_dft 0x0 +#define CS4224_PP_CLKMON_ING_STATUS 0x1D03 +#define CS4224_PP_CLKMON_ING_STATUS_dft 0x0 +#define CS4224_PP_CLKMON_ING_COUNT1 0x1D04 +#define CS4224_PP_CLKMON_ING_COUNT1_dft 0x0 +#define CS4224_PP_CLKMON_ING_COUNT0 0x1D05 +#define CS4224_PP_CLKMON_ING_COUNT0_dft 0x0 +#define CS4224_PP_CLKMON_ING_MINTHRESH1 0x1D06 +#define CS4224_PP_CLKMON_ING_MINTHRESH1_dft 0x0 +#define CS4224_PP_CLKMON_ING_MINTHRESH0 0x1D07 +#define CS4224_PP_CLKMON_ING_MINTHRESH0_dft 0x0 +#define CS4224_PP_CLKMON_ING_MAXTHRESH1 0x1D08 +#define CS4224_PP_CLKMON_ING_MAXTHRESH1_dft 0x0 +#define CS4224_PP_CLKMON_ING_MAXTHRESH0 0x1D09 +#define CS4224_PP_CLKMON_ING_MAXTHRESH0_dft 0x0 +#define CS4224_PP_CLKMON_EGR_CLKSEL 0x1D10 +#define CS4224_PP_CLKMON_EGR_CLKSEL_dft 0x7F +#define CS4224_PP_CLKMON_EGR_CTRL 0x1D11 +#define CS4224_PP_CLKMON_EGR_CTRL_dft 0x110 +#define CS4224_PP_CLKMON_EGR_DURATION 0x1D12 +#define CS4224_PP_CLKMON_EGR_DURATION_dft 0x0 +#define CS4224_PP_CLKMON_EGR_STATUS 0x1D13 +#define CS4224_PP_CLKMON_EGR_STATUS_dft 0x0 +#define CS4224_PP_CLKMON_EGR_COUNT1 0x1D14 +#define CS4224_PP_CLKMON_EGR_COUNT1_dft 0x0 +#define CS4224_PP_CLKMON_EGR_COUNT0 0x1D15 +#define CS4224_PP_CLKMON_EGR_COUNT0_dft 0x0 +#define CS4224_PP_CLKMON_EGR_MINTHRESH1 0x1D16 +#define CS4224_PP_CLKMON_EGR_MINTHRESH1_dft 0x0 +#define CS4224_PP_CLKMON_EGR_MINTHRESH0 0x1D17 +#define CS4224_PP_CLKMON_EGR_MINTHRESH0_dft 0x0 +#define CS4224_PP_CLKMON_EGR_MAXTHRESH1 0x1D18 +#define CS4224_PP_CLKMON_EGR_MAXTHRESH1_dft 0x0 +#define CS4224_PP_CLKMON_EGR_MAXTHRESH0 0x1D19 +#define CS4224_PP_CLKMON_EGR_MAXTHRESH0_dft 0x0 +#define CS4224_EEPROM_LOADER_STATUS 0x5001 +#define CS4224_EEPROM_LOADER_STATUS_dft 0x0 +#define CS4224_EEPROM_MICRO_ACCESS_CONTROL 0x5005 +#define CS4224_EEPROM_MICRO_ACCESS_CONTROL_dft 0x0 +#define CS4224_EEPROM_MICRO_ACCESS_STATUS 0x5006 +#define CS4224_EEPROM_MICRO_ACCESS_STATUS_dft 0x0 + +/* bit masks */ +#define CS_BIT0 0x0001 +#define CS_BIT1 0x0002 +#define CS_BIT2 0x0004 +#define CS_BIT3 0x0008 +#define CS_BIT4 0x0010 +#define CS_BIT5 0x0020 +#define CS_BIT6 0x0040 +#define CS_BIT7 0x0080 +#define CS_BIT8 0x0100 +#define CS_BIT9 0x0200 +#define CS_BIT10 0x0400 +#define CS_BIT11 0x0800 +#define CS_BIT12 0x1000 +#define CS_BIT13 0x2000 +#define CS_BIT14 0x4000 +#define CS_BIT15 0x8000 + +/* bit masks for MSB registers */ +#define CS_MSB_BIT16 0x0001 +#define CS_MSB_BIT17 0x0002 +#define CS_MSB_BIT18 0x0004 +#define CS_MSB_BIT19 0x0008 +#define CS_MSB_BIT20 0x0010 +#define CS_MSB_BIT21 0x0020 +#define CS_MSB_BIT22 0x0040 +#define CS_MSB_BIT23 0x0080 +#define CS_MSB_BIT24 0x0100 +#define CS_MSB_BIT25 0x0200 +#define CS_MSB_BIT26 0x0400 +#define CS_MSB_BIT27 0x0800 +#define CS_MSB_BIT28 0x1000 +#define CS_MSB_BIT29 0x2000 +#define CS_MSB_BIT30 0x4000 +#define CS_MSB_BIT31 0x8000 + +unsigned int CS_ABS(int value); + +void *CS_MEMSET(void *p, int c, int n); +void *CS_MEMCPY(void *p, const void *src, int n); +int CS_STRLEN(const char *s); +char *CS_STRCAT(char *dest, const char *source); +char *CS_STRNCPY(char *dest, const char *source, int count); + +#define CS_IF_SET(val, mask) (((val) & (mask)) != 0) +#define CS_IF_ALL_SET(val, mask) (((val) & (mask)) == mask) +#define CS_IF_CLR(val, mask) (((val) & (mask)) == 0) +#define CS_SET(val, mask) (((val) | (mask))) +#define CS_CLR(val, mask) (((val) & ~(mask))) +#define CS_TOGGLE(val, mask) (((val) ^ (mask))) + +enum e_cs4224_kran_an_status_t { + CS4224_KRAN_AN_NOT_DONE, + CS4224_KRAN_AN_DONE, +}; + +struct cs4224_kran_advertised_config_t_s { + /* (A4) (4 x 10G) 40G Faceplate/Cable */ + unsigned short tech_cr4; + + /* (A3) (4 x 10G) 40G Backplane */ + unsigned short tech_kr4; + + /* (A2) 10G Backplane */ + unsigned short tech_kr; + + /* (A0) 1G Backplane */ + unsigned short tech_kx; + + /* (A1) (4 x 2.5G) 10G Backplane */ + unsigned short tech_kx4; + + /* (F0) FEC Ability */ + unsigned short f0; + + /* (F1) FEC Requested */ + unsigned short f1; + + /* (C0) Link Partner Pause Ability */ + unsigned short pause_0; + + /* (C1) Link Partner Pause Ability */ + unsigned short pause_1; + + /* (D13) Remote Fault */ + unsigned short rf; +}; + +struct cs4224_kran_advanced_config_t_s { + /* Enable the line side fixed-phase override */ + unsigned char phase_or; + + /* Enable the host side fixed-phase override */ + unsigned char hphase_or; + + /* Enable the AN Ability Detect Timeout */ + unsigned char en_adt; + + /* Enable the TP Max Wait Timer */ + unsigned char en_mwt; + + /* Skip Auto-Negotiation */ + unsigned char skip_an; + + /* Skip Training */ + unsigned char skip_tp; + + /* Skip line side Phase Calibration */ + unsigned char skip_phsc; + + /* Enable Link Fail Inhibit Timer */ + unsigned char en_lfit; + + /* Enable AN Retries */ + unsigned char en_retry; + + /* Disable AN start */ + unsigned char dis_start; + + /* Enable DFE Power Savings */ + unsigned char en_pwrsv; + + /* Enable DFE */ + unsigned char en_dfe; + + /* Count Frames with Invalid Markers */ + unsigned char bad_mrkrs; + + /* Disable PCS Sync Checks in Mission Mode */ + unsigned char dis_sync; + /* Enable the tx squelch control in the egress (host->line) path */ + unsigned char sqlch_egr; + + /* Enable the tx squelch control in the ingress (line->host) path */ + unsigned char sqlch_ing; + + /* Enables the use of the ring oscillator VCO */ + unsigned char ring; + + /* Line side Fixed-phase value, used only when phase_or is TRUE */ + unsigned short phase_ov; + + /* Host side fixed-phase value, used only when hphase_or is TRUE */ + unsigned short hphase_ov; + + /* Number of Additional Frames to Send at the Start of SEND_DATA */ + unsigned short xtra_f; + + /* Iterations to Wait for PCS to Sync (multiply by 2^16) */ + unsigned short pcs_itr; + + /* 10G LFI Timeout */ + unsigned short lfi_10g; + + /* TP_TX maximum wait */ + unsigned short max_wait; + + /* LFI Threshold */ + unsigned short lfi_thres; + + /* 1G LFI timeout */ + unsigned short lfi_1g; + + /* Override the LINK_READY wait_timer */ + unsigned short wait_tmr; + + /* True = Main-cursor incremented to maximum, + * False=Main-cursor untouched + */ + unsigned char tpm0; + + /* True = Post-cursor adaptive calibration, + * False=Post-cursor incremented to maximum + */ + unsigned char tpm1; + + /* True = Send preset command at start */ + unsigned char tpm2; + + /* True = Send init command at start */ + unsigned char tpm3; + + /* True = Force local_rx_ready to True immediately */ + unsigned char tpm4; + + /* Always set to 'b000 */ + unsigned short tpm567; + + /* True = Enable pre/main/post Cursor Preset Values */ + unsigned char preset; + + /* True = Skip Rx data corruption */ + unsigned char tpm30; + + /* True = Invert Pre & Post cursor orientation (Leeds emulation mode) */ + unsigned char tpm31; + + /* True = calibrate if we lose lock */ + unsigned char jmp2cal; + + /* True = reference clock frequency is 106.25Mhz, + * set according to rules->ref_clk_rate + */ + unsigned char ref106; + + /* True = two-pass mode for optical links enabled */ + unsigned short two_pass_mode; + + /* True = disable FEC even when FEC is advertized and negotiated */ + unsigned short fec_bypass; + + /* Time to EDC converge in DFE mode, line side, + * range 0...0xffff, default 0x0180 + */ + unsigned short line_t_to_conv_dfe; + + /* Time to EDC converge in DFE mode, host side, + * range 0...0xffff, default 0x0240 + */ + unsigned short host_t_to_conv_dfe; + +}; + +struct cs4224_kran_config_t_s { + struct cs4224_kran_advertised_config_t_s advertised; + struct cs4224_kran_advanced_config_t_s advanced; +}; + +struct cs4224_kran_results_t_s { + /* Parallel detect */ + unsigned char bp_par_detect:1; + + /* (4 x 10G) 40G CR4 capability detect */ + unsigned char bp_40gcr4:1; + + /* (4 x 10G) 40G KR4 capability detect */ + unsigned char bp_40gkr4:1; + + /* 10G KR capability detect */ + unsigned char bp_10gkr:1; + + /* 1G KX capability detect */ + unsigned char bp_1000kx:1; + + /* (4 x 2.5G) 10G KX4 capability detect */ + unsigned char bp_10gkx4:1; + + /* FEC capability detect */ + unsigned char bp_fec:1; + + /* Remote Fault */ + unsigned char bp_rf:1; + + /* Pause ability */ + unsigned char bp_pause:3; +}; +extern unsigned int cs4224_max_num_ports; + +unsigned int CS4224_MAX_NUM_PORTS(void); +unsigned int CS4224_MAX_NUM_SLICES(unsigned int slice); +unsigned int CS4224_MAX_NUM_DIES(unsigned int slice); + +#define CS4224_RULE_DISABLED 0xFFFF +#define CS4224_MAX_NUM_CS4223_PORTS 4 /* 4 port duplex */ +#define CS4224_MAX_NUM_CS4224_PORTS 16 /* 16 port simplex */ +#define CS4224_MAX_NUM_CS4343_PORTS 8 /* 8 port duplex */ +#define CS4224_MAX_NUM_CS4221_PORTS 10 /* 10 port simplex */ +#define CS4224_MAX_NUM_CS4227_PORTS 2 /* 2 port duplex */ +#define CS4224_MAX_NUM_CS4210_PORTS 16 /* 16 port simplex */ +#define CS4224_MAX_NUM_CS4341_PORTS 8 /* 8 port duplex */ + +/* The number of available dies in the device */ +#define CS4224_MAX_NUM_CS4223_DIES 1 /* 4 port duplex */ +#define CS4224_MAX_NUM_CS4224_DIES 2 /* 16 port simplex */ +#define CS4224_MAX_NUM_CS4343_DIES 2 /* 8 port duplex */ +#define CS4224_MAX_NUM_CS4221_DIES 2 /* 10 port simplex */ +#define CS4224_MAX_NUM_CS4227_DIES 1 /* 2 port duplex */ +#define CS4224_MAX_NUM_CS4210_DIES 2 /* 16 port simplex */ +#define CS4224_MAX_NUM_CS4341_DIES 2 /* 8 port duplex */ + +/* The difference between line and host PP registers */ +#define CS4224_LINE_TO_HOST_OFFSET 0x0800 + +#define CS4224_REF_CLK_156p25 156250 /* kHz */ +#define CS4224_REF_CLK_155p52 155520 +#define CS4224_REF_CLK_106p25 106250 + +/* The preferred GLOBAL_MDIO_CONFIG value */ +#define CS4224_GLOBAL_MDIO_CONFIG_pref 0x78 + +/* Required or loaded ucode image bit map */ +enum e_cs4224_ucode_image { + CS4224_UCODE_IMAGE_NONE = 0x0, + CS4224_UCODE_IMAGE_KR = 0x1, + CS4224_UCODE_IMAGE_FC = 0x2, + CS4224_UCODE_IMAGE_ANY = 0x3, +}; + +/* Hardware ID numbers for the ASIC as defined in Efuse SKU */ +enum e_cs4224_hardware_id { + /* Undefined */ + CS4224_HW_UNDEF = 0, + + /* 4 port duplex */ + CS4224_HW_CS4223 = 0x0010, + + /* 16 port simplex */ + CS4224_HW_CS4224 = 0x0011, + + /* 8 port duplex */ + CS4224_HW_CS4343 = 0x0012, + + /* 10 port simplex */ + CS4224_HW_CS4221 = 0x0013, + + /* 2 port duplex */ + CS4224_HW_CS4227 = 0x0014, + + /* 16 port simplex, 15G only */ + CS4224_HW_CS4210 = 0x0015, + + /* 8 port duplex, 10G only */ + CS4224_HW_CS4341 = 0x0016 +}; + +/* Pre-defined target applications used + * with the cs4224_rules_set_default() method + * to setup default configurations + */ +enum e_cs4224_target_application { + /* Configure the device for 156.25MHz ref clock, 1.25GHz operation */ + CS4224_TARGET_APPLICATION_1G = 0, + + /* Configure the device for 156.25MHz ref clock, 5GHz operation */ + CS4224_TARGET_APPLICATION_5G, + + /* Configure the device for 156.25MHz ref clock, 7.5GHz operation */ + CS4224_TARGET_APPLICATION_7p5G, + + /* Configure the device for 156.25MHz ref clock, 8GHz operation */ + CS4224_TARGET_APPLICATION_8G, + + /* Configure the device for 156.25MHz ref clock, 8.5GHz operation */ + CS4224_TARGET_APPLICATION_8p5G, + + /* Configure the device for 156.25MHz ref clock, 10.3125GHz operation */ + CS4224_TARGET_APPLICATION_10G, + + /* Configure the device for 156.25MHz ref clock, 15GHz operation */ + CS4224_TARGET_APPLICATION_15G, + CS4224_TARGET_APPLICATION_10G_KR, + CS4224_TARGET_APPLICATION_40G_KR, + + /* Configure the device for KR-AN operation */ + CS4224_TARGET_APPLICATION_KRAN, + + /* Configure the device for FC-AN operation */ + CS4224_TARGET_APPLICATION_FCAN, + + /* Configure the device for 106.25MHz refclk, 14.025GHz FC */ + CS4224_TARGET_APPLICATION_16G_FC, + + /* Configure the device for 106.25MHz refclk, 10.51875GHz FC */ + CS4224_TARGET_APPLICATION_10G_FC, + + /* Configure the device for 106.25MHz refclk, 8.5GHz FC */ + CS4224_TARGET_APPLICATION_8G_FC, + + /* Configure the device for 106.25MHz refclk, 4.25GHz FC */ + CS4224_TARGET_APPLICATION_4G_FC, + + /* Configure the device for 106.25MHz refclk, 2.125GHz FC*/ + CS4224_TARGET_APPLICATION_2G_FC, + + /* Configure the device for 106.25MHz refclk, 1.0625GHz FC */ + CS4224_TARGET_APPLICATION_1G_FC, + + /* Configure the device for 156.25MHz refclk, 622.08MHz OC12 */ + CS4224_TARGET_APPLICATION_OC12 +}; + +#define e_cs4224_cfg_sides_t e_cs4224_datapath_dir_t + +/* Data-path direction and side selector */ +enum e_cs4224_datapath_dir_t { + /* Select the Line to Host path (Ingress) */ + CS4224_LINE_RX_TO_HOST_TX_DIR = 1, + + /* Configure the line side */ + CS4224_CFG_LINE_SIDE = 1, + + /* Select the Host to Line path (Egress) */ + CS4224_HOST_RX_TO_LINE_TX_DIR = 2, + + /* Configure the host side */ + CS4224_CFG_HOST_SIDE = 2, + + /* The channel is simplex; direction is picked automatically by API */ + CS4224_SIMPLEX_DIR = 3, + + /* Configure a simplex slice */ + CS4224_CFG_SIMPLEX = 3, +}; + +/* The supply voltage for the voltage monitor */ +enum e_cs4224_mon_vlt_supply { + /* 0.9V supply TX */ + CS4224_VLT_SUPPLY_0p9V = 0, + + /* 1.8V supply */ + CS4224_VLT_SUPPLY_1p8V = 1, +}; + +/* The EDC modes supported by the microcode */ +enum e_cs4224_edc_mode { + /* + * Disable the microcode. Does not disable the EDC. + * + * @{warning, + * This mode is not recommended and should not be used unless + * explicitly told to do so by Cortina + * } + */ + CS_HSIO_EDC_MODE_DISABLED = 0x0001, + + /* + * DFE mode meant for CX1 or direct attach compatible cables. + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied + * } + */ + CS_HSIO_EDC_MODE_CX1 = 0x0002, + + /* + * Non-DFE mode meant to support low channel loss applications. + * + * Short for 'short reach'. This mode is suitable for connecting to + * SR modules, very short on-board connections, or anything involving + * slow data rates. + * + * @{note, + * Although it's a fully adaptive mode, unlike DFE modes receiver tuning + * is required to maximize performance. See these rules: + * + * - rules.rx_if.dplx_line_eq (Duplex devices) + * - rules.rx_if.dplx_host_eq (Duplex devices) + * - rules.rx_if.splx_eq (Simplex devices) + * } + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 622Mbps ! 15Gbps ! API Optimized range + * } + * + */ + CS_HSIO_EDC_MODE_SR = 0x0004, + + /* + * DFE mode meant to support ZR modules. + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied + * } + */ + CS_HSIO_EDC_MODE_ZR = 0x0008, + + /* + * DFE mode meant to support DWDM modules. + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied + * } + */ + CS_HSIO_EDC_MODE_DWDM = 0x0010, + + /* + * DFE mode meant to support 9.8 to 12.5G data rates over a backplane. + * + * @{note, + * KR-AN DFE mode is supported through CS_HSIO_EDC_MODE_10G_BP, + * see KR-AN programming + * examples for more info. + * } + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied to improve + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied to improve + * } + */ + CS_HSIO_EDC_MODE_10G_BP = 0x0020, + + /* + * DFE mode meant to support 12.5 to 15G data rates over a backplane. + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 12.5Gbps ! <14Gbps ! Optional tuning could be applied. + * - 14Gbps ! 15Gbps ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_15G_BP = 0x0040, + + /* + * DFE mode meant to support 5 to 7.5G data rates over a backplane. + * + * @{note, + * CS_HSIO_EDC_MODE_5G_BP and CS_HSIO_EDC_MODE_7p5G_BP are functionally + * equivalent + * } + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 5.0Gbps ! 7.5Gbps ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_5G_BP = 0x0080, + + /* + * DFE mode meant to support 5 to 7.5G data rates over a backplane. + * + * @{note, + * CS_HSIO_EDC_MODE_5G_BP and CS_HSIO_EDC_MODE_7p5G_BP are functionally + * equivalent + * } + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 5.0Gbps ! 7.5Gbps ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_7p5G_BP = 0x0100, + + /* + * DFE mode meant to support 8 to 8.6G data rates over a backplane. + * + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 8.0Gbps ! 8.6Gbps ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_8p5G_BP = 0x0200, + + /* + * DFE mode for the line side on FC-AN connections. + * + * @{note, + * FC-AN SR/DFE mode on the line side is supported through + * CS_HSIO_EDC_MODE_FCAN, + * see FC-AN programming examples for more info. + * } + * + * @{table, + * -h Supported Data Rates + * -s Fibre Channel Rates ! Note + * - FC1, FC2, FC4, FC8, FC10, FC16 ! API optimized range + * } + */ + CS_HSIO_EDC_MODE_FCAN = 0x0400, + + /* + * DFE mode meant for very specific 15G backplane applications. + * + * @{warning, + * Do not use unless advised to do so by a Cortina AE. + * } + */ + CS_HSIO_EDC_MODE_15G_BP_27dB = 0x0800, + + /* + * DFE mode meant for Single Mode Fibre with a Long Reach Module (SMLRM) + * @{table, + * -h Supported Data Rates + * -s Min ! Max ! Note + * - 9.8Gbps ! <10.6Gbps ! API Optimized range + * - 10.6Gbps ! <11.3Gbps ! Optional tuning could be applied + * - 11.3Gbps ! <12.5Gbps ! Optional tuning could be applied + * } + */ + CS_HSIO_EDC_MODE_SMLRM = 0x1000 +}; + +/* Settings used to compensate for trace loss on the board */ +enum e_cs4224_trace_loss { + /* For trace loss where trace loss <= 1dB */ + CS_HSIO_TRACE_LOSS_0dB, + + /* For trace loss where trace loss <= 2dB */ + CS_HSIO_TRACE_LOSS_1dB, + + /* For trace loss where 2dB < trace loss <= 3dB */ + CS_HSIO_TRACE_LOSS_2dB, + + /* For trace loss where 3dB < trace loss < 4dB */ + CS_HSIO_TRACE_LOSS_3dB, + + /* For trace loss where 4dB < trace loss <= 5dB */ + CS_HSIO_TRACE_LOSS_4dB, + + /* For trace loss where 5dB < trace loss <= 5.5dB */ + CS_HSIO_TRACE_LOSS_5dB, + + /* For trace loss where trace loss > 5.5dB */ + CS_HSIO_TRACE_LOSS_6dB, + + /* For trace loss where trace loss = 15dB */ + CS_HSIO_TRACE_LOSS_15dB, + + /* For trace loss where trace loss = 27dB */ + CS_HSIO_TRACE_LOSS_27dB, + + /* For CR4 cables */ + CS_HSIO_TRACE_LOSS_CR4, + + /* Special case for no-loss coax cables, for use in the lab */ + CS_HSIO_TRACE_LOSS_LAB, +}; + +/* Polarity Inversion bit map */ +enum e_cs4224_polarity_inv_t { + /* No polarity inversion */ + CS4224_POLARITY_INV_NONE = 0, + + /* Duplex host Tx driver polarity inversion */ + CS4224_POLARITY_INV_DPLX_HOST_TX = 1 << 0, + + /* Duplex line Tx driver polarity inversion */ + CS4224_POLARITY_INV_DPLX_LINE_TX = 1 << 1, + + /* Simplex Tx driver polarity inversion */ + CS4224_POLARITY_INV_SPLX_TX = 1 << 2, + + /* Duplex host Rx (digital, pre-FEC) polarity inversion */ + CS4224_POLARITY_INV_DPLX_HOST_RX = 1 << 3, + + /* Duplex line Rx (digital, pre-FEC) polarity inversion */ + CS4224_POLARITY_INV_DPLX_LINE_RX = 1 << 4, + + /* Simplex Rx (digital, pre-FEC) polarity inversion */ + CS4224_POLARITY_INV_SPLX_RX = 1 << 5, + +}; + +/* Determines which microsequencer to stall/un-stall */ +enum e_cs4224_mseq_id { + /* The simplex (line or host) microsequencer */ + CS4224_SPLX_MSEQ = 0, + + /* The duplex (line) microsequencer */ + CS4224_DPLX_LINE_MSEQ = 1, + + /* The duplex (host) microsequencer */ + CS4224_DPLX_HOST_MSEQ = 2, +}; + +/* Protection switch specific actions, note that for digital broadcast switching + * the 0 refers to the lower slice (even) of the protection pair, slice 1 the + * higher (odd). + */ +enum e_cs4224_switch_action_t { + /* disable switch */ + CS4224_SWITCH_DISABLE = 0, + + /* Duplex 2x2 switch from slices 0 to 1 and 1 to 0 bi-directionally */ + CS4224_SWITCH_DIGITAL_SWITCH_2x2 = 1, + /* Duplex 2x2 switch from slices 0 to 1 and 1 to 0 bi-directionally */ + CS4224_SWITCH_DUPLEX_SWITCH_2x2 = 1, + + /* Digital broadcast, Rx/Tx on slice 0 to 0 with line Tx only on 1 */ + CS4224_SWITCH_DIGITAL_BROADCAST_0_to_0 = 2, + /* Duplex broadcast, Rx/Tx on slice 0 to 0 with line Tx only on 1 */ + CS4224_SWITCH_DUPLEX_BROADCAST_0_to_0 = 2, + + /* Digital broadcast, Rx/Tx on slice 1 to 1 with line Tx only on 0 */ + CS4224_SWITCH_DIGITAL_BROADCAST_1_to_1 = 3, + CS4224_SWITCH_DUPLEX_BROADCAST_1_to_1 = 3, + + /* Digital broadcast, Rx/Tx on slice 0 to 1 with line Tx only on 0 */ + CS4224_SWITCH_DIGITAL_BROADCAST_0_to_1 = 4, + CS4224_SWITCH_DUPLEX_BROADCAST_0_to_1 = 4, + + /* Digital broadcast, Rx/Tx on slice 1 to 0 with line Tx only on 1 */ + CS4224_SWITCH_DIGITAL_BROADCAST_1_to_0 = 5, + CS4224_SWITCH_DUPLEX_BROADCAST_1_to_0 = 5, + + /* Simplex 2x2 switch of slice with mate */ + CS4224_SWITCH_SIMPLEX_SWITCH_2x2 = 6, + /* Analog 2x2 switch of slice with mate */ + CS4224_SWITCH_ANALOG_SWITCH_2x2 = 6, + + /* Simplex broadcast, transmits on slice and its mate */ + CS4224_SWITCH_SIMPLEX_BROADCAST = 7, + /* Analog broadcast, transmits on slice and its mate */ + CS4224_SWITCH_ANALOG_BROADCAST = 7, + +}; + +/* The CLKDIV_CTRL, SRX_DDIV_SEL dividers + * NOTE: There are accidentally two structures like this, the other is below + */ +enum e_cs4224_clkdiv_ddiv_t { + /* Rx serial clock div by 1 */ + CS4224_CLKDIV_DDIV_BY_1 = 0, + + /* Rx serial clock div by 2 */ + CS4224_CLKDIV_DDIV_BY_2 = 1, + + /* Rx serial clock div by 4 */ + CS4224_CLKDIV_DDIV_BY_4 = 2, + + /* Rx serial clock div by 8 */ + CS4224_CLKDIV_DDIV_BY_8 = 3, + + /* Rx serial clock div by 16 */ + CS4224_CLKDIV_DDIV_BY_16 = 4, + + /* Rx serial clock div by 32 */ + CS4224_CLKDIV_DDIV_BY_32 = 5, + + /* Rx serial clock div by 64 */ + CS4224_CLKDIV_DDIV_BY_64 = 6, + + /* Rx serial clock div by 128 */ + CS4224_CLKDIV_DDIV_BY_128 = 7, + +}; + +/* Divider for the clock rate for receive data path */ +enum e_cs4224_ddiv_divide { + /* Divide by 1 */ + CS4224_DDIV_DIV1 = 0, + + /* Divide by 2 */ + CS4224_DDIV_DIV2 = 1, + + /* Divide by 4 */ + CS4224_DDIV_DIV4 = 2, + + /* Divide by 8 */ + CS4224_DDIV_DIV8 = 3, + + /* Divide by 16 */ + CS4224_DDIV_DIV16 = 4, + + /* Divide by 32 */ + CS4224_DDIV_DIV32 = 5, + + /* Divide by 64 */ + CS4224_DDIV_DIV64 = 6, + + /* Divide by 128 */ + CS4224_DDIV_DIV128 = 7 +}; + +/* The CLKDIV_CTRL, SRX_RDIV_SEL dividers + * NOTE: There are accidentally two structures like this, the other is below + */ +enum e_cs4224_clkdiv_rdiv_t { + /* Rx serial clock div by 8 */ + CS4224_CLKDIV_RDIV_BY_8 = 0, + + /* Rx serial clock div by 16 */ + CS4224_CLKDIV_RDIV_BY_16 = 1, + + /* Rx serial clock div by 32 */ + CS4224_CLKDIV_RDIV_BY_32 = 2, + + /* Rx serial clock div by 40 */ + CS4224_CLKDIV_RDIV_BY_40 = 3, + + /* Rx serial clock div by 64 */ + CS4224_CLKDIV_RDIV_BY_64 = 4, + + /* Rx serial clock div by 66 */ + CS4224_CLKDIV_RDIV_BY_66 = 5, + + /* Rx serial clock div by 80 */ + CS4224_CLKDIV_RDIV_BY_80 = 6, + + /* Rx serial clock div by 100 */ + CS4224_CLKDIV_RDIV_BY_100 = 7, + + /* Rx serial clock div by 128 */ + CS4224_CLKDIV_RDIV_BY_128 = 8, +}; + +/* The serial clock divider to receive PFD + * for comparison to the clock reference. + */ +enum e_cs4224_rdiv_divide { + /* Rx serial clock div by 8 */ + CS4224_RDIV_DIV8 = 0, + + /* Rx serial clock div by 16 */ + CS4224_RDIV_DIV16 = 1, + + /* Rx serial clock div by 32 */ + CS4224_RDIV_DIV32 = 2, + + /* Rx serial clock div by 40 */ + CS4224_RDIV_DIV40 = 3, + + /* Rx serial clock div by 64 */ + CS4224_RDIV_DIV64 = 4, + + /* Rx serial clock div by 66 */ + CS4224_RDIV_DIV66 = 5, + + /* Rx serial clock div by 80 */ + CS4224_RDIV_DIV80 = 6, + + /* Rx serial clock div by 100 */ + CS4224_RDIV_DIV100 = 7, + + /* Rx serial clock div by 128 */ + CS4224_RDIV_DIV128 = 8, +}; + +/* Accumulator width options for the Fractional-N divider */ +enum e_cs4224_fracdiv_accumulator_width { + /* 8 bit accumulator */ + CS4224_FRACDIV_ACCUM_WIDTH_8BIT = 0, + + /* 16 bit accumulator */ + CS4224_FRACDIV_ACCUM_WIDTH_16BIT = 1, + + /* 24 bit accumulator */ + CS4224_FRACDIV_ACCUM_WIDTH_24BIT = 2, + + /* 32 bit accumulator */ + CS4224_FRACDIV_ACCUM_WIDTH_32BIT = 3, +}; + +/* The clock monitor clock source divider */ +enum e_cs4224_clk_mon_clksel_div { + /* Divide by 1 */ + CS4224_CLK_MON_DIV1 = 0, + + /* Divide by 4 */ + CS4224_CLK_MON_DIV4 = 1, + + /* Divide by 8 */ + CS4224_CLK_MON_DIV8 = 2, + + /* Divide by 16 */ + CS4224_CLK_MON_DIV16 = 3, +}; + +/* The per-port (pp) clock monitor clock source */ +enum e_cs4224_pp_clk_mon_clksel_src { + /* Clock source is SRX_CLK */ + CS4224_CLK_MON_PP_SRX = 0x00 << 2, + + /* Clock source is STX_CLK */ + CS4224_CLK_MON_PP_STX = 0x01 << 2, + + /* Clock source is SRX_CLK_LD */ + CS4224_CLK_MON_PP_CLK_LD = 0x02 << 2, + + /* Clock source is SRX_REF_LD */ + CS4224_CLK_MON_PP_REF_LD = 0x03 << 2, + + /* Clock source is SRX_FAST_CLK */ + CS4224_CLK_MON_PP_FAST = 0x04 << 2, + + /* Clock source is SRX_DIV32_OUT */ + CS4224_CLK_MON_PP_DIV32 = 0x05 << 2, + + /* Clock source is SRX_DIV80_OUT */ + CS4224_CLK_MON_PP_DIV80 = 0x06 << 2, + + /* Clock source is SRX_DIV64_OUT */ + CS4224_CLK_MON_PP_DIV64 = 0x07 << 2, + + /* Clock source is SRX_MON_CLK */ + CS4224_CLK_MON_PP_MON = 0x08 << 2, + + /* Clock source is no clock */ + CS4224_CLK_MON_PP_NO_CLK = 0x10 << 2, + + /* Clock source is reset dividers, output idle */ + CS4224_CLK_MON_PP_RESET = 0x3f, + +}; + +/* The global (gbl) clock monitor clock source */ +enum e_cs4224_gbl_clk_mon_clksel_src { + /* Clock source is process monitor */ + CS4224_CLK_MON_GBL_PMON = 0x00 << 2, + + /* Clock source is process monitor divided by 2 */ + CS4224_CLK_MON_GBL_PMOND2 = 0x01 << 2, + + /* Clock source is process monitor divided by 4 */ + CS4224_CLK_MON_GBL_PMOND4 = 0x02 << 2, + + /* Clock source is reference clock */ + CS4224_CLK_MON_GBL_REFCLK = 0x03 << 2, + + /* Clock source is clockless VCO clock */ + CS4224_CLK_MON_GBL_VCO = 0x04 << 2, + + /* Clock source is GPIO1 */ + CS4224_CLK_MON_GBL_GPIO1 = 0x06 << 2, + + /* Clock source is GPIO2 */ + CS4224_CLK_MON_GBL_GPIO2 = 0x07 << 2, + + /* Clock source is port pair 0 egress selected clock */ + CS4224_CLK_MON_GBL_PP0EGR = 0x08 << 2, + + /* Clock source is port pair 0 ingress selected clock */ + CS4224_CLK_MON_GBL_PP0ING = 0x09 << 2, + + /* Clock source is port pair 1 egress selected clock */ + CS4224_CLK_MON_GBL_PP1EGR = 0x0a << 2, + + /* Clock source is port pair 1 ingress selected clock */ + CS4224_CLK_MON_GBL_PP1ING = 0x0b << 2, + + /* Clock source is port pair 2 egress selected clock */ + CS4224_CLK_MON_GBL_PP2EGR = 0x0c << 2, + + /* Clock source is port pair 2 ingress selected clock */ + CS4224_CLK_MON_GBL_PP2ING = 0x0d << 2, + + /* Clock source is port pair 3 egress selected clock */ + CS4224_CLK_MON_GBL_PP3EGR = 0x0e << 2, + + /* Clock source is port pair 3 ingress selected clock */ + CS4224_CLK_MON_GBL_PP3ING = 0x0f << 2, + + /* Clock source is no clock */ + CS4224_CLK_MON_GBL_NO_CLK = 0x10 << 2, + + /* Clock source is reset dividers, output idle */ + CS4224_CLK_MON_GBL_RESET = 0x7f, +}; + +/* Used to select the driver being configured */ +enum e_cs4224_tx_driver_interface { + /* The host side transmitter */ + CS4224_TX_HOST_INTERFACE = 0, + + /* The line side transmitter */ + CS4224_TX_LINE_INTERFACE = 1, + + /* If in simplex mode this automatically + * determines the appropriate transmitter for the channel + */ + CS4224_TX_SIMPLEX_INTERFACE = 2, +}; + +/* PCS Monitor Status */ +struct cs4224_pcs_monitor_status_t { + /* PCS monitor reveiver state machine sync status */ + unsigned char sync; + + /* PCS monitor is in a high bit error state (XGPCS only) */ + unsigned int high_ber; +}; + +/* FEC Statistics */ +struct cs4224_fec_stats_t { + /* Number of FEC blocks transmitted by the line side Tx module */ + unsigned int tx_blk_total; + + /* Number of FEC blocks received (decoded) by the line side Rx module */ + unsigned int rx_blk_total; + + /* Number of FEC blocks successfully corrected by the Rx module */ + unsigned int rx_blk_corr; + + /* Number of FEC blocks unable to be corrected by the Rx module */ + unsigned int rx_blk_uncorr; + + /* Number of zero bit errors detected by the Rx module */ + unsigned int rx_zero_errs; + + /* Number of one bit errors detected by the Rx module */ + unsigned int rx_one_errs; +}; + +/* + * Configuration for the per-port (pp) clock monitor + * Use cs4224_pp_clk_mon_cfg_init() to initialize + */ +struct cs4224_pp_clk_mon_cfg_t { + /* Select the clock source divider */ + enum e_cs4224_clk_mon_clksel_div clksel_divider; + + /* Select the clock source */ + enum e_cs4224_pp_clk_mon_clksel_src clksel_src; + + /* Start counting flag */ + unsigned char go; + + /* Enable counter to free run */ + unsigned char free_run; + + /* Time duration to count */ + unsigned short duration; + + /* minimum count threshold */ + unsigned int min_thresh; + + /* maximum count threshold */ + unsigned int max_thresh; +}; + +/* Configuration for the global (gbl) clock monitor */ +struct cs4224_gbl_clk_mon_cfg_t { + /* Select the clock source divider */ + enum e_cs4224_clk_mon_clksel_div clksel_divider; + + /* Select the clock source */ + enum e_cs4224_gbl_clk_mon_clksel_src clksel_src; + + /* Start counting flag */ + unsigned char go; + + /* Enable counter to free run */ + unsigned char free_run; + + /* Time duration to count */ + unsigned short duration; + + /* minimum count threshold, 32 bits */ + unsigned short min_thresh_0; + unsigned short min_thresh_1; + + /* maximum count threshold, 32 bits */ + unsigned short max_thresh_0; + unsigned short max_thresh_1; +}; + +/* + * This structure is used to store state information + * that is used when enabling a 2x2 or broadcast + * switch. + */ +struct cs4224_switch_state_t { + /* The state of the line SRX0_RX_CLKOUT_CTRL register */ + unsigned short line_srx0_rx_clkout_ctrl; + + /* The state of the host SRX0_RX_CLKOUT_CTRL register */ + unsigned short host_srx0_rx_clkout_ctrl; + + /* The state of the line COMMON_STX0_MISC register */ + unsigned short line_stx0_misc; + + /* The state of the host COMMON_STX0_MISC register */ + unsigned short host_stx0_misc; + + /* The state of the line DSP_MSEQ_POWER_DOWN_LSB register */ + unsigned short line_mseq_power_down; + + /* The state of the host DSP_MSEQ_POWER_DOWN_LSB register */ + unsigned short host_mseq_power_down; + + /* The state of the line STX0_DRIVER_CONFIG register */ + unsigned short line_stx0_driver_config; + + /* The state of the host STX0_DRIVER_CONFIG register */ + unsigned short host_stx0_driver_config; + + /* The state of the line DSP_MSEQ_MAIL_SEL register */ + unsigned short line_dsp_mseq_mail_sel; + + /* The state of the host DSP_MSEQ_MAIL_SEL register */ + unsigned short host_dsp_mseq_mail_sel; + + /* The state of the host SRX0_VCO_CONFIG register */ + unsigned short host_srx0_vco_config; + + /* The state of the host SRX0_AGC_CONFIG1 register */ + unsigned short host_srx0_agc_config1; + + /* The state of the host SRX0_DFE_CONFIG register */ + unsigned short host_srx0_dfe_config; + + /* The state of the line SRX0_RX_CONFIG register */ + unsigned short line_srx0_rx_config; + + /* The state of the host SRX0_RX_CONFIG register */ + unsigned short host_srx0_rx_config; + + /* The state of the line MSEQ_SPARE12_LSB register */ + unsigned short line_spare12_lsb; + + /* The state of the host MSEQ_SPARE12_LSB register */ + unsigned short host_spare12_lsb; + + /* The state of the line MSEQ_SPARE26_LSB register */ + unsigned short line_spare26_lsb; +}; + +/* + * This structure is used to maintain device state when + * managing the duplex 2x2 protection switching. It must + * be initialized when the switch is first initialized and + * then gets passed to consecutive API calls to manage + * the h/w state. + */ +struct cs4224_switch_pair_state_t { + /* + * This flag is used to determine whether or not the + * switch state has been initialized. Before activating the + * switch for the first time this variable should be set to + * FALSE to ensure that the API knows that the state + * should be stored. + */ + unsigned char initialized; + + /* + * This flag is managed by the user to setup the switch in low + * latency mode. This bypasses the digital path through + * the chip and achieves the lowest possible latency. However + * it cannot be used when KR-AN or FC-AN are enabled + */ + unsigned char low_latency_switching; + + /* + * State space used to manage the two slices of + * the switch pair. This is managed automatically + * by the API. + */ + struct cs4224_switch_state_t slices[2]; + + /* + * For duplex switching on dual-die devices, write the switch config to + * both dies at the same time. + * + * Ignored for simplex switching. Only supported in superfast methods. + * Only relevant for the 8-port duplex devices. + * + * For which pairs will be set at the same time: + * + * @{table, + * -h Slice pairs that will be set when broadcast is enabled + * -s Die 1 ! Die 0 + * - 0/1 ! 6/7 + * - 2/3 ! 4/5 + * } + */ + unsigned char broadcast; +}; + +/* Configuration for the SyncE application */ +struct cs4224_rules_synce_config_t { + /* Enable SyncE */ + unsigned char enable; + + /* The core fracN integer divisor */ + unsigned short divisor; + + /* The core fracN numerator */ + unsigned int numerator; + + /* The clock divider */ + enum e_cs4224_clk_mon_clksel_div clk_divider; + + /* the GPIO to ouput the SyncE signal, + * range GPIO1 thru GPIO4 and GPIO_INTERR + */ + unsigned char gpio; + + /* the direction, line Rx or host Rx */ + enum e_cs4224_datapath_dir_t dir; +}; + +/* Configuration for the CDR frac-N's in the Rx and Tx interfaces */ +struct cs4224_rules_fracdiv_config_t { + /* Enable the fracN block */ + unsigned char enable; + + /* The integer divisor, 8 bits wide */ + unsigned short divisor; + + /* The numerator, 24bits wide */ + unsigned int numerator; + +}; + +/* Configuration rules for trace loss on the Rx or Tx interfaces */ +struct cs4224_rules_intf_t { + /* Trace loss setting */ + enum e_cs4224_trace_loss traceloss; +}; + +struct cs4224_advanced_rules_t { + unsigned char phsel_bypass; + unsigned short phsel_bypass_value; +}; + +/* Rx interface rules for device initialization */ +struct cs4224_rules_rx_if_t { + /* The EDC mode for the Rx interface (simplex only) */ + enum e_cs4224_edc_mode splx_edc_mode; + + /* The line EDC mode for the Rx interface (duplex only) */ + enum e_cs4224_edc_mode dplx_line_edc_mode; + + /* The host EDC mode for the Rx interface (duplex only) */ + enum e_cs4224_edc_mode dplx_host_edc_mode; + + /* Rx equalization rules (simplex only) */ + struct cs4224_rules_intf_t splx_eq; + + /* Rx line equalization rules (duplex only) */ + struct cs4224_rules_intf_t dplx_line_eq; + + /* Rx host equalization rules (duplex only) */ + struct cs4224_rules_intf_t dplx_host_eq; +}; + +/* Tx interface rules for device initialization */ +struct cs4224_rules_tx_if_t { + /* Disable the transmitter (simplex only) */ + unsigned char splx_disable; + + /* Disable the line transmitter (duplex only) */ + unsigned char dplx_line_disable; + + /* Disable the host transmitter (duplex only) */ + unsigned char dplx_host_disable; + + /* Tx driver initialization rules (simplex only) */ + struct cs4224_rules_intf_t splx_driver; + + /* Tx line driver initialization rules (duplex only) */ + struct cs4224_rules_intf_t dplx_line_driver; + + /* Tx host driver initialization rules (duplex only) */ + struct cs4224_rules_intf_t dplx_host_driver; + + /* power-down flag */ + unsigned char power_down; +}; + +/* Divider values for controlling CLKDIV_CTRL register */ +struct cs4224_rules_div_config_t { + /* Enable the manual CLKDIV_CTRL register updates */ + unsigned char enable; + + /* The SRX_RDIV_SEL divider */ + unsigned short rdiv; + + /* The SRX_DDIV_SEL divider */ + unsigned short ddiv; + + /* The SRX_FASTDIV_SEL divider */ + unsigned short fastdiv; +}; + +/* + * This structure is used to manage callback functions + * required during the initialization process. + */ +struct cs4224_callback_t { + /* Pointer to user data passed back to the callback */ + void *user_data; + + /* Pointer to the callback method */ + void *fcn_ptr; +}; + +/* KR-AN specific rules */ +struct cs4224_rules_kran_t { + /* The advertised supported datarates, + * see enum e_cs4224_kran_data_rates_t + */ + unsigned int data_rates; + + /* FEC ability flag (F0) */ + unsigned char fec_ability_f0; + + /* FEC requested flag (F1) */ + unsigned char fec_requested_f1; + + /* Pause ability flag (C0) */ + unsigned char pause_ability_c0; + + /* Pause ability flag (C1) */ + unsigned char pause_ability_c1; + + /* Remote Fault flag (D13) */ + unsigned char remote_fault_d13; + + /* Training enable flag */ + unsigned char allow_training; + + unsigned char wait_for_an_done; + + /* A callback method */ + struct cs4224_callback_t poll_kran_callback; + + /* Internal advanced settings */ + struct cs4224_kran_advanced_config_t_s advanced; +}; + +enum e_cs4224_fcan_data_rate_t { + /* 1 GE */ + CS4224_FCAN_DATA_RATE_1G = 0x1, + + /* 2 GE */ + CS4224_FCAN_DATA_RATE_2G = 0X2, + + /* 4 GE */ + CS4224_FCAN_DATA_RATE_4G = 0x4, + + /* 8 GE */ + CS4224_FCAN_DATA_RATE_8G = 0x8, + + /* 16 GE */ + CS4224_FCAN_DATA_RATE_16G = 0x10, + + /* Disabled - the default value for the negotiated_rate + * variable to prevent compilation problems + */ + CS4224_FCAN_DATA_RATE_DISABLED = 0, +}; + +enum e_cs4224_fcan_an_status_t { + /* FC-AN negotiated a data rate */ + CS4224_FCAN_AN_DONE = 0x1, + + /* FC-AN could not negotiate a data rate */ + CS4224_FCAN_AN_NOT_DONE = 0x2, +}; + +/* FC-AN VCO mode */ +enum e_cs4224_fcan_vco_mode_t { + /* VCO in PD mode (through-timing) */ + CS4224_FCAN_VCO_PD_MODE = 0, + + /* VCO in PFD mode (local-timing) */ + CS4224_FCAN_VCO_PFD_MODE, +}; + +/* FC-AN advanced rules for debugging */ +struct cs4224_fcan_advanced_t { + /* Set Main tap to Maximum */ + unsigned char enable_tp_main_tap_to_max; + + /* Turn on adaptive post */ + unsigned char enable_tp_adaptive_post; + + /* Send Preset at the begining of training */ + unsigned char enable_tp_send_preset; + + /* Send Init at the begining of training */ + unsigned char enable_tp_send_init; + + /* Force local_rx_ready initial condition */ + unsigned char enable_tp_frc_lcl_rx_ready; + + /* lp_status inital condition */ + unsigned char enable_tp_lp_status; + + /* Send hold inital condition */ + unsigned char enable_tp_send_hold; + + /* SWC in limits initial condition */ + unsigned char enable_tp_swc_in_limits; + + /* Jump to cal.asm during train_taps if LOL */ + unsigned char enable_jmp_to_caldotasm; + + /* Disable FCAN power-savings */ + unsigned char disable_fc_power_savings; + + /* When disabled, PCS sync not monitored on line side, testing only */ + unsigned char disable_pcs_checks; + + /* Enable training to work in the lab with no loss cables */ + unsigned char enable_no_loss; + + /* Start AN immediately after pre-AN config, default is TRUE */ + unsigned char start_an; +}; + +/* FC-AN specific rules */ +struct cs4224_rules_fcan_t { + unsigned short data_rates; + struct cs4224_callback_t poll_fcan_callback; + unsigned char wait_for_an_done; + enum e_cs4224_fcan_data_rate_t negotiated_rate; + unsigned char speed_negotiation_support; + unsigned char training_protocol_support; + unsigned char fec_capable; + unsigned char fec_request; + unsigned char transmitter_fixed; + struct cs4224_fcan_advanced_t advanced; +}; + +/* + * This structure defines the rules used to initialize the + * device. These rules serve as the high-level configuration + * switches that a user can adjust to control the behavior + * of the device(s). + */ +struct cs4224_rules_t { + enum e_cs4224_target_application application; + struct cs4224_rules_rx_if_t rx_if; + struct cs4224_rules_tx_if_t tx_if; + struct cs4224_rules_fcan_t fcan; + struct cs4224_rules_kran_t kran; + int ref_clk_rate; + struct cs4224_rules_div_config_t clkdiv; + struct cs4224_rules_fracdiv_config_t fracdiv; + struct cs4224_rules_synce_config_t synce; + unsigned char unsquelch_driver; + unsigned char tx_auto_squelch; + unsigned char enable_ac_decoupling_caps; + unsigned char show_debug_info; + unsigned char enable_power_savings; + unsigned char enable_fec; + enum e_cs4224_polarity_inv_t polarity_inv; + unsigned char enable_die_broadcast; + struct cs4224_advanced_rules_t advanced; + unsigned char mseq_dyn_reconfig; +}; + +/* VCO lock status */ +struct cs4224_vco_lock_status_t { + unsigned char rx_line_lock; + unsigned char rx_host_lock; +}; + +/* Struct to define a interface, used for methods that operate on multiple + * interfaces at a time (cs4224_wait_for_links_ready, etc) + */ +struct cs4224_interface_t { + unsigned int slice; + enum e_cs4224_mseq_id mseq_id; +}; + +typedef int(*cs4224_callback_lock)(unsigned int slice); +typedef int(*cs4224_callback_unlock)(unsigned int slice); + +/* Callback methods for implementing h/w locking */ +void cs4224_set_callback_for_lock(cs4224_callback_lock callback); +void cs4224_set_callback_for_unlock(cs4224_callback_unlock callback); + +void cs4224_reset_static_state(void); +void cs4224_reset_die_static_state(unsigned int die); + +unsigned int cs4224_get_die_from_slice( + unsigned int slice); + +int cs4224_reg_get_channel( + unsigned int slice, + unsigned int addr, + unsigned short *data); + +unsigned short cs4224_reg_read( + unsigned int slice, + unsigned int addr); + +int cs4224_reg_set_channel( + unsigned int channel, + unsigned int addr, + unsigned short data); + +int cs4224_reg_set_chk_channel( + unsigned int channel, + unsigned int addr, + unsigned short data); + +int cs4224_reg_get( + unsigned int die, + unsigned int addr, + unsigned short *data); + +int cs4224_reg_set( + unsigned int die, + unsigned int addr, + unsigned short data); + +int cs4224_lock( + unsigned int slice); + +int cs4224_unlock( + unsigned int slice); + +enum e_cs4224_hardware_id cs4224_hw_id( + unsigned int slice); + +unsigned char cs4224_is_hw_simplex(unsigned int slice); +unsigned char cs4224_is_hw_duplex(unsigned int slice); + +int cs4224_mon_volt_read_fixp( + unsigned int slice, + enum e_cs4224_mon_vlt_supply volt_source, + unsigned int *voltage); + +unsigned int cs4224_adj_pp( + unsigned int slice, + unsigned short addr); + +int cs4224_init_global_timer_fixp( + unsigned int slice, + unsigned int ref_clk_freq); + +unsigned int cs4224_adj_mseq( + unsigned int slice, + unsigned short addr); + +int cs4224_simplex_mate_slice( + unsigned int slice, + unsigned int *mate); + +unsigned char cs4224_line_rx_to_host_tx_dir( + unsigned int slice); + +int cs4224_version( + char *buffer, + unsigned int buffer_len); + +int cs4224_resync_elsto( + unsigned int slice, + unsigned short elsto_reg); + +int cs4224_init_vco( + unsigned int slice, + unsigned int addr); + +int cs4224_slice_change_rate_intf( + unsigned int slice, + enum e_cs4224_cfg_sides_t intf, + struct cs4224_rules_t *rules); + +int cs4224_rules_set_default( + enum e_cs4224_target_application application, + struct cs4224_rules_t *rules); + +int cs4224_slice_enter_operational_state( + unsigned int slice, + struct cs4224_rules_t *rules); + +int cs4224_get_mseq_id( + unsigned int slice, + enum e_cs4224_mseq_id *mseq_id); + +unsigned int cs4224_mseq_get_addr_offset( + unsigned int slice, + enum e_cs4224_mseq_id mseq); + +int cs4224_get_cfg_side( + unsigned int slice, + enum e_cs4224_cfg_sides_t *side); + +void cs4224_mseq_stall_set_delay(int us); +int cs4224_mseq_stall_get_delay(void); + +int cs4224_mseq_stall( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char stall); + +int cs4224_mseqs_stall( + struct cs4224_interface_t interfaces[], + unsigned short length, + unsigned char stall); + +int cs4224_mseq_enable_power_savings( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char enable); + +int cs4224_init_driver_settings( + unsigned int slice, + enum e_cs4224_tx_driver_interface intf, + unsigned short ctrla, + unsigned short ctrlb); + +int cs4224_config_polarity_inv_points( + unsigned int slice, + unsigned short inv_points); + +int cs4224_enable_polarity_inv( + unsigned int slice, + struct cs4224_rules_t *rules); + +int cs4224_query_polarity_inv( + unsigned int slice, + unsigned short *inv_points); + +int cs4224_debug_dump_polarity_inv( + unsigned int slice); + +void cs4224_pp_clk_mon_cfg_init( + struct cs4224_pp_clk_mon_cfg_t *clk_mon_cfg); + +int cs4224_pp_clock_monitor( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + struct cs4224_pp_clk_mon_cfg_t *clk_mon_cfg); + +int cs4224_pp_clock_monitor_freq_fixp( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + struct cs4224_pp_clk_mon_cfg_t *pp_clk_mon_cfg, + unsigned int ref_clk_rate, + unsigned short *freq); + +int cs4224_gbl_clock_monitor( + unsigned int slice, + struct cs4224_gbl_clk_mon_cfg_t *clk_mon_cfg); + +int cs4224_fracdiv_core_init( + unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned short divisor, + unsigned int numerator); + +int cs4224_fracdiv_cdr_init( + unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned short divisor, + unsigned int numerator); + +int cs4224_slice_soft_reset( + unsigned int slice); + +int cs4224_slice_soft_reset_intf( + unsigned int slice, + enum e_cs4224_cfg_sides_t intf); + +int cs4224_mseq_squelch_ctrl( + unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned char enable); + +int cs4224_send_squelch_request( + unsigned int slice, + enum e_cs4224_datapath_dir_t dir, + unsigned char squelch); + +int cs4224_squelch_driver( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + unsigned char squelch); + +int cs4224_hard_reset_die(unsigned int die); +int cs4224_hard_reset(unsigned int slice); + +void cs4224_debug_ucode_show_version(unsigned int slice); + +int cs4224_mux_enable( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + unsigned char enable); + +int cs4224_demux_enable( + unsigned int slice, + enum e_cs4224_cfg_sides_t side, + unsigned char enable); + +int cs4224_init_edc_mode_set( + unsigned int slice, + struct cs4224_rules_t *rules); + +int cs4224_init_edc_mode_intf( + unsigned int slice, + struct cs4224_rules_t *rules, + enum e_cs4224_mseq_id intf); + +unsigned char cs4224_is_eeprom_finished(unsigned int die); + +int cs4224_wait_for_eeprom_finished( + unsigned int die, + unsigned int max_iterations, + unsigned int ms_delay_between_iterations); + +int cs4224_restore_powered_down_regs(unsigned int slice); + +int cs4224_slice_power_down( + unsigned int slice); + +int cs4224_save_edc_mode( + unsigned int slice, + unsigned short reg_offset, + enum e_cs4224_edc_mode edc_mode); + +int cs4224_query_edc_mode( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + enum e_cs4224_edc_mode *edc_mode); + +int cs4224_query_mseq_is_stalled( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char *stalled); + +int cs4224_query_mseq_power_savings( + unsigned int slice, + enum e_cs4224_mseq_id mseq_id, + unsigned char *enabled); + +const char *cs4224_translate_edc_mode(enum e_cs4224_edc_mode edc_mode); +const char *cs4224_translate_app_mode( + enum e_cs4224_target_application app_mode); +const char *cs4224_switch_translate_state( + enum e_cs4224_switch_action_t state); +const char *cs4224_translate_cfg_side(enum e_cs4224_cfg_sides_t side); +int cs4224_check_rules(unsigned int slice, struct cs4224_rules_t *rules); +unsigned int cs4224_query_data_rate(const struct cs4224_rules_t *rules); + +int cs4224_ucode_data_prgm_image( + unsigned int slice, + unsigned short microcode[], + unsigned int len_buffer); + +int cs4224_ucode_data_prgm_image_broadcast( + unsigned int slice, + unsigned short microcode[], + unsigned int len_buffer); + +void cs4223_glue_phydev_set(struct phy_device *phydev); + +#endif /* __CORTINA_API_H_ */ diff --git a/include/dm/device.h b/include/dm/device.h index bb9faa0ed93..8f015450293 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -67,6 +67,9 @@ struct driver_info; /* Driver plat has been read. Cleared when the device is removed */ #define DM_FLAG_PLATDATA_VALID (1 << 12) +/* DM should ignore the assign default clocks for this driver */ +#define DM_FLAG_IGNORE_DEFAULT_CLKS (1 << 13) + /* * Device is removed without switching off its power domain. This might * be required, i. e. for serial console (debug) output when booting OS. @@ -343,6 +346,7 @@ struct driver { int (*child_post_bind)(struct udevice *dev); int (*child_pre_probe)(struct udevice *dev); int (*child_post_remove)(struct udevice *dev); + int (*handle_interrupts)(struct udevice *dev); int priv_auto; int plat_auto; int per_child_auto; diff --git a/include/dm/of_extra.h b/include/dm/of_extra.h index ca15df21b06..f54f0ed3aa5 100644 --- a/include/dm/of_extra.h +++ b/include/dm/of_extra.h @@ -86,4 +86,24 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type, const char *suffix, fdt_addr_t *basep, fdt_size_t *sizep); +/** + * ofnode_phy_is_fixed_link() - Detect fixed-link pseudo-PHY device + * + * This function detects whether the ethernet controller connects to a + * fixed-link pseudo-PHY device. + * + * This function supports the following two DT bindings: + * - the new DT binding, where 'fixed-link' is a sub-node of the + * Ethernet device + * - the old DT binding, where 'fixed-link' is a property with 5 + * cells encoding various information about the fixed PHY + * + * If both new and old bindings exist, the new one is preferred. + * + * @param eth_node ofnode containing the fixed-link subnode/property + * @param phy_node if fixed-link PHY detected, containing the PHY ofnode + * @return true if a fixed-link pseudo-PHY device exists, false otherwise + */ +bool ofnode_phy_is_fixed_link(ofnode eth_node, ofnode *phy_node); + #endif diff --git a/include/dm/simple_bus.h b/include/dm/simple_bus.h index 4ad4cc4051d..b7104013c05 100644 --- a/include/dm/simple_bus.h +++ b/include/dm/simple_bus.h @@ -7,9 +7,9 @@ #define __DM_SIMPLE_BUS_H struct simple_bus_plat { - u32 base; - u32 size; - u32 target; + fdt_addr_t base; + fdt_size_t size; + fdt_addr_t target; }; #endif diff --git a/include/dsi_host.h b/include/dsi_host.h index 9dfc7b36872..22a6cd3b43b 100644 --- a/include/dsi_host.h +++ b/include/dsi_host.h @@ -70,4 +70,12 @@ int dsi_host_init(struct udevice *dev, */ int dsi_host_enable(struct udevice *dev); +/** + * dsi_host_disable + * + * @dev: dsi host device + * @return 0 if OK, -ve on error + */ +int dsi_host_disable(struct udevice *dev); + #endif diff --git a/include/dt-bindings/clock/imx6qdl-clock.h b/include/dt-bindings/clock/imx6qdl-clock.h index 29050337d9d..2a25fdb2d9b 100644 --- a/include/dt-bindings/clock/imx6qdl-clock.h +++ b/include/dt-bindings/clock/imx6qdl-clock.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -269,6 +269,15 @@ #define IMX6QDL_CLK_PRG0_APB 256 #define IMX6QDL_CLK_PRG1_APB 257 #define IMX6QDL_CLK_PRE_AXI 258 -#define IMX6QDL_CLK_END 259 +#define IMX6QDL_CLK_MLB_SEL 259 +#define IMX6QDL_CLK_MLB_PODF 260 +#define IMX6QDL_CLK_AXI_ALT_SEL 261 +#define IMX6QDL_CLK_LDB_DI0_DIV_7 262 +#define IMX6QDL_CLK_LDB_DI1_DIV_7 263 +#define IMX6QDL_CLK_LDB_DI0_DIV_SEL 264 +#define IMX6QDL_CLK_LDB_DI1_DIV_SEL 265 +#define IMX6QDL_CLK_DCIC1 266 +#define IMX6QDL_CLK_DCIC2 267 +#define IMX6QDL_CLK_END 268 #endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */ diff --git a/include/dt-bindings/clock/imx6sll-clock.h b/include/dt-bindings/clock/imx6sll-clock.h index 39c25671d67..22493cf47aa 100644 --- a/include/dt-bindings/clock/imx6sll-clock.h +++ b/include/dt-bindings/clock/imx6sll-clock.h @@ -198,7 +198,8 @@ #define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 #define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 #define IMX6SLL_CLK_EXTERN_AUDIO 172 +#define IMX6SLL_CLK_GPT_3M 173 -#define IMX6SLL_CLK_END 173 +#define IMX6SLL_CLK_END 174 #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index b2325d3e236..89eadb96da2 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -1,5 +1,6 @@ /* * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -168,7 +169,7 @@ #define IMX7D_SPDIF_ROOT_SRC 155 #define IMX7D_SPDIF_ROOT_CG 156 #define IMX7D_SPDIF_ROOT_DIV 157 -#define IMX7D_ENET1_REF_ROOT_CLK 158 +#define IMX7D_ENET1_IPG_ROOT_CLK 158 #define IMX7D_ENET1_REF_ROOT_SRC 159 #define IMX7D_ENET1_REF_ROOT_CG 160 #define IMX7D_ENET1_REF_ROOT_DIV 161 @@ -176,7 +177,7 @@ #define IMX7D_ENET1_TIME_ROOT_SRC 163 #define IMX7D_ENET1_TIME_ROOT_CG 164 #define IMX7D_ENET1_TIME_ROOT_DIV 165 -#define IMX7D_ENET2_REF_ROOT_CLK 166 +#define IMX7D_ENET2_IPG_ROOT_CLK 166 #define IMX7D_ENET2_REF_ROOT_SRC 167 #define IMX7D_ENET2_REF_ROOT_CG 168 #define IMX7D_ENET2_REF_ROOT_DIV 169 @@ -455,5 +456,8 @@ #define IMX7D_SNVS_CLK 442 #define IMX7D_CAAM_CLK 443 #define IMX7D_KPP_ROOT_CLK 444 -#define IMX7D_CLK_END 445 +#define IMX7D_PXP_IPG_CLK 445 +#define IMX7D_PXP_AXI_CLK 446 +#define IMX7D_CLK_END 447 + #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/clock/imx8mp-clock.h b/include/dt-bindings/clock/imx8mp-clock.h index e8d68fbb6e3..3784cbbc75f 100644 --- a/include/dt-bindings/clock/imx8mp-clock.h +++ b/include/dt-bindings/clock/imx8mp-clock.h @@ -322,68 +322,155 @@ #define IMX8MP_CLK_HSIO_AXI 311 #define IMX8MP_CLK_MEDIA_ISP 312 -#define IMX8MP_CLK_END 313 +#define IMX8MP_CLK_MEDIA_DISP2_PIX 313 +#define IMX8MP_CLK_MEDIA_LDB_ROOT 314 +#define IMX8MP_CLK_AUDIO_AHB_ROOT 315 +#define IMX8MP_CLK_AUDIO_AXI_ROOT 316 +#define IMX8MP_CLK_SAI1_ROOT 317 +#define IMX8MP_CLK_SAI2_ROOT 318 +#define IMX8MP_CLK_SAI3_ROOT 319 +#define IMX8MP_CLK_SAI5_ROOT 320 +#define IMX8MP_CLK_SAI6_ROOT 321 +#define IMX8MP_CLK_SAI7_ROOT 322 +#define IMX8MP_CLK_PDM_ROOT 323 -#define IMX8MP_CLK_AUDIOMIX_SAI1_IPG 0 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1 1 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2 2 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3 3 -#define IMX8MP_CLK_AUDIOMIX_SAI2_IPG 4 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1 5 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2 6 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3 7 -#define IMX8MP_CLK_AUDIOMIX_SAI3_IPG 8 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1 9 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2 10 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3 11 -#define IMX8MP_CLK_AUDIOMIX_SAI5_IPG 12 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1 13 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2 14 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3 15 -#define IMX8MP_CLK_AUDIOMIX_SAI6_IPG 16 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1 17 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2 18 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3 19 -#define IMX8MP_CLK_AUDIOMIX_SAI7_IPG 20 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1 21 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2 22 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3 23 -#define IMX8MP_CLK_AUDIOMIX_ASRC_IPG 24 -#define IMX8MP_CLK_AUDIOMIX_PDM_IPG 25 -#define IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT 26 -#define IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT 27 -#define IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT 28 -#define IMX8MP_CLK_AUDIOMIX_DSP_ROOT 29 -#define IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT 30 -#define IMX8MP_CLK_AUDIOMIX_EARC_IPG 31 -#define IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG 32 -#define IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG 33 -#define IMX8MP_CLK_AUDIOMIX_EDMA_ROOT 34 -#define IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT 35 -#define IMX8MP_CLK_AUDIOMIX_MU2_ROOT 36 -#define IMX8MP_CLK_AUDIOMIX_MU3_ROOT 37 -#define IMX8MP_CLK_AUDIOMIX_EARC_PHY 38 -#define IMX8MP_CLK_AUDIOMIX_PDM_ROOT 39 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1_SEL 40 -#define IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2_SEL 41 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1_SEL 42 -#define IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2_SEL 43 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1_SEL 44 -#define IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2_SEL 45 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK1_SEL 46 -#define IMX8MP_CLK_AUDIOMIX_SAI4_MCLK2_SEL 47 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1_SEL 48 -#define IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2_SEL 49 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1_SEL 50 -#define IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2_SEL 51 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1_SEL 52 -#define IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2_SEL 53 -#define IMX8MP_CLK_AUDIOMIX_PDM_SEL 54 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_REF_SEL 55 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL 56 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_BYPASS 57 -#define IMX8MP_CLK_AUDIOMIX_SAI_PLL_OUT 58 +#define IMX8MP_SAI1_MCLK 324 +#define IMX8MP_SAI2_MCLK 325 +#define IMX8MP_SAI3_MCLK 326 +#define IMX8MP_SAI4_MCLK 327 +#define IMX8MP_SAI5_MCLK 328 +#define IMX8MP_SAI6_MCLK 329 +#define IMX8MP_SAI7_MCLK 330 -#define IMX8MP_CLK_AUDIOMIX_END 59 +#define IMX8MP_CLK_END 331 + +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_IPG 0 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1 1 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2 2 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK3 3 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_IPG 4 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1 5 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2 6 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK3 7 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_IPG 8 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1 9 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2 10 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK3 11 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_IPG 12 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1 13 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2 14 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK3 15 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_IPG 16 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1 17 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2 18 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK3 19 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_IPG 20 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1 21 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2 22 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK3 23 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_ASRC_IPG 24 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_IPG 25 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SDMA3_ROOT 27 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SPBA2_ROOT 28 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_DSP_ROOT 29 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_DSPDBG_ROOT 30 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_IPG 31 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_OCRAMA_IPG 32 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_AUD2HTX_IPG 33 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_EDMA_ROOT 34 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_AUDPLL_ROOT 35 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_MU2_ROOT 36 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_MU3_ROOT 37 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_EARC_PHY 38 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_ROOT 39 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK1_SEL 40 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI1_MCLK2_SEL 41 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK1_SEL 42 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI2_MCLK2_SEL 43 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK1_SEL 44 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI3_MCLK2_SEL 45 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI4_MCLK1_SEL 46 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI4_MCLK2_SEL 47 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK1_SEL 48 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI5_MCLK2_SEL 49 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK1_SEL 50 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI6_MCLK2_SEL 51 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK1_SEL 52 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI7_MCLK2_SEL 53 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_PDM_SEL 54 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_REF_SEL 55 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL 56 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_BYPASS 57 +#define IMX8MP_CLK_AUDIO_BLK_CTRL_SAI_PLL_OUT 58 + +#define IMX8MP_CLK_AUDIO_BLK_CTRL_END 59 + +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_APB_CLK 0 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_B_CLK 1 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_REF266M_CLK 2 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL24M_CLK 3 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_XTAL32K_CLK 4 +#define IMX8MP_CLK_HDMI_BLK_CTRL_GLOBAL_TX_PIX_CLK 5 +#define IMX8MP_CLK_HDMI_BLK_CTRL_IRQS_STEER_CLK 6 +#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDMI_CLK 7 +#define IMX8MP_CLK_HDMI_BLK_CTRL_NOC_HDCP_CLK 8 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_APB_CLK 9 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_B_CLK 10 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PDI_CLK 11 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_PIX_CLK 12 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_SPU_CLK 13 +#define IMX8MP_CLK_HDMI_BLK_CTRL_FDCC_REF_CLK 14 +#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_APB_CLK 15 +#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_B_CLK 16 +#define IMX8MP_CLK_HDMI_BLK_CTRL_HRV_MWR_CEA_CLK 17 +#define IMX8MP_CLK_HDMI_BLK_CTRL_VSFD_CEA_CLK 18 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_HPI_CLK 19 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_APB_CLK 20 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_CEC_CLK 21 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_ESM_CLK 22 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_GPA_CLK 23 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIXEL_CLK 24 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SFR_CLK 25 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SKP_CLK 26 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PREP_CLK 27 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_APB_CLK 28 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PHY_INT_CLK 29 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_SEC_MEM_CLK 30 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_SKP_CLK 31 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_VID_LINK_PIX_CLK 32 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_TRNG_APB_CLK 33 +#define IMX8MP_CLK_HDMI_BLK_CTRL_HTXPHY_CLK_SEL 34 +#define IMX8MP_CLK_HDMI_BLK_CTRL_LCDIF_CLK_SEL 35 +#define IMX8MP_CLK_HDMI_BLK_CTRL_TX_PIPE_CLK_SEL 36 + +#define IMX8MP_CLK_HDMI_BLK_CTRL_END 37 + +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_PCLK 0 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI_CLKREF 1 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_PCLK 2 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI_ACLK 3 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_PIXEL 4 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_APB 5 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_PROC 6 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISI_APB 7 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_BUS_BLK 8 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_PCLK 9 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_CSI2_ACLK 10 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_PIXEL 11 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_APB 12 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_COR 13 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AXI 14 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP1_AHB 15 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_COR 16 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AXI 17 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_ISP0_AHB 18 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_COR 19 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AXI 20 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_DWE_AHB 21 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_MIPI_DSI2 22 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF_AXI 23 +#define IMX8MP_CLK_MEDIA_BLK_CTRL_LCDIF2_AXI 24 + +#define IMX8MP_CLK_MEDIA_BLK_CTRL_END 25 #endif diff --git a/include/dt-bindings/clock/imx8mq-clock.h b/include/dt-bindings/clock/imx8mq-clock.h index 9b8045d75b8..4724f0978a3 100644 --- a/include/dt-bindings/clock/imx8mq-clock.h +++ b/include/dt-bindings/clock/imx8mq-clock.h @@ -431,6 +431,8 @@ #define IMX8MQ_CLK_A53_CORE 289 -#define IMX8MQ_CLK_END 290 +#define IMX8MQ_CLK_PHY_27MHZ 290 + +#define IMX8MQ_CLK_END 291 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */ diff --git a/include/dt-bindings/clock/imx8qm-clock.h b/include/dt-bindings/clock/imx8qm-clock.h index 58de976e638..3d3afe0e2c4 100644 --- a/include/dt-bindings/clock/imx8qm-clock.h +++ b/include/dt-bindings/clock/imx8qm-clock.h @@ -841,6 +841,16 @@ #define IMX8QM_AUD_DSP_CORE_CLK 794 #define IMX8QM_AUD_OCRAM_IPG 795 -#define IMX8QM_CLK_END 796 +/* MIPI DSI */ +#define IMX8QM_MIPI0_DSI_PHY_DIV 796 +#define IMX8QM_MIPI0_DSI_PHY_CLK 797 +#define IMX8QM_MIPI1_DSI_PHY_DIV 798 +#define IMX8QM_MIPI1_DSI_PHY_CLK 799 + +#define IMX8QM_SDHC0_AHB_CLK 800 +#define IMX8QM_SDHC1_AHB_CLK 801 +#define IMX8QM_SDHC2_AHB_CLK 802 + +#define IMX8QM_CLK_END 813 #endif /* __DT_BINDINGS_CLOCK_IMX8QM_H */ diff --git a/include/dt-bindings/clock/imx8qxp-clock.h b/include/dt-bindings/clock/imx8qxp-clock.h index d0334ea3988..aa95ed33413 100644 --- a/include/dt-bindings/clock/imx8qxp-clock.h +++ b/include/dt-bindings/clock/imx8qxp-clock.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 NXP + * Copyright 2018-2020 NXP */ #ifndef __DT_BINDINGS_CLOCK_IMX8QXP_H @@ -298,11 +298,8 @@ #define IMX8QXP_MIPI0_I2C1_DIV 274 #define IMX8QXP_MIPI0_I2C0_CLK 275 #define IMX8QXP_MIPI0_I2C1_CLK 276 -#define IMX8QXP_MIPI0_I2C0_IPG_S_CLK 277 #define IMX8QXP_MIPI0_I2C0_IPG_CLK 278 -#define IMX8QXP_MIPI0_I2C1_IPG_S_CLK 279 #define IMX8QXP_MIPI0_I2C1_IPG_CLK 280 -#define IMX8QXP_MIPI0_PWM_IPG_S_CLK 281 #define IMX8QXP_MIPI0_PWM_IPG_CLK 282 #define IMX8QXP_MIPI0_PWM_32K_CLK 283 #define IMX8QXP_MIPI0_GPIO_IPG_CLK 284 @@ -499,11 +496,8 @@ #define IMX8QXP_MIPI1_I2C1_DIV 461 #define IMX8QXP_MIPI1_I2C0_CLK 462 #define IMX8QXP_MIPI1_I2C1_CLK 463 -#define IMX8QXP_MIPI1_I2C0_IPG_S_CLK 464 #define IMX8QXP_MIPI1_I2C0_IPG_CLK 465 -#define IMX8QXP_MIPI1_I2C1_IPG_S_CLK 466 #define IMX8QXP_MIPI1_I2C1_IPG_CLK 467 -#define IMX8QXP_MIPI1_PWM_IPG_S_CLK 468 #define IMX8QXP_MIPI1_PWM_IPG_CLK 469 #define IMX8QXP_MIPI1_PWM_32K_CLK 470 #define IMX8QXP_MIPI1_GPIO_IPG_CLK 471 @@ -579,5 +573,28 @@ #define IMX8QXP_LSIO_MU5A_IPG_S_CLK 528 #define IMX8QXP_LSIO_MU5A_IPG_CLK 529 -#define IMX8QXP_CLK_END 530 + +/* LCD part2 */ +#define IMX8QXP_LCD_PXL_BYPASS_DIV 530 +#define IMX8QXP_LCD_PXL_SEL 531 +#define IMX8QXP_LCD_PXL_DIV 532 +#define IMX8QXP_LCD_PXL_CLK 533 +#define IMX8QXP_ELCDIF_PLL_DIV 534 +#define IMX8QXP_ELCDIF_PLL 535 +#define IMX8QXP_LCD_SEL 536 + +#define IMX8DXL_EQOS_MEM_CLK 537 +#define IMX8DXL_EQOS_ACLK 538 +#define IMX8DXL_EQOS_CSR_CLK 539 +#define IMX8DXL_EQOS_CLK 540 +#define IMX8DXL_EQOS_PTP_CLK_S 541 +#define IMX8DXL_EQOS_PTP_CLK 542 + +#define IMX8DXL_USB2_PHY2_IPG_CLK 543 + +#define IMX8QXP_SDHC0_AHB_CLK 544 +#define IMX8QXP_SDHC1_AHB_CLK 545 +#define IMX8QXP_SDHC2_AHB_CLK 546 + +#define IMX8DXL_CLK_END 547 #endif /* __DT_BINDINGS_CLOCK_IMX8QXP_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8dxl.h b/include/dt-bindings/pinctrl/pads-imx8dxl.h new file mode 100644 index 00000000000..3bf686050a8 --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8dxl.h @@ -0,0 +1,662 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +/*! + * Header file used to configure SoC pad list. + */ + +#ifndef SC_PADS_H +#define SC_PADS_H + +/* Includes */ + +/* Defines */ + +/*! + * @name Pad Definitions + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B 0 /* HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00, LSIO.GPIO7.IO00 */ +#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /* HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01, LSIO.GPIO7.IO01 */ +#define SC_P_PCIE_CTRL0_WAKE_B 2 /* HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02, LSIO.GPIO7.IO02 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /* */ +#define SC_P_USB_SS3_TC0 4 /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03, LSIO.GPIO7.IO03 */ +#define SC_P_USB_SS3_TC1 5 /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04, LSIO.GPIO7.IO04 */ +#define SC_P_USB_SS3_TC2 6 /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05, LSIO.GPIO7.IO05 */ +#define SC_P_USB_SS3_TC3 7 /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06, LSIO.GPIO7.IO06 */ +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /* */ +#define SC_P_EMMC0_CLK 9 /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ +#define SC_P_EMMC0_CMD 10 /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ +#define SC_P_EMMC0_DATA0 11 /* CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */ +#define SC_P_EMMC0_DATA1 12 /* CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */ +#define SC_P_EMMC0_DATA2 13 /* CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */ +#define SC_P_EMMC0_DATA3 14 /* CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */ +#define SC_P_EMMC0_DATA4 15 /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.GPIO4.IO13 */ +#define SC_P_EMMC0_DATA5 16 /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.GPIO4.IO14 */ +#define SC_P_EMMC0_DATA6 17 /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.GPIO4.IO15 */ +#define SC_P_EMMC0_DATA7 18 /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.GPIO4.IO16 */ +#define SC_P_EMMC0_STROBE 19 /* CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.GPIO4.IO17 */ +#define SC_P_EMMC0_RESET_B 20 /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 21 /* */ +#define SC_P_USDHC1_RESET_B 22 /* CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, CONN.NAND.WE_B, LSIO.GPIO4.IO19, LSIO.GPIO7.IO08 */ +#define SC_P_USDHC1_VSELECT 23 /* CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20, LSIO.GPIO7.IO09 */ +#define SC_P_CTL_NAND_RE_P_N 24 /* */ +#define SC_P_USDHC1_WP 25 /* CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, CONN.NAND.ALE, LSIO.GPIO4.IO21, LSIO.GPIO7.IO10 */ +#define SC_P_USDHC1_CD_B 26 /* CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22, LSIO.GPIO7.IO11 */ +#define SC_P_CTL_NAND_DQS_P_N 27 /* */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 28 /* */ +#define SC_P_ENET0_RGMII_TXC 29 /* CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29, CONN.USDHC2.CLK */ +#define SC_P_ENET0_RGMII_TX_CTL 30 /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30, CONN.USDHC2.CMD */ +#define SC_P_ENET0_RGMII_TXD0 31 /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31, CONN.USDHC2.DATA0 */ +#define SC_P_ENET0_RGMII_TXD1 32 /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00, CONN.USDHC2.DATA1 */ +#define SC_P_ENET0_RGMII_TXD2 33 /* CONN.ENET0.RGMII_TXD2, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01, CONN.USDHC2.DATA2 */ +#define SC_P_ENET0_RGMII_TXD3 34 /* CONN.ENET0.RGMII_TXD3, CONN.NAND.RE_B, LSIO.GPIO5.IO02, CONN.USDHC2.DATA3 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35 /* */ +#define SC_P_ENET0_RGMII_RXC 36 /* CONN.ENET0.RGMII_RXC, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ +#define SC_P_ENET0_RGMII_RX_CTL 37 /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */ +#define SC_P_ENET0_RGMII_RXD0 38 /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 39 /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RXD2 40 /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ +#define SC_P_ENET0_RGMII_RXD3 41 /* CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 42 /* */ +#define SC_P_ENET0_REFCLK_125M_25M 43 /* CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.EQOS.PPS_IN, CONN.EQOS.PPS_OUT, LSIO.GPIO5.IO09 */ +#define SC_P_ENET0_MDIO 44 /* CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.EQOS.MDIO, LSIO.GPIO5.IO10, LSIO.GPIO7.IO16 */ +#define SC_P_ENET0_MDC 45 /* CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.EQOS.MDC, LSIO.GPIO5.IO11, LSIO.GPIO7.IO17 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 46 /* */ +#define SC_P_ENET1_RGMII_TXC 47 /* LSIO.GPIO0.IO00, CONN.EQOS.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.EQOS.RGMII_TXC, CONN.EQOS.RCLK50M_IN */ +#define SC_P_ENET1_RGMII_TXD2 48 /* , ADMA.LCDIF.D01, CONN.EQOS.RGMII_TXD2, LSIO.GPIO0.IO01 */ +#define SC_P_ENET1_RGMII_TX_CTL 49 /* , ADMA.LCDIF.D02, CONN.EQOS.RGMII_TX_CTL, LSIO.GPIO0.IO02 */ +#define SC_P_ENET1_RGMII_TXD3 50 /* , ADMA.LCDIF.D03, CONN.EQOS.RGMII_TXD3, LSIO.GPIO0.IO03 */ +#define SC_P_ENET1_RGMII_RXC 51 /* , ADMA.LCDIF.D04, CONN.EQOS.RGMII_RXC, LSIO.GPIO0.IO04 */ +#define SC_P_ENET1_RGMII_RXD3 52 /* , ADMA.LCDIF.D05, CONN.EQOS.RGMII_RXD3, LSIO.GPIO0.IO05 */ +#define SC_P_ENET1_RGMII_RXD2 53 /* , ADMA.LCDIF.D06, CONN.EQOS.RGMII_RXD2, LSIO.GPIO0.IO06, LSIO.GPIO6.IO00 */ +#define SC_P_ENET1_RGMII_RXD1 54 /* , ADMA.LCDIF.D07, CONN.EQOS.RGMII_RXD1, LSIO.GPIO0.IO07, LSIO.GPIO6.IO01 */ +#define SC_P_ENET1_RGMII_TXD0 55 /* , ADMA.LCDIF.D08, CONN.EQOS.RGMII_TXD0, LSIO.GPIO0.IO08, LSIO.GPIO6.IO02 */ +#define SC_P_ENET1_RGMII_TXD1 56 /* , ADMA.LCDIF.D09, CONN.EQOS.RGMII_TXD1, LSIO.GPIO0.IO09, LSIO.GPIO6.IO03 */ +#define SC_P_ENET1_RGMII_RXD0 57 /* ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.EQOS.RGMII_RXD0, LSIO.GPIO0.IO10, LSIO.GPIO6.IO04 */ +#define SC_P_ENET1_RGMII_RX_CTL 58 /* ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.EQOS.RGMII_RX_CTL, LSIO.GPIO0.IO11, LSIO.GPIO6.IO05 */ +#define SC_P_ENET1_REFCLK_125M_25M 59 /* ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.EQOS.REFCLK_125M_25M, LSIO.GPIO0.IO12, LSIO.GPIO6.IO06 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 60 /* */ +#define SC_P_SPI3_SCK 61 /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13, ADMA.LCDIF.D00 */ +#define SC_P_SPI3_SDO 62 /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14, ADMA.LCDIF.D01 */ +#define SC_P_SPI3_SDI 63 /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15, ADMA.LCDIF.D02 */ +#define SC_P_SPI3_CS0 64 /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16, ADMA.LCDIF.CS */ +#define SC_P_SPI3_CS1 65 /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16, ADMA.LCDIF.RD_E */ +#define SC_P_MCLK_IN1 66 /* ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17, ADMA.LCDIF.D03 */ +#define SC_P_MCLK_IN0 67 /* ADMA.ACM.MCLK_IN0, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19, ADMA.LCDIF.RS */ +#define SC_P_MCLK_OUT0 68 /* ADMA.ACM.MCLK_OUT0, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20, ADMA.LCDIF.WR_RWN */ +#define SC_P_UART1_TX 69 /* ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21, ADMA.LCDIF.D04 */ +#define SC_P_UART1_RX 70 /* ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22, ADMA.LCDIF.D05 */ +#define SC_P_UART1_RTS_B 71 /* ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK, ADMA.LCDIF.D06 */ +#define SC_P_UART1_CTS_B 72 /* ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24, ADMA.LCDIF.D07 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 73 /* */ +#define SC_P_SPI0_SCK 74 /* ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04, ADMA.LCDIF.D08 */ +#define SC_P_SPI0_SDI 75 /* ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05, ADMA.LCDIF.D09 */ +#define SC_P_SPI0_SDO 76 /* ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06, ADMA.LCDIF.D10 */ +#define SC_P_SPI0_CS1 77 /* ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07, ADMA.LCDIF.D11 */ +#define SC_P_SPI0_CS0 78 /* ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08, ADMA.LCDIF.D12 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 79 /* */ +#define SC_P_ADC_IN1 80 /* ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO1.IO09, ADMA.LCDIF.D13 */ +#define SC_P_ADC_IN0 81 /* ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO1.IO10, ADMA.LCDIF.D14 */ +#define SC_P_ADC_IN3 82 /* ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11, ADMA.LCDIF.D15 */ +#define SC_P_ADC_IN2 83 /* ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12, ADMA.LCDIF.D16 */ +#define SC_P_ADC_IN5 84 /* ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, ADMA.LCDIF.LCDBUSY, LSIO.GPIO1.IO13, ADMA.LCDIF.D17 */ +#define SC_P_ADC_IN4 85 /* ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, ADMA.LCDIF.LCDRESET, LSIO.GPIO1.IO14 */ +#define SC_P_FLEXCAN0_RX 86 /* ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15, LSIO.GPIO6.IO08 */ +#define SC_P_FLEXCAN0_TX 87 /* ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16, LSIO.GPIO6.IO09 */ +#define SC_P_FLEXCAN1_RX 88 /* ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17, LSIO.GPIO6.IO10 */ +#define SC_P_FLEXCAN1_TX 89 /* ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18, LSIO.GPIO6.IO11 */ +#define SC_P_FLEXCAN2_RX 90 /* ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19, LSIO.GPIO6.IO12 */ +#define SC_P_FLEXCAN2_TX 91 /* ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20, LSIO.GPIO6.IO13 */ +#define SC_P_UART0_RX 92 /* ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21, LSIO.GPIO6.IO14 */ +#define SC_P_UART0_TX 93 /* ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22, LSIO.GPIO6.IO15 */ +#define SC_P_UART2_TX 94 /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23, LSIO.GPIO6.IO16 */ +#define SC_P_UART2_RX 95 /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24, LSIO.GPIO6.IO17 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 96 /* */ +#define SC_P_JTAG_TRST_B 97 /* SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */ +#define SC_P_PMIC_I2C_SCL 98 /* SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */ +#define SC_P_PMIC_I2C_SDA 99 /* SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */ +#define SC_P_PMIC_INT_B 100 /* SCU.DSC.PMIC_INT_B */ +#define SC_P_SCU_GPIO0_00 101 /* SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */ +#define SC_P_SCU_GPIO0_01 102 /* SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */ +#define SC_P_SCU_PMIC_STANDBY 103 /* SCU.DSC.PMIC_STANDBY */ +#define SC_P_SCU_BOOT_MODE1 104 /* SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE0 105 /* SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE2 106 /* SCU.DSC.BOOT_MODE2, SCU.DSC.RTC_CLOCK_OUTPUT_32K */ +#define SC_P_SNVS_TAMPER_OUT1 107 /* , LSIO.GPIO2.IO05_IN, LSIO.GPIO6.IO19_IN */ +#define SC_P_SNVS_TAMPER_OUT2 108 /* , LSIO.GPIO2.IO06_IN, LSIO.GPIO6.IO20_IN */ +#define SC_P_SNVS_TAMPER_OUT3 109 /* , ADMA.SAI2.RXC, LSIO.GPIO2.IO07_IN, LSIO.GPIO6.IO21_IN */ +#define SC_P_SNVS_TAMPER_OUT4 110 /* , ADMA.SAI2.RXD, LSIO.GPIO2.IO08_IN, LSIO.GPIO6.IO22_IN */ +#define SC_P_SNVS_TAMPER_IN0 111 /* , ADMA.SAI2.RXFS, LSIO.GPIO2.IO09_IN, LSIO.GPIO6.IO23_IN */ +#define SC_P_SNVS_TAMPER_IN1 112 /* , ADMA.SAI3.RXC, LSIO.GPIO2.IO10_IN, LSIO.GPIO6.IO24_IN */ +#define SC_P_SNVS_TAMPER_IN2 113 /* , ADMA.SAI3.RXD, LSIO.GPIO2.IO11_IN, LSIO.GPIO6.IO25_IN */ +#define SC_P_SNVS_TAMPER_IN3 114 /* , ADMA.SAI3.RXFS, LSIO.GPIO2.IO12_IN, LSIO.GPIO6.IO26_IN */ +#define SC_P_SPI1_SCK 115 /* , ADMA.I2C2.SDA, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */ +#define SC_P_SPI1_SDO 116 /* , ADMA.I2C2.SCL, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */ +#define SC_P_SPI1_SDI 117 /* , ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */ +#define SC_P_SPI1_CS0 118 /* , ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 119 /* */ +#define SC_P_QSPI0A_DATA1 120 /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ +#define SC_P_QSPI0A_DATA0 121 /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ +#define SC_P_QSPI0A_DATA3 122 /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ +#define SC_P_QSPI0A_DATA2 123 /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ +#define SC_P_QSPI0A_SS0_B 124 /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ +#define SC_P_QSPI0A_DQS 125 /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ +#define SC_P_QSPI0A_SCLK 126 /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 127 /* */ +#define SC_P_QSPI0B_SCLK 128 /* LSIO.QSPI0B.SCLK, LSIO.GPIO3.IO17 */ +#define SC_P_QSPI0B_DQS 129 /* LSIO.QSPI0B.DQS, LSIO.GPIO3.IO22 */ +#define SC_P_QSPI0B_DATA1 130 /* LSIO.QSPI0B.DATA1, LSIO.GPIO3.IO19 */ +#define SC_P_QSPI0B_DATA0 131 /* LSIO.QSPI0B.DATA0, LSIO.GPIO3.IO18 */ +#define SC_P_QSPI0B_DATA3 132 /* LSIO.QSPI0B.DATA3, LSIO.GPIO3.IO21 */ +#define SC_P_QSPI0B_DATA2 133 /* LSIO.QSPI0B.DATA2, LSIO.GPIO3.IO20 */ +#define SC_P_QSPI0B_SS0_B 134 /* LSIO.QSPI0B.SS0_B, LSIO.GPIO3.IO23, LSIO.QSPI0A.SS1_B */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 135 /* */ +/*@}*/ + +/*! + * @name Pad Mux Definitions + * format: name padid padmux + */ +/*@{*/ +#define SC_P_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B SC_P_PCIE_CTRL0_PERST_B 0 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 SC_P_PCIE_CTRL0_PERST_B 4 +#define SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO7_IO00 SC_P_PCIE_CTRL0_PERST_B 5 +#define SC_P_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B SC_P_PCIE_CTRL0_CLKREQ_B 0 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 4 +#define SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7_IO01 SC_P_PCIE_CTRL0_CLKREQ_B 5 +#define SC_P_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B SC_P_PCIE_CTRL0_WAKE_B 0 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 SC_P_PCIE_CTRL0_WAKE_B 4 +#define SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_IO02 SC_P_PCIE_CTRL0_WAKE_B 5 +#define SC_P_USB_SS3_TC0_ADMA_I2C1_SCL SC_P_USB_SS3_TC0 0 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR SC_P_USB_SS3_TC0 1 +#define SC_P_USB_SS3_TC0_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC0 2 +#define SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 SC_P_USB_SS3_TC0 4 +#define SC_P_USB_SS3_TC0_LSIO_GPIO7_IO03 SC_P_USB_SS3_TC0 5 +#define SC_P_USB_SS3_TC1_ADMA_I2C1_SCL SC_P_USB_SS3_TC1 0 +#define SC_P_USB_SS3_TC1_CONN_USB_OTG2_PWR SC_P_USB_SS3_TC1 1 +#define SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 SC_P_USB_SS3_TC1 4 +#define SC_P_USB_SS3_TC1_LSIO_GPIO7_IO04 SC_P_USB_SS3_TC1 5 +#define SC_P_USB_SS3_TC2_ADMA_I2C1_SDA SC_P_USB_SS3_TC2 0 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC SC_P_USB_SS3_TC2 1 +#define SC_P_USB_SS3_TC2_CONN_USB_OTG2_OC SC_P_USB_SS3_TC2 2 +#define SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 SC_P_USB_SS3_TC2 4 +#define SC_P_USB_SS3_TC2_LSIO_GPIO7_IO05 SC_P_USB_SS3_TC2 5 +#define SC_P_USB_SS3_TC3_ADMA_I2C1_SDA SC_P_USB_SS3_TC3 0 +#define SC_P_USB_SS3_TC3_CONN_USB_OTG2_OC SC_P_USB_SS3_TC3 1 +#define SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 SC_P_USB_SS3_TC3 4 +#define SC_P_USB_SS3_TC3_LSIO_GPIO7_IO06 SC_P_USB_SS3_TC3 5 +#define SC_P_EMMC0_CLK_CONN_EMMC0_CLK SC_P_EMMC0_CLK 0 +#define SC_P_EMMC0_CLK_CONN_NAND_READY_B SC_P_EMMC0_CLK 1 +#define SC_P_EMMC0_CLK_LSIO_GPIO4_IO07 SC_P_EMMC0_CLK 4 +#define SC_P_EMMC0_CMD_CONN_EMMC0_CMD SC_P_EMMC0_CMD 0 +#define SC_P_EMMC0_CMD_CONN_NAND_DQS SC_P_EMMC0_CMD 1 +#define SC_P_EMMC0_CMD_LSIO_GPIO4_IO08 SC_P_EMMC0_CMD 4 +#define SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 SC_P_EMMC0_DATA0 0 +#define SC_P_EMMC0_DATA0_CONN_NAND_DATA00 SC_P_EMMC0_DATA0 1 +#define SC_P_EMMC0_DATA0_LSIO_GPIO4_IO09 SC_P_EMMC0_DATA0 4 +#define SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 SC_P_EMMC0_DATA1 0 +#define SC_P_EMMC0_DATA1_CONN_NAND_DATA01 SC_P_EMMC0_DATA1 1 +#define SC_P_EMMC0_DATA1_LSIO_GPIO4_IO10 SC_P_EMMC0_DATA1 4 +#define SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 SC_P_EMMC0_DATA2 0 +#define SC_P_EMMC0_DATA2_CONN_NAND_DATA02 SC_P_EMMC0_DATA2 1 +#define SC_P_EMMC0_DATA2_LSIO_GPIO4_IO11 SC_P_EMMC0_DATA2 4 +#define SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 SC_P_EMMC0_DATA3 0 +#define SC_P_EMMC0_DATA3_CONN_NAND_DATA03 SC_P_EMMC0_DATA3 1 +#define SC_P_EMMC0_DATA3_LSIO_GPIO4_IO12 SC_P_EMMC0_DATA3 4 +#define SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 SC_P_EMMC0_DATA4 0 +#define SC_P_EMMC0_DATA4_CONN_NAND_DATA04 SC_P_EMMC0_DATA4 1 +#define SC_P_EMMC0_DATA4_LSIO_GPIO4_IO13 SC_P_EMMC0_DATA4 4 +#define SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 SC_P_EMMC0_DATA5 0 +#define SC_P_EMMC0_DATA5_CONN_NAND_DATA05 SC_P_EMMC0_DATA5 1 +#define SC_P_EMMC0_DATA5_LSIO_GPIO4_IO14 SC_P_EMMC0_DATA5 4 +#define SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 SC_P_EMMC0_DATA6 0 +#define SC_P_EMMC0_DATA6_CONN_NAND_DATA06 SC_P_EMMC0_DATA6 1 +#define SC_P_EMMC0_DATA6_LSIO_GPIO4_IO15 SC_P_EMMC0_DATA6 4 +#define SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 SC_P_EMMC0_DATA7 0 +#define SC_P_EMMC0_DATA7_CONN_NAND_DATA07 SC_P_EMMC0_DATA7 1 +#define SC_P_EMMC0_DATA7_LSIO_GPIO4_IO16 SC_P_EMMC0_DATA7 4 +#define SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE SC_P_EMMC0_STROBE 0 +#define SC_P_EMMC0_STROBE_CONN_NAND_CLE SC_P_EMMC0_STROBE 1 +#define SC_P_EMMC0_STROBE_LSIO_GPIO4_IO17 SC_P_EMMC0_STROBE 4 +#define SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B SC_P_EMMC0_RESET_B 0 +#define SC_P_EMMC0_RESET_B_CONN_NAND_WP_B SC_P_EMMC0_RESET_B 1 +#define SC_P_EMMC0_RESET_B_LSIO_GPIO4_IO18 SC_P_EMMC0_RESET_B 4 +#define SC_P_USDHC1_RESET_B_CONN_USDHC1_RESET_B SC_P_USDHC1_RESET_B 0 +#define SC_P_USDHC1_RESET_B_CONN_NAND_RE_N SC_P_USDHC1_RESET_B 1 +#define SC_P_USDHC1_RESET_B_ADMA_SPI2_SCK SC_P_USDHC1_RESET_B 2 +#define SC_P_USDHC1_RESET_B_CONN_NAND_WE_B SC_P_USDHC1_RESET_B 3 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 SC_P_USDHC1_RESET_B 4 +#define SC_P_USDHC1_RESET_B_LSIO_GPIO7_IO08 SC_P_USDHC1_RESET_B 5 +#define SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT SC_P_USDHC1_VSELECT 0 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_P SC_P_USDHC1_VSELECT 1 +#define SC_P_USDHC1_VSELECT_ADMA_SPI2_SDO SC_P_USDHC1_VSELECT 2 +#define SC_P_USDHC1_VSELECT_CONN_NAND_RE_B SC_P_USDHC1_VSELECT 3 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO4_IO20 SC_P_USDHC1_VSELECT 4 +#define SC_P_USDHC1_VSELECT_LSIO_GPIO7_IO09 SC_P_USDHC1_VSELECT 5 +#define SC_P_USDHC1_WP_CONN_USDHC1_WP SC_P_USDHC1_WP 0 +#define SC_P_USDHC1_WP_CONN_NAND_DQS_N SC_P_USDHC1_WP 1 +#define SC_P_USDHC1_WP_ADMA_SPI2_SDI SC_P_USDHC1_WP 2 +#define SC_P_USDHC1_WP_CONN_NAND_ALE SC_P_USDHC1_WP 3 +#define SC_P_USDHC1_WP_LSIO_GPIO4_IO21 SC_P_USDHC1_WP 4 +#define SC_P_USDHC1_WP_LSIO_GPIO7_IO10 SC_P_USDHC1_WP 5 +#define SC_P_USDHC1_CD_B_CONN_USDHC1_CD_B SC_P_USDHC1_CD_B 0 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS_P SC_P_USDHC1_CD_B 1 +#define SC_P_USDHC1_CD_B_ADMA_SPI2_CS0 SC_P_USDHC1_CD_B 2 +#define SC_P_USDHC1_CD_B_CONN_NAND_DQS SC_P_USDHC1_CD_B 3 +#define SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 SC_P_USDHC1_CD_B 4 +#define SC_P_USDHC1_CD_B_LSIO_GPIO7_IO11 SC_P_USDHC1_CD_B 5 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC SC_P_ENET0_RGMII_TXC 0 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT SC_P_ENET0_RGMII_TXC 1 +#define SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN SC_P_ENET0_RGMII_TXC 2 +#define SC_P_ENET0_RGMII_TXC_CONN_NAND_CE1_B SC_P_ENET0_RGMII_TXC 3 +#define SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 SC_P_ENET0_RGMII_TXC 4 +#define SC_P_ENET0_RGMII_TXC_CONN_USDHC2_CLK SC_P_ENET0_RGMII_TXC 5 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL SC_P_ENET0_RGMII_TX_CTL 0 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B SC_P_ENET0_RGMII_TX_CTL 3 +#define SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 SC_P_ENET0_RGMII_TX_CTL 4 +#define SC_P_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD SC_P_ENET0_RGMII_TX_CTL 5 +#define SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 SC_P_ENET0_RGMII_TXD0 0 +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT SC_P_ENET0_RGMII_TXD0 3 +#define SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 SC_P_ENET0_RGMII_TXD0 4 +#define SC_P_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 SC_P_ENET0_RGMII_TXD0 5 +#define SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 SC_P_ENET0_RGMII_TXD1 0 +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC1_WP SC_P_ENET0_RGMII_TXD1 3 +#define SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 SC_P_ENET0_RGMII_TXD1 4 +#define SC_P_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 SC_P_ENET0_RGMII_TXD1 5 +#define SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 SC_P_ENET0_RGMII_TXD2 0 +#define SC_P_ENET0_RGMII_TXD2_CONN_NAND_CE0_B SC_P_ENET0_RGMII_TXD2 2 +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B SC_P_ENET0_RGMII_TXD2 3 +#define SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 SC_P_ENET0_RGMII_TXD2 4 +#define SC_P_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 SC_P_ENET0_RGMII_TXD2 5 +#define SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 SC_P_ENET0_RGMII_TXD3 0 +#define SC_P_ENET0_RGMII_TXD3_CONN_NAND_RE_B SC_P_ENET0_RGMII_TXD3 2 +#define SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 SC_P_ENET0_RGMII_TXD3 4 +#define SC_P_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 SC_P_ENET0_RGMII_TXD3 5 +#define SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC SC_P_ENET0_RGMII_RXC 0 +#define SC_P_ENET0_RGMII_RXC_CONN_NAND_WE_B SC_P_ENET0_RGMII_RXC 2 +#define SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK SC_P_ENET0_RGMII_RXC 3 +#define SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 SC_P_ENET0_RGMII_RXC 4 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL SC_P_ENET0_RGMII_RX_CTL 0 +#define SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD SC_P_ENET0_RGMII_RX_CTL 3 +#define SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 SC_P_ENET0_RGMII_RX_CTL 4 +#define SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 SC_P_ENET0_RGMII_RXD0 0 +#define SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 SC_P_ENET0_RGMII_RXD0 3 +#define SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 SC_P_ENET0_RGMII_RXD0 4 +#define SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 SC_P_ENET0_RGMII_RXD1 0 +#define SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 SC_P_ENET0_RGMII_RXD1 3 +#define SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 SC_P_ENET0_RGMII_RXD1 4 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 SC_P_ENET0_RGMII_RXD2 0 +#define SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER SC_P_ENET0_RGMII_RXD2 1 +#define SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 SC_P_ENET0_RGMII_RXD2 3 +#define SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 SC_P_ENET0_RGMII_RXD2 4 +#define SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 SC_P_ENET0_RGMII_RXD3 0 +#define SC_P_ENET0_RGMII_RXD3_CONN_NAND_ALE SC_P_ENET0_RGMII_RXD3 2 +#define SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 SC_P_ENET0_RGMII_RXD3 3 +#define SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 SC_P_ENET0_RGMII_RXD3 4 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M SC_P_ENET0_REFCLK_125M_25M 0 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS SC_P_ENET0_REFCLK_125M_25M 1 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_IN SC_P_ENET0_REFCLK_125M_25M 2 +#define SC_P_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_OUT SC_P_ENET0_REFCLK_125M_25M 3 +#define SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 SC_P_ENET0_REFCLK_125M_25M 4 +#define SC_P_ENET0_MDIO_CONN_ENET0_MDIO SC_P_ENET0_MDIO 0 +#define SC_P_ENET0_MDIO_ADMA_I2C3_SDA SC_P_ENET0_MDIO 1 +#define SC_P_ENET0_MDIO_CONN_EQOS_MDIO SC_P_ENET0_MDIO 2 +#define SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 SC_P_ENET0_MDIO 4 +#define SC_P_ENET0_MDIO_LSIO_GPIO7_IO16 SC_P_ENET0_MDIO 5 +#define SC_P_ENET0_MDC_CONN_ENET0_MDC SC_P_ENET0_MDC 0 +#define SC_P_ENET0_MDC_ADMA_I2C3_SCL SC_P_ENET0_MDC 1 +#define SC_P_ENET0_MDC_CONN_EQOS_MDC SC_P_ENET0_MDC 2 +#define SC_P_ENET0_MDC_LSIO_GPIO5_IO11 SC_P_ENET0_MDC 4 +#define SC_P_ENET0_MDC_LSIO_GPIO7_IO17 SC_P_ENET0_MDC 5 +#define SC_P_ENET1_RGMII_TXC_LSIO_GPIO0_IO00 SC_P_ENET1_RGMII_TXC 0 +#define SC_P_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_OUT SC_P_ENET1_RGMII_TXC 1 +#define SC_P_ENET1_RGMII_TXC_ADMA_LCDIF_D00 SC_P_ENET1_RGMII_TXC 2 +#define SC_P_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC SC_P_ENET1_RGMII_TXC 3 +#define SC_P_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_IN SC_P_ENET1_RGMII_TXC 4 +#define SC_P_ENET1_RGMII_TXD2_ADMA_LCDIF_D01 SC_P_ENET1_RGMII_TXD2 2 +#define SC_P_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 SC_P_ENET1_RGMII_TXD2 3 +#define SC_P_ENET1_RGMII_TXD2_LSIO_GPIO0_IO01 SC_P_ENET1_RGMII_TXD2 4 +#define SC_P_ENET1_RGMII_TX_CTL_ADMA_LCDIF_D02 SC_P_ENET1_RGMII_TX_CTL 2 +#define SC_P_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL SC_P_ENET1_RGMII_TX_CTL 3 +#define SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO0_IO02 SC_P_ENET1_RGMII_TX_CTL 4 +#define SC_P_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 SC_P_ENET1_RGMII_TXD3 2 +#define SC_P_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 SC_P_ENET1_RGMII_TXD3 3 +#define SC_P_ENET1_RGMII_TXD3_LSIO_GPIO0_IO03 SC_P_ENET1_RGMII_TXD3 4 +#define SC_P_ENET1_RGMII_RXC_ADMA_LCDIF_D04 SC_P_ENET1_RGMII_RXC 2 +#define SC_P_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC SC_P_ENET1_RGMII_RXC 3 +#define SC_P_ENET1_RGMII_RXC_LSIO_GPIO0_IO04 SC_P_ENET1_RGMII_RXC 4 +#define SC_P_ENET1_RGMII_RXD3_ADMA_LCDIF_D05 SC_P_ENET1_RGMII_RXD3 2 +#define SC_P_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 SC_P_ENET1_RGMII_RXD3 3 +#define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO0_IO05 SC_P_ENET1_RGMII_RXD3 4 +#define SC_P_ENET1_RGMII_RXD2_ADMA_LCDIF_D06 SC_P_ENET1_RGMII_RXD2 2 +#define SC_P_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 SC_P_ENET1_RGMII_RXD2 3 +#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO0_IO06 SC_P_ENET1_RGMII_RXD2 4 +#define SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO00 SC_P_ENET1_RGMII_RXD2 5 +#define SC_P_ENET1_RGMII_RXD1_ADMA_LCDIF_D07 SC_P_ENET1_RGMII_RXD1 2 +#define SC_P_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 SC_P_ENET1_RGMII_RXD1 3 +#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO0_IO07 SC_P_ENET1_RGMII_RXD1 4 +#define SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO01 SC_P_ENET1_RGMII_RXD1 5 +#define SC_P_ENET1_RGMII_TXD0_ADMA_LCDIF_D08 SC_P_ENET1_RGMII_TXD0 2 +#define SC_P_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 SC_P_ENET1_RGMII_TXD0 3 +#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO0_IO08 SC_P_ENET1_RGMII_TXD0 4 +#define SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO02 SC_P_ENET1_RGMII_TXD0 5 +#define SC_P_ENET1_RGMII_TXD1_ADMA_LCDIF_D09 SC_P_ENET1_RGMII_TXD1 2 +#define SC_P_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 SC_P_ENET1_RGMII_TXD1 3 +#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO0_IO09 SC_P_ENET1_RGMII_TXD1 4 +#define SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO03 SC_P_ENET1_RGMII_TXD1 5 +#define SC_P_ENET1_RGMII_RXD0_ADMA_SPDIF0_RX SC_P_ENET1_RGMII_RXD0 0 +#define SC_P_ENET1_RGMII_RXD0_ADMA_MQS_R SC_P_ENET1_RGMII_RXD0 1 +#define SC_P_ENET1_RGMII_RXD0_ADMA_LCDIF_D10 SC_P_ENET1_RGMII_RXD0 2 +#define SC_P_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 SC_P_ENET1_RGMII_RXD0 3 +#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO0_IO10 SC_P_ENET1_RGMII_RXD0 4 +#define SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO04 SC_P_ENET1_RGMII_RXD0 5 +#define SC_P_ENET1_RGMII_RX_CTL_ADMA_SPDIF0_TX SC_P_ENET1_RGMII_RX_CTL 0 +#define SC_P_ENET1_RGMII_RX_CTL_ADMA_MQS_L SC_P_ENET1_RGMII_RX_CTL 1 +#define SC_P_ENET1_RGMII_RX_CTL_ADMA_LCDIF_D11 SC_P_ENET1_RGMII_RX_CTL 2 +#define SC_P_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL SC_P_ENET1_RGMII_RX_CTL 3 +#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO0_IO11 SC_P_ENET1_RGMII_RX_CTL 4 +#define SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO05 SC_P_ENET1_RGMII_RX_CTL 5 +#define SC_P_ENET1_REFCLK_125M_25M_ADMA_SPDIF0_EXT_CLK SC_P_ENET1_REFCLK_125M_25M 0 +#define SC_P_ENET1_REFCLK_125M_25M_ADMA_LCDIF_D12 SC_P_ENET1_REFCLK_125M_25M 2 +#define SC_P_ENET1_REFCLK_125M_25M_CONN_EQOS_REFCLK_125M_25M SC_P_ENET1_REFCLK_125M_25M 3 +#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO0_IO12 SC_P_ENET1_REFCLK_125M_25M 4 +#define SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO6_IO06 SC_P_ENET1_REFCLK_125M_25M 5 +#define SC_P_SPI3_SCK_ADMA_SPI3_SCK SC_P_SPI3_SCK 0 +#define SC_P_SPI3_SCK_ADMA_LCDIF_D13 SC_P_SPI3_SCK 2 +#define SC_P_SPI3_SCK_LSIO_GPIO0_IO13 SC_P_SPI3_SCK 4 +#define SC_P_SPI3_SCK_ADMA_LCDIF_D00 SC_P_SPI3_SCK 5 +#define SC_P_SPI3_SDO_ADMA_SPI3_SDO SC_P_SPI3_SDO 0 +#define SC_P_SPI3_SDO_ADMA_LCDIF_D14 SC_P_SPI3_SDO 2 +#define SC_P_SPI3_SDO_LSIO_GPIO0_IO14 SC_P_SPI3_SDO 4 +#define SC_P_SPI3_SDO_ADMA_LCDIF_D01 SC_P_SPI3_SDO 5 +#define SC_P_SPI3_SDI_ADMA_SPI3_SDI SC_P_SPI3_SDI 0 +#define SC_P_SPI3_SDI_ADMA_LCDIF_D15 SC_P_SPI3_SDI 2 +#define SC_P_SPI3_SDI_LSIO_GPIO0_IO15 SC_P_SPI3_SDI 4 +#define SC_P_SPI3_SDI_ADMA_LCDIF_D02 SC_P_SPI3_SDI 5 +#define SC_P_SPI3_CS0_ADMA_SPI3_CS0 SC_P_SPI3_CS0 0 +#define SC_P_SPI3_CS0_ADMA_ACM_MCLK_OUT1 SC_P_SPI3_CS0 1 +#define SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC SC_P_SPI3_CS0 2 +#define SC_P_SPI3_CS0_LSIO_GPIO0_IO16 SC_P_SPI3_CS0 4 +#define SC_P_SPI3_CS0_ADMA_LCDIF_CS SC_P_SPI3_CS0 5 +#define SC_P_SPI3_CS1_ADMA_SPI3_CS1 SC_P_SPI3_CS1 0 +#define SC_P_SPI3_CS1_ADMA_I2C3_SCL SC_P_SPI3_CS1 1 +#define SC_P_SPI3_CS1_ADMA_LCDIF_RESET SC_P_SPI3_CS1 2 +#define SC_P_SPI3_CS1_ADMA_SPI2_CS0 SC_P_SPI3_CS1 3 +#define SC_P_SPI3_CS1_ADMA_LCDIF_D16 SC_P_SPI3_CS1 4 +#define SC_P_SPI3_CS1_ADMA_LCDIF_RD_E SC_P_SPI3_CS1 5 +#define SC_P_MCLK_IN1_ADMA_ACM_MCLK_IN1 SC_P_MCLK_IN1 0 +#define SC_P_MCLK_IN1_ADMA_I2C3_SDA SC_P_MCLK_IN1 1 +#define SC_P_MCLK_IN1_ADMA_LCDIF_EN SC_P_MCLK_IN1 2 +#define SC_P_MCLK_IN1_ADMA_SPI2_SCK SC_P_MCLK_IN1 3 +#define SC_P_MCLK_IN1_ADMA_LCDIF_D17 SC_P_MCLK_IN1 4 +#define SC_P_MCLK_IN1_ADMA_LCDIF_D03 SC_P_MCLK_IN1 5 +#define SC_P_MCLK_IN0_ADMA_ACM_MCLK_IN0 SC_P_MCLK_IN0 0 +#define SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC SC_P_MCLK_IN0 2 +#define SC_P_MCLK_IN0_ADMA_SPI2_SDI SC_P_MCLK_IN0 3 +#define SC_P_MCLK_IN0_LSIO_GPIO0_IO19 SC_P_MCLK_IN0 4 +#define SC_P_MCLK_IN0_ADMA_LCDIF_RS SC_P_MCLK_IN0 5 +#define SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 SC_P_MCLK_OUT0 0 +#define SC_P_MCLK_OUT0_ADMA_LCDIF_CLK SC_P_MCLK_OUT0 2 +#define SC_P_MCLK_OUT0_ADMA_SPI2_SDO SC_P_MCLK_OUT0 3 +#define SC_P_MCLK_OUT0_LSIO_GPIO0_IO20 SC_P_MCLK_OUT0 4 +#define SC_P_MCLK_OUT0_ADMA_LCDIF_WR_RWN SC_P_MCLK_OUT0 5 +#define SC_P_UART1_TX_ADMA_UART1_TX SC_P_UART1_TX 0 +#define SC_P_UART1_TX_LSIO_PWM0_OUT SC_P_UART1_TX 1 +#define SC_P_UART1_TX_LSIO_GPT0_CAPTURE SC_P_UART1_TX 2 +#define SC_P_UART1_TX_LSIO_GPIO0_IO21 SC_P_UART1_TX 4 +#define SC_P_UART1_TX_ADMA_LCDIF_D04 SC_P_UART1_TX 5 +#define SC_P_UART1_RX_ADMA_UART1_RX SC_P_UART1_RX 0 +#define SC_P_UART1_RX_LSIO_PWM1_OUT SC_P_UART1_RX 1 +#define SC_P_UART1_RX_LSIO_GPT0_COMPARE SC_P_UART1_RX 2 +#define SC_P_UART1_RX_LSIO_GPT1_CLK SC_P_UART1_RX 3 +#define SC_P_UART1_RX_LSIO_GPIO0_IO22 SC_P_UART1_RX 4 +#define SC_P_UART1_RX_ADMA_LCDIF_D05 SC_P_UART1_RX 5 +#define SC_P_UART1_RTS_B_ADMA_UART1_RTS_B SC_P_UART1_RTS_B 0 +#define SC_P_UART1_RTS_B_LSIO_PWM2_OUT SC_P_UART1_RTS_B 1 +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D16 SC_P_UART1_RTS_B 2 +#define SC_P_UART1_RTS_B_LSIO_GPT1_CAPTURE SC_P_UART1_RTS_B 3 +#define SC_P_UART1_RTS_B_LSIO_GPT0_CLK SC_P_UART1_RTS_B 4 +#define SC_P_UART1_RTS_B_ADMA_LCDIF_D06 SC_P_UART1_RTS_B 5 +#define SC_P_UART1_CTS_B_ADMA_UART1_CTS_B SC_P_UART1_CTS_B 0 +#define SC_P_UART1_CTS_B_LSIO_PWM3_OUT SC_P_UART1_CTS_B 1 +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D17 SC_P_UART1_CTS_B 2 +#define SC_P_UART1_CTS_B_LSIO_GPT1_COMPARE SC_P_UART1_CTS_B 3 +#define SC_P_UART1_CTS_B_LSIO_GPIO0_IO24 SC_P_UART1_CTS_B 4 +#define SC_P_UART1_CTS_B_ADMA_LCDIF_D07 SC_P_UART1_CTS_B 5 +#define SC_P_SPI0_SCK_ADMA_SPI0_SCK SC_P_SPI0_SCK 0 +#define SC_P_SPI0_SCK_ADMA_SAI0_TXC SC_P_SPI0_SCK 1 +#define SC_P_SPI0_SCK_M40_I2C0_SCL SC_P_SPI0_SCK 2 +#define SC_P_SPI0_SCK_M40_GPIO0_IO00 SC_P_SPI0_SCK 3 +#define SC_P_SPI0_SCK_LSIO_GPIO1_IO04 SC_P_SPI0_SCK 4 +#define SC_P_SPI0_SCK_ADMA_LCDIF_D08 SC_P_SPI0_SCK 5 +#define SC_P_SPI0_SDI_ADMA_SPI0_SDI SC_P_SPI0_SDI 0 +#define SC_P_SPI0_SDI_ADMA_SAI0_TXD SC_P_SPI0_SDI 1 +#define SC_P_SPI0_SDI_M40_TPM0_CH0 SC_P_SPI0_SDI 2 +#define SC_P_SPI0_SDI_M40_GPIO0_IO02 SC_P_SPI0_SDI 3 +#define SC_P_SPI0_SDI_LSIO_GPIO1_IO05 SC_P_SPI0_SDI 4 +#define SC_P_SPI0_SDI_ADMA_LCDIF_D09 SC_P_SPI0_SDI 5 +#define SC_P_SPI0_SDO_ADMA_SPI0_SDO SC_P_SPI0_SDO 0 +#define SC_P_SPI0_SDO_ADMA_SAI0_TXFS SC_P_SPI0_SDO 1 +#define SC_P_SPI0_SDO_M40_I2C0_SDA SC_P_SPI0_SDO 2 +#define SC_P_SPI0_SDO_M40_GPIO0_IO01 SC_P_SPI0_SDO 3 +#define SC_P_SPI0_SDO_LSIO_GPIO1_IO06 SC_P_SPI0_SDO 4 +#define SC_P_SPI0_SDO_ADMA_LCDIF_D10 SC_P_SPI0_SDO 5 +#define SC_P_SPI0_CS1_ADMA_SPI0_CS1 SC_P_SPI0_CS1 0 +#define SC_P_SPI0_CS1_ADMA_SAI0_RXC SC_P_SPI0_CS1 1 +#define SC_P_SPI0_CS1_ADMA_SAI1_TXD SC_P_SPI0_CS1 2 +#define SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT SC_P_SPI0_CS1 3 +#define SC_P_SPI0_CS1_LSIO_GPIO1_IO07 SC_P_SPI0_CS1 4 +#define SC_P_SPI0_CS1_ADMA_LCDIF_D11 SC_P_SPI0_CS1 5 +#define SC_P_SPI0_CS0_ADMA_SPI0_CS0 SC_P_SPI0_CS0 0 +#define SC_P_SPI0_CS0_ADMA_SAI0_RXD SC_P_SPI0_CS0 1 +#define SC_P_SPI0_CS0_M40_TPM0_CH1 SC_P_SPI0_CS0 2 +#define SC_P_SPI0_CS0_M40_GPIO0_IO03 SC_P_SPI0_CS0 3 +#define SC_P_SPI0_CS0_LSIO_GPIO1_IO08 SC_P_SPI0_CS0 4 +#define SC_P_SPI0_CS0_ADMA_LCDIF_D12 SC_P_SPI0_CS0 5 +#define SC_P_ADC_IN1_ADMA_ADC_IN1 SC_P_ADC_IN1 0 +#define SC_P_ADC_IN1_M40_I2C0_SDA SC_P_ADC_IN1 1 +#define SC_P_ADC_IN1_M40_GPIO0_IO01 SC_P_ADC_IN1 2 +#define SC_P_ADC_IN1_ADMA_I2C0_SDA SC_P_ADC_IN1 3 +#define SC_P_ADC_IN1_LSIO_GPIO1_IO09 SC_P_ADC_IN1 4 +#define SC_P_ADC_IN1_ADMA_LCDIF_D13 SC_P_ADC_IN1 5 +#define SC_P_ADC_IN0_ADMA_ADC_IN0 SC_P_ADC_IN0 0 +#define SC_P_ADC_IN0_M40_I2C0_SCL SC_P_ADC_IN0 1 +#define SC_P_ADC_IN0_M40_GPIO0_IO00 SC_P_ADC_IN0 2 +#define SC_P_ADC_IN0_ADMA_I2C0_SCL SC_P_ADC_IN0 3 +#define SC_P_ADC_IN0_LSIO_GPIO1_IO10 SC_P_ADC_IN0 4 +#define SC_P_ADC_IN0_ADMA_LCDIF_D14 SC_P_ADC_IN0 5 +#define SC_P_ADC_IN3_ADMA_ADC_IN3 SC_P_ADC_IN3 0 +#define SC_P_ADC_IN3_M40_UART0_TX SC_P_ADC_IN3 1 +#define SC_P_ADC_IN3_M40_GPIO0_IO03 SC_P_ADC_IN3 2 +#define SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 SC_P_ADC_IN3 3 +#define SC_P_ADC_IN3_LSIO_GPIO1_IO11 SC_P_ADC_IN3 4 +#define SC_P_ADC_IN3_ADMA_LCDIF_D15 SC_P_ADC_IN3 5 +#define SC_P_ADC_IN2_ADMA_ADC_IN2 SC_P_ADC_IN2 0 +#define SC_P_ADC_IN2_M40_UART0_RX SC_P_ADC_IN2 1 +#define SC_P_ADC_IN2_M40_GPIO0_IO02 SC_P_ADC_IN2 2 +#define SC_P_ADC_IN2_ADMA_ACM_MCLK_IN0 SC_P_ADC_IN2 3 +#define SC_P_ADC_IN2_LSIO_GPIO1_IO12 SC_P_ADC_IN2 4 +#define SC_P_ADC_IN2_ADMA_LCDIF_D16 SC_P_ADC_IN2 5 +#define SC_P_ADC_IN5_ADMA_ADC_IN5 SC_P_ADC_IN5 0 +#define SC_P_ADC_IN5_M40_TPM0_CH1 SC_P_ADC_IN5 1 +#define SC_P_ADC_IN5_M40_GPIO0_IO05 SC_P_ADC_IN5 2 +#define SC_P_ADC_IN5_ADMA_LCDIF_LCDBUSY SC_P_ADC_IN5 3 +#define SC_P_ADC_IN5_LSIO_GPIO1_IO13 SC_P_ADC_IN5 4 +#define SC_P_ADC_IN5_ADMA_LCDIF_D17 SC_P_ADC_IN5 5 +#define SC_P_ADC_IN4_ADMA_ADC_IN4 SC_P_ADC_IN4 0 +#define SC_P_ADC_IN4_M40_TPM0_CH0 SC_P_ADC_IN4 1 +#define SC_P_ADC_IN4_M40_GPIO0_IO04 SC_P_ADC_IN4 2 +#define SC_P_ADC_IN4_ADMA_LCDIF_LCDRESET SC_P_ADC_IN4 3 +#define SC_P_ADC_IN4_LSIO_GPIO1_IO14 SC_P_ADC_IN4 4 +#define SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX SC_P_FLEXCAN0_RX 0 +#define SC_P_FLEXCAN0_RX_ADMA_SAI2_RXC SC_P_FLEXCAN0_RX 1 +#define SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B SC_P_FLEXCAN0_RX 2 +#define SC_P_FLEXCAN0_RX_ADMA_SAI1_TXC SC_P_FLEXCAN0_RX 3 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO1_IO15 SC_P_FLEXCAN0_RX 4 +#define SC_P_FLEXCAN0_RX_LSIO_GPIO6_IO08 SC_P_FLEXCAN0_RX 5 +#define SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX SC_P_FLEXCAN0_TX 0 +#define SC_P_FLEXCAN0_TX_ADMA_SAI2_RXD SC_P_FLEXCAN0_TX 1 +#define SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B SC_P_FLEXCAN0_TX 2 +#define SC_P_FLEXCAN0_TX_ADMA_SAI1_TXFS SC_P_FLEXCAN0_TX 3 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO1_IO16 SC_P_FLEXCAN0_TX 4 +#define SC_P_FLEXCAN0_TX_LSIO_GPIO6_IO09 SC_P_FLEXCAN0_TX 5 +#define SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX SC_P_FLEXCAN1_RX 0 +#define SC_P_FLEXCAN1_RX_ADMA_SAI2_RXFS SC_P_FLEXCAN1_RX 1 +#define SC_P_FLEXCAN1_RX_ADMA_FTM_CH2 SC_P_FLEXCAN1_RX 2 +#define SC_P_FLEXCAN1_RX_ADMA_SAI1_TXD SC_P_FLEXCAN1_RX 3 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 SC_P_FLEXCAN1_RX 4 +#define SC_P_FLEXCAN1_RX_LSIO_GPIO6_IO10 SC_P_FLEXCAN1_RX 5 +#define SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX SC_P_FLEXCAN1_TX 0 +#define SC_P_FLEXCAN1_TX_ADMA_SAI3_RXC SC_P_FLEXCAN1_TX 1 +#define SC_P_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 SC_P_FLEXCAN1_TX 2 +#define SC_P_FLEXCAN1_TX_ADMA_SAI1_RXD SC_P_FLEXCAN1_TX 3 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 SC_P_FLEXCAN1_TX 4 +#define SC_P_FLEXCAN1_TX_LSIO_GPIO6_IO11 SC_P_FLEXCAN1_TX 5 +#define SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX SC_P_FLEXCAN2_RX 0 +#define SC_P_FLEXCAN2_RX_ADMA_SAI3_RXD SC_P_FLEXCAN2_RX 1 +#define SC_P_FLEXCAN2_RX_ADMA_UART3_RX SC_P_FLEXCAN2_RX 2 +#define SC_P_FLEXCAN2_RX_ADMA_SAI1_RXFS SC_P_FLEXCAN2_RX 3 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO1_IO19 SC_P_FLEXCAN2_RX 4 +#define SC_P_FLEXCAN2_RX_LSIO_GPIO6_IO12 SC_P_FLEXCAN2_RX 5 +#define SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX SC_P_FLEXCAN2_TX 0 +#define SC_P_FLEXCAN2_TX_ADMA_SAI3_RXFS SC_P_FLEXCAN2_TX 1 +#define SC_P_FLEXCAN2_TX_ADMA_UART3_TX SC_P_FLEXCAN2_TX 2 +#define SC_P_FLEXCAN2_TX_ADMA_SAI1_RXC SC_P_FLEXCAN2_TX 3 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO1_IO20 SC_P_FLEXCAN2_TX 4 +#define SC_P_FLEXCAN2_TX_LSIO_GPIO6_IO13 SC_P_FLEXCAN2_TX 5 +#define SC_P_UART0_RX_ADMA_UART0_RX SC_P_UART0_RX 0 +#define SC_P_UART0_RX_ADMA_MQS_R SC_P_UART0_RX 1 +#define SC_P_UART0_RX_ADMA_FLEXCAN0_RX SC_P_UART0_RX 2 +#define SC_P_UART0_RX_SCU_UART0_RX SC_P_UART0_RX 3 +#define SC_P_UART0_RX_LSIO_GPIO1_IO21 SC_P_UART0_RX 4 +#define SC_P_UART0_RX_LSIO_GPIO6_IO14 SC_P_UART0_RX 5 +#define SC_P_UART0_TX_ADMA_UART0_TX SC_P_UART0_TX 0 +#define SC_P_UART0_TX_ADMA_MQS_L SC_P_UART0_TX 1 +#define SC_P_UART0_TX_ADMA_FLEXCAN0_TX SC_P_UART0_TX 2 +#define SC_P_UART0_TX_SCU_UART0_TX SC_P_UART0_TX 3 +#define SC_P_UART0_TX_LSIO_GPIO1_IO22 SC_P_UART0_TX 4 +#define SC_P_UART0_TX_LSIO_GPIO6_IO15 SC_P_UART0_TX 5 +#define SC_P_UART2_TX_ADMA_UART2_TX SC_P_UART2_TX 0 +#define SC_P_UART2_TX_ADMA_FTM_CH1 SC_P_UART2_TX 1 +#define SC_P_UART2_TX_ADMA_FLEXCAN1_TX SC_P_UART2_TX 2 +#define SC_P_UART2_TX_LSIO_GPIO1_IO23 SC_P_UART2_TX 4 +#define SC_P_UART2_TX_LSIO_GPIO6_IO16 SC_P_UART2_TX 5 +#define SC_P_UART2_RX_ADMA_UART2_RX SC_P_UART2_RX 0 +#define SC_P_UART2_RX_ADMA_FTM_CH0 SC_P_UART2_RX 1 +#define SC_P_UART2_RX_ADMA_FLEXCAN1_RX SC_P_UART2_RX 2 +#define SC_P_UART2_RX_LSIO_GPIO1_IO24 SC_P_UART2_RX 4 +#define SC_P_UART2_RX_LSIO_GPIO6_IO17 SC_P_UART2_RX 5 +#define SC_P_JTAG_TRST_B_SCU_JTAG_TRST_B SC_P_JTAG_TRST_B 0 +#define SC_P_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT SC_P_JTAG_TRST_B 1 +#define SC_P_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL SC_P_PMIC_I2C_SCL 0 +#define SC_P_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON SC_P_PMIC_I2C_SCL 1 +#define SC_P_PMIC_I2C_SCL_LSIO_GPIO2_IO01 SC_P_PMIC_I2C_SCL 4 +#define SC_P_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA SC_P_PMIC_I2C_SDA 0 +#define SC_P_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON SC_P_PMIC_I2C_SDA 1 +#define SC_P_PMIC_I2C_SDA_LSIO_GPIO2_IO02 SC_P_PMIC_I2C_SDA 4 +#define SC_P_PMIC_INT_B_SCU_DSC_PMIC_INT_B SC_P_PMIC_INT_B 0 +#define SC_P_SCU_GPIO0_00_SCU_GPIO0_IO00 SC_P_SCU_GPIO0_00 0 +#define SC_P_SCU_GPIO0_00_SCU_UART0_RX SC_P_SCU_GPIO0_00 1 +#define SC_P_SCU_GPIO0_00_M40_UART0_RX SC_P_SCU_GPIO0_00 2 +#define SC_P_SCU_GPIO0_00_ADMA_UART3_RX SC_P_SCU_GPIO0_00 3 +#define SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 SC_P_SCU_GPIO0_00 4 +#define SC_P_SCU_GPIO0_01_SCU_GPIO0_IO01 SC_P_SCU_GPIO0_01 0 +#define SC_P_SCU_GPIO0_01_SCU_UART0_TX SC_P_SCU_GPIO0_01 1 +#define SC_P_SCU_GPIO0_01_M40_UART0_TX SC_P_SCU_GPIO0_01 2 +#define SC_P_SCU_GPIO0_01_ADMA_UART3_TX SC_P_SCU_GPIO0_01 3 +#define SC_P_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT SC_P_SCU_GPIO0_01 4 +#define SC_P_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY SC_P_SCU_PMIC_STANDBY 0 +#define SC_P_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 SC_P_SCU_BOOT_MODE1 0 +#define SC_P_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 SC_P_SCU_BOOT_MODE0 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 SC_P_SCU_BOOT_MODE2 0 +#define SC_P_SCU_BOOT_MODE2_SCU_DSC_RTC_CLOCK_OUTPUT_32K SC_P_SCU_BOOT_MODE2 1 +#define SC_P_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN SC_P_SNVS_TAMPER_OUT1 4 +#define SC_P_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO19_IN SC_P_SNVS_TAMPER_OUT1 5 +#define SC_P_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN SC_P_SNVS_TAMPER_OUT2 4 +#define SC_P_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO20_IN SC_P_SNVS_TAMPER_OUT2 5 +#define SC_P_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC SC_P_SNVS_TAMPER_OUT3 2 +#define SC_P_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO07_IN SC_P_SNVS_TAMPER_OUT3 4 +#define SC_P_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO21_IN SC_P_SNVS_TAMPER_OUT3 5 +#define SC_P_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD SC_P_SNVS_TAMPER_OUT4 2 +#define SC_P_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN SC_P_SNVS_TAMPER_OUT4 4 +#define SC_P_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO22_IN SC_P_SNVS_TAMPER_OUT4 5 +#define SC_P_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS SC_P_SNVS_TAMPER_IN0 2 +#define SC_P_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN SC_P_SNVS_TAMPER_IN0 4 +#define SC_P_SNVS_TAMPER_IN0_LSIO_GPIO6_IO23_IN SC_P_SNVS_TAMPER_IN0 5 +#define SC_P_SNVS_TAMPER_IN1_ADMA_SAI3_RXC SC_P_SNVS_TAMPER_IN1 2 +#define SC_P_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN SC_P_SNVS_TAMPER_IN1 4 +#define SC_P_SNVS_TAMPER_IN1_LSIO_GPIO6_IO24_IN SC_P_SNVS_TAMPER_IN1 5 +#define SC_P_SNVS_TAMPER_IN2_ADMA_SAI3_RXD SC_P_SNVS_TAMPER_IN2 2 +#define SC_P_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN SC_P_SNVS_TAMPER_IN2 4 +#define SC_P_SNVS_TAMPER_IN2_LSIO_GPIO6_IO25_IN SC_P_SNVS_TAMPER_IN2 5 +#define SC_P_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS SC_P_SNVS_TAMPER_IN3 2 +#define SC_P_SNVS_TAMPER_IN3_LSIO_GPIO2_IO12_IN SC_P_SNVS_TAMPER_IN3 4 +#define SC_P_SNVS_TAMPER_IN3_LSIO_GPIO6_IO26_IN SC_P_SNVS_TAMPER_IN3 5 +#define SC_P_SPI1_SCK_ADMA_I2C2_SDA SC_P_SPI1_SCK 2 +#define SC_P_SPI1_SCK_ADMA_SPI1_SCK SC_P_SPI1_SCK 3 +#define SC_P_SPI1_SCK_LSIO_GPIO3_IO00 SC_P_SPI1_SCK 4 +#define SC_P_SPI1_SDO_ADMA_I2C2_SCL SC_P_SPI1_SDO 2 +#define SC_P_SPI1_SDO_ADMA_SPI1_SDO SC_P_SPI1_SDO 3 +#define SC_P_SPI1_SDO_LSIO_GPIO3_IO01 SC_P_SPI1_SDO 4 +#define SC_P_SPI1_SDI_ADMA_I2C3_SCL SC_P_SPI1_SDI 2 +#define SC_P_SPI1_SDI_ADMA_SPI1_SDI SC_P_SPI1_SDI 3 +#define SC_P_SPI1_SDI_LSIO_GPIO3_IO02 SC_P_SPI1_SDI 4 +#define SC_P_SPI1_CS0_ADMA_I2C3_SDA SC_P_SPI1_CS0 2 +#define SC_P_SPI1_CS0_ADMA_SPI1_CS0 SC_P_SPI1_CS0 3 +#define SC_P_SPI1_CS0_LSIO_GPIO3_IO03 SC_P_SPI1_CS0 4 +#define SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 SC_P_QSPI0A_DATA1 0 +#define SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 SC_P_QSPI0A_DATA1 4 +#define SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 SC_P_QSPI0A_DATA0 0 +#define SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 SC_P_QSPI0A_DATA0 4 +#define SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 SC_P_QSPI0A_DATA3 0 +#define SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 SC_P_QSPI0A_DATA3 4 +#define SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 SC_P_QSPI0A_DATA2 0 +#define SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 SC_P_QSPI0A_DATA2 4 +#define SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B SC_P_QSPI0A_SS0_B 0 +#define SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 SC_P_QSPI0A_SS0_B 4 +#define SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS SC_P_QSPI0A_DQS 0 +#define SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 SC_P_QSPI0A_DQS 4 +#define SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK SC_P_QSPI0A_SCLK 0 +#define SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 SC_P_QSPI0A_SCLK 4 +#define SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK SC_P_QSPI0B_SCLK 0 +#define SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 SC_P_QSPI0B_SCLK 4 +#define SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS SC_P_QSPI0B_DQS 0 +#define SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 SC_P_QSPI0B_DQS 4 +#define SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 SC_P_QSPI0B_DATA1 0 +#define SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 SC_P_QSPI0B_DATA1 4 +#define SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 SC_P_QSPI0B_DATA0 0 +#define SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 SC_P_QSPI0B_DATA0 4 +#define SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 SC_P_QSPI0B_DATA3 0 +#define SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 SC_P_QSPI0B_DATA3 4 +#define SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 SC_P_QSPI0B_DATA2 0 +#define SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 SC_P_QSPI0B_DATA2 4 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B SC_P_QSPI0B_SS0_B 0 +#define SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 SC_P_QSPI0B_SS0_B 4 +#define SC_P_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B SC_P_QSPI0B_SS0_B 5 +/*@}*/ + +/*! + * @name Fake Pad Mux Definitions + * format: name padid 0 + */ +/*@{*/ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 +/*@}*/ + +#endif /* SC_PADS_H */ diff --git a/include/dt-bindings/pinctrl/pads-imx8qm.h b/include/dt-bindings/pinctrl/pads-imx8qm.h index e980fd55ede..5416669f035 100644 --- a/include/dt-bindings/pinctrl/pads-imx8qm.h +++ b/include/dt-bindings/pinctrl/pads-imx8qm.h @@ -275,13 +275,11 @@ #define SC_P_ENET1_RGMII_RXD2 266 /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ #define SC_P_ENET1_RGMII_RXD3 267 /* CONN.ENET1.RGMII_RXD3, DMA.UART3.RX, VPU.TSI_S1.CLK, LSIO.GPIO6.IO21 */ #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 268 /* */ -/*@}*/ -/*! - * @name Pad Mux Definitions +/* + * Pad Mux Definitions * format: name padid padmux */ -/*@{*/ #define SC_P_SIM0_CLK_DMA_SIM0_CLK SC_P_SIM0_CLK 0 #define SC_P_SIM0_CLK_LSIO_GPIO0_IO00 SC_P_SIM0_CLK 3 #define SC_P_SIM0_RST_DMA_SIM0_RST SC_P_SIM0_RST 0 @@ -955,7 +953,31 @@ #define SC_P_ENET1_RGMII_RXD3_DMA_UART3_RX SC_P_ENET1_RGMII_RXD3 1 #define SC_P_ENET1_RGMII_RXD3_VPU_TSI_S1_CLK SC_P_ENET1_RGMII_RXD3 2 #define SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 SC_P_ENET1_RGMII_RXD3 3 -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 -#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 -#endif /* SC_PADS_H */ +/* + * Fake Pad Mux Definitions + * format: name padid 0 + */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SIM_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SIM 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0 +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO_PAD SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHC 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLHT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOTHR 0 +#define SC_P_COMP_CTL_GPIO_3V3_USB3IO_PAD SC_P_COMP_CTL_GPIO_3V3_USB3IO 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI1 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL2 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 0 +#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA 0 + +#endif /* SC_PADS_H */ diff --git a/include/dt-bindings/reset/imx8mm-dispmix.h b/include/dt-bindings/reset/imx8mm-dispmix.h new file mode 100644 index 00000000000..3af137b1bfe --- /dev/null +++ b/include/dt-bindings/reset/imx8mm-dispmix.h @@ -0,0 +1,49 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __IMX8MM_DISPMIX_H__ +#define __IMX8MM_DISPMIX_H__ + +/* DISPMIX soft reset */ +#define IMX8MM_CSI_BRIDGE_CHIP_RESET 0 +#define IMX8MM_CSI_BRIDGE_IPG_HARD_ASYNC_RESET 1 +#define IMX8MM_CSI_BRIDGE_CSI_HRESET 2 +#define IMX8MM_CAMERA_PIXEL_RESET 3 +#define IMX8MM_MIPI_CSI_I_PRESET 4 +#define IMX8MM_MIPI_DSI_I_PRESET 5 +#define IMX8MM_BUS_RSTN_BLK_SYNC 6 +#define IMX8MM_DISPMIX_SFT_RSTN_NUM 7 + +/* DISPMIX clock soft enable */ +#define IMX8MM_CSI_BRIDGE_CSI_HCLK_EN 0 +#define IMX8MM_CSI_BRIDGE_SPU_CLK_EN 1 +#define IMX8MM_CSI_BRIDGE_MEM_WRAPPER_CLK_EN 2 +#define IMX8MM_CSI_BRIDGE_IPG_CLK_EN 3 +#define IMX8MM_CSI_BRIDGE_IPG_CLK_S_EN 4 +#define IMX8MM_CSI_BRIDGE_IPG_CLK_S_RAW_EN 5 +#define IMX8MM_LCDIF_APB_CLK_EN 6 +#define IMX8MM_LCDIF_PIXEL_CLK_EN 7 +#define IMX8MM_MIPI_DSI_PCLK_EN 8 +#define IMX8MM_MIPI_DSI_CLKREF_EN 9 +#define IMX8MM_MIPI_CSI_ACLK_EN 10 +#define IMX8MM_MIPI_CSI_PCLK_EN 11 +#define IMX8MM_BUS_BLK_CLK_EN 12 +#define IMX8MM_DISPMIX_CLK_EN_NUM 13 + +/* MIPI reset */ +#define IMX8MM_MIPI_S_RESET 0 +#define IMX8MM_MIPI_M_RESET 1 +#define IMX8MM_MIPI_RESET_NUM 2 + +#endif diff --git a/include/dt-bindings/reset/imx8mn-dispmix.h b/include/dt-bindings/reset/imx8mn-dispmix.h new file mode 100644 index 00000000000..8703ebe7d4b --- /dev/null +++ b/include/dt-bindings/reset/imx8mn-dispmix.h @@ -0,0 +1,47 @@ +/* + * Copyright 2019 NXP + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __IMX8MN_DISPMIX_H__ +#define __IMX8MN_DISPMIX_H__ + +/* DISPMIX soft reset */ +#define IMX8MN_MIPI_DSI_PCLK_RESET 0 +#define IMX8MN_MIPI_DSI_CLKREF_RESET 1 +#define IMX8MN_MIPI_CSI_PCLK_RESET 2 +#define IMX8MN_MIPI_CSI_ACLK_RESET 3 +#define IMX8MN_LCDIF_PIXEL_CLK_RESET 4 +#define IMX8MN_LCDIF_APB_CLK_RESET 5 +#define IMX8MN_ISI_PROC_CLK_RESET 6 +#define IMX8MN_ISI_APB_CLK_RESET 7 +#define IMX8MN_BUS_BLK_CLK_RESET 8 +#define IMX8MN_DISPMIX_SFT_RSTN_NUM 9 + +/* DISPMIX clock soft enable */ +#define IMX8MN_MIPI_DSI_PCLK_EN 0 +#define IMX8MN_MIPI_DSI_CLKREF_EN 1 +#define IMX8MN_MIPI_CSI_PCLK_EN 2 +#define IMX8MN_MIPI_CSI_ACLK_EN 3 +#define IMX8MN_LCDIF_PIXEL_CLK_EN 4 +#define IMX8MN_LCDIF_APB_CLK_EN 5 +#define IMX8MN_ISI_PROC_CLK_EN 6 +#define IMX8MN_ISI_APB_CLK_EN 7 +#define IMX8MN_BUS_BLK_CLK_EN 8 +#define IMX8MN_DISPMIX_CLK_EN_NUM 9 + +/* MIPI reset */ +#define IMX8MN_MIPI_S_RESET 0 +#define IMX8MN_MIPI_M_RESET 1 +#define IMX8MN_MIPI_RESET_NUM 2 + +#endif diff --git a/include/dt-bindings/reset/imx8mp-reset.h b/include/dt-bindings/reset/imx8mp-reset.h new file mode 100644 index 00000000000..113a9a0e835 --- /dev/null +++ b/include/dt-bindings/reset/imx8mp-reset.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2020 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8MP_H +#define DT_BINDING_RESET_IMX8MP_H + +#define IMX8MP_RESET_A53_CORE_POR_RESET0 0 +#define IMX8MP_RESET_A53_CORE_POR_RESET1 1 +#define IMX8MP_RESET_A53_CORE_POR_RESET2 2 +#define IMX8MP_RESET_A53_CORE_POR_RESET3 3 +#define IMX8MP_RESET_A53_CORE_RESET0 4 +#define IMX8MP_RESET_A53_CORE_RESET1 5 +#define IMX8MP_RESET_A53_CORE_RESET2 6 +#define IMX8MP_RESET_A53_CORE_RESET3 7 +#define IMX8MP_RESET_A53_DBG_RESET0 8 +#define IMX8MP_RESET_A53_DBG_RESET1 9 +#define IMX8MP_RESET_A53_DBG_RESET2 10 +#define IMX8MP_RESET_A53_DBG_RESET3 11 +#define IMX8MP_RESET_A53_ETM_RESET0 12 +#define IMX8MP_RESET_A53_ETM_RESET1 13 +#define IMX8MP_RESET_A53_ETM_RESET2 14 +#define IMX8MP_RESET_A53_ETM_RESET3 15 +#define IMX8MP_RESET_A53_SOC_DBG_RESET 16 +#define IMX8MP_RESET_A53_L2RESET 17 +#define IMX8MP_RESET_SW_NON_SCLR_M7C_RST 18 +#define IMX8MP_RESET_OTG1_PHY_RESET 19 +#define IMX8MP_RESET_OTG2_PHY_RESET 20 +#define IMX8MP_RESET_SUPERMIX_RESET 21 +#define IMX8MP_RESET_AUDIOMIX_RESET 22 +#define IMX8MP_RESET_MLMIX_RESET 23 +#define IMX8MP_RESET_PCIEPHY 24 +#define IMX8MP_RESET_PCIEPHY_PERST 25 +#define IMX8MP_RESET_PCIE_CTRL_APPS_EN 26 +#define IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF 27 +#define IMX8MP_RESET_HDMI_PHY_APB_RESET 28 +#define IMX8MP_RESET_MEDIA_RESET 29 +#define IMX8MP_RESET_GPU2D_RESET 30 +#define IMX8MP_RESET_GPU3D_RESET 31 +#define IMX8MP_RESET_GPU_RESET 32 +#define IMX8MP_RESET_VPU_RESET 33 +#define IMX8MP_RESET_VPU_G1_RESET 34 +#define IMX8MP_RESET_VPU_G2_RESET 35 +#define IMX8MP_RESET_VPUVC8KE_RESET 36 +#define IMX8MP_RESET_NOC_RESET 37 +#define IMX8MP_RESET_PCIE_CTRL_APPS_CLK_REQ 38 + +#define IMX8MP_RESET_NUM 39 + +#define IMX8MP_AUDIO_BLK_CTRL_EARC_RESET 0 +#define IMX8MP_AUDIO_BLK_CTRL_EARC_PHY_RESET 1 + +#define IMX8MP_AUDIO_BLK_CTRL_RESET_NUM 2 + +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_PCLK 0 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI_CLKREF 1 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_PCLK 2 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI_ACLK 3 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_PIXEL 4 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_APB 5 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_PROC 6 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISI_APB 7 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_BUS_BLK 8 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_PCLK 9 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_CSI2_ACLK 10 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_PIXEL 11 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_APB 12 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_COR 13 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AXI 14 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP1_AHB 15 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_COR 16 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AXI 17 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_ISP0_AHB 18 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_COR 19 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AXI 20 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_DWE_AHB 21 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_MIPI_DSI2 22 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF_AXI 23 +#define IMX8MP_MEDIA_BLK_CTRL_RESET_LCDIF2_AXI 24 + +#define IMX8MP_MEDIA_BLK_CTRL_RESET_NUM 25 + +#define IMX8MP_HDMI_BLK_CTRL_HDMI_TX_RESET 0 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_PHY_RESET 1 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_PAI_RESET 2 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_PVI_RESET 3 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_TRNG_RESET 4 +#define IMX8MP_HDMI_BLK_CTRL_IRQ_STEER_RESET 5 +#define IMX8MP_HDMI_BLK_CTRL_HDMI_HDCP_RESET 6 +#define IMX8MP_HDMI_BLK_CTRL_LCDIF_RESET 7 + +#define IMX8MP_HDMI_BLK_CTRL_RESET_NUM 8 + + +#endif diff --git a/include/dt-bindings/reset/imx8mq-reset.h b/include/dt-bindings/reset/imx8mq-reset.h old mode 100755 new mode 100644 index 9a301082d36..2a04e9cffde --- a/include/dt-bindings/reset/imx8mq-reset.h +++ b/include/dt-bindings/reset/imx8mq-reset.h @@ -58,7 +58,9 @@ #define IMX8MQ_RESET_DDRC2_PRST 47 /* i.MX8MM does NOT support */ #define IMX8MQ_RESET_DDRC2_CORE_RESET 48 /* i.MX8MM does NOT support */ #define IMX8MQ_RESET_DDRC2_PHY_RESET 49 /* i.MX8MM does NOT support */ +#define IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ 50 /* i.MX8M PCIe CTL CLK REQ */ +#define IMX8MQ_RESET_PCIE2_CTRL_APPS_CLK_REQ 51 /* i.MX8M PCIe CTL CLK REQ */ -#define IMX8MQ_RESET_NUM 50 +#define IMX8MQ_RESET_NUM 52 #endif diff --git a/include/dt-bindings/soc/imx8_hsio.h b/include/dt-bindings/soc/imx8_hsio.h new file mode 100644 index 00000000000..a237ceb8262 --- /dev/null +++ b/include/dt-bindings/soc/imx8_hsio.h @@ -0,0 +1,31 @@ +/* + * Copyright 2017 NXP + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_IMX8_HSIO_H +#define __DT_BINDINGS_IMX8_HSIO_H + +/* + * imx8qm hsio has pciea, pcieb and sata modules, and hsio + * can be configured to the following different work modes. + * 1 - pciea 2 lanes and one sata ahci port. + * 2 - pciea 1 lane, pcieb 1 lane and one sata ahci port. + * 3 - pciea 2 lanes, pcieb 1 lane. + * Choose one mode, refer to the exact hardware board design. + */ +#define PCIEAX2SATA 1 +#define PCIEAX1PCIEBX1SATA 2 +#define PCIEAX2PCIEBX1 3 + +#endif /* __DT_BINDINGS_IMX8_HSIO_H */ + diff --git a/include/dt-bindings/soc/imx8_pd.h b/include/dt-bindings/soc/imx8_pd.h index 682b608eef8..966d971daed 100644 --- a/include/dt-bindings/soc/imx8_pd.h +++ b/include/dt-bindings/soc/imx8_pd.h @@ -55,6 +55,7 @@ #define PD_DMA_CAN_2 dma_flexcan2 #define PD_DMA_PWM_0 dma_pwm0 #define PD_DMA_LCD_0 dma_lcd0 +#define PD_DMA_ELCDIF_PLL dma_elcdif_pll #define PD_HSIO hsio_power_domain #define PD_HSIO_PCIE_A hsio_pcie0 @@ -92,6 +93,10 @@ #define PD_LSIO_PWM_5 lsio_pwm5 #define PD_LSIO_PWM_6 lsio_pwm6 #define PD_LSIO_PWM_7 lsio_pwm7 +#define PD_LSIO_MU5A lsio_mu5a +#define PD_LSIO_MU6A lsio_mu6a +#define PD_LSIO_MU8A lsio_mu8a +#define PD_LSIO_MU9A lsio_mu9a #define PD_CONN connectivity_power_domain #define PD_CONN_SDHC_0 conn_sdhc0 @@ -135,7 +140,7 @@ #define PD_AUD_GPT_10 audio_gpt10 #define PD_AUD_AMIX audio_amix #define PD_AUD_MQS_0 audio_mqs0 -#define PD_AUD_HIFI audio_hifi +#define PD_AUD_DSP audio_dsp #define PD_AUD_OCRAM audio_ocram #define PD_AUD_MCLK_OUT_0 audio_mclkout0 #define PD_AUD_MCLK_OUT_1 audio_mclkout1 @@ -167,22 +172,39 @@ #define PD_MIPI_CSI0 mipi_csi0_power_domain #define PD_MIPI_CSI0_PWM mipi_csi0_pwm -#define PD_MIPI_CSI0_I2C mipi_csi0_i2c +#define PD_MIPI_CSI0_I2C0 mipi_csi0_i2c0 #define PD_MIPI_CSI1 mipi_csi1_power_domain #define PD_MIPI_CSI1_PWM_0 mipi_csi1_pwm -#define PD_MIPI_CSI1_I2C_0 mipi_csi1_i2c +#define PD_MIPI_CSI1_I2C0 mipi_csi1_i2c0 + +#define PD_PARALLEL_CSI parallel_csi_power_domain +#define PD_PARALLEL_CSI_I2C parallel_csi_i2c +#define PD_PARALLEL_CSI_PWM parallel_csi_pwm +#define PD_PARALLEL_CSI_PLL parallel_csi_pll #define PD_HDMI hdmi_power_domain +#define PD_HDMI_PLL_0 hdmi_pll0 +#define PD_HDMI_PLL_1 hdmi_pll1 #define PD_HDMI_I2C_0 hdmi_i2c +#define PD_HDMI_I2S_0 hdmi_i2s #define PD_HDMI_PWM_0 hdmi_pwm #define PD_HDMI_GPIO_0 hdmi_gpio #define PD_HDMI_RX hdmi_rx_power_domain +#define PD_HDMI_RX_BYPASS hdmi_rx_bypass #define PD_HDMI_RX_I2C hdmi_rx_i2c #define PD_HDMI_RX_PWM hdmi_rx_pwm #define PD_CM40 cm40_power_domain #define PD_CM40_I2C cm40_i2c #define PD_CM40_INTMUX cm40_intmux +#define PD_CM41 cm41_power_domain +#define PD_CM41_I2C cm41_i2c +#define PD_CM41_INTMUX cm41_intmux + +#define PD_CAAM caam_power_domain +#define PD_CAAM_JR1 caam_job_ring1 +#define PD_CAAM_JR2 caam_job_ring2 +#define PD_CAAM_JR3 caam_job_ring3 #endif /* __DT_BINDINGS_IMX8_PD_H */ diff --git a/include/dt-bindings/soc/imx_rsrc.h b/include/dt-bindings/soc/imx_rsrc.h index fb6878f6e24..da4b7b88791 100644 --- a/include/dt-bindings/soc/imx_rsrc.h +++ b/include/dt-bindings/soc/imx_rsrc.h @@ -34,15 +34,15 @@ #define SC_R_DC_0_BLIT1 20 #define SC_R_DC_0_BLIT2 21 #define SC_R_DC_0_BLIT_OUT 22 -#define SC_R_DC_0_CAPTURE0 23 -#define SC_R_DC_0_CAPTURE1 24 +#define SC_R_PERF 23 +#define SC_R_USB_1_PHY 24 #define SC_R_DC_0_WARP 25 -#define SC_R_DC_0_INTEGRAL0 26 -#define SC_R_DC_0_INTEGRAL1 27 +#define SC_R_V2X_MU_0 26 +#define SC_R_V2X_MU_1 27 #define SC_R_DC_0_VIDEO0 28 #define SC_R_DC_0_VIDEO1 29 #define SC_R_DC_0_FRAC0 30 -#define SC_R_DC_0_FRAC1 31 +#define SC_R_V2X_MU_2 31 #define SC_R_DC_0 32 #define SC_R_GPU_2_PID0 33 #define SC_R_DC_0_PLL_0 34 @@ -51,17 +51,17 @@ #define SC_R_DC_1_BLIT1 37 #define SC_R_DC_1_BLIT2 38 #define SC_R_DC_1_BLIT_OUT 39 -#define SC_R_DC_1_CAPTURE0 40 -#define SC_R_DC_1_CAPTURE1 41 +#define SC_R_V2X_MU_3 40 +#define SC_R_V2X_MU_4 41 #define SC_R_DC_1_WARP 42 -#define SC_R_DC_1_INTEGRAL0 43 -#define SC_R_DC_1_INTEGRAL1 44 +#define SC_R_TBU_CTL 43 +#define SC_R_SECVIO 44 #define SC_R_DC_1_VIDEO0 45 #define SC_R_DC_1_VIDEO1 46 #define SC_R_DC_1_FRAC0 47 -#define SC_R_DC_1_FRAC1 48 +#define SC_R_UNUSED13 48 #define SC_R_DC_1 49 -#define SC_R_GPU_3_PID0 50 +#define SC_R_UNUSED14 50 #define SC_R_DC_1_PLL_0 51 #define SC_R_DC_1_PLL_1 52 #define SC_R_SPI_0 53 @@ -151,10 +151,10 @@ #define SC_R_DMA_1_CH29 137 #define SC_R_DMA_1_CH30 138 #define SC_R_DMA_1_CH31 139 -#define SC_R_UNUSED1 140 -#define SC_R_UNUSED2 141 -#define SC_R_UNUSED3 142 -#define SC_R_UNUSED4 143 +#define SC_R_V2X_PID0 140 +#define SC_R_V2X_PID1 141 +#define SC_R_V2X_PID2 142 +#define SC_R_V2X_PID3 143 #define SC_R_GPU_0_PID0 144 #define SC_R_GPU_0_PID1 145 #define SC_R_GPU_0_PID2 146 @@ -301,8 +301,8 @@ #define SC_R_M4_0_UART 287 #define SC_R_M4_0_I2C 288 #define SC_R_M4_0_INTMUX 289 -#define SC_R_M4_0_SIM 290 -#define SC_R_M4_0_WDOG 291 +#define SC_R_ENET_0_A0 290 +#define SC_R_ENET_0_A1 291 #define SC_R_M4_0_MU_0B 292 #define SC_R_M4_0_MU_0A0 293 #define SC_R_M4_0_MU_0A1 294 @@ -321,8 +321,8 @@ #define SC_R_M4_1_UART 307 #define SC_R_M4_1_I2C 308 #define SC_R_M4_1_INTMUX 309 -#define SC_R_M4_1_SIM 310 -#define SC_R_M4_1_WDOG 311 +#define SC_R_UNUSED17 310 +#define SC_R_UNUSED18 311 #define SC_R_M4_1_MU_0B 312 #define SC_R_M4_1_MU_0A0 313 #define SC_R_M4_1_MU_0A1 314 @@ -334,7 +334,7 @@ #define SC_R_SAI_2 320 #define SC_R_IRQSTR_SCU2 321 #define SC_R_IRQSTR_DSP 322 -#define SC_R_UNUSED5 323 +#define SC_R_ELCDIF_PLL 323 #define SC_R_OCRAM 324 #define SC_R_AUDIO_PLL_0 325 #define SC_R_PI_0 326 @@ -377,12 +377,12 @@ #define SC_R_VPU_PID5 363 #define SC_R_VPU_PID6 364 #define SC_R_VPU_PID7 365 -#define SC_R_VPU_UART 366 -#define SC_R_VPUCORE 367 -#define SC_R_VPUCORE_0 368 -#define SC_R_VPUCORE_1 369 -#define SC_R_VPUCORE_2 370 -#define SC_R_VPUCORE_3 371 +#define SC_R_ENET_0_A2 366 +#define SC_R_ENET_1_A0 367 +#define SC_R_ENET_1_A1 368 +#define SC_R_ENET_1_A2 369 +#define SC_R_ENET_1_A3 370 +#define SC_R_ENET_1_A4 371 #define SC_R_DMA_4_CH0 372 #define SC_R_DMA_4_CH1 373 #define SC_R_DMA_4_CH2 374 @@ -552,7 +552,12 @@ #define SC_R_VPU_MU_3 538 #define SC_R_VPU_ENC_1 539 #define SC_R_VPU 540 -#define SC_R_LAST 541 +#define SC_R_DMA_5_CH0 541 +#define SC_R_DMA_5_CH1 542 +#define SC_R_DMA_5_CH2 543 +#define SC_R_DMA_5_CH3 544 +#define SC_R_ATTESTATION 545 +#define SC_R_LAST 546 #define SC_R_NONE 0xFFF0 #endif /* DT_BINDINGS_RSCRC_IMX_H */ diff --git a/include/dwc3-uboot.h b/include/dwc3-uboot.h index e08530ec4e5..bcd7428f4cd 100644 --- a/include/dwc3-uboot.h +++ b/include/dwc3-uboot.h @@ -18,6 +18,7 @@ struct dwc3_device { enum usb_dr_mode dr_mode; enum usb_phy_interface hsphy_mode; u32 maximum_speed; + u16 power_down_scale; unsigned tx_fifo_resize:1; unsigned has_lpm_erratum; u8 lpm_nyet_threshold; diff --git a/include/eeprom_field.h b/include/eeprom_field.h index 05c0d145921..311c49401a6 100644 --- a/include/eeprom_field.h +++ b/include/eeprom_field.h @@ -14,25 +14,36 @@ struct eeprom_field { char *name; int size; - unsigned char *buf; - void (*print)(const struct eeprom_field *eeprom_field); - int (*update)(struct eeprom_field *eeprom_field, char *value); + void (*print)(const struct eeprom_field *eeprom_field, uchar *fbuf); + int (*update)(struct eeprom_field *eeprom_field, uchar *fbuf, + char *value); + int (*read)(const struct eeprom_field *field, uchar *fbuf, uchar *buf, + int buf_size); }; -void eeprom_field_print_bin(const struct eeprom_field *field); -int eeprom_field_update_bin(struct eeprom_field *field, char *value); - -void eeprom_field_print_bin_rev(const struct eeprom_field *field); -int eeprom_field_update_bin_rev(struct eeprom_field *field, char *value); - -void eeprom_field_print_mac(const struct eeprom_field *field); -int eeprom_field_update_mac(struct eeprom_field *field, char *value); - -void eeprom_field_print_ascii(const struct eeprom_field *field); -int eeprom_field_update_ascii(struct eeprom_field *field, char *value); - -void eeprom_field_print_reserved(const struct eeprom_field *field); -int eeprom_field_update_reserved(struct eeprom_field *field, char *value); +void eeprom_field_print_bin(const struct eeprom_field *field, uchar *fbuf); +int eeprom_field_update_bin(struct eeprom_field *field, uchar *fbuf, + char *value); +int eeprom_field_read_bin(const struct eeprom_field *field, uchar *fbuf, + uchar *buf, int buf_size); + +void eeprom_field_print_bin_rev(const struct eeprom_field *field, uchar *fbuf); +int eeprom_field_update_bin_rev(struct eeprom_field *field, uchar *fbuf, + char *value); +int eeprom_field_read_rev(const struct eeprom_field *field, uchar *fbuf, + uchar *buf, int buf_size); + +void eeprom_field_print_mac(const struct eeprom_field *field, uchar *fbuf); +int eeprom_field_update_mac(struct eeprom_field *field, uchar *fbuf, + char *value); + +void eeprom_field_print_ascii(const struct eeprom_field *field, uchar *fbuf); +int eeprom_field_update_ascii(struct eeprom_field *field, uchar *fbuf, + char *value); + +void eeprom_field_print_reserved(const struct eeprom_field *field, uchar *fbuf); +int eeprom_field_update_reserved(struct eeprom_field *field, uchar *fbuf, + char *value); #endif diff --git a/include/eeprom_layout.h b/include/eeprom_layout.h index 730d963ab96..50e8ec10858 100644 --- a/include/eeprom_layout.h +++ b/include/eeprom_layout.h @@ -22,6 +22,8 @@ struct eeprom_layout { void (*print)(const struct eeprom_layout *eeprom_layout); int (*update)(struct eeprom_layout *eeprom_layout, char *field_name, char *new_data); + int (*read)(struct eeprom_layout *eeprom_layout, char *field_name, + uchar *buf, int buf_size); }; void eeprom_layout_setup(struct eeprom_layout *layout, unsigned char *buf, diff --git a/include/efi_api.h b/include/efi_api.h index 4ccde1d24da..2671177078f 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -230,6 +230,10 @@ enum efi_reset_type { EFI_GUID(0x6dcbd5ed, 0xe82d, 0x4c44, 0xbd, 0xa1, \ 0x71, 0x94, 0x19, 0x9a, 0xd9, 0x2a) +#define EFI_MEMORY_ONLY_RESET_CONTROL_GUID \ + EFI_GUID(0xe20939be, 0x32d4, 0x41be, 0xa1, 0x50, \ + 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29) + struct efi_capsule_header { efi_guid_t capsule_guid; u32 header_size; diff --git a/include/efi_loader.h b/include/efi_loader.h index 68daa1a4a9d..445da8f0c89 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -214,6 +214,8 @@ extern const efi_guid_t efi_guid_rng_protocol; extern const efi_guid_t efi_guid_capsule_report; /* GUID of firmware management protocol */ extern const efi_guid_t efi_guid_firmware_management_protocol; +/* GUID of memory only reset control */ +extern const efi_guid_t efi_memory_only_reset_control_guid; extern unsigned int __efi_runtime_start, __efi_runtime_stop; extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop; diff --git a/include/env.h b/include/env.h index c15339a93f1..8fb7888711b 100644 --- a/include/env.h +++ b/include/env.h @@ -377,4 +377,11 @@ int env_get_char(int index); * This is used for those unfortunate archs with crappy toolchains */ void env_reloc(void); + +#ifdef ENV_IS_EMBEDDED +#define env_get_offset(x) x +#else +long long env_get_offset(long long defautl_offset); +#endif + #endif diff --git a/include/env_internal.h b/include/env_internal.h index 708c833a550..9f922079b59 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -127,6 +127,7 @@ extern const unsigned char default_environment[]; enum env_location { ENVL_UNKNOWN, ENVL_EEPROM, + ENVL_ESATA, ENVL_EXT4, ENVL_FAT, ENVL_FLASH, diff --git a/include/fastboot.h b/include/fastboot.h index 57daaf12982..70d5b330627 100644 --- a/include/fastboot.h +++ b/include/fastboot.h @@ -48,7 +48,26 @@ enum { FASTBOOT_COMMAND_ACMD, FASTBOOT_COMMAND_UCMD, #endif - +#ifdef CONFIG_FSL_FASTBOOT + FASTBOOT_COMMAND_UPLOAD, + FASTBOOT_COMMAND_GETSTAGED, +#ifdef CONFIG_FASTBOOT_LOCK + FASTBOOT_COMMAND_FLASHING, + FASTBOOT_COMMAND_OEM, +#endif +#ifdef CONFIG_AVB_SUPPORT + FASTBOOT_COMMAND_SETACTIVE, +#endif +#ifdef CONFIG_AVB_ATX + FASTBOOT_COMMAND_STAGE, +#endif +#endif +#ifdef CONFIG_ANDROID_RECOVERY + FASTBOOT_COMMAND_RECOVERY_FASTBOOT, +#endif +#ifdef CONFIG_VIRTUAL_AB_SUPPORT + FASTBOOT_COMMAND_SNAPSHOT_UPDATE, +#endif FASTBOOT_COMMAND_COUNT }; @@ -176,4 +195,9 @@ void fastboot_data_complete(char *response); #if CONFIG_IS_ENABLED(FASTBOOT_UUU_SUPPORT) void fastboot_acmd_complete(void); #endif + +int fastboot_tx_write_more(const char *buffer); + +int fastboot_tx_write(const char *buffer, unsigned int buffer_size); + #endif /* _FASTBOOT_H_ */ diff --git a/include/fb_fsl.h b/include/fb_fsl.h new file mode 100644 index 00000000000..dece725c1b9 --- /dev/null +++ b/include/fb_fsl.h @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + */ + +#ifndef FB_FSL_H +#define FB_FSL_H +#include +#include + +#define FASTBOOT_PTENTRY_FLAGS_REPEAT(n) (n & 0x0f) +#define FASTBOOT_PTENTRY_FLAGS_REPEAT_MASK 0x0000000F + +/* Writes happen a block at a time. + If the write fails, go to next block + NEXT_GOOD_BLOCK and CONTIGOUS_BLOCK can not both be set */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_NEXT_GOOD_BLOCK 0x00000010 + +/* Find a contiguous block big enough for a the whole file + NEXT_GOOD_BLOCK and CONTIGOUS_BLOCK can not both be set */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_CONTIGUOUS_BLOCK 0x00000020 + +/* Write the file with write.i */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_I 0x00000100 + +/* Write the file with write.trimffs */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_TRIMFFS 0x00000200 + +/* Write the file as a series of variable/value pairs + using the setenv and saveenv commands */ +#define FASTBOOT_PTENTRY_FLAGS_WRITE_ENV 0x00000400 + +/* Uneraseable partition */ +#define FASTBOOT_PTENTRY_FLAGS_UNERASEABLE 0x00000800 + +#define FASTBOOT_MMC_BOOT_PARTITION_ID 1 +#define FASTBOOT_MMC_USER_PARTITION_ID 0 +#define FASTBOOT_MMC_NONE_PARTITION_ID -1 +#define FASTBOOT_MMC_BOOT1_PARTITION_ID 2 + +#define FASTBOOT_PARTITION_TEE "tos" +#define FASTBOOT_PARTITION_PRDATA "presistdata" + +#ifdef CONFIG_AVB_SUPPORT +#define FASTBOOT_PARTITION_AVBKEY "avbkey" +#endif + +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +#define FASTBOOT_MCU_FIRMWARE_PARTITION "mcu_os" +#endif + +#define FASTBOOT_PARTITION_METADATA "metadata" + +#ifdef CONFIG_ANDROID_AB_SUPPORT +#define FASTBOOT_PARTITION_BOOT_A "boot_a" +#define FASTBOOT_PARTITION_RECOVERY "recovery" +#define FASTBOOT_PARTITION_SYSTEM_A "system_a" +#define FASTBOOT_PARTITION_BOOTLOADER "bootloader0" +#define FASTBOOT_PARTITION_DATA "userdata" +#define FASTBOOT_PARTITION_BOOT_B "boot_b" +#define FASTBOOT_PARTITION_SYSTEM_B "system_b" +#define FASTBOOT_PARTITION_OEM_A "oem_a" +#define FASTBOOT_PARTITION_VENDOR_A "vendor_a" +#define FASTBOOT_PARTITION_OEM_B "oem_b" +#define FASTBOOT_PARTITION_VENDOR_B "vendor_b" +#ifdef CONFIG_AVB_SUPPORT +#define FASTBOOT_PARTITION_VBMETA_A "vbmeta_a" +#define FASTBOOT_PARTITION_VBMETA_B "vbmeta_b" +#endif +#define FASTBOOT_PARTITION_MISC "misc" +#define FASTBOOT_PARTITION_GPT "gpt" +#define FASTBOOT_PARTITION_FBMISC "fbmisc" +#else +#define FASTBOOT_PARTITION_BOOT "boot" +#define FASTBOOT_PARTITION_RECOVERY "recovery" +#define FASTBOOT_PARTITION_SYSTEM "system" +#define FASTBOOT_PARTITION_CACHE "cache" +#define FASTBOOT_PARTITION_DEVICE "device" +#define FASTBOOT_PARTITION_BOOTLOADER "bootloader" +#define FASTBOOT_PARTITION_DATA "userdata" +#define FASTBOOT_PARTITION_GPT "gpt" +#define FASTBOOT_PARTITION_MISC "misc" +#define FASTBOOT_PARTITION_FBMISC "fbmisc" +#endif + +#ifdef CONFIG_IMX_TRUSTY_OS +#ifndef CONFIG_AVB_ATX +#define FASTBOOT_SET_RPMB_STAGED_KEY "set-rpmb-staged-key" +#define FASTBOOT_SET_RPMB_HARDWARE_KEY "set-rpmb-hardware-key" +#define FASTBOOT_SET_VBMETA_PUBLIC_KEY "set-public-key" +#define FASTBOOT_ERASE_RPMB "erase-rpmb" +#endif + +#define FASTBOOT_SET_CA_RESP "at-set-ca-response" +#define FASTBOOT_GET_CA_REQ "at-get-ca-request" +#define FASTBOOT_SET_RSA_ATTESTATION_KEY "set-rsa-atte-key" +#define FASTBOOT_SET_EC_ATTESTATION_KEY "set-ec-atte-key" +#define FASTBOOT_APPEND_RSA_ATTESTATION_CERT "append-rsa-atte-cert" +#define FASTBOOT_APPEND_EC_ATTESTATION_CERT "append-ec-atte-cert" +#define FASTBOOT_SET_RSA_ATTESTATION_KEY_ENC "set-rsa-atte-key-enc" +#define FASTBOOT_SET_EC_ATTESTATION_KEY_ENC "set-ec-atte-key-enc" +#define FASTBOOT_APPEND_RSA_ATTESTATION_CERT_ENC "append-rsa-atte-cert-enc" +#define FASTBOOT_APPEND_EC_ATTESTATION_CERT_ENC "append-ec-atte-cert-enc" +#define FASTBOOT_GET_MPPUBK "get-mppubk" +#define FASTBOOT_GET_SERIAL_NUMBER "get-serial-number" +#define FASTBOOT_APPEND_ATTESTATION_ID "append-device-id" +#define FASTBOOT_WV_PROVISION "provision-wv-keybox" +#define FASTBOOT_WV_PROVISION_ENC "provision-wv-keybox-enc" +#endif + +#ifdef CONFIG_ANDROID_THINGS_SUPPORT +#define FASTBOOT_BOOTLOADER_VBOOT_KEY "fuse at-bootloader-vboot-key" +#ifdef CONFIG_AVB_ATX +#define FASTBOOT_AVB_AT_PERM_ATTR "fuse at-perm-attr" +#define FASTBOOT_AT_UNLOCK_VBOOT "at-unlock-vboot" +#define FASTBOOT_AT_LOCK_VBOOT "at-lock-vboot" +#define FASTBOOT_AT_DISABLE_UNLOCK_VBOOT "at-disable-unlock-vboot" +#define FASTBOOT_AT_GET_UNLOCK_CHALLENGE "at-get-vboot-unlock-challenge" +#endif /* CONFIG_AVB_ATX */ +#endif /* CONFIG_ANDROID_THINGS_SUPPORT */ + +#ifndef TEE_HWPARTITION_ID +#define TEE_HWPARTITION_ID 2 +#endif + +#define FASTBOOT_PARTITION_ALL "all" + +#define MMC_SATA_BLOCK_SIZE 512 + +#define ANDROID_MBR_OFFSET 0 +#define ANDROID_MBR_SIZE 0x200 +#define ANDROID_BOOTLOADER_SIZE 0x400000 + +#define ANDROID_GPT_OFFSET 0 +#define ANDROID_GPT_SIZE 0x100000 +#define ANDROID_GPT_END 0x4400 + +/* To support the Android-style naming of flash */ +#define MAX_PTN 32 + +enum { + DEV_SATA, + DEV_MMC, + DEV_NAND, +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT + /* SPI Flash */ + DEV_SF +#endif +}; + +typedef enum { +#ifdef CONFIG_ANDROID_RECOVERY + /* Revoery boot due to combo keys pressed */ + BOOTMODE_RECOVERY_KEY_PRESSED, + /* Recovery boot due to boot-recovery cmd in misc parition */ + BOOTMODE_RECOVERY_BCB_CMD, +#endif + /* Fastboot boot due to bootonce-bootloader cmd in misc parition */ + BOOTMODE_FASTBOOT_BCB_CMD, + /* Normal boot */ + BOOTMODE_NORMAL +}FbBootMode; + +/* flash partitions are defined in terms of blocks +** (flash erase units) +*/ +struct fastboot_ptentry { + /* The logical name for this partition, null terminated */ + char name[20]; + /* The start wrt the nand part, must be multiple of nand block size */ + unsigned int start; + /* The length of the partition, must be multiple of nand block size */ + unsigned long length; + /* Controls the details of how operations are done on the partition + See the FASTBOOT_PTENTRY_FLAGS_*'s defined below */ + unsigned int flags; + /* partition id: 0 - normal partition; 1 - boot partition */ + unsigned int partition_id; + /* partition number in block device */ + unsigned int partition_index; + /* partition file system type in string */ + char fstype[16]; + /* filesystem UUID as string, if exists */ +#ifdef CONFIG_PARTITION_UUIDS + char uuid[37]; +#endif +}; + +struct fastboot_device_info { + unsigned char type; + unsigned char dev_id; +}; + +extern struct fastboot_device_info fastboot_devinfo; + +#ifdef CONFIG_FLASH_MCUFIRMWARE_SUPPORT +extern struct fastboot_device_info fastboot_firmwareinfo; +#endif + +extern struct fastboot_ptentry g_ptable[MAX_PTN]; +extern unsigned int g_pcount; + +/* Prepare the fastboot environments, + * should be executed before "fastboot" cmd + */ +void fastboot_setup(void); + + +/* The Android-style flash handling */ + +/* tools to populate and query the partition table */ +void fastboot_flash_add_ptn(struct fastboot_ptentry *ptn); +struct fastboot_ptentry *fastboot_flash_find_ptn(const char *name); +struct fastboot_ptentry *fastboot_flash_get_ptn(unsigned n); +unsigned int fastboot_flash_get_ptn_count(void); +void fastboot_flash_dump_ptn(void); + +/* Make board into special boot mode */ +void fastboot_run_bootmode(void); + +/*Setup board-relative fastboot environment */ +void board_fastboot_setup(void); + +/*return partition index according name*/ +int fastboot_flash_find_index(const char *name); + +bool fastboot_parts_is_slot(void); + +bool fastboot_parts_is_raw(struct fastboot_ptentry *ptn); + +/*get partition base name from gpt without "_a/_b"*/ +int fastboot_parts_get_name(char (*partition_base_name)[20]); + +void fastboot_load_partitions(void); + +void fastboot_none_resp(char *response); + +void fastboot_process_erase(const char *cmdbuf, char *response); + +void fastboot_process_flash(const char *cmdbuf, void *download_buffer, + u32 download_bytes, char *response); + +/*check whether bootloader is overlay with GPT table*/ +bool bootloader_gpt_overlay(void); +/* Check whether the combo keys pressed + * Return 1 if combo keys pressed for recovery boot + * Return 0 if no combo keys pressed + */ +int is_recovery_key_pressing(void); + +/* Reads |num_bytes| from offset |offset| from partition with name + * |partition| (NUL-terminated UTF-8 string). If |offset| is + * negative, its absolute value should be interpreted as the number + * of bytes from the end of the partition. + * It's basically copied from fsl_read_from_partition_multi() because + * we may want to read partition when AVB is not enabled. */ +int read_from_partition_multi(const char* partition, + int64_t offset, size_t num_bytes,void* buffer, size_t* out_num_read); +#endif /* FB_FSL_H */ diff --git a/include/fs.h b/include/fs.h index 0794b50d102..acaa553460f 100644 --- a/include/fs.h +++ b/include/fs.h @@ -19,6 +19,8 @@ struct cmd_tbl; struct blk_desc; +int do_fat_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); + /** * do_fat_fsload - Run the fatload command * diff --git a/include/fsl_avb.h b/include/fsl_avb.h new file mode 100644 index 00000000000..9c7cfe059d0 --- /dev/null +++ b/include/fsl_avb.h @@ -0,0 +1,207 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_AVB_H__ +#define __FSL_AVB_H__ + +#include "../lib/avb/libavb_atx/libavb_atx.h" +#include "../lib/avb/fsl/fsl_bootctrl.h" +/* Reads |num_bytes| from offset |offset| from partition with name + * |partition| (NUL-terminated UTF-8 string). If |offset| is + * negative, its absolute value should be interpreted as the number + * of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * |offset| is outside the partition, and AVB_IO_RESULT_ERROR_IO if + * there was an I/O error from the underlying I/O subsystem. If the + * operation succeeds as requested AVB_IO_RESULT_OK is returned and + * the data is available in |buffer|. + * + * The only time partial I/O may occur is if reading beyond the end + * of the partition. In this case the value returned in + * |out_num_read| may be smaller than |num_bytes|. + */ +AvbIOResult fsl_read_from_partition(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read); + +/* multi block read version + * */ +AvbIOResult fsl_read_from_partition_multi(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read); + +/* Writes |num_bytes| from |bffer| at offset |offset| to partition + * with name |partition| (NUL-terminated UTF-8 string). If |offset| + * is negative, its absolute value should be interpreted as the + * number of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * byterange goes outside the partition, and AVB_IO_RESULT_ERROR_IO + * if there was an I/O error from the underlying I/O subsystem. If + * the operation succeeds as requested AVB_IO_RESULT_OK is + * returned. + * + * This function never does any partial I/O, it either transfers all + * of the requested bytes or returns an error. + */ +AvbIOResult fsl_write_to_partition(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + const void* buffer); + +/* Checks if the given public key used to sign the 'vbmeta' + * partition is trusted. Boot loaders typically compare this with + * embedded key material generated with 'avbtool + * extract_public_key'. + * + * If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set - + * true if trusted or false if untrusted. + */ +AvbIOResult fsl_validate_vbmeta_public_key_rpmb(AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted); + +/* Gets the rollback index corresponding to the slot given by + * |rollback_index_slot|. The value is returned in + * |out_rollback_index|. Returns AVB_IO_RESULT_OK if the rollback + * index was retrieved, otherwise an error code. + * + * A device may have a limited amount of rollback index slots (say, + * one or four) so may error out if |rollback_index_slot| exceeds + * this number. + */ +AvbIOResult fsl_read_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t* out_rollback_index); + +/* Sets the rollback index corresponding to the slot given by + * |rollback_index_slot| to |rollback_index|. Returns + * AVB_IO_RESULT_OK if the rollback index was set, otherwise an + * error code. + * + * A device may have a limited amount of rollback index slots (say, + * one or four) so may error out if |rollback_index_slot| exceeds + * this number. + */ +AvbIOResult fsl_write_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t rollback_index); + +/* Gets whether the device is unlocked. The value is returned in + * |out_is_unlocked| (true if unlocked, false otherwise). Returns + * AVB_IO_RESULT_OK if the state was retrieved, otherwise an error + * code. + */ +AvbIOResult fsl_read_is_device_unlocked(AvbOps* ops, bool* out_is_unlocked); + +/* Gets the unique partition GUID for a partition with name in + * |partition| (NUL-terminated UTF-8 string). The GUID is copied as + * a string into |guid_buf| of size |guid_buf_size| and will be NUL + * terminated. The string must be lower-case and properly + * hyphenated. For example: + * + * 527c1c6d-6361-4593-8842-3c78fcd39219 + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_unique_guid_for_partition(AvbOps* ops, + const char* partition, + char* guid_buf, + size_t guid_buf_size); + +/* Gets the size of a partition with the name in |partition| + * (NUL-terminated UTF-8 string). Returns the value in + * |out_size_num_bytes|. + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_size_of_partition(AvbOps* ops, + const char* partition, + uint64_t* out_size_num_bytes); + +/* reset rollback_index part in avbkey partition + * used in the switch from LOCK to UNLOCK + * return 0 if success, non 0 if fail. + * */ +int rbkidx_erase(void); + +/* init the avbkey in rpmb partition, include the header/public key/rollback index + * for public key/rollback index part, use caam to do encrypt + * return 0 if success, non 0 if fail. + * */ +int avbkey_init(uint8_t *plainkey, uint32_t keylen); + +/* Reads permanent |attributes| data. There are no restrictions on where this + * data is stored. On success, returns AVB_IO_RESULT_OK and populates + * |attributes|. + */ +AvbIOResult fsl_read_permanent_attributes( + AvbAtxOps* atx_ops, AvbAtxPermanentAttributes* attributes); + +/* Reads a |hash| of permanent attributes. This hash MUST be retrieved from a + * permanently read-only location (e.g. fuses) when a device is LOCKED. On + * success, returned AVB_IO_RESULT_OK and populates |hash|. + */ +AvbIOResult fsl_read_permanent_attributes_hash(AvbAtxOps* atx_ops, + uint8_t hash[AVB_SHA256_DIGEST_SIZE]); + +/* Provides the key version of a key used during verification. This may be + * useful for managing the minimum key version. + */ +void fsl_set_key_version(AvbAtxOps* atx_ops, + size_t rollback_index_location, + uint64_t key_version); + +/* Generates |num_bytes| random bytes and stores them in |output|, + * which must point to a buffer large enough to store the bytes. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_random(AvbAtxOps* atx_ops, + size_t num_bytes, + uint8_t* output); + +/* Program ATX perm_attr into RPMB partition */ +int avb_atx_fuse_perm_attr(uint8_t *staged_buffer, uint32_t size); + +/* Initialize rpmb key with the staged key */ +int fastboot_set_rpmb_staged_key(uint8_t *staged_buf, uint32_t key_size); + +/* Initialize rpmb key with hardware key which is derived from BKEK */ +int fastboot_set_rpmb_hardware_key(void); + +/* Generate ATX unlock challenge */ +int avb_atx_get_unlock_challenge(struct AvbAtxOps* atx_ops, + uint8_t *upload_buffer, uint32_t *size); +/* Verify ATX unlock credential */ +int avb_atx_verify_unlock_credential(struct AvbAtxOps* atx_ops, + uint8_t *staged_buffer); +/* Check if the perm-attr have been fused. */ +bool perm_attr_are_fused(void); + +/* Check if the unlock vboot is already disabled */ +bool at_unlock_vboot_is_disabled(void); + +/* disable at unlock vboot */ +int at_disable_vboot_unlock(void); + +/* Set vbmeta public key */ +int avb_set_public_key(uint8_t *staged_buffer, uint32_t size); + +/* Get manufacture protection public key */ +int fastboot_get_mppubk(uint8_t *staged_buffer, uint32_t *size); + +/* Check if hab is closed. */ +bool hab_is_enabled(void); + +/* Return if device is in spl recovery mode. */ +bool is_spl_recovery(void); + +#endif /* __FSL_AVB_H__ */ diff --git a/include/fsl_avb_logo.h b/include/fsl_avb_logo.h new file mode 100644 index 00000000000..300d137a920 --- /dev/null +++ b/include/fsl_avb_logo.h @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright NXP 2020 + * + */ + +#ifndef __FSL_AVB_LOGO_H__ +#define __FSL_AVB_LOGO_H__ + +extern unsigned short orange_warning_bmp_palette[]; +extern unsigned char orange_warning_bmp_bitmap[]; + +#endif /* __FSL_AVB_LOGO_H__ */ diff --git a/include/fsl_caam.h b/include/fsl_caam.h new file mode 100644 index 00000000000..29f5ca12953 --- /dev/null +++ b/include/fsl_caam.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2012-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * Copyright 2018 NXP + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CAAM_H__ +#define __CAAM_H__ + +//! @name Error codes +//@{ +#if !defined(SUCCESS) +#define SUCCESS (0) +#endif + +#define ERROR_ANY (-1) +#define ERROR_IN_PAGE_ALLOC (1) + + +//////////////////////////////////////////////////////////////////////////////// +//! @brief Enable and initialize the CAAM driver. +//! +//! This function enables the clock to the CAAM. It initializes the RNG, and +//! instantiate it to allow generation of key for blob. +//! +//////////////////////////////////////////////////////////////////////////////// +void caam_open(void); + +//////////////////////////////////////////////////////////////////////////////// +//! @brief Generate a blob of a secure key. +//! +//! @param[in] plain_data_addr Location address of the plain text data. +//! @param[in] blob_addr Location address of the blob. +//! @param[in] size Size in bytes of the data to encrypt. +//! +//! @return SUCCESS +//! @return ERROR_XXX +//////////////////////////////////////////////////////////////////////////////// +uint32_t caam_gen_blob(uint32_t plain_data_addr, uint32_t blob_addr, uint32_t size); + +//////////////////////////////////////////////////////////////////////////////// +//! @brief Decapsulate a blob of a secure key. +//! +//! @param[in] blob_addr Location address of the blob. +//! +//! @return SUCCESS +//! @return ERROR_XXX +//////////////////////////////////////////////////////////////////////////////// +uint32_t caam_decap_blob(uint32_t plain_text, uint32_t blob_addr, uint32_t size); +uint32_t caam_hwrng(uint8_t *output_ptr, uint32_t output_len); + +#endif /* __CAAM_H__ */ diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 850a304bd7d..f86afe5dad8 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -190,6 +190,9 @@ #define DLL_RESET 0x40000000 #define DLL_FREQ_SEL 0x08000000 +/* DLL config 1 register */ +#define DLL_PD_PULSE_STRETCH_SEL 0x80000000 + /* DLL status 0 register */ #define DLL_STS_SLV_LOCK 0x08000000 diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 45ed635a77b..b0920344641 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -39,6 +39,7 @@ #define VENDORSPEC_HCKEN 0x00001000 #define VENDORSPEC_IPGEN 0x00000800 #define VENDORSPEC_INIT 0x20007809 +#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 #define IRQSTAT 0x0002e030 #define IRQSTAT_DMAE (0x10000000) @@ -96,6 +97,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) +#define PRSSTAT_SDOFF (0x00000080) #define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 1c6f1eb23ec..ebdf6a9ef32 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -3,6 +3,7 @@ * Common internal memory map for some Freescale SoCs * * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2018 NXP */ #ifndef __FSL_SEC_H @@ -12,8 +13,8 @@ #include #ifdef CONFIG_SYS_FSL_SEC_LE -#define sec_in32(a) in_le32(a) -#define sec_out32(a, v) out_le32(a, v) +#define sec_in32(a) in_le32((ulong *)(ulong)(a)) +#define sec_out32(a, v) out_le32((ulong *)(ulong)(a), v) #define sec_in16(a) in_le16(a) #define sec_clrbits32 clrbits_le32 #define sec_setbits32 setbits_le32 @@ -27,10 +28,13 @@ #error Neither CONFIG_SYS_FSL_SEC_LE nor CONFIG_SYS_FSL_SEC_BE is defined #endif +#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ + /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */ #if CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* RNG4 TRNG test registers */ struct rng4tst { +#define RTMCTL_ACC 0x20 #define RTMCTL_PRGM 0x00010000 /* 1 -> program mode, 0 -> run mode */ #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in both entropy shifter and @@ -191,11 +195,10 @@ typedef struct ccsr_sec { #define SEC_CHAVID_LS_RNG_SHIFT 16 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000 -#define CONFIG_JRSTARTR_JR0 0x00000001 - struct jr_regs { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) u32 irba_l; u32 irba_h; #else @@ -209,7 +212,8 @@ struct jr_regs { u32 rsvd3; u32 irja; #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) u32 orba_l; u32 orba_h; #else @@ -242,7 +246,8 @@ struct jr_regs { */ struct sg_entry { #if defined(CONFIG_SYS_FSL_SEC_LE) && \ - !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) + !(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)) uint32_t addr_lo; /* Memory Address - lo */ uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else @@ -261,9 +266,8 @@ struct sg_entry { #define SG_ENTRY_OFFSET_SHIFT 0 }; -#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */ - -#if defined(CONFIG_MX6) || defined(CONFIG_MX7) +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) /* Job Ring Base Address */ #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) /* Secure Memory Offset varies accross versions */ @@ -271,7 +275,8 @@ struct sg_entry { #define SM_V2_OFFSET 0xa00 /*Secure Memory Versioning */ #define SMVID_V2 0x20105 -#define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2) +#define SM_VERSION(x) ({typeof(x) _x = x; \ + _x < SMVID_V2 ? 1 : (_x < 0x20300 ? 2 : 3); }) #define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET) /* CAAM Job Ring 0 Registers */ /* Secure Memory Partition Owner register */ @@ -298,8 +303,10 @@ struct sg_entry { #define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4) #define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC) #define SM_PERM(v) (v == 1 ? 0x10 : 0x4) -#define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8) -#define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC) +#define SM_GROUP2(v) ({typeof(v) _v = v; \ + _v == 1 ? 0x14 : (_v == 2 ? 0x8 : 0xC); }) +#define SM_GROUP1(v) ({typeof(v) _v = v; \ + _v == 1 ? 0x18 : (_v == 2 ? 0xC : 0x8); }) #define CMD_PAGE_ALLOC 0x1 #define CMD_PAGE_DEALLOC 0x2 #define CMD_PART_DEALLOC 0x3 @@ -317,10 +324,15 @@ struct sg_entry { #define SEC_MEM_PAGE2 (CAAM_ARB_BASE_ADDR + 0x2000) #define SEC_MEM_PAGE3 (CAAM_ARB_BASE_ADDR + 0x3000) -#define JR_MID 2 /* Matches ROM configuration */ -#define KS_G1 (1 << JR_MID) /* CAAM only */ -#define PERM 0x0000B008 /* Clear on release, lock SMAP - * lock SMAG group 1 Blob */ +#ifdef CONFIG_IMX8M +#define JR_MID (1) /* Matches ATF configuration */ +#define KS_G1 (0x10000 << JR_MID) /* CAAM only */ +#define PERM (0xB080) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ +#else +#define JR_MID (2) /* Matches ROM configuration */ +#define KS_G1 BIT(JR_MID) /* CAAM only */ +#define PERM (0xB008) /* CSP, SMAP_LCK, SMAG_LCK, G1_BLOB */ +#endif /* CONFIG_IMX8M */ /* HAB WRAPPED KEY header */ #define WRP_HDR_SIZE 0x08 @@ -340,6 +352,13 @@ struct sg_entry { #endif +#define FSL_CAAM_MP_PUBK_BYTES 64 +#define FSL_CAAM_MP_PRVK_BYTES 32 +#define FSL_CAAM_MP_MES_DGST_BYTES 32 + +#define FSL_CAAM_ORSR_JRa_OFFSET 0x102c +#define FSL_CAAM_MAX_JR_SIZE 4 + /* blob_dek: * Encapsulates the src in a secure blob and stores it dst * @src: reference to the plaintext @@ -349,12 +368,49 @@ struct sg_entry { */ int blob_dek(const u8 *src, u8 *dst, u8 len); +int gen_mppubk(u8 *dst); + +int sign_mppubk(const u8 *m, int data_size, u8 *dgst, u8 *c, u8 *d); + #if defined(CONFIG_ARCH_C29X) int sec_init_idx(uint8_t); #endif int sec_init(void); u8 caam_get_era(void); + +/** + * blob_decap() - Decapsulate the data from a blob + * @key_mod: - Key modifier address + * @src: - Source address (blob) + * @dst: - Destination address (data) + * @len: - Size of decapsulated data + * + * Note: Start and end of the key_mod, src and dst buffers have to be aligned to + * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed. + * + * Returns zero on success, negative on error. + */ +int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len); + +/** + * blob_encap() - Encapsulate the data as a blob + * @key_mod: - Key modifier address + * @src: - Source address (data) + * @dst: - Destination address (blob) + * @len: - Size of data to be encapsulated + * + * Note: Start and end of the key_mod, src and dst buffers have to be aligned to + * the cache line size (ARCH_DMA_MINALIGN) for the CAAM operation to succeed. + * + * Returns zero on success, negative on error. + */ +int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len); + +int derive_blob_kek(u8 *bkek_buf, u8 *key_mod, u32 key_sz); + +int hwrng_generate(u8 *dst, u32 len); + #endif #endif /* __FSL_SEC_H */ diff --git a/include/g_dnl.h b/include/g_dnl.h index 836ee602c8d..050b618f51e 100644 --- a/include/g_dnl.h +++ b/include/g_dnl.h @@ -44,5 +44,6 @@ bool g_dnl_detach(void); void g_dnl_trigger_detach(void); void g_dnl_clear_detach(void); int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget); +int board_usb_gadget_port_auto(void); #endif /* __G_DOWNLOAD_H_ */ diff --git a/include/gis.h b/include/gis.h new file mode 100644 index 00000000000..e156743407a --- /dev/null +++ b/include/gis.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef GIS_H +#define GIS_H + +#define FMT_YUV444 0 +#define FMT_YUYV 1 +#define FMT_UYVY 2 +#define FMT_RGB565 3 +#define FMT_RGB888 4 + +void mxc_enable_gis(void); +void mxc_disable_gis(void); + +#endif diff --git a/include/image.h b/include/image.h index b4b284d52b7..7ad42d71843 100644 --- a/include/image.h +++ b/include/image.h @@ -1522,9 +1522,13 @@ struct cipher_algo *image_get_cipher_algo(const char *full_name); #if !defined(USE_HOSTCC) #if defined(CONFIG_ANDROID_BOOT_IMAGE) struct andr_img_hdr; +struct boot_img_hdr_v3; +struct vendor_boot_img_hdr_v3; int android_image_check_header(const struct andr_img_hdr *hdr); +int android_image_check_header_v3(const struct boot_img_hdr_v3 *hdr, const struct vendor_boot_img_hdr_v3 *vendor_hdr); int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify, ulong *os_data, ulong *os_len); +int android_image_get_kernel_v3(const struct boot_img_hdr_v3 *hdr, const struct vendor_boot_img_hdr_v3 *vendor_hdr); int android_image_get_ramdisk(const struct andr_img_hdr *hdr, ulong *rd_data, ulong *rd_len); int android_image_get_second(const struct andr_img_hdr *hdr, @@ -1539,6 +1543,9 @@ void android_print_contents(const struct andr_img_hdr *hdr); #if !defined(CONFIG_SPL_BUILD) bool android_image_print_dtb_contents(ulong hdr_addr); #endif +bool image_arm64(void *images); +uint32_t kernel_size(void *images); +ulong kernel_relocate_addr(ulong images); #endif /* CONFIG_ANDROID_BOOT_IMAGE */ #endif /* !USE_HOSTCC */ diff --git a/include/imx8_hdmi.h b/include/imx8_hdmi.h new file mode 100644 index 00000000000..eb1253cf51f --- /dev/null +++ b/include/imx8_hdmi.h @@ -0,0 +1,13 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX8_HDMI_H__ +#define __IMX8_HDMI_H__ + +int imx8_hdmi_enable(int encoding, struct video_mode_settings *vms); +void imx8_hdmi_disable(void); + +#endif /* __IMX8_HDMI_H__*/ diff --git a/include/imx8image.h b/include/imx8image.h index 00c614ab6cc..3705460512d 100644 --- a/include/imx8image.h +++ b/include/imx8image.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2018 NXP + * Copyright 2018-2020 NXP * * Peng Fan */ @@ -180,7 +180,8 @@ enum imx8image_fld_types { typedef enum SOC_TYPE { NONE = 0, QX, - QM + QM, + DXL } soc_type_t; typedef enum option_type { diff --git a/include/imx_m4_mu.h b/include/imx_m4_mu.h new file mode 100644 index 00000000000..b53e9e8b231 --- /dev/null +++ b/include/imx_m4_mu.h @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#ifndef __IMX_M4_MU_H__ +#define __IMX_M4_MU_H__ + +enum imx_m4_msg_type { + MU_MSG_REQ = 0x1, /* request message sent from A side */ + MU_MSG_RESP = 0x2, /* response message from B side for request */ + MU_MSG_READY_A = 0x3, /* A side notifies ready */ + MU_MSG_READY_B = 0x4, /* B side notifies ready */ +}; + +union imx_m4_msg { + struct { + u32 seq; + u32 type; + u32 buffer; + u32 size; + } format; + u32 data[4]; +}; +#endif diff --git a/include/imx_sip.h b/include/imx_sip.h index 26dbe0421a0..22a733d8777 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -13,7 +13,19 @@ #define IMX_SIP_BUILDINFO_GET_COMMITHASH 0x00 #define IMX_SIP_SRC 0xC2000005 -#define IMX_SIP_SRC_M4_START 0x00 -#define IMX_SIP_SRC_M4_STARTED 0x01 +#define IMX_SIP_SRC_MCU_START 0x00 +#define IMX_SIP_SRC_MCU_STARTED 0x01 + +#define IMX_SIP_HAB 0xC2000007 +#define IMX_SIP_HAB_AUTHENTICATE 0x00 +#define IMX_SIP_HAB_ENTRY 0x01 +#define IMX_SIP_HAB_EXIT 0x02 +#define IMX_SIP_HAB_REPORT_EVENT 0x03 +#define IMX_SIP_HAB_REPORT_STATUS 0x04 +#define IMX_SIP_HAB_FAILSAFE 0x05 +#define IMX_SIP_HAB_CHECK_TARGET 0x06 + +#define IMX_SIP_FIPS_CONFIG 0xC200000D +#define IMX_SIP_FIPS_CONFIG_SET 0x1 #endif diff --git a/include/imxdpuv1.h b/include/imxdpuv1.h new file mode 100644 index 00000000000..cb12bb8c0f1 --- /dev/null +++ b/include/imxdpuv1.h @@ -0,0 +1,998 @@ +/* + * Copyright (c) 2015-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMXDPUV1_H +#define IMXDPUV1_H + +#include +#include + +/* these will be removed */ +#undef IMXDPUV1_VERSION_0 +#define IMXDPUV1_VERSION_1 + +/* #define DEBUG */ +/* #define ENABLE_IMXDPUV1_TRACE */ +/* #define ENABLE_IMXDPUV1_TRACE_REG */ +/* #define ENABLE_IMXDPUV1_TRACE_IRQ */ +/* #define ENABLE_IMXDPUV1_TRACE_IRQ_READ */ +/* #define ENABLE_IMXDPUV1_TRACE_IRQ_WRITE */ + +#ifdef ENABLE_IMXDPUV1_TRACE +#define IMXDPUV1_TRACE(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) +#else +#define IMXDPUV1_TRACE(fmt, ...) do {} while (0) +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_IRQ +#define IMXDPUV1_TRACE_IRQ(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) +#else +#define IMXDPUV1_TRACE_IRQ(fmt, ...) do {} while (0) +#endif + +#ifdef ENABLE_IMXDPUV1_TRACE_REG +#define IMXDPUV1_TRACE_REG(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) +#else +#define IMXDPUV1_TRACE_REG(fmt, ...) do {} while (0) +#endif + +#define IMXDPUV1_PRINT(fmt, ...) \ +printf((fmt), ##__VA_ARGS__) + +/* #define IMXDPUV1_TCON0_MAP_24BIT_0_23 */ +/* #define IMXDPUV1_TCON1_MAP_24BIT_0_23 */ + +/* todo: this need to come from device tree */ +#define IMXDPUV1_NUM_DI_MAX 2 +#define IMXDPUV1_MAX_NUM 2 +#define IMXDPUV1_NUM_DI 2 +#define IMXDPUV1_NUM_CI 2 +#define IMXDPUV1_REGS_BASE_PHY0 0x56180000 +#define IMXDPUV1_REGS_BASE_PHY1 0x57180000 +#define IMXDPUV1_REGS_BASE_SIZE 0x14000 + +#ifdef IMXDPUV1_VERSION_0 +#define IMXDPUV1_ENABLE_INTSTAT2 +#endif +#define IMXDPUV1_SET_FIELD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) +#define IMXDPUV1_GET_FIELD(field, reg) (((reg)&(field ## _MASK)) >> (field ## _SHIFT)) + +/* + IMXDPU windows, planes, layers, streams + + IMXDPU hardware documentation confuses the meaning of layers and + planes. These are software usages of these terms. + + window - a logical buffer of pixels in a rectangular arrangment. + Image, Integral and video planes suport one window. + Fractional and warp plane support 8 windows. Blending is not + supported between the sub-windows of a fractional or warp plane. + + sub-window - one of the eight logical windows of a fractional or warp + plane. + + channel - the logical DMA configuration for etiher a fetch or store unit + + plane - a plane is a hardware supported feature. There are four types + of display planes: + + video x2 + fractional x2 + intergral x2 + warp + + layer - each of the 7 planes is fed to a layer blender. Full Alpha + blending is supported for all of the planes fed to the layer + blender. + + streams - the layer bleder produces four streams: two normal streams + (0 and 1) and two panic streams (4 and 5). + + In normal mode, streams 0 and 1 are fed to the displays. + In panic mode, streams 4 and 5 are fed to the displays. +*/ + + +/*! + * Enumeration of IMXDPU blend mode flags + */ +typedef enum { + IMXDPUV1_PLANE_CLUT = 1 << 0, /* Color lookup */ + IMXDPUV1_PLANE_DECODE = 1 << 1, /* Decode compressed bufers */ + IMXDPUV1_PLANE_ETERNAL_ALPHA = 1 << 2, /* supports external alpha buffer */ + IMXDPUV1_PLANE_VIDEO_PROC = 1 << 2, /* Gamma, Matrix, Scaler, histogram */ + IMXDPUV1_PLANE_PLANAR = 1 << 3, /* Support Planar pixel buffers*/ + IMXDPUV1_PLANE_WARP = 1 << 4, /* Warping */ + IMXDPUV1_PLANE_MULTIWINDOW = 1 << 5, /* Support multiple buffers per plane */ + IMXDPUV1_PLANE_CAPTURE = 1 << 6, /* Video capture */ +} imxdpuv1_plane_features_t; + +/*! + * Enumeration of IMXDPU layer blend mode flags + */ +typedef enum { + IMXDPUV1_LAYER_NONE = 1 << 0, /* Disable blending */ + IMXDPUV1_LAYER_TRANSPARENCY = 1 << 1, /* Transparency */ + IMXDPUV1_LAYER_GLOBAL_ALPHA = 1 << 2, /* Global alpha mode */ + IMXDPUV1_LAYER_LOCAL_ALPHA = 1 << 3, /* Alpha contained in source buffer */ + IMXDPUV1_LAYER_EXTERN_ALPHA = 1 << 4, /* Alpha is contained in a separate plane */ + IMXDPUV1_LAYER_PRE_MULITPLY = 1 << 5, /* Pre-multiply alpha mode */ +} imxdpuv1_layer_blend_modes_t; + +/*! + * Enumeration of IMXDPU layers + */ +typedef enum { + IMXDPUV1_LAYER_0 = 0, + IMXDPUV1_LAYER_1, + IMXDPUV1_LAYER_2, + IMXDPUV1_LAYER_3, + IMXDPUV1_LAYER_4, +#ifdef IMXDPUV1_VERSION_0 + IMXDPUV1_LAYER_5, + IMXDPUV1_LAYER_6, +#endif + IMXDPUV1_LAYER_MAX, +} imxdpuv1_layer_idx_t; + +/*! + * Enumeration of IMXDPU sub-windows + */ +typedef enum { + IMXDPUV1_SUBWINDOW_NONE = 0, + IMXDPUV1_SUBWINDOW_1, + IMXDPUV1_SUBWINDOW_2, + IMXDPUV1_SUBWINDOW_3, + IMXDPUV1_SUBWINDOW_4, + IMXDPUV1_SUBWINDOW_5, + IMXDPUV1_SUBWINDOW_6, + IMXDPUV1_SUBWINDOW_7, + IMXDPUV1_SUBWINDOW_8, +} imxdpuv1_subwindow_id_t; + +/*! + * Enumeration of IMXDPU display streams + */ +typedef enum { + IMXDPUV1_DISPLAY_STREAM_NONE = (0), + IMXDPUV1_DISPLAY_STREAM_0 = (1U<<0), + IMXDPUV1_DISPLAY_STREAM_1 = (1U<<1), + IMXDPUV1_DISPLAY_STREAM_4 = (1U<<4), + IMXDPUV1_DISPLAY_STREAM_5 = (1U<<5), +} imxdpuv1_display_stream_t; + +/*! + * Enumeration of IMXDPU rotation modes + */ +typedef enum { + /* todo: these need to aligh to imxdpu scan direction */ + IMXDPUV1_ROTATE_NONE = 0, + IMXDPUV1_ROTATE_VERT_FLIP = 1, + IMXDPUV1_ROTATE_HORIZ_FLIP = 2, + IMXDPUV1_ROTATE_180 = 3, + IMXDPUV1_ROTATE_90_RIGHT = 4, + IMXDPUV1_ROTATE_90_RIGHT_VFLIP = 5, + IMXDPUV1_ROTATE_90_RIGHT_HFLIP = 6, + IMXDPUV1_ROTATE_90_LEFT = 7, +} imxdpuv1_rotate_mode_t; + + +/*! + * Enumeration of types of buffers for a logical channel. + */ +typedef enum { + IMXDPUV1_OUTPUT_BUFFER = 0, /*!< Buffer for output from IMXDPU BLIT or capture */ + IMXDPUV1_ALPHA_IN_BUFFER = 1, /*!< Buffer for alpha input to IMXDPU */ + IMXDPUV1_GRAPH_IN_BUFFER = 2, /*!< Buffer for graphics input to IMXDPU */ + IMXDPUV1_VIDEO_IN_BUFFER = 3, /*!< Buffer for video input to IMXDPU */ +} imxdpuv1_buffer_t; + +#ifdef IMXDPUV1_VERSION_0 +/*! + * Enumeration of IMXDPU logical block ids + * NOTE: these match the hardware layout and are not arbitrary + */ +typedef enum { + IMXDPUV1_ID_NONE = 0, + IMXDPUV1_ID_FETCHDECODE9, + IMXDPUV1_ID_FETCHPERSP9, + IMXDPUV1_ID_FETCHECO9, + IMXDPUV1_ID_ROP9, + IMXDPUV1_ID_CLUT9, + IMXDPUV1_ID_MATRIX9, + IMXDPUV1_ID_HSCALER9, + IMXDPUV1_ID_VSCALER9, + IMXDPUV1_ID_FILTER9, + IMXDPUV1_ID_BLITBLEND9, + IMXDPUV1_ID_STORE9, + IMXDPUV1_ID_CONSTFRAME0, + IMXDPUV1_ID_EXTDST0, + IMXDPUV1_ID_CONSTFRAME4, + IMXDPUV1_ID_EXTDST4, + IMXDPUV1_ID_CONSTFRAME1, + IMXDPUV1_ID_EXTDST1, + IMXDPUV1_ID_CONSTFRAME5, + IMXDPUV1_ID_EXTDST5, + IMXDPUV1_ID_EXTSRC4, + IMXDPUV1_ID_STORE4, + IMXDPUV1_ID_EXTSRC5, + IMXDPUV1_ID_STORE5, + IMXDPUV1_ID_FETCHDECODE2, + IMXDPUV1_ID_FETCHDECODE3, + IMXDPUV1_ID_FETCHWARP2, + IMXDPUV1_ID_FETCHECO2, + IMXDPUV1_ID_FETCHDECODE0, + IMXDPUV1_ID_FETCHECO0, + IMXDPUV1_ID_FETCHDECODE1, + IMXDPUV1_ID_FETCHECO1, + IMXDPUV1_ID_FETCHLAYER0, + IMXDPUV1_ID_FETCHLAYER1, + IMXDPUV1_ID_GAMMACOR4, + IMXDPUV1_ID_MATRIX4, + IMXDPUV1_ID_HSCALER4, + IMXDPUV1_ID_VSCALER4, + IMXDPUV1_ID_HISTOGRAM4, + IMXDPUV1_ID_GAMMACOR5, + IMXDPUV1_ID_MATRIX5, + IMXDPUV1_ID_HSCALER5, + IMXDPUV1_ID_VSCALER5, + IMXDPUV1_ID_HISTOGRAM5, + IMXDPUV1_ID_LAYERBLEND0, + IMXDPUV1_ID_LAYERBLEND1, + IMXDPUV1_ID_LAYERBLEND2, + IMXDPUV1_ID_LAYERBLEND3, + IMXDPUV1_ID_LAYERBLEND4, + IMXDPUV1_ID_LAYERBLEND5, + IMXDPUV1_ID_LAYERBLEND6, + IMXDPUV1_ID_EXTSRC0, + IMXDPUV1_ID_EXTSRC1, + IMXDPUV1_ID_DISENGCFG, + IMXDPUV1_ID_FRAMEDUMP0, + IMXDPUV1_ID_FRAMEDUMP1, + IMXDPUV1_ID_FRAMEGEN0, + IMXDPUV1_ID_MATRIX0, + IMXDPUV1_ID_GAMMACOR0, + IMXDPUV1_ID_DITHER0, + IMXDPUV1_ID_TCON0, + IMXDPUV1_ID_SIG0, + IMXDPUV1_ID_FRAMEGEN1, + IMXDPUV1_ID_MATRIX1, + IMXDPUV1_ID_GAMMACOR1, + IMXDPUV1_ID_DITHER1, + IMXDPUV1_ID_TCON1, + IMXDPUV1_ID_SIG1, + IMXDPUV1_ID_CAPENGCFG, + IMXDPUV1_ID_FRAMECAP4, + IMXDPUV1_ID_FRAMECAP5, + IMXDPUV1_ID_ANALYSER4, + IMXDPUV1_ID_ANALYSER5, + /* the following are added arbitrarily */ + IMXDPUV1_ID_DPUXPC, + +} imxdpuv1_id_t; +#else +/*! + * Enumeration of IMXDPU logical block ids + * NOTE: these match the hardware layout and are not arbitrary + */ +typedef enum { + IMXDPUV1_ID_NONE = 0, + IMXDPUV1_ID_FETCHDECODE9, + IMXDPUV1_ID_FETCHWARP9, + IMXDPUV1_ID_FETCHECO9, + IMXDPUV1_ID_ROP9, + IMXDPUV1_ID_CLUT9, + IMXDPUV1_ID_MATRIX9, + IMXDPUV1_ID_HSCALER9, + IMXDPUV1_ID_VSCALER9, + IMXDPUV1_ID_FILTER9, + IMXDPUV1_ID_BLITBLEND9, + IMXDPUV1_ID_STORE9, + IMXDPUV1_ID_CONSTFRAME0, + IMXDPUV1_ID_EXTDST0, + IMXDPUV1_ID_CONSTFRAME4, + IMXDPUV1_ID_EXTDST4, + IMXDPUV1_ID_CONSTFRAME1, + IMXDPUV1_ID_EXTDST1, + IMXDPUV1_ID_CONSTFRAME5, + IMXDPUV1_ID_EXTDST5, + IMXDPUV1_ID_FETCHWARP2, + IMXDPUV1_ID_FETCHECO2, + IMXDPUV1_ID_FETCHDECODE0, + IMXDPUV1_ID_FETCHECO0, + IMXDPUV1_ID_FETCHDECODE1, + IMXDPUV1_ID_FETCHECO1, + IMXDPUV1_ID_FETCHLAYER0, + IMXDPUV1_ID_MATRIX4, + IMXDPUV1_ID_HSCALER4, + IMXDPUV1_ID_VSCALER4, + IMXDPUV1_ID_MATRIX5, + IMXDPUV1_ID_HSCALER5, + IMXDPUV1_ID_VSCALER5, + IMXDPUV1_ID_LAYERBLEND0, + IMXDPUV1_ID_LAYERBLEND1, + IMXDPUV1_ID_LAYERBLEND2, + IMXDPUV1_ID_LAYERBLEND3, + IMXDPUV1_ID_DISENGCFG, + IMXDPUV1_ID_FRAMEGEN0, + IMXDPUV1_ID_MATRIX0, + IMXDPUV1_ID_GAMMACOR0, + IMXDPUV1_ID_DITHER0, + IMXDPUV1_ID_TCON0, + IMXDPUV1_ID_SIG0, + IMXDPUV1_ID_FRAMEGEN1, + IMXDPUV1_ID_MATRIX1, + IMXDPUV1_ID_GAMMACOR1, + IMXDPUV1_ID_DITHER1, + IMXDPUV1_ID_TCON1, + IMXDPUV1_ID_SIG1, + IMXDPUV1_ID_DPUXPC, +} imxdpuv1_id_t; +#endif + +#ifdef IMXDPUV1_VERSION_0 +typedef enum { + IMXDPUV1_SHDLD_CONSTFRAME0 = 1U << 4, + IMXDPUV1_SHDLD_CONSTFRAME4 = 1U << 5, + IMXDPUV1_SHDLD_CONSTFRAME1 = 1U << 6, + IMXDPUV1_SHDLD_CONSTFRAME5 = 1U << 7, + IMXDPUV1_SHDLD_EXTSRC4 = 1U << 8, + IMXDPUV1_SHDLD_EXTSRC5 = 1U << 9, + IMXDPUV1_SHDLD_FETCHDECODE2 = 1U << 10, + IMXDPUV1_SHDLD_FETCHDECODE3 = 1U << 11, + IMXDPUV1_SHDLD_FETCHWARP2 = 1U << 12, + IMXDPUV1_SHDLD_FETCHECO2 = 1U << 13, + IMXDPUV1_SHDLD_FETCHDECODE0 = 1U << 14, + IMXDPUV1_SHDLD_FETCHECO0 = 1U << 15, + IMXDPUV1_SHDLD_FETCHDECODE1 = 1U << 16, + IMXDPUV1_SHDLD_FETCHECO1 = 1U << 17, + IMXDPUV1_SHDLD_FETCHLAYER0 = 1U << 18, + IMXDPUV1_SHDLD_FETCHLAYER1 = 1U << 19, + IMXDPUV1_SHDLD_EXTSRC0 = 1U << 20, + IMXDPUV1_SHDLD_EXTSRC1 = 1U << 21, +} imxdpuv1_shadow_load_req_id_t; +#else +typedef enum { + IMXDPUV1_SHDLD_CONSTFRAME0 = 1U << 4, + IMXDPUV1_SHDLD_CONSTFRAME4 = 1U << 5, + IMXDPUV1_SHDLD_CONSTFRAME1 = 1U << 6, + IMXDPUV1_SHDLD_CONSTFRAME5 = 1U << 7, + IMXDPUV1_SHDLD_FETCHWARP2 = 1U << 8, + IMXDPUV1_SHDLD_FETCHECO2 = 1U << 9, + IMXDPUV1_SHDLD_FETCHDECODE0 = 1U << 10, + IMXDPUV1_SHDLD_FETCHECO0 = 1U << 11, + IMXDPUV1_SHDLD_FETCHDECODE1 = 1U << 12, + IMXDPUV1_SHDLD_FETCHECO1 = 1U << 13, + IMXDPUV1_SHDLD_FETCHLAYER0 = 1U << 14, + + IMXDPUV1_SHDLD_EXTSRC4 = 0, + IMXDPUV1_SHDLD_EXTSRC5 = 0, + IMXDPUV1_SHDLD_FETCHDECODE2 = 0, + IMXDPUV1_SHDLD_FETCHDECODE3 = 0, + IMXDPUV1_SHDLD_FETCHLAYER1 = 0, + IMXDPUV1_SHDLD_EXTSRC0 = 0, + IMXDPUV1_SHDLD_EXTSRC1 = 0, + +} imxdpuv1_shadow_load_req_id_t; + + +#endif +typedef struct { + imxdpuv1_id_t primary; + imxdpuv1_id_t secondary; + imxdpuv1_display_stream_t stream; + bool enable; +} imxdpuv1_layer_t; + +typedef enum { + /* Fetch Channels */ + IMXDPUV1_CHAN_IDX_IN_FIRST = 0, + IMXDPUV1_CHAN_IDX_00 = 0, /* IMXDPUV1_ID_SRC_FETCHDECODE2 */ + IMXDPUV1_CHAN_IDX_01, /* IMXDPUV1_ID_SRC_FETCHDECODE0 */ + IMXDPUV1_CHAN_IDX_02, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_03, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_04, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_05, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_06, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_07, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_08, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_09, /* IMXDPUV1_ID_SRC_FETCHLAYER0 */ + IMXDPUV1_CHAN_IDX_10, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_11, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_12, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_13, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_14, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_15, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_16, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_17, /* IMXDPUV1_ID_SRC_FETCHWARP2 */ + IMXDPUV1_CHAN_IDX_18, /* IMXDPUV1_ID_SRC_FETCHDECODE3 */ + IMXDPUV1_CHAN_IDX_19, /* IMXDPUV1_ID_SRC_FETCHDECODE1 */ + IMXDPUV1_CHAN_IDX_20, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_21, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_22, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_23, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_24, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_25, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_26, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_27, /* IMXDPUV1_ID_SRC_FETCHLAYER1 */ + IMXDPUV1_CHAN_IDX_28, /* IMXDPUV1_ID_SRC_ECO0 */ + IMXDPUV1_CHAN_IDX_29, /* IMXDPUV1_ID_SRC_ECO1 */ + IMXDPUV1_CHAN_IDX_30, /* IMXDPUV1_ID_SRC_ECO2 */ + IMXDPUV1_CHAN_IDX_IN_MAX, /* Last fetch channel + 1 */ + + /* Store Channels */ + IMXDPUV1_CHAN_IDX_OUT_FIRST = 32, + IMXDPUV1_CHAN_IDX_32 = 32,/* IMXDPUV1_ID_DST_STORE4 */ + IMXDPUV1_CHAN_IDX_33, /* IMXDPUV1_ID_DST_STORE5 */ + IMXDPUV1_CHAN_IDX_OUT_MAX,/* Last fetch channel + 1 */ + IMXDPUV1_CHAN_IDX_MAX = IMXDPUV1_CHAN_IDX_OUT_MAX, +} imxdpuv1_chan_idx_t; + +typedef enum { + IMXDPUV1_SUB_NONE = 0, + IMXDPUV1_SUB_1 = 1U << 0, /* IMXDPUV1_ID_FETCHLAYER0, layer 1 */ + IMXDPUV1_SUB_2 = 1U << 1, /* IMXDPUV1_ID_FETCHLAYER0, layer 2 */ + IMXDPUV1_SUB_3 = 1U << 2, /* IMXDPUV1_ID_FETCHLAYER0, layer 3 */ + IMXDPUV1_SUB_4 = 1U << 3, /* IMXDPUV1_ID_FETCHLAYER0, layer 4 */ + IMXDPUV1_SUB_5 = 1U << 4, /* IMXDPUV1_ID_FETCHLAYER0, layer 5 */ + IMXDPUV1_SUB_6 = 1U << 5, /* IMXDPUV1_ID_FETCHLAYER0, layer 6 */ + IMXDPUV1_SUB_7 = 1U << 6, /* IMXDPUV1_ID_FETCHLAYER0, layer 7 */ + IMXDPUV1_SUB_8 = 1U << 7, /* IMXDPUV1_ID_FETCHLAYER0, layer 8 */ +} imxdpuv1_chan_sub_idx_t; + +/* IMXDPU Channel + * Consistist of four fields + * src - block id of source or destination + * sec - block id of secondary source for fetcheco + * sub - sub index of block for fetchlayer or fetchwarp + * idx - logical channel index + * + */ +#define make_channel(__blk_id, __eco_id, __sub, __idx) \ +(((__u32)(__idx)<<0)|((__u32)(__eco_id)<<8)|((__u32)(__sub)<<16)|((__u32)(__blk_id)<<24)) + +#define get_channel_blk(chan) (((__u32)(chan) >> 24) & 0xff) +#define get_channel_sub(chan) (((__u32)(chan) >> 16) & 0xff) +#define get_eco_idx(chan) (((__u32)(chan) >> 8) & 0xff) +#define get_channel_idx(chan) (((__u32)(chan) >> 0) & 0xff) +#define IMXDPUV1_SUBCHAN_LAYER_OFFSET 0x28 + +typedef enum { +#ifdef IMXDPUV1_VERSION_0 + /* Fetch Channels */ + IMXDPUV1_CHAN_00 = make_channel(IMXDPUV1_ID_FETCHDECODE2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 0), + IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0, 28, IMXDPUV1_SUB_NONE, 1), + IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2), + IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3), + IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4), + IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5), + IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6), + IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7), + IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8), + IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9), + IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_1, 10), + IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_2, 11), + IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_3, 12), + IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_4, 13), + IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_5, 14), + IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_6, 15), + IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_7, 16), + IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_8, 17), + IMXDPUV1_CHAN_18 = make_channel(IMXDPUV1_ID_FETCHDECODE3, 30, IMXDPUV1_SUB_NONE, 18), + IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1, 29, IMXDPUV1_SUB_NONE, 19), + IMXDPUV1_CHAN_20 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 20), + IMXDPUV1_CHAN_21 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 21), + IMXDPUV1_CHAN_22 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 22), + IMXDPUV1_CHAN_23 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 23), + IMXDPUV1_CHAN_24 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 24), + IMXDPUV1_CHAN_25 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 25), + IMXDPUV1_CHAN_26 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 26), + IMXDPUV1_CHAN_27 = make_channel(IMXDPUV1_ID_FETCHLAYER1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 27), + IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28), + IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29), + IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30), + /* Store Channels */ + IMXDPUV1_CHAN_32 = make_channel(IMXDPUV1_ID_STORE4, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 32), + IMXDPUV1_CHAN_33 = make_channel(IMXDPUV1_ID_STORE5, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 33), +#else + /* Fetch Channels */ + IMXDPUV1_CHAN_00 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_01 = make_channel(IMXDPUV1_ID_FETCHDECODE0, 28, IMXDPUV1_SUB_NONE, 1), + IMXDPUV1_CHAN_02 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_1, 2), + IMXDPUV1_CHAN_03 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_2, 3), + IMXDPUV1_CHAN_04 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_3, 4), + IMXDPUV1_CHAN_05 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_4, 5), + IMXDPUV1_CHAN_06 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_5, 6), + IMXDPUV1_CHAN_07 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_6, 7), + IMXDPUV1_CHAN_08 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_7, 8), + IMXDPUV1_CHAN_09 = make_channel(IMXDPUV1_ID_FETCHLAYER0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_8, 9), + IMXDPUV1_CHAN_10 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_1, 10), + IMXDPUV1_CHAN_11 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_2, 11), + IMXDPUV1_CHAN_12 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_3, 12), + IMXDPUV1_CHAN_13 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_4, 13), + IMXDPUV1_CHAN_14 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_5, 14), + IMXDPUV1_CHAN_15 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_6, 15), + IMXDPUV1_CHAN_16 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_7, 16), + IMXDPUV1_CHAN_17 = make_channel(IMXDPUV1_ID_FETCHWARP2, 30, IMXDPUV1_SUB_8, 17), + IMXDPUV1_CHAN_18 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_19 = make_channel(IMXDPUV1_ID_FETCHDECODE1, 29, IMXDPUV1_SUB_NONE, 19), + IMXDPUV1_CHAN_20 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_21 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_22 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_23 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_24 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_25 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_26 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_27 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_28 = make_channel(IMXDPUV1_ID_FETCHECO0, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 28), + IMXDPUV1_CHAN_29 = make_channel(IMXDPUV1_ID_FETCHECO1, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 29), + IMXDPUV1_CHAN_30 = make_channel(IMXDPUV1_ID_FETCHECO2, IMXDPUV1_ID_NONE, IMXDPUV1_SUB_NONE, 30), + /* Store Channels */ + IMXDPUV1_CHAN_32 = make_channel(0, 0, 0, 0), + IMXDPUV1_CHAN_33 = make_channel(0, 0, 0, 0), +#endif +} imxdpuv1_chan_t; + +/* Aliases for Channels */ +#define IMXDPUV1_CHAN_VIDEO_0 IMXDPUV1_CHAN_01 +#define IMXDPUV1_CHAN_VIDEO_1 IMXDPUV1_CHAN_19 + +#define IMXDPUV1_CHAN_INTEGRAL_0 IMXDPUV1_CHAN_00 +#define IMXDPUV1_CHAN_INTEGRAL_1 IMXDPUV1_CHAN_18 + +#define IMXDPUV1_CHAN_FRACTIONAL_0_1 IMXDPUV1_CHAN_02 +#define IMXDPUV1_CHAN_FRACTIONAL_0_2 IMXDPUV1_CHAN_03 +#define IMXDPUV1_CHAN_FRACTIONAL_0_3 IMXDPUV1_CHAN_04 +#define IMXDPUV1_CHAN_FRACTIONAL_0_4 IMXDPUV1_CHAN_05 +#define IMXDPUV1_CHAN_FRACTIONAL_0_5 IMXDPUV1_CHAN_06 +#define IMXDPUV1_CHAN_FRACTIONAL_0_6 IMXDPUV1_CHAN_07 +#define IMXDPUV1_CHAN_FRACTIONAL_0_7 IMXDPUV1_CHAN_08 +#define IMXDPUV1_CHAN_FRACTIONAL_0_8 IMXDPUV1_CHAN_09 + +#define IMXDPUV1_CHAN_FRACTIONAL_1_1 IMXDPUV1_CHAN_20 +#define IMXDPUV1_CHAN_FRACTIONAL_1_2 IMXDPUV1_CHAN_21 +#define IMXDPUV1_CHAN_FRACTIONAL_1_3 IMXDPUV1_CHAN_22 +#define IMXDPUV1_CHAN_FRACTIONAL_1_4 IMXDPUV1_CHAN_23 +#define IMXDPUV1_CHAN_FRACTIONAL_1_5 IMXDPUV1_CHAN_24 +#define IMXDPUV1_CHAN_FRACTIONAL_1_6 IMXDPUV1_CHAN_25 +#define IMXDPUV1_CHAN_FRACTIONAL_1_7 IMXDPUV1_CHAN_26 +#define IMXDPUV1_CHAN_FRACTIONAL_1_8 IMXDPUV1_CHAN_27 + +#define IMXDPUV1_CHAN_WARP_2_1 IMXDPUV1_CHAN_10 +#define IMXDPUV1_CHAN_WARP_2_2 IMXDPUV1_CHAN_11 +#define IMXDPUV1_CHAN_WARP_2_3 IMXDPUV1_CHAN_12 +#define IMXDPUV1_CHAN_WARP_2_4 IMXDPUV1_CHAN_13 +#define IMXDPUV1_CHAN_WARP_2_5 IMXDPUV1_CHAN_14 +#define IMXDPUV1_CHAN_WARP_2_6 IMXDPUV1_CHAN_15 +#define IMXDPUV1_CHAN_WARP_2_7 IMXDPUV1_CHAN_16 +#define IMXDPUV1_CHAN_WARP_2_8 IMXDPUV1_CHAN_17 + +#define IMXDPUV1_CHAN_CAPTURE_0 IMXDPUV1_CHAN_32 +#define IMXDPUV1_CHAN_CAPTURE_1 IMXDPUV1_CHAN_33 + + +/* IMXDPU Pixel format definitions */ +/* Four-character-code (FOURCC) */ +#ifdef fourcc +#warning "fourcc is already defined ... redeifining it here!" +#undef fourcc +#endif +#define fourcc(a, b, c, d)\ + (((__u32)(a)<<0)|((__u32)(b)<<8)|((__u32)(c)<<16)|((__u32)(d)<<24)) + + +/*! @} */ +/*! @name Generic Formats */ +/*! @{ */ +#define IMXDPUV1_PIX_FMT_GENERIC fourcc('D', 'P', 'U', '0') /*!< IPU Generic Data */ +#define IMXDPUV1_PIX_FMT_GENERIC_32 fourcc('D', 'P', 'U', '1') /*!< IPU Generic Data */ +#define IMXDPUV1_PIX_FMT_GENERIC_16 fourcc('D', 'P', 'U', '2') /*!< IPU Generic Data */ + +/*! @} */ +/*! @name RGB Formats */ +/*! @{ */ +#define IMXDPUV1_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*!< 8 RGB-3-3-2 */ +#define IMXDPUV1_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*!< 16 RGB-5-5-5 */ +#define IMXDPUV1_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*!< 16 RGB-5-6-5 */ +#define IMXDPUV1_PIX_FMT_BGRA4444 fourcc('4', '4', '4', '4') /*!< 16 RGBA-4-4-4-4 */ +#define IMXDPUV1_PIX_FMT_BGRA5551 fourcc('5', '5', '5', '1') /*!< 16 RGBA-5-5-5-1 */ +#define IMXDPUV1_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*!< 18 RGB-6-6-6 */ +#define IMXDPUV1_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*!< 18 BGR-6-6-6 */ +#define IMXDPUV1_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*!< 24 BGR-8-8-8 */ +#define IMXDPUV1_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*!< 24 RGB-8-8-8 */ +#define IMXDPUV1_PIX_FMT_GBR24 fourcc('G', 'B', 'R', '3') /*!< 24 GBR-8-8-8 */ +#define IMXDPUV1_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*!< 32 BGR-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_BGRA32 fourcc('B', 'G', 'R', 'A') /*!< 32 BGR-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_RGB32 fourcc('R', 'G', 'B', '4') /*!< 32 RGB-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_RGBA32 fourcc('R', 'G', 'B', 'A') /*!< 32 RGB-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_ABGR32 fourcc('A', 'B', 'G', 'R') /*!< 32 ABGR-8-8-8-8 */ +#define IMXDPUV1_PIX_FMT_ARGB32 fourcc('A', 'R', 'G', 'B') /*!< 32 ARGB-8-8-8-8 */ + +/*! @} */ +/*! @name YUV Interleaved Formats */ +/*! @{ */ +#define IMXDPUV1_PIX_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') /*!< 16 YUV 4:2:2 */ +#define IMXDPUV1_PIX_FMT_UYVY fourcc('U', 'Y', 'V', 'Y') /*!< 16 YUV 4:2:2 */ +#define IMXDPUV1_PIX_FMT_YVYU fourcc('Y', 'V', 'Y', 'U') /*!< 16 YVYU 4:2:2 */ +#define IMXDPUV1_PIX_FMT_VYUY fourcc('V', 'Y', 'U', 'Y') /*!< 16 VYYU 4:2:2 */ +#define IMXDPUV1_PIX_FMT_Y41P fourcc('Y', '4', '1', 'P') /*!< 12 YUV 4:1:1 */ +#define IMXDPUV1_PIX_FMT_YUV444 fourcc('Y', '4', '4', '4') /*!< 24 YUV 4:4:4 */ +#define IMXDPUV1_PIX_FMT_VYU444 fourcc('V', '4', '4', '4') /*!< 24 VYU 4:4:4 */ +#define IMXDPUV1_PIX_FMT_AYUV fourcc('A', 'Y', 'U', 'V') /*!< 32 AYUV 4:4:4:4 */ + +/* two planes -- one Y, one Cb + Cr interleaved */ +#define IMXDPUV1_PIX_FMT_NV12 fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */ +#define IMXDPUV1_PIX_FMT_NV16 fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */ + +#define IMXDPUV1_CAP_FMT_RGB24 fourcc('R', 'G', 'B', '3') +#define IMXDPUV1_CAP_FMT_BT656 fourcc('B', '6', '5', '6') +#define IMXDPUV1_CAP_FMT_YUYV fourcc('Y', 'U', 'Y', 'V') + +struct imxdpuv1_soc; +/*! + * Definition of IMXDPU rectangle structure + */ +typedef struct { + int16_t top; /* y coordinate of top/left pixel */ + int16_t left; /* x coordinate top/left pixel */ + int16_t width; + int16_t height; +} imxdpuv1_rect_t; + + +/*! + * Union of initialization parameters for a logical channel. + */ +typedef union { + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; /* capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + } common; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t capture_id; /* disp_id/capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + uint32_t h_scale_factor; /* downscaling out/in */ + uint32_t h_phase; + uint32_t v_scale_factor; /* downscaling out/in */ + uint32_t v_phase[2][2]; + bool use_video_proc; + bool interlaced; + } store; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + uint32_t h_scale_factor; /* downscaling out/in */ + uint32_t h_phase; + uint32_t v_scale_factor; /* downscaling out/in */ + uint32_t v_phase[2][2]; + bool use_video_proc; + bool interlaced; + } fetch_decode; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; /* capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + } fetch_layer; + struct { + imxdpuv1_chan_t chan; + uint32_t src_pixel_fmt; + uint16_t src_width; + uint16_t src_height; + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + uint16_t stride; + uint32_t dest_pixel_fmt; + uint8_t blend_mode; + uint8_t blend_layer; + uint8_t disp_id; /* capture id */ + int16_t dest_top; + int16_t dest_left; + uint16_t dest_width; + uint16_t dest_height; + uint32_t const_color; + bool use_global_alpha; + bool use_local_alpha; + } fetch_warp; +} imxdpuv1_channel_params_t; + +/*! + * Enumeration of IMXDPU video mode flags + */ +enum imxdpuv1_mode_flags { + /* 1 is active high 0 is active low */ + IMXDPUV1_MODE_FLAGS_HSYNC_POL = 1 << 0, + IMXDPUV1_MODE_FLAGS_VSYNC_POL = 1 << 1, + IMXDPUV1_MODE_FLAGS_DE_POL = 1 << 2, + + /* drive data on positive .edge */ + IMXDPUV1_MODE_FLAGS_CLK_POL = 1 << 3, + + IMXDPUV1_MODE_FLAGS_INTERLACED = 1 << 4 , + + /* Left/Right Synchronous display mode, both display pipe are + combined to make one display. All mode timings are divided by + two for each half screen. + Note: This may not be needed we may force this for any width + over ~2048 + */ + IMXDPUV1_MODE_FLAGS_LRSYNC = 1 << 8, + + /* Split mode each pipe is split into two displays */ + IMXDPUV1_MODE_FLAGS_SPLIT = 1 << 9, + + IMXDPUV1_MODE_FLAGS_32BIT = 1 << 16, + IMXDPUV1_MODE_FLAGS_BT656_10BIT = 1 << 17, + IMXDPUV1_MODE_FLAGS_BT656_8BIT = 1 << 18, +}; + +struct imxdpuv1_videomode { + char name[64]; /* may not be needed */ + + uint32_t pixelclock; /* Hz */ + + /* htotal (pixels) = hlen + hfp + hsync + hbp */ + uint32_t hlen; + uint32_t hfp; + uint32_t hbp; + uint32_t hsync; + + /* field0 - vtotal (lines) = vlen + vfp + vsync + vbp */ + uint32_t vlen; + uint32_t vfp; + uint32_t vbp; + uint32_t vsync; + + /* field1 */ + uint32_t vlen1; + uint32_t vfp1; + uint32_t vbp1; + uint32_t vsync1; + + uint32_t flags; + uint32_t format; + uint32_t dest_format; /*buffer format for capture*/ + int16_t clip_top; + int16_t clip_left; + uint16_t clip_width; + uint16_t clip_height; + +}; + +#define IMXDPUV1_ENABLE 1 +#define IMXDPUV1_DISABLE 0 + +#define IMXDPUV1_TRUE 1 +#define IMXDPUV1_FALSE 0 +#define IMXDPUV1_OFFSET_INVALID 0x10000000 /* this should force an access error */ +#define IMXDPUV1_CHANNEL_INVALID 0x0 /* this should force an access error */ + +#define IMXDPUV1_MIN(_X, _Y) ((_X) < (_Y) ? (_X) : (_Y)) + +/* Native color type */ +#define IMXDPUV1_COLOR_CONSTALPHA_MASK 0xFFU +#define IMXDPUV1_COLOR_CONSTALPHA_SHIFT 0U +#define IMXDPUV1_COLOR_CONSTBLUE_MASK 0xFF00U +#define IMXDPUV1_COLOR_CONSTBLUE_SHIFT 8U +#define IMXDPUV1_COLOR_CONSTGREEN_MASK 0xFF0000U +#define IMXDPUV1_COLOR_CONSTGREEN_SHIFT 16U +#define IMXDPUV1_COLOR_CONSTRED_MASK 0xFF000000U +#define IMXDPUV1_COLOR_CONSTRED_SHIFT 24U + +#define IMXDPUV1_IRQF_NONE 0x0 +#define IMXDPUV1_IRQF_ONESHOT 0x1 +#define IMXDPUV1_INTERRUPT_MAX (66 + 1) /* IMXDPUV1_FRAMECAP5_SYNC_OFF_IRQ + (66) is last interrupt */ + +int imxdpuv1_enable_irq(int8_t imxdpuv1_id, uint32_t irq); +int imxdpuv1_disable_irq(int8_t imxdpuv1_id, uint32_t irq); +int imxdpuv1_clear_all_irqs(int8_t imxdpuv1_id); +int imxdpuv1_clear_irq(int8_t imxdpuv1_id, uint32_t irq); +int imxdpuv1_init_irqs(int8_t imxdpuv1_id); +int imxdpuv1_request_irq(int8_t imxdpuv1_id, + uint32_t irq, + int(*handler) (int, void *), + uint32_t irq_flags, + const char *devname, void *data) ; +int imxdpuv1_free_irq(int8_t imxdpuv1_id, uint32_t irq, void *data); +int imxdpuv1_uninit_interrupts(int8_t imxdpuv1_id); +int imxdpuv1_handle_irq(int32_t imxdpuv1_id); +struct imxdpuv1_soc *imxdpuv1_get_soc(int8_t imxdpuv1_id); +int imxdpuv1_init(int8_t imxdpuv1_id); +int imxdpuv1_init_sync_panel(int8_t imxdpuv1_id, int8_t disp, + uint32_t pixel_fmt, + struct imxdpuv1_videomode mode); +int imxdpuv1_uninit_sync_panel(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_reset_disp_panel(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_disp_init(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_disp_setup_frame_gen( + int8_t imxdpuv1_id, + int8_t disp, + const struct imxdpuv1_videomode *mode, + uint16_t cc_red, /* 10 bits */ + uint16_t cc_green, /* 10 bits */ + uint16_t cc_blue, /* 10 bits */ + uint8_t cc_alpha, + bool test_mode_enable); +int imxdpuv1_disp_enable_frame_gen(int8_t imxdpuv1_id, + int8_t disp, + bool enable); +int imxdpuv1_disp_setup_constframe(int8_t imxdpuv1_id, + int8_t disp, + uint8_t bg_red, + uint8_t bg_green, + uint8_t bg_blue, + uint8_t bg_alpha); +int imxdpuv1_disp_setup_layer(int8_t imxdpuv1_id, + const imxdpuv1_layer_t *layer, + imxdpuv1_layer_idx_t layer_idx, + bool is_top_layer); +void imxdpuv1_disp_dump_mode(const struct imxdpuv1_videomode *mode); +int imxdpuv1_bytes_per_pixel(uint32_t fmt); +int imxdpuv1_init_channel_buffer(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t stride, + imxdpuv1_rotate_mode_t rot_mode, + dma_addr_t phyaddr_0, + uint32_t u_offset, + uint32_t v_offset); +int32_t imxdpuv1_update_channel_buffer(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + dma_addr_t phyaddr_0); +int imxdpuv1_init_channel(int8_t imxdpuv1_id, + imxdpuv1_channel_params_t *params); +int imxdpuv1_disp_set_layer_global_alpha(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + uint8_t alpha); +int imxdpuv1_disp_set_layer_position(int8_t imxdpuv1_id, + imxdpuv1_layer_idx_t layer_idx, + int16_t x, int16_t y); +int imxdpuv1_disp_set_chan_position(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + int16_t x, int16_t y); +int imxdpuv1_disp_update_fgen_status(int8_t imxdpuv1_id, int8_t disp); +int imxdpuv1_disp_show_fgen_status(int8_t imxdpuv1_id); +void imxdpuv1_dump_int_stat(int8_t imxdpuv1_id); +void imxdpuv1_dump_layerblend(int8_t imxdpuv1_id); +int imxdpuv1_disp_force_shadow_load(int8_t imxdpuv1_id, + int8_t disp, + uint64_t mask); +int imxdpuv1_disp_set_chan_crop(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height); +void imxdpuv1_dump_pixencfg_status(int8_t imxdpuv1_id); +int imxdpuv1_dump_channel(int8_t imxdpuv1_id, imxdpuv1_chan_t chan); +uint32_t imxdpuv1_get_planes(uint32_t fmt); + +int imxdpuv1_disp_setup_channel(int8_t imxdpuv1_id, + imxdpuv1_chan_t chan, + uint32_t src_pixel_fmt, + uint16_t src_width, + uint16_t src_height, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height, + uint16_t stride, + uint8_t disp_id, + int16_t dest_top, + int16_t dest_left, + uint16_t dest_width, + uint16_t dest_height, + uint32_t const_color, + bool use_global_alpha, + bool use_local_alpha, + unsigned int disp_addr); +int imxdpuv1_disp_check_shadow_loads(int8_t imxdpuv1_id, int8_t disp); + +int imxdpuv1_cap_setup_frame( + int8_t imxdpuv1_id, + int8_t src_id, + int8_t dest_id, + int8_t sync_count, + const struct imxdpuv1_videomode *cap_mode); +int imxdpuv1_cap_setup_crop( + int8_t imxdpuv1_id, + int8_t src_id, + int16_t clip_top, + int16_t clip_left, + uint16_t clip_width, + uint16_t clip_height); + +int imxdpuv1_cap_enable(int8_t imxdpuv1_id, int8_t cap, bool enable); +int imxdpuv1_cap_request_shadow_load(int8_t imxdpuv1_id, int8_t dest_id, uint32_t mask); + +/* FIXME: add api if needed */ +static inline int32_t imxdpuv1_csi_enable_mclk_if(int8_t imxdpuv1_id, int src, uint32_t cap, + bool flag, bool wait) +{ + printf("%s(): %s:%d stubbed feature\n", __func__, __FILE__, __LINE__); + return 0; +} +#endif /* IMXDPUV1_H */ diff --git a/include/imxdpuv1_events.h b/include/imxdpuv1_events.h new file mode 100644 index 00000000000..7f8ed8157d0 --- /dev/null +++ b/include/imxdpuv1_events.h @@ -0,0 +1,353 @@ +/* + * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef IMXDPUV1_EVENTS_H +#define IMXDPUV1_EVENTS_H + +/* Shadow load (Blit Engine) */ +#define IMXDPUV1_STORE9_SHDLOAD_IRQ 0U +#define IMXDPUV1_STORE9_SHDLOAD_CMD 0U + +/* Frame complete (Blit Engine) */ +#define IMXDPUV1_STORE9_FRAMECOMPLETE_IRQ 1U +#define IMXDPUV1_STORE9_FRAMECOMPLETE_CMD 1U + +/* Sequence complete (Blit Engine) */ +#define IMXDPUV1_STORE9_SEQCOMPLETE_IRQ 2U +#define IMXDPUV1_STORE9_SEQCOMPLETE_CMD 2U + +/* Shadow load (Display Controller Content Stream 0) */ +#define IMXDPUV1_EXTDST0_SHDLOAD_IRQ 3U +#define IMXDPUV1_EXTDST0_SHDLOAD_CMD 3U + +/* Frame complete (Display Controller Content Stream 0) */ +#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_IRQ 4U +#define IMXDPUV1_EXTDST0_FRAMECOMPLETE_CMD 4U + +/* Sequence complete (Display Controller Content Stream 0) */ +#define IMXDPUV1_EXTDST0_SEQCOMPLETE_IRQ 5U +#define IMXDPUV1_EXTDST0_SEQCOMPLETE_CMD 5U + +/* Shadow load (Display Controller Safety Stream 0) */ +#define IMXDPUV1_EXTDST4_SHDLOAD_IRQ 6U +#define IMXDPUV1_EXTDST4_SHDLOAD_CMD 6U + +/* Frame complete (Display Controller Safety Stream 0) */ +#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_IRQ 7U +#define IMXDPUV1_EXTDST4_FRAMECOMPLETE_CMD 7U + +/* Sequence complete (Display Controller Safety Stream 0) */ +#define IMXDPUV1_EXTDST4_SEQCOMPLETE_IRQ 8U +#define IMXDPUV1_EXTDST4_SEQCOMPLETE_CMD 8U + +/* Shadow load (Display Controller Content Stream 1) */ +#define IMXDPUV1_EXTDST1_SHDLOAD_IRQ 9U +#define IMXDPUV1_EXTDST1_SHDLOAD_CMD 9U + +/* Frame complete (Display Controller Content Stream 1) */ +#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_IRQ 10U +#define IMXDPUV1_EXTDST1_FRAMECOMPLETE_CMD 10U + +/* Sequence complete (Display Controller Content Stream 1) */ +#define IMXDPUV1_EXTDST1_SEQCOMPLETE_IRQ 11U +#define IMXDPUV1_EXTDST1_SEQCOMPLETE_CMD 11U + +/* Shadow load (Display Controller Safety Stream 1) */ +#define IMXDPUV1_EXTDST5_SHDLOAD_IRQ 12U +#define IMXDPUV1_EXTDST5_SHDLOAD_CMD 12U + +/* Frame complete (Display Controller Safety Stream 1) */ +#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_IRQ 13U +#define IMXDPUV1_EXTDST5_FRAMECOMPLETE_CMD 13U + +/* Sequence complete (Display Controller Safety Stream 1) */ +#define IMXDPUV1_EXTDST5_SEQCOMPLETE_IRQ 14U +#define IMXDPUV1_EXTDST5_SEQCOMPLETE_CMD 14U + +/* Shadow load (Display Controller Display Stream 0) */ +#define IMXDPUV1_DISENGCFG_SHDLOAD0_IRQ 15U +#define IMXDPUV1_DISENGCFG_SHDLOAD0_CMD 15U + +/* Frame complete (Display Controller Display Stream 0) */ +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_IRQ 16U +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE0_CMD 16U + +/* Sequence complete (Display Controller Display Stream 0) */ +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_IRQ 17U +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE0_CMD 17U + +/* Programmable interrupt 0 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT0_IRQ 18U +#define IMXDPUV1_FRAMEGEN0_INT0_CMD 18U + +/* Programmable interrupt 1 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT1_IRQ 19U +#define IMXDPUV1_FRAMEGEN0_INT1_CMD 19U + +/* Programmable interrupt 2 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT2_IRQ 20U +#define IMXDPUV1_FRAMEGEN0_INT2_CMD 20U + +/* Programmable interrupt 3 (Display Controller Display Stream 0 FrameGen #0 unit) */ +#define IMXDPUV1_FRAMEGEN0_INT3_IRQ 21U +#define IMXDPUV1_FRAMEGEN0_INT3_CMD 21U + +/* Shadow load (Display Controller Display Stream 0 Sig #0 unit) */ +#define IMXDPUV1_SIG0_SHDLOAD_IRQ 22U +#define IMXDPUV1_SIG0_SHDLOAD_CMD 22U + +/* Measurement valid (Display Controller Display Stream 0 Sig #0 unit) */ +#define IMXDPUV1_SIG0_VALID_IRQ 23U +#define IMXDPUV1_SIG0_VALID_CMD 23U + +/* Error condition (Display Controller Display Stream 0 Sig #0 unit) */ +#define IMXDPUV1_SIG0_ERROR_IRQ 24U +#define IMXDPUV1_SIG0_ERROR_CMD 24U + +/* Shadow load (Display Controller Display Stream 1) */ +#define IMXDPUV1_DISENGCFG_SHDLOAD1_IRQ 25U +#define IMXDPUV1_DISENGCFG_SHDLOAD1_CMD 25U + +/* Frame complete (Display Controller Display Stream 1) */ +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_IRQ 26U +#define IMXDPUV1_DISENGCFG_FRAMECOMPLETE1_CMD 26U + +/* Sequence complete (Display Controller Display Stream 1) */ +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_IRQ 27U +#define IMXDPUV1_DISENGCFG_SEQCOMPLETE1_CMD 27U + +/* Programmable interrupt 0 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT0_IRQ 28U +#define IMXDPUV1_FRAMEGEN1_INT0_CMD 28U + +/* Programmable interrupt 1 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT1_IRQ 29U +#define IMXDPUV1_FRAMEGEN1_INT1_CMD 29U + +/* Programmable interrupt 2 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT2_IRQ 30U +#define IMXDPUV1_FRAMEGEN1_INT2_CMD 30U + +/* Programmable interrupt 3 (Display Controller Display Stream 1 FrameGen #1 unit) */ +#define IMXDPUV1_FRAMEGEN1_INT3_IRQ 31U +#define IMXDPUV1_FRAMEGEN1_INT3_CMD 31U + +/* Shadow load (Display Controller Display Stream 1 Sig #1 unit) */ +#define IMXDPUV1_SIG1_SHDLOAD_IRQ 32U +#define IMXDPUV1_SIG1_SHDLOAD_CMD 32U + +/* Measurement valid (Display Controller Display Stream 1 Sig #1 unit) */ +#define IMXDPUV1_SIG1_VALID_IRQ 33U +#define IMXDPUV1_SIG1_VALID_CMD 33U + +/* Error condition (Display Controller Display Stream 1 Sig #1 unit) */ +#define IMXDPUV1_SIG1_ERROR_IRQ 34U +#define IMXDPUV1_SIG1_ERROR_CMD 34U + +/* Reserved Do not use */ +#define IMXDPUV1_RESERVED35_IRQ 35U +#define IMXDPUV1_RESERVED35_CMD 35U + +/* Error condition (Command Sequencer) */ +#define IMXDPUV1_CMDSEQ_ERROR_IRQ 36U +#define IMXDPUV1_CMDSEQ_ERROR_CMD 36U + +/* Software interrupt 0 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW0_IRQ 37U +#define IMXDPUV1_COMCTRL_SW0_CMD 37U + +/* Software interrupt 1 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW1_IRQ 38U +#define IMXDPUV1_COMCTRL_SW1_CMD 38U + +/* Software interrupt 2 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW2_IRQ 39U +#define IMXDPUV1_COMCTRL_SW2_CMD 39U + +/* Software interrupt 3 (Common Control) */ +#define IMXDPUV1_COMCTRL_SW3_IRQ 40U +#define IMXDPUV1_COMCTRL_SW3_CMD 40U + +/* Synchronization status activated (Display Controller Safety stream 0) */ +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_IRQ 41U +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_ON_CMD 41U + +/* Synchronization status deactivated (Display Controller Safety stream 0) */ +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_IRQ 42U +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_OFF_CMD 42U + +/* Synchronization status activated (Display Controller Content stream 0) */ +#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_IRQ 43U +#define IMXDPUV1_FRAMEGEN0_SECSYNC_ON_CMD 43U + +/* Synchronization status deactivated (Display Controller Content stream 0) */ +#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_IRQ 44U +#define IMXDPUV1_FRAMEGEN0_SECSYNC_OFF_CMD 44U + +/* Synchronization status activated (Display Controller Safety stream 1) */ +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_IRQ 45U +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_ON_CMD 45U + +/* Synchronization status deactivated (Display Controller Safety stream 1) */ +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_IRQ 46U +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_OFF_CMD 46U + +/* Synchronization status activated (Display Controller Content stream 1) */ +#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_IRQ 47U +#define IMXDPUV1_FRAMEGEN1_SECSYNC_ON_CMD 47U + +/* Synchronization status deactivated (Display Controller Content stream 1) */ +#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_IRQ 48U +#define IMXDPUV1_FRAMEGEN1_SECSYNC_OFF_CMD 48U + +/* Synchronization status (Display Controller Safety stream 0) */ +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_CMD 49U +#define IMXDPUV1_FRAMEGEN0_PRIMSYNC_STS 0U + +/* Synchronization status (Display Controller Content stream 0) */ +#define IMXDPUV1_FRAMEGEN0_SECSYNC_CMD 50U +#define IMXDPUV1_FRAMEGEN0_SECSYNC_STS 1U + +/* Synchronization status (Display Controller Safety stream 1) */ +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_CMD 51U +#define IMXDPUV1_FRAMEGEN1_PRIMSYNC_STS 2U + +/* Synchronization status (Display Controller Content stream 1) */ +#define IMXDPUV1_FRAMEGEN1_SECSYNC_CMD 52U +#define IMXDPUV1_FRAMEGEN1_SECSYNC_STS 3U + +/* Shadow load request (Display Controller Pixel Engine configuration Store #9 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_STORE9_SHDLDREQ_CMD 53U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #0 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_SHDLDREQ_CMD 54U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #4 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_SHDLDREQ_CMD 55U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #1 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_SHDLDREQ_CMD 56U + +/* Shadow load request (Display Controller Pixel Engine configuration ExtDst #5 synchronizer) */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_SHDLDREQ_CMD 57U + +/* Shadow load request (Blit Engine FetchDecode #9 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_SHDLDREQ_CMD 58U + +/* Shadow load request (Blit Engine FetchWarp #9 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_SHDLDREQ_CMD 59U + +/* Shadow load request (Blit Engine FetchEco #9 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_SHDLDREQ_CMD 60U + +/* Shadow load request (Display Controller ConstFrame #0 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_SHDLDREQ_CMD 61U + +/* Shadow load request (Display Controller ConstFrame #4 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_SHDLDREQ_CMD 62U + +/* Shadow load request (Display Controller ConstFrame #1 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_SHDLDREQ_CMD 63U + +/* Shadow load request (Display Controller ConstFrame #5 tree) */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_SHDLDREQ_CMD 64U + +/* Shadow load request (Display Controller FetchWarp #2 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_SHDLDREQ_CMD 65U + +/* Shadow load request (Display Controller FetchEco #2 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_SHDLDREQ_CMD 66U + +/* Shadow load request (Display Controller FetchDecode #0 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_SHDLDREQ_CMD 67U + +/* Shadow load request (Display Controller FetchEco #0 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_SHDLDREQ_CMD 68U + +/* Shadow load request (Display Controller FetchDecode #1 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_SHDLDREQ_CMD 69U + +/* Shadow load request (Display Controller FetchEco #1 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_SHDLDREQ_CMD 70U + +/* Shadow load request (Display Controller FetchLayer #0 tree) */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_SHDLDREQ_CMD 71U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 0) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ0_CMD 72U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 1) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ1_CMD 73U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 2) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ2_CMD 74U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 3) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ3_CMD 75U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 4) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ4_CMD 76U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 5) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ5_CMD 77U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 6) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ6_CMD 78U + +/* Shadow load request (Blit Engine FetchWarp #9 unit Layer 7) */ +#define IMXDPUV1_FETCHWARP9_SHDLDREQ7_CMD 79U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 0) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ0_CMD 80U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 1) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ1_CMD 81U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 2) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ2_CMD 82U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 3) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ3_CMD 83U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 4) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ4_CMD 84U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 5) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ5_CMD 85U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 6) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ6_CMD 86U + +/* Shadow load request (Display Controller FetchWarp #2 unit Layer 7) */ +#define IMXDPUV1_FETCHWARP2_SHDLDREQ7_CMD 87U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 0) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ0_CMD 88U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 1) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ1_CMD 89U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 2) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ2_CMD 90U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 3) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ3_CMD 91U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 4) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ4_CMD 92U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 5) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ5_CMD 93U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 6) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ6_CMD 94U + +/* Shadow load request (Display Controller FetchLayer #0 unit Layer 7) */ +#define IMXDPUV1_FETCHLAYER0_SHDLDREQ7_CMD 95U + + +#endif /* IMXDPUV1_EVENTS */ diff --git a/include/imxdpuv1_registers.h b/include/imxdpuv1_registers.h new file mode 100644 index 00000000000..eb9676b0bbf --- /dev/null +++ b/include/imxdpuv1_registers.h @@ -0,0 +1,22682 @@ +/* + * Copyright (c) 2005-2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/* Instance: IMXDPU */ + +#ifndef IMXDPUV1_REGISTERS_H +#define IMXDPUV1_REGISTERS_H +/* Register: IMXDPUV1_comctrl_IPIdentifier */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER ((uint32_t)(0)) +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_VALUE 0x21340400U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_MASK 0xF0U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNDELIVERYID_SHIFT 4U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_MASK 0xF00U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL_SHIFT 8U +/* Field Value: DESIGNMATURITYLEVEL__PREFS, Pre feasibility study. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__PREFS 0x1U +/* Field Value: DESIGNMATURITYLEVEL__FS, Feasibility study. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__FS 0x2U +/* Field Value: DESIGNMATURITYLEVEL__R0, Functionality complete. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R0 0x3U +/* Field Value: DESIGNMATURITYLEVEL__R1, Verification complete. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_DESIGNMATURITYLEVEL__R1 0x4U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_MASK 0xF000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPEVOLUTION_SHIFT 12U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_MASK 0xF0000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET_SHIFT 16U +/* Field Value: IPFEATURESET__E, Minimal functionality (Eco). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__E 0x1U +/* Field Value: IPFEATURESET__L, Reduced functionality (Light). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__L 0x2U +/* Field Value: IPFEATURESET__P, Advanced functionality (Plus). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__P 0x4U +/* Field Value: IPFEATURESET__X, Extensive functionality (eXtensive). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFEATURESET__X 0x5U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_MASK 0xF00000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION_SHIFT 20U +/* Field Value: IPAPPLICATION__B, Blit Engine only. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__B 0x1U +/* Field Value: IPAPPLICATION__D, Blit Engine and Display Controller. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__D 0x2U +/* Field Value: IPAPPLICATION__V, Display Controller only (with direct capture). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__V 0x3U +/* Field Value: IPAPPLICATION__G, Blit Engine, Display Controller (with direct + * capture), Capture Controller (buffered capture) and Drawing Engine. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__G 0x4U +/* Field Value: IPAPPLICATION__C, Display Controller only. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPAPPLICATION__C 0x5U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_MASK 0xF000000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION_SHIFT 24U +/* Field Value: IPCONFIGURATION__M, Graphics core only (Module). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__M 0x1U +/* Field Value: IPCONFIGURATION__S, Subsystem including a graphics core (System). */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPCONFIGURATION__S 0x2U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_MASK 0xF0000000U +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY_SHIFT 28U +/* Field Value: IPFAMILY__IMXDPU2010, IMXDPU building block generation 2010. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2010 0U +/* Field Value: IPFAMILY__IMXDPU2012, IMXDPU building block generation 2012. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2012 0x1U +/* Field Value: IPFAMILY__IMXDPU2013, IMXDPU building block generation 2013. */ +#define IMXDPUV1_COMCTRL_IPIDENTIFIER_IPFAMILY__IMXDPU2013 0x2U + +/* Register: IMXDPUV1_comctrl_LockUnlock */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK ((uint32_t)(0x40)) +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_COMCTRL_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_comctrl_LockStatus */ +#define IMXDPUV1_COMCTRL_LOCKSTATUS ((uint32_t)(0x44)) +#define IMXDPUV1_COMCTRL_LOCKSTATUS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_COMCTRL_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_comctrl_UserInterruptMask0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0 ((uint32_t)(0x48)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK0_USERINTERRUPTMASK0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptMask1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1 ((uint32_t)(0x4C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTMASK1_USERINTERRUPTMASK1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptEnable0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0 ((uint32_t)(0x50)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE0_INTERRUPTENABLE0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptEnable1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1 ((uint32_t)(0x54)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTENABLE1_INTERRUPTENABLE1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptPreset0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0 ((uint32_t)(0x58)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET0_INTERRUPTPRESET0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptPreset1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1 ((uint32_t)(0x5C)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTPRESET1_INTERRUPTPRESET1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptClear0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0 ((uint32_t)(0x60)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR0_INTERRUPTCLEAR0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptClear1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1 ((uint32_t)(0x64)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTCLEAR1_INTERRUPTCLEAR1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptStatus0 */ +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0 ((uint32_t)(0x68)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS0_INTERRUPTSTATUS0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_InterruptStatus1 */ +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1 ((uint32_t)(0x6C)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_INTERRUPTSTATUS1_INTERRUPTSTATUS1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptEnable0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0 ((uint32_t)(0x80)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE0_USERINTERRUPTENABLE0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptEnable1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1 ((uint32_t)(0x84)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTENABLE1_USERINTERRUPTENABLE1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptPreset0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0 ((uint32_t)(0x88)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET0_USERINTERRUPTPRESET0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptPreset1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1 ((uint32_t)(0x8C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTPRESET1_USERINTERRUPTPRESET1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptClear0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0 ((uint32_t)(0x90)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR0_USERINTERRUPTCLEAR0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptClear1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1 ((uint32_t)(0x94)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTCLEAR1_USERINTERRUPTCLEAR1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptStatus0 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0 ((uint32_t)(0x98)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS0_USERINTERRUPTSTATUS0_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_UserInterruptStatus1 */ +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1 ((uint32_t)(0xA8)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_RESET_MASK 0U +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_USERINTERRUPTSTATUS1_USERINTERRUPTSTATUS1_SHIFT 0U + +/* Register: IMXDPUV1_comctrl_GeneralPurpose */ +#define IMXDPUV1_COMCTRL_GENERALPURPOSE ((uint32_t)(0x100)) +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_VALUE 0U +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_MASK 0xFFFFFFFFU +#define IMXDPUV1_COMCTRL_GENERALPURPOSE_GENERALPURPOSE_SHIFT 0U + +/* Register: IMXDPUV1_cmdseq_HIF */ +#define IMXDPUV1_CMDSEQ_HIF ((uint32_t)(0x400)) +#define IMXDPUV1_CMDSEQ_HIF_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CMDSEQ_HIF_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_HIF_RESET_MASK 0U +#define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_HIF_COMMANDFIFO_SHIFT 0U + +/* Register: IMXDPUV1_cmdseq_LockUnlockHIF */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF ((uint32_t)(0x500)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_RESET_MASK 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF_SHIFT 0U +/* Field Value: LOCKUNLOCKHIF__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCKHIF__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCKHIF__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCKHIF__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCKHIF__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCKHIF_LOCKUNLOCKHIF__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_cmdseq_LockStatusHIF */ +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF ((uint32_t)(0x504)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_MASK 0x1U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_LOCKSTATUSHIF_SHIFT 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_MASK 0x10U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_PRIVILEGESTATUSHIF_SHIFT 4U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_MASK 0x100U +#define IMXDPUV1_CMDSEQ_LOCKSTATUSHIF_FREEZESTATUSHIF_SHIFT 8U + +/* Register: IMXDPUV1_cmdseq_LockUnlock */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK ((uint32_t)(0x580)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CMDSEQ_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_cmdseq_LockStatus */ +#define IMXDPUV1_CMDSEQ_LOCKSTATUS ((uint32_t)(0x584)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CMDSEQ_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_cmdseq_BufferAddress */ +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS ((uint32_t)(0x588)) +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_MASK 0x1U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_LOCAL_SHIFT 0U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_MASK 0xFFFFFFE0U +#define IMXDPUV1_CMDSEQ_BUFFERADDRESS_ADDR_SHIFT 5U + +/* Register: IMXDPUV1_cmdseq_BufferSize */ +#define IMXDPUV1_CMDSEQ_BUFFERSIZE ((uint32_t)(0x58C)) +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_VALUE 0x80U +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_RESET_MASK 0xFFF8U +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_MASK 0xFFF8U +#define IMXDPUV1_CMDSEQ_BUFFERSIZE_SIZE_SHIFT 3U + +/* Register: IMXDPUV1_cmdseq_WatermarkControl */ +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL ((uint32_t)(0x590)) +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_OFFSET ((uint32_t)(0x190)) +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_VALUE 0x600020U +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_MASK 0xFFFFU +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_LOWWM_SHIFT 0U +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_MASK 0xFFFF0000U +#define IMXDPUV1_CMDSEQ_WATERMARKCONTROL_HIGHWM_SHIFT 16U + +/* Register: IMXDPUV1_cmdseq_Control */ +#define IMXDPUV1_CMDSEQ_CONTROL ((uint32_t)(0x594)) +#define IMXDPUV1_CMDSEQ_CONTROL_OFFSET ((uint32_t)(0x194)) +#define IMXDPUV1_CMDSEQ_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_MASK 0x1U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRAXIW_SHIFT 0U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_MASK 0x4U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRRBUF_SHIFT 2U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_MASK 0x8U +#define IMXDPUV1_CMDSEQ_CONTROL_CLRCMDBUF_SHIFT 3U +#define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_MASK 0x80000000U +#define IMXDPUV1_CMDSEQ_CONTROL_CLEAR_SHIFT 31U + +/* Register: IMXDPUV1_cmdseq_Status */ +#define IMXDPUV1_CMDSEQ_STATUS ((uint32_t)(0x598)) +#define IMXDPUV1_CMDSEQ_STATUS_OFFSET ((uint32_t)(0x198)) +#define IMXDPUV1_CMDSEQ_STATUS_RESET_VALUE 0x41000080U +#define IMXDPUV1_CMDSEQ_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_MASK 0x1FFFFU +#define IMXDPUV1_CMDSEQ_STATUS_FIFOSPACE_SHIFT 0U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_MASK 0x1000000U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOEMPTY_SHIFT 24U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_MASK 0x2000000U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOFULL_SHIFT 25U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_MASK 0x4000000U +#define IMXDPUV1_CMDSEQ_STATUS_FIFOWMSTATE_SHIFT 26U +#define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_MASK 0x8000000U +#define IMXDPUV1_CMDSEQ_STATUS_WATCHDOG_SHIFT 27U +#define IMXDPUV1_CMDSEQ_STATUS_READBUSY_MASK 0x10000000U +#define IMXDPUV1_CMDSEQ_STATUS_READBUSY_SHIFT 28U +#define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_MASK 0x20000000U +#define IMXDPUV1_CMDSEQ_STATUS_WRITEBUSY_SHIFT 29U +#define IMXDPUV1_CMDSEQ_STATUS_IDLE_MASK 0x40000000U +#define IMXDPUV1_CMDSEQ_STATUS_IDLE_SHIFT 30U +#define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_MASK 0x80000000U +#define IMXDPUV1_CMDSEQ_STATUS_ERRORHALT_SHIFT 31U + +/* Register: IMXDPUV1_cmdseq_PrefetchWindowStart */ +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART ((uint32_t)(0x59C)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_OFFSET ((uint32_t)(0x19C)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_VALUE 0U +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWSTART_PWSTART_SHIFT 2U + +/* Register: IMXDPUV1_cmdseq_PrefetchWindowEnd */ +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND ((uint32_t)(0x5A0)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_OFFSET ((uint32_t)(0x1A0)) +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_VALUE 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_MASK 0xFFFFFFFCU +#define IMXDPUV1_CMDSEQ_PREFETCHWINDOWEND_PWEND_SHIFT 2U + +/* Register: IMXDPUV1_pixengcfg_SafetyLockUnlock */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK ((uint32_t)(0x800)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK_SHIFT 0U +/* Field Value: SAFETYLOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: SAFETYLOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: SAFETYLOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: SAFETYLOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKUNLOCK_SAFETYLOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_SafetyLockStatus */ +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS ((uint32_t)(0x804)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYLOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYPRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_SAFETYLOCKSTATUS_SAFETYFREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_store9_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK ((uint32_t)(0x808)) +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_SAFETYMASK_STORE9_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst0_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK ((uint32_t)(0x80C)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_SAFETYMASK_EXTDST0_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst4_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK ((uint32_t)(0x810)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_SAFETYMASK_EXTDST4_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst1_SafetyMask_0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0 ((uint32_t)(0x814)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_SAFETYMASK_0_EXTDST1_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_extdst5_SafetyMask */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK ((uint32_t)(0x818)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_SAFETYMASK_EXTDST5_SAFETYMASK_SHIFT 0U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK ((uint32_t)(0x820)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHDECODE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege + * protection. Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKUNLOCK_FETCHDECODE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS ((uint32_t)(0x824)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_LOCKSTATUS_FETCHDECODE9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC ((uint32_t)(0x828)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL_SHIFT 0U +/* Field Value: FETCHDECODE9_SRC_SEL__DISABLE, Unit fetchdecode9 input port + * src is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__DISABLE 0U +/* Field Value: FETCHDECODE9_SRC_SEL__FETCHECO9, Unit fetchdecode9 input port + * src is connected to output of unit fetcheco9 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHECO9 0x3U +/* Field Value: FETCHDECODE9_SRC_SEL__FETCHPERSP9, Unit fetchdecode9 input + * port src is connected to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_DYNAMIC_FETCHDECODE9_SRC_SEL__FETCHPERSP9 0x2U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode9_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS ((uint32_t)(0x82C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL_SHIFT 16U +/* Field Value: FETCHDECODE9_SEL__STORE9, fetchdecode9 module is used from + * store9 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE9 0x1U +/* Field Value: FETCHDECODE9_SEL__EXTDST0, fetchdecode9 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST0 0x2U +/* Field Value: FETCHDECODE9_SEL__EXTDST4, fetchdecode9 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST4 0x3U +/* Field Value: FETCHDECODE9_SEL__EXTDST1, fetchdecode9 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST1 0x4U +/* Field Value: FETCHDECODE9_SEL__EXTDST5, fetchdecode9 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__EXTDST5 0x5U +/* Field Value: FETCHDECODE9_SEL__STORE4, fetchdecode9 module is used from + * store4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE4 0x6U +/* Field Value: FETCHDECODE9_SEL__STORE5, fetchdecode9 module is used from + * store5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__STORE5 0x7U +/* Field Value: FETCHDECODE9_SEL__DISABLE, fetchdecode9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE9_STATUS_FETCHDECODE9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK ((uint32_t)(0x840)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHWARP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHWARP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKUNLOCK_FETCHWARP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS ((uint32_t)(0x844)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_LOCKSTATUS_FETCHWARP9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC ((uint32_t)(0x848)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL_SHIFT 0U +/* Field Value: FETCHWARP9_SRC_SEL__DISABLE, Unit fetchpersp9 input port src + * is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__DISABLE 0U +/* Field Value: FETCHWARP9_SRC_SEL__FETCHECO9, Unit fetchpersp9 input port + * src is connected to output of unit fetcheco9 */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_DYNAMIC_FETCHWARP9_SRC_SEL__FETCHECO9 0x3U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp9_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS ((uint32_t)(0x84C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL_SHIFT 16U +/* Field Value: FETCHWARP9_SEL__STORE9, fetchpersp9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE9 0x1U +/* Field Value: FETCHWARP9_SEL__EXTDST0, fetchpersp9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST0 0x2U +/* Field Value: FETCHWARP9_SEL__EXTDST4, fetchpersp9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST4 0x3U +/* Field Value: FETCHWARP9_SEL__EXTDST1, fetchpersp9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST1 0x4U +/* Field Value: FETCHWARP9_SEL__EXTDST5, fetchpersp9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__EXTDST5 0x5U +/* Field Value: FETCHWARP9_SEL__STORE4, fetchpersp9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE4 0x6U +/* Field Value: FETCHWARP9_SEL__STORE5, fetchpersp9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__STORE5 0x7U +/* Field Value: FETCHWARP9_SEL__DISABLE, fetchpersp9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP9_STATUS_FETCHWARP9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK ((uint32_t)(0x850)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKUNLOCK_FETCHECO9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS ((uint32_t)(0x854)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_LOCKSTATUS_FETCHECO9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco9_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS ((uint32_t)(0x858)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL_SHIFT 16U +/* Field Value: FETCHECO9_SEL__STORE9, fetcheco9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE9 0x1U +/* Field Value: FETCHECO9_SEL__EXTDST0, fetcheco9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO9_SEL__EXTDST4, fetcheco9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO9_SEL__EXTDST1, fetcheco9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO9_SEL__EXTDST5, fetcheco9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO9_SEL__STORE4, fetcheco9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE4 0x6U +/* Field Value: FETCHECO9_SEL__STORE5, fetcheco9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__STORE5 0x7U +/* Field Value: FETCHECO9_SEL__DISABLE, fetcheco9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO9_STATUS_FETCHECO9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_rop9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK ((uint32_t)(0x860)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK_SHIFT 0U +/* Field Value: ROP9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: ROP9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: ROP9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: ROP9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKUNLOCK_ROP9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_rop9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS ((uint32_t)(0x864)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_ROP9_LOCKSTATUS_ROP9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_rop9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC ((uint32_t)(0x868)) +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL_SHIFT 0U +/* Field Value: ROP9_PRIM_SEL__DISABLE, Unit rop9 input port prim is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__DISABLE 0U +/* Field Value: ROP9_PRIM_SEL__FETCHDECODE9, Unit rop9 input port prim is + * connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHDECODE9 0x1U +/* Field Value: ROP9_PRIM_SEL__FETCHPERSP9, Unit rop9 input port prim is connected + * to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_PRIM_SEL__FETCHPERSP9 0x2U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL_SHIFT 8U +/* Field Value: ROP9_SEC_SEL__DISABLE, Unit rop9 input port sec is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__DISABLE 0U +/* Field Value: ROP9_SEC_SEL__FETCHECO9, Unit rop9 input port sec is connected + * to output of unit fetcheco9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_SEC_SEL__FETCHECO9 0x3U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_MASK 0x3F0000U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL_SHIFT 16U +/* Field Value: ROP9_TERT_SEL__DISABLE, Unit rop9 input port tert is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__DISABLE 0U +/* Field Value: ROP9_TERT_SEL__FETCHDECODE9, Unit rop9 input port tert is + * connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHDECODE9 0x1U +/* Field Value: ROP9_TERT_SEL__FETCHPERSP9, Unit rop9 input port tert is connected + * to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_TERT_SEL__FETCHPERSP9 0x2U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN_SHIFT 24U +/* Field Value: ROP9_CLKEN__DISABLE, Clock for rop9 is disabled */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__DISABLE 0U +/* Field Value: ROP9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, frequency + * is defined by the register setting for this pipeline (see [endpoint_name]_Static + * register) */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__AUTOMATIC 0x1U +/* Field Value: ROP9_CLKEN__FULL, Clock for rop9 is without gating */ +#define IMXDPUV1_PIXENGCFG_ROP9_DYNAMIC_ROP9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_rop9_Status */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS ((uint32_t)(0x86C)) +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL_SHIFT 16U +/* Field Value: ROP9_SEL__STORE9, rop9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE9 0x1U +/* Field Value: ROP9_SEL__EXTDST0, rop9 module is used from extdst0 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST0 0x2U +/* Field Value: ROP9_SEL__EXTDST4, rop9 module is used from extdst4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST4 0x3U +/* Field Value: ROP9_SEL__EXTDST1, rop9 module is used from extdst1 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST1 0x4U +/* Field Value: ROP9_SEL__EXTDST5, rop9 module is used from extdst5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__EXTDST5 0x5U +/* Field Value: ROP9_SEL__STORE4, rop9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE4 0x6U +/* Field Value: ROP9_SEL__STORE5, rop9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__STORE5 0x7U +/* Field Value: ROP9_SEL__DISABLE, rop9 module is not used */ +#define IMXDPUV1_PIXENGCFG_ROP9_STATUS_ROP9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_clut9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK ((uint32_t)(0x880)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK_SHIFT 0U +/* Field Value: CLUT9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CLUT9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CLUT9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CLUT9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKUNLOCK_CLUT9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_clut9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS ((uint32_t)(0x884)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CLUT9_LOCKSTATUS_CLUT9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_clut9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC ((uint32_t)(0x888)) +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL_SHIFT 0U +/* Field Value: CLUT9_SRC_SEL__DISABLE, Unit clut9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__DISABLE 0U +/* Field Value: CLUT9_SRC_SEL__BLITBLEND9, Unit clut9 input port src is connected + * to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: CLUT9_SRC_SEL__ROP9, Unit clut9 input port src is connected + * to output of unit rop9 */ +#define IMXDPUV1_PIXENGCFG_CLUT9_DYNAMIC_CLUT9_SRC_SEL__ROP9 0x4U + +/* Register: IMXDPUV1_pixengcfg_clut9_Status */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS ((uint32_t)(0x88C)) +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL_SHIFT 16U +/* Field Value: CLUT9_SEL__STORE9, clut9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE9 0x1U +/* Field Value: CLUT9_SEL__EXTDST0, clut9 module is used from extdst0 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST0 0x2U +/* Field Value: CLUT9_SEL__EXTDST4, clut9 module is used from extdst4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST4 0x3U +/* Field Value: CLUT9_SEL__EXTDST1, clut9 module is used from extdst1 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST1 0x4U +/* Field Value: CLUT9_SEL__EXTDST5, clut9 module is used from extdst5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__EXTDST5 0x5U +/* Field Value: CLUT9_SEL__STORE4, clut9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE4 0x6U +/* Field Value: CLUT9_SEL__STORE5, clut9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__STORE5 0x7U +/* Field Value: CLUT9_SEL__DISABLE, clut9 module is not used */ +#define IMXDPUV1_PIXENGCFG_CLUT9_STATUS_CLUT9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_matrix9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK ((uint32_t)(0x8A0)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK_SHIFT 0U +/* Field Value: MATRIX9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: MATRIX9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: MATRIX9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKUNLOCK_MATRIX9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_matrix9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS ((uint32_t)(0x8A4)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_MATRIX9_LOCKSTATUS_MATRIX9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_matrix9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC ((uint32_t)(0x8A8)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL_SHIFT 0U +/* Field Value: MATRIX9_SRC_SEL__DISABLE, Unit matrix9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__DISABLE 0U +/* Field Value: MATRIX9_SRC_SEL__CLUT9, Unit matrix9 input port src is connected + * to output of unit clut9 */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__CLUT9 0x5U +/* Field Value: MATRIX9_SRC_SEL__BLITBLEND9, Unit matrix9 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: MATRIX9_SRC_SEL__ROP9, Unit matrix9 input port src is connected + * to output of unit rop9 */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_SRC_SEL__ROP9 0x4U +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN_SHIFT 24U +/* Field Value: MATRIX9_CLKEN__DISABLE, Clock for matrix9 is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__DISABLE 0U +/* Field Value: MATRIX9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__AUTOMATIC 0x1U +/* Field Value: MATRIX9_CLKEN__FULL, Clock for matrix9 is without gating */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_DYNAMIC_MATRIX9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_matrix9_Status */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS ((uint32_t)(0x8AC)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL_SHIFT 16U +/* Field Value: MATRIX9_SEL__STORE9, matrix9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE9 0x1U +/* Field Value: MATRIX9_SEL__EXTDST0, matrix9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST0 0x2U +/* Field Value: MATRIX9_SEL__EXTDST4, matrix9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST4 0x3U +/* Field Value: MATRIX9_SEL__EXTDST1, matrix9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST1 0x4U +/* Field Value: MATRIX9_SEL__EXTDST5, matrix9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__EXTDST5 0x5U +/* Field Value: MATRIX9_SEL__STORE4, matrix9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE4 0x6U +/* Field Value: MATRIX9_SEL__STORE5, matrix9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__STORE5 0x7U +/* Field Value: MATRIX9_SEL__DISABLE, matrix9 module is not used */ +#define IMXDPUV1_PIXENGCFG_MATRIX9_STATUS_MATRIX9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK ((uint32_t)(0x8C0)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK_SHIFT 0U +/* Field Value: HSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: HSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: HSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKUNLOCK_HSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS ((uint32_t)(0x8C4)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_HSCALER9_LOCKSTATUS_HSCALER9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC ((uint32_t)(0x8C8)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL_SHIFT 0U +/* Field Value: HSCALER9_SRC_SEL__DISABLE, Unit hscaler9 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__DISABLE 0U +/* Field Value: HSCALER9_SRC_SEL__VSCALER9, Unit hscaler9 input port src is + * connected to output of unit vscaler9 */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__VSCALER9 0x8U +/* Field Value: HSCALER9_SRC_SEL__FILTER9, Unit hscaler9 input port src is + * connected to output of unit filter9 */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__FILTER9 0x9U +/* Field Value: HSCALER9_SRC_SEL__MATRIX9, Unit hscaler9 input port src is + * connected to output of unit matrix9 */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_SRC_SEL__MATRIX9 0x6U +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN_SHIFT 24U +/* Field Value: HSCALER9_CLKEN__DISABLE, Clock for hscaler9 is disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__DISABLE 0U +/* Field Value: HSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__AUTOMATIC 0x1U +/* Field Value: HSCALER9_CLKEN__FULL, Clock for hscaler9 is without gating */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_DYNAMIC_HSCALER9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_hscaler9_Status */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS ((uint32_t)(0x8CC)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL_SHIFT 16U +/* Field Value: HSCALER9_SEL__STORE9, hscaler9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE9 0x1U +/* Field Value: HSCALER9_SEL__EXTDST0, hscaler9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST0 0x2U +/* Field Value: HSCALER9_SEL__EXTDST4, hscaler9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST4 0x3U +/* Field Value: HSCALER9_SEL__EXTDST1, hscaler9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST1 0x4U +/* Field Value: HSCALER9_SEL__EXTDST5, hscaler9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__EXTDST5 0x5U +/* Field Value: HSCALER9_SEL__STORE4, hscaler9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE4 0x6U +/* Field Value: HSCALER9_SEL__STORE5, hscaler9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__STORE5 0x7U +/* Field Value: HSCALER9_SEL__DISABLE, hscaler9 module is not used */ +#define IMXDPUV1_PIXENGCFG_HSCALER9_STATUS_HSCALER9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK ((uint32_t)(0x8E0)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK_SHIFT 0U +/* Field Value: VSCALER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: VSCALER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: VSCALER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKUNLOCK_VSCALER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS ((uint32_t)(0x8E4)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_VSCALER9_LOCKSTATUS_VSCALER9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC ((uint32_t)(0x8E8)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL_SHIFT 0U +/* Field Value: VSCALER9_SRC_SEL__DISABLE, Unit vscaler9 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__DISABLE 0U +/* Field Value: VSCALER9_SRC_SEL__HSCALER9, Unit vscaler9 input port src is + * connected to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__HSCALER9 0x7U +/* Field Value: VSCALER9_SRC_SEL__MATRIX9, Unit vscaler9 input port src is + * connected to output of unit matrix9 */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_SRC_SEL__MATRIX9 0x6U +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN_SHIFT 24U +/* Field Value: VSCALER9_CLKEN__DISABLE, Clock for vscaler9 is disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__DISABLE 0U +/* Field Value: VSCALER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__AUTOMATIC 0x1U +/* Field Value: VSCALER9_CLKEN__FULL, Clock for vscaler9 is without gating */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_DYNAMIC_VSCALER9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_vscaler9_Status */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS ((uint32_t)(0x8EC)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL_SHIFT 16U +/* Field Value: VSCALER9_SEL__STORE9, vscaler9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE9 0x1U +/* Field Value: VSCALER9_SEL__EXTDST0, vscaler9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST0 0x2U +/* Field Value: VSCALER9_SEL__EXTDST4, vscaler9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST4 0x3U +/* Field Value: VSCALER9_SEL__EXTDST1, vscaler9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST1 0x4U +/* Field Value: VSCALER9_SEL__EXTDST5, vscaler9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__EXTDST5 0x5U +/* Field Value: VSCALER9_SEL__STORE4, vscaler9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE4 0x6U +/* Field Value: VSCALER9_SEL__STORE5, vscaler9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__STORE5 0x7U +/* Field Value: VSCALER9_SEL__DISABLE, vscaler9 module is not used */ +#define IMXDPUV1_PIXENGCFG_VSCALER9_STATUS_VSCALER9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_filter9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK ((uint32_t)(0x900)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK_SHIFT 0U +/* Field Value: FILTER9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FILTER9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FILTER9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FILTER9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKUNLOCK_FILTER9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_filter9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS ((uint32_t)(0x904)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FILTER9_LOCKSTATUS_FILTER9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_filter9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC ((uint32_t)(0x908)) +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL_SHIFT 0U +/* Field Value: FILTER9_SRC_SEL__DISABLE, Unit filter9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__DISABLE 0U +/* Field Value: FILTER9_SRC_SEL__HSCALER9, Unit filter9 input port src is + * connected to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__HSCALER9 0x7U +/* Field Value: FILTER9_SRC_SEL__MATRIX9, Unit filter9 input port src is connected + * to output of unit matrix9 */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_SRC_SEL__MATRIX9 0x6U +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN_SHIFT 24U +/* Field Value: FILTER9_CLKEN__DISABLE, Clock for filter9 is disabled */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__DISABLE 0U +/* Field Value: FILTER9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__AUTOMATIC 0x1U +/* Field Value: FILTER9_CLKEN__FULL, Clock for filter9 is without gating */ +#define IMXDPUV1_PIXENGCFG_FILTER9_DYNAMIC_FILTER9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_filter9_Status */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS ((uint32_t)(0x90C)) +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL_SHIFT 16U +/* Field Value: FILTER9_SEL__STORE9, filter9 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE9 0x1U +/* Field Value: FILTER9_SEL__EXTDST0, filter9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST0 0x2U +/* Field Value: FILTER9_SEL__EXTDST4, filter9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST4 0x3U +/* Field Value: FILTER9_SEL__EXTDST1, filter9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST1 0x4U +/* Field Value: FILTER9_SEL__EXTDST5, filter9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__EXTDST5 0x5U +/* Field Value: FILTER9_SEL__STORE4, filter9 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE4 0x6U +/* Field Value: FILTER9_SEL__STORE5, filter9 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__STORE5 0x7U +/* Field Value: FILTER9_SEL__DISABLE, filter9 module is not used */ +#define IMXDPUV1_PIXENGCFG_FILTER9_STATUS_FILTER9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK ((uint32_t)(0x920)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK_SHIFT 0U +/* Field Value: BLITBLEND9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: BLITBLEND9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKUNLOCK_BLITBLEND9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS ((uint32_t)(0x924)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_LOCKSTATUS_BLITBLEND9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC ((uint32_t)(0x928)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL_SHIFT 0U +/* Field Value: BLITBLEND9_PRIM_SEL__DISABLE, Unit blitblend9 input port prim + * is disabled */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__DISABLE 0U +/* Field Value: BLITBLEND9_PRIM_SEL__HSCALER9, Unit blitblend9 input port + * prim is connected to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__HSCALER9 0x7U +/* Field Value: BLITBLEND9_PRIM_SEL__VSCALER9, Unit blitblend9 input port + * prim is connected to output of unit vscaler9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__VSCALER9 0x8U +/* Field Value: BLITBLEND9_PRIM_SEL__FILTER9, Unit blitblend9 input port prim + * is connected to output of unit filter9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__FILTER9 0x9U +/* Field Value: BLITBLEND9_PRIM_SEL__ROP9, Unit blitblend9 input port prim + * is connected to output of unit rop9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_PRIM_SEL__ROP9 0x4U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL_SHIFT 8U +/* Field Value: BLITBLEND9_SEC_SEL__DISABLE, Unit blitblend9 input port sec + * is disabled */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__DISABLE 0U +/* Field Value: BLITBLEND9_SEC_SEL__FETCHDECODE9, Unit blitblend9 input port + * sec is connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHDECODE9 0x1U +/* Field Value: BLITBLEND9_SEC_SEL__FETCHPERSP9, Unit blitblend9 input port + * sec is connected to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_SEC_SEL__FETCHPERSP9 0x2U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN_SHIFT 24U +/* Field Value: BLITBLEND9_CLKEN__DISABLE, Clock for blitblend9 is disabled */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__DISABLE 0U +/* Field Value: BLITBLEND9_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__AUTOMATIC 0x1U +/* Field Value: BLITBLEND9_CLKEN__FULL, Clock for blitblend9 is without gating */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_DYNAMIC_BLITBLEND9_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_blitblend9_Status */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS ((uint32_t)(0x92C)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL_SHIFT 16U +/* Field Value: BLITBLEND9_SEL__STORE9, blitblend9 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE9 0x1U +/* Field Value: BLITBLEND9_SEL__EXTDST0, blitblend9 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST0 0x2U +/* Field Value: BLITBLEND9_SEL__EXTDST4, blitblend9 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST4 0x3U +/* Field Value: BLITBLEND9_SEL__EXTDST1, blitblend9 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST1 0x4U +/* Field Value: BLITBLEND9_SEL__EXTDST5, blitblend9 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__EXTDST5 0x5U +/* Field Value: BLITBLEND9_SEL__STORE4, blitblend9 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE4 0x6U +/* Field Value: BLITBLEND9_SEL__STORE5, blitblend9 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__STORE5 0x7U +/* Field Value: BLITBLEND9_SEL__DISABLE, blitblend9 module is not used */ +#define IMXDPUV1_PIXENGCFG_BLITBLEND9_STATUS_BLITBLEND9_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_store9_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK ((uint32_t)(0x940)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK_SHIFT 0U +/* Field Value: STORE9_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: STORE9_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: STORE9_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: STORE9_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKUNLOCK_STORE9_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_store9_LockStatus */ +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS ((uint32_t)(0x944)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_STORE9_LOCKSTATUS_STORE9_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_store9_Static */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC ((uint32_t)(0x948)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE_SHIFT 8U +/* Field Value: STORE9_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__SINGLE 0U +/* Field Value: STORE9_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET_SHIFT 11U +/* Field Value: STORE9_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__OPERATION 0U +/* Field Value: STORE9_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_STORE9_STATIC_STORE9_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_store9_Dynamic */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC ((uint32_t)(0x94C)) +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_VALUE 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL_SHIFT 0U +/* Field Value: STORE9_SRC_SEL__DISABLE, Unit store9 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__DISABLE 0U +/* Field Value: STORE9_SRC_SEL__HSCALER9, Unit store9 input port src is connected + * to output of unit hscaler9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__HSCALER9 0x7U +/* Field Value: STORE9_SRC_SEL__VSCALER9, Unit store9 input port src is connected + * to output of unit vscaler9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__VSCALER9 0x8U +/* Field Value: STORE9_SRC_SEL__FILTER9, Unit store9 input port src is connected + * to output of unit filter9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FILTER9 0x9U +/* Field Value: STORE9_SRC_SEL__BLITBLEND9, Unit store9 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: STORE9_SRC_SEL__FETCHDECODE9, Unit store9 input port src is + * connected to output of unit fetchdecode9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHDECODE9 0x1U +/* Field Value: STORE9_SRC_SEL__FETCHPERSP9, Unit store9 input port src is + * connected to output of unit fetchpersp9 */ +#define IMXDPUV1_PIXENGCFG_STORE9_DYNAMIC_STORE9_SRC_SEL__FETCHPERSP9 0x2U + +/* Register: IMXDPUV1_pixengcfg_store9_Request */ +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST ((uint32_t)(0x950)) +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_STORE9_REQUEST_STORE9_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_store9_Trigger */ +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER ((uint32_t)(0x954)) +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_STORE9_TRIGGER_STORE9_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_store9_Status */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS ((uint32_t)(0x958)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS_SHIFT 0U +/* Field Value: STORE9_PIPELINE_STATUS__EMPTY, Pipeline with endpoint store9 + * is empty */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__EMPTY 0U +/* Field Value: STORE9_PIPELINE_STATUS__RUNNING, Pipeline with endpoint store9 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint store9 is currently processing one operation with a second one + * already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: STORE9_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY_SHIFT 8U +/* Field Value: STORE9_SYNC_BUSY__IDLE, store9 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__IDLE 0U +/* Field Value: STORE9_SYNC_BUSY__BUSY, store9 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_STORE9_STATUS_STORE9_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK ((uint32_t)(0x960)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKUNLOCK_CONSTFRAME0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS ((uint32_t)(0x964)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_LOCKSTATUS_CONSTFRAME0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe0_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS ((uint32_t)(0x968)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL_SHIFT 16U +/* Field Value: CONSTFRAME0_SEL__STORE9, constframe0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME0_SEL__EXTDST0, constframe0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME0_SEL__EXTDST4, constframe0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME0_SEL__EXTDST1, constframe0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME0_SEL__EXTDST5, constframe0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME0_SEL__STORE4, constframe0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME0_SEL__STORE5, constframe0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME0_SEL__DISABLE, constframe0 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME0_STATUS_CONSTFRAME0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK ((uint32_t)(0x980)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKUNLOCK_EXTDST0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS ((uint32_t)(0x984)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST0_LOCKSTATUS_EXTDST0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC ((uint32_t)(0x988)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST0_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST0_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET_SHIFT 11U +/* Field Value: EXTDST0_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__OPERATION 0U +/* Field Value: EXTDST0_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATIC_EXTDST0_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC ((uint32_t)(0x98C)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_VALUE 0x2CU +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST0_SRC_SEL__DISABLE, Unit extdst0 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST0_SRC_SEL__BLITBLEND9, Unit extdst0 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME0, Unit extdst0 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME1, Unit extdst0 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME4, Unit extdst0 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST0_SRC_SEL__CONSTFRAME5, Unit extdst0 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST0_SRC_SEL__MATRIX4, Unit extdst0 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST0_SRC_SEL__HSCALER4, Unit extdst0 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST0_SRC_SEL__VSCALER4, Unit extdst0 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST0_SRC_SEL__EXTSRC4, Unit extdst0 input port src is connected + * to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC4 0x14U +/* Field Value: EXTDST0_SRC_SEL__MATRIX5, Unit extdst0 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST0_SRC_SEL__HSCALER5, Unit extdst0 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST0_SRC_SEL__VSCALER5, Unit extdst0 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST0_SRC_SEL__EXTSRC5, Unit extdst0 input port src is connected + * to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__EXTSRC5 0x16U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND6, Unit extdst0 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND5, Unit extdst0 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND4, Unit extdst0 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND3, Unit extdst0 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND2, Unit extdst0 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND1, Unit extdst0 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST0_SRC_SEL__LAYERBLEND0, Unit extdst0 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_DYNAMIC_EXTDST0_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst0_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST ((uint32_t)(0x990)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_OFFSET ((uint32_t)(0x190)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST0_REQUEST_EXTDST0_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER ((uint32_t)(0x994)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_OFFSET ((uint32_t)(0x194)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST0_TRIGGER_EXTDST0_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst0_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS ((uint32_t)(0x998)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_OFFSET ((uint32_t)(0x198)) +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST0_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst0 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst0 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst0 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST0_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST0_SYNC_BUSY__IDLE, extdst0 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST0_SYNC_BUSY__BUSY, extdst0 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST0_STATUS_EXTDST0_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK ((uint32_t)(0x9A0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_OFFSET ((uint32_t)(0x1A0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKUNLOCK_CONSTFRAME4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS ((uint32_t)(0x9A4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_OFFSET ((uint32_t)(0x1A4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_LOCKSTATUS_CONSTFRAME4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe4_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS ((uint32_t)(0x9A8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_OFFSET ((uint32_t)(0x1A8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL_SHIFT 16U +/* Field Value: CONSTFRAME4_SEL__STORE9, constframe4 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME4_SEL__EXTDST0, constframe4 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME4_SEL__EXTDST4, constframe4 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME4_SEL__EXTDST1, constframe4 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME4_SEL__EXTDST5, constframe4 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME4_SEL__STORE4, constframe4 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME4_SEL__STORE5, constframe4 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME4_SEL__DISABLE, constframe4 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME4_STATUS_CONSTFRAME4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK ((uint32_t)(0x9C0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_OFFSET ((uint32_t)(0x1C0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKUNLOCK_EXTDST4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS ((uint32_t)(0x9C4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_OFFSET ((uint32_t)(0x1C4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST4_LOCKSTATUS_EXTDST4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC ((uint32_t)(0x9C8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_OFFSET ((uint32_t)(0x1C8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST4_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST4_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET_SHIFT 11U +/* Field Value: EXTDST4_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__OPERATION 0U +/* Field Value: EXTDST4_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATIC_EXTDST4_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC ((uint32_t)(0x9CC)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_OFFSET ((uint32_t)(0x1CC)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_VALUE 0x30U +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST4_SRC_SEL__DISABLE, Unit extdst4 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST4_SRC_SEL__BLITBLEND9, Unit extdst4 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME0, Unit extdst4 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME1, Unit extdst4 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME4, Unit extdst4 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST4_SRC_SEL__CONSTFRAME5, Unit extdst4 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST4_SRC_SEL__MATRIX4, Unit extdst4 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST4_SRC_SEL__HSCALER4, Unit extdst4 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST4_SRC_SEL__VSCALER4, Unit extdst4 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST4_SRC_SEL__MATRIX5, Unit extdst4 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST4_SRC_SEL__HSCALER5, Unit extdst4 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST4_SRC_SEL__VSCALER5, Unit extdst4 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND6, Unit extdst4 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND5, Unit extdst4 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND4, Unit extdst4 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND3, Unit extdst4 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND2, Unit extdst4 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND1, Unit extdst4 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST4_SRC_SEL__LAYERBLEND0, Unit extdst4 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_DYNAMIC_EXTDST4_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst4_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST ((uint32_t)(0x9D0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_OFFSET ((uint32_t)(0x1D0)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST4_REQUEST_EXTDST4_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER ((uint32_t)(0x9D4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_OFFSET ((uint32_t)(0x1D4)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST4_TRIGGER_EXTDST4_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst4_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS ((uint32_t)(0x9D8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_OFFSET ((uint32_t)(0x1D8)) +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST4_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst4 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst4 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst4 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST4_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST4_SYNC_BUSY__IDLE, extdst4 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST4_SYNC_BUSY__BUSY, extdst4 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST4_STATUS_EXTDST4_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK ((uint32_t)(0x9E0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_OFFSET ((uint32_t)(0x1E0)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKUNLOCK_CONSTFRAME1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS ((uint32_t)(0x9E4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_OFFSET ((uint32_t)(0x1E4)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_LOCKSTATUS_CONSTFRAME1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe1_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS ((uint32_t)(0x9E8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_OFFSET ((uint32_t)(0x1E8)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL_SHIFT 16U +/* Field Value: CONSTFRAME1_SEL__STORE9, constframe1 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME1_SEL__EXTDST0, constframe1 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME1_SEL__EXTDST4, constframe1 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME1_SEL__EXTDST1, constframe1 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME1_SEL__EXTDST5, constframe1 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME1_SEL__STORE4, constframe1 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME1_SEL__STORE5, constframe1 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME1_SEL__DISABLE, constframe1 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME1_STATUS_CONSTFRAME1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK ((uint32_t)(0xA00)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_OFFSET ((uint32_t)(0x200)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKUNLOCK_EXTDST1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS ((uint32_t)(0xA04)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_OFFSET ((uint32_t)(0x204)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST1_LOCKSTATUS_EXTDST1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC ((uint32_t)(0xA08)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_OFFSET ((uint32_t)(0x208)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST1_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST1_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET_SHIFT 11U +/* Field Value: EXTDST1_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__OPERATION 0U +/* Field Value: EXTDST1_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATIC_EXTDST1_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC ((uint32_t)(0xA0C)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_OFFSET ((uint32_t)(0x20C)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_VALUE 0x2DU +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST1_SRC_SEL__DISABLE, Unit extdst1 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST1_SRC_SEL__BLITBLEND9, Unit extdst1 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME0, Unit extdst1 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME1, Unit extdst1 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME4, Unit extdst1 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST1_SRC_SEL__CONSTFRAME5, Unit extdst1 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST1_SRC_SEL__MATRIX4, Unit extdst1 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST1_SRC_SEL__HSCALER4, Unit extdst1 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST1_SRC_SEL__VSCALER4, Unit extdst1 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST1_SRC_SEL__EXTSRC4, Unit extdst1 input port src is connected + * to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC4 0x14U +/* Field Value: EXTDST1_SRC_SEL__MATRIX5, Unit extdst1 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST1_SRC_SEL__HSCALER5, Unit extdst1 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST1_SRC_SEL__VSCALER5, Unit extdst1 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST1_SRC_SEL__EXTSRC5, Unit extdst1 input port src is connected + * to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__EXTSRC5 0x16U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND6, Unit extdst1 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND5, Unit extdst1 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND4, Unit extdst1 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND3, Unit extdst1 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND2, Unit extdst1 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND1, Unit extdst1 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST1_SRC_SEL__LAYERBLEND0, Unit extdst1 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_DYNAMIC_EXTDST1_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst1_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST ((uint32_t)(0xA10)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_OFFSET ((uint32_t)(0x210)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST1_REQUEST_EXTDST1_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER ((uint32_t)(0xA14)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_OFFSET ((uint32_t)(0x214)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST1_TRIGGER_EXTDST1_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst1_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS ((uint32_t)(0xA18)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_OFFSET ((uint32_t)(0x218)) +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST1_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst1 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst1 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst1 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST1_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST1_SYNC_BUSY__IDLE, extdst1 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST1_SYNC_BUSY__BUSY, extdst1 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST1_STATUS_EXTDST1_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_constframe5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK ((uint32_t)(0xA20)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_OFFSET ((uint32_t)(0x220)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK_SHIFT 0U +/* Field Value: CONSTFRAME5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKUNLOCK_CONSTFRAME5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_constframe5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS ((uint32_t)(0xA24)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_OFFSET ((uint32_t)(0x224)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_LOCKSTATUS_CONSTFRAME5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_constframe5_Status */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS ((uint32_t)(0xA28)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_OFFSET ((uint32_t)(0x228)) +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL_SHIFT 16U +/* Field Value: CONSTFRAME5_SEL__STORE9, constframe5 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE9 0x1U +/* Field Value: CONSTFRAME5_SEL__EXTDST0, constframe5 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST0 0x2U +/* Field Value: CONSTFRAME5_SEL__EXTDST4, constframe5 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST4 0x3U +/* Field Value: CONSTFRAME5_SEL__EXTDST1, constframe5 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST1 0x4U +/* Field Value: CONSTFRAME5_SEL__EXTDST5, constframe5 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__EXTDST5 0x5U +/* Field Value: CONSTFRAME5_SEL__STORE4, constframe5 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE4 0x6U +/* Field Value: CONSTFRAME5_SEL__STORE5, constframe5 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__STORE5 0x7U +/* Field Value: CONSTFRAME5_SEL__DISABLE, constframe5 module is not used */ +#define IMXDPUV1_PIXENGCFG_CONSTFRAME5_STATUS_CONSTFRAME5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_extdst5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK ((uint32_t)(0xA40)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_OFFSET ((uint32_t)(0x240)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK_SHIFT 0U +/* Field Value: EXTDST5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: EXTDST5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: EXTDST5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKUNLOCK_EXTDST5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_extdst5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS ((uint32_t)(0xA44)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_OFFSET ((uint32_t)(0x244)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST5_LOCKSTATUS_EXTDST5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Static */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC ((uint32_t)(0xA48)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_OFFSET ((uint32_t)(0x248)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_VALUE 0x800010U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SHDEN_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_POWERDOWN_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE_SHIFT 8U +/* Field Value: EXTDST5_SYNC_MODE__SINGLE, Reconfig pipeline after explicit + * trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__SINGLE 0U +/* Field Value: EXTDST5_SYNC_MODE__AUTO, Reconfig pipeline after every kick + * when idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SYNC_MODE__AUTO 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_MASK 0x800U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET_SHIFT 11U +/* Field Value: EXTDST5_SW_RESET__OPERATION, Normal Operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__OPERATION 0U +/* Field Value: EXTDST5_SW_RESET__SWRESET, Software Reset */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_SW_RESET__SWRESET 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_MASK 0xFF0000U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATIC_EXTDST5_DIV_SHIFT 16U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC ((uint32_t)(0xA4C)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_OFFSET ((uint32_t)(0x24C)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_VALUE 0x31U +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL_SHIFT 0U +/* Field Value: EXTDST5_SRC_SEL__DISABLE, Unit extdst5 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__DISABLE 0U +/* Field Value: EXTDST5_SRC_SEL__BLITBLEND9, Unit extdst5 input port src is + * connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__BLITBLEND9 0xAU +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME0, Unit extdst5 input port src + * is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME0 0xCU +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME1, Unit extdst5 input port src + * is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME1 0x10U +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME4, Unit extdst5 input port src + * is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME4 0xEU +/* Field Value: EXTDST5_SRC_SEL__CONSTFRAME5, Unit extdst5 input port src + * is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__CONSTFRAME5 0x12U +/* Field Value: EXTDST5_SRC_SEL__MATRIX4, Unit extdst5 input port src is connected + * to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX4 0x23U +/* Field Value: EXTDST5_SRC_SEL__HSCALER4, Unit extdst5 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER4 0x24U +/* Field Value: EXTDST5_SRC_SEL__VSCALER4, Unit extdst5 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER4 0x25U +/* Field Value: EXTDST5_SRC_SEL__MATRIX5, Unit extdst5 input port src is connected + * to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__MATRIX5 0x28U +/* Field Value: EXTDST5_SRC_SEL__HSCALER5, Unit extdst5 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__HSCALER5 0x29U +/* Field Value: EXTDST5_SRC_SEL__VSCALER5, Unit extdst5 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__VSCALER5 0x2AU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND6, Unit extdst5 input port src + * is connected to output of unit layerblend6 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND6 0x32U +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND5, Unit extdst5 input port src + * is connected to output of unit layerblend5 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND5 0x31U +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND4, Unit extdst5 input port src + * is connected to output of unit layerblend4 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND4 0x30U +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND3, Unit extdst5 input port src + * is connected to output of unit layerblend3 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND3 0x2FU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND2, Unit extdst5 input port src + * is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND2 0x2EU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND1, Unit extdst5 input port src + * is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND1 0x2DU +/* Field Value: EXTDST5_SRC_SEL__LAYERBLEND0, Unit extdst5 input port src + * is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_DYNAMIC_EXTDST5_SRC_SEL__LAYERBLEND0 0x2CU + +/* Register: IMXDPUV1_pixengcfg_extdst5_Request */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST ((uint32_t)(0xA50)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_OFFSET ((uint32_t)(0x250)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SEL_SHDLDREQ_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_MASK 0x3FFFFEU +#define IMXDPUV1_PIXENGCFG_EXTDST5_REQUEST_EXTDST5_SHDLDREQ_SHIFT 1U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Trigger */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER ((uint32_t)(0xA54)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_OFFSET ((uint32_t)(0x254)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_RESET_MASK 0xFFFFFFEEU +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_SYNC_TRIGGER_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_EXTDST5_TRIGGER_EXTDST5_TRIGGER_SEQUENCE_COMPLETE_SHIFT 4U + +/* Register: IMXDPUV1_pixengcfg_extdst5_Status */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS ((uint32_t)(0xA58)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_OFFSET ((uint32_t)(0x258)) +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_MASK 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS_SHIFT 0U +/* Field Value: EXTDST5_PIPELINE_STATUS__EMPTY, Pipeline with endpoint extdst5 + * is empty */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__EMPTY 0U +/* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING, Pipeline with endpoint extdst5 + * is currently processing one operation */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING 0x1U +/* Field Value: EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED, Pipeline with + * endpoint extdst5 is currently processing one operation with a second + * one already kicked to be processed afterwards */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RUNNING_RETRIGGERED 0x2U +/* Field Value: EXTDST5_PIPELINE_STATUS__RESERVED, reserved */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_PIPELINE_STATUS__RESERVED 0x3U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY_SHIFT 8U +/* Field Value: EXTDST5_SYNC_BUSY__IDLE, extdst5 synchronizer is idle */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__IDLE 0U +/* Field Value: EXTDST5_SYNC_BUSY__BUSY, extdst5 synchronizer is busy */ +#define IMXDPUV1_PIXENGCFG_EXTDST5_STATUS_EXTDST5_SYNC_BUSY__BUSY 0x1U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK ((uint32_t)(0xA60)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_OFFSET ((uint32_t)(0x260)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHWARP2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHWARP2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKUNLOCK_FETCHWARP2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS ((uint32_t)(0xA64)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_OFFSET ((uint32_t)(0x264)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_LOCKSTATUS_FETCHWARP2_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC ((uint32_t)(0xA68)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_OFFSET ((uint32_t)(0x268)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL_SHIFT 0U +/* Field Value: FETCHWARP2_SRC_SEL__DISABLE, Unit fetchwarp2 input port src + * is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__DISABLE 0U +/* Field Value: FETCHWARP2_SRC_SEL__FETCHECO2, Unit fetchwarp2 input port + * src is connected to output of unit fetcheco2 */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_DYNAMIC_FETCHWARP2_SRC_SEL__FETCHECO2 0x1BU + +/* Register: IMXDPUV1_pixengcfg_fetchwarp2_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS ((uint32_t)(0xA6C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_OFFSET ((uint32_t)(0x26C)) +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL_SHIFT 16U +/* Field Value: FETCHWARP2_SEL__STORE9, fetchwarp2 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE9 0x1U +/* Field Value: FETCHWARP2_SEL__EXTDST0, fetchwarp2 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST0 0x2U +/* Field Value: FETCHWARP2_SEL__EXTDST4, fetchwarp2 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST4 0x3U +/* Field Value: FETCHWARP2_SEL__EXTDST1, fetchwarp2 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST1 0x4U +/* Field Value: FETCHWARP2_SEL__EXTDST5, fetchwarp2 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__EXTDST5 0x5U +/* Field Value: FETCHWARP2_SEL__STORE4, fetchwarp2 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE4 0x6U +/* Field Value: FETCHWARP2_SEL__STORE5, fetchwarp2 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__STORE5 0x7U +/* Field Value: FETCHWARP2_SEL__DISABLE, fetchwarp2 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHWARP2_STATUS_FETCHWARP2_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco2_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK ((uint32_t)(0xA70)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_OFFSET ((uint32_t)(0x270)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKUNLOCK_FETCHECO2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco2_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS ((uint32_t)(0xA74)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_OFFSET ((uint32_t)(0x274)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_LOCKSTATUS_FETCHECO2_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco2_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS ((uint32_t)(0xA78)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_OFFSET ((uint32_t)(0x278)) +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL_SHIFT 16U +/* Field Value: FETCHECO2_SEL__STORE9, fetcheco2 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE9 0x1U +/* Field Value: FETCHECO2_SEL__EXTDST0, fetcheco2 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO2_SEL__EXTDST4, fetcheco2 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO2_SEL__EXTDST1, fetcheco2 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO2_SEL__EXTDST5, fetcheco2 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO2_SEL__STORE4, fetcheco2 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE4 0x6U +/* Field Value: FETCHECO2_SEL__STORE5, fetcheco2 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__STORE5 0x7U +/* Field Value: FETCHECO2_SEL__DISABLE, fetcheco2 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO2_STATUS_FETCHECO2_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK ((uint32_t)(0xA80)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_OFFSET ((uint32_t)(0x280)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHDECODE0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege + * protection. Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKUNLOCK_FETCHDECODE0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS ((uint32_t)(0xA84)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_OFFSET ((uint32_t)(0x284)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_LOCKSTATUS_FETCHDECODE0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC ((uint32_t)(0xA88)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_OFFSET ((uint32_t)(0x288)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL_SHIFT 0U +/* Field Value: FETCHDECODE0_SRC_SEL__DISABLE, Unit fetchdecode0 input port + * src is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__DISABLE 0U +/* Field Value: FETCHDECODE0_SRC_SEL__FETCHECO0, Unit fetchdecode0 input port + * src is connected to output of unit fetcheco0 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHECO0 0x1DU +/* Field Value: FETCHDECODE0_SRC_SEL__FETCHDECODE2, Unit fetchdecode0 input + * port src is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_DYNAMIC_FETCHDECODE0_SRC_SEL__FETCHDECODE2 0x18U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode0_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS ((uint32_t)(0xA8C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_OFFSET ((uint32_t)(0x28C)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL_SHIFT 16U +/* Field Value: FETCHDECODE0_SEL__STORE9, fetchdecode0 module is used from + * store9 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE9 0x1U +/* Field Value: FETCHDECODE0_SEL__EXTDST0, fetchdecode0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST0 0x2U +/* Field Value: FETCHDECODE0_SEL__EXTDST4, fetchdecode0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST4 0x3U +/* Field Value: FETCHDECODE0_SEL__EXTDST1, fetchdecode0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST1 0x4U +/* Field Value: FETCHDECODE0_SEL__EXTDST5, fetchdecode0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__EXTDST5 0x5U +/* Field Value: FETCHDECODE0_SEL__STORE4, fetchdecode0 module is used from + * store4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE4 0x6U +/* Field Value: FETCHDECODE0_SEL__STORE5, fetchdecode0 module is used from + * store5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__STORE5 0x7U +/* Field Value: FETCHDECODE0_SEL__DISABLE, fetchdecode0 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE0_STATUS_FETCHDECODE0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK ((uint32_t)(0xA90)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_OFFSET ((uint32_t)(0x290)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKUNLOCK_FETCHECO0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS ((uint32_t)(0xA94)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_OFFSET ((uint32_t)(0x294)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_LOCKSTATUS_FETCHECO0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco0_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS ((uint32_t)(0xA98)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_OFFSET ((uint32_t)(0x298)) +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL_SHIFT 16U +/* Field Value: FETCHECO0_SEL__STORE9, fetcheco0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE9 0x1U +/* Field Value: FETCHECO0_SEL__EXTDST0, fetcheco0 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO0_SEL__EXTDST4, fetcheco0 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO0_SEL__EXTDST1, fetcheco0 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO0_SEL__EXTDST5, fetcheco0 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO0_SEL__STORE4, fetcheco0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE4 0x6U +/* Field Value: FETCHECO0_SEL__STORE5, fetcheco0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__STORE5 0x7U +/* Field Value: FETCHECO0_SEL__DISABLE, fetcheco0 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO0_STATUS_FETCHECO0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK ((uint32_t)(0xAA0)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_OFFSET ((uint32_t)(0x2A0)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHDECODE1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege + * protection. Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKUNLOCK_FETCHDECODE1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS ((uint32_t)(0xAA4)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_OFFSET ((uint32_t)(0x2A4)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_LOCKSTATUS_FETCHDECODE1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_Dynamic */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC ((uint32_t)(0xAA8)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_OFFSET ((uint32_t)(0x2A8)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL_SHIFT 0U +/* Field Value: FETCHDECODE1_SRC_SEL__DISABLE, Unit fetchdecode1 input port + * src is disabled */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__DISABLE 0U +/* Field Value: FETCHDECODE1_SRC_SEL__FETCHECO1, Unit fetchdecode1 input port + * src is connected to output of unit fetcheco1 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHECO1 0x1FU +/* Field Value: FETCHDECODE1_SRC_SEL__FETCHDECODE3, Unit fetchdecode1 input + * port src is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_DYNAMIC_FETCHDECODE1_SRC_SEL__FETCHDECODE3 0x19U + +/* Register: IMXDPUV1_pixengcfg_fetchdecode1_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS ((uint32_t)(0xAAC)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_OFFSET ((uint32_t)(0x2AC)) +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL_SHIFT 16U +/* Field Value: FETCHDECODE1_SEL__STORE9, fetchdecode1 module is used from + * store9 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE9 0x1U +/* Field Value: FETCHDECODE1_SEL__EXTDST0, fetchdecode1 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST0 0x2U +/* Field Value: FETCHDECODE1_SEL__EXTDST4, fetchdecode1 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST4 0x3U +/* Field Value: FETCHDECODE1_SEL__EXTDST1, fetchdecode1 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST1 0x4U +/* Field Value: FETCHDECODE1_SEL__EXTDST5, fetchdecode1 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__EXTDST5 0x5U +/* Field Value: FETCHDECODE1_SEL__STORE4, fetchdecode1 module is used from + * store4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE4 0x6U +/* Field Value: FETCHDECODE1_SEL__STORE5, fetchdecode1 module is used from + * store5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__STORE5 0x7U +/* Field Value: FETCHDECODE1_SEL__DISABLE, fetchdecode1 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHDECODE1_STATUS_FETCHDECODE1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetcheco1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK ((uint32_t)(0xAB0)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_OFFSET ((uint32_t)(0x2B0)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHECO1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHECO1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHECO1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKUNLOCK_FETCHECO1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetcheco1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS ((uint32_t)(0xAB4)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_OFFSET ((uint32_t)(0x2B4)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_LOCKSTATUS_FETCHECO1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetcheco1_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS ((uint32_t)(0xAB8)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_OFFSET ((uint32_t)(0x2B8)) +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL_SHIFT 16U +/* Field Value: FETCHECO1_SEL__STORE9, fetcheco1 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE9 0x1U +/* Field Value: FETCHECO1_SEL__EXTDST0, fetcheco1 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST0 0x2U +/* Field Value: FETCHECO1_SEL__EXTDST4, fetcheco1 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST4 0x3U +/* Field Value: FETCHECO1_SEL__EXTDST1, fetcheco1 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST1 0x4U +/* Field Value: FETCHECO1_SEL__EXTDST5, fetcheco1 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__EXTDST5 0x5U +/* Field Value: FETCHECO1_SEL__STORE4, fetcheco1 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE4 0x6U +/* Field Value: FETCHECO1_SEL__STORE5, fetcheco1 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__STORE5 0x7U +/* Field Value: FETCHECO1_SEL__DISABLE, fetcheco1 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHECO1_STATUS_FETCHECO1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK ((uint32_t)(0xAC0)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_OFFSET ((uint32_t)(0x2C0)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK_SHIFT 0U +/* Field Value: FETCHLAYER0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKUNLOCK_FETCHLAYER0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_fetchlayer0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS ((uint32_t)(0xAC4)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_OFFSET ((uint32_t)(0x2C4)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_LOCKSTATUS_FETCHLAYER0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_fetchlayer0_Status */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS ((uint32_t)(0xAC8)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_OFFSET ((uint32_t)(0x2C8)) +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL_SHIFT 16U +/* Field Value: FETCHLAYER0_SEL__STORE9, fetchlayer0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE9 0x1U +/* Field Value: FETCHLAYER0_SEL__EXTDST0, fetchlayer0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST0 0x2U +/* Field Value: FETCHLAYER0_SEL__EXTDST4, fetchlayer0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST4 0x3U +/* Field Value: FETCHLAYER0_SEL__EXTDST1, fetchlayer0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST1 0x4U +/* Field Value: FETCHLAYER0_SEL__EXTDST5, fetchlayer0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__EXTDST5 0x5U +/* Field Value: FETCHLAYER0_SEL__STORE4, fetchlayer0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE4 0x6U +/* Field Value: FETCHLAYER0_SEL__STORE5, fetchlayer0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__STORE5 0x7U +/* Field Value: FETCHLAYER0_SEL__DISABLE, fetchlayer0 module is not used */ +#define IMXDPUV1_PIXENGCFG_FETCHLAYER0_STATUS_FETCHLAYER0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_matrix4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK ((uint32_t)(0xAE0)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_OFFSET ((uint32_t)(0x2E0)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK_SHIFT 0U +/* Field Value: MATRIX4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: MATRIX4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: MATRIX4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKUNLOCK_MATRIX4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_matrix4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS ((uint32_t)(0xAE4)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_OFFSET ((uint32_t)(0x2E4)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_MATRIX4_LOCKSTATUS_MATRIX4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_matrix4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC ((uint32_t)(0xAE8)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_OFFSET ((uint32_t)(0x2E8)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL_SHIFT 0U +/* Field Value: MATRIX4_SRC_SEL__DISABLE, Unit matrix4 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__DISABLE 0U +/* Field Value: MATRIX4_SRC_SEL__GAMMACOR4, Unit matrix4 input port src is + * connected to output of unit gammacor4 */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_SRC_SEL__GAMMACOR4 0x22U +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN_SHIFT 24U +/* Field Value: MATRIX4_CLKEN__DISABLE, Clock for matrix4 is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__DISABLE 0U +/* Field Value: MATRIX4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__AUTOMATIC 0x1U +/* Field Value: MATRIX4_CLKEN__FULL, Clock for matrix4 is without gating */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_DYNAMIC_MATRIX4_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_matrix4_Status */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS ((uint32_t)(0xAEC)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_OFFSET ((uint32_t)(0x2EC)) +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL_SHIFT 16U +/* Field Value: MATRIX4_SEL__STORE9, matrix4 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE9 0x1U +/* Field Value: MATRIX4_SEL__EXTDST0, matrix4 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST0 0x2U +/* Field Value: MATRIX4_SEL__EXTDST4, matrix4 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST4 0x3U +/* Field Value: MATRIX4_SEL__EXTDST1, matrix4 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST1 0x4U +/* Field Value: MATRIX4_SEL__EXTDST5, matrix4 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__EXTDST5 0x5U +/* Field Value: MATRIX4_SEL__STORE4, matrix4 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE4 0x6U +/* Field Value: MATRIX4_SEL__STORE5, matrix4 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__STORE5 0x7U +/* Field Value: MATRIX4_SEL__DISABLE, matrix4 module is not used */ +#define IMXDPUV1_PIXENGCFG_MATRIX4_STATUS_MATRIX4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK ((uint32_t)(0xB00)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0x300)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK_SHIFT 0U +/* Field Value: HSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: HSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: HSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKUNLOCK_HSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS ((uint32_t)(0xB04)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x304)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_HSCALER4_LOCKSTATUS_HSCALER4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC ((uint32_t)(0xB08)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_OFFSET ((uint32_t)(0x308)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL_SHIFT 0U +/* Field Value: HSCALER4_SRC_SEL__DISABLE, Unit hscaler4 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__DISABLE 0U +/* Field Value: HSCALER4_SRC_SEL__EXTSRC4, Unit hscaler4 input port src is + * connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__EXTSRC4 0x14U +/* Field Value: HSCALER4_SRC_SEL__FETCHDECODE0, Unit hscaler4 input port src + * is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE0 0x1CU +/* Field Value: HSCALER4_SRC_SEL__FETCHDECODE2, Unit hscaler4 input port src + * is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__FETCHDECODE2 0x18U +/* Field Value: HSCALER4_SRC_SEL__MATRIX4, Unit hscaler4 input port src is + * connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__MATRIX4 0x23U +/* Field Value: HSCALER4_SRC_SEL__VSCALER4, Unit hscaler4 input port src is + * connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_SRC_SEL__VSCALER4 0x25U +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN_SHIFT 24U +/* Field Value: HSCALER4_CLKEN__DISABLE, Clock for hscaler4 is disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__DISABLE 0U +/* Field Value: HSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__AUTOMATIC 0x1U +/* Field Value: HSCALER4_CLKEN__FULL, Clock for hscaler4 is without gating */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_DYNAMIC_HSCALER4_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_hscaler4_Status */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS ((uint32_t)(0xB0C)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_OFFSET ((uint32_t)(0x30C)) +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL_SHIFT 16U +/* Field Value: HSCALER4_SEL__STORE9, hscaler4 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE9 0x1U +/* Field Value: HSCALER4_SEL__EXTDST0, hscaler4 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST0 0x2U +/* Field Value: HSCALER4_SEL__EXTDST4, hscaler4 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST4 0x3U +/* Field Value: HSCALER4_SEL__EXTDST1, hscaler4 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST1 0x4U +/* Field Value: HSCALER4_SEL__EXTDST5, hscaler4 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__EXTDST5 0x5U +/* Field Value: HSCALER4_SEL__STORE4, hscaler4 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE4 0x6U +/* Field Value: HSCALER4_SEL__STORE5, hscaler4 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__STORE5 0x7U +/* Field Value: HSCALER4_SEL__DISABLE, hscaler4 module is not used */ +#define IMXDPUV1_PIXENGCFG_HSCALER4_STATUS_HSCALER4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK ((uint32_t)(0xB20)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0x320)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK_SHIFT 0U +/* Field Value: VSCALER4_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: VSCALER4_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: VSCALER4_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKUNLOCK_VSCALER4_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_LockStatus */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS ((uint32_t)(0xB24)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x324)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_VSCALER4_LOCKSTATUS_VSCALER4_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_Dynamic */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC ((uint32_t)(0xB28)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_OFFSET ((uint32_t)(0x328)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL_SHIFT 0U +/* Field Value: VSCALER4_SRC_SEL__DISABLE, Unit vscaler4 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__DISABLE 0U +/* Field Value: VSCALER4_SRC_SEL__EXTSRC4, Unit vscaler4 input port src is + * connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__EXTSRC4 0x14U +/* Field Value: VSCALER4_SRC_SEL__FETCHDECODE0, Unit vscaler4 input port src + * is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE0 0x1CU +/* Field Value: VSCALER4_SRC_SEL__FETCHDECODE2, Unit vscaler4 input port src + * is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__FETCHDECODE2 0x18U +/* Field Value: VSCALER4_SRC_SEL__HSCALER4, Unit vscaler4 input port src is + * connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__HSCALER4 0x24U +/* Field Value: VSCALER4_SRC_SEL__MATRIX4, Unit vscaler4 input port src is + * connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_SRC_SEL__MATRIX4 0x23U +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN_SHIFT 24U +/* Field Value: VSCALER4_CLKEN__DISABLE, Clock for vscaler4 is disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__DISABLE 0U +/* Field Value: VSCALER4_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__AUTOMATIC 0x1U +/* Field Value: VSCALER4_CLKEN__FULL, Clock for vscaler4 is without gating */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_DYNAMIC_VSCALER4_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_vscaler4_Status */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS ((uint32_t)(0xB2C)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_OFFSET ((uint32_t)(0x32C)) +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL_SHIFT 16U +/* Field Value: VSCALER4_SEL__STORE9, vscaler4 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE9 0x1U +/* Field Value: VSCALER4_SEL__EXTDST0, vscaler4 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST0 0x2U +/* Field Value: VSCALER4_SEL__EXTDST4, vscaler4 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST4 0x3U +/* Field Value: VSCALER4_SEL__EXTDST1, vscaler4 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST1 0x4U +/* Field Value: VSCALER4_SEL__EXTDST5, vscaler4 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__EXTDST5 0x5U +/* Field Value: VSCALER4_SEL__STORE4, vscaler4 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE4 0x6U +/* Field Value: VSCALER4_SEL__STORE5, vscaler4 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__STORE5 0x7U +/* Field Value: VSCALER4_SEL__DISABLE, vscaler4 module is not used */ +#define IMXDPUV1_PIXENGCFG_VSCALER4_STATUS_VSCALER4_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_matrix5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK ((uint32_t)(0xB40)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_OFFSET ((uint32_t)(0x340)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK_SHIFT 0U +/* Field Value: MATRIX5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: MATRIX5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: MATRIX5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKUNLOCK_MATRIX5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_matrix5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS ((uint32_t)(0xB44)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_OFFSET ((uint32_t)(0x344)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_MATRIX5_LOCKSTATUS_MATRIX5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_matrix5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC ((uint32_t)(0xB48)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_OFFSET ((uint32_t)(0x348)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL_SHIFT 0U +/* Field Value: MATRIX5_SRC_SEL__DISABLE, Unit matrix5 input port src is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL__DISABLE 0U +/* Field Value: MATRIX5_SRC_SEL__GAMMACOR5, Unit matrix5 input port src is + * connected to output of unit gammacor5 */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_SRC_SEL__GAMMACOR5 0x27U +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN_SHIFT 24U +/* Field Value: MATRIX5_CLKEN__DISABLE, Clock for matrix5 is disabled */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__DISABLE 0U +/* Field Value: MATRIX5_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__AUTOMATIC 0x1U +/* Field Value: MATRIX5_CLKEN__FULL, Clock for matrix5 is without gating */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_DYNAMIC_MATRIX5_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_matrix5_Status */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS ((uint32_t)(0xB4C)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_OFFSET ((uint32_t)(0x34C)) +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL_SHIFT 16U +/* Field Value: MATRIX5_SEL__STORE9, matrix5 module is used from store9 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE9 0x1U +/* Field Value: MATRIX5_SEL__EXTDST0, matrix5 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST0 0x2U +/* Field Value: MATRIX5_SEL__EXTDST4, matrix5 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST4 0x3U +/* Field Value: MATRIX5_SEL__EXTDST1, matrix5 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST1 0x4U +/* Field Value: MATRIX5_SEL__EXTDST5, matrix5 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__EXTDST5 0x5U +/* Field Value: MATRIX5_SEL__STORE4, matrix5 module is used from store4 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE4 0x6U +/* Field Value: MATRIX5_SEL__STORE5, matrix5 module is used from store5 processing + * path */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__STORE5 0x7U +/* Field Value: MATRIX5_SEL__DISABLE, matrix5 module is not used */ +#define IMXDPUV1_PIXENGCFG_MATRIX5_STATUS_MATRIX5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK ((uint32_t)(0xB60)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0x360)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK_SHIFT 0U +/* Field Value: HSCALER5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: HSCALER5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: HSCALER5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: HSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: HSCALER5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKUNLOCK_HSCALER5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS ((uint32_t)(0xB64)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x364)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_HSCALER5_LOCKSTATUS_HSCALER5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC ((uint32_t)(0xB68)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_OFFSET ((uint32_t)(0x368)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL_SHIFT 0U +/* Field Value: HSCALER5_SRC_SEL__DISABLE, Unit hscaler5 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__DISABLE 0U +/* Field Value: HSCALER5_SRC_SEL__EXTSRC5, Unit hscaler5 input port src is + * connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__EXTSRC5 0x16U +/* Field Value: HSCALER5_SRC_SEL__FETCHDECODE1, Unit hscaler5 input port src + * is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__FETCHDECODE1 0x1EU +/* Field Value: HSCALER5_SRC_SEL__FETCHDECODE3, Unit hscaler5 input port src + * is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__FETCHDECODE3 0x19U +/* Field Value: HSCALER5_SRC_SEL__MATRIX5, Unit hscaler5 input port src is + * connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__MATRIX5 0x28U +/* Field Value: HSCALER5_SRC_SEL__VSCALER5, Unit hscaler5 input port src is + * connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_SRC_SEL__VSCALER5 0x2AU +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN_SHIFT 24U +/* Field Value: HSCALER5_CLKEN__DISABLE, Clock for hscaler5 is disabled */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__DISABLE 0U +/* Field Value: HSCALER5_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__AUTOMATIC 0x1U +/* Field Value: HSCALER5_CLKEN__FULL, Clock for hscaler5 is without gating */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_DYNAMIC_HSCALER5_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_hscaler5_Status */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS ((uint32_t)(0xB6C)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_OFFSET ((uint32_t)(0x36C)) +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL_SHIFT 16U +/* Field Value: HSCALER5_SEL__STORE9, hscaler5 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE9 0x1U +/* Field Value: HSCALER5_SEL__EXTDST0, hscaler5 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST0 0x2U +/* Field Value: HSCALER5_SEL__EXTDST4, hscaler5 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST4 0x3U +/* Field Value: HSCALER5_SEL__EXTDST1, hscaler5 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST1 0x4U +/* Field Value: HSCALER5_SEL__EXTDST5, hscaler5 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__EXTDST5 0x5U +/* Field Value: HSCALER5_SEL__STORE4, hscaler5 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE4 0x6U +/* Field Value: HSCALER5_SEL__STORE5, hscaler5 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__STORE5 0x7U +/* Field Value: HSCALER5_SEL__DISABLE, hscaler5 module is not used */ +#define IMXDPUV1_PIXENGCFG_HSCALER5_STATUS_HSCALER5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK ((uint32_t)(0xB80)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0x380)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK_SHIFT 0U +/* Field Value: VSCALER5_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset counter + * value is 1. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: VSCALER5_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. + * Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: VSCALER5_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: VSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: VSCALER5_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKUNLOCK_VSCALER5_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_LockStatus */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS ((uint32_t)(0xB84)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x384)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_VSCALER5_LOCKSTATUS_VSCALER5_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_Dynamic */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC ((uint32_t)(0xB88)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_OFFSET ((uint32_t)(0x388)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL_SHIFT 0U +/* Field Value: VSCALER5_SRC_SEL__DISABLE, Unit vscaler5 input port src is + * disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__DISABLE 0U +/* Field Value: VSCALER5_SRC_SEL__EXTSRC5, Unit vscaler5 input port src is + * connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__EXTSRC5 0x16U +/* Field Value: VSCALER5_SRC_SEL__FETCHDECODE1, Unit vscaler5 input port src + * is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__FETCHDECODE1 0x1EU +/* Field Value: VSCALER5_SRC_SEL__FETCHDECODE3, Unit vscaler5 input port src + * is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__FETCHDECODE3 0x19U +/* Field Value: VSCALER5_SRC_SEL__HSCALER5, Unit vscaler5 input port src is + * connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__HSCALER5 0x29U +/* Field Value: VSCALER5_SRC_SEL__MATRIX5, Unit vscaler5 input port src is + * connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_SRC_SEL__MATRIX5 0x28U +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN_SHIFT 24U +/* Field Value: VSCALER5_CLKEN__DISABLE, Clock for vscaler5 is disabled */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__DISABLE 0U +/* Field Value: VSCALER5_CLKEN__AUTOMATIC, Clock is enabled if unit is used, + * frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__AUTOMATIC 0x1U +/* Field Value: VSCALER5_CLKEN__FULL, Clock for vscaler5 is without gating */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_DYNAMIC_VSCALER5_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_vscaler5_Status */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS ((uint32_t)(0xB8C)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_OFFSET ((uint32_t)(0x38C)) +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL_SHIFT 16U +/* Field Value: VSCALER5_SEL__STORE9, vscaler5 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE9 0x1U +/* Field Value: VSCALER5_SEL__EXTDST0, vscaler5 module is used from extdst0 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST0 0x2U +/* Field Value: VSCALER5_SEL__EXTDST4, vscaler5 module is used from extdst4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST4 0x3U +/* Field Value: VSCALER5_SEL__EXTDST1, vscaler5 module is used from extdst1 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST1 0x4U +/* Field Value: VSCALER5_SEL__EXTDST5, vscaler5 module is used from extdst5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__EXTDST5 0x5U +/* Field Value: VSCALER5_SEL__STORE4, vscaler5 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE4 0x6U +/* Field Value: VSCALER5_SEL__STORE5, vscaler5 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__STORE5 0x7U +/* Field Value: VSCALER5_SEL__DISABLE, vscaler5 module is not used */ +#define IMXDPUV1_PIXENGCFG_VSCALER5_STATUS_VSCALER5_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK ((uint32_t)(0xBA0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_OFFSET ((uint32_t)(0x3A0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND0_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND0_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND0_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND0_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND0_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKUNLOCK_LAYERBLEND0_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS ((uint32_t)(0xBA4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_OFFSET ((uint32_t)(0x3A4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_LOCKSTATUS_LAYERBLEND0_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC ((uint32_t)(0xBA8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_OFFSET ((uint32_t)(0x3A8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_RESET_VALUE 0x1001C0CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND0_PRIM_SEL__DISABLE, Unit layerblend0 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND0_PRIM_SEL__BLITBLEND9, Unit layerblend0 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME0, Unit layerblend0 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME1, Unit layerblend0 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME4, Unit layerblend0 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND0_PRIM_SEL__CONSTFRAME5, Unit layerblend0 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND0_PRIM_SEL__MATRIX4, Unit layerblend0 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND0_PRIM_SEL__HSCALER4, Unit layerblend0 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND0_PRIM_SEL__VSCALER4, Unit layerblend0 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND0_PRIM_SEL__EXTSRC4, Unit layerblend0 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND0_PRIM_SEL__MATRIX5, Unit layerblend0 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND0_PRIM_SEL__HSCALER5, Unit layerblend0 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND0_PRIM_SEL__VSCALER5, Unit layerblend0 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND0_PRIM_SEL__EXTSRC5, Unit layerblend0 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_PRIM_SEL__EXTSRC5 0x16U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND0_SEC_SEL__DISABLE, Unit layerblend0 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE2, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE3, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHWARP2, Unit layerblend0 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE0, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHDECODE1, Unit layerblend0 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND0_SEC_SEL__MATRIX4, Unit layerblend0 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND0_SEC_SEL__HSCALER4, Unit layerblend0 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND0_SEC_SEL__VSCALER4, Unit layerblend0 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND0_SEC_SEL__MATRIX5, Unit layerblend0 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND0_SEC_SEL__HSCALER5, Unit layerblend0 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND0_SEC_SEL__VSCALER5, Unit layerblend0 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHLAYER0, Unit layerblend0 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND0_SEC_SEL__FETCHLAYER1, Unit layerblend0 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND0_CLKEN__DISABLE, Clock for layerblend0 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND0_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND0_CLKEN__FULL, Clock for layerblend0 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_DYNAMIC_LAYERBLEND0_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend0_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS ((uint32_t)(0xBAC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_OFFSET ((uint32_t)(0x3AC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL_SHIFT 16U +/* Field Value: LAYERBLEND0_SEL__STORE9, layerblend0 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND0_SEL__EXTDST0, layerblend0 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND0_SEL__EXTDST4, layerblend0 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND0_SEL__EXTDST1, layerblend0 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND0_SEL__EXTDST5, layerblend0 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND0_SEL__STORE4, layerblend0 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND0_SEL__STORE5, layerblend0 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND0_SEL__DISABLE, layerblend0 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND0_STATUS_LAYERBLEND0_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK ((uint32_t)(0xBC0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_OFFSET ((uint32_t)(0x3C0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND1_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND1_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND1_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND1_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND1_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKUNLOCK_LAYERBLEND1_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS ((uint32_t)(0xBC4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_OFFSET ((uint32_t)(0x3C4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_LOCKSTATUS_LAYERBLEND1_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC ((uint32_t)(0xBC8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_OFFSET ((uint32_t)(0x3C8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_RESET_VALUE 0x1001E10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND1_PRIM_SEL__DISABLE, Unit layerblend1 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND1_PRIM_SEL__BLITBLEND9, Unit layerblend1 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME0, Unit layerblend1 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME1, Unit layerblend1 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME4, Unit layerblend1 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND1_PRIM_SEL__CONSTFRAME5, Unit layerblend1 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND1_PRIM_SEL__MATRIX4, Unit layerblend1 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND1_PRIM_SEL__HSCALER4, Unit layerblend1 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND1_PRIM_SEL__VSCALER4, Unit layerblend1 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND1_PRIM_SEL__EXTSRC4, Unit layerblend1 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND1_PRIM_SEL__MATRIX5, Unit layerblend1 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND1_PRIM_SEL__HSCALER5, Unit layerblend1 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND1_PRIM_SEL__VSCALER5, Unit layerblend1 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND1_PRIM_SEL__EXTSRC5, Unit layerblend1 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__EXTSRC5 0x16U +/* Field Value: LAYERBLEND1_PRIM_SEL__LAYERBLEND0, Unit layerblend1 input + * port prim is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_PRIM_SEL__LAYERBLEND0 0x2CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND1_SEC_SEL__DISABLE, Unit layerblend1 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE2, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE3, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHWARP2, Unit layerblend1 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE0, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHDECODE1, Unit layerblend1 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND1_SEC_SEL__MATRIX4, Unit layerblend1 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND1_SEC_SEL__HSCALER4, Unit layerblend1 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND1_SEC_SEL__VSCALER4, Unit layerblend1 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND1_SEC_SEL__MATRIX5, Unit layerblend1 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND1_SEC_SEL__HSCALER5, Unit layerblend1 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND1_SEC_SEL__VSCALER5, Unit layerblend1 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHLAYER0, Unit layerblend1 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND1_SEC_SEL__FETCHLAYER1, Unit layerblend1 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND1_CLKEN__DISABLE, Clock for layerblend1 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND1_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND1_CLKEN__FULL, Clock for layerblend1 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_DYNAMIC_LAYERBLEND1_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend1_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS ((uint32_t)(0xBCC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_OFFSET ((uint32_t)(0x3CC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL_SHIFT 16U +/* Field Value: LAYERBLEND1_SEL__STORE9, layerblend1 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND1_SEL__EXTDST0, layerblend1 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND1_SEL__EXTDST4, layerblend1 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND1_SEL__EXTDST1, layerblend1 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND1_SEL__EXTDST5, layerblend1 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND1_SEL__STORE4, layerblend1 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND1_SEL__STORE5, layerblend1 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND1_SEL__DISABLE, layerblend1 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND1_STATUS_LAYERBLEND1_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK ((uint32_t)(0xBE0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_OFFSET ((uint32_t)(0x3E0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND2_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND2_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND2_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND2_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND2_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKUNLOCK_LAYERBLEND2_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS ((uint32_t)(0xBE4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_OFFSET ((uint32_t)(0x3E4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_LOCKSTATUS_LAYERBLEND2_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC ((uint32_t)(0xBE8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_OFFSET ((uint32_t)(0x3E8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND2_PRIM_SEL__DISABLE, Unit layerblend2 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND2_PRIM_SEL__BLITBLEND9, Unit layerblend2 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME0, Unit layerblend2 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME1, Unit layerblend2 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME4, Unit layerblend2 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND2_PRIM_SEL__CONSTFRAME5, Unit layerblend2 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND2_PRIM_SEL__MATRIX4, Unit layerblend2 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND2_PRIM_SEL__HSCALER4, Unit layerblend2 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND2_PRIM_SEL__VSCALER4, Unit layerblend2 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND2_PRIM_SEL__EXTSRC4, Unit layerblend2 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND2_PRIM_SEL__MATRIX5, Unit layerblend2 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND2_PRIM_SEL__HSCALER5, Unit layerblend2 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND2_PRIM_SEL__VSCALER5, Unit layerblend2 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND2_PRIM_SEL__EXTSRC5, Unit layerblend2 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__EXTSRC5 0x16U +/* Field Value: LAYERBLEND2_PRIM_SEL__LAYERBLEND1, Unit layerblend2 input + * port prim is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__LAYERBLEND1 0x2DU +/* Field Value: LAYERBLEND2_PRIM_SEL__LAYERBLEND0, Unit layerblend2 input + * port prim is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_PRIM_SEL__LAYERBLEND0 0x2CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND2_SEC_SEL__DISABLE, Unit layerblend2 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE2, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE3, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHWARP2, Unit layerblend2 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE0, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHDECODE1, Unit layerblend2 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND2_SEC_SEL__MATRIX4, Unit layerblend2 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND2_SEC_SEL__HSCALER4, Unit layerblend2 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND2_SEC_SEL__VSCALER4, Unit layerblend2 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND2_SEC_SEL__MATRIX5, Unit layerblend2 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND2_SEC_SEL__HSCALER5, Unit layerblend2 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND2_SEC_SEL__VSCALER5, Unit layerblend2 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHLAYER0, Unit layerblend2 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND2_SEC_SEL__FETCHLAYER1, Unit layerblend2 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND2_CLKEN__DISABLE, Clock for layerblend2 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND2_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND2_CLKEN__FULL, Clock for layerblend2 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_DYNAMIC_LAYERBLEND2_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend2_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS ((uint32_t)(0xBEC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_OFFSET ((uint32_t)(0x3EC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL_SHIFT 16U +/* Field Value: LAYERBLEND2_SEL__STORE9, layerblend2 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND2_SEL__EXTDST0, layerblend2 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND2_SEL__EXTDST4, layerblend2 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND2_SEL__EXTDST1, layerblend2 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND2_SEL__EXTDST5, layerblend2 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND2_SEL__STORE4, layerblend2 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND2_SEL__STORE5, layerblend2 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND2_SEL__DISABLE, layerblend2 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND2_STATUS_LAYERBLEND2_SEL__DISABLE 0U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_LockUnlock */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK ((uint32_t)(0xC00)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK_SHIFT 0U +/* Field Value: LAYERBLEND3_LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. + * When the counter value is null, lock protection is active. Reset + * counter value is 1. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LAYERBLEND3_LOCKUNLOCK__UNLOCK_KEY, Increments the unlock + * counter. Max allowed value is 15. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LAYERBLEND3_LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LAYERBLEND3_LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege + * protection. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LAYERBLEND3_LOCKUNLOCK__FREEZE_KEY, Freezes current protection + * status. Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKUNLOCK_LAYERBLEND3_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_LockStatus */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS ((uint32_t)(0xC04)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_LOCKSTATUS_LAYERBLEND3_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_Dynamic */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC ((uint32_t)(0xC08)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_RESET_VALUE 0x1000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL_MASK 0x3FU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL_SHIFT 0U +/* Field Value: LAYERBLEND3_PRIM_SEL__DISABLE, Unit layerblend3 input port + * prim is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__DISABLE 0U +/* Field Value: LAYERBLEND3_PRIM_SEL__BLITBLEND9, Unit layerblend3 input port + * prim is connected to output of unit blitblend9 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__BLITBLEND9 0xAU +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME0, Unit layerblend3 input + * port prim is connected to output of unit constframe0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME0 0xCU +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME1, Unit layerblend3 input + * port prim is connected to output of unit constframe1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME1 0x10U +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME4, Unit layerblend3 input + * port prim is connected to output of unit constframe4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME4 0xEU +/* Field Value: LAYERBLEND3_PRIM_SEL__CONSTFRAME5, Unit layerblend3 input + * port prim is connected to output of unit constframe5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__CONSTFRAME5 0x12U +/* Field Value: LAYERBLEND3_PRIM_SEL__MATRIX4, Unit layerblend3 input port + * prim is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND3_PRIM_SEL__HSCALER4, Unit layerblend3 input port + * prim is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND3_PRIM_SEL__VSCALER4, Unit layerblend3 input port + * prim is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND3_PRIM_SEL__EXTSRC4, Unit layerblend3 input port + * prim is connected to output of unit extsrc4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__EXTSRC4 0x14U +/* Field Value: LAYERBLEND3_PRIM_SEL__MATRIX5, Unit layerblend3 input port + * prim is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND3_PRIM_SEL__HSCALER5, Unit layerblend3 input port + * prim is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND3_PRIM_SEL__VSCALER5, Unit layerblend3 input port + * prim is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND3_PRIM_SEL__EXTSRC5, Unit layerblend3 input port + * prim is connected to output of unit extsrc5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__EXTSRC5 0x16U +/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND2, Unit layerblend3 input + * port prim is connected to output of unit layerblend2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND2 0x2EU +/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND1, Unit layerblend3 input + * port prim is connected to output of unit layerblend1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND1 0x2DU +/* Field Value: LAYERBLEND3_PRIM_SEL__LAYERBLEND0, Unit layerblend3 input + * port prim is connected to output of unit layerblend0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_PRIM_SEL__LAYERBLEND0 0x2CU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL_MASK 0x3F00U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL_SHIFT 8U +/* Field Value: LAYERBLEND3_SEC_SEL__DISABLE, Unit layerblend3 input port + * sec is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__DISABLE 0U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE2, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE2 0x18U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE3, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode3 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE3 0x19U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHWARP2, Unit layerblend3 input port + * sec is connected to output of unit fetchwarp2 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHWARP2 0x1AU +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE0, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE0 0x1CU +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHDECODE1, Unit layerblend3 input + * port sec is connected to output of unit fetchdecode1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHDECODE1 0x1EU +/* Field Value: LAYERBLEND3_SEC_SEL__MATRIX4, Unit layerblend3 input port + * sec is connected to output of unit matrix4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__MATRIX4 0x23U +/* Field Value: LAYERBLEND3_SEC_SEL__HSCALER4, Unit layerblend3 input port + * sec is connected to output of unit hscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__HSCALER4 0x24U +/* Field Value: LAYERBLEND3_SEC_SEL__VSCALER4, Unit layerblend3 input port + * sec is connected to output of unit vscaler4 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__VSCALER4 0x25U +/* Field Value: LAYERBLEND3_SEC_SEL__MATRIX5, Unit layerblend3 input port + * sec is connected to output of unit matrix5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__MATRIX5 0x28U +/* Field Value: LAYERBLEND3_SEC_SEL__HSCALER5, Unit layerblend3 input port + * sec is connected to output of unit hscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__HSCALER5 0x29U +/* Field Value: LAYERBLEND3_SEC_SEL__VSCALER5, Unit layerblend3 input port + * sec is connected to output of unit vscaler5 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__VSCALER5 0x2AU +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHLAYER0, Unit layerblend3 input port + * sec is connected to output of unit fetchlayer0 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHLAYER0 0x20U +/* Field Value: LAYERBLEND3_SEC_SEL__FETCHLAYER1, Unit layerblend3 input port + * sec is connected to output of unit fetchlayer1 */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_SEC_SEL__FETCHLAYER1 0x21U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN_MASK 0x3000000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN_SHIFT 24U +/* Field Value: LAYERBLEND3_CLKEN__DISABLE, Clock for layerblend3 is disabled */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__DISABLE 0U +/* Field Value: LAYERBLEND3_CLKEN__AUTOMATIC, Clock is enabled if unit is + * used, frequency is defined by the register setting for this pipeline (see + * [endpoint_name]_Static register) */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__AUTOMATIC 0x1U +/* Field Value: LAYERBLEND3_CLKEN__FULL, Clock for layerblend3 is without + * gating */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_DYNAMIC_LAYERBLEND3_CLKEN__FULL 0x3U + +/* Register: IMXDPUV1_pixengcfg_layerblend3_Status */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS ((uint32_t)(0xC0C)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_RESET_VALUE 0U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_RESET_MASK 0xFFF8FFFFU +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL_MASK 0x70000U +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL_SHIFT 16U +/* Field Value: LAYERBLEND3_SEL__STORE9, layerblend3 module is used from store9 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE9 0x1U +/* Field Value: LAYERBLEND3_SEL__EXTDST0, layerblend3 module is used from + * extdst0 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST0 0x2U +/* Field Value: LAYERBLEND3_SEL__EXTDST4, layerblend3 module is used from + * extdst4 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST4 0x3U +/* Field Value: LAYERBLEND3_SEL__EXTDST1, layerblend3 module is used from + * extdst1 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST1 0x4U +/* Field Value: LAYERBLEND3_SEL__EXTDST5, layerblend3 module is used from + * extdst5 processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__EXTDST5 0x5U +/* Field Value: LAYERBLEND3_SEL__STORE4, layerblend3 module is used from store4 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE4 0x6U +/* Field Value: LAYERBLEND3_SEL__STORE5, layerblend3 module is used from store5 + * processing path */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__STORE5 0x7U +/* Field Value: LAYERBLEND3_SEL__DISABLE, layerblend3 module is not used */ +#define IMXDPUV1_PIXENGCFG_LAYERBLEND3_STATUS_LAYERBLEND3_SEL__DISABLE 0U + +/* Register: IMXDPUV1_FetchDecode9_LockUnlock */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK ((uint32_t)(0x1000)) +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHDECODE9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_FetchDecode9_LockStatus */ +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS ((uint32_t)(0x1004)) +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHDECODE9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode9_StaticControl */ +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL ((uint32_t)(0x1008)) +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_BurstBufferManagement */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x100C)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_FetchDecode9_RingBufStartAddr0 */ +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0 ((uint32_t)(0x1010)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_RingBufWrapAddr0 */ +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0 ((uint32_t)(0x1014)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_FrameProperties0 */ +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0 ((uint32_t)(0x1018)) +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_BaseAddress0 */ +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0 ((uint32_t)(0x101C)) +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1020)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1024)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ColorComponentBits0 */ +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0 ((uint32_t)(0x1028)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode9_ColorComponentShift0 */ +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x102C)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHDECODE9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode9_LayerOffset0 */ +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0 ((uint32_t)(0x1030)) +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1034)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x1038)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode9_ConstantColor0 */ +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0 ((uint32_t)(0x103C)) +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode9_LayerProperty0 */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0 ((uint32_t)(0x1040)) +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode9_FrameDimensions */ +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS ((uint32_t)(0x1044)) +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode9_FrameResampling */ +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING ((uint32_t)(0x1048)) +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHDECODE9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode9_DecodeControl */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL ((uint32_t)(0x104C)) +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression). */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U +/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length. */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_COMPRESSIONMODE__RL 0x3U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS_SHIFT 15U +/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U +/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format */ +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_FETCHDECODE9_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_FetchDecode9_SourceBufferLength */ +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH ((uint32_t)(0x1050)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_FETCHDECODE9_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_Control */ +#define IMXDPUV1_FETCHDECODE9_CONTROL ((uint32_t)(0x1054)) +#define IMXDPUV1_FETCHDECODE9_CONTROL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHDECODE9_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U +/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed + * samples (UV samples between Y samples). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U +/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned + * samples (UV samples at Y sample positions). */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHDECODE9_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHDECODE9_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHDECODE9_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHDECODE9_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_FetchDecode9_ControlTrigger */ +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER ((uint32_t)(0x1058)) +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_Start */ +#define IMXDPUV1_FETCHDECODE9_START ((uint32_t)(0x105C)) +#define IMXDPUV1_FETCHDECODE9_START_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHDECODE9_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE9_START_START_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_FetchType */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE ((uint32_t)(0x1060)) +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE9_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_FetchDecode9_DecoderStatus */ +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS ((uint32_t)(0x1064)) +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U +#define IMXDPUV1_FETCHDECODE9_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U + +/* Register: IMXDPUV1_FetchDecode9_ReadAddress0 */ +#define IMXDPUV1_FETCHDECODE9_READADDRESS0 ((uint32_t)(0x1068)) +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_READADDRESS0_READADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode9_BurstBufferProperties */ +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES ((uint32_t)(0x106C)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode9_Status */ +#define IMXDPUV1_FETCHDECODE9_STATUS ((uint32_t)(0x1070)) +#define IMXDPUV1_FETCHDECODE9_STATUS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHDECODE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE9_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHDECODE9_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_FetchDecode9_HiddenStatus */ +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS ((uint32_t)(0x1074)) +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode9_ColorPalette */ +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE ((uint32_t)(0x1400)) +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHDECODE9_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_LockUnlock */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK ((uint32_t)(0x1800)) +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHWARP9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetchwarp9_LockStatus */ +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS ((uint32_t)(0x1804)) +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp9_StaticControl */ +#define IMXDPUV1_FETCHWARP9_STATICCONTROL ((uint32_t)(0x1808)) +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_VALUE 0xFF000000U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_BurstBufferManagement */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x180C)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress0 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0 ((uint32_t)(0x1810)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1814)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1818)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits0 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0 ((uint32_t)(0x181C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift0 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x1820)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset0 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0 ((uint32_t)(0x1824)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1828)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x182C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor0 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0 ((uint32_t)(0x1830)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty0 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0 ((uint32_t)(0x1834)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress1 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1 ((uint32_t)(0x1838)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_BASEADDRESS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS1_BASEADDRESS1_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes1 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1 ((uint32_t)(0x183C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension1 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1 ((uint32_t)(0x1840)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits1 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1 ((uint32_t)(0x1844)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift1 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1 ((uint32_t)(0x1848)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset1 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1 ((uint32_t)(0x184C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset1 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1 ((uint32_t)(0x1850)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions1 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1 ((uint32_t)(0x1854)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor1 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1 ((uint32_t)(0x1858)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty1 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1 ((uint32_t)(0x185C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1_SHIFT 4U +/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U +/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHAMASKENABLE1_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHAMASKENABLE1_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHAMASKENABLE1_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHAMASKENABLE1_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U +/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress2 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2 ((uint32_t)(0x1860)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_BASEADDRESS2_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS2_BASEADDRESS2_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes2 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2 ((uint32_t)(0x1864)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension2 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2 ((uint32_t)(0x1868)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits2 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2 ((uint32_t)(0x186C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift2 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2 ((uint32_t)(0x1870)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset2 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2 ((uint32_t)(0x1874)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset2 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2 ((uint32_t)(0x1878)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions2 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2 ((uint32_t)(0x187C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor2 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2 ((uint32_t)(0x1880)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty2 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2 ((uint32_t)(0x1884)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2_SHIFT 4U +/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U +/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHAMASKENABLE2_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHAMASKENABLE2_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHAMASKENABLE2_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHAMASKENABLE2_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U +/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress3 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3 ((uint32_t)(0x1888)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_BASEADDRESS3_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS3_BASEADDRESS3_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes3 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3 ((uint32_t)(0x188C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension3 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3 ((uint32_t)(0x1890)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits3 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3 ((uint32_t)(0x1894)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift3 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3 ((uint32_t)(0x1898)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset3 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3 ((uint32_t)(0x189C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset3 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3 ((uint32_t)(0x18A0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions3 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3 ((uint32_t)(0x18A4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor3 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3 ((uint32_t)(0x18A8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty3 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3 ((uint32_t)(0x18AC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3_SHIFT 4U +/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U +/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHAMASKENABLE3_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHAMASKENABLE3_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHAMASKENABLE3_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHAMASKENABLE3_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U +/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress4 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4 ((uint32_t)(0x18B0)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_BASEADDRESS4_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS4_BASEADDRESS4_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes4 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4 ((uint32_t)(0x18B4)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension4 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4 ((uint32_t)(0x18B8)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits4 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4 ((uint32_t)(0x18BC)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift4 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4 ((uint32_t)(0x18C0)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset4 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4 ((uint32_t)(0x18C4)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset4 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4 ((uint32_t)(0x18C8)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions4 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4 ((uint32_t)(0x18CC)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor4 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4 ((uint32_t)(0x18D0)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty4 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4 ((uint32_t)(0x18D4)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4_SHIFT 4U +/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U +/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHAMASKENABLE4_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHAMASKENABLE4_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHAMASKENABLE4_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHAMASKENABLE4_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U +/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress5 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5 ((uint32_t)(0x18D8)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_BASEADDRESS5_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS5_BASEADDRESS5_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes5 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5 ((uint32_t)(0x18DC)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension5 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5 ((uint32_t)(0x18E0)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits5 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5 ((uint32_t)(0x18E4)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift5 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5 ((uint32_t)(0x18E8)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset5 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5 ((uint32_t)(0x18EC)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset5 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5 ((uint32_t)(0x18F0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions5 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5 ((uint32_t)(0x18F4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor5 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5 ((uint32_t)(0x18F8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty5 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5 ((uint32_t)(0x18FC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5_SHIFT 4U +/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U +/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHAMASKENABLE5_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHAMASKENABLE5_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHAMASKENABLE5_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHAMASKENABLE5_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U +/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress6 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6 ((uint32_t)(0x1900)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_BASEADDRESS6_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS6_BASEADDRESS6_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes6 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6 ((uint32_t)(0x1904)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension6 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6 ((uint32_t)(0x1908)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits6 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6 ((uint32_t)(0x190C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift6 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6 ((uint32_t)(0x1910)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset6 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6 ((uint32_t)(0x1914)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset6 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6 ((uint32_t)(0x1918)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions6 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6 ((uint32_t)(0x191C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor6 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6 ((uint32_t)(0x1920)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty6 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6 ((uint32_t)(0x1924)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6_SHIFT 4U +/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U +/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHAMASKENABLE6_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHAMASKENABLE6_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHAMASKENABLE6_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHAMASKENABLE6_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U +/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_BaseAddress7 */ +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7 ((uint32_t)(0x1928)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_BASEADDRESS7_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_BASEADDRESS7_BASEADDRESS7_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferAttributes7 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7 ((uint32_t)(0x192C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_SourceBufferDimension7 */ +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7 ((uint32_t)(0x1930)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentBits7 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7 ((uint32_t)(0x1934)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_ColorComponentShift7 */ +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7 ((uint32_t)(0x1938)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP9_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerOffset7 */ +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7 ((uint32_t)(0x193C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowOffset7 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7 ((uint32_t)(0x1940)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ClipWindowDimensions7 */ +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7 ((uint32_t)(0x1944)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp9_ConstantColor7 */ +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7 ((uint32_t)(0x1948)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_LayerProperty7 */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7 ((uint32_t)(0x194C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7_MASK 0x30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7_SHIFT 4U +/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U +/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHAMASKENABLE7_MASK 0x400U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHAMASKENABLE7_SHIFT 10U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHAMASKENABLE7_MASK 0x4000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHAMASKENABLE7_SHIFT 14U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U +/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_FrameDimensions */ +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS ((uint32_t)(0x1950)) +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp9_FrameResampling */ +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING ((uint32_t)(0x1954)) +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHWARP9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_WarpControl */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL ((uint32_t)(0x1958)) +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPBITSPERPIXEL_MASK 0x3FU +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPBITSPERPIXEL_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE_MASK 0x300U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE_SHIFT 8U +/* Field Value: WARPCOORDINATEMODE__PNT, x and y (sample points). */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__PNT 0U +/* Field Value: WARPCOORDINATEMODE__D_PNT, dx and dy (vectors between adjacent + * sample points). */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__D_PNT 0x1U +/* Field Value: WARPCOORDINATEMODE__DD_PNT, ddx and ddy (deltas between adjacent + * vectors). */ +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPCOORDINATEMODE__DD_PNT 0x2U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPSYMMETRICOFFSET_MASK 0x1000U +#define IMXDPUV1_FETCHWARP9_WARPCONTROL_WARPSYMMETRICOFFSET_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp9_ArbStartX */ +#define IMXDPUV1_FETCHWARP9_ARBSTARTX ((uint32_t)(0x195C)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_ARBSTARTX_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTX_ARBSTARTX_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_ArbStartY */ +#define IMXDPUV1_FETCHWARP9_ARBSTARTY ((uint32_t)(0x1960)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_ARBSTARTY_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP9_ARBSTARTY_ARBSTARTY_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_ArbDelta */ +#define IMXDPUV1_FETCHWARP9_ARBDELTA ((uint32_t)(0x1964)) +#define IMXDPUV1_FETCHWARP9_ARBDELTA_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_FETCHWARP9_ARBDELTA_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXX_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXX_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXY_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAXY_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYX_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYX_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_ARBDELTA_ARBDELTAYY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_FIRPositions */ +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS ((uint32_t)(0x1968)) +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_RESET_VALUE 0xA965U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR0POSITION_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR0POSITION_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR1POSITION_MASK 0xF0U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR1POSITION_SHIFT 4U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR2POSITION_MASK 0xF00U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR2POSITION_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR3POSITION_MASK 0xF000U +#define IMXDPUV1_FETCHWARP9_FIRPOSITIONS_FIR3POSITION_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp9_FIRCoefficients */ +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS ((uint32_t)(0x196C)) +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR0COEFFICIENT_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR0COEFFICIENT_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR1COEFFICIENT_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR1COEFFICIENT_SHIFT 8U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR2COEFFICIENT_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR2COEFFICIENT_SHIFT 16U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR3COEFFICIENT_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP9_FIRCOEFFICIENTS_FIR3COEFFICIENT_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp9_Control */ +#define IMXDPUV1_FETCHWARP9_CONTROL ((uint32_t)(0x1970)) +#define IMXDPUV1_FETCHWARP9_CONTROL_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_FETCHWARP9_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHWARP9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHWARP9_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHWARP9_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHWARP9_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPCOLOR__LAYER 0x1U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPLAYER_MASK 0xE0000U +#define IMXDPUV1_FETCHWARP9_CONTROL_CLIPLAYER_SHIFT 17U +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE_MASK 0x700000U +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE_SHIFT 20U +/* Field Value: FILTERMODE__NEAREST, Chooses pixel closest to sample point */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__NEAREST 0U +/* Field Value: FILTERMODE__BILINEAR, Calculates result from 4 pixels closest + * to sample point */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__BILINEAR 0x1U +/* Field Value: FILTERMODE__FIR2, FIR mode with 2 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__FIR2 0x2U +/* Field Value: FILTERMODE__FIR4, FIR mode with 4 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__FIR4 0x3U +/* Field Value: FILTERMODE__HOR_LINEAR, Calculates result from 2 pixels closest + * to the sample point and on the same line */ +#define IMXDPUV1_FETCHWARP9_CONTROL_FILTERMODE__HOR_LINEAR 0x4U + +/* Register: IMXDPUV1_fetchwarp9_TriggerEnable */ +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE ((uint32_t)(0x1974)) +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_TRIGGERENABLE_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_ControlTrigger */ +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER ((uint32_t)(0x1978)) +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_Start */ +#define IMXDPUV1_FETCHWARP9_START ((uint32_t)(0x197C)) +#define IMXDPUV1_FETCHWARP9_START_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_FETCHWARP9_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP9_START_START_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp9_FetchType */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE ((uint32_t)(0x1980)) +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP9_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetchwarp9_BurstBufferProperties */ +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES ((uint32_t)(0x1984)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp9_Status */ +#define IMXDPUV1_FETCHWARP9_STATUS ((uint32_t)(0x1988)) +#define IMXDPUV1_FETCHWARP9_STATUS_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_FETCHWARP9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP9_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHWARP9_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_fetchwarp9_HiddenStatus */ +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS ((uint32_t)(0x198C)) +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco9_LockUnlock */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK ((uint32_t)(0x1C00)) +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco9_LockStatus */ +#define IMXDPUV1_FETCHECO9_LOCKSTATUS ((uint32_t)(0x1C04)) +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco9_StaticControl */ +#define IMXDPUV1_FETCHECO9_STATICCONTROL ((uint32_t)(0x1C08)) +#define IMXDPUV1_FETCHECO9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x1C0C)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco9_BaseAddress0 */ +#define IMXDPUV1_FETCHECO9_BASEADDRESS0 ((uint32_t)(0x1C10)) +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco9_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x1C14)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x1C18)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO9_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0 ((uint32_t)(0x1C1C)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco9_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0 ((uint32_t)(0x1C20)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO9_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco9_LayerOffset0 */ +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0 ((uint32_t)(0x1C24)) +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO9_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0 ((uint32_t)(0x1C28)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x1C2C)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO9_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco9_ConstantColor0 */ +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0 ((uint32_t)(0x1C30)) +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO9_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco9_LayerProperty0 */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0 ((uint32_t)(0x1C34)) +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco9_FrameDimensions */ +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS ((uint32_t)(0x1C38)) +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO9_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco9_FrameResampling */ +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING ((uint32_t)(0x1C3C)) +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO9_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco9_Control */ +#define IMXDPUV1_FETCHECO9_CONTROL ((uint32_t)(0x1C40)) +#define IMXDPUV1_FETCHECO9_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO9_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO9_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO9_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO9_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco9_ControlTrigger */ +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER ((uint32_t)(0x1C44)) +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO9_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco9_Start */ +#define IMXDPUV1_FETCHECO9_START ((uint32_t)(0x1C48)) +#define IMXDPUV1_FETCHECO9_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO9_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO9_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco9_FetchType */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE ((uint32_t)(0x1C4C)) +#define IMXDPUV1_FETCHECO9_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO9_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO9_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco9_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES ((uint32_t)(0x1C50)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO9_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco9_HiddenStatus */ +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS ((uint32_t)(0x1C54)) +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO9_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_rop9_LockUnlock */ +#define IMXDPUV1_ROP9_LOCKUNLOCK ((uint32_t)(0x2000)) +#define IMXDPUV1_ROP9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_ROP9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_ROP9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_ROP9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_rop9_LockStatus */ +#define IMXDPUV1_ROP9_LOCKSTATUS ((uint32_t)(0x2004)) +#define IMXDPUV1_ROP9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_ROP9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_ROP9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_ROP9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_ROP9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_ROP9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_ROP9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_ROP9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_rop9_StaticControl */ +#define IMXDPUV1_ROP9_STATICCONTROL ((uint32_t)(0x2008)) +#define IMXDPUV1_ROP9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_ROP9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_ROP9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_ROP9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_rop9_Control */ +#define IMXDPUV1_ROP9_CONTROL ((uint32_t)(0x200C)) +#define IMXDPUV1_ROP9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_ROP9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_ROP9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_ROP9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode */ +#define IMXDPUV1_ROP9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__OPERATION, Normal Operation */ +#define IMXDPUV1_ROP9_CONTROL_MODE__OPERATION 0x1U +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE_MASK 0x10U +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE_SHIFT 4U +/* Field Value: ALPHAMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE__ROP 0U +/* Field Value: ALPHAMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_ALPHAMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE_MASK 0x20U +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE_SHIFT 5U +/* Field Value: BLUEMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE__ROP 0U +/* Field Value: BLUEMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_BLUEMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_GREENMODE_MASK 0x40U +#define IMXDPUV1_ROP9_CONTROL_GREENMODE_SHIFT 6U +/* Field Value: GREENMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_GREENMODE__ROP 0U +/* Field Value: GREENMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_GREENMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_REDMODE_MASK 0x80U +#define IMXDPUV1_ROP9_CONTROL_REDMODE_SHIFT 7U +/* Field Value: REDMODE__ROP, Normal raster operation mode, using the operation + * index */ +#define IMXDPUV1_ROP9_CONTROL_REDMODE__ROP 0U +/* Field Value: REDMODE__ADD, Add mode, adds this component from all enabled + * inputs, clamps to 1 */ +#define IMXDPUV1_ROP9_CONTROL_REDMODE__ADD 0x1U +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2_MASK 0x100U +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2_SHIFT 8U +/* Field Value: PRIMDIV2__BYPASS, No change to input */ +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2__BYPASS 0U +/* Field Value: PRIMDIV2__DIVIDEBY2, Input is divided by two/shift to the + * right by one */ +#define IMXDPUV1_ROP9_CONTROL_PRIMDIV2__DIVIDEBY2 0x1U +#define IMXDPUV1_ROP9_CONTROL_SECDIV2_MASK 0x200U +#define IMXDPUV1_ROP9_CONTROL_SECDIV2_SHIFT 9U +/* Field Value: SECDIV2__BYPASS, No change to input */ +#define IMXDPUV1_ROP9_CONTROL_SECDIV2__BYPASS 0U +/* Field Value: SECDIV2__DIVIDEBY2, Input is divided by two/shift to the right + * by one */ +#define IMXDPUV1_ROP9_CONTROL_SECDIV2__DIVIDEBY2 0x1U +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2_MASK 0x400U +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2_SHIFT 10U +/* Field Value: TERTDIV2__BYPASS, No change to input */ +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2__BYPASS 0U +/* Field Value: TERTDIV2__DIVIDEBY2, Input is divided by two/shift to the + * right by one */ +#define IMXDPUV1_ROP9_CONTROL_TERTDIV2__DIVIDEBY2 0x1U + +/* Register: IMXDPUV1_rop9_RasterOperationIndices */ +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES ((uint32_t)(0x2010)) +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_RESET_VALUE 0U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXALPHA_MASK 0xFFU +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXALPHA_SHIFT 0U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXBLUE_MASK 0xFF00U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXBLUE_SHIFT 8U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXGREEN_MASK 0xFF0000U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXGREEN_SHIFT 16U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXRED_MASK 0xFF000000U +#define IMXDPUV1_ROP9_RASTEROPERATIONINDICES_OPINDEXRED_SHIFT 24U + +/* Register: IMXDPUV1_rop9_PrimControlWord */ +#define IMXDPUV1_ROP9_PRIMCONTROLWORD ((uint32_t)(0x2014)) +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_rop9_SecControlWord */ +#define IMXDPUV1_ROP9_SECCONTROLWORD ((uint32_t)(0x2018)) +#define IMXDPUV1_ROP9_SECCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_ROP9_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_ROP9_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_ROP9_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_rop9_TertControlWord */ +#define IMXDPUV1_ROP9_TERTCONTROLWORD ((uint32_t)(0x201C)) +#define IMXDPUV1_ROP9_TERTCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_ROP9_TERTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_ROP9_TERTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_ROP9_TERTCONTROLWORD_T_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_ROP9_TERTCONTROLWORD_T_VAL_SHIFT 0U + +/* Register: IMXDPUV1_clut9_LockUnlock */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK ((uint32_t)(0x2400)) +#define IMXDPUV1_CLUT9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CLUT9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CLUT9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_clut9_LockStatus */ +#define IMXDPUV1_CLUT9_LOCKSTATUS ((uint32_t)(0x2404)) +#define IMXDPUV1_CLUT9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CLUT9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CLUT9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CLUT9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CLUT9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CLUT9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CLUT9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_clut9_StaticControl */ +#define IMXDPUV1_CLUT9_STATICCONTROL ((uint32_t)(0x2408)) +#define IMXDPUV1_CLUT9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CLUT9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CLUT9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_clut9_UnshadowedControl */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL ((uint32_t)(0x240C)) +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK 0x1U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT 0U +/* Field Value: B_EN__DISABLE, disable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__DISABLE 0U +/* Field Value: B_EN__ENABLE, enable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_B_EN__ENABLE 0x1U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK 0x2U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT 1U +/* Field Value: G_EN__DISABLE, disable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__DISABLE 0U +/* Field Value: G_EN__ENABLE, enable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_G_EN__ENABLE 0x1U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK 0x4U +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT 2U +/* Field Value: R_EN__DISABLE, disable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__DISABLE 0U +/* Field Value: R_EN__ENABLE, enable */ +#define IMXDPUV1_CLUT9_UNSHADOWEDCONTROL_R_EN__ENABLE 0x1U + +/* Register: IMXDPUV1_clut9_Control */ +#define IMXDPUV1_CLUT9_CONTROL ((uint32_t)(0x2410)) +#define IMXDPUV1_CLUT9_CONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CLUT9_CONTROL_RESET_VALUE 0x800U +#define IMXDPUV1_CLUT9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_CLUT9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, module in neutral mode, input data is bypassed + * to the output */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__LUT, module in color lookup mode (LUT holds a 10bit + * color value for CLut derivate and 8bit color value for CLutL derivate + * for each input color) */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__LUT 0x1U +/* Field Value: MODE__INDEX_10BIT, module in 10bit color index table mode + * (LUT holds a 3x10bit color value for derivate CLut and 3x8bit color value + * for CLUTL derivate, indexed with the red input color) */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__INDEX_10BIT 0x2U +/* Field Value: MODE__INDEX_RGBA, module in RGBA color index table mode (LUT + * holds a 3x8bit color value and a 6bit alpha value for CLut derivate + * and 3x6bit color value and 6bit alpha value for CLutL derivate, indexed + * with the red input color) */ +#define IMXDPUV1_CLUT9_CONTROL_MODE__INDEX_RGBA 0x3U +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT_MASK 0x10U +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT_SHIFT 4U +/* Field Value: COL_8BIT__DISABLE, color is 10bit output */ +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT__DISABLE 0U +/* Field Value: COL_8BIT__ENABLE, color is 8bit output (dithering of internal + * 10bit value) */ +#define IMXDPUV1_CLUT9_CONTROL_COL_8BIT__ENABLE 0x1U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK_MASK 0x20U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK_SHIFT 5U +/* Field Value: ALPHAMASK__DISABLE, Alpha mask mode disabled */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK__DISABLE 0U +/* Field Value: ALPHAMASK__ENABLE, Alpha mask mode enabled */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAMASK__ENABLE 0x1U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT_MASK 0x40U +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT_SHIFT 6U +/* Field Value: ALPHAINVERT__NORMAL, Disable computation for alpha smaller + * than 128 */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT__NORMAL 0U +/* Field Value: ALPHAINVERT__INVERT, Disable computation for alpha greater + * than or equal to 128 */ +#define IMXDPUV1_CLUT9_CONTROL_ALPHAINVERT__INVERT 0x1U +#define IMXDPUV1_CLUT9_CONTROL_IDX_BITS_MASK 0xF00U +#define IMXDPUV1_CLUT9_CONTROL_IDX_BITS_SHIFT 8U + +/* Register: IMXDPUV1_clut9_Status */ +#define IMXDPUV1_CLUT9_STATUS ((uint32_t)(0x2414)) +#define IMXDPUV1_CLUT9_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CLUT9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_STATUS_WRITE_TIMEOUT_MASK 0x1U +#define IMXDPUV1_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT 0U +#define IMXDPUV1_CLUT9_STATUS_READ_TIMEOUT_MASK 0x10U +#define IMXDPUV1_CLUT9_STATUS_READ_TIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_clut9_LastControlWord */ +#define IMXDPUV1_CLUT9_LASTCONTROLWORD ((uint32_t)(0x2418)) +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_clut9_LUT */ +#define IMXDPUV1_CLUT9_LUT ((uint32_t)(0x2800)) +#define IMXDPUV1_CLUT9_LUT_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CLUT9_LUT_RESET_VALUE 0U +#define IMXDPUV1_CLUT9_LUT_RESET_MASK 0xC0000000U +#define IMXDPUV1_CLUT9_LUT_BLUE_MASK 0x3FFU +#define IMXDPUV1_CLUT9_LUT_BLUE_SHIFT 0U +#define IMXDPUV1_CLUT9_LUT_GREEN_MASK 0xFFC00U +#define IMXDPUV1_CLUT9_LUT_GREEN_SHIFT 10U +#define IMXDPUV1_CLUT9_LUT_RED_MASK 0x3FF00000U +#define IMXDPUV1_CLUT9_LUT_RED_SHIFT 20U + +/* Register: IMXDPUV1_matrix9_LockUnlock */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK ((uint32_t)(0x2C00)) +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix9_LockStatus */ +#define IMXDPUV1_MATRIX9_LOCKSTATUS ((uint32_t)(0x2C04)) +#define IMXDPUV1_MATRIX9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix9_StaticControl */ +#define IMXDPUV1_MATRIX9_STATICCONTROL ((uint32_t)(0x2C08)) +#define IMXDPUV1_MATRIX9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix9_Control */ +#define IMXDPUV1_MATRIX9_CONTROL ((uint32_t)(0x2C0C)) +#define IMXDPUV1_MATRIX9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX9_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX9_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix9_Red0 */ +#define IMXDPUV1_MATRIX9_RED0 ((uint32_t)(0x2C10)) +#define IMXDPUV1_MATRIX9_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX9_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX9_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX9_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Red1 */ +#define IMXDPUV1_MATRIX9_RED1 ((uint32_t)(0x2C14)) +#define IMXDPUV1_MATRIX9_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX9_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX9_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Green0 */ +#define IMXDPUV1_MATRIX9_GREEN0 ((uint32_t)(0x2C18)) +#define IMXDPUV1_MATRIX9_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX9_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX9_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX9_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Green1 */ +#define IMXDPUV1_MATRIX9_GREEN1 ((uint32_t)(0x2C1C)) +#define IMXDPUV1_MATRIX9_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX9_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX9_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Blue0 */ +#define IMXDPUV1_MATRIX9_BLUE0 ((uint32_t)(0x2C20)) +#define IMXDPUV1_MATRIX9_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX9_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX9_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Blue1 */ +#define IMXDPUV1_MATRIX9_BLUE1 ((uint32_t)(0x2C24)) +#define IMXDPUV1_MATRIX9_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX9_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX9_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX9_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Alpha0 */ +#define IMXDPUV1_MATRIX9_ALPHA0 ((uint32_t)(0x2C28)) +#define IMXDPUV1_MATRIX9_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX9_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX9_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_Alpha1 */ +#define IMXDPUV1_MATRIX9_ALPHA1 ((uint32_t)(0x2C2C)) +#define IMXDPUV1_MATRIX9_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX9_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX9_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX9_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_OffsetVector0 */ +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0 ((uint32_t)(0x2C30)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_OffsetVector1 */ +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1 ((uint32_t)(0x2C34)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX9_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix9_LastControlWord */ +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD ((uint32_t)(0x2C38)) +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_LockUnlock */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK ((uint32_t)(0x3000)) +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_HSCALER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_hscaler9_LockStatus */ +#define IMXDPUV1_HSCALER9_LOCKSTATUS ((uint32_t)(0x3004)) +#define IMXDPUV1_HSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_HSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_HSCALER9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_hscaler9_StaticControl */ +#define IMXDPUV1_HSCALER9_STATICCONTROL ((uint32_t)(0x3008)) +#define IMXDPUV1_HSCALER9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_HSCALER9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_HSCALER9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_Setup1 */ +#define IMXDPUV1_HSCALER9_SETUP1 ((uint32_t)(0x300C)) +#define IMXDPUV1_HSCALER9_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_HSCALER9_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_HSCALER9_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_HSCALER9_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_Setup2 */ +#define IMXDPUV1_HSCALER9_SETUP2 ((uint32_t)(0x3010)) +#define IMXDPUV1_HSCALER9_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_HSCALER9_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_HSCALER9_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_hscaler9_Control */ +#define IMXDPUV1_HSCALER9_CONTROL ((uint32_t)(0x3014)) +#define IMXDPUV1_HSCALER9_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_HSCALER9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_HSCALER9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_HSCALER9_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size) */ +#define IMXDPUV1_HSCALER9_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_HSCALER9_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_HSCALER9_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_HSCALER9_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_vscaler9_LockUnlock */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK ((uint32_t)(0x3400)) +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_VSCALER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_vscaler9_LockStatus */ +#define IMXDPUV1_VSCALER9_LOCKSTATUS ((uint32_t)(0x3404)) +#define IMXDPUV1_VSCALER9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_VSCALER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_VSCALER9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_vscaler9_StaticControl */ +#define IMXDPUV1_VSCALER9_STATICCONTROL ((uint32_t)(0x3408)) +#define IMXDPUV1_VSCALER9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_VSCALER9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_VSCALER9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup1 */ +#define IMXDPUV1_VSCALER9_SETUP1 ((uint32_t)(0x340C)) +#define IMXDPUV1_VSCALER9_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_VSCALER9_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_VSCALER9_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_VSCALER9_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup2 */ +#define IMXDPUV1_VSCALER9_SETUP2 ((uint32_t)(0x3410)) +#define IMXDPUV1_VSCALER9_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_VSCALER9_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup3 */ +#define IMXDPUV1_VSCALER9_SETUP3 ((uint32_t)(0x3414)) +#define IMXDPUV1_VSCALER9_SETUP3_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_VSCALER9_SETUP3_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP3_PHASE_OFFSET1_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP3_PHASE_OFFSET1_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup4 */ +#define IMXDPUV1_VSCALER9_SETUP4 ((uint32_t)(0x3418)) +#define IMXDPUV1_VSCALER9_SETUP4_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_VSCALER9_SETUP4_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP4_PHASE_OFFSET2_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP4_PHASE_OFFSET2_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Setup5 */ +#define IMXDPUV1_VSCALER9_SETUP5 ((uint32_t)(0x341C)) +#define IMXDPUV1_VSCALER9_SETUP5_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_VSCALER9_SETUP5_RESET_VALUE 0U +#define IMXDPUV1_VSCALER9_SETUP5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_SETUP5_PHASE_OFFSET3_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER9_SETUP5_PHASE_OFFSET3_SHIFT 0U + +/* Register: IMXDPUV1_vscaler9_Control */ +#define IMXDPUV1_VSCALER9_CONTROL ((uint32_t)(0x3420)) +#define IMXDPUV1_VSCALER9_CONTROL_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_VSCALER9_CONTROL_RESET_VALUE 0x2000U +#define IMXDPUV1_VSCALER9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_VSCALER9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_VSCALER9_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size). */ +#define IMXDPUV1_VSCALER9_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_VSCALER9_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE_MASK 0x3000U +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE_SHIFT 12U +/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__ALWAYS0 0U +/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__ALWAYS1 0x1U +/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input + * field polarity. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__INPUT 0x2U +/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting + * with 0 after reset. */ +#define IMXDPUV1_VSCALER9_CONTROL_FIELD_MODE__TOGGLE 0x3U +#define IMXDPUV1_VSCALER9_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_VSCALER9_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_filter9_LockUnlock */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK ((uint32_t)(0x3800)) +#define IMXDPUV1_FILTER9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FILTER9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FILTER9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_filter9_LockStatus */ +#define IMXDPUV1_FILTER9_LOCKSTATUS ((uint32_t)(0x3804)) +#define IMXDPUV1_FILTER9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FILTER9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FILTER9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FILTER9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FILTER9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FILTER9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FILTER9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_filter9_StaticControl */ +#define IMXDPUV1_FILTER9_STATICCONTROL ((uint32_t)(0x3808)) +#define IMXDPUV1_FILTER9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FILTER9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FILTER9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_filter9_Control */ +#define IMXDPUV1_FILTER9_CONTROL ((uint32_t)(0x380C)) +#define IMXDPUV1_FILTER9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FILTER9_CONTROL_RESET_VALUE 0x5500U +#define IMXDPUV1_FILTER9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_FILTER9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the filter, all + * other settings are ignored. */ +#define IMXDPUV1_FILTER9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Filter is active. */ +#define IMXDPUV1_FILTER9_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE_MASK 0x30U +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE_SHIFT 4U +/* Field Value: TILE_MODE__PAD, Samples outside the frame are padded with + * the last valid border pixels. */ +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__PAD 0U +/* Field Value: TILE_MODE__ZERO, Samples outside the frame are treated as + * zero pixel value. */ +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__ZERO 0x1U +/* Field Value: TILE_MODE__PAD_ZERO, Applies tile mode PAD to RGB channels + * and tile mode ZERO to alpha channel. */ +#define IMXDPUV1_FILTER9_CONTROL_TILE_MODE__PAD_ZERO 0x2U +#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE_MASK 0xFFFF00U +#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__FIR_5X5, FIR filter 5x5 window. */ +#define IMXDPUV1_FILTER9_CONTROL_FILTER_MODE__FIR_5X5 0x55U +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT_MASK 0x30000000U +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT_SHIFT 28U +/* Field Value: BUFFER_FORMAT__RGB888, RGB888 format. Alpha is not filtered + * but set to constant value 255. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGB888 0U +/* Field Value: BUFFER_FORMAT__RGBA5658, RGBA5658 format. Alpha is filtered. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA5658 0x1U +/* Field Value: BUFFER_FORMAT__RGBA8888, RGBA8888 format. Alpha is filtered. + * The filter window is limited to 5x4. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA8888 0x2U +/* Field Value: BUFFER_FORMAT__RGBA1010108, RGBA10.10.10.8 format. Alpha is + * filtered. The filter window is limited to 5x3. */ +#define IMXDPUV1_FILTER9_CONTROL_BUFFER_FORMAT__RGBA1010108 0x3U + +/* Register: IMXDPUV1_filter9_FIR_control */ +#define IMXDPUV1_FILTER9_FIR_CONTROL ((uint32_t)(0x3810)) +#define IMXDPUV1_FILTER9_FIR_CONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FILTER9_FIR_CONTROL_RESET_VALUE 0xEU +#define IMXDPUV1_FILTER9_FIR_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_COMPONENT_SELECT_MASK 0xFU +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_COMPONENT_SELECT_SHIFT 0U +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_EXPONENT_MASK 0xF00U +#define IMXDPUV1_FILTER9_FIR_CONTROL_FIR_EXPONENT_SHIFT 8U + +/* Register: IMXDPUV1_filter9_Coefficients0 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS0 ((uint32_t)(0x3814)) +#define IMXDPUV1_FILTER9_COEFFICIENTS0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FILTER9_COEFFICIENTS0_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF0_0_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF0_0_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF1_0_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF1_0_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF2_0_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF2_0_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF3_0_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS0_COEFF3_0_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients1 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS1 ((uint32_t)(0x3818)) +#define IMXDPUV1_FILTER9_COEFFICIENTS1_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FILTER9_COEFFICIENTS1_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF4_0_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF4_0_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF0_1_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF0_1_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF1_1_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF1_1_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF2_1_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS1_COEFF2_1_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients2 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS2 ((uint32_t)(0x381C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS2_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS2_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF3_1_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF3_1_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF4_1_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF4_1_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF0_2_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF0_2_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF1_2_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS2_COEFF1_2_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients3 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS3 ((uint32_t)(0x3820)) +#define IMXDPUV1_FILTER9_COEFFICIENTS3_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FILTER9_COEFFICIENTS3_RESET_VALUE 0x1U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF2_2_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF2_2_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF3_2_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF3_2_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF4_2_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF4_2_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF0_3_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS3_COEFF0_3_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients4 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS4 ((uint32_t)(0x3824)) +#define IMXDPUV1_FILTER9_COEFFICIENTS4_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FILTER9_COEFFICIENTS4_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF1_3_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF1_3_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF2_3_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF2_3_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF3_3_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF3_3_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF4_3_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS4_COEFF4_3_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients5 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS5 ((uint32_t)(0x3828)) +#define IMXDPUV1_FILTER9_COEFFICIENTS5_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FILTER9_COEFFICIENTS5_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF0_4_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF0_4_SHIFT 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF1_4_MASK 0xFF00U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF1_4_SHIFT 8U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF2_4_MASK 0xFF0000U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF2_4_SHIFT 16U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF3_4_MASK 0xFF000000U +#define IMXDPUV1_FILTER9_COEFFICIENTS5_COEFF3_4_SHIFT 24U + +/* Register: IMXDPUV1_filter9_Coefficients6 */ +#define IMXDPUV1_FILTER9_COEFFICIENTS6 ((uint32_t)(0x382C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS6_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FILTER9_COEFFICIENTS6_RESET_VALUE 0U +#define IMXDPUV1_FILTER9_COEFFICIENTS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS6_COEFF4_4_MASK 0xFFU +#define IMXDPUV1_FILTER9_COEFFICIENTS6_COEFF4_4_SHIFT 0U + +/* Register: IMXDPUV1_blitblend9_LockUnlock */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK ((uint32_t)(0x3C00)) +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_BLITBLEND9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_blitblend9_LockStatus */ +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS ((uint32_t)(0x3C04)) +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_BLITBLEND9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_blitblend9_StaticControl */ +#define IMXDPUV1_BLITBLEND9_STATICCONTROL ((uint32_t)(0x3C08)) +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_blitblend9_Control */ +#define IMXDPUV1_BLITBLEND9_CONTROL ((uint32_t)(0x3C0C)) +#define IMXDPUV1_BLITBLEND9_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_BLITBLEND9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode, only route pixels and commands + * from primary input to output */ +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__OPERATION, Normal Operation */ +#define IMXDPUV1_BLITBLEND9_CONTROL_MODE__OPERATION 0x1U + +/* Register: IMXDPUV1_blitblend9_NeutralBorder */ +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER ((uint32_t)(0x3C10)) +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE_MASK 0x1U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE_SHIFT 0U +/* Field Value: NEUTRALBORDERMODE__PRIMARY, Bypasses primary pixel */ +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE__PRIMARY 0U +/* Field Value: NEUTRALBORDERMODE__SECONDARY, Bypasses secondary pixel */ +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERMODE__SECONDARY 0x1U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERLEFT_MASK 0x700U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERLEFT_SHIFT 8U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERRIGHT_MASK 0x7000U +#define IMXDPUV1_BLITBLEND9_NEUTRALBORDER_NEUTRALBORDERRIGHT_SHIFT 12U + +/* Register: IMXDPUV1_blitblend9_ConstantColor */ +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR ((uint32_t)(0x3C14)) +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_BLITBLEND9_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_blitblend9_ColorRedBlendFunction */ +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION ((uint32_t)(0x3C18)) +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDSRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORREDBLENDFUNCTION_BLENDFUNCCOLORREDDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_ColorGreenBlendFunction */ +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION ((uint32_t)(0x3C1C)) +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENSRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORGREENBLENDFUNCTION_BLENDFUNCCOLORGREENDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_ColorBlueBlendFunction */ +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION ((uint32_t)(0x3C20)) +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUESRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_COLORBLUEBLENDFUNCTION_BLENDFUNCCOLORBLUEDST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_AlphaBlendFunction */ +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION ((uint32_t)(0x3C24)) +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_RESET_VALUE 0x3000300U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHASRC__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ZERO 0U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE 0x1U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_COLOR 0x300U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_SRC_COLOR 0x301U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_ALPHA 0x302U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_SRC_ALPHA 0x303U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_DST_ALPHA 0x304U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_DST_ALPHA 0x305U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_DST_COLOR 0x306U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_DST_COLOR 0x307U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_SRC_ALPHA_SATURATE 0x308U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_CONSTANT_COLOR 0x8001U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_CONSTANT_COLOR 0x8002U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_CONSTANT_ALPHA 0x8003U +#define IMXDPUV1_BLITBLEND9_ALPHABLENDFUNCTION_BLENDFUNCALPHADST__GL_ONE_MINUS_CONSTANT_ALPHA 0x8004U + +/* Register: IMXDPUV1_blitblend9_BlendMode1 */ +#define IMXDPUV1_BLITBLEND9_BLENDMODE1 ((uint32_t)(0x3C28)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_RESET_VALUE 0x80068006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORRED__VG_BLEND_ADDITIVE 0x2009U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE1_BLENDMODECOLORGREEN__VG_BLEND_ADDITIVE 0x2009U + +/* Register: IMXDPUV1_blitblend9_BlendMode2 */ +#define IMXDPUV1_BLITBLEND9_BLENDMODE2 ((uint32_t)(0x3C2C)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_RESET_VALUE 0x80068006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE_MASK 0xFFFFU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODECOLORBLUE__VG_BLEND_ADDITIVE 0x2009U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA_MASK 0xFFFF0000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA_SHIFT 16U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_ADD 0x8006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_MIN 0x8007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_MAX 0x8008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_SUBTRACT 0x800AU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__GL_FUNC_REVERSE_SUBTRACT 0x800BU +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC 0x2000U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC_OVER 0x2001U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DST_OVER 0x2002U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SRC_IN 0x2003U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DST_IN 0x2004U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_MULTIPLY 0x2005U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_SCREEN 0x2006U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_DARKEN 0x2007U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_LIGHTEN 0x2008U +#define IMXDPUV1_BLITBLEND9_BLENDMODE2_BLENDMODEALPHA__VG_BLEND_ADDITIVE 0x2009U + +/* Register: IMXDPUV1_blitblend9_DirectSetup */ +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP ((uint32_t)(0x3C30)) +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_COLORDEBUG_MASK 0x3FFU +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_COLORDEBUG_SHIFT 0U +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_ALPHADEBUG_MASK 0x3FF0000U +#define IMXDPUV1_BLITBLEND9_DIRECTSETUP_ALPHADEBUG_SHIFT 16U + +/* Register: IMXDPUV1_blitblend9_PrimControlWord */ +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD ((uint32_t)(0x3C34)) +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_blitblend9_SecControlWord */ +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD ((uint32_t)(0x3C38)) +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_store9_LockUnlock */ +#define IMXDPUV1_STORE9_LOCKUNLOCK ((uint32_t)(0x4000)) +#define IMXDPUV1_STORE9_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_STORE9_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_STORE9_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_STORE9_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_store9_LockStatus */ +#define IMXDPUV1_STORE9_LOCKSTATUS ((uint32_t)(0x4004)) +#define IMXDPUV1_STORE9_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_STORE9_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_STORE9_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_STORE9_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_STORE9_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_STORE9_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_STORE9_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_store9_StaticControl */ +#define IMXDPUV1_STORE9_STATICCONTROL ((uint32_t)(0x4008)) +#define IMXDPUV1_STORE9_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_STORE9_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_STORE9_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_STORE9_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0x100U +#define IMXDPUV1_STORE9_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 8U + +/* Register: IMXDPUV1_store9_BurstBufferManagement */ +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT ((uint32_t)(0x400C)) +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x400U +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_STORE9_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U + +/* Register: IMXDPUV1_store9_RingBufStartAddr */ +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR ((uint32_t)(0x4010)) +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RESET_VALUE 0U +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RINGBUFSTARTADDR_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFSTARTADDR_RINGBUFSTARTADDR_SHIFT 0U + +/* Register: IMXDPUV1_store9_RingBufWrapAddr */ +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR ((uint32_t)(0x4014)) +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RESET_VALUE 0U +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RINGBUFWRAPADDR_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_RINGBUFWRAPADDR_RINGBUFWRAPADDR_SHIFT 0U + +/* Register: IMXDPUV1_store9_BaseAddress */ +#define IMXDPUV1_STORE9_BASEADDRESS ((uint32_t)(0x4018)) +#define IMXDPUV1_STORE9_BASEADDRESS_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_STORE9_BASEADDRESS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_BASEADDRESS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_BASEADDRESS_BASEADDRESS_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_BASEADDRESS_BASEADDRESS_SHIFT 0U + +/* Register: IMXDPUV1_store9_DestinationBufferAttributes */ +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES ((uint32_t)(0x401C)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_RESET_VALUE 0x200004FFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE_MASK 0x1FFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_STRIDE_SHIFT 0U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL_MASK 0x7F000000U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERATTRIBUTES_BITSPERPIXEL_SHIFT 24U + +/* Register: IMXDPUV1_store9_DestinationBufferDimension */ +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION ((uint32_t)(0x4020)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINEWIDTH_SHIFT 0U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT_MASK 0x3FFF0000U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERDIMENSION_LINECOUNT_SHIFT 16U + +/* Register: IMXDPUV1_store9_FrameOffset */ +#define IMXDPUV1_STORE9_FRAMEOFFSET ((uint32_t)(0x4024)) +#define IMXDPUV1_STORE9_FRAMEOFFSET_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_STORE9_FRAMEOFFSET_RESET_VALUE 0U +#define IMXDPUV1_STORE9_FRAMEOFFSET_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET_MASK 0x7FFFU +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEXOFFSET_SHIFT 0U +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET_MASK 0x7FFF0000U +#define IMXDPUV1_STORE9_FRAMEOFFSET_FRAMEYOFFSET_SHIFT 16U + +/* Register: IMXDPUV1_store9_ColorComponentBits */ +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS ((uint32_t)(0x4028)) +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_RESET_VALUE 0x8080808U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSALPHA_MASK 0xFU +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSALPHA_SHIFT 0U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSBLUE_MASK 0xF00U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSBLUE_SHIFT 8U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSGREEN_MASK 0xF0000U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSGREEN_SHIFT 16U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSRED_MASK 0xF000000U +#define IMXDPUV1_STORE9_COLORCOMPONENTBITS_COMPONENTBITSRED_SHIFT 24U + +/* Register: IMXDPUV1_store9_ColorComponentShift */ +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT ((uint32_t)(0x402C)) +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_RESET_VALUE 0x18100800U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTALPHA_MASK 0x1FU +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTALPHA_SHIFT 0U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE_MASK 0x1F00U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTBLUE_SHIFT 8U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN_MASK 0x1F0000U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTGREEN_SHIFT 16U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED_MASK 0x1F000000U +#define IMXDPUV1_STORE9_COLORCOMPONENTSHIFT_COMPONENTSHIFTRED_SHIFT 24U + +/* Register: IMXDPUV1_store9_Control */ +#define IMXDPUV1_STORE9_CONTROL ((uint32_t)(0x4030)) +#define IMXDPUV1_STORE9_CONTROL_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_STORE9_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_STORE9_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_CONTROL_COLORDITHERENABLE_MASK 0x1U +#define IMXDPUV1_STORE9_CONTROL_COLORDITHERENABLE_SHIFT 0U +#define IMXDPUV1_STORE9_CONTROL_ALPHADITHERENABLE_MASK 0x2U +#define IMXDPUV1_STORE9_CONTROL_ALPHADITHERENABLE_SHIFT 1U +#define IMXDPUV1_STORE9_CONTROL_DITHEROFFSET_MASK 0xF0U +#define IMXDPUV1_STORE9_CONTROL_DITHEROFFSET_SHIFT 4U +#define IMXDPUV1_STORE9_CONTROL_GAMMAAPPLYENABLE_MASK 0x1000U +#define IMXDPUV1_STORE9_CONTROL_GAMMAAPPLYENABLE_SHIFT 12U +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE_MASK 0x30000U +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE_SHIFT 16U +/* Field Value: YUVCONVERSIONMODE__OFF, No conversion. Input data must be + * RGB. */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__OFF 0U +/* Field Value: YUVCONVERSIONMODE__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_STORE9_CONTROL_YUVCONVERSIONMODE__ITU709 0x3U +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE_MASK 0xC0000U +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE_SHIFT 18U +/* Field Value: RASTERMODE__NORMAL, RGBA or YUV 4:4:4 pixel buffer. */ +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__YUV422, [Store derivate only] Packed YUV 4:2:2 + * pixel buffer. Effect is that U samples are written for pixels with even + * and V samples for odd column index only. So BitsPerPixel must be set + * to the size that a pair of YU or YV has in memory (most typically 16 + * bits). All correlated widths and horizontal offsets must be even. */ +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__YUV422 0x1U +/* Field Value: RASTERMODE__ENCODE, [Store derivate only] RLAD compressed + * bit stream. */ +#define IMXDPUV1_STORE9_CONTROL_RASTERMODE__ENCODE 0x2U +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE_MASK 0x300000U +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE_SHIFT 20U +/* Field Value: YUV422DOWNSAMPLINGMODE__NEAREST, Nearest mode. Discards all + * odd samples, outputs even samples. */ +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__NEAREST 0U +/* Field Value: YUV422DOWNSAMPLINGMODE__COALIGNED, Linear coaligned mode. + * 3 nearest UV samples are combined in linear filter to get one output sample. */ +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__COALIGNED 0x1U +/* Field Value: YUV422DOWNSAMPLINGMODE__INTERSPERSED, Linear interspersed + * mode. 2 nearest UV samples are combined in linear filter to get one output + * sample. */ +#define IMXDPUV1_STORE9_CONTROL_YUV422DOWNSAMPLINGMODE__INTERSPERSED 0x2U + +/* Register: IMXDPUV1_store9_EncodeControl */ +#define IMXDPUV1_STORE9_ENCODECONTROL ((uint32_t)(0x4034)) +#define IMXDPUV1_STORE9_ENCODECONTROL_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_STORE9_ENCODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_STORE9_ENCODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE_MASK 0x1U +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_STORE9_ENCODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_STORE9_ENCODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_store9_DestinationBufferLength */ +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH ((uint32_t)(0x4038)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RLEWORDSMAX_MASK 0x1FFFFFFFU +#define IMXDPUV1_STORE9_DESTINATIONBUFFERLENGTH_RLEWORDSMAX_SHIFT 0U + +/* Register: IMXDPUV1_store9_Start */ +#define IMXDPUV1_STORE9_START ((uint32_t)(0x403C)) +#define IMXDPUV1_STORE9_START_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_STORE9_START_RESET_VALUE 0U +#define IMXDPUV1_STORE9_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_STORE9_START_START_MASK 0x1U +#define IMXDPUV1_STORE9_START_START_SHIFT 0U + +/* Register: IMXDPUV1_store9_EncoderStatus */ +#define IMXDPUV1_STORE9_ENCODERSTATUS ((uint32_t)(0x4040)) +#define IMXDPUV1_STORE9_ENCODERSTATUS_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_STORE9_ENCODERSTATUS_RESET_VALUE 0x1FFFFFFFU +#define IMXDPUV1_STORE9_ENCODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_ENCODERSTATUS_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_STORE9_ENCODERSTATUS_RLEWORDS_SHIFT 0U +#define IMXDPUV1_STORE9_ENCODERSTATUS_BUFFERTOOSMALL_MASK 0x80000000U +#define IMXDPUV1_STORE9_ENCODERSTATUS_BUFFERTOOSMALL_SHIFT 31U + +/* Register: IMXDPUV1_store9_WriteAddress */ +#define IMXDPUV1_STORE9_WRITEADDRESS ((uint32_t)(0x4044)) +#define IMXDPUV1_STORE9_WRITEADDRESS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_STORE9_WRITEADDRESS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_WRITEADDRESS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_WRITEADDRESS_WRITEADDRESS_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_WRITEADDRESS_WRITEADDRESS_SHIFT 0U + +/* Register: IMXDPUV1_store9_FrameProperties */ +#define IMXDPUV1_STORE9_FRAMEPROPERTIES ((uint32_t)(0x4048)) +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_FIELDID_MASK 0x1U +#define IMXDPUV1_STORE9_FRAMEPROPERTIES_FIELDID_SHIFT 0U + +/* Register: IMXDPUV1_store9_BurstBufferProperties */ +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES ((uint32_t)(0x404C)) +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE0FFU +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_MAXBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_STORE9_BURSTBUFFERPROPERTIES_MAXBURSTLENGTH_SHIFT 8U + +/* Register: IMXDPUV1_store9_LastControlWord */ +#define IMXDPUV1_STORE9_LASTCONTROLWORD ((uint32_t)(0x4050)) +#define IMXDPUV1_STORE9_LASTCONTROLWORD_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_STORE9_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_STORE9_LASTCONTROLWORD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_store9_PerfCounter */ +#define IMXDPUV1_STORE9_PERFCOUNTER ((uint32_t)(0x4054)) +#define IMXDPUV1_STORE9_PERFCOUNTER_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_STORE9_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_STORE9_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_STORE9_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_store9_Status */ +#define IMXDPUV1_STORE9_STATUS ((uint32_t)(0x4058)) +#define IMXDPUV1_STORE9_STATUS_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_STORE9_STATUS_RESET_VALUE 0U +#define IMXDPUV1_STORE9_STATUS_RESET_MASK 0xFFFFFF8EU +#define IMXDPUV1_STORE9_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_STORE9_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_STORE9_STATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_STORE9_STATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_STORE9_STATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_STORE9_STATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_STORE9_STATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_STORE9_STATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_STORE9_STATUS_PIXELBUSERROR_MASK 0x100U +#define IMXDPUV1_STORE9_STATUS_PIXELBUSERROR_SHIFT 8U +#define IMXDPUV1_STORE9_STATUS_ENCODEROVERFLOW_MASK 0x10000U +#define IMXDPUV1_STORE9_STATUS_ENCODEROVERFLOW_SHIFT 16U +#define IMXDPUV1_STORE9_STATUS_ENCODERSTALLPIXEL_MASK 0x20000U +#define IMXDPUV1_STORE9_STATUS_ENCODERSTALLPIXEL_SHIFT 17U + +/* Register: IMXDPUV1_constframe0_LockUnlock */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK ((uint32_t)(0x4400)) +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe0_LockStatus */ +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS ((uint32_t)(0x4404)) +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe0_StaticControl */ +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL ((uint32_t)(0x4408)) +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe0_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS ((uint32_t)(0x440C)) +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe0_ConstantColor */ +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR ((uint32_t)(0x4410)) +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME0_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe0_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER ((uint32_t)(0x4414)) +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe0_Start */ +#define IMXDPUV1_CONSTFRAME0_START ((uint32_t)(0x4418)) +#define IMXDPUV1_CONSTFRAME0_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME0_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME0_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe0_Status */ +#define IMXDPUV1_CONSTFRAME0_STATUS ((uint32_t)(0x441C)) +#define IMXDPUV1_CONSTFRAME0_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME0_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME0_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME0_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME0_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME0_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst0_LockUnlock */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK ((uint32_t)(0x4800)) +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst0_LockStatus */ +#define IMXDPUV1_EXTDST0_LOCKSTATUS ((uint32_t)(0x4804)) +#define IMXDPUV1_EXTDST0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst0_StaticControl */ +#define IMXDPUV1_EXTDST0_STATICCONTROL ((uint32_t)(0x4808)) +#define IMXDPUV1_EXTDST0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST0_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST0_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST0_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst0_Control */ +#define IMXDPUV1_EXTDST0_CONTROL ((uint32_t)(0x480C)) +#define IMXDPUV1_EXTDST0_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST0_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_SoftwareKick */ +#define IMXDPUV1_EXTDST0_SOFTWAREKICK ((uint32_t)(0x4810)) +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST0_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_Status */ +#define IMXDPUV1_EXTDST0_STATUS ((uint32_t)(0x4814)) +#define IMXDPUV1_EXTDST0_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST0_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_ControlWord */ +#define IMXDPUV1_EXTDST0_CONTROLWORD ((uint32_t)(0x4818)) +#define IMXDPUV1_EXTDST0_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST0_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst0_CurPixelCnt */ +#define IMXDPUV1_EXTDST0_CURPIXELCNT ((uint32_t)(0x481C)) +#define IMXDPUV1_EXTDST0_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST0_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst0_LastPixelCnt */ +#define IMXDPUV1_EXTDST0_LASTPIXELCNT ((uint32_t)(0x4820)) +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst0_PerfCounter */ +#define IMXDPUV1_EXTDST0_PERFCOUNTER ((uint32_t)(0x4824)) +#define IMXDPUV1_EXTDST0_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST0_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST0_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST0_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_LockUnlock */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK ((uint32_t)(0x4C00)) +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe4_LockStatus */ +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS ((uint32_t)(0x4C04)) +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe4_StaticControl */ +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL ((uint32_t)(0x4C08)) +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS ((uint32_t)(0x4C0C)) +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME4_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe4_ConstantColor */ +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR ((uint32_t)(0x4C10)) +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME4_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe4_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER ((uint32_t)(0x4C14)) +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_Start */ +#define IMXDPUV1_CONSTFRAME4_START ((uint32_t)(0x4C18)) +#define IMXDPUV1_CONSTFRAME4_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME4_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME4_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe4_Status */ +#define IMXDPUV1_CONSTFRAME4_STATUS ((uint32_t)(0x4C1C)) +#define IMXDPUV1_CONSTFRAME4_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME4_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME4_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME4_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME4_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME4_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst4_LockUnlock */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK ((uint32_t)(0x5000)) +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst4_LockStatus */ +#define IMXDPUV1_EXTDST4_LOCKSTATUS ((uint32_t)(0x5004)) +#define IMXDPUV1_EXTDST4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst4_StaticControl */ +#define IMXDPUV1_EXTDST4_STATICCONTROL ((uint32_t)(0x5008)) +#define IMXDPUV1_EXTDST4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST4_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST4_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST4_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST4_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST4_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst4_Control */ +#define IMXDPUV1_EXTDST4_CONTROL ((uint32_t)(0x500C)) +#define IMXDPUV1_EXTDST4_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST4_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST4_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_SoftwareKick */ +#define IMXDPUV1_EXTDST4_SOFTWAREKICK ((uint32_t)(0x5010)) +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST4_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_Status */ +#define IMXDPUV1_EXTDST4_STATUS ((uint32_t)(0x5014)) +#define IMXDPUV1_EXTDST4_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST4_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST4_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_ControlWord */ +#define IMXDPUV1_EXTDST4_CONTROLWORD ((uint32_t)(0x5018)) +#define IMXDPUV1_EXTDST4_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST4_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst4_CurPixelCnt */ +#define IMXDPUV1_EXTDST4_CURPIXELCNT ((uint32_t)(0x501C)) +#define IMXDPUV1_EXTDST4_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST4_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST4_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst4_LastPixelCnt */ +#define IMXDPUV1_EXTDST4_LASTPIXELCNT ((uint32_t)(0x5020)) +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST4_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst4_PerfCounter */ +#define IMXDPUV1_EXTDST4_PERFCOUNTER ((uint32_t)(0x5024)) +#define IMXDPUV1_EXTDST4_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST4_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST4_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST4_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_LockUnlock */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK ((uint32_t)(0x5400)) +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe1_LockStatus */ +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS ((uint32_t)(0x5404)) +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe1_StaticControl */ +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL ((uint32_t)(0x5408)) +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS ((uint32_t)(0x540C)) +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe1_ConstantColor */ +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR ((uint32_t)(0x5410)) +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME1_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe1_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER ((uint32_t)(0x5414)) +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_Start */ +#define IMXDPUV1_CONSTFRAME1_START ((uint32_t)(0x5418)) +#define IMXDPUV1_CONSTFRAME1_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME1_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME1_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe1_Status */ +#define IMXDPUV1_CONSTFRAME1_STATUS ((uint32_t)(0x541C)) +#define IMXDPUV1_CONSTFRAME1_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME1_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME1_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME1_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME1_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME1_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst1_LockUnlock */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK ((uint32_t)(0x5800)) +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst1_LockStatus */ +#define IMXDPUV1_EXTDST1_LOCKSTATUS ((uint32_t)(0x5804)) +#define IMXDPUV1_EXTDST1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst1_StaticControl */ +#define IMXDPUV1_EXTDST1_STATICCONTROL ((uint32_t)(0x5808)) +#define IMXDPUV1_EXTDST1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST1_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST1_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST1_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst1_Control */ +#define IMXDPUV1_EXTDST1_CONTROL ((uint32_t)(0x580C)) +#define IMXDPUV1_EXTDST1_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST1_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_SoftwareKick */ +#define IMXDPUV1_EXTDST1_SOFTWAREKICK ((uint32_t)(0x5810)) +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST1_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_Status */ +#define IMXDPUV1_EXTDST1_STATUS ((uint32_t)(0x5814)) +#define IMXDPUV1_EXTDST1_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST1_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_ControlWord */ +#define IMXDPUV1_EXTDST1_CONTROLWORD ((uint32_t)(0x5818)) +#define IMXDPUV1_EXTDST1_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST1_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst1_CurPixelCnt */ +#define IMXDPUV1_EXTDST1_CURPIXELCNT ((uint32_t)(0x581C)) +#define IMXDPUV1_EXTDST1_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST1_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST1_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst1_LastPixelCnt */ +#define IMXDPUV1_EXTDST1_LASTPIXELCNT ((uint32_t)(0x5820)) +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST1_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst1_PerfCounter */ +#define IMXDPUV1_EXTDST1_PERFCOUNTER ((uint32_t)(0x5824)) +#define IMXDPUV1_EXTDST1_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST1_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST1_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST1_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_LockUnlock */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK ((uint32_t)(0x5C00)) +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_CONSTFRAME5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_constframe5_LockStatus */ +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS ((uint32_t)(0x5C04)) +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_CONSTFRAME5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_constframe5_StaticControl */ +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL ((uint32_t)(0x5C08)) +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_FrameDimensions */ +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS ((uint32_t)(0x5C0C)) +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_CONSTFRAME5_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_constframe5_ConstantColor */ +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR ((uint32_t)(0x5C10)) +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTALPHA_MASK 0xFFU +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTALPHA_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTBLUE_MASK 0xFF00U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTBLUE_SHIFT 8U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTGREEN_MASK 0xFF0000U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTGREEN_SHIFT 16U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTRED_MASK 0xFF000000U +#define IMXDPUV1_CONSTFRAME5_CONSTANTCOLOR_CONSTANTRED_SHIFT 24U + +/* Register: IMXDPUV1_constframe5_ControlTrigger */ +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER ((uint32_t)(0x5C14)) +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_Start */ +#define IMXDPUV1_CONSTFRAME5_START ((uint32_t)(0x5C18)) +#define IMXDPUV1_CONSTFRAME5_START_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_CONSTFRAME5_START_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_CONSTFRAME5_START_START_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_START_START_SHIFT 0U + +/* Register: IMXDPUV1_constframe5_Status */ +#define IMXDPUV1_CONSTFRAME5_STATUS ((uint32_t)(0x5C1C)) +#define IMXDPUV1_CONSTFRAME5_STATUS_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_CONSTFRAME5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_CONSTFRAME5_STATUS_RESET_MASK 0xFFFFFFFCU +#define IMXDPUV1_CONSTFRAME5_STATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_CONSTFRAME5_STATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_CONSTFRAME5_STATUS_SHADOWSTATUS_MASK 0x2U +#define IMXDPUV1_CONSTFRAME5_STATUS_SHADOWSTATUS_SHIFT 1U + +/* Register: IMXDPUV1_extdst5_LockUnlock */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK ((uint32_t)(0x6000)) +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_EXTDST5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_extdst5_LockStatus */ +#define IMXDPUV1_EXTDST5_LOCKSTATUS ((uint32_t)(0x6004)) +#define IMXDPUV1_EXTDST5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_EXTDST5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_EXTDST5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_extdst5_StaticControl */ +#define IMXDPUV1_EXTDST5_STATICCONTROL ((uint32_t)(0x6008)) +#define IMXDPUV1_EXTDST5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_EXTDST5_STATICCONTROL_RESET_VALUE 0x100U +#define IMXDPUV1_EXTDST5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_EXTDST5_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE_MASK 0x100U +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE_SHIFT 8U +/* Field Value: KICK_MODE__SOFTWARE, kick generation by KICK field only */ +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE__SOFTWARE 0U +/* Field Value: KICK_MODE__EXTERNAL, kick signal from external allowed */ +#define IMXDPUV1_EXTDST5_STATICCONTROL_KICK_MODE__EXTERNAL 0x1U +#define IMXDPUV1_EXTDST5_STATICCONTROL_PERFCOUNTMODE_MASK 0x1000U +#define IMXDPUV1_EXTDST5_STATICCONTROL_PERFCOUNTMODE_SHIFT 12U + +/* Register: IMXDPUV1_extdst5_Control */ +#define IMXDPUV1_EXTDST5_CONTROL ((uint32_t)(0x600C)) +#define IMXDPUV1_EXTDST5_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_EXTDST5_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_CONTROL_GAMMAAPPLYENABLE_MASK 0x1U +#define IMXDPUV1_EXTDST5_CONTROL_GAMMAAPPLYENABLE_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_SoftwareKick */ +#define IMXDPUV1_EXTDST5_SOFTWAREKICK ((uint32_t)(0x6010)) +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_EXTDST5_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_Status */ +#define IMXDPUV1_EXTDST5_STATUS ((uint32_t)(0x6014)) +#define IMXDPUV1_EXTDST5_STATUS_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_EXTDST5_STATUS_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_STATUS_CNT_ERR_STS_MASK 0x1U +#define IMXDPUV1_EXTDST5_STATUS_CNT_ERR_STS_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_ControlWord */ +#define IMXDPUV1_EXTDST5_CONTROLWORD ((uint32_t)(0x6018)) +#define IMXDPUV1_EXTDST5_CONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_EXTDST5_CONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_CONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_CONTROLWORD_CW_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_CONTROLWORD_CW_VAL_SHIFT 0U + +/* Register: IMXDPUV1_extdst5_CurPixelCnt */ +#define IMXDPUV1_EXTDST5_CURPIXELCNT ((uint32_t)(0x601C)) +#define IMXDPUV1_EXTDST5_CURPIXELCNT_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_EXTDST5_CURPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST5_CURPIXELCNT_C_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst5_LastPixelCnt */ +#define IMXDPUV1_EXTDST5_LASTPIXELCNT ((uint32_t)(0x6020)) +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_RESET_MASK 0U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_XVAL_MASK 0xFFFFU +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_XVAL_SHIFT 0U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_YVAL_MASK 0xFFFF0000U +#define IMXDPUV1_EXTDST5_LASTPIXELCNT_L_YVAL_SHIFT 16U + +/* Register: IMXDPUV1_extdst5_PerfCounter */ +#define IMXDPUV1_EXTDST5_PERFCOUNTER ((uint32_t)(0x6024)) +#define IMXDPUV1_EXTDST5_PERFCOUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_EXTDST5_PERFCOUNTER_RESET_VALUE 0U +#define IMXDPUV1_EXTDST5_PERFCOUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_PERFCOUNTER_PERFRESULT_MASK 0xFFFFFFFFU +#define IMXDPUV1_EXTDST5_PERFCOUNTER_PERFRESULT_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_LockUnlock */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK ((uint32_t)(0x6400)) +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHWARP2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetchwarp2_LockStatus */ +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS ((uint32_t)(0x6404)) +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp2_StaticControl */ +#define IMXDPUV1_FETCHWARP2_STATICCONTROL ((uint32_t)(0x6408)) +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_VALUE 0xFF000000U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_BurstBufferManagement */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT ((uint32_t)(0x640C)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress0 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0 ((uint32_t)(0x6410)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x6414)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x6418)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits0 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0 ((uint32_t)(0x641C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift0 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0 ((uint32_t)(0x6420)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset0 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0 ((uint32_t)(0x6424)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0 ((uint32_t)(0x6428)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x642C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor0 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0 ((uint32_t)(0x6430)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty0 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0 ((uint32_t)(0x6434)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress1 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1 ((uint32_t)(0x6438)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_BASEADDRESS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS1_BASEADDRESS1_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes1 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1 ((uint32_t)(0x643C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension1 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1 ((uint32_t)(0x6440)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits1 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1 ((uint32_t)(0x6444)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift1 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1 ((uint32_t)(0x6448)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset1 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1 ((uint32_t)(0x644C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset1 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1 ((uint32_t)(0x6450)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions1 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1 ((uint32_t)(0x6454)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor1 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1 ((uint32_t)(0x6458)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty1 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1 ((uint32_t)(0x645C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1_SHIFT 4U +/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U +/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHAMASKENABLE1_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHAMASKENABLE1_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHAMASKENABLE1_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHAMASKENABLE1_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U +/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress2 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2 ((uint32_t)(0x6460)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_BASEADDRESS2_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS2_BASEADDRESS2_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes2 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2 ((uint32_t)(0x6464)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension2 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2 ((uint32_t)(0x6468)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits2 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2 ((uint32_t)(0x646C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift2 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2 ((uint32_t)(0x6470)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset2 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2 ((uint32_t)(0x6474)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset2 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2 ((uint32_t)(0x6478)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions2 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2 ((uint32_t)(0x647C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor2 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2 ((uint32_t)(0x6480)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty2 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2 ((uint32_t)(0x6484)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2_SHIFT 4U +/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U +/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHAMASKENABLE2_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHAMASKENABLE2_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHAMASKENABLE2_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHAMASKENABLE2_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U +/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress3 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3 ((uint32_t)(0x6488)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_BASEADDRESS3_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS3_BASEADDRESS3_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes3 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3 ((uint32_t)(0x648C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension3 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3 ((uint32_t)(0x6490)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits3 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3 ((uint32_t)(0x6494)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift3 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3 ((uint32_t)(0x6498)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset3 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3 ((uint32_t)(0x649C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset3 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3 ((uint32_t)(0x64A0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions3 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3 ((uint32_t)(0x64A4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor3 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3 ((uint32_t)(0x64A8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty3 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3 ((uint32_t)(0x64AC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3_SHIFT 4U +/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U +/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHAMASKENABLE3_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHAMASKENABLE3_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHAMASKENABLE3_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHAMASKENABLE3_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U +/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress4 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4 ((uint32_t)(0x64B0)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_BASEADDRESS4_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS4_BASEADDRESS4_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes4 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4 ((uint32_t)(0x64B4)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension4 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4 ((uint32_t)(0x64B8)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits4 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4 ((uint32_t)(0x64BC)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift4 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4 ((uint32_t)(0x64C0)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset4 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4 ((uint32_t)(0x64C4)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset4 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4 ((uint32_t)(0x64C8)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions4 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4 ((uint32_t)(0x64CC)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor4 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4 ((uint32_t)(0x64D0)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty4 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4 ((uint32_t)(0x64D4)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4_SHIFT 4U +/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U +/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHAMASKENABLE4_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHAMASKENABLE4_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHAMASKENABLE4_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHAMASKENABLE4_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U +/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress5 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5 ((uint32_t)(0x64D8)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_BASEADDRESS5_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS5_BASEADDRESS5_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes5 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5 ((uint32_t)(0x64DC)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension5 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5 ((uint32_t)(0x64E0)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits5 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5 ((uint32_t)(0x64E4)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift5 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5 ((uint32_t)(0x64E8)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset5 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5 ((uint32_t)(0x64EC)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset5 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5 ((uint32_t)(0x64F0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions5 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5 ((uint32_t)(0x64F4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor5 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5 ((uint32_t)(0x64F8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty5 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5 ((uint32_t)(0x64FC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5_SHIFT 4U +/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U +/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHAMASKENABLE5_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHAMASKENABLE5_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHAMASKENABLE5_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHAMASKENABLE5_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U +/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress6 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6 ((uint32_t)(0x6500)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_BASEADDRESS6_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS6_BASEADDRESS6_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes6 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6 ((uint32_t)(0x6504)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension6 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6 ((uint32_t)(0x6508)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits6 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6 ((uint32_t)(0x650C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift6 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6 ((uint32_t)(0x6510)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset6 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6 ((uint32_t)(0x6514)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset6 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6 ((uint32_t)(0x6518)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions6 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6 ((uint32_t)(0x651C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor6 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6 ((uint32_t)(0x6520)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty6 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6 ((uint32_t)(0x6524)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6_SHIFT 4U +/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U +/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHAMASKENABLE6_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHAMASKENABLE6_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHAMASKENABLE6_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHAMASKENABLE6_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U +/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_BaseAddress7 */ +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7 ((uint32_t)(0x6528)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_BASEADDRESS7_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_BASEADDRESS7_BASEADDRESS7_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferAttributes7 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7 ((uint32_t)(0x652C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_SourceBufferDimension7 */ +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7 ((uint32_t)(0x6530)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentBits7 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7 ((uint32_t)(0x6534)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_ColorComponentShift7 */ +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7 ((uint32_t)(0x6538)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U +#define IMXDPUV1_FETCHWARP2_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerOffset7 */ +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7 ((uint32_t)(0x653C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowOffset7 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7 ((uint32_t)(0x6540)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ClipWindowDimensions7 */ +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7 ((uint32_t)(0x6544)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchwarp2_ConstantColor7 */ +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7 ((uint32_t)(0x6548)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_LayerProperty7 */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7 ((uint32_t)(0x654C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7_MASK 0x30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7_SHIFT 4U +/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U +/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHAMASKENABLE7_MASK 0x400U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHAMASKENABLE7_SHIFT 10U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHAMASKENABLE7_MASK 0x4000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHAMASKENABLE7_SHIFT 14U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U +/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_FrameDimensions */ +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS ((uint32_t)(0x6550)) +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHWARP2_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetchwarp2_FrameResampling */ +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING ((uint32_t)(0x6554)) +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHWARP2_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_WarpControl */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL ((uint32_t)(0x6558)) +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPBITSPERPIXEL_MASK 0x3FU +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPBITSPERPIXEL_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE_MASK 0x300U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE_SHIFT 8U +/* Field Value: WARPCOORDINATEMODE__PNT, x and y (sample points). */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__PNT 0U +/* Field Value: WARPCOORDINATEMODE__D_PNT, dx and dy (vectors between adjacent + * sample points). */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__D_PNT 0x1U +/* Field Value: WARPCOORDINATEMODE__DD_PNT, ddx and ddy (deltas between adjacent + * vectors). */ +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPCOORDINATEMODE__DD_PNT 0x2U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPSYMMETRICOFFSET_MASK 0x1000U +#define IMXDPUV1_FETCHWARP2_WARPCONTROL_WARPSYMMETRICOFFSET_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp2_ArbStartX */ +#define IMXDPUV1_FETCHWARP2_ARBSTARTX ((uint32_t)(0x655C)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_ARBSTARTX_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTX_ARBSTARTX_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_ArbStartY */ +#define IMXDPUV1_FETCHWARP2_ARBSTARTY ((uint32_t)(0x6560)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_ARBSTARTY_MASK 0x1FFFFFU +#define IMXDPUV1_FETCHWARP2_ARBSTARTY_ARBSTARTY_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_ArbDelta */ +#define IMXDPUV1_FETCHWARP2_ARBDELTA ((uint32_t)(0x6564)) +#define IMXDPUV1_FETCHWARP2_ARBDELTA_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_FETCHWARP2_ARBDELTA_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXX_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXX_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXY_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAXY_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYX_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYX_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYY_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_ARBDELTA_ARBDELTAYY_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_FIRPositions */ +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS ((uint32_t)(0x6568)) +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_RESET_VALUE 0xA965U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR0POSITION_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR0POSITION_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR1POSITION_MASK 0xF0U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR1POSITION_SHIFT 4U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR2POSITION_MASK 0xF00U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR2POSITION_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR3POSITION_MASK 0xF000U +#define IMXDPUV1_FETCHWARP2_FIRPOSITIONS_FIR3POSITION_SHIFT 12U + +/* Register: IMXDPUV1_fetchwarp2_FIRCoefficients */ +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS ((uint32_t)(0x656C)) +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_RESET_VALUE 0x20U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR0COEFFICIENT_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR0COEFFICIENT_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR1COEFFICIENT_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR1COEFFICIENT_SHIFT 8U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR2COEFFICIENT_MASK 0xFF0000U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR2COEFFICIENT_SHIFT 16U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR3COEFFICIENT_MASK 0xFF000000U +#define IMXDPUV1_FETCHWARP2_FIRCOEFFICIENTS_FIR3COEFFICIENT_SHIFT 24U + +/* Register: IMXDPUV1_fetchwarp2_Control */ +#define IMXDPUV1_FETCHWARP2_CONTROL ((uint32_t)(0x6570)) +#define IMXDPUV1_FETCHWARP2_CONTROL_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_FETCHWARP2_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHWARP2_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHWARP2_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHWARP2_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHWARP2_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPCOLOR__LAYER 0x1U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPLAYER_MASK 0xE0000U +#define IMXDPUV1_FETCHWARP2_CONTROL_CLIPLAYER_SHIFT 17U +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE_MASK 0x700000U +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE_SHIFT 20U +/* Field Value: FILTERMODE__NEAREST, Chooses pixel closest to sample point */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__NEAREST 0U +/* Field Value: FILTERMODE__BILINEAR, Calculates result from 4 pixels closest + * to sample point */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__BILINEAR 0x1U +/* Field Value: FILTERMODE__FIR2, FIR mode with 2 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__FIR2 0x2U +/* Field Value: FILTERMODE__FIR4, FIR mode with 4 programmable pixel positions + * and coefficients */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__FIR4 0x3U +/* Field Value: FILTERMODE__HOR_LINEAR, Calculates result from 2 pixels closest + * to the sample point and on the same line */ +#define IMXDPUV1_FETCHWARP2_CONTROL_FILTERMODE__HOR_LINEAR 0x4U + +/* Register: IMXDPUV1_fetchwarp2_TriggerEnable */ +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE ((uint32_t)(0x6574)) +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_TRIGGERENABLE_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_ControlTrigger */ +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER ((uint32_t)(0x6578)) +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_Start */ +#define IMXDPUV1_FETCHWARP2_START ((uint32_t)(0x657C)) +#define IMXDPUV1_FETCHWARP2_START_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_FETCHWARP2_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHWARP2_START_START_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetchwarp2_FetchType */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE ((uint32_t)(0x6580)) +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHWARP2_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetchwarp2_BurstBufferProperties */ +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES ((uint32_t)(0x6584)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHWARP2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetchwarp2_Status */ +#define IMXDPUV1_FETCHWARP2_STATUS ((uint32_t)(0x6588)) +#define IMXDPUV1_FETCHWARP2_STATUS_OFFSET ((uint32_t)(0x188)) +#define IMXDPUV1_FETCHWARP2_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHWARP2_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHWARP2_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_fetchwarp2_HiddenStatus */ +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS ((uint32_t)(0x658C)) +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_OFFSET ((uint32_t)(0x18C)) +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHWARP2_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco2_LockUnlock */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK ((uint32_t)(0x6800)) +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco2_LockStatus */ +#define IMXDPUV1_FETCHECO2_LOCKSTATUS ((uint32_t)(0x6804)) +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO2_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco2_StaticControl */ +#define IMXDPUV1_FETCHECO2_STATICCONTROL ((uint32_t)(0x6808)) +#define IMXDPUV1_FETCHECO2_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO2_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO2_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT ((uint32_t)(0x680C)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco2_BaseAddress0 */ +#define IMXDPUV1_FETCHECO2_BASEADDRESS0 ((uint32_t)(0x6810)) +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco2_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x6814)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x6818)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO2_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0 ((uint32_t)(0x681C)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco2_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0 ((uint32_t)(0x6820)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO2_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco2_LayerOffset0 */ +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0 ((uint32_t)(0x6824)) +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO2_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0 ((uint32_t)(0x6828)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x682C)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO2_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco2_ConstantColor0 */ +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0 ((uint32_t)(0x6830)) +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO2_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco2_LayerProperty0 */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0 ((uint32_t)(0x6834)) +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco2_FrameDimensions */ +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS ((uint32_t)(0x6838)) +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO2_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco2_FrameResampling */ +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING ((uint32_t)(0x683C)) +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO2_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco2_Control */ +#define IMXDPUV1_FETCHECO2_CONTROL ((uint32_t)(0x6840)) +#define IMXDPUV1_FETCHECO2_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO2_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO2_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO2_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO2_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO2_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco2_ControlTrigger */ +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER ((uint32_t)(0x6844)) +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO2_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco2_Start */ +#define IMXDPUV1_FETCHECO2_START ((uint32_t)(0x6848)) +#define IMXDPUV1_FETCHECO2_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO2_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO2_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO2_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco2_FetchType */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE ((uint32_t)(0x684C)) +#define IMXDPUV1_FETCHECO2_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO2_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO2_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco2_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES ((uint32_t)(0x6850)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO2_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco2_HiddenStatus */ +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS ((uint32_t)(0x6854)) +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO2_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_LockUnlock */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK ((uint32_t)(0x6C00)) +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHDECODE0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_FetchDecode0_LockStatus */ +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS ((uint32_t)(0x6C04)) +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHDECODE0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_StaticControl */ +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL ((uint32_t)(0x6C08)) +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_BurstBufferManagement */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT ((uint32_t)(0x6C0C)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_FetchDecode0_RingBufStartAddr0 */ +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0 ((uint32_t)(0x6C10)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_RingBufWrapAddr0 */ +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0 ((uint32_t)(0x6C14)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_FrameProperties0 */ +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0 ((uint32_t)(0x6C18)) +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_BaseAddress0 */ +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0 ((uint32_t)(0x6C1C)) +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x6C20)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x6C24)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ColorComponentBits0 */ +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0 ((uint32_t)(0x6C28)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode0_ColorComponentShift0 */ +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0 ((uint32_t)(0x6C2C)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHDECODE0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode0_LayerOffset0 */ +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0 ((uint32_t)(0x6C30)) +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0 ((uint32_t)(0x6C34)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x6C38)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode0_ConstantColor0 */ +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0 ((uint32_t)(0x6C3C)) +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode0_LayerProperty0 */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0 ((uint32_t)(0x6C40)) +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode0_FrameDimensions */ +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS ((uint32_t)(0x6C44)) +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode0_FrameResampling */ +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING ((uint32_t)(0x6C48)) +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHDECODE0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode0_DecodeControl */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL ((uint32_t)(0x6C4C)) +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression). */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U +/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length. */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_COMPRESSIONMODE__RL 0x3U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS_SHIFT 15U +/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U +/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format */ +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_FETCHDECODE0_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_FetchDecode0_SourceBufferLength */ +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH ((uint32_t)(0x6C50)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_FETCHDECODE0_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_Control */ +#define IMXDPUV1_FETCHDECODE0_CONTROL ((uint32_t)(0x6C54)) +#define IMXDPUV1_FETCHDECODE0_CONTROL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHDECODE0_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U +/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed + * samples (UV samples between Y samples). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U +/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned + * samples (UV samples at Y sample positions). */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHDECODE0_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHDECODE0_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHDECODE0_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_FetchDecode0_ControlTrigger */ +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER ((uint32_t)(0x6C58)) +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_Start */ +#define IMXDPUV1_FETCHDECODE0_START ((uint32_t)(0x6C5C)) +#define IMXDPUV1_FETCHDECODE0_START_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHDECODE0_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE0_START_START_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_FetchType */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE ((uint32_t)(0x6C60)) +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE0_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_FetchDecode0_DecoderStatus */ +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS ((uint32_t)(0x6C64)) +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U +#define IMXDPUV1_FETCHDECODE0_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U + +/* Register: IMXDPUV1_FetchDecode0_ReadAddress0 */ +#define IMXDPUV1_FETCHDECODE0_READADDRESS0 ((uint32_t)(0x6C68)) +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_READADDRESS0_READADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode0_BurstBufferProperties */ +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES ((uint32_t)(0x6C6C)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_Status */ +#define IMXDPUV1_FETCHDECODE0_STATUS ((uint32_t)(0x6C70)) +#define IMXDPUV1_FETCHDECODE0_STATUS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHDECODE0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE0_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHDECODE0_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_FetchDecode0_HiddenStatus */ +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS ((uint32_t)(0x6C74)) +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode0_ColorPalette */ +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE ((uint32_t)(0x7000)) +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHDECODE0_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_LockUnlock */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK ((uint32_t)(0x7400)) +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco0_LockStatus */ +#define IMXDPUV1_FETCHECO0_LOCKSTATUS ((uint32_t)(0x7404)) +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco0_StaticControl */ +#define IMXDPUV1_FETCHECO0_STATICCONTROL ((uint32_t)(0x7408)) +#define IMXDPUV1_FETCHECO0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT ((uint32_t)(0x740C)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco0_BaseAddress0 */ +#define IMXDPUV1_FETCHECO0_BASEADDRESS0 ((uint32_t)(0x7410)) +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x7414)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x7418)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0 ((uint32_t)(0x741C)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco0_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0 ((uint32_t)(0x7420)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco0_LayerOffset0 */ +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0 ((uint32_t)(0x7424)) +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0 ((uint32_t)(0x7428)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x742C)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco0_ConstantColor0 */ +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0 ((uint32_t)(0x7430)) +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco0_LayerProperty0 */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0 ((uint32_t)(0x7434)) +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco0_FrameDimensions */ +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS ((uint32_t)(0x7438)) +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco0_FrameResampling */ +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING ((uint32_t)(0x743C)) +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco0_Control */ +#define IMXDPUV1_FETCHECO0_CONTROL ((uint32_t)(0x7440)) +#define IMXDPUV1_FETCHECO0_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO0_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO0_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO0_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO0_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco0_ControlTrigger */ +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER ((uint32_t)(0x7444)) +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_Start */ +#define IMXDPUV1_FETCHECO0_START ((uint32_t)(0x7448)) +#define IMXDPUV1_FETCHECO0_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO0_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO0_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco0_FetchType */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE ((uint32_t)(0x744C)) +#define IMXDPUV1_FETCHECO0_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO0_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO0_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco0_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES ((uint32_t)(0x7450)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco0_HiddenStatus */ +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS ((uint32_t)(0x7454)) +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_LockUnlock */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK ((uint32_t)(0x7800)) +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHDECODE1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_FetchDecode1_LockStatus */ +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS ((uint32_t)(0x7804)) +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHDECODE1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_StaticControl */ +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL ((uint32_t)(0x7808)) +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE1_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_BurstBufferManagement */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT ((uint32_t)(0x780C)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_FetchDecode1_RingBufStartAddr0 */ +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0 ((uint32_t)(0x7810)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFSTARTADDR0_RINGBUFSTARTADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_RingBufWrapAddr0 */ +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0 ((uint32_t)(0x7814)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_RINGBUFWRAPADDR0_RINGBUFWRAPADDR0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_FrameProperties0 */ +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0 ((uint32_t)(0x7818)) +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_FIELDID0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_FRAMEPROPERTIES0_FIELDID0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_BaseAddress0 */ +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0 ((uint32_t)(0x781C)) +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x7820)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x7824)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ColorComponentBits0 */ +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0 ((uint32_t)(0x7828)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode1_ColorComponentShift0 */ +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0 ((uint32_t)(0x782C)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHDECODE1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode1_LayerOffset0 */ +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0 ((uint32_t)(0x7830)) +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE1_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0 ((uint32_t)(0x7834)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x7838)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_FetchDecode1_ConstantColor0 */ +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0 ((uint32_t)(0x783C)) +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE1_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode1_LayerProperty0 */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0 ((uint32_t)(0x7840)) +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHAMASKENABLE0_MASK 0x400U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHAMASKENABLE0_SHIFT 10U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHAMASKENABLE0_MASK 0x4000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHAMASKENABLE0_SHIFT 14U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode1_FrameDimensions */ +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS ((uint32_t)(0x7844)) +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHDECODE1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_FetchDecode1_FrameResampling */ +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING ((uint32_t)(0x7848)) +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHDECODE1_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_FetchDecode1_DecodeControl */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL ((uint32_t)(0x784C)) +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RESET_VALUE 0x88880001U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE_MASK 0x3U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE_SHIFT 0U +/* Field Value: COMPRESSIONMODE__RLAD, Run-Length Adaptive Dithering (lossy + * compression). */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLAD 0U +/* Field Value: COMPRESSIONMODE__RLAD_UNIFORM, Run-Length Adaptive Dithering + * (lossy compression; uniform package size). */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLAD_UNIFORM 0x1U +/* Field Value: COMPRESSIONMODE__RLA, Run-Length Adaptive (lossless compression). */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RLA 0x2U +/* Field Value: COMPRESSIONMODE__RL, Standard Run-Length. */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_COMPRESSIONMODE__RL 0x3U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS_MASK 0x8000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS_SHIFT 15U +/* Field Value: RLADENDIANNESS__BIGENDIAN, Big endian format */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS__BIGENDIAN 0U +/* Field Value: RLADENDIANNESS__LITTLEENDIAN, Little endian format */ +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADENDIANNESS__LITTLEENDIAN 0x1U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSRED_MASK 0xF0000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSRED_SHIFT 16U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSGREEN_MASK 0xF00000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSGREEN_SHIFT 20U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSBLUE_MASK 0xF000000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSBLUE_SHIFT 24U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSALPHA_MASK 0xF0000000U +#define IMXDPUV1_FETCHDECODE1_DECODECONTROL_RLADCOMPBITSALPHA_SHIFT 28U + +/* Register: IMXDPUV1_FetchDecode1_SourceBufferLength */ +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH ((uint32_t)(0x7850)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWORDS_MASK 0x1FFFFFFFU +#define IMXDPUV1_FETCHDECODE1_SOURCEBUFFERLENGTH_RLEWORDS_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_Control */ +#define IMXDPUV1_FETCHDECODE1_CONTROL ((uint32_t)(0x7854)) +#define IMXDPUV1_FETCHDECODE1_CONTROL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHDECODE1_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE_MASK 0x7U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE_SHIFT 0U +/* Field Value: RASTERMODE__NORMAL, First sample at StartX/Y relative to origin. + * Hor/ver increments using DeltaX/Y and DeltaSwap setup. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__NORMAL 0U +/* Field Value: RASTERMODE__DECODE, [FetchDecode/FetchDecodeL only] Source + * buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver + * increments = (1,0)/(0,1). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__DECODE 0x1U +/* Field Value: RASTERMODE__ARBITRARY, [FetchPersp/Warp/Rot/RotL only] Arbitrary + * warping (filter is active). Coordinates are read from frame input + * port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY + * must be setup. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__ARBITRARY 0x2U +/* Field Value: RASTERMODE__PERSPECTIVE, [FetchPersp only] Affine/Perspective + * warping (filter is active). First sample at PerspStartX/Y/W. Hor/ver + * increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__PERSPECTIVE 0x3U +/* Field Value: RASTERMODE__YUV422, [FetchPersp/Decode only] Source buffer + * is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver increments + * = (1,0)/(0,1). All corellated window widths and horizontal offsets must + * be even. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__YUV422 0x4U +/* Field Value: RASTERMODE__AFFINE, [FetchRot/RotL only] Affine warping (filter + * is active). First sample at AffineStartX/Y. Hor/ver increments using + * AffineDeltaXX/XY/YX/YY. Cartesian coordinates. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_RASTERMODE__AFFINE 0x5U +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT_MASK 0x18U +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT_SHIFT 3U +/* Field Value: INPUTSELECT__INACTIVE, Not used. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__INACTIVE 0U +/* Field Value: INPUTSELECT__COMPPACK, Used for component packing (e.g. UV + * or source alpha buffer). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__COMPPACK 0x1U +/* Field Value: INPUTSELECT__ALPHAMASK, Used for RGB and alpha pre-multiply + * stage (mask alpha buffer). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__ALPHAMASK 0x2U +/* Field Value: INPUTSELECT__COORDINATE, Used for arbitrary warping (coordinate + * buffer). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_INPUTSELECT__COORDINATE 0x3U +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE_SHIFT 5U +/* Field Value: YUV422UPSAMPLINGMODE__REPLICATE, Replicate mode for interspersed + * samples (UV samples between Y samples). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE__REPLICATE 0U +/* Field Value: YUV422UPSAMPLINGMODE__INTERPOLATE, Interpolate mode for coaligned + * samples (UV samples at Y sample positions). */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_YUV422UPSAMPLINGMODE__INTERPOLATE 0x1U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHDECODE1_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHDECODE1_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHDECODE1_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHDECODE1_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_FetchDecode1_ControlTrigger */ +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER ((uint32_t)(0x7858)) +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_Start */ +#define IMXDPUV1_FETCHDECODE1_START ((uint32_t)(0x785C)) +#define IMXDPUV1_FETCHDECODE1_START_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHDECODE1_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHDECODE1_START_START_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_START_START_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_FetchType */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE ((uint32_t)(0x7860)) +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHDECODE1_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_FetchDecode1_DecoderStatus */ +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS ((uint32_t)(0x7864)) +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOSMALL_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOSMALL_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOLARGE_MASK 0x2U +#define IMXDPUV1_FETCHDECODE1_DECODERSTATUS_BUFFERTOOLARGE_SHIFT 1U + +/* Register: IMXDPUV1_FetchDecode1_ReadAddress0 */ +#define IMXDPUV1_FETCHDECODE1_READADDRESS0 ((uint32_t)(0x7868)) +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_READADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_READADDRESS0_READADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_FetchDecode1_BurstBufferProperties */ +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES ((uint32_t)(0x786C)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHDECODE1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_Status */ +#define IMXDPUV1_FETCHDECODE1_STATUS ((uint32_t)(0x7870)) +#define IMXDPUV1_FETCHDECODE1_STATUS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHDECODE1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHDECODE1_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHDECODE1_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_FetchDecode1_HiddenStatus */ +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS ((uint32_t)(0x7874)) +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHDECODE1_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_FetchDecode1_ColorPalette */ +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE ((uint32_t)(0x7C00)) +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHDECODE1_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_LockUnlock */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK ((uint32_t)(0x8000)) +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHECO1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetcheco1_LockStatus */ +#define IMXDPUV1_FETCHECO1_LOCKSTATUS ((uint32_t)(0x8004)) +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHECO1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco1_StaticControl */ +#define IMXDPUV1_FETCHECO1_STATICCONTROL ((uint32_t)(0x8008)) +#define IMXDPUV1_FETCHECO1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO1_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_BurstBufferManagement */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT ((uint32_t)(0x800C)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetcheco1_BaseAddress0 */ +#define IMXDPUV1_FETCHECO1_BASEADDRESS0 ((uint32_t)(0x8010)) +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x8014)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x8018)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO1_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ColorComponentBits0 */ +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0 ((uint32_t)(0x801C)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco1_ColorComponentShift0 */ +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0 ((uint32_t)(0x8020)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHECO1_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco1_LayerOffset0 */ +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0 ((uint32_t)(0x8024)) +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO1_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0 ((uint32_t)(0x8028)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x802C)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO1_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetcheco1_ConstantColor0 */ +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0 ((uint32_t)(0x8030)) +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHECO1_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco1_LayerProperty0 */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0 ((uint32_t)(0x8034)) +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_RESET_VALUE 0x80000000U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco1_FrameDimensions */ +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS ((uint32_t)(0x8038)) +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHECO1_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetcheco1_FrameResampling */ +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING ((uint32_t)(0x803C)) +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHECO1_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetcheco1_Control */ +#define IMXDPUV1_FETCHECO1_CONTROL ((uint32_t)(0x8040)) +#define IMXDPUV1_FETCHECO1_CONTROL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHECO1_CONTROL_RESET_VALUE 0x10000U +#define IMXDPUV1_FETCHECO1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHECO1_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHECO1_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHECO1_CONTROL_CLIPCOLOR__LAYER 0x1U + +/* Register: IMXDPUV1_fetcheco1_ControlTrigger */ +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER ((uint32_t)(0x8044)) +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHECO1_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_Start */ +#define IMXDPUV1_FETCHECO1_START ((uint32_t)(0x8048)) +#define IMXDPUV1_FETCHECO1_START_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHECO1_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHECO1_START_START_MASK 0x1U +#define IMXDPUV1_FETCHECO1_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetcheco1_FetchType */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE ((uint32_t)(0x804C)) +#define IMXDPUV1_FETCHECO1_FETCHTYPE_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHECO1_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHECO1_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetcheco1_BurstBufferProperties */ +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES ((uint32_t)(0x8050)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHECO1_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetcheco1_HiddenStatus */ +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS ((uint32_t)(0x8054)) +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHECO1_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_LockUnlock */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK ((uint32_t)(0x8400)) +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FETCHLAYER0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_fetchlayer0_LockStatus */ +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS ((uint32_t)(0x8404)) +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_StaticControl */ +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL ((uint32_t)(0x8408)) +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_RESET_VALUE 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_BASEADDRESSAUTOUPDATE_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_STATICCONTROL_SHDLDREQSTICKY_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_BurstBufferManagement */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT ((uint32_t)(0x840C)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_RESET_VALUE 0x404U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE_SHIFT 31U +/* Field Value: LINEMODE__DISPLAY, Mandatory setting for operation in the + * Display Controller. Works also for Blit Engine with marginal performance + * impact. */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE__DISPLAY 0U +/* Field Value: LINEMODE__BLIT, Recommended setting for operation in the Blit + * Engine. */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERMANAGEMENT_LINEMODE__BLIT 0x1U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress0 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0 ((uint32_t)(0x8410)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_BASEADDRESS0_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS0_BASEADDRESS0_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes0 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0 ((uint32_t)(0x8414)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_RESET_VALUE 0x2004FFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_STRIDE0_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_STRIDE0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES0_BITSPERPIXEL0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension0 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0 ((uint32_t)(0x8418)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINEWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINECOUNT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION0_LINECOUNT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits0 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0 ((uint32_t)(0x841C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_COMPONENTBITSRED0_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFORMAT0_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS0_ITUFORMAT0_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift0 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0 ((uint32_t)(0x8420)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT0_COMPONENTSHIFTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset0 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0 ((uint32_t)(0x8424)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET0_LAYERYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset0 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0 ((uint32_t)(0x8428)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWXOFFSET0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET0_CLIPWINDOWYOFFSET0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions0 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0 ((uint32_t)(0x842C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWWIDTH0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS0_CLIPWINDOWHEIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor0 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0 ((uint32_t)(0x8430)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTALPHA0_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTALPHA0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTBLUE0_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTBLUE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTGREEN0_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTGREEN0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTRED0_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR0_CONSTANTRED0_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty0 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0 ((uint32_t)(0x8434)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_VALUE 0x80000100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PALETTEENABLE0_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PALETTEENABLE0_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0_SHIFT 4U +/* Field Value: TILEMODE0__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE0__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE0__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_PAD 0x2U +/* Field Value: TILEMODE0__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_TILEMODE0__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHASRCENABLE0_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHASRCENABLE0_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHACONSTENABLE0_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHACONSTENABLE0_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHATRANSENABLE0_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_ALPHATRANSENABLE0_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHASRCENABLE0_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHASRCENABLE0_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHACONSTENABLE0_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_RGBALPHATRANSENABLE0_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PREMULCONSTRGB0_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_PREMULCONSTRGB0_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE0__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__OFF 0U +/* Field Value: YUVCONVERSIONMODE0__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE0__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE0__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_YUVCONVERSIONMODE0__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_GAMMAREMOVEENABLE0_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_CLIPWINDOWENABLE0_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_CLIPWINDOWENABLE0_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY0_SOURCEBUFFERENABLE0_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress1 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1 ((uint32_t)(0x8438)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_BASEADDRESS1_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS1_BASEADDRESS1_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes1 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1 ((uint32_t)(0x843C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_STRIDE1_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_STRIDE1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES1_BITSPERPIXEL1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension1 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1 ((uint32_t)(0x8440)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINEWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINEWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINECOUNT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION1_LINECOUNT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits1 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1 ((uint32_t)(0x8444)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSRED1_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_COMPONENTBITSRED1_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFORMAT1_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS1_ITUFORMAT1_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift1 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1 ((uint32_t)(0x8448)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT1_COMPONENTSHIFTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset1 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1 ((uint32_t)(0x844C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET1_LAYERYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset1 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1 ((uint32_t)(0x8450)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWXOFFSET1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET1_CLIPWINDOWYOFFSET1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions1 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1 ((uint32_t)(0x8454)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWWIDTH1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS1_CLIPWINDOWHEIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor1 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1 ((uint32_t)(0x8458)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTALPHA1_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTALPHA1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTBLUE1_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTBLUE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTGREEN1_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTGREEN1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTRED1_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR1_CONSTANTRED1_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty1 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1 ((uint32_t)(0x845C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PALETTEENABLE1_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PALETTEENABLE1_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1_SHIFT 4U +/* Field Value: TILEMODE1__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE1__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE1__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_PAD 0x2U +/* Field Value: TILEMODE1__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_TILEMODE1__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHASRCENABLE1_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHASRCENABLE1_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHACONSTENABLE1_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHACONSTENABLE1_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHATRANSENABLE1_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_ALPHATRANSENABLE1_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHASRCENABLE1_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHASRCENABLE1_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHACONSTENABLE1_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHACONSTENABLE1_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHATRANSENABLE1_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_RGBALPHATRANSENABLE1_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PREMULCONSTRGB1_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_PREMULCONSTRGB1_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE1__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__OFF 0U +/* Field Value: YUVCONVERSIONMODE1__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE1__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE1__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_YUVCONVERSIONMODE1__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_GAMMAREMOVEENABLE1_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_GAMMAREMOVEENABLE1_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_CLIPWINDOWENABLE1_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_CLIPWINDOWENABLE1_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_SOURCEBUFFERENABLE1_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY1_SOURCEBUFFERENABLE1_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress2 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2 ((uint32_t)(0x8460)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_BASEADDRESS2_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS2_BASEADDRESS2_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes2 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2 ((uint32_t)(0x8464)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_STRIDE2_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_STRIDE2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES2_BITSPERPIXEL2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension2 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2 ((uint32_t)(0x8468)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINEWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINEWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINECOUNT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION2_LINECOUNT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits2 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2 ((uint32_t)(0x846C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSRED2_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_COMPONENTBITSRED2_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFORMAT2_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS2_ITUFORMAT2_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift2 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2 ((uint32_t)(0x8470)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT2_COMPONENTSHIFTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset2 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2 ((uint32_t)(0x8474)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET2_LAYERYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset2 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2 ((uint32_t)(0x8478)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWXOFFSET2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET2_CLIPWINDOWYOFFSET2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions2 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2 ((uint32_t)(0x847C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWWIDTH2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS2_CLIPWINDOWHEIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor2 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2 ((uint32_t)(0x8480)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTALPHA2_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTALPHA2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTBLUE2_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTBLUE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTGREEN2_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTGREEN2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTRED2_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR2_CONSTANTRED2_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty2 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2 ((uint32_t)(0x8484)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PALETTEENABLE2_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PALETTEENABLE2_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2_SHIFT 4U +/* Field Value: TILEMODE2__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE2__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE2__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_PAD 0x2U +/* Field Value: TILEMODE2__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_TILEMODE2__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHASRCENABLE2_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHASRCENABLE2_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHACONSTENABLE2_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHACONSTENABLE2_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHATRANSENABLE2_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_ALPHATRANSENABLE2_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHASRCENABLE2_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHASRCENABLE2_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHACONSTENABLE2_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHACONSTENABLE2_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHATRANSENABLE2_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_RGBALPHATRANSENABLE2_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PREMULCONSTRGB2_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_PREMULCONSTRGB2_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE2__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__OFF 0U +/* Field Value: YUVCONVERSIONMODE2__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE2__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE2__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_YUVCONVERSIONMODE2__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_GAMMAREMOVEENABLE2_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_GAMMAREMOVEENABLE2_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_CLIPWINDOWENABLE2_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_CLIPWINDOWENABLE2_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_SOURCEBUFFERENABLE2_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY2_SOURCEBUFFERENABLE2_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress3 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3 ((uint32_t)(0x8488)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_BASEADDRESS3_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS3_BASEADDRESS3_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes3 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3 ((uint32_t)(0x848C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_STRIDE3_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_STRIDE3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES3_BITSPERPIXEL3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension3 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3 ((uint32_t)(0x8490)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINEWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINEWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINECOUNT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION3_LINECOUNT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits3 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3 ((uint32_t)(0x8494)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSRED3_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_COMPONENTBITSRED3_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFORMAT3_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS3_ITUFORMAT3_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift3 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3 ((uint32_t)(0x8498)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT3_COMPONENTSHIFTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset3 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3 ((uint32_t)(0x849C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET3_LAYERYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset3 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3 ((uint32_t)(0x84A0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWXOFFSET3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET3_CLIPWINDOWYOFFSET3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions3 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3 ((uint32_t)(0x84A4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWWIDTH3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS3_CLIPWINDOWHEIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor3 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3 ((uint32_t)(0x84A8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTALPHA3_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTALPHA3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTBLUE3_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTBLUE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTGREEN3_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTGREEN3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTRED3_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR3_CONSTANTRED3_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty3 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3 ((uint32_t)(0x84AC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PALETTEENABLE3_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PALETTEENABLE3_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3_SHIFT 4U +/* Field Value: TILEMODE3__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE3__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE3__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_PAD 0x2U +/* Field Value: TILEMODE3__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_TILEMODE3__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHASRCENABLE3_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHASRCENABLE3_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHACONSTENABLE3_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHACONSTENABLE3_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHATRANSENABLE3_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_ALPHATRANSENABLE3_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHASRCENABLE3_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHASRCENABLE3_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHACONSTENABLE3_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHACONSTENABLE3_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHATRANSENABLE3_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_RGBALPHATRANSENABLE3_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PREMULCONSTRGB3_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_PREMULCONSTRGB3_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE3__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__OFF 0U +/* Field Value: YUVCONVERSIONMODE3__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE3__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE3__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_YUVCONVERSIONMODE3__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_GAMMAREMOVEENABLE3_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_GAMMAREMOVEENABLE3_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_CLIPWINDOWENABLE3_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_CLIPWINDOWENABLE3_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_SOURCEBUFFERENABLE3_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY3_SOURCEBUFFERENABLE3_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress4 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4 ((uint32_t)(0x84B0)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_BASEADDRESS4_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS4_BASEADDRESS4_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes4 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4 ((uint32_t)(0x84B4)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_STRIDE4_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_STRIDE4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES4_BITSPERPIXEL4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension4 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4 ((uint32_t)(0x84B8)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINEWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINEWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINECOUNT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION4_LINECOUNT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits4 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4 ((uint32_t)(0x84BC)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSRED4_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_COMPONENTBITSRED4_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFORMAT4_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS4_ITUFORMAT4_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift4 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4 ((uint32_t)(0x84C0)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT4_COMPONENTSHIFTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset4 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4 ((uint32_t)(0x84C4)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET4_LAYERYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset4 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4 ((uint32_t)(0x84C8)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWXOFFSET4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET4_CLIPWINDOWYOFFSET4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions4 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4 ((uint32_t)(0x84CC)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWWIDTH4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS4_CLIPWINDOWHEIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor4 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4 ((uint32_t)(0x84D0)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTALPHA4_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTALPHA4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTBLUE4_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTBLUE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTGREEN4_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTGREEN4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTRED4_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR4_CONSTANTRED4_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty4 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4 ((uint32_t)(0x84D4)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PALETTEENABLE4_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PALETTEENABLE4_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4_SHIFT 4U +/* Field Value: TILEMODE4__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE4__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE4__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_PAD 0x2U +/* Field Value: TILEMODE4__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_TILEMODE4__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHASRCENABLE4_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHASRCENABLE4_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHACONSTENABLE4_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHACONSTENABLE4_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHATRANSENABLE4_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_ALPHATRANSENABLE4_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHASRCENABLE4_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHASRCENABLE4_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHACONSTENABLE4_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHACONSTENABLE4_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHATRANSENABLE4_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_RGBALPHATRANSENABLE4_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PREMULCONSTRGB4_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_PREMULCONSTRGB4_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE4__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__OFF 0U +/* Field Value: YUVCONVERSIONMODE4__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE4__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE4__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_YUVCONVERSIONMODE4__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_GAMMAREMOVEENABLE4_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_GAMMAREMOVEENABLE4_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_CLIPWINDOWENABLE4_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_CLIPWINDOWENABLE4_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_SOURCEBUFFERENABLE4_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY4_SOURCEBUFFERENABLE4_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress5 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5 ((uint32_t)(0x84D8)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_BASEADDRESS5_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS5_BASEADDRESS5_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes5 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5 ((uint32_t)(0x84DC)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_STRIDE5_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_STRIDE5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES5_BITSPERPIXEL5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension5 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5 ((uint32_t)(0x84E0)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINEWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINEWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINECOUNT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION5_LINECOUNT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits5 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5 ((uint32_t)(0x84E4)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSRED5_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_COMPONENTBITSRED5_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFORMAT5_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS5_ITUFORMAT5_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift5 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5 ((uint32_t)(0x84E8)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT5_COMPONENTSHIFTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset5 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5 ((uint32_t)(0x84EC)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET5_LAYERYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset5 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5 ((uint32_t)(0x84F0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWXOFFSET5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET5_CLIPWINDOWYOFFSET5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions5 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5 ((uint32_t)(0x84F4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWWIDTH5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS5_CLIPWINDOWHEIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor5 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5 ((uint32_t)(0x84F8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTALPHA5_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTALPHA5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTBLUE5_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTBLUE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTGREEN5_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTGREEN5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTRED5_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR5_CONSTANTRED5_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty5 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5 ((uint32_t)(0x84FC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PALETTEENABLE5_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PALETTEENABLE5_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5_SHIFT 4U +/* Field Value: TILEMODE5__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE5__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE5__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_PAD 0x2U +/* Field Value: TILEMODE5__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_TILEMODE5__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHASRCENABLE5_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHASRCENABLE5_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHACONSTENABLE5_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHACONSTENABLE5_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHATRANSENABLE5_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_ALPHATRANSENABLE5_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHASRCENABLE5_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHASRCENABLE5_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHACONSTENABLE5_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHACONSTENABLE5_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHATRANSENABLE5_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_RGBALPHATRANSENABLE5_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PREMULCONSTRGB5_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_PREMULCONSTRGB5_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE5__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__OFF 0U +/* Field Value: YUVCONVERSIONMODE5__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE5__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE5__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_YUVCONVERSIONMODE5__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_GAMMAREMOVEENABLE5_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_GAMMAREMOVEENABLE5_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_CLIPWINDOWENABLE5_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_CLIPWINDOWENABLE5_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_SOURCEBUFFERENABLE5_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY5_SOURCEBUFFERENABLE5_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress6 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6 ((uint32_t)(0x8500)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_BASEADDRESS6_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS6_BASEADDRESS6_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes6 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6 ((uint32_t)(0x8504)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_STRIDE6_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_STRIDE6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES6_BITSPERPIXEL6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension6 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6 ((uint32_t)(0x8508)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINEWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINEWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINECOUNT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION6_LINECOUNT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits6 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6 ((uint32_t)(0x850C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSRED6_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_COMPONENTBITSRED6_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFORMAT6_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS6_ITUFORMAT6_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift6 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6 ((uint32_t)(0x8510)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT6_COMPONENTSHIFTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset6 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6 ((uint32_t)(0x8514)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET6_LAYERYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset6 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6 ((uint32_t)(0x8518)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWXOFFSET6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET6_CLIPWINDOWYOFFSET6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions6 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6 ((uint32_t)(0x851C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWWIDTH6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS6_CLIPWINDOWHEIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor6 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6 ((uint32_t)(0x8520)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTALPHA6_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTALPHA6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTBLUE6_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTBLUE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTGREEN6_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTGREEN6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTRED6_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR6_CONSTANTRED6_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty6 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6 ((uint32_t)(0x8524)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PALETTEENABLE6_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PALETTEENABLE6_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6_SHIFT 4U +/* Field Value: TILEMODE6__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE6__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE6__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_PAD 0x2U +/* Field Value: TILEMODE6__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_TILEMODE6__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHASRCENABLE6_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHASRCENABLE6_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHACONSTENABLE6_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHACONSTENABLE6_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHATRANSENABLE6_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_ALPHATRANSENABLE6_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHASRCENABLE6_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHASRCENABLE6_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHACONSTENABLE6_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHACONSTENABLE6_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHATRANSENABLE6_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_RGBALPHATRANSENABLE6_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PREMULCONSTRGB6_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_PREMULCONSTRGB6_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE6__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__OFF 0U +/* Field Value: YUVCONVERSIONMODE6__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE6__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE6__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_YUVCONVERSIONMODE6__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_GAMMAREMOVEENABLE6_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_GAMMAREMOVEENABLE6_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_CLIPWINDOWENABLE6_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_CLIPWINDOWENABLE6_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_SOURCEBUFFERENABLE6_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY6_SOURCEBUFFERENABLE6_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_BaseAddress7 */ +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7 ((uint32_t)(0x8528)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_BASEADDRESS7_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_BASEADDRESS7_BASEADDRESS7_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferAttributes7 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7 ((uint32_t)(0x852C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_RESET_VALUE 0x200003U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_STRIDE7_MASK 0xFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_STRIDE7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_MASK 0x3F0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERATTRIBUTES7_BITSPERPIXEL7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_SourceBufferDimension7 */ +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7 ((uint32_t)(0x8530)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_RESET_VALUE 0x3FFF3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINEWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINEWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINECOUNT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_SOURCEBUFFERDIMENSION7_LINECOUNT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentBits7 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7 ((uint32_t)(0x8534)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_RESET_VALUE 0x8080808U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_MASK 0xF00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_MASK 0xF0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSRED7_MASK 0xF000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_COMPONENTBITSRED7_SHIFT 24U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFORMAT7_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTBITS7_ITUFORMAT7_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_ColorComponentShift7 */ +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7 ((uint32_t)(0x8538)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_RESET_VALUE 0x18100800U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_MASK 0x1FU +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_MASK 0x1F0000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_MASK 0x1F000000U +#define IMXDPUV1_FETCHLAYER0_COLORCOMPONENTSHIFT7_COMPONENTSHIFTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerOffset7 */ +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7 ((uint32_t)(0x853C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_LAYEROFFSET7_LAYERYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowOffset7 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7 ((uint32_t)(0x8540)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_MASK 0x7FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWXOFFSET7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_MASK 0x7FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWOFFSET7_CLIPWINDOWYOFFSET7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ClipWindowDimensions7 */ +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7 ((uint32_t)(0x8544)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWWIDTH7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_CLIPWINDOWDIMENSIONS7_CLIPWINDOWHEIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_fetchlayer0_ConstantColor7 */ +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7 ((uint32_t)(0x8548)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTALPHA7_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTALPHA7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTBLUE7_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTBLUE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTGREEN7_MASK 0xFF0000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTGREEN7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTRED7_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_CONSTANTCOLOR7_CONSTANTRED7_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_LayerProperty7 */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7 ((uint32_t)(0x854C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_VALUE 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PALETTEENABLE7_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PALETTEENABLE7_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7_MASK 0x30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7_SHIFT 4U +/* Field Value: TILEMODE7__TILE_FILL_ZERO, Use zero value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_FILL_ZERO 0U +/* Field Value: TILEMODE7__TILE_FILL_CONSTANT, Use constant color register + * value */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_FILL_CONSTANT 0x1U +/* Field Value: TILEMODE7__TILE_PAD, Use closest pixel from source buffer. + * Must not be used for DECODE or YUV422 operations or when SourceBufferEnable + * is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_PAD 0x2U +/* Field Value: TILEMODE7__TILE_PAD_ZERO, Use closest pixel from source buffer + * but zero for alpha component. Must not be used for DECODE or YUV422 + * operations or when SourceBufferEnable is 0. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_TILEMODE7__TILE_PAD_ZERO 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHASRCENABLE7_MASK 0x100U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHASRCENABLE7_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHACONSTENABLE7_MASK 0x200U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHACONSTENABLE7_SHIFT 9U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHATRANSENABLE7_MASK 0x800U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_ALPHATRANSENABLE7_SHIFT 11U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHASRCENABLE7_MASK 0x1000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHASRCENABLE7_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHACONSTENABLE7_MASK 0x2000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHACONSTENABLE7_SHIFT 13U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHATRANSENABLE7_MASK 0x8000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_RGBALPHATRANSENABLE7_SHIFT 15U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PREMULCONSTRGB7_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_PREMULCONSTRGB7_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7_MASK 0x60000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7_SHIFT 17U +/* Field Value: YUVCONVERSIONMODE7__OFF, No conversion. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__OFF 0U +/* Field Value: YUVCONVERSIONMODE7__ITU601, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.601-6 (standard definition TV). + * Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601 0x1U +/* Field Value: YUVCONVERSIONMODE7__ITU601_FR, Conversion from YCbCr (YUV) + * to RGB according to ITU recommendation BT.601-6, but assuming full range + * YUV inputs (0..255). Most typically used for computer graphics (e.g. + * for JPEG encoding). */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU601_FR 0x2U +/* Field Value: YUVCONVERSIONMODE7__ITU709, Conversion from YCbCr (YUV) to + * RGB according to ITU recommendation BT.709-5 part 2 (high definition + * TV). Input range is 16..235 for Y and 16..240 for U/V. */ +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_YUVCONVERSIONMODE7__ITU709 0x3U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_GAMMAREMOVEENABLE7_MASK 0x100000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_GAMMAREMOVEENABLE7_SHIFT 20U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_CLIPWINDOWENABLE7_MASK 0x40000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_CLIPWINDOWENABLE7_SHIFT 30U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_SOURCEBUFFERENABLE7_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_LAYERPROPERTY7_SOURCEBUFFERENABLE7_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_FrameDimensions */ +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS ((uint32_t)(0x8550)) +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_RESET_VALUE 0xEF013FU +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEWIDTH_MASK 0x3FFFU +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEWIDTH_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEHEIGHT_MASK 0x3FFF0000U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_FRAMEHEIGHT_SHIFT 16U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_EMPTYFRAME_MASK 0x80000000U +#define IMXDPUV1_FETCHLAYER0_FRAMEDIMENSIONS_EMPTYFRAME_SHIFT 31U + +/* Register: IMXDPUV1_fetchlayer0_FrameResampling */ +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING ((uint32_t)(0x8554)) +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_RESET_VALUE 0x104000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTX_MASK 0x3FU +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTX_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTY_MASK 0xFC0U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_STARTY_SHIFT 6U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAX_MASK 0x3F000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAX_SHIFT 12U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAY_MASK 0xFC0000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_DELTAY_SHIFT 18U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_SWAPDIRECTION_MASK 0x1000000U +#define IMXDPUV1_FETCHLAYER0_FRAMERESAMPLING_SWAPDIRECTION_SHIFT 24U + +/* Register: IMXDPUV1_fetchlayer0_Control */ +#define IMXDPUV1_FETCHLAYER0_CONTROL ((uint32_t)(0x8558)) +#define IMXDPUV1_FETCHLAYER0_CONTROL_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_FETCHLAYER0_CONTROL_RESET_VALUE 0x10700U +#define IMXDPUV1_FETCHLAYER0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_CONTROL_RAWPIXEL_MASK 0x80U +#define IMXDPUV1_FETCHLAYER0_CONTROL_RAWPIXEL_SHIFT 7U +#define IMXDPUV1_FETCHLAYER0_CONTROL_PALETTEIDXWIDTH_MASK 0x700U +#define IMXDPUV1_FETCHLAYER0_CONTROL_PALETTEIDXWIDTH_SHIFT 8U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR_MASK 0x10000U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR_SHIFT 16U +/* Field Value: CLIPCOLOR__NULL, Null color. */ +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR__NULL 0U +/* Field Value: CLIPCOLOR__LAYER, Color of layer number given by ClipLayer + * (or layer 0 when Fetch unit has one layer only). The color is then the + * layer's source or tiling color. */ +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPCOLOR__LAYER 0x1U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPLAYER_MASK 0xE0000U +#define IMXDPUV1_FETCHLAYER0_CONTROL_CLIPLAYER_SHIFT 17U + +/* Register: IMXDPUV1_fetchlayer0_TriggerEnable */ +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE ((uint32_t)(0x855C)) +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_TRIGGERENABLE_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_ControlTrigger */ +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER ((uint32_t)(0x8560)) +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_CONTROLTRIGGER_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_Start */ +#define IMXDPUV1_FETCHLAYER0_START ((uint32_t)(0x8564)) +#define IMXDPUV1_FETCHLAYER0_START_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_FETCHLAYER0_START_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_START_RESET_MASK 0xFFFFFFFEU +#define IMXDPUV1_FETCHLAYER0_START_START_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_START_START_SHIFT 0U + +/* Register: IMXDPUV1_fetchlayer0_FetchType */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE ((uint32_t)(0x8568)) +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_RESET_MASK 0xFFFFFFF0U +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE_MASK 0xFU +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE_SHIFT 0U +/* Field Value: FETCHTYPE__DECODE, Fetch unit with RL and RLAD decoder. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__DECODE 0U +/* Field Value: FETCHTYPE__LAYER, Fetch unit with fractional plane (8 layers). */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__LAYER 0x1U +/* Field Value: FETCHTYPE__WARP, Fetch unit with arbitrary warping and fractional + * plane (8 layers). */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__WARP 0x2U +/* Field Value: FETCHTYPE__ECO, Fetch unit with minimum feature set for alpha, + * chroma and coordinate planes. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ECO 0x3U +/* Field Value: FETCHTYPE__PERSP, Fetch unit with affine, perspective and + * arbitrary warping. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__PERSP 0x4U +/* Field Value: FETCHTYPE__ROT, Fetch unit with affine and arbitrary warping. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ROT 0x5U +/* Field Value: FETCHTYPE__DECODEL, Fetch unit with RL and RLAD decoder, reduced + * feature set. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__DECODEL 0x6U +/* Field Value: FETCHTYPE__LAYERL, Fetch unit with fractional plane (8 layers), + * reduced feature set. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__LAYERL 0x7U +/* Field Value: FETCHTYPE__ROTL, Fetch unit with affine and arbitrary warping, + * reduced feature set. */ +#define IMXDPUV1_FETCHLAYER0_FETCHTYPE_FETCHTYPE__ROTL 0x8U + +/* Register: IMXDPUV1_fetchlayer0_BurstBufferProperties */ +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES ((uint32_t)(0x856C)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_RESET_MASK 0xFFFFE000U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_MASK 0xFFU +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_MANAGEDBURSTBUFFERS_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_MASK 0x1F00U +#define IMXDPUV1_FETCHLAYER0_BURSTBUFFERPROPERTIES_BURSTLENGTHFORMAXBUFFERS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_Status */ +#define IMXDPUV1_FETCHLAYER0_STATUS ((uint32_t)(0x8570)) +#define IMXDPUV1_FETCHLAYER0_STATUS_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_FETCHLAYER0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FETCHLAYER0_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_STATUS_WRITETIMEOUT_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_STATUS_READTIMEOUT_MASK 0x10U +#define IMXDPUV1_FETCHLAYER0_STATUS_READTIMEOUT_SHIFT 4U + +/* Register: IMXDPUV1_fetchlayer0_HiddenStatus */ +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS ((uint32_t)(0x8574)) +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_RESET_MASK 0xFFFF008EU +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUSY_MASK 0x1U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUSY_SHIFT 0U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUFFERSIDLE_MASK 0x10U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSBUFFERSIDLE_SHIFT 4U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSREQUEST_MASK 0x20U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSREQUEST_SHIFT 5U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSCOMPLETE_MASK 0x40U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_STATUSCOMPLETE_SHIFT 6U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_SHADOWSTATUS_MASK 0xFF00U +#define IMXDPUV1_FETCHLAYER0_HIDDENSTATUS_SHADOWSTATUS_SHIFT 8U + +/* Register: IMXDPUV1_fetchlayer0_ColorPalette */ +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE ((uint32_t)(0x8800)) +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_RESET_VALUE 0U +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_RESET_MASK 0xFF000000U +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_COLORPALETTE_MASK 0xFFFFFFU +#define IMXDPUV1_FETCHLAYER0_COLORPALETTE_COLORPALETTE_SHIFT 0U + +/* Register: IMXDPUV1_matrix4_LockUnlock */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK ((uint32_t)(0x8C00)) +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix4_LockStatus */ +#define IMXDPUV1_MATRIX4_LOCKSTATUS ((uint32_t)(0x8C04)) +#define IMXDPUV1_MATRIX4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix4_StaticControl */ +#define IMXDPUV1_MATRIX4_STATICCONTROL ((uint32_t)(0x8C08)) +#define IMXDPUV1_MATRIX4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix4_Control */ +#define IMXDPUV1_MATRIX4_CONTROL ((uint32_t)(0x8C0C)) +#define IMXDPUV1_MATRIX4_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX4_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX4_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX4_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX4_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix4_Red0 */ +#define IMXDPUV1_MATRIX4_RED0 ((uint32_t)(0x8C10)) +#define IMXDPUV1_MATRIX4_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX4_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX4_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX4_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Red1 */ +#define IMXDPUV1_MATRIX4_RED1 ((uint32_t)(0x8C14)) +#define IMXDPUV1_MATRIX4_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX4_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX4_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Green0 */ +#define IMXDPUV1_MATRIX4_GREEN0 ((uint32_t)(0x8C18)) +#define IMXDPUV1_MATRIX4_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX4_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX4_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX4_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Green1 */ +#define IMXDPUV1_MATRIX4_GREEN1 ((uint32_t)(0x8C1C)) +#define IMXDPUV1_MATRIX4_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX4_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX4_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Blue0 */ +#define IMXDPUV1_MATRIX4_BLUE0 ((uint32_t)(0x8C20)) +#define IMXDPUV1_MATRIX4_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX4_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX4_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Blue1 */ +#define IMXDPUV1_MATRIX4_BLUE1 ((uint32_t)(0x8C24)) +#define IMXDPUV1_MATRIX4_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX4_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX4_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX4_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Alpha0 */ +#define IMXDPUV1_MATRIX4_ALPHA0 ((uint32_t)(0x8C28)) +#define IMXDPUV1_MATRIX4_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX4_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX4_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_Alpha1 */ +#define IMXDPUV1_MATRIX4_ALPHA1 ((uint32_t)(0x8C2C)) +#define IMXDPUV1_MATRIX4_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX4_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX4_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX4_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_OffsetVector0 */ +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0 ((uint32_t)(0x8C30)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_OffsetVector1 */ +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1 ((uint32_t)(0x8C34)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX4_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix4_LastControlWord */ +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD ((uint32_t)(0x8C38)) +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX4_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_LockUnlock */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK ((uint32_t)(0x9000)) +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_HSCALER4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_hscaler4_LockStatus */ +#define IMXDPUV1_HSCALER4_LOCKSTATUS ((uint32_t)(0x9004)) +#define IMXDPUV1_HSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_HSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_HSCALER4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_hscaler4_StaticControl */ +#define IMXDPUV1_HSCALER4_STATICCONTROL ((uint32_t)(0x9008)) +#define IMXDPUV1_HSCALER4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_HSCALER4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_HSCALER4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_Setup1 */ +#define IMXDPUV1_HSCALER4_SETUP1 ((uint32_t)(0x900C)) +#define IMXDPUV1_HSCALER4_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_HSCALER4_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_HSCALER4_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_HSCALER4_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_Setup2 */ +#define IMXDPUV1_HSCALER4_SETUP2 ((uint32_t)(0x9010)) +#define IMXDPUV1_HSCALER4_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_HSCALER4_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_HSCALER4_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_hscaler4_Control */ +#define IMXDPUV1_HSCALER4_CONTROL ((uint32_t)(0x9014)) +#define IMXDPUV1_HSCALER4_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_HSCALER4_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER4_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_HSCALER4_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_HSCALER4_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size) */ +#define IMXDPUV1_HSCALER4_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_HSCALER4_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_HSCALER4_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_HSCALER4_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_vscaler4_LockUnlock */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK ((uint32_t)(0x9400)) +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_VSCALER4_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_vscaler4_LockStatus */ +#define IMXDPUV1_VSCALER4_LOCKSTATUS ((uint32_t)(0x9404)) +#define IMXDPUV1_VSCALER4_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_VSCALER4_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_VSCALER4_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_vscaler4_StaticControl */ +#define IMXDPUV1_VSCALER4_STATICCONTROL ((uint32_t)(0x9408)) +#define IMXDPUV1_VSCALER4_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_VSCALER4_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_VSCALER4_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup1 */ +#define IMXDPUV1_VSCALER4_SETUP1 ((uint32_t)(0x940C)) +#define IMXDPUV1_VSCALER4_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_VSCALER4_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_VSCALER4_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_VSCALER4_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup2 */ +#define IMXDPUV1_VSCALER4_SETUP2 ((uint32_t)(0x9410)) +#define IMXDPUV1_VSCALER4_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_VSCALER4_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup3 */ +#define IMXDPUV1_VSCALER4_SETUP3 ((uint32_t)(0x9414)) +#define IMXDPUV1_VSCALER4_SETUP3_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_VSCALER4_SETUP3_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP3_PHASE_OFFSET1_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP3_PHASE_OFFSET1_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup4 */ +#define IMXDPUV1_VSCALER4_SETUP4 ((uint32_t)(0x9418)) +#define IMXDPUV1_VSCALER4_SETUP4_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_VSCALER4_SETUP4_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP4_PHASE_OFFSET2_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP4_PHASE_OFFSET2_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Setup5 */ +#define IMXDPUV1_VSCALER4_SETUP5 ((uint32_t)(0x941C)) +#define IMXDPUV1_VSCALER4_SETUP5_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_VSCALER4_SETUP5_RESET_VALUE 0U +#define IMXDPUV1_VSCALER4_SETUP5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_SETUP5_PHASE_OFFSET3_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER4_SETUP5_PHASE_OFFSET3_SHIFT 0U + +/* Register: IMXDPUV1_vscaler4_Control */ +#define IMXDPUV1_VSCALER4_CONTROL ((uint32_t)(0x9420)) +#define IMXDPUV1_VSCALER4_CONTROL_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_VSCALER4_CONTROL_RESET_VALUE 0x2000U +#define IMXDPUV1_VSCALER4_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER4_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_VSCALER4_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_VSCALER4_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size). */ +#define IMXDPUV1_VSCALER4_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_VSCALER4_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE_MASK 0x3000U +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE_SHIFT 12U +/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__ALWAYS0 0U +/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__ALWAYS1 0x1U +/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input + * field polarity. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__INPUT 0x2U +/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting + * with 0 after reset. */ +#define IMXDPUV1_VSCALER4_CONTROL_FIELD_MODE__TOGGLE 0x3U +#define IMXDPUV1_VSCALER4_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_VSCALER4_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_LockUnlock */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK ((uint32_t)(0x9800)) +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix5_LockStatus */ +#define IMXDPUV1_MATRIX5_LOCKSTATUS ((uint32_t)(0x9804)) +#define IMXDPUV1_MATRIX5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix5_StaticControl */ +#define IMXDPUV1_MATRIX5_STATICCONTROL ((uint32_t)(0x9808)) +#define IMXDPUV1_MATRIX5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix5_Control */ +#define IMXDPUV1_MATRIX5_CONTROL ((uint32_t)(0x980C)) +#define IMXDPUV1_MATRIX5_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX5_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX5_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX5_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX5_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix5_Red0 */ +#define IMXDPUV1_MATRIX5_RED0 ((uint32_t)(0x9810)) +#define IMXDPUV1_MATRIX5_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX5_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX5_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX5_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Red1 */ +#define IMXDPUV1_MATRIX5_RED1 ((uint32_t)(0x9814)) +#define IMXDPUV1_MATRIX5_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX5_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX5_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Green0 */ +#define IMXDPUV1_MATRIX5_GREEN0 ((uint32_t)(0x9818)) +#define IMXDPUV1_MATRIX5_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX5_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX5_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX5_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Green1 */ +#define IMXDPUV1_MATRIX5_GREEN1 ((uint32_t)(0x981C)) +#define IMXDPUV1_MATRIX5_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX5_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX5_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Blue0 */ +#define IMXDPUV1_MATRIX5_BLUE0 ((uint32_t)(0x9820)) +#define IMXDPUV1_MATRIX5_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX5_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX5_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Blue1 */ +#define IMXDPUV1_MATRIX5_BLUE1 ((uint32_t)(0x9824)) +#define IMXDPUV1_MATRIX5_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX5_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX5_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX5_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Alpha0 */ +#define IMXDPUV1_MATRIX5_ALPHA0 ((uint32_t)(0x9828)) +#define IMXDPUV1_MATRIX5_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX5_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX5_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_Alpha1 */ +#define IMXDPUV1_MATRIX5_ALPHA1 ((uint32_t)(0x982C)) +#define IMXDPUV1_MATRIX5_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX5_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX5_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX5_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_OffsetVector0 */ +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0 ((uint32_t)(0x9830)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_OffsetVector1 */ +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1 ((uint32_t)(0x9834)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX5_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix5_LastControlWord */ +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD ((uint32_t)(0x9838)) +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX5_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_LockUnlock */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK ((uint32_t)(0x9C00)) +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_HSCALER5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_hscaler5_LockStatus */ +#define IMXDPUV1_HSCALER5_LOCKSTATUS ((uint32_t)(0x9C04)) +#define IMXDPUV1_HSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_HSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_HSCALER5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_hscaler5_StaticControl */ +#define IMXDPUV1_HSCALER5_STATICCONTROL ((uint32_t)(0x9C08)) +#define IMXDPUV1_HSCALER5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_HSCALER5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_HSCALER5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_Setup1 */ +#define IMXDPUV1_HSCALER5_SETUP1 ((uint32_t)(0x9C0C)) +#define IMXDPUV1_HSCALER5_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_HSCALER5_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_HSCALER5_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_HSCALER5_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_Setup2 */ +#define IMXDPUV1_HSCALER5_SETUP2 ((uint32_t)(0x9C10)) +#define IMXDPUV1_HSCALER5_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_HSCALER5_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_HSCALER5_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_hscaler5_Control */ +#define IMXDPUV1_HSCALER5_CONTROL ((uint32_t)(0x9C14)) +#define IMXDPUV1_HSCALER5_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_HSCALER5_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_HSCALER5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_HSCALER5_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_HSCALER5_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_HSCALER5_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size) */ +#define IMXDPUV1_HSCALER5_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_HSCALER5_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_HSCALER5_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_HSCALER5_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_vscaler5_LockUnlock */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK ((uint32_t)(0xA000)) +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_VSCALER5_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_vscaler5_LockStatus */ +#define IMXDPUV1_VSCALER5_LOCKSTATUS ((uint32_t)(0xA004)) +#define IMXDPUV1_VSCALER5_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_VSCALER5_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_VSCALER5_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_vscaler5_StaticControl */ +#define IMXDPUV1_VSCALER5_STATICCONTROL ((uint32_t)(0xA008)) +#define IMXDPUV1_VSCALER5_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_VSCALER5_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_VSCALER5_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup1 */ +#define IMXDPUV1_VSCALER5_SETUP1 ((uint32_t)(0xA00C)) +#define IMXDPUV1_VSCALER5_SETUP1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_VSCALER5_SETUP1_RESET_VALUE 0x80000U +#define IMXDPUV1_VSCALER5_SETUP1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP1_SCALE_FACTOR_MASK 0xFFFFFU +#define IMXDPUV1_VSCALER5_SETUP1_SCALE_FACTOR_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup2 */ +#define IMXDPUV1_VSCALER5_SETUP2 ((uint32_t)(0xA010)) +#define IMXDPUV1_VSCALER5_SETUP2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_VSCALER5_SETUP2_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP2_PHASE_OFFSET_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP2_PHASE_OFFSET_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup3 */ +#define IMXDPUV1_VSCALER5_SETUP3 ((uint32_t)(0xA014)) +#define IMXDPUV1_VSCALER5_SETUP3_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_VSCALER5_SETUP3_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP3_PHASE_OFFSET1_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP3_PHASE_OFFSET1_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup4 */ +#define IMXDPUV1_VSCALER5_SETUP4 ((uint32_t)(0xA018)) +#define IMXDPUV1_VSCALER5_SETUP4_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_VSCALER5_SETUP4_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP4_PHASE_OFFSET2_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP4_PHASE_OFFSET2_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Setup5 */ +#define IMXDPUV1_VSCALER5_SETUP5 ((uint32_t)(0xA01C)) +#define IMXDPUV1_VSCALER5_SETUP5_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_VSCALER5_SETUP5_RESET_VALUE 0U +#define IMXDPUV1_VSCALER5_SETUP5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_SETUP5_PHASE_OFFSET3_MASK 0x1FFFFFU +#define IMXDPUV1_VSCALER5_SETUP5_PHASE_OFFSET3_SHIFT 0U + +/* Register: IMXDPUV1_vscaler5_Control */ +#define IMXDPUV1_VSCALER5_CONTROL ((uint32_t)(0xA020)) +#define IMXDPUV1_VSCALER5_CONTROL_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_VSCALER5_CONTROL_RESET_VALUE 0x2000U +#define IMXDPUV1_VSCALER5_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_VSCALER5_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the scaler, all + * other settings are ignored. */ +#define IMXDPUV1_VSCALER5_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Scaler is active. */ +#define IMXDPUV1_VSCALER5_CONTROL_MODE__ACTIVE 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE_MASK 0x10U +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE_SHIFT 4U +/* Field Value: SCALE_MODE__DOWNSCALE, Down-scaling (output size less or equal + * input size). */ +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE__DOWNSCALE 0U +/* Field Value: SCALE_MODE__UPSCALE, Up-scaling (output size greater or equal + * input size). */ +#define IMXDPUV1_VSCALER5_CONTROL_SCALE_MODE__UPSCALE 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE_MASK 0x100U +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE_SHIFT 8U +/* Field Value: FILTER_MODE__NEAREST, Nearest filter (point-sampling) */ +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE__NEAREST 0U +/* Field Value: FILTER_MODE__LINEAR, Box filter (linear) */ +#define IMXDPUV1_VSCALER5_CONTROL_FILTER_MODE__LINEAR 0x1U +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE_MASK 0x3000U +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE_SHIFT 12U +/* Field Value: FIELD_MODE__ALWAYS0, Constant 0 indicates frame or top field. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__ALWAYS0 0U +/* Field Value: FIELD_MODE__ALWAYS1, Constant 1 indicates bottom field. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__ALWAYS1 0x1U +/* Field Value: FIELD_MODE__INPUT, Output field polarity is taken from input + * field polarity. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__INPUT 0x2U +/* Field Value: FIELD_MODE__TOGGLE, Output field polarity toggles, starting + * with 0 after reset. */ +#define IMXDPUV1_VSCALER5_CONTROL_FIELD_MODE__TOGGLE 0x3U +#define IMXDPUV1_VSCALER5_CONTROL_OUTPUT_SIZE_MASK 0x3FFF0000U +#define IMXDPUV1_VSCALER5_CONTROL_OUTPUT_SIZE_SHIFT 16U + +/* Register: IMXDPUV1_layerblend0_LockUnlock */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK ((uint32_t)(0xA400)) +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend0_LockStatus */ +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS ((uint32_t)(0xA404)) +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend0_StaticControl */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL ((uint32_t)(0xA408)) +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND0_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend0_Control */ +#define IMXDPUV1_LAYERBLEND0_CONTROL ((uint32_t)(0xA40C)) +#define IMXDPUV1_LAYERBLEND0_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND0_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND0_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND0_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend0_BlendControl */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL ((uint32_t)(0xA410)) +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND0_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend0_Position */ +#define IMXDPUV1_LAYERBLEND0_POSITION ((uint32_t)(0xA414)) +#define IMXDPUV1_LAYERBLEND0_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND0_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND0_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND0_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND0_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend0_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD ((uint32_t)(0xA418)) +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend0_SecControlWord */ +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD ((uint32_t)(0xA41C)) +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND0_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend1_LockUnlock */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK ((uint32_t)(0xA800)) +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend1_LockStatus */ +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS ((uint32_t)(0xA804)) +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend1_StaticControl */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL ((uint32_t)(0xA808)) +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND1_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend1_Control */ +#define IMXDPUV1_LAYERBLEND1_CONTROL ((uint32_t)(0xA80C)) +#define IMXDPUV1_LAYERBLEND1_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND1_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND1_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND1_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend1_BlendControl */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL ((uint32_t)(0xA810)) +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND1_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend1_Position */ +#define IMXDPUV1_LAYERBLEND1_POSITION ((uint32_t)(0xA814)) +#define IMXDPUV1_LAYERBLEND1_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND1_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND1_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND1_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND1_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend1_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD ((uint32_t)(0xA818)) +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend1_SecControlWord */ +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD ((uint32_t)(0xA81C)) +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND1_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend2_LockUnlock */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK ((uint32_t)(0xAC00)) +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND2_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend2_LockStatus */ +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS ((uint32_t)(0xAC04)) +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND2_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend2_StaticControl */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL ((uint32_t)(0xAC08)) +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND2_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend2_Control */ +#define IMXDPUV1_LAYERBLEND2_CONTROL ((uint32_t)(0xAC0C)) +#define IMXDPUV1_LAYERBLEND2_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND2_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND2_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND2_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend2_BlendControl */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL ((uint32_t)(0xAC10)) +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND2_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend2_Position */ +#define IMXDPUV1_LAYERBLEND2_POSITION ((uint32_t)(0xAC14)) +#define IMXDPUV1_LAYERBLEND2_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND2_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND2_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND2_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND2_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend2_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD ((uint32_t)(0xAC18)) +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend2_SecControlWord */ +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD ((uint32_t)(0xAC1C)) +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND2_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend3_LockUnlock */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK ((uint32_t)(0xB000)) +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_LAYERBLEND3_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_layerblend3_LockStatus */ +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS ((uint32_t)(0xB004)) +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_LAYERBLEND3_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_layerblend3_StaticControl */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL ((uint32_t)(0xB008)) +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_VALUE 0x14U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL_MASK 0x6U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL_SHIFT 1U +/* Field Value: SHDLDSEL__PRIMARY, Load shadows with shadow load token on + * primary input (background plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__PRIMARY 0U +/* Field Value: SHDLDSEL__SECONDARY, Load shadows with shadow load token on + * secondary input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__SECONDARY 0x1U +/* Field Value: SHDLDSEL__BOTH, Load shadows with shadow load token on any + * input. */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDLDSEL__BOTH 0x2U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL_MASK 0x18U +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL_SHIFT 3U +/* Field Value: SHDTOKSEL__PRIMARY, When a token was received on the primary + * input (background plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__PRIMARY 0U +/* Field Value: SHDTOKSEL__SECONDARY, When a token was received on the secondary + * input (foreground plane). */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__SECONDARY 0x1U +/* Field Value: SHDTOKSEL__BOTH, When a token was received on any input. */ +#define IMXDPUV1_LAYERBLEND3_STATICCONTROL_SHDTOKSEL__BOTH 0x2U + +/* Register: IMXDPUV1_layerblend3_Control */ +#define IMXDPUV1_LAYERBLEND3_CONTROL ((uint32_t)(0xB00C)) +#define IMXDPUV1_LAYERBLEND3_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_LAYERBLEND3_CONTROL_RESET_VALUE 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module is in neutral mode. Output is same as + * primary input. */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__BLEND, Module is in blending mode. */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_MODE__BLEND 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE_MASK 0x4U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE_SHIFT 2U +/* Field Value: ALPHAMASKENABLE__DISABLE, AlphaMask feature disabled */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE__DISABLE 0U +/* Field Value: ALPHAMASKENABLE__ENABLE, AlphaMask feature enabled */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKENABLE__ENABLE 0x1U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE_MASK 0x70U +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE_SHIFT 4U +/* Field Value: ALPHAMASKMODE__PRIM, Areas with primary input alpha > 128 + * will be mapped to 255 and the rest will have an alpha value of 0 */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM 0U +/* Field Value: ALPHAMASKMODE__SEC, The area of the secondary input will get + * an alpha value of 255 and the rest will be 0 */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__SEC 0x1U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC, Behaves as if the output of modes + * PRIM and SEC would be ORed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC 0x2U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC, Behaves as if the output of modes + * PRIM and SEC would be ANDed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC 0x3U +/* Field Value: ALPHAMASKMODE__PRIM_INV, Behaves as if the output of mode + * PRIM would be inverted */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_INV 0x4U +/* Field Value: ALPHAMASKMODE__SEC_INV, Behaves as if the output of mode SEC + * would be inverted */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__SEC_INV 0x5U +/* Field Value: ALPHAMASKMODE__PRIM_OR_SEC_INV, Behaves as if the output of + * modes PRIM and SEC_INV would be ORed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_OR_SEC_INV 0x6U +/* Field Value: ALPHAMASKMODE__PRIM_AND_SEC_INV, Behaves as if the output + * of modes PRIM and SEC_INV would be ANDed together */ +#define IMXDPUV1_LAYERBLEND3_CONTROL_ALPHAMASKMODE__PRIM_AND_SEC_INV 0x7U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECLOWPASSEN_MASK 0x100U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECLOWPASSEN_SHIFT 8U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECREPLICATEEN_MASK 0x200U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECREPLICATEEN_SHIFT 9U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWEVENCOLDIS_MASK 0x3C00U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWEVENCOLDIS_SHIFT 10U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWODDCOLDIS_MASK 0x3C000U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECEVENROWODDCOLDIS_SHIFT 14U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWEVENCOLDIS_MASK 0x3C0000U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWEVENCOLDIS_SHIFT 18U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWODDCOLDIS_MASK 0x3C00000U +#define IMXDPUV1_LAYERBLEND3_CONTROL_SECODDROWODDCOLDIS_SHIFT 22U + +/* Register: IMXDPUV1_layerblend3_BlendControl */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL ((uint32_t)(0xB010)) +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_RESET_VALUE 0x1010U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_MASK 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC_SHIFT 0U +/* Field Value: PRIM_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_MASK 0x70U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC_SHIFT 4U +/* Field Value: SEC_C_BLD_FUNC__ZERO, Cout = Cin * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ZERO 0U +/* Field Value: SEC_C_BLD_FUNC__ONE, Cout = Cin * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_C_BLD_FUNC__PRIM_ALPHA, Cout = Cin * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Cout = Cin * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_C_BLD_FUNC__SEC_ALPHA, Cout = Cin * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Cout = Cin * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_C_BLD_FUNC__CONST_ALPHA, Cout = Cin * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Cout = Cin * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_C_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_MASK 0x700U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC_SHIFT 8U +/* Field Value: PRIM_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ZERO 0U +/* Field Value: PRIM_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE 0x1U +/* Field Value: PRIM_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: PRIM_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: PRIM_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - + * ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_PRIM_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_MASK 0x7000U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC_SHIFT 12U +/* Field Value: SEC_A_BLD_FUNC__ZERO, Aout = Ain * 0 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ZERO 0U +/* Field Value: SEC_A_BLD_FUNC__ONE, Aout = Ain * 1 */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE 0x1U +/* Field Value: SEC_A_BLD_FUNC__PRIM_ALPHA, Aout = Ain * ALPHA_prim */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__PRIM_ALPHA 0x2U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA, Aout = Ain * (1 - ALPHA_prim) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_PRIM_ALPHA 0x3U +/* Field Value: SEC_A_BLD_FUNC__SEC_ALPHA, Aout = Ain * ALPHA_sec */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__SEC_ALPHA 0x4U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA, Aout = Ain * (1 - ALPHA_sec) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_SEC_ALPHA 0x5U +/* Field Value: SEC_A_BLD_FUNC__CONST_ALPHA, Aout = Ain * ALPHA_const */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__CONST_ALPHA 0x6U +/* Field Value: SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA, Aout = Ain * (1 - ALPHA_const) */ +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_SEC_A_BLD_FUNC__ONE_MINUS_CONST_ALPHA 0x7U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_BLENDALPHA_MASK 0xFF0000U +#define IMXDPUV1_LAYERBLEND3_BLENDCONTROL_BLENDALPHA_SHIFT 16U + +/* Register: IMXDPUV1_layerblend3_Position */ +#define IMXDPUV1_LAYERBLEND3_POSITION ((uint32_t)(0xB014)) +#define IMXDPUV1_LAYERBLEND3_POSITION_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_LAYERBLEND3_POSITION_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_POSITION_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_POSITION_XPOS_MASK 0xFFFFU +#define IMXDPUV1_LAYERBLEND3_POSITION_XPOS_SHIFT 0U +#define IMXDPUV1_LAYERBLEND3_POSITION_YPOS_MASK 0xFFFF0000U +#define IMXDPUV1_LAYERBLEND3_POSITION_YPOS_SHIFT 16U + +/* Register: IMXDPUV1_layerblend3_PrimControlWord */ +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD ((uint32_t)(0xB018)) +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_PRIMCONTROLWORD_P_VAL_SHIFT 0U + +/* Register: IMXDPUV1_layerblend3_SecControlWord */ +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD ((uint32_t)(0xB01C)) +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_S_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_LAYERBLEND3_SECCONTROLWORD_S_VAL_SHIFT 0U + +/* Register: IMXDPUV1_disengcfg_LockUnlock0 */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0 ((uint32_t)(0xB400)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_RESET_MASK 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0_SHIFT 0U +/* Field Value: LOCKUNLOCK0__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK0__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK0__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK0__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK0__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK0_LOCKUNLOCK0__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_disengcfg_LockStatus0 */ +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0 ((uint32_t)(0xB404)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_LOCKSTATUS0_MASK 0x1U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_LOCKSTATUS0_SHIFT 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_PRIVILEGESTATUS0_MASK 0x10U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_PRIVILEGESTATUS0_SHIFT 4U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_FREEZESTATUS0_MASK 0x100U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS0_FREEZESTATUS0_SHIFT 8U + +/* Register: IMXDPUV1_disengcfg_ClockCtrl0 */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0 ((uint32_t)(0xB408)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_RESET_VALUE 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0_MASK 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0_SHIFT 0U +/* Field Value: DSPCLKDIVIDE0__DIV1, External display clock signal has pixel + * clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0__DIV1 0U +/* Field Value: DSPCLKDIVIDE0__DIV2, External display clock signal has twice + * the pixel clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL0_DSPCLKDIVIDE0__DIV2 0x1U + +/* Register: IMXDPUV1_disengcfg_PolarityCtrl0 */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0 ((uint32_t)(0xB40C)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_RESET_VALUE 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0_MASK 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0_SHIFT 0U +/* Field Value: POLHS0__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__LOW 0U +/* Field Value: POLHS0__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLHS0__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0_MASK 0x2U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0_SHIFT 1U +/* Field Value: POLVS0__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__LOW 0U +/* Field Value: POLVS0__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLVS0__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0_MASK 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0_SHIFT 2U +/* Field Value: POLEN0__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__LOW 0U +/* Field Value: POLEN0__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_POLEN0__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0_MASK 0x8U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0_SHIFT 3U +/* Field Value: PIXINV0__NONINV, No inversion of pixel data */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0__NONINV 0U +/* Field Value: PIXINV0__INV, Pixel data inverted (1. complement) */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL0_PIXINV0__INV 0x1U + +/* Register: IMXDPUV1_disengcfg_SrcSelect0 */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0 ((uint32_t)(0xB410)) +#define IMXDPUV1_DISENGCFG_SRCSELECT0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DISENGCFG_SRCSELECT0_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0_MASK 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0_SHIFT 0U +/* Field Value: SIG_SELECT0__FRAMEGEN, Source is FrameGen#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__FRAMEGEN 0U +/* Field Value: SIG_SELECT0__GAMMACOR, Source is GammaCor#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__GAMMACOR 0x1U +/* Field Value: SIG_SELECT0__MATRIX, Source is Matrix#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__MATRIX 0x2U +/* Field Value: SIG_SELECT0__DITHER, Source is Dither#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_SIG_SELECT0__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0_MASK 0x10U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0_SHIFT 4U +/* Field Value: PATH_SELECT0__GAMMA_FIRST, Framegen - Gamma - Matrix - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0__GAMMA_FIRST 0U +/* Field Value: PATH_SELECT0__MATRIX_FIRST, Framegen - Matrix - Gamma - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_PATH_SELECT0__MATRIX_FIRST 0x1U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0_MASK 0x300U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0_SHIFT 8U +/* Field Value: DUMP0_SELECT0__FRAMEGEN, Source is FrameGen#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__FRAMEGEN 0U +/* Field Value: DUMP0_SELECT0__GAMMACOR, Source is GammaCor#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__GAMMACOR 0x1U +/* Field Value: DUMP0_SELECT0__MATRIX, Source is Matrix#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__MATRIX 0x2U +/* Field Value: DUMP0_SELECT0__DITHER, Source is Dither#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP0_SELECT0__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0_MASK 0xC00U +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0_SHIFT 10U +/* Field Value: DUMP1_SELECT0__FRAMEGEN, Source is FrameGen#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__FRAMEGEN 0U +/* Field Value: DUMP1_SELECT0__GAMMACOR, Source is GammaCor#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__GAMMACOR 0x1U +/* Field Value: DUMP1_SELECT0__MATRIX, Source is Matrix#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__MATRIX 0x2U +/* Field Value: DUMP1_SELECT0__DITHER, Source is Dither#0 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT0_DUMP1_SELECT0__DITHER 0x3U + +/* Register: IMXDPUV1_disengcfg_LockUnlock1 */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1 ((uint32_t)(0xB420)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_RESET_MASK 0U +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1_SHIFT 0U +/* Field Value: LOCKUNLOCK1__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK1__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK1__PRIVILEGE_KEY, Enables privilege protection. + * Disabled after reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK1__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK1__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DISENGCFG_LOCKUNLOCK1_LOCKUNLOCK1__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_disengcfg_LockStatus1 */ +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1 ((uint32_t)(0xB424)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_LOCKSTATUS1_MASK 0x1U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_LOCKSTATUS1_SHIFT 0U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_PRIVILEGESTATUS1_MASK 0x10U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_PRIVILEGESTATUS1_SHIFT 4U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_FREEZESTATUS1_MASK 0x100U +#define IMXDPUV1_DISENGCFG_LOCKSTATUS1_FREEZESTATUS1_SHIFT 8U + +/* Register: IMXDPUV1_disengcfg_ClockCtrl1 */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1 ((uint32_t)(0xB428)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_RESET_VALUE 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1_MASK 0x1U +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1_SHIFT 0U +/* Field Value: DSPCLKDIVIDE1__DIV1, External display clock signal has pixel + * clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1__DIV1 0U +/* Field Value: DSPCLKDIVIDE1__DIV2, External display clock signal has twice + * the pixel clock frequency. */ +#define IMXDPUV1_DISENGCFG_CLOCKCTRL1_DSPCLKDIVIDE1__DIV2 0x1U + +/* Register: IMXDPUV1_disengcfg_PolarityCtrl1 */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1 ((uint32_t)(0xB42C)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_RESET_VALUE 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1_MASK 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1_SHIFT 0U +/* Field Value: POLHS1__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__LOW 0U +/* Field Value: POLHS1__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLHS1__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1_MASK 0x2U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1_SHIFT 1U +/* Field Value: POLVS1__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__LOW 0U +/* Field Value: POLVS1__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLVS1__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1_MASK 0x4U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1_SHIFT 2U +/* Field Value: POLEN1__LOW, Low active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__LOW 0U +/* Field Value: POLEN1__HIGH, High active */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_POLEN1__HIGH 0x1U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1_MASK 0x8U +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1_SHIFT 3U +/* Field Value: PIXINV1__NONINV, No inversion of pixel data */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1__NONINV 0U +/* Field Value: PIXINV1__INV, Pixel data inverted (1. complement) */ +#define IMXDPUV1_DISENGCFG_POLARITYCTRL1_PIXINV1__INV 0x1U + +/* Register: IMXDPUV1_disengcfg_SrcSelect1 */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1 ((uint32_t)(0xB430)) +#define IMXDPUV1_DISENGCFG_SRCSELECT1_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_DISENGCFG_SRCSELECT1_RESET_VALUE 0U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1_MASK 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1_SHIFT 0U +/* Field Value: SIG_SELECT1__FRAMEGEN, Source is FrameGen#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__FRAMEGEN 0U +/* Field Value: SIG_SELECT1__GAMMACOR, Source is GammaCor#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__GAMMACOR 0x1U +/* Field Value: SIG_SELECT1__MATRIX, Source is Matrix#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__MATRIX 0x2U +/* Field Value: SIG_SELECT1__DITHER, Source is Dither#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_SIG_SELECT1__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1_MASK 0x10U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1_SHIFT 4U +/* Field Value: PATH_SELECT1__GAMMA_FIRST, Framegen - Gamma - Matrix - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1__GAMMA_FIRST 0U +/* Field Value: PATH_SELECT1__MATRIX_FIRST, Framegen - Matrix - Gamma - Dither. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_PATH_SELECT1__MATRIX_FIRST 0x1U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1_MASK 0x300U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1_SHIFT 8U +/* Field Value: DUMP0_SELECT1__FRAMEGEN, Source is FrameGen#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__FRAMEGEN 0U +/* Field Value: DUMP0_SELECT1__GAMMACOR, Source is GammaCor#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__GAMMACOR 0x1U +/* Field Value: DUMP0_SELECT1__MATRIX, Source is Matrix#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__MATRIX 0x2U +/* Field Value: DUMP0_SELECT1__DITHER, Source is Dither#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP0_SELECT1__DITHER 0x3U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1_MASK 0xC00U +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1_SHIFT 10U +/* Field Value: DUMP1_SELECT1__FRAMEGEN, Source is FrameGen#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__FRAMEGEN 0U +/* Field Value: DUMP1_SELECT1__GAMMACOR, Source is GammaCor#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__GAMMACOR 0x1U +/* Field Value: DUMP1_SELECT1__MATRIX, Source is Matrix#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__MATRIX 0x2U +/* Field Value: DUMP1_SELECT1__DITHER, Source is Dither#1 output. */ +#define IMXDPUV1_DISENGCFG_SRCSELECT1_DUMP1_SELECT1__DITHER 0x3U + +/* Register: IMXDPUV1_framegen0_LockUnlock */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK ((uint32_t)(0xB800)) +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FRAMEGEN0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_framegen0_LockStatus */ +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS ((uint32_t)(0xB804)) +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FRAMEGEN0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_framegen0_FgStCtrl */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL ((uint32_t)(0xB808)) +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_SHDEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_SHDEN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE_SHIFT 1U +/* Field Value: FGSYNCMODE__OFF, No side-by-side synchronization. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__OFF 0U +/* Field Value: FGSYNCMODE__MASTER, Framegen is master. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__MASTER 0x1U +/* Field Value: FGSYNCMODE__SLAVE_CYC, Framegen is slave. Runs in cyclic synchronization + * mode. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__SLAVE_CYC 0x2U +/* Field Value: FGSYNCMODE__SLAVE_ONCE, Framegen is slave. Runs in one time + * synchronization mode. */ +#define IMXDPUV1_FRAMEGEN0_FGSTCTRL_FGSYNCMODE__SLAVE_ONCE 0x3U + +/* Register: IMXDPUV1_framegen0_HtCfg1 */ +#define IMXDPUV1_FRAMEGEN0_HTCFG1 ((uint32_t)(0xB80C)) +#define IMXDPUV1_FRAMEGEN0_HTCFG1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FRAMEGEN0_HTCFG1_RESET_VALUE 0x18F0140U +#define IMXDPUV1_FRAMEGEN0_HTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_HTCFG1_HTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_HtCfg2 */ +#define IMXDPUV1_FRAMEGEN0_HTCFG2 ((uint32_t)(0xB810)) +#define IMXDPUV1_FRAMEGEN0_HTCFG2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FRAMEGEN0_HTCFG2_RESET_VALUE 0x8047001FU +#define IMXDPUV1_FRAMEGEN0_HTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_HTCFG2_HSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_VtCfg1 */ +#define IMXDPUV1_FRAMEGEN0_VTCFG1 ((uint32_t)(0xB814)) +#define IMXDPUV1_FRAMEGEN0_VTCFG1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FRAMEGEN0_VTCFG1_RESET_VALUE 0xFC00F0U +#define IMXDPUV1_FRAMEGEN0_VTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_VTCFG1_VTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_VtCfg2 */ +#define IMXDPUV1_FRAMEGEN0_VTCFG2 ((uint32_t)(0xB818)) +#define IMXDPUV1_FRAMEGEN0_VTCFG2_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FRAMEGEN0_VTCFG2_RESET_VALUE 0x80090003U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_VTCFG2_VSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int0Config */ +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG ((uint32_t)(0xB81C)) +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT0CONFIG_INT0EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int1Config */ +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG ((uint32_t)(0xB820)) +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT1CONFIG_INT1EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int2Config */ +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG ((uint32_t)(0xB824)) +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT2CONFIG_INT2EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_Int3Config */ +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG ((uint32_t)(0xB828)) +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_INT3CONFIG_INT3EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_PKickConfig */ +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG ((uint32_t)(0xB82C)) +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKINT0EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKINT0EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_PKICKCONFIG_PKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_SKickConfig */ +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG ((uint32_t)(0xB830)) +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKINT1EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG_SHIFT 30U +/* Field Value: SKICKTRIG__INTERNAL, Use internal skick signal, trigger point + * defined by SKickRow and SKickCol. */ +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG__INTERNAL 0U +/* Field Value: SKICKTRIG__EXTERNAL, Use external skick input as trigger. */ +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKTRIG__EXTERNAL 0x1U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN0_SKICKCONFIG_SKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen0_SecStatConfig */ +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG ((uint32_t)(0xB834)) +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_RESET_VALUE 0x112U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVGOODFRAMES_MASK 0xFU +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVGOODFRAMES_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVBADFRAMES_MASK 0xF0U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVBADFRAMES_SHIFT 4U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVSKEWINRANGE_MASK 0xF00U +#define IMXDPUV1_FRAMEGEN0_SECSTATCONFIG_LEVSKEWINRANGE_SHIFT 8U + +/* Register: IMXDPUV1_framegen0_FgSRCR1 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1 ((uint32_t)(0xB838)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE_SHIFT 1U +/* Field Value: SRMODE__OFF, Skew Regulation is off. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__OFF 0U +/* Field Value: SRMODE__HREG, Horizontal regulation enabled. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__HREG 0x1U +/* Field Value: SRMODE__VREG, Vertical regulation enabled. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__VREG 0x2U +/* Field Value: SRMODE__BOTH, Both regulation modes are enabled. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRMODE__BOTH 0x3U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRADJ_MASK 0x8U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRADJ_SHIFT 3U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREVEN_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREVEN_SHIFT 4U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRFASTSYNC_MASK 0x20U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRFASTSYNC_SHIFT 5U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQALIGN_MASK 0x40U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQALIGN_SHIFT 6U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL_MASK 0x180U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL_SHIFT 7U +/* Field Value: SRQVAL__ZERO, Fixed two LSB values of HTOTAL are 0b00. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__ZERO 0U +/* Field Value: SRQVAL__ONE, Fixed two LSB values of HTOTAL are 0b01. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__ONE 0x1U +/* Field Value: SRQVAL__TWO, Fixed two LSB values of HTOTAL are 0b10. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__TWO 0x2U +/* Field Value: SRQVAL__THREE, Fixed two LSB values of HTOTAL are 0b11. */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRQVAL__THREE 0x3U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRDBGDISP_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SRDBGDISP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREPOFF_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR1_SREPOFF_SHIFT 17U + +/* Register: IMXDPUV1_framegen0_FgSRCR2 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR2 ((uint32_t)(0xB83C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_RESET_VALUE 0x1B70188U +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR2_HTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgSRCR3 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR3 ((uint32_t)(0xB840)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_RESET_VALUE 0x11500FBU +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_FGSRCR3_VTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgSRCR4 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR4 ((uint32_t)(0xB844)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_RESET_VALUE 0xC8U +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_TARGETSKEW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR4_TARGETSKEW_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSRCR5 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR5 ((uint32_t)(0xB848)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_SYNCRANGELOW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR5_SYNCRANGELOW_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSRCR6 */ +#define IMXDPUV1_FRAMEGEN0_FGSRCR6 ((uint32_t)(0xB84C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_RESET_VALUE 0x190U +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_SYNCRANGEHIGH_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRCR6_SYNCRANGEHIGH_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgKSDR */ +#define IMXDPUV1_FRAMEGEN0_FGKSDR ((uint32_t)(0xB850)) +#define IMXDPUV1_FRAMEGEN0_FGKSDR_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FRAMEGEN0_FGKSDR_RESET_VALUE 0x20002U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGKSDR_PCNTCPLMAX_MASK 0x7U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_PCNTCPLMAX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_SCNTCPLMAX_MASK 0x70000U +#define IMXDPUV1_FRAMEGEN0_FGKSDR_SCNTCPLMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_PaCfg */ +#define IMXDPUV1_FRAMEGEN0_PACFG ((uint32_t)(0xB854)) +#define IMXDPUV1_FRAMEGEN0_PACFG_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FRAMEGEN0_PACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN0_PACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_PACFG_PSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_SaCfg */ +#define IMXDPUV1_FRAMEGEN0_SACFG ((uint32_t)(0xB858)) +#define IMXDPUV1_FRAMEGEN0_SACFG_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FRAMEGEN0_SACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN0_SACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN0_SACFG_SSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgInCtrl */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL ((uint32_t)(0xB85C)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_RESET_VALUE 0x6U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM_MASK 0x7U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM_SHIFT 0U +/* Field Value: FGDM__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__BLACK 0U +/* Field Value: FGDM__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__CONSTCOL 0x1U +/* Field Value: FGDM__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__PRIM 0x2U +/* Field Value: FGDM__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC 0x3U +/* Field Value: FGDM__PRIM_ON_TOP, Both inputs overlaid with primary on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__PRIM_ON_TOP 0x4U +/* Field Value: FGDM__SEC_ON_TOP, Both inputs overlaid with secondary on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__SEC_ON_TOP 0x5U +/* Field Value: FGDM__TEST, White color background with test pattern is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_FGDM__TEST 0x6U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA_MASK 0x8U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENPRIMALPHA_SHIFT 3U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_FGINCTRL_ENSECALPHA_SHIFT 4U + +/* Register: IMXDPUV1_framegen0_FgInCtrlPanic */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC ((uint32_t)(0xB860)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC_MASK 0x7U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC_SHIFT 0U +/* Field Value: FGDMPANIC__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__BLACK 0U +/* Field Value: FGDMPANIC__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__CONSTCOL 0x1U +/* Field Value: FGDMPANIC__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__PRIM 0x2U +/* Field Value: FGDMPANIC__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__SEC 0x3U +/* Field Value: FGDMPANIC__PRIM_ON_TOP, Both inputs overlaid with primary + * on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__PRIM_ON_TOP 0x4U +/* Field Value: FGDMPANIC__SEC_ON_TOP, Both inputs overlaid with secondary + * on top. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__SEC_ON_TOP 0x5U +/* Field Value: FGDMPANIC__TEST, White color background with test pattern + * is shown. */ +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_FGDMPANIC__TEST 0x6U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC_MASK 0x8U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENPRIMALPHAPANIC_SHIFT 3U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC_MASK 0x10U +#define IMXDPUV1_FRAMEGEN0_FGINCTRLPANIC_ENSECALPHAPANIC_SHIFT 4U + +/* Register: IMXDPUV1_framegen0_FgCCR */ +#define IMXDPUV1_FRAMEGEN0_FGCCR ((uint32_t)(0xB864)) +#define IMXDPUV1_FRAMEGEN0_FGCCR_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FRAMEGEN0_FGCCR_RESET_VALUE 0x7FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCCR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE_MASK 0x3FFU +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCBLUE_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN_MASK 0xFFC00U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCGREEN_SHIFT 10U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCRED_MASK 0x3FF00000U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCRED_SHIFT 20U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN0_FGCCR_CCALPHA_SHIFT 30U + +/* Register: IMXDPUV1_framegen0_FgEnable */ +#define IMXDPUV1_FRAMEGEN0_FGENABLE ((uint32_t)(0xB868)) +#define IMXDPUV1_FRAMEGEN0_FGENABLE_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FRAMEGEN0_FGENABLE_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGENABLE_FGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSlr */ +#define IMXDPUV1_FRAMEGEN0_FGSLR ((uint32_t)(0xB86C)) +#define IMXDPUV1_FRAMEGEN0_FGSLR_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FRAMEGEN0_FGSLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSLR_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSLR_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgEnSts */ +#define IMXDPUV1_FRAMEGEN0_FGENSTS ((uint32_t)(0xB870)) +#define IMXDPUV1_FRAMEGEN0_FGENSTS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FRAMEGEN0_FGENSTS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGENSTS_ENSTS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_ENSTS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_PANICSTAT_MASK 0x2U +#define IMXDPUV1_FRAMEGEN0_FGENSTS_PANICSTAT_SHIFT 1U + +/* Register: IMXDPUV1_framegen0_FgTimeStamp */ +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP ((uint32_t)(0xB874)) +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_LINEINDEX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX_MASK 0xFFFFC000U +#define IMXDPUV1_FRAMEGEN0_FGTIMESTAMP_FRAMEINDEX_SHIFT 14U + +/* Register: IMXDPUV1_framegen0_FgChStat */ +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT ((uint32_t)(0xB878)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PFIFOEMPTY_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT_MASK 0x100U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_PRIMSYNCSTAT_SHIFT 8U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SFIFOEMPTY_SHIFT 16U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SKEWRANGEERR_SHIFT 17U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT_MASK 0x1000000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTAT_SECSYNCSTAT_SHIFT 24U + +/* Register: IMXDPUV1_framegen0_FgChStatClr */ +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR ((uint32_t)(0xB87C)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRPRIMSTAT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN0_FGCHSTATCLR_CLRSECSTAT_SHIFT 16U + +/* Register: IMXDPUV1_framegen0_FgSkewMon */ +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON ((uint32_t)(0xB880)) +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_SKEWMON_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSKEWMON_SKEWMON_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSFifoMin */ +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN ((uint32_t)(0xB884)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_SFIFOMIN_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMIN_SFIFOMIN_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSFifoMax */ +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX ((uint32_t)(0xB888)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_SFIFOMAX_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOMAX_SFIFOMAX_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSFifoFillClr */ +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR ((uint32_t)(0xB88C)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_SFIFOFILLCLR_MASK 0x1U +#define IMXDPUV1_FRAMEGEN0_FGSFIFOFILLCLR_SFIFOFILLCLR_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSrEpD */ +#define IMXDPUV1_FRAMEGEN0_FGSREPD ((uint32_t)(0xB890)) +#define IMXDPUV1_FRAMEGEN0_FGSREPD_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FRAMEGEN0_FGSREPD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSREPD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSREPD_EPVAL_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSREPD_EPVAL_SHIFT 0U + +/* Register: IMXDPUV1_framegen0_FgSrFtD */ +#define IMXDPUV1_FRAMEGEN0_FGSRFTD ((uint32_t)(0xB894)) +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_FRTOT_MASK 0xFFFFFFFU +#define IMXDPUV1_FRAMEGEN0_FGSRFTD_FRTOT_SHIFT 0U + +/* Register: IMXDPUV1_matrix0_LockUnlock */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK ((uint32_t)(0xBC00)) +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix0_LockStatus */ +#define IMXDPUV1_MATRIX0_LOCKSTATUS ((uint32_t)(0xBC04)) +#define IMXDPUV1_MATRIX0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix0_StaticControl */ +#define IMXDPUV1_MATRIX0_STATICCONTROL ((uint32_t)(0xBC08)) +#define IMXDPUV1_MATRIX0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX0_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX0_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix0_Control */ +#define IMXDPUV1_MATRIX0_CONTROL ((uint32_t)(0xBC0C)) +#define IMXDPUV1_MATRIX0_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX0_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX0_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix0_Red0 */ +#define IMXDPUV1_MATRIX0_RED0 ((uint32_t)(0xBC10)) +#define IMXDPUV1_MATRIX0_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX0_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX0_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX0_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Red1 */ +#define IMXDPUV1_MATRIX0_RED1 ((uint32_t)(0xBC14)) +#define IMXDPUV1_MATRIX0_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX0_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX0_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Green0 */ +#define IMXDPUV1_MATRIX0_GREEN0 ((uint32_t)(0xBC18)) +#define IMXDPUV1_MATRIX0_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX0_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX0_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX0_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Green1 */ +#define IMXDPUV1_MATRIX0_GREEN1 ((uint32_t)(0xBC1C)) +#define IMXDPUV1_MATRIX0_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX0_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX0_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Blue0 */ +#define IMXDPUV1_MATRIX0_BLUE0 ((uint32_t)(0xBC20)) +#define IMXDPUV1_MATRIX0_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX0_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX0_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Blue1 */ +#define IMXDPUV1_MATRIX0_BLUE1 ((uint32_t)(0xBC24)) +#define IMXDPUV1_MATRIX0_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX0_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX0_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX0_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Alpha0 */ +#define IMXDPUV1_MATRIX0_ALPHA0 ((uint32_t)(0xBC28)) +#define IMXDPUV1_MATRIX0_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX0_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX0_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_Alpha1 */ +#define IMXDPUV1_MATRIX0_ALPHA1 ((uint32_t)(0xBC2C)) +#define IMXDPUV1_MATRIX0_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX0_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX0_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX0_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_OffsetVector0 */ +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0 ((uint32_t)(0xBC30)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_OffsetVector1 */ +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1 ((uint32_t)(0xBC34)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX0_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix0_LastControlWord */ +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD ((uint32_t)(0xBC38)) +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX0_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_gammacor0_LockUnlock */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK ((uint32_t)(0xC000)) +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_GAMMACOR0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_gammacor0_LockStatus */ +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS ((uint32_t)(0xC004)) +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_GAMMACOR0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_gammacor0_StaticControl */ +#define IMXDPUV1_GAMMACOR0_STATICCONTROL ((uint32_t)(0xC008)) +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_RESET_VALUE 0xEU +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_BLUEWRITEENABLE_MASK 0x2U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_BLUEWRITEENABLE_SHIFT 1U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_GREENWRITEENABLE_MASK 0x4U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_GREENWRITEENABLE_SHIFT 2U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_REDWRITEENABLE_MASK 0x8U +#define IMXDPUV1_GAMMACOR0_STATICCONTROL_REDWRITEENABLE_SHIFT 3U + +/* Register: IMXDPUV1_gammacor0_LutStart */ +#define IMXDPUV1_GAMMACOR0_LUTSTART ((uint32_t)(0xC00C)) +#define IMXDPUV1_GAMMACOR0_LUTSTART_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_GAMMACOR0_LUTSTART_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LUTSTART_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTBLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTBLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTRED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR0_LUTSTART_STARTRED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor0_LutDeltas */ +#define IMXDPUV1_GAMMACOR0_LUTDELTAS ((uint32_t)(0xC010)) +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_RESET_MASK 0xC0000000U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTABLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTABLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTAGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTAGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTARED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR0_LUTDELTAS_DELTARED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor0_Control */ +#define IMXDPUV1_GAMMACOR0_CONTROL ((uint32_t)(0xC014)) +#define IMXDPUV1_GAMMACOR0_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_GAMMACOR0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed + * to the output. */ +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__GAMMACOR, Module in gamma correction mode. */ +#define IMXDPUV1_GAMMACOR0_CONTROL_MODE__GAMMACOR 0x1U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_GAMMACOR0_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_gammacor0_Status */ +#define IMXDPUV1_GAMMACOR0_STATUS ((uint32_t)(0xC018)) +#define IMXDPUV1_GAMMACOR0_STATUS_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_GAMMACOR0_STATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_GAMMACOR0_STATUS_WRITETIMEOUT_SHIFT 0U + +/* Register: IMXDPUV1_gammacor0_LastControlWord */ +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD ((uint32_t)(0xC01C)) +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR0_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_dither0_LockUnlock */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK ((uint32_t)(0xC400)) +#define IMXDPUV1_DITHER0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DITHER0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DITHER0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_dither0_LockStatus */ +#define IMXDPUV1_DITHER0_LOCKSTATUS ((uint32_t)(0xC404)) +#define IMXDPUV1_DITHER0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DITHER0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_DITHER0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_DITHER0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_DITHER0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_DITHER0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_DITHER0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_dither0_Control */ +#define IMXDPUV1_DITHER0_CONTROL ((uint32_t)(0xC408)) +#define IMXDPUV1_DITHER0_CONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DITHER0_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_DITHER0_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the Dither Unit, + * all other settings are ignored. */ +#define IMXDPUV1_DITHER0_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Dither Unit is active. */ +#define IMXDPUV1_DITHER0_CONTROL_MODE__ACTIVE 0x1U + +/* Register: IMXDPUV1_dither0_DitherControl */ +#define IMXDPUV1_DITHER0_DITHERCONTROL ((uint32_t)(0xC40C)) +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DITHER0_DITHERCONTROL_RESET_VALUE 0x300222U +#define IMXDPUV1_DITHER0_DITHERCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT_MASK 0x7U +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT_SHIFT 0U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO8, Reduces blue component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO8 0x2U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO7, Reduces blue component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO7 0x3U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO6, Reduces blue component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO6 0x4U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO5, Reduces blue component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO5 0x5U +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT_MASK 0x70U +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT_SHIFT 4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO8, Reduces green component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO8 0x2U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO7, Reduces green component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO7 0x3U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO6, Reduces green component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO6 0x4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO5, Reduces green component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO5 0x5U +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT_MASK 0x700U +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT_SHIFT 8U +/* Field Value: RED_RANGE_SELECT__RED_10TO8, Reduces red component width from + * 10 bit to 8bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO8 0x2U +/* Field Value: RED_RANGE_SELECT__RED_10TO7, Reduces red component width from + * 10 bit to 7bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO7 0x3U +/* Field Value: RED_RANGE_SELECT__RED_10TO6, Reduces red component width from + * 10 bit to 6bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO6 0x4U +/* Field Value: RED_RANGE_SELECT__RED_10TO5, Reduces red component width from + * 10 bit to 5bit. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO5 0x5U +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT_MASK 0x10000U +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT_SHIFT 16U +/* Field Value: OFFSET_SELECT__OFFS_SPATIAL, Offset is a bayer matrix value, + * which is selected according to pixel frame position. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT__OFFS_SPATIAL 0U +/* Field Value: OFFSET_SELECT__OFFS_TEMPORAL, Offset is the sum from a bayer + * matrix value, which is selected according to pixel frame position, + * and a value from a regular sequence, which changes each frame. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_OFFSET_SELECT__OFFS_TEMPORAL 0x1U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT_MASK 0x300000U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT_SHIFT 20U +/* Field Value: ALGO_SELECT__NO_CORRECTION, Best possible resolution for most + * dark colors. Adds a diminutive offset to overall image brightness. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__NO_CORRECTION 0x1U +/* Field Value: ALGO_SELECT__BRIGHTNESS_CORRECTION, Preserves overall image + * brightness. Cannot resolve most dark and most bright colors. All codes + * in-between are distributed perfectly smooth. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__BRIGHTNESS_CORRECTION 0x2U +/* Field Value: ALGO_SELECT__CONTRAST_CORRECTION, Preserves overall image + * brightness. Best possible distribution of color codes over complete range. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALGO_SELECT__CONTRAST_CORRECTION 0x3U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE_MASK 0x3000000U +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE_SHIFT 24U +/* Field Value: ALPHA_MODE__DISABLE, The alpha bit is not considered. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__DISABLE 0U +/* Field Value: ALPHA_MODE__ENABLE_BY1, Red, green and blue components are + * only dithered, if the alpha bit is 1. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__ENABLE_BY1 0x1U +/* Field Value: ALPHA_MODE__ENABLE_BY0, Red, green and blue components are + * only dithered, if the alpha bit is 0. */ +#define IMXDPUV1_DITHER0_DITHERCONTROL_ALPHA_MODE__ENABLE_BY0 0x2U + +/* Register: IMXDPUV1_dither0_Release */ +#define IMXDPUV1_DITHER0_RELEASE ((uint32_t)(0xC410)) +#define IMXDPUV1_DITHER0_RELEASE_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DITHER0_RELEASE_RESET_VALUE 0U +#define IMXDPUV1_DITHER0_RELEASE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER0_RELEASE_SUBVERSION_MASK 0xFFU +#define IMXDPUV1_DITHER0_RELEASE_SUBVERSION_SHIFT 0U +#define IMXDPUV1_DITHER0_RELEASE_VERSION_MASK 0xFF00U +#define IMXDPUV1_DITHER0_RELEASE_VERSION_SHIFT 8U + +/* Register: IMXDPUV1_tcon0_SSqCnts */ +#define IMXDPUV1_TCON0_SSQCNTS ((uint32_t)(0xC800)) +#define IMXDPUV1_TCON0_SSQCNTS_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON0_SSQCNTS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SSQCNTS_RESET_MASK 0U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQY_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQY_SHIFT 0U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_FIELD_MASK 0x8000U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_FIELD_SHIFT 15U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQX_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_SEQX_SHIFT 16U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_OUT_MASK 0x80000000U +#define IMXDPUV1_TCON0_SSQCNTS_SSQCNTS_OUT_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_LockUnlock */ +#define IMXDPUV1_TCON0_LOCKUNLOCK ((uint32_t)(0xCC00)) +#define IMXDPUV1_TCON0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_TCON0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_TCON0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_tcon0_LockStatus */ +#define IMXDPUV1_TCON0_LOCKSTATUS ((uint32_t)(0xCC04)) +#define IMXDPUV1_TCON0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_TCON0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_TCON0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_TCON0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_TCON0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_TCON0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_TCON0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_tcon0_SSqCycle */ +#define IMXDPUV1_TCON0_SSQCYCLE ((uint32_t)(0xCC08)) +#define IMXDPUV1_TCON0_SSQCYCLE_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_TCON0_SSQCYCLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SSQCYCLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SSQCYCLE_SSQCYCLE_MASK 0x3FU +#define IMXDPUV1_TCON0_SSQCYCLE_SSQCYCLE_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SWreset */ +#define IMXDPUV1_TCON0_SWRESET ((uint32_t)(0xCC0C)) +#define IMXDPUV1_TCON0_SWRESET_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_TCON0_SWRESET_RESET_VALUE 0x3FC00410U +#define IMXDPUV1_TCON0_SWRESET_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SWRESET_SWRESET_MASK 0x1U +#define IMXDPUV1_TCON0_SWRESET_SWRESET_SHIFT 0U +/* Field Value: SWRESET__OPERATION, operation mode */ +#define IMXDPUV1_TCON0_SWRESET_SWRESET__OPERATION 0U +/* Field Value: SWRESET__SWRESET, So long SWReset = 0x1 tcon is in 'SW reset + * state' and it is released by internal logic (SWReset is released and + * end of frame arrived), read: 0b: reset not active 1b: reset active (that + * means NO pixel of video frame is excepted until 'SW reset state' + * is released) */ +#define IMXDPUV1_TCON0_SWRESET_SWRESET__SWRESET 0x1U +#define IMXDPUV1_TCON0_SWRESET_ENRESETWORD_MASK 0xFFF0U +#define IMXDPUV1_TCON0_SWRESET_ENRESETWORD_SHIFT 4U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDEND_MASK 0xFF0000U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDEND_SHIFT 16U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDSTART_MASK 0xFF000000U +#define IMXDPUV1_TCON0_SWRESET_RESETWORDSTART_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_TCON_CTRL */ +#define IMXDPUV1_TCON0_TCON_CTRL ((uint32_t)(0xCC10)) +#define IMXDPUV1_TCON0_TCON_CTRL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_TCON0_TCON_CTRL_RESET_VALUE 0x1401408U +#define IMXDPUV1_TCON0_TCON_CTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE_MASK 0x3U +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE_SHIFT 0U +/* Field Value: CHANNELMODE__SINGLE, Single pixel mode. Both channels channel + * are active at full pixel clock. If bitmap of both panels are the same, + * both panels are identical */ +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__SINGLE 0U +/* Field Value: CHANNELMODE__DUAL_INTERLEAVED, Dual pixel mode. Both channels + * are active at half the pixel clock. 1st channel drives display columns + * with even and 2nd one with odd index. */ +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__DUAL_INTERLEAVED 0x1U +/* Field Value: CHANNELMODE__DUAL_SPLIT, Dual pixel mode. Both channels are + * active at half the pixel clock. 1st channel drives the left and 2nd + * one the righ half of the display. Note : data_en is needed in this mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_CHANNELMODE__DUAL_SPLIT 0x2U +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC_MASK 0x4U +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC_SHIFT 2U +/* Field Value: TCON_SYNC__H_VLAST, tcon timing generator synchronized to + * hlast, vlast */ +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC__H_VLAST 0U +/* Field Value: TCON_SYNC__H_VSYNC, tcon timing generator synchronized to + * hsync, vsync where horizontal synchronization is synchronized at the falling + * edge of hsync */ +#define IMXDPUV1_TCON0_TCON_CTRL_TCON_SYNC__H_VSYNC 0x1U +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS_MASK 0x8U +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS_SHIFT 3U +/* Field Value: BYPASS__TCON_MODE, tcon operation mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS__TCON_MODE 0U +/* Field Value: BYPASS__BYPASS_MODE, tcon in Bypass mode. input pixel and + * its sync-signals are bypassed to tcon-output */ +#define IMXDPUV1_TCON0_TCON_CTRL_BYPASS__BYPASS_MODE 0x1U +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL_MASK 0xF0U +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL_SHIFT 4U +/* Field Value: INV_CTRL__DISABLE, Disable inversion control */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__DISABLE 0U +/* Field Value: INV_CTRL__RGB_2_BITS, Enable inversion control for number + * of RGB-Bits = 2 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_2_BITS 0x1U +/* Field Value: INV_CTRL__RGB_4_BITS, Enable inversion control for number + * of RGB-Bits = 4 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_4_BITS 0x2U +/* Field Value: INV_CTRL__RGB_6_BITS, Enable inversion control for number + * of RGB-Bits = 6 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_6_BITS 0x3U +/* Field Value: INV_CTRL__RGB_8_BITS, Enable inversion control for number + * of RGB-Bits = 8 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_8_BITS 0x4U +/* Field Value: INV_CTRL__RGB_10_BITS, Enable inversion control for number + * of RGB-Bits = 10 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_10_BITS 0x5U +/* Field Value: INV_CTRL__RGB_12_BITS, Enable inversion control for number + * of RGB-Bits = 12 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_12_BITS 0x6U +/* Field Value: INV_CTRL__RGB_14_BITS, Enable inversion control for number + * of RGB-Bits = 14 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_14_BITS 0x7U +/* Field Value: INV_CTRL__RGB_16_BITS, Enable inversion control for number + * of RGB-Bits = 16 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_16_BITS 0x8U +/* Field Value: INV_CTRL__RGB_18_BITS, Enable inversion control for number + * of RGB-Bits = 18 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_18_BITS 0x9U +/* Field Value: INV_CTRL__RGB_20_BITS, Enable inversion control for number + * of RGB-Bits = 20 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_20_BITS 0xAU +/* Field Value: INV_CTRL__RGB_22_BITS, Enable inversion control for number + * of RGB-Bits = 22 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_22_BITS 0xBU +/* Field Value: INV_CTRL__RGB_24_BITS, Enable inversion control for number + * of RGB-Bits = 24 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_24_BITS 0xCU +/* Field Value: INV_CTRL__RGB_26_BITS, Enable inversion control for number + * of RGB-Bits = 26 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_26_BITS 0xDU +/* Field Value: INV_CTRL__RGB_28_BITS, Enable inversion control for number + * of RGB-Bits = 28 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_28_BITS 0xEU +/* Field Value: INV_CTRL__RGB_30_BITS, Enable inversion control for number + * of RGB-Bits = 30 */ +#define IMXDPUV1_TCON0_TCON_CTRL_INV_CTRL__RGB_30_BITS 0xFU +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS_MASK 0x100U +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS_SHIFT 8U +/* Field Value: ENLVDS__ENABLE_LVDS, Enable LVDS , TTL and RSDS are disable + * */ +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS__ENABLE_LVDS 0x1U +/* Field Value: ENLVDS__DISABLE_LVDS, Disable LVDS, Enable TTL and RSDS */ +#define IMXDPUV1_TCON0_TCON_CTRL_ENLVDS__DISABLE_LVDS 0U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE_MASK 0x200U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE_SHIFT 9U +/* Field Value: LVDSMODE__MINI_LVDS, MiniLVDS */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE__MINI_LVDS 0x1U +/* Field Value: LVDSMODE__LVDS, LVDS Mode, refered to OpenLDI */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDSMODE__LVDS 0U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE_MASK 0x400U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE_SHIFT 10U +/* Field Value: LVDS_BALANCE__BALANCED, LVDS operates in 24 bits Balanced + * Mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__BALANCED 0x1U +/* Field Value: LVDS_BALANCE__UNBALANCED, LVDS operates in 24 bits Unbalanced + * Mode */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_BALANCE__UNBALANCED 0U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV_MASK 0x800U +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV_SHIFT 11U +/* Field Value: LVDS_CLOCK_INV__INV, Invert LVDS Clock */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV__INV 0x1U +/* Field Value: LVDS_CLOCK_INV__NON_INV, NON-Invert LVDS Clock */ +#define IMXDPUV1_TCON0_TCON_CTRL_LVDS_CLOCK_INV__NON_INV 0U +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE_MASK 0x7000U +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE_SHIFT 12U +/* Field Value: MINILVDS_OPCODE__MODE_3PAIRS, MiniLVDS operates in 6 and 8 + * bit data, three pairs */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_3PAIRS 0U +/* Field Value: MINILVDS_OPCODE__MODE_4PAIRS, Not Implemented */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS 0x1U +/* Field Value: MINILVDS_OPCODE__MODE_5PAIRS, Not Implemented */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_5PAIRS 0x2U +/* Field Value: MINILVDS_OPCODE__MODE_6PAIRS, MiniLVDS operates in 6 and 8 + * bit data, six pairs */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__MODE_6PAIRS 0x3U +/* Field Value: MINILVDS_OPCODE__RESERVED1, RESERVED1 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED1 0x4U +/* Field Value: MINILVDS_OPCODE__RESERVED2, RESERVED2 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED2 0x5U +/* Field Value: MINILVDS_OPCODE__RESERVED3, RESERVED3 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED3 0x6U +/* Field Value: MINILVDS_OPCODE__RESERVED4, RESERVED4 */ +#define IMXDPUV1_TCON0_TCON_CTRL_MINILVDS_OPCODE__RESERVED4 0x7U +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP_MASK 0x8000U +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP_SHIFT 15U +/* Field Value: DUAL_SWAP__SWAP, swapping pixels between lower-channel and + * upper-channel */ +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP__SWAP 0x1U +/* Field Value: DUAL_SWAP__NON_SWAP, NON-swapping pixels between lower-channel + * and upper-channel */ +#define IMXDPUV1_TCON0_TCON_CTRL_DUAL_SWAP__NON_SWAP 0U +#define IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION_MASK 0x3FFF0000U +#define IMXDPUV1_TCON0_TCON_CTRL_SPLITPOSITION_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_RSDSInvCtrl */ +#define IMXDPUV1_TCON0_RSDSINVCTRL ((uint32_t)(0xCC14)) +#define IMXDPUV1_TCON0_RSDSINVCTRL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_TCON0_RSDSINVCTRL_RESET_VALUE 0U +#define IMXDPUV1_TCON0_RSDSINVCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_MASK 0x7FFFU +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_SHIFT 0U +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_DUAL_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_RSDSINVCTRL_RSDS_INV_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_MapBit3_0 */ +#define IMXDPUV1_TCON0_MAPBIT3_0 ((uint32_t)(0xCC18)) +#define IMXDPUV1_TCON0_MAPBIT3_0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_TCON0_MAPBIT3_0_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON0_MAPBIT3_0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT0_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT0_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT1_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT1_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT2_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT2_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT3_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT3_0_MAPBIT3_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit7_4 */ +#define IMXDPUV1_TCON0_MAPBIT7_4 ((uint32_t)(0xCC1C)) +#define IMXDPUV1_TCON0_MAPBIT7_4_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_TCON0_MAPBIT7_4_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON0_MAPBIT7_4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT4_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT4_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT5_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT5_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT6_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT6_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT7_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT7_4_MAPBIT7_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit11_8 */ +#define IMXDPUV1_TCON0_MAPBIT11_8 ((uint32_t)(0xCC20)) +#define IMXDPUV1_TCON0_MAPBIT11_8_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_TCON0_MAPBIT11_8_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON0_MAPBIT11_8_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT8_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT8_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT9_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT9_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT10_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT10_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT11_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT11_8_MAPBIT11_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit15_12 */ +#define IMXDPUV1_TCON0_MAPBIT15_12 ((uint32_t)(0xCC24)) +#define IMXDPUV1_TCON0_MAPBIT15_12_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_TCON0_MAPBIT15_12_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON0_MAPBIT15_12_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT12_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT12_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT13_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT13_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT14_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT14_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT15_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT15_12_MAPBIT15_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit19_16 */ +#define IMXDPUV1_TCON0_MAPBIT19_16 ((uint32_t)(0xCC28)) +#define IMXDPUV1_TCON0_MAPBIT19_16_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_TCON0_MAPBIT19_16_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON0_MAPBIT19_16_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT16_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT16_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT17_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT17_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT18_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT18_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT19_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT19_16_MAPBIT19_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit23_20 */ +#define IMXDPUV1_TCON0_MAPBIT23_20 ((uint32_t)(0xCC2C)) +#define IMXDPUV1_TCON0_MAPBIT23_20_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_TCON0_MAPBIT23_20_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON0_MAPBIT23_20_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT20_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT20_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT21_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT21_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT22_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT22_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT23_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT23_20_MAPBIT23_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit27_24 */ +#define IMXDPUV1_TCON0_MAPBIT27_24 ((uint32_t)(0xCC30)) +#define IMXDPUV1_TCON0_MAPBIT27_24_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_TCON0_MAPBIT27_24_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON0_MAPBIT27_24_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT24_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT24_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT25_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT25_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT26_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT26_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT27_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT27_24_MAPBIT27_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit31_28 */ +#define IMXDPUV1_TCON0_MAPBIT31_28 ((uint32_t)(0xCC34)) +#define IMXDPUV1_TCON0_MAPBIT31_28_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_TCON0_MAPBIT31_28_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON0_MAPBIT31_28_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT28_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT28_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT29_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT29_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT30_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT30_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT31_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT31_28_MAPBIT31_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit34_32 */ +#define IMXDPUV1_TCON0_MAPBIT34_32 ((uint32_t)(0xCC38)) +#define IMXDPUV1_TCON0_MAPBIT34_32_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_TCON0_MAPBIT34_32_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON0_MAPBIT34_32_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT32_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT32_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT33_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT33_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT34_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT34_32_MAPBIT34_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_MapBit3_0_Dual */ +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL ((uint32_t)(0xCC3C)) +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT0_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT0_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT1_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT1_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT2_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT2_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT3_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT3_0_DUAL_MAPBIT3_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit7_4_Dual */ +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL ((uint32_t)(0xCC40)) +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT4_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT4_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT5_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT5_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT6_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT6_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT7_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT7_4_DUAL_MAPBIT7_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit11_8_Dual */ +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL ((uint32_t)(0xCC44)) +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT8_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT8_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT9_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT9_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT10_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT10_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT11_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT11_8_DUAL_MAPBIT11_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit15_12_Dual */ +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL ((uint32_t)(0xCC48)) +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT12_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT12_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT13_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT13_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT14_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT14_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT15_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT15_12_DUAL_MAPBIT15_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit19_16_Dual */ +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL ((uint32_t)(0xCC4C)) +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT16_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT16_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT17_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT17_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT18_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT18_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT19_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT19_16_DUAL_MAPBIT19_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit23_20_Dual */ +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL ((uint32_t)(0xCC50)) +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT20_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT20_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT21_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT21_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT22_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT22_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT23_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT23_20_DUAL_MAPBIT23_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit27_24_Dual */ +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL ((uint32_t)(0xCC54)) +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT24_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT24_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT25_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT25_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT26_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT26_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT27_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT27_24_DUAL_MAPBIT27_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit31_28_Dual */ +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL ((uint32_t)(0xCC58)) +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT28_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT28_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT29_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT29_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT30_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT30_DUAL_SHIFT 16U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT31_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON0_MAPBIT31_28_DUAL_MAPBIT31_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon0_MapBit34_32_Dual */ +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL ((uint32_t)(0xCC5C)) +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT32_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT32_DUAL_SHIFT 0U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT33_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT33_DUAL_SHIFT 8U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT34_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON0_MAPBIT34_32_DUAL_MAPBIT34_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon0_SPG0PosOn */ +#define IMXDPUV1_TCON0_SPG0POSON ((uint32_t)(0xCC60)) +#define IMXDPUV1_TCON0_SPG0POSON_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_TCON0_SPG0POSON_RESET_VALUE 0x1480000U +#define IMXDPUV1_TCON0_SPG0POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_Y0_SHIFT 0U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_X0_SHIFT 16U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG0POSON_SPGPSON_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG0MaskOn */ +#define IMXDPUV1_TCON0_SPG0MASKON ((uint32_t)(0xCC64)) +#define IMXDPUV1_TCON0_SPG0MASKON_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_TCON0_SPG0MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG0MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKON_SPGMKON0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKON_SPGMKON0_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG0PosOff */ +#define IMXDPUV1_TCON0_SPG0POSOFF ((uint32_t)(0xCC68)) +#define IMXDPUV1_TCON0_SPG0POSOFF_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_TCON0_SPG0POSOFF_RESET_VALUE 0x1680000U +#define IMXDPUV1_TCON0_SPG0POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_Y0_SHIFT 0U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_X0_SHIFT 16U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG0MaskOff */ +#define IMXDPUV1_TCON0_SPG0MASKOFF ((uint32_t)(0xCC6C)) +#define IMXDPUV1_TCON0_SPG0MASKOFF_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_TCON0_SPG0MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG0MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKOFF_SPGMKOFF0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG0MASKOFF_SPGMKOFF0_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG1PosOn */ +#define IMXDPUV1_TCON0_SPG1POSON ((uint32_t)(0xCC70)) +#define IMXDPUV1_TCON0_SPG1POSON_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_TCON0_SPG1POSON_RESET_VALUE 0xF3U +#define IMXDPUV1_TCON0_SPG1POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_Y1_SHIFT 0U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_X1_SHIFT 16U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG1POSON_SPGPSON_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG1MaskOn */ +#define IMXDPUV1_TCON0_SPG1MASKON ((uint32_t)(0xCC74)) +#define IMXDPUV1_TCON0_SPG1MASKON_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_TCON0_SPG1MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKON_SPGMKON1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKON_SPGMKON1_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG1PosOff */ +#define IMXDPUV1_TCON0_SPG1POSOFF ((uint32_t)(0xCC78)) +#define IMXDPUV1_TCON0_SPG1POSOFF_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_TCON0_SPG1POSOFF_RESET_VALUE 0xF7U +#define IMXDPUV1_TCON0_SPG1POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_Y1_SHIFT 0U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_X1_SHIFT 16U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG1MaskOff */ +#define IMXDPUV1_TCON0_SPG1MASKOFF ((uint32_t)(0xCC7C)) +#define IMXDPUV1_TCON0_SPG1MASKOFF_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_TCON0_SPG1MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG1MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKOFF_SPGMKOFF1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG1MASKOFF_SPGMKOFF1_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG2PosOn */ +#define IMXDPUV1_TCON0_SPG2POSON ((uint32_t)(0xCC80)) +#define IMXDPUV1_TCON0_SPG2POSON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_TCON0_SPG2POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG2POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_Y2_SHIFT 0U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_X2_SHIFT 16U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG2POSON_SPGPSON_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG2MaskOn */ +#define IMXDPUV1_TCON0_SPG2MASKON ((uint32_t)(0xCC84)) +#define IMXDPUV1_TCON0_SPG2MASKON_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_TCON0_SPG2MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG2MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKON_SPGMKON2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKON_SPGMKON2_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG2PosOff */ +#define IMXDPUV1_TCON0_SPG2POSOFF ((uint32_t)(0xCC88)) +#define IMXDPUV1_TCON0_SPG2POSOFF_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_TCON0_SPG2POSOFF_RESET_VALUE 0x1400000U +#define IMXDPUV1_TCON0_SPG2POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_Y2_SHIFT 0U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_X2_SHIFT 16U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG2MaskOff */ +#define IMXDPUV1_TCON0_SPG2MASKOFF ((uint32_t)(0xCC8C)) +#define IMXDPUV1_TCON0_SPG2MASKOFF_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_TCON0_SPG2MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON0_SPG2MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKOFF_SPGMKOFF2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG2MASKOFF_SPGMKOFF2_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG3PosOn */ +#define IMXDPUV1_TCON0_SPG3POSON ((uint32_t)(0xCC90)) +#define IMXDPUV1_TCON0_SPG3POSON_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_TCON0_SPG3POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG3POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_Y3_SHIFT 0U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_X3_SHIFT 16U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG3POSON_SPGPSON_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG3MaskOn */ +#define IMXDPUV1_TCON0_SPG3MASKON ((uint32_t)(0xCC94)) +#define IMXDPUV1_TCON0_SPG3MASKON_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_TCON0_SPG3MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKON_SPGMKON3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKON_SPGMKON3_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG3PosOff */ +#define IMXDPUV1_TCON0_SPG3POSOFF ((uint32_t)(0xCC98)) +#define IMXDPUV1_TCON0_SPG3POSOFF_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_TCON0_SPG3POSOFF_RESET_VALUE 0xF0U +#define IMXDPUV1_TCON0_SPG3POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_Y3_SHIFT 0U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_X3_SHIFT 16U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG3MaskOff */ +#define IMXDPUV1_TCON0_SPG3MASKOFF ((uint32_t)(0xCC9C)) +#define IMXDPUV1_TCON0_SPG3MASKOFF_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_TCON0_SPG3MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG3MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKOFF_SPGMKOFF3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG3MASKOFF_SPGMKOFF3_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG4PosOn */ +#define IMXDPUV1_TCON0_SPG4POSON ((uint32_t)(0xCCA0)) +#define IMXDPUV1_TCON0_SPG4POSON_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_TCON0_SPG4POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_Y4_SHIFT 0U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_X4_SHIFT 16U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG4POSON_SPGPSON_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG4MaskOn */ +#define IMXDPUV1_TCON0_SPG4MASKON ((uint32_t)(0xCCA4)) +#define IMXDPUV1_TCON0_SPG4MASKON_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_TCON0_SPG4MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKON_SPGMKON4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKON_SPGMKON4_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG4PosOff */ +#define IMXDPUV1_TCON0_SPG4POSOFF ((uint32_t)(0xCCA8)) +#define IMXDPUV1_TCON0_SPG4POSOFF_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_TCON0_SPG4POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_Y4_SHIFT 0U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_X4_SHIFT 16U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG4MaskOff */ +#define IMXDPUV1_TCON0_SPG4MASKOFF ((uint32_t)(0xCCAC)) +#define IMXDPUV1_TCON0_SPG4MASKOFF_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_TCON0_SPG4MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG4MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKOFF_SPGMKOFF4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG4MASKOFF_SPGMKOFF4_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG5PosOn */ +#define IMXDPUV1_TCON0_SPG5POSON ((uint32_t)(0xCCB0)) +#define IMXDPUV1_TCON0_SPG5POSON_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_TCON0_SPG5POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_Y5_SHIFT 0U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_X5_SHIFT 16U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG5POSON_SPGPSON_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG5MaskOn */ +#define IMXDPUV1_TCON0_SPG5MASKON ((uint32_t)(0xCCB4)) +#define IMXDPUV1_TCON0_SPG5MASKON_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_TCON0_SPG5MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKON_SPGMKON5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKON_SPGMKON5_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG5PosOff */ +#define IMXDPUV1_TCON0_SPG5POSOFF ((uint32_t)(0xCCB8)) +#define IMXDPUV1_TCON0_SPG5POSOFF_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_TCON0_SPG5POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_Y5_SHIFT 0U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_X5_SHIFT 16U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG5MaskOff */ +#define IMXDPUV1_TCON0_SPG5MASKOFF ((uint32_t)(0xCCBC)) +#define IMXDPUV1_TCON0_SPG5MASKOFF_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_TCON0_SPG5MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG5MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKOFF_SPGMKOFF5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG5MASKOFF_SPGMKOFF5_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG6PosOn */ +#define IMXDPUV1_TCON0_SPG6POSON ((uint32_t)(0xCCC0)) +#define IMXDPUV1_TCON0_SPG6POSON_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_TCON0_SPG6POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_Y6_SHIFT 0U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_X6_SHIFT 16U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG6POSON_SPGPSON_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG6MaskOn */ +#define IMXDPUV1_TCON0_SPG6MASKON ((uint32_t)(0xCCC4)) +#define IMXDPUV1_TCON0_SPG6MASKON_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_TCON0_SPG6MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKON_SPGMKON6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKON_SPGMKON6_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG6PosOff */ +#define IMXDPUV1_TCON0_SPG6POSOFF ((uint32_t)(0xCCC8)) +#define IMXDPUV1_TCON0_SPG6POSOFF_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_TCON0_SPG6POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_Y6_SHIFT 0U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_X6_SHIFT 16U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG6MaskOff */ +#define IMXDPUV1_TCON0_SPG6MASKOFF ((uint32_t)(0xCCCC)) +#define IMXDPUV1_TCON0_SPG6MASKOFF_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_TCON0_SPG6MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG6MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKOFF_SPGMKOFF6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG6MASKOFF_SPGMKOFF6_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG7PosOn */ +#define IMXDPUV1_TCON0_SPG7POSON ((uint32_t)(0xCCD0)) +#define IMXDPUV1_TCON0_SPG7POSON_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_TCON0_SPG7POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_Y7_SHIFT 0U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_X7_SHIFT 16U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG7POSON_SPGPSON_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG7MaskOn */ +#define IMXDPUV1_TCON0_SPG7MASKON ((uint32_t)(0xCCD4)) +#define IMXDPUV1_TCON0_SPG7MASKON_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_TCON0_SPG7MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKON_SPGMKON7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKON_SPGMKON7_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG7PosOff */ +#define IMXDPUV1_TCON0_SPG7POSOFF ((uint32_t)(0xCCD8)) +#define IMXDPUV1_TCON0_SPG7POSOFF_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_TCON0_SPG7POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_Y7_SHIFT 0U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_X7_SHIFT 16U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG7MaskOff */ +#define IMXDPUV1_TCON0_SPG7MASKOFF ((uint32_t)(0xCCDC)) +#define IMXDPUV1_TCON0_SPG7MASKOFF_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_TCON0_SPG7MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG7MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKOFF_SPGMKOFF7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG7MASKOFF_SPGMKOFF7_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG8PosOn */ +#define IMXDPUV1_TCON0_SPG8POSON ((uint32_t)(0xCCE0)) +#define IMXDPUV1_TCON0_SPG8POSON_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_TCON0_SPG8POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_Y8_SHIFT 0U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_X8_SHIFT 16U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG8POSON_SPGPSON_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG8MaskOn */ +#define IMXDPUV1_TCON0_SPG8MASKON ((uint32_t)(0xCCE4)) +#define IMXDPUV1_TCON0_SPG8MASKON_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_TCON0_SPG8MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKON_SPGMKON8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKON_SPGMKON8_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG8PosOff */ +#define IMXDPUV1_TCON0_SPG8POSOFF ((uint32_t)(0xCCE8)) +#define IMXDPUV1_TCON0_SPG8POSOFF_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_TCON0_SPG8POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_Y8_SHIFT 0U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_X8_SHIFT 16U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG8MaskOff */ +#define IMXDPUV1_TCON0_SPG8MASKOFF ((uint32_t)(0xCCEC)) +#define IMXDPUV1_TCON0_SPG8MASKOFF_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_TCON0_SPG8MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG8MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKOFF_SPGMKOFF8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG8MASKOFF_SPGMKOFF8_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG9PosOn */ +#define IMXDPUV1_TCON0_SPG9POSON ((uint32_t)(0xCCF0)) +#define IMXDPUV1_TCON0_SPG9POSON_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_TCON0_SPG9POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_Y9_SHIFT 0U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_X9_SHIFT 16U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG9POSON_SPGPSON_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG9MaskOn */ +#define IMXDPUV1_TCON0_SPG9MASKON ((uint32_t)(0xCCF4)) +#define IMXDPUV1_TCON0_SPG9MASKON_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_TCON0_SPG9MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKON_SPGMKON9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKON_SPGMKON9_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG9PosOff */ +#define IMXDPUV1_TCON0_SPG9POSOFF ((uint32_t)(0xCCF8)) +#define IMXDPUV1_TCON0_SPG9POSOFF_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_TCON0_SPG9POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_Y9_SHIFT 0U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_X9_SHIFT 16U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG9MaskOff */ +#define IMXDPUV1_TCON0_SPG9MASKOFF ((uint32_t)(0xCCFC)) +#define IMXDPUV1_TCON0_SPG9MASKOFF_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_TCON0_SPG9MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG9MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKOFF_SPGMKOFF9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG9MASKOFF_SPGMKOFF9_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG10PosOn */ +#define IMXDPUV1_TCON0_SPG10POSON ((uint32_t)(0xCD00)) +#define IMXDPUV1_TCON0_SPG10POSON_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_TCON0_SPG10POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_Y10_SHIFT 0U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_X10_SHIFT 16U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG10POSON_SPGPSON_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG10MaskOn */ +#define IMXDPUV1_TCON0_SPG10MASKON ((uint32_t)(0xCD04)) +#define IMXDPUV1_TCON0_SPG10MASKON_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_TCON0_SPG10MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKON_SPGMKON10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKON_SPGMKON10_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG10PosOff */ +#define IMXDPUV1_TCON0_SPG10POSOFF ((uint32_t)(0xCD08)) +#define IMXDPUV1_TCON0_SPG10POSOFF_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_TCON0_SPG10POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_Y10_SHIFT 0U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_X10_SHIFT 16U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG10MaskOff */ +#define IMXDPUV1_TCON0_SPG10MASKOFF ((uint32_t)(0xCD0C)) +#define IMXDPUV1_TCON0_SPG10MASKOFF_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_TCON0_SPG10MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG10MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKOFF_SPGMKOFF10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG10MASKOFF_SPGMKOFF10_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG11PosOn */ +#define IMXDPUV1_TCON0_SPG11POSON ((uint32_t)(0xCD10)) +#define IMXDPUV1_TCON0_SPG11POSON_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_TCON0_SPG11POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_Y11_SHIFT 0U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_X11_SHIFT 16U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG11POSON_SPGPSON_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG11MaskOn */ +#define IMXDPUV1_TCON0_SPG11MASKON ((uint32_t)(0xCD14)) +#define IMXDPUV1_TCON0_SPG11MASKON_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_TCON0_SPG11MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKON_SPGMKON11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKON_SPGMKON11_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SPG11PosOff */ +#define IMXDPUV1_TCON0_SPG11POSOFF ((uint32_t)(0xCD18)) +#define IMXDPUV1_TCON0_SPG11POSOFF_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_TCON0_SPG11POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_Y11_SHIFT 0U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_X11_SHIFT 16U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON0_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon0_SPG11MaskOff */ +#define IMXDPUV1_TCON0_SPG11MASKOFF ((uint32_t)(0xCD1C)) +#define IMXDPUV1_TCON0_SPG11MASKOFF_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_TCON0_SPG11MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SPG11MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKOFF_SPGMKOFF11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON0_SPG11MASKOFF_SPGMKOFF11_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx0Sigs */ +#define IMXDPUV1_TCON0_SMX0SIGS ((uint32_t)(0xCD20)) +#define IMXDPUV1_TCON0_SMX0SIGS_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_TCON0_SMX0SIGS_RESET_VALUE 0x2U +#define IMXDPUV1_TCON0_SMX0SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX0SIGS_SMX0SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx0FctTable */ +#define IMXDPUV1_TCON0_SMX0FCTTABLE ((uint32_t)(0xCD24)) +#define IMXDPUV1_TCON0_SMX0FCTTABLE_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_TCON0_SMX0FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON0_SMX0FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX0FCTTABLE_SMXFCT0_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX0FCTTABLE_SMXFCT0_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx1Sigs */ +#define IMXDPUV1_TCON0_SMX1SIGS ((uint32_t)(0xCD28)) +#define IMXDPUV1_TCON0_SMX1SIGS_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_TCON0_SMX1SIGS_RESET_VALUE 0x3U +#define IMXDPUV1_TCON0_SMX1SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX1SIGS_SMX1SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx1FctTable */ +#define IMXDPUV1_TCON0_SMX1FCTTABLE ((uint32_t)(0xCD2C)) +#define IMXDPUV1_TCON0_SMX1FCTTABLE_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_TCON0_SMX1FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON0_SMX1FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX1FCTTABLE_SMXFCT1_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX1FCTTABLE_SMXFCT1_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx2Sigs */ +#define IMXDPUV1_TCON0_SMX2SIGS ((uint32_t)(0xCD30)) +#define IMXDPUV1_TCON0_SMX2SIGS_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_TCON0_SMX2SIGS_RESET_VALUE 0x2CU +#define IMXDPUV1_TCON0_SMX2SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX2SIGS_SMX2SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx2FctTable */ +#define IMXDPUV1_TCON0_SMX2FCTTABLE ((uint32_t)(0xCD34)) +#define IMXDPUV1_TCON0_SMX2FCTTABLE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_TCON0_SMX2FCTTABLE_RESET_VALUE 0x8U +#define IMXDPUV1_TCON0_SMX2FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX2FCTTABLE_SMXFCT2_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX2FCTTABLE_SMXFCT2_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx3Sigs */ +#define IMXDPUV1_TCON0_SMX3SIGS ((uint32_t)(0xCD38)) +#define IMXDPUV1_TCON0_SMX3SIGS_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_TCON0_SMX3SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX3SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX3SIGS_SMX3SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx3FctTable */ +#define IMXDPUV1_TCON0_SMX3FCTTABLE ((uint32_t)(0xCD3C)) +#define IMXDPUV1_TCON0_SMX3FCTTABLE_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_TCON0_SMX3FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX3FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX3FCTTABLE_SMXFCT3_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX3FCTTABLE_SMXFCT3_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx4Sigs */ +#define IMXDPUV1_TCON0_SMX4SIGS ((uint32_t)(0xCD40)) +#define IMXDPUV1_TCON0_SMX4SIGS_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_TCON0_SMX4SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX4SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX4SIGS_SMX4SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx4FctTable */ +#define IMXDPUV1_TCON0_SMX4FCTTABLE ((uint32_t)(0xCD44)) +#define IMXDPUV1_TCON0_SMX4FCTTABLE_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_TCON0_SMX4FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX4FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX4FCTTABLE_SMXFCT4_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX4FCTTABLE_SMXFCT4_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx5Sigs */ +#define IMXDPUV1_TCON0_SMX5SIGS ((uint32_t)(0xCD48)) +#define IMXDPUV1_TCON0_SMX5SIGS_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_TCON0_SMX5SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX5SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX5SIGS_SMX5SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx5FctTable */ +#define IMXDPUV1_TCON0_SMX5FCTTABLE ((uint32_t)(0xCD4C)) +#define IMXDPUV1_TCON0_SMX5FCTTABLE_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_TCON0_SMX5FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX5FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX5FCTTABLE_SMXFCT5_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX5FCTTABLE_SMXFCT5_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx6Sigs */ +#define IMXDPUV1_TCON0_SMX6SIGS ((uint32_t)(0xCD50)) +#define IMXDPUV1_TCON0_SMX6SIGS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_TCON0_SMX6SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX6SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX6SIGS_SMX6SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx6FctTable */ +#define IMXDPUV1_TCON0_SMX6FCTTABLE ((uint32_t)(0xCD54)) +#define IMXDPUV1_TCON0_SMX6FCTTABLE_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_TCON0_SMX6FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX6FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX6FCTTABLE_SMXFCT6_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX6FCTTABLE_SMXFCT6_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx7Sigs */ +#define IMXDPUV1_TCON0_SMX7SIGS ((uint32_t)(0xCD58)) +#define IMXDPUV1_TCON0_SMX7SIGS_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_TCON0_SMX7SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX7SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX7SIGS_SMX7SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx7FctTable */ +#define IMXDPUV1_TCON0_SMX7FCTTABLE ((uint32_t)(0xCD5C)) +#define IMXDPUV1_TCON0_SMX7FCTTABLE_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_TCON0_SMX7FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX7FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX7FCTTABLE_SMXFCT7_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX7FCTTABLE_SMXFCT7_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx8Sigs */ +#define IMXDPUV1_TCON0_SMX8SIGS ((uint32_t)(0xCD60)) +#define IMXDPUV1_TCON0_SMX8SIGS_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_TCON0_SMX8SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX8SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX8SIGS_SMX8SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx8FctTable */ +#define IMXDPUV1_TCON0_SMX8FCTTABLE ((uint32_t)(0xCD64)) +#define IMXDPUV1_TCON0_SMX8FCTTABLE_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_TCON0_SMX8FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX8FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX8FCTTABLE_SMXFCT8_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX8FCTTABLE_SMXFCT8_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx9Sigs */ +#define IMXDPUV1_TCON0_SMX9SIGS ((uint32_t)(0xCD68)) +#define IMXDPUV1_TCON0_SMX9SIGS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_TCON0_SMX9SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX9SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX9SIGS_SMX9SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx9FctTable */ +#define IMXDPUV1_TCON0_SMX9FCTTABLE ((uint32_t)(0xCD6C)) +#define IMXDPUV1_TCON0_SMX9FCTTABLE_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_TCON0_SMX9FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX9FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX9FCTTABLE_SMXFCT9_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX9FCTTABLE_SMXFCT9_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx10Sigs */ +#define IMXDPUV1_TCON0_SMX10SIGS ((uint32_t)(0xCD70)) +#define IMXDPUV1_TCON0_SMX10SIGS_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_TCON0_SMX10SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX10SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX10SIGS_SMX10SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx10FctTable */ +#define IMXDPUV1_TCON0_SMX10FCTTABLE ((uint32_t)(0xCD74)) +#define IMXDPUV1_TCON0_SMX10FCTTABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_TCON0_SMX10FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX10FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX10FCTTABLE_SMXFCT10_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX10FCTTABLE_SMXFCT10_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_SMx11Sigs */ +#define IMXDPUV1_TCON0_SMX11SIGS ((uint32_t)(0xCD78)) +#define IMXDPUV1_TCON0_SMX11SIGS_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_TCON0_SMX11SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX11SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON0_SMX11SIGS_SMX11SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon0_SMx11FctTable */ +#define IMXDPUV1_TCON0_SMX11FCTTABLE ((uint32_t)(0xCD7C)) +#define IMXDPUV1_TCON0_SMX11FCTTABLE_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_TCON0_SMX11FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON0_SMX11FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX11FCTTABLE_SMXFCT11_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_SMX11FCTTABLE_SMXFCT11_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_Reset_Over_Unferflow */ +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW ((uint32_t)(0xCD80)) +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_VALUE 0U +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_STATUS_MASK 0x1U +#define IMXDPUV1_TCON0_RESET_OVER_UNFERFLOW_RESET_STATUS_SHIFT 0U + +/* Register: IMXDPUV1_tcon0_Dual_Debug */ +#define IMXDPUV1_TCON0_DUAL_DEBUG ((uint32_t)(0xCD84)) +#define IMXDPUV1_TCON0_DUAL_DEBUG_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_TCON0_DUAL_DEBUG_RESET_VALUE 0U +#define IMXDPUV1_TCON0_DUAL_DEBUG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_MASK 0x1U +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_SHIFT 0U +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_MASK 0x2U +#define IMXDPUV1_TCON0_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_SHIFT 1U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_MASK 0x10U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_SHIFT 4U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_MASK 0x20U +#define IMXDPUV1_TCON0_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_SHIFT 5U + +/* Register: IMXDPUV1_sig0_LockUnlock */ +#define IMXDPUV1_SIG0_LOCKUNLOCK ((uint32_t)(0xD000)) +#define IMXDPUV1_SIG0_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_SIG0_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_SIG0_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_SIG0_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_sig0_LockStatus */ +#define IMXDPUV1_SIG0_LOCKSTATUS ((uint32_t)(0xD004)) +#define IMXDPUV1_SIG0_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_SIG0_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_SIG0_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_SIG0_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_SIG0_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_SIG0_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_SIG0_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_SIG0_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_sig0_StaticControl */ +#define IMXDPUV1_SIG0_STATICCONTROL ((uint32_t)(0xD008)) +#define IMXDPUV1_SIG0_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_SIG0_STATICCONTROL_RESET_VALUE 0x8000000U +#define IMXDPUV1_SIG0_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_SIG0_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL_MASK 0x10U +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL_SHIFT 4U +/* Field Value: SHDLDSEL__LOCAL, Shadows are loaded at start of frame for + * each evaluation window for which ShdLdReq has been set. */ +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL__LOCAL 0U +/* Field Value: SHDLDSEL__GLOBAL, Shadows of all evaluation windows are loaded + * synchronous to the display stream (shadow load token received on + * frame input port). */ +#define IMXDPUV1_SIG0_STATICCONTROL_SHDLDSEL__GLOBAL 0x1U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRES_MASK 0xFF0000U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRES_SHIFT 16U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRESRESET_MASK 0xFF000000U +#define IMXDPUV1_SIG0_STATICCONTROL_ERRTHRESRESET_SHIFT 24U + +/* Register: IMXDPUV1_sig0_PanicColor */ +#define IMXDPUV1_SIG0_PANICCOLOR ((uint32_t)(0xD00C)) +#define IMXDPUV1_SIG0_PANICCOLOR_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_SIG0_PANICCOLOR_RESET_VALUE 0U +#define IMXDPUV1_SIG0_PANICCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_PANICCOLOR_PANICALPHA_MASK 0x80U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICALPHA_SHIFT 7U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICBLUE_MASK 0xFF00U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICBLUE_SHIFT 8U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICGREEN_MASK 0xFF0000U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICGREEN_SHIFT 16U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICRED_MASK 0xFF000000U +#define IMXDPUV1_SIG0_PANICCOLOR_PANICRED_SHIFT 24U + +/* Register: IMXDPUV1_sig0_EvalControl0 */ +#define IMXDPUV1_SIG0_EVALCONTROL0 ((uint32_t)(0xD010)) +#define IMXDPUV1_SIG0_EVALCONTROL0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_SIG0_EVALCONTROL0_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL0_ENEVALWIN0_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENEVALWIN0_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENCRC0_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENCRC0_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAMASK0_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAMASK0_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAINV0_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL0_ALPHAINV0_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENLOCALPANIC0_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENLOCALPANIC0_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENGLOBALPANIC0_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL0_ENGLOBALPANIC0_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft0 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT0 ((uint32_t)(0xD014)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_XEVALUPPERLEFT0_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_XEVALUPPERLEFT0_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_YEVALUPPERLEFT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT0_YEVALUPPERLEFT0_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight0 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0 ((uint32_t)(0xD018)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef0 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF0 ((uint32_t)(0xD01C)) +#define IMXDPUV1_SIG0_SIGCRCREDREF0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_SIG0_SIGCRCREDREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF0_SIGCRCREDREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF0_SIGCRCREDREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef0 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF0 ((uint32_t)(0xD020)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_SIGCRCGREENREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF0_SIGCRCGREENREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef0 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0 ((uint32_t)(0xD024)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_SIGCRCBLUEREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF0_SIGCRCBLUEREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed0 */ +#define IMXDPUV1_SIG0_SIGCRCRED0 ((uint32_t)(0xD028)) +#define IMXDPUV1_SIG0_SIGCRCRED0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_SIG0_SIGCRCRED0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED0_SIGCRCRED0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED0_SIGCRCRED0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen0 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN0 ((uint32_t)(0xD02C)) +#define IMXDPUV1_SIG0_SIGCRCGREEN0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_SIG0_SIGCRCGREEN0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN0_SIGCRCGREEN0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN0_SIGCRCGREEN0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue0 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE0 ((uint32_t)(0xD030)) +#define IMXDPUV1_SIG0_SIGCRCBLUE0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_SIG0_SIGCRCBLUE0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE0_SIGCRCBLUE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE0_SIGCRCBLUE0_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl1 */ +#define IMXDPUV1_SIG0_EVALCONTROL1 ((uint32_t)(0xD034)) +#define IMXDPUV1_SIG0_EVALCONTROL1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_SIG0_EVALCONTROL1_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL1_ENEVALWIN1_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENEVALWIN1_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENCRC1_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENCRC1_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAMASK1_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAMASK1_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAINV1_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL1_ALPHAINV1_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENLOCALPANIC1_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENLOCALPANIC1_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENGLOBALPANIC1_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL1_ENGLOBALPANIC1_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft1 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT1 ((uint32_t)(0xD038)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_XEVALUPPERLEFT1_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_XEVALUPPERLEFT1_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_YEVALUPPERLEFT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT1_YEVALUPPERLEFT1_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight1 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1 ((uint32_t)(0xD03C)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef1 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF1 ((uint32_t)(0xD040)) +#define IMXDPUV1_SIG0_SIGCRCREDREF1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_SIG0_SIGCRCREDREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF1_SIGCRCREDREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF1_SIGCRCREDREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef1 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF1 ((uint32_t)(0xD044)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_SIGCRCGREENREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF1_SIGCRCGREENREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef1 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1 ((uint32_t)(0xD048)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_SIGCRCBLUEREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF1_SIGCRCBLUEREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed1 */ +#define IMXDPUV1_SIG0_SIGCRCRED1 ((uint32_t)(0xD04C)) +#define IMXDPUV1_SIG0_SIGCRCRED1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_SIG0_SIGCRCRED1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED1_SIGCRCRED1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED1_SIGCRCRED1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen1 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN1 ((uint32_t)(0xD050)) +#define IMXDPUV1_SIG0_SIGCRCGREEN1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_SIG0_SIGCRCGREEN1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN1_SIGCRCGREEN1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN1_SIGCRCGREEN1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue1 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE1 ((uint32_t)(0xD054)) +#define IMXDPUV1_SIG0_SIGCRCBLUE1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_SIG0_SIGCRCBLUE1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE1_SIGCRCBLUE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE1_SIGCRCBLUE1_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl2 */ +#define IMXDPUV1_SIG0_EVALCONTROL2 ((uint32_t)(0xD058)) +#define IMXDPUV1_SIG0_EVALCONTROL2_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_SIG0_EVALCONTROL2_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL2_ENEVALWIN2_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENEVALWIN2_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENCRC2_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENCRC2_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAMASK2_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAMASK2_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAINV2_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL2_ALPHAINV2_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENLOCALPANIC2_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENLOCALPANIC2_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENGLOBALPANIC2_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL2_ENGLOBALPANIC2_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft2 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT2 ((uint32_t)(0xD05C)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_XEVALUPPERLEFT2_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_XEVALUPPERLEFT2_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_YEVALUPPERLEFT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT2_YEVALUPPERLEFT2_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight2 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2 ((uint32_t)(0xD060)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef2 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF2 ((uint32_t)(0xD064)) +#define IMXDPUV1_SIG0_SIGCRCREDREF2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_SIG0_SIGCRCREDREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF2_SIGCRCREDREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF2_SIGCRCREDREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef2 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF2 ((uint32_t)(0xD068)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_SIGCRCGREENREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF2_SIGCRCGREENREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef2 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2 ((uint32_t)(0xD06C)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_SIGCRCBLUEREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF2_SIGCRCBLUEREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed2 */ +#define IMXDPUV1_SIG0_SIGCRCRED2 ((uint32_t)(0xD070)) +#define IMXDPUV1_SIG0_SIGCRCRED2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_SIG0_SIGCRCRED2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED2_SIGCRCRED2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED2_SIGCRCRED2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen2 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN2 ((uint32_t)(0xD074)) +#define IMXDPUV1_SIG0_SIGCRCGREEN2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_SIG0_SIGCRCGREEN2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN2_SIGCRCGREEN2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN2_SIGCRCGREEN2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue2 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE2 ((uint32_t)(0xD078)) +#define IMXDPUV1_SIG0_SIGCRCBLUE2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_SIG0_SIGCRCBLUE2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE2_SIGCRCBLUE2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE2_SIGCRCBLUE2_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl3 */ +#define IMXDPUV1_SIG0_EVALCONTROL3 ((uint32_t)(0xD07C)) +#define IMXDPUV1_SIG0_EVALCONTROL3_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_SIG0_EVALCONTROL3_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL3_ENEVALWIN3_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENEVALWIN3_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENCRC3_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENCRC3_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAMASK3_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAMASK3_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAINV3_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL3_ALPHAINV3_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENLOCALPANIC3_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENLOCALPANIC3_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENGLOBALPANIC3_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL3_ENGLOBALPANIC3_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft3 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT3 ((uint32_t)(0xD080)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_XEVALUPPERLEFT3_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_XEVALUPPERLEFT3_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_YEVALUPPERLEFT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT3_YEVALUPPERLEFT3_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight3 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3 ((uint32_t)(0xD084)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef3 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF3 ((uint32_t)(0xD088)) +#define IMXDPUV1_SIG0_SIGCRCREDREF3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_SIG0_SIGCRCREDREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF3_SIGCRCREDREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF3_SIGCRCREDREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef3 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF3 ((uint32_t)(0xD08C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_SIGCRCGREENREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF3_SIGCRCGREENREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef3 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3 ((uint32_t)(0xD090)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_SIGCRCBLUEREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF3_SIGCRCBLUEREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed3 */ +#define IMXDPUV1_SIG0_SIGCRCRED3 ((uint32_t)(0xD094)) +#define IMXDPUV1_SIG0_SIGCRCRED3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_SIG0_SIGCRCRED3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED3_SIGCRCRED3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED3_SIGCRCRED3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen3 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN3 ((uint32_t)(0xD098)) +#define IMXDPUV1_SIG0_SIGCRCGREEN3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_SIG0_SIGCRCGREEN3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN3_SIGCRCGREEN3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN3_SIGCRCGREEN3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue3 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE3 ((uint32_t)(0xD09C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE3_SIGCRCBLUE3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE3_SIGCRCBLUE3_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl4 */ +#define IMXDPUV1_SIG0_EVALCONTROL4 ((uint32_t)(0xD0A0)) +#define IMXDPUV1_SIG0_EVALCONTROL4_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_SIG0_EVALCONTROL4_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL4_ENEVALWIN4_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENEVALWIN4_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENCRC4_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENCRC4_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAMASK4_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAMASK4_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAINV4_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL4_ALPHAINV4_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENLOCALPANIC4_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENLOCALPANIC4_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENGLOBALPANIC4_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL4_ENGLOBALPANIC4_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft4 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT4 ((uint32_t)(0xD0A4)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_XEVALUPPERLEFT4_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_XEVALUPPERLEFT4_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_YEVALUPPERLEFT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT4_YEVALUPPERLEFT4_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight4 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4 ((uint32_t)(0xD0A8)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef4 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF4 ((uint32_t)(0xD0AC)) +#define IMXDPUV1_SIG0_SIGCRCREDREF4_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_SIG0_SIGCRCREDREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF4_SIGCRCREDREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF4_SIGCRCREDREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef4 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF4 ((uint32_t)(0xD0B0)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_SIGCRCGREENREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF4_SIGCRCGREENREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef4 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4 ((uint32_t)(0xD0B4)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_SIGCRCBLUEREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF4_SIGCRCBLUEREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed4 */ +#define IMXDPUV1_SIG0_SIGCRCRED4 ((uint32_t)(0xD0B8)) +#define IMXDPUV1_SIG0_SIGCRCRED4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_SIG0_SIGCRCRED4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED4_SIGCRCRED4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED4_SIGCRCRED4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen4 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN4 ((uint32_t)(0xD0BC)) +#define IMXDPUV1_SIG0_SIGCRCGREEN4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_SIG0_SIGCRCGREEN4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN4_SIGCRCGREEN4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN4_SIGCRCGREEN4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue4 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE4 ((uint32_t)(0xD0C0)) +#define IMXDPUV1_SIG0_SIGCRCBLUE4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_SIG0_SIGCRCBLUE4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE4_SIGCRCBLUE4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE4_SIGCRCBLUE4_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl5 */ +#define IMXDPUV1_SIG0_EVALCONTROL5 ((uint32_t)(0xD0C4)) +#define IMXDPUV1_SIG0_EVALCONTROL5_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_SIG0_EVALCONTROL5_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL5_ENEVALWIN5_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENEVALWIN5_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENCRC5_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENCRC5_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAMASK5_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAMASK5_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAINV5_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL5_ALPHAINV5_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENLOCALPANIC5_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENLOCALPANIC5_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENGLOBALPANIC5_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL5_ENGLOBALPANIC5_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft5 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT5 ((uint32_t)(0xD0C8)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_XEVALUPPERLEFT5_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_XEVALUPPERLEFT5_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_YEVALUPPERLEFT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT5_YEVALUPPERLEFT5_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight5 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5 ((uint32_t)(0xD0CC)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef5 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF5 ((uint32_t)(0xD0D0)) +#define IMXDPUV1_SIG0_SIGCRCREDREF5_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_SIG0_SIGCRCREDREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF5_SIGCRCREDREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF5_SIGCRCREDREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef5 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF5 ((uint32_t)(0xD0D4)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_SIGCRCGREENREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF5_SIGCRCGREENREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef5 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5 ((uint32_t)(0xD0D8)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_SIGCRCBLUEREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF5_SIGCRCBLUEREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed5 */ +#define IMXDPUV1_SIG0_SIGCRCRED5 ((uint32_t)(0xD0DC)) +#define IMXDPUV1_SIG0_SIGCRCRED5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_SIG0_SIGCRCRED5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED5_SIGCRCRED5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED5_SIGCRCRED5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen5 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN5 ((uint32_t)(0xD0E0)) +#define IMXDPUV1_SIG0_SIGCRCGREEN5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_SIG0_SIGCRCGREEN5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN5_SIGCRCGREEN5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN5_SIGCRCGREEN5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue5 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE5 ((uint32_t)(0xD0E4)) +#define IMXDPUV1_SIG0_SIGCRCBLUE5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_SIG0_SIGCRCBLUE5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE5_SIGCRCBLUE5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE5_SIGCRCBLUE5_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl6 */ +#define IMXDPUV1_SIG0_EVALCONTROL6 ((uint32_t)(0xD0E8)) +#define IMXDPUV1_SIG0_EVALCONTROL6_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_SIG0_EVALCONTROL6_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL6_ENEVALWIN6_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENEVALWIN6_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENCRC6_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENCRC6_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAMASK6_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAMASK6_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAINV6_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL6_ALPHAINV6_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENLOCALPANIC6_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENLOCALPANIC6_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENGLOBALPANIC6_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL6_ENGLOBALPANIC6_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft6 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT6 ((uint32_t)(0xD0EC)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_XEVALUPPERLEFT6_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_XEVALUPPERLEFT6_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_YEVALUPPERLEFT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT6_YEVALUPPERLEFT6_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight6 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6 ((uint32_t)(0xD0F0)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef6 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF6 ((uint32_t)(0xD0F4)) +#define IMXDPUV1_SIG0_SIGCRCREDREF6_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_SIG0_SIGCRCREDREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF6_SIGCRCREDREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF6_SIGCRCREDREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef6 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF6 ((uint32_t)(0xD0F8)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_SIGCRCGREENREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF6_SIGCRCGREENREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef6 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6 ((uint32_t)(0xD0FC)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_SIGCRCBLUEREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF6_SIGCRCBLUEREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed6 */ +#define IMXDPUV1_SIG0_SIGCRCRED6 ((uint32_t)(0xD100)) +#define IMXDPUV1_SIG0_SIGCRCRED6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_SIG0_SIGCRCRED6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED6_SIGCRCRED6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED6_SIGCRCRED6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen6 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN6 ((uint32_t)(0xD104)) +#define IMXDPUV1_SIG0_SIGCRCGREEN6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_SIG0_SIGCRCGREEN6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN6_SIGCRCGREEN6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN6_SIGCRCGREEN6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue6 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE6 ((uint32_t)(0xD108)) +#define IMXDPUV1_SIG0_SIGCRCBLUE6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_SIG0_SIGCRCBLUE6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE6_SIGCRCBLUE6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE6_SIGCRCBLUE6_SHIFT 0U + +/* Register: IMXDPUV1_sig0_EvalControl7 */ +#define IMXDPUV1_SIG0_EVALCONTROL7 ((uint32_t)(0xD10C)) +#define IMXDPUV1_SIG0_EVALCONTROL7_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_SIG0_EVALCONTROL7_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALCONTROL7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALCONTROL7_ENEVALWIN7_MASK 0x1U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENEVALWIN7_SHIFT 0U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENCRC7_MASK 0x2U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENCRC7_SHIFT 1U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAMASK7_MASK 0x100U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAMASK7_SHIFT 8U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAINV7_MASK 0x200U +#define IMXDPUV1_SIG0_EVALCONTROL7_ALPHAINV7_SHIFT 9U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENLOCALPANIC7_MASK 0x10000U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENLOCALPANIC7_SHIFT 16U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENGLOBALPANIC7_MASK 0x20000U +#define IMXDPUV1_SIG0_EVALCONTROL7_ENGLOBALPANIC7_SHIFT 17U + +/* Register: IMXDPUV1_sig0_EvalUpperLeft7 */ +#define IMXDPUV1_SIG0_EVALUPPERLEFT7 ((uint32_t)(0xD110)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_XEVALUPPERLEFT7_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_XEVALUPPERLEFT7_SHIFT 0U +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_YEVALUPPERLEFT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALUPPERLEFT7_YEVALUPPERLEFT7_SHIFT 16U + +/* Register: IMXDPUV1_sig0_EvalLowerRight7 */ +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7 ((uint32_t)(0xD114)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_RESET_VALUE 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_MASK 0x3FFFU +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_SHIFT 0U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG0_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_sig0_SigCRCRedRef7 */ +#define IMXDPUV1_SIG0_SIGCRCREDREF7 ((uint32_t)(0xD118)) +#define IMXDPUV1_SIG0_SIGCRCREDREF7_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_SIG0_SIGCRCREDREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF7_SIGCRCREDREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCREDREF7_SIGCRCREDREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreenRef7 */ +#define IMXDPUV1_SIG0_SIGCRCGREENREF7 ((uint32_t)(0xD11C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_SIGCRCGREENREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREENREF7_SIGCRCGREENREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlueRef7 */ +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7 ((uint32_t)(0xD120)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_SIGCRCBLUEREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUEREF7_SIGCRCBLUEREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCRed7 */ +#define IMXDPUV1_SIG0_SIGCRCRED7 ((uint32_t)(0xD124)) +#define IMXDPUV1_SIG0_SIGCRCRED7_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_SIG0_SIGCRCRED7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED7_SIGCRCRED7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCRED7_SIGCRCRED7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCGreen7 */ +#define IMXDPUV1_SIG0_SIGCRCGREEN7 ((uint32_t)(0xD128)) +#define IMXDPUV1_SIG0_SIGCRCGREEN7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_SIG0_SIGCRCGREEN7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN7_SIGCRCGREEN7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCGREEN7_SIGCRCGREEN7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SigCRCBlue7 */ +#define IMXDPUV1_SIG0_SIGCRCBLUE7 ((uint32_t)(0xD12C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_SIG0_SIGCRCBLUE7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE7_SIGCRCBLUE7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SIGCRCBLUE7_SIGCRCBLUE7_SHIFT 0U + +/* Register: IMXDPUV1_sig0_ShadowLoad */ +#define IMXDPUV1_SIG0_SHADOWLOAD ((uint32_t)(0xD130)) +#define IMXDPUV1_SIG0_SHADOWLOAD_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_SIG0_SHADOWLOAD_RESET_VALUE 0U +#define IMXDPUV1_SIG0_SHADOWLOAD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SHADOWLOAD_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_SIG0_SHADOWLOAD_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_sig0_ContinuousMode */ +#define IMXDPUV1_SIG0_CONTINUOUSMODE ((uint32_t)(0xD134)) +#define IMXDPUV1_SIG0_CONTINUOUSMODE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_SIG0_CONTINUOUSMODE_RESET_VALUE 0U +#define IMXDPUV1_SIG0_CONTINUOUSMODE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_CONTINUOUSMODE_ENCONT_MASK 0x1U +#define IMXDPUV1_SIG0_CONTINUOUSMODE_ENCONT_SHIFT 0U + +/* Register: IMXDPUV1_sig0_SoftwareKick */ +#define IMXDPUV1_SIG0_SOFTWAREKICK ((uint32_t)(0xD138)) +#define IMXDPUV1_SIG0_SOFTWAREKICK_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_SIG0_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_SIG0_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_SIG0_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_sig0_Status */ +#define IMXDPUV1_SIG0_STATUS ((uint32_t)(0xD13C)) +#define IMXDPUV1_SIG0_STATUS_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_SIG0_STATUS_RESET_VALUE 0x100000U +#define IMXDPUV1_SIG0_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG0_STATUS_STSSIGERROR_MASK 0xFFU +#define IMXDPUV1_SIG0_STATUS_STSSIGERROR_SHIFT 0U +#define IMXDPUV1_SIG0_STATUS_STSSIGVALID_MASK 0x10000U +#define IMXDPUV1_SIG0_STATUS_STSSIGVALID_SHIFT 16U +#define IMXDPUV1_SIG0_STATUS_STSSIGIDLE_MASK 0x100000U +#define IMXDPUV1_SIG0_STATUS_STSSIGIDLE_SHIFT 20U + +/* Register: IMXDPUV1_framegen1_LockUnlock */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK ((uint32_t)(0xD400)) +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_FRAMEGEN1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_framegen1_LockStatus */ +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS ((uint32_t)(0xD404)) +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_FRAMEGEN1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_framegen1_FgStCtrl */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL ((uint32_t)(0xD408)) +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_SHDEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_SHDEN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE_SHIFT 1U +/* Field Value: FGSYNCMODE__OFF, No side-by-side synchronization. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__OFF 0U +/* Field Value: FGSYNCMODE__MASTER, Framegen is master. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__MASTER 0x1U +/* Field Value: FGSYNCMODE__SLAVE_CYC, Framegen is slave. Runs in cyclic synchronization + * mode. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_CYC 0x2U +/* Field Value: FGSYNCMODE__SLAVE_ONCE, Framegen is slave. Runs in one time + * synchronization mode. */ +#define IMXDPUV1_FRAMEGEN1_FGSTCTRL_FGSYNCMODE__SLAVE_ONCE 0x3U + +/* Register: IMXDPUV1_framegen1_HtCfg1 */ +#define IMXDPUV1_FRAMEGEN1_HTCFG1 ((uint32_t)(0xD40C)) +#define IMXDPUV1_FRAMEGEN1_HTCFG1_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_FRAMEGEN1_HTCFG1_RESET_VALUE 0x18F0140U +#define IMXDPUV1_FRAMEGEN1_HTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_HTCFG1_HTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_HtCfg2 */ +#define IMXDPUV1_FRAMEGEN1_HTCFG2 ((uint32_t)(0xD410)) +#define IMXDPUV1_FRAMEGEN1_HTCFG2_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_FRAMEGEN1_HTCFG2_RESET_VALUE 0x8047001FU +#define IMXDPUV1_FRAMEGEN1_HTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_HTCFG2_HSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_VtCfg1 */ +#define IMXDPUV1_FRAMEGEN1_VTCFG1 ((uint32_t)(0xD414)) +#define IMXDPUV1_FRAMEGEN1_VTCFG1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_FRAMEGEN1_VTCFG1_RESET_VALUE 0xFC00F0U +#define IMXDPUV1_FRAMEGEN1_VTCFG1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VACT_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VACT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VTOTAL_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_VTCFG1_VTOTAL_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_VtCfg2 */ +#define IMXDPUV1_FRAMEGEN1_VTCFG2 ((uint32_t)(0xD418)) +#define IMXDPUV1_FRAMEGEN1_VTCFG2_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_FRAMEGEN1_VTCFG2_RESET_VALUE 0x80090003U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSYNC_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSYNC_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSBP_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSBP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_VTCFG2_VSEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int0Config */ +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG ((uint32_t)(0xD41C)) +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT0CONFIG_INT0EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int1Config */ +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG ((uint32_t)(0xD420)) +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT1CONFIG_INT1EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int2Config */ +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG ((uint32_t)(0xD424)) +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT2CONFIG_INT2EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_Int3Config */ +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG ((uint32_t)(0xD428)) +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3COL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3COL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3HSEN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3HSEN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3ROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3ROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3EN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_INT3CONFIG_INT3EN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_PKickConfig */ +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG ((uint32_t)(0xD42C)) +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKINT0EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKINT0EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_PKICKCONFIG_PKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_SKickConfig */ +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG ((uint32_t)(0xD430)) +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_RESET_VALUE 0xF00140U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKCOL_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKCOL_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKINT1EN_MASK 0x8000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKINT1EN_SHIFT 15U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKROW_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKROW_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG_SHIFT 30U +/* Field Value: SKICKTRIG__INTERNAL, Use internal skick signal, trigger point + * defined by SKickRow and SKickCol. */ +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG__INTERNAL 0U +/* Field Value: SKICKTRIG__EXTERNAL, Use external skick input as trigger. */ +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKTRIG__EXTERNAL 0x1U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKEN_MASK 0x80000000U +#define IMXDPUV1_FRAMEGEN1_SKICKCONFIG_SKICKEN_SHIFT 31U + +/* Register: IMXDPUV1_framegen1_SecStatConfig */ +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG ((uint32_t)(0xD434)) +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_RESET_VALUE 0x112U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVGOODFRAMES_MASK 0xFU +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVGOODFRAMES_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVBADFRAMES_MASK 0xF0U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVBADFRAMES_SHIFT 4U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVSKEWINRANGE_MASK 0xF00U +#define IMXDPUV1_FRAMEGEN1_SECSTATCONFIG_LEVSKEWINRANGE_SHIFT 8U + +/* Register: IMXDPUV1_framegen1_FgSRCR1 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1 ((uint32_t)(0xD438)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE_MASK 0x6U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE_SHIFT 1U +/* Field Value: SRMODE__OFF, Skew Regulation is off. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__OFF 0U +/* Field Value: SRMODE__HREG, Horizontal regulation enabled. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__HREG 0x1U +/* Field Value: SRMODE__VREG, Vertical regulation enabled. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__VREG 0x2U +/* Field Value: SRMODE__BOTH, Both regulation modes are enabled. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRMODE__BOTH 0x3U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRADJ_MASK 0x8U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRADJ_SHIFT 3U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREVEN_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREVEN_SHIFT 4U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRFASTSYNC_MASK 0x20U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRFASTSYNC_SHIFT 5U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQALIGN_MASK 0x40U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQALIGN_SHIFT 6U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL_MASK 0x180U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL_SHIFT 7U +/* Field Value: SRQVAL__ZERO, Fixed two LSB values of HTOTAL are 0b00. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__ZERO 0U +/* Field Value: SRQVAL__ONE, Fixed two LSB values of HTOTAL are 0b01. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__ONE 0x1U +/* Field Value: SRQVAL__TWO, Fixed two LSB values of HTOTAL are 0b10. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__TWO 0x2U +/* Field Value: SRQVAL__THREE, Fixed two LSB values of HTOTAL are 0b11. */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRQVAL__THREE 0x3U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRDBGDISP_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SRDBGDISP_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREPOFF_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR1_SREPOFF_SHIFT 17U + +/* Register: IMXDPUV1_framegen1_FgSRCR2 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR2 ((uint32_t)(0xD43C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_RESET_VALUE 0x1B70188U +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR2_HTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgSRCR3 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR3 ((uint32_t)(0xD440)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_RESET_VALUE 0x11500FBU +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMIN_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMIN_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMAX_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_FGSRCR3_VTOTALMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgSRCR4 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR4 ((uint32_t)(0xD444)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_RESET_VALUE 0xC8U +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_TARGETSKEW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR4_TARGETSKEW_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSRCR5 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR5 ((uint32_t)(0xD448)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_SYNCRANGELOW_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR5_SYNCRANGELOW_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSRCR6 */ +#define IMXDPUV1_FRAMEGEN1_FGSRCR6 ((uint32_t)(0xD44C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_RESET_VALUE 0x190U +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_SYNCRANGEHIGH_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRCR6_SYNCRANGEHIGH_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgKSDR */ +#define IMXDPUV1_FRAMEGEN1_FGKSDR ((uint32_t)(0xD450)) +#define IMXDPUV1_FRAMEGEN1_FGKSDR_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_FRAMEGEN1_FGKSDR_RESET_VALUE 0x20002U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGKSDR_PCNTCPLMAX_MASK 0x7U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_PCNTCPLMAX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_SCNTCPLMAX_MASK 0x70000U +#define IMXDPUV1_FRAMEGEN1_FGKSDR_SCNTCPLMAX_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_PaCfg */ +#define IMXDPUV1_FRAMEGEN1_PACFG ((uint32_t)(0xD454)) +#define IMXDPUV1_FRAMEGEN1_PACFG_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_FRAMEGEN1_PACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN1_PACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_PACFG_PSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_SaCfg */ +#define IMXDPUV1_FRAMEGEN1_SACFG ((uint32_t)(0xD458)) +#define IMXDPUV1_FRAMEGEN1_SACFG_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_FRAMEGEN1_SACFG_RESET_VALUE 0x10001U +#define IMXDPUV1_FRAMEGEN1_SACFG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTY_MASK 0x3FFF0000U +#define IMXDPUV1_FRAMEGEN1_SACFG_SSTARTY_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgInCtrl */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL ((uint32_t)(0xD45C)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_RESET_VALUE 0x6U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM_MASK 0x7U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM_SHIFT 0U +/* Field Value: FGDM__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__BLACK 0U +/* Field Value: FGDM__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__CONSTCOL 0x1U +/* Field Value: FGDM__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__PRIM 0x2U +/* Field Value: FGDM__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__SEC 0x3U +/* Field Value: FGDM__PRIM_ON_TOP, Both inputs overlaid with primary on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__PRIM_ON_TOP 0x4U +/* Field Value: FGDM__SEC_ON_TOP, Both inputs overlaid with secondary on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__SEC_ON_TOP 0x5U +/* Field Value: FGDM__TEST, White color background with test pattern is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_FGDM__TEST 0x6U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENPRIMALPHA_MASK 0x8U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENPRIMALPHA_SHIFT 3U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENSECALPHA_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_FGINCTRL_ENSECALPHA_SHIFT 4U + +/* Register: IMXDPUV1_framegen1_FgInCtrlPanic */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC ((uint32_t)(0xD460)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC_MASK 0x7U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC_SHIFT 0U +/* Field Value: FGDMPANIC__BLACK, Black Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__BLACK 0U +/* Field Value: FGDMPANIC__CONSTCOL, Constant Color Background is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__CONSTCOL 0x1U +/* Field Value: FGDMPANIC__PRIM, Primary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__PRIM 0x2U +/* Field Value: FGDMPANIC__SEC, Secondary input only is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__SEC 0x3U +/* Field Value: FGDMPANIC__PRIM_ON_TOP, Both inputs overlaid with primary + * on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__PRIM_ON_TOP 0x4U +/* Field Value: FGDMPANIC__SEC_ON_TOP, Both inputs overlaid with secondary + * on top. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__SEC_ON_TOP 0x5U +/* Field Value: FGDMPANIC__TEST, White color background with test pattern + * is shown. */ +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_FGDMPANIC__TEST 0x6U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENPRIMALPHAPANIC_MASK 0x8U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENPRIMALPHAPANIC_SHIFT 3U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENSECALPHAPANIC_MASK 0x10U +#define IMXDPUV1_FRAMEGEN1_FGINCTRLPANIC_ENSECALPHAPANIC_SHIFT 4U + +/* Register: IMXDPUV1_framegen1_FgCCR */ +#define IMXDPUV1_FRAMEGEN1_FGCCR ((uint32_t)(0xD464)) +#define IMXDPUV1_FRAMEGEN1_FGCCR_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_FRAMEGEN1_FGCCR_RESET_VALUE 0x7FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCCR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCBLUE_MASK 0x3FFU +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCBLUE_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCGREEN_MASK 0xFFC00U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCGREEN_SHIFT 10U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCRED_MASK 0x3FF00000U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCRED_SHIFT 20U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCALPHA_MASK 0x40000000U +#define IMXDPUV1_FRAMEGEN1_FGCCR_CCALPHA_SHIFT 30U + +/* Register: IMXDPUV1_framegen1_FgEnable */ +#define IMXDPUV1_FRAMEGEN1_FGENABLE ((uint32_t)(0xD468)) +#define IMXDPUV1_FRAMEGEN1_FGENABLE_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_FRAMEGEN1_FGENABLE_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGENABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGENABLE_FGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGENABLE_FGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSlr */ +#define IMXDPUV1_FRAMEGEN1_FGSLR ((uint32_t)(0xD46C)) +#define IMXDPUV1_FRAMEGEN1_FGSLR_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_FRAMEGEN1_FGSLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSLR_SHDTOKGEN_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSLR_SHDTOKGEN_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgEnSts */ +#define IMXDPUV1_FRAMEGEN1_FGENSTS ((uint32_t)(0xD470)) +#define IMXDPUV1_FRAMEGEN1_FGENSTS_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_FRAMEGEN1_FGENSTS_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGENSTS_ENSTS_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_ENSTS_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_PANICSTAT_MASK 0x2U +#define IMXDPUV1_FRAMEGEN1_FGENSTS_PANICSTAT_SHIFT 1U + +/* Register: IMXDPUV1_framegen1_FgTimeStamp */ +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP ((uint32_t)(0xD474)) +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_LINEINDEX_MASK 0x3FFFU +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_LINEINDEX_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_FRAMEINDEX_MASK 0xFFFFC000U +#define IMXDPUV1_FRAMEGEN1_FGTIMESTAMP_FRAMEINDEX_SHIFT 14U + +/* Register: IMXDPUV1_framegen1_FgChStat */ +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT ((uint32_t)(0xD478)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PFIFOEMPTY_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PFIFOEMPTY_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PRIMSYNCSTAT_MASK 0x100U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_PRIMSYNCSTAT_SHIFT 8U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SFIFOEMPTY_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SFIFOEMPTY_SHIFT 16U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SKEWRANGEERR_MASK 0x20000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SKEWRANGEERR_SHIFT 17U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SECSYNCSTAT_MASK 0x1000000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTAT_SECSYNCSTAT_SHIFT 24U + +/* Register: IMXDPUV1_framegen1_FgChStatClr */ +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR ((uint32_t)(0xD47C)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRPRIMSTAT_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRPRIMSTAT_SHIFT 0U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRSECSTAT_MASK 0x10000U +#define IMXDPUV1_FRAMEGEN1_FGCHSTATCLR_CLRSECSTAT_SHIFT 16U + +/* Register: IMXDPUV1_framegen1_FgSkewMon */ +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON ((uint32_t)(0xD480)) +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_SKEWMON_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSKEWMON_SKEWMON_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSFifoMin */ +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN ((uint32_t)(0xD484)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_SFIFOMIN_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMIN_SFIFOMIN_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSFifoMax */ +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX ((uint32_t)(0xD488)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_SFIFOMAX_MASK 0xFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOMAX_SFIFOMAX_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSFifoFillClr */ +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR ((uint32_t)(0xD48C)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_SFIFOFILLCLR_MASK 0x1U +#define IMXDPUV1_FRAMEGEN1_FGSFIFOFILLCLR_SFIFOFILLCLR_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSrEpD */ +#define IMXDPUV1_FRAMEGEN1_FGSREPD ((uint32_t)(0xD490)) +#define IMXDPUV1_FRAMEGEN1_FGSREPD_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_FRAMEGEN1_FGSREPD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSREPD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSREPD_EPVAL_MASK 0x1FFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSREPD_EPVAL_SHIFT 0U + +/* Register: IMXDPUV1_framegen1_FgSrFtD */ +#define IMXDPUV1_FRAMEGEN1_FGSRFTD ((uint32_t)(0xD494)) +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_RESET_VALUE 0U +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_FRTOT_MASK 0xFFFFFFFU +#define IMXDPUV1_FRAMEGEN1_FGSRFTD_FRTOT_SHIFT 0U + +/* Register: IMXDPUV1_matrix1_LockUnlock */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK ((uint32_t)(0xD800)) +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_MATRIX1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_matrix1_LockStatus */ +#define IMXDPUV1_MATRIX1_LOCKSTATUS ((uint32_t)(0xD804)) +#define IMXDPUV1_MATRIX1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_MATRIX1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_MATRIX1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_matrix1_StaticControl */ +#define IMXDPUV1_MATRIX1_STATICCONTROL ((uint32_t)(0xD808)) +#define IMXDPUV1_MATRIX1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_MATRIX1_STATICCONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_MATRIX1_STATICCONTROL_SHDEN_SHIFT 0U + +/* Register: IMXDPUV1_matrix1_Control */ +#define IMXDPUV1_MATRIX1_CONTROL ((uint32_t)(0xD80C)) +#define IMXDPUV1_MATRIX1_CONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_MATRIX1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_CONTROL_MODE_MASK 0x3U +#define IMXDPUV1_MATRIX1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__MATRIX, Module in matrix mode, input data is multiplied + * with matrix values */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__MATRIX 0x1U +/* Field Value: MODE__PREMUL, Module in alpha pre-multiplication mode, input + * color is multiplied with input alpha */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__PREMUL 0x2U +/* Field Value: MODE__RSVD, Reserved, do not use */ +#define IMXDPUV1_MATRIX1_CONTROL_MODE__RSVD 0x3U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_MATRIX1_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_matrix1_Red0 */ +#define IMXDPUV1_MATRIX1_RED0 ((uint32_t)(0xD810)) +#define IMXDPUV1_MATRIX1_RED0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_MATRIX1_RED0_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX1_RED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_RED0_A11_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_RED0_A11_SHIFT 0U +#define IMXDPUV1_MATRIX1_RED0_A12_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_RED0_A12_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Red1 */ +#define IMXDPUV1_MATRIX1_RED1 ((uint32_t)(0xD814)) +#define IMXDPUV1_MATRIX1_RED1_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_MATRIX1_RED1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_RED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_RED1_A13_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_RED1_A13_SHIFT 0U +#define IMXDPUV1_MATRIX1_RED1_A14_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_RED1_A14_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Green0 */ +#define IMXDPUV1_MATRIX1_GREEN0 ((uint32_t)(0xD818)) +#define IMXDPUV1_MATRIX1_GREEN0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_MATRIX1_GREEN0_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX1_GREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_GREEN0_A21_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_GREEN0_A21_SHIFT 0U +#define IMXDPUV1_MATRIX1_GREEN0_A22_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_GREEN0_A22_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Green1 */ +#define IMXDPUV1_MATRIX1_GREEN1 ((uint32_t)(0xD81C)) +#define IMXDPUV1_MATRIX1_GREEN1_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_MATRIX1_GREEN1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_GREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_GREEN1_A23_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_GREEN1_A23_SHIFT 0U +#define IMXDPUV1_MATRIX1_GREEN1_A24_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_GREEN1_A24_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Blue0 */ +#define IMXDPUV1_MATRIX1_BLUE0 ((uint32_t)(0xD820)) +#define IMXDPUV1_MATRIX1_BLUE0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_MATRIX1_BLUE0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_BLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_BLUE0_A31_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_BLUE0_A31_SHIFT 0U +#define IMXDPUV1_MATRIX1_BLUE0_A32_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_BLUE0_A32_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Blue1 */ +#define IMXDPUV1_MATRIX1_BLUE1 ((uint32_t)(0xD824)) +#define IMXDPUV1_MATRIX1_BLUE1_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_MATRIX1_BLUE1_RESET_VALUE 0x400U +#define IMXDPUV1_MATRIX1_BLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_BLUE1_A33_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_BLUE1_A33_SHIFT 0U +#define IMXDPUV1_MATRIX1_BLUE1_A34_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_BLUE1_A34_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Alpha0 */ +#define IMXDPUV1_MATRIX1_ALPHA0 ((uint32_t)(0xD828)) +#define IMXDPUV1_MATRIX1_ALPHA0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_MATRIX1_ALPHA0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_ALPHA0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_ALPHA0_A41_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_ALPHA0_A41_SHIFT 0U +#define IMXDPUV1_MATRIX1_ALPHA0_A42_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_ALPHA0_A42_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_Alpha1 */ +#define IMXDPUV1_MATRIX1_ALPHA1 ((uint32_t)(0xD82C)) +#define IMXDPUV1_MATRIX1_ALPHA1_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_MATRIX1_ALPHA1_RESET_VALUE 0x4000000U +#define IMXDPUV1_MATRIX1_ALPHA1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_ALPHA1_A43_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_ALPHA1_A43_SHIFT 0U +#define IMXDPUV1_MATRIX1_ALPHA1_A44_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_ALPHA1_A44_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_OffsetVector0 */ +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0 ((uint32_t)(0xD830)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C1_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C1_SHIFT 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C2_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR0_C2_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_OffsetVector1 */ +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1 ((uint32_t)(0xD834)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C3_MASK 0x1FFFU +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C3_SHIFT 0U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C4_MASK 0x1FFF0000U +#define IMXDPUV1_MATRIX1_OFFSETVECTOR1_C4_SHIFT 16U + +/* Register: IMXDPUV1_matrix1_LastControlWord */ +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD ((uint32_t)(0xD838)) +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_MATRIX1_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_gammacor1_LockUnlock */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK ((uint32_t)(0xDC00)) +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_GAMMACOR1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_gammacor1_LockStatus */ +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS ((uint32_t)(0xDC04)) +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_GAMMACOR1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_gammacor1_StaticControl */ +#define IMXDPUV1_GAMMACOR1_STATICCONTROL ((uint32_t)(0xDC08)) +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_RESET_VALUE 0xEU +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE_MASK 0x2U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_BLUEWRITEENABLE_SHIFT 1U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE_MASK 0x4U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_GREENWRITEENABLE_SHIFT 2U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE_MASK 0x8U +#define IMXDPUV1_GAMMACOR1_STATICCONTROL_REDWRITEENABLE_SHIFT 3U + +/* Register: IMXDPUV1_gammacor1_LutStart */ +#define IMXDPUV1_GAMMACOR1_LUTSTART ((uint32_t)(0xDC0C)) +#define IMXDPUV1_GAMMACOR1_LUTSTART_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_GAMMACOR1_LUTSTART_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LUTSTART_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTBLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTBLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTRED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR1_LUTSTART_STARTRED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor1_LutDeltas */ +#define IMXDPUV1_GAMMACOR1_LUTDELTAS ((uint32_t)(0xDC10)) +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_RESET_MASK 0xC0000000U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTABLUE_MASK 0x3FFU +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTABLUE_SHIFT 0U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTAGREEN_MASK 0xFFC00U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTAGREEN_SHIFT 10U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTARED_MASK 0x3FF00000U +#define IMXDPUV1_GAMMACOR1_LUTDELTAS_DELTARED_SHIFT 20U + +/* Register: IMXDPUV1_gammacor1_Control */ +#define IMXDPUV1_GAMMACOR1_CONTROL ((uint32_t)(0xDC14)) +#define IMXDPUV1_GAMMACOR1_CONTROL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_GAMMACOR1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Module in neutral mode, input data is bypassed + * to the output. */ +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__GAMMACOR, Module in gamma correction mode. */ +#define IMXDPUV1_GAMMACOR1_CONTROL_MODE__GAMMACOR 0x1U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAMASK_MASK 0x10U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAMASK_SHIFT 4U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAINVERT_MASK 0x20U +#define IMXDPUV1_GAMMACOR1_CONTROL_ALPHAINVERT_SHIFT 5U + +/* Register: IMXDPUV1_gammacor1_Status */ +#define IMXDPUV1_GAMMACOR1_STATUS ((uint32_t)(0xDC18)) +#define IMXDPUV1_GAMMACOR1_STATUS_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_GAMMACOR1_STATUS_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_STATUS_WRITETIMEOUT_MASK 0x1U +#define IMXDPUV1_GAMMACOR1_STATUS_WRITETIMEOUT_SHIFT 0U + +/* Register: IMXDPUV1_gammacor1_LastControlWord */ +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD ((uint32_t)(0xDC1C)) +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_RESET_VALUE 0U +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_RESET_MASK 0U +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_L_VAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_GAMMACOR1_LASTCONTROLWORD_L_VAL_SHIFT 0U + +/* Register: IMXDPUV1_dither1_LockUnlock */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK ((uint32_t)(0xE000)) +#define IMXDPUV1_DITHER1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DITHER1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_DITHER1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_dither1_LockStatus */ +#define IMXDPUV1_DITHER1_LOCKSTATUS ((uint32_t)(0xE004)) +#define IMXDPUV1_DITHER1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DITHER1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_DITHER1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_DITHER1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_DITHER1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_DITHER1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_DITHER1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_dither1_Control */ +#define IMXDPUV1_DITHER1_CONTROL ((uint32_t)(0xE008)) +#define IMXDPUV1_DITHER1_CONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DITHER1_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_CONTROL_MODE_MASK 0x1U +#define IMXDPUV1_DITHER1_CONTROL_MODE_SHIFT 0U +/* Field Value: MODE__NEUTRAL, Neutral mode. Pixels by-pass the Dither Unit, + * all other settings are ignored. */ +#define IMXDPUV1_DITHER1_CONTROL_MODE__NEUTRAL 0U +/* Field Value: MODE__ACTIVE, Dither Unit is active. */ +#define IMXDPUV1_DITHER1_CONTROL_MODE__ACTIVE 0x1U + +/* Register: IMXDPUV1_dither1_DitherControl */ +#define IMXDPUV1_DITHER1_DITHERCONTROL ((uint32_t)(0xE00C)) +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DITHER1_DITHERCONTROL_RESET_VALUE 0x300222U +#define IMXDPUV1_DITHER1_DITHERCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT_MASK 0x7U +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT_SHIFT 0U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO8, Reduces blue component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO8 0x2U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO7, Reduces blue component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO7 0x3U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO6, Reduces blue component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO6 0x4U +/* Field Value: BLUE_RANGE_SELECT__BLUE_10TO5, Reduces blue component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_BLUE_RANGE_SELECT__BLUE_10TO5 0x5U +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT_MASK 0x70U +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT_SHIFT 4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO8, Reduces green component width + * from 10 bit to 8bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO8 0x2U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO7, Reduces green component width + * from 10 bit to 7bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO7 0x3U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO6, Reduces green component width + * from 10 bit to 6bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO6 0x4U +/* Field Value: GREEN_RANGE_SELECT__GREEN_10TO5, Reduces green component width + * from 10 bit to 5bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_GREEN_RANGE_SELECT__GREEN_10TO5 0x5U +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT_MASK 0x700U +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT_SHIFT 8U +/* Field Value: RED_RANGE_SELECT__RED_10TO8, Reduces red component width from + * 10 bit to 8bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO8 0x2U +/* Field Value: RED_RANGE_SELECT__RED_10TO7, Reduces red component width from + * 10 bit to 7bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO7 0x3U +/* Field Value: RED_RANGE_SELECT__RED_10TO6, Reduces red component width from + * 10 bit to 6bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO6 0x4U +/* Field Value: RED_RANGE_SELECT__RED_10TO5, Reduces red component width from + * 10 bit to 5bit. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_RED_RANGE_SELECT__RED_10TO5 0x5U +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT_MASK 0x10000U +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT_SHIFT 16U +/* Field Value: OFFSET_SELECT__OFFS_SPATIAL, Offset is a bayer matrix value, + * which is selected according to pixel frame position. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT__OFFS_SPATIAL 0U +/* Field Value: OFFSET_SELECT__OFFS_TEMPORAL, Offset is the sum from a bayer + * matrix value, which is selected according to pixel frame position, + * and a value from a regular sequence, which changes each frame. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_OFFSET_SELECT__OFFS_TEMPORAL 0x1U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT_MASK 0x300000U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT_SHIFT 20U +/* Field Value: ALGO_SELECT__NO_CORRECTION, Best possible resolution for most + * dark colors. Adds a diminutive offset to overall image brightness. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__NO_CORRECTION 0x1U +/* Field Value: ALGO_SELECT__BRIGHTNESS_CORRECTION, Preserves overall image + * brightness. Cannot resolve most dark and most bright colors. All codes + * in-between are distributed perfectly smooth. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__BRIGHTNESS_CORRECTION 0x2U +/* Field Value: ALGO_SELECT__CONTRAST_CORRECTION, Preserves overall image + * brightness. Best possible distribution of color codes over complete range. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALGO_SELECT__CONTRAST_CORRECTION 0x3U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE_MASK 0x3000000U +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE_SHIFT 24U +/* Field Value: ALPHA_MODE__DISABLE, The alpha bit is not considered. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__DISABLE 0U +/* Field Value: ALPHA_MODE__ENABLE_BY1, Red, green and blue components are + * only dithered, if the alpha bit is 1. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__ENABLE_BY1 0x1U +/* Field Value: ALPHA_MODE__ENABLE_BY0, Red, green and blue components are + * only dithered, if the alpha bit is 0. */ +#define IMXDPUV1_DITHER1_DITHERCONTROL_ALPHA_MODE__ENABLE_BY0 0x2U + +/* Register: IMXDPUV1_dither1_Release */ +#define IMXDPUV1_DITHER1_RELEASE ((uint32_t)(0xE010)) +#define IMXDPUV1_DITHER1_RELEASE_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DITHER1_RELEASE_RESET_VALUE 0U +#define IMXDPUV1_DITHER1_RELEASE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DITHER1_RELEASE_SUBVERSION_MASK 0xFFU +#define IMXDPUV1_DITHER1_RELEASE_SUBVERSION_SHIFT 0U +#define IMXDPUV1_DITHER1_RELEASE_VERSION_MASK 0xFF00U +#define IMXDPUV1_DITHER1_RELEASE_VERSION_SHIFT 8U + +/* Register: IMXDPUV1_tcon1_SSqCnts */ +#define IMXDPUV1_TCON1_SSQCNTS ((uint32_t)(0xE400)) +#define IMXDPUV1_TCON1_SSQCNTS_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON1_SSQCNTS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SSQCNTS_RESET_MASK 0U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQY_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQY_SHIFT 0U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_FIELD_MASK 0x8000U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_FIELD_SHIFT 15U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQX_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_SEQX_SHIFT 16U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_OUT_MASK 0x80000000U +#define IMXDPUV1_TCON1_SSQCNTS_SSQCNTS_OUT_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_LockUnlock */ +#define IMXDPUV1_TCON1_LOCKUNLOCK ((uint32_t)(0xE800)) +#define IMXDPUV1_TCON1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_TCON1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_TCON1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_TCON1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_tcon1_LockStatus */ +#define IMXDPUV1_TCON1_LOCKSTATUS ((uint32_t)(0xE804)) +#define IMXDPUV1_TCON1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_TCON1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_TCON1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_TCON1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_TCON1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_TCON1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_TCON1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_tcon1_SSqCycle */ +#define IMXDPUV1_TCON1_SSQCYCLE ((uint32_t)(0xE808)) +#define IMXDPUV1_TCON1_SSQCYCLE_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_TCON1_SSQCYCLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SSQCYCLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SSQCYCLE_SSQCYCLE_MASK 0x3FU +#define IMXDPUV1_TCON1_SSQCYCLE_SSQCYCLE_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SWreset */ +#define IMXDPUV1_TCON1_SWRESET ((uint32_t)(0xE80C)) +#define IMXDPUV1_TCON1_SWRESET_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_TCON1_SWRESET_RESET_VALUE 0x3FC00410U +#define IMXDPUV1_TCON1_SWRESET_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SWRESET_SWRESET_MASK 0x1U +#define IMXDPUV1_TCON1_SWRESET_SWRESET_SHIFT 0U +/* Field Value: SWRESET__OPERATION, operation mode */ +#define IMXDPUV1_TCON1_SWRESET_SWRESET__OPERATION 0U +/* Field Value: SWRESET__SWRESET, So long SWReset = 0x1 tcon is in 'SW reset + * state' and it is released by internal logic (SWReset is released and + * end of frame arrived), read: 0b: reset not active 1b: reset active (that + * means NO pixel of video frame is excepted until 'SW reset state' + * is released) */ +#define IMXDPUV1_TCON1_SWRESET_SWRESET__SWRESET 0x1U +#define IMXDPUV1_TCON1_SWRESET_ENRESETWORD_MASK 0xFFF0U +#define IMXDPUV1_TCON1_SWRESET_ENRESETWORD_SHIFT 4U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDEND_MASK 0xFF0000U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDEND_SHIFT 16U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDSTART_MASK 0xFF000000U +#define IMXDPUV1_TCON1_SWRESET_RESETWORDSTART_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_TCON_CTRL */ +#define IMXDPUV1_TCON1_TCON_CTRL ((uint32_t)(0xE810)) +#define IMXDPUV1_TCON1_TCON_CTRL_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_TCON1_TCON_CTRL_RESET_VALUE 0x1401408U +#define IMXDPUV1_TCON1_TCON_CTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE_MASK 0x3U +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE_SHIFT 0U +/* Field Value: CHANNELMODE__SINGLE, Single pixel mode. Both channels channel + * are active at full pixel clock. If bitmap of both panels are the same, + * both panels are identical */ +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__SINGLE 0U +/* Field Value: CHANNELMODE__DUAL_INTERLEAVED, Dual pixel mode. Both channels + * are active at half the pixel clock. 1st channel drives display columns + * with even and 2nd one with odd index. */ +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__DUAL_INTERLEAVED 0x1U +/* Field Value: CHANNELMODE__DUAL_SPLIT, Dual pixel mode. Both channels are + * active at half the pixel clock. 1st channel drives the left and 2nd + * one the righ half of the display. Note : data_en is needed in this mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_CHANNELMODE__DUAL_SPLIT 0x2U +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC_MASK 0x4U +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC_SHIFT 2U +/* Field Value: TCON_SYNC__H_VLAST, tcon timing generator synchronized to + * hlast, vlast */ +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC__H_VLAST 0U +/* Field Value: TCON_SYNC__H_VSYNC, tcon timing generator synchronized to + * hsync, vsync where horizontal synchronization is synchronized at the falling + * edge of hsync */ +#define IMXDPUV1_TCON1_TCON_CTRL_TCON_SYNC__H_VSYNC 0x1U +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS_MASK 0x8U +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS_SHIFT 3U +/* Field Value: BYPASS__TCON_MODE, tcon operation mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS__TCON_MODE 0U +/* Field Value: BYPASS__BYPASS_MODE, tcon in Bypass mode. input pixel and + * its sync-signals are bypassed to tcon-output */ +#define IMXDPUV1_TCON1_TCON_CTRL_BYPASS__BYPASS_MODE 0x1U +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL_MASK 0xF0U +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL_SHIFT 4U +/* Field Value: INV_CTRL__DISABLE, Disable inversion control */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__DISABLE 0U +/* Field Value: INV_CTRL__RGB_2_BITS, Enable inversion control for number + * of RGB-Bits = 2 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_2_BITS 0x1U +/* Field Value: INV_CTRL__RGB_4_BITS, Enable inversion control for number + * of RGB-Bits = 4 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_4_BITS 0x2U +/* Field Value: INV_CTRL__RGB_6_BITS, Enable inversion control for number + * of RGB-Bits = 6 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_6_BITS 0x3U +/* Field Value: INV_CTRL__RGB_8_BITS, Enable inversion control for number + * of RGB-Bits = 8 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_8_BITS 0x4U +/* Field Value: INV_CTRL__RGB_10_BITS, Enable inversion control for number + * of RGB-Bits = 10 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_10_BITS 0x5U +/* Field Value: INV_CTRL__RGB_12_BITS, Enable inversion control for number + * of RGB-Bits = 12 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_12_BITS 0x6U +/* Field Value: INV_CTRL__RGB_14_BITS, Enable inversion control for number + * of RGB-Bits = 14 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_14_BITS 0x7U +/* Field Value: INV_CTRL__RGB_16_BITS, Enable inversion control for number + * of RGB-Bits = 16 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_16_BITS 0x8U +/* Field Value: INV_CTRL__RGB_18_BITS, Enable inversion control for number + * of RGB-Bits = 18 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_18_BITS 0x9U +/* Field Value: INV_CTRL__RGB_20_BITS, Enable inversion control for number + * of RGB-Bits = 20 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_20_BITS 0xAU +/* Field Value: INV_CTRL__RGB_22_BITS, Enable inversion control for number + * of RGB-Bits = 22 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_22_BITS 0xBU +/* Field Value: INV_CTRL__RGB_24_BITS, Enable inversion control for number + * of RGB-Bits = 24 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_24_BITS 0xCU +/* Field Value: INV_CTRL__RGB_26_BITS, Enable inversion control for number + * of RGB-Bits = 26 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_26_BITS 0xDU +/* Field Value: INV_CTRL__RGB_28_BITS, Enable inversion control for number + * of RGB-Bits = 28 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_28_BITS 0xEU +/* Field Value: INV_CTRL__RGB_30_BITS, Enable inversion control for number + * of RGB-Bits = 30 */ +#define IMXDPUV1_TCON1_TCON_CTRL_INV_CTRL__RGB_30_BITS 0xFU +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS_MASK 0x100U +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS_SHIFT 8U +/* Field Value: ENLVDS__ENABLE_LVDS, Enable LVDS , TTL and RSDS are disable + * */ +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS__ENABLE_LVDS 0x1U +/* Field Value: ENLVDS__DISABLE_LVDS, Disable LVDS, Enable TTL and RSDS */ +#define IMXDPUV1_TCON1_TCON_CTRL_ENLVDS__DISABLE_LVDS 0U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE_MASK 0x200U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE_SHIFT 9U +/* Field Value: LVDSMODE__MINI_LVDS, MiniLVDS */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE__MINI_LVDS 0x1U +/* Field Value: LVDSMODE__LVDS, LVDS Mode, refered to OpenLDI */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDSMODE__LVDS 0U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE_MASK 0x400U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE_SHIFT 10U +/* Field Value: LVDS_BALANCE__BALANCED, LVDS operates in 24 bits Balanced + * Mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE__BALANCED 0x1U +/* Field Value: LVDS_BALANCE__UNBALANCED, LVDS operates in 24 bits Unbalanced + * Mode */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_BALANCE__UNBALANCED 0U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV_MASK 0x800U +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV_SHIFT 11U +/* Field Value: LVDS_CLOCK_INV__INV, Invert LVDS Clock */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV__INV 0x1U +/* Field Value: LVDS_CLOCK_INV__NON_INV, NON-Invert LVDS Clock */ +#define IMXDPUV1_TCON1_TCON_CTRL_LVDS_CLOCK_INV__NON_INV 0U +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE_MASK 0x7000U +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE_SHIFT 12U +/* Field Value: MINILVDS_OPCODE__MODE_3PAIRS, MiniLVDS operates in 6 and 8 + * bit data, three pairs */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_3PAIRS 0U +/* Field Value: MINILVDS_OPCODE__MODE_4PAIRS, Not Implemented */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_4PAIRS 0x1U +/* Field Value: MINILVDS_OPCODE__MODE_5PAIRS, Not Implemented */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_5PAIRS 0x2U +/* Field Value: MINILVDS_OPCODE__MODE_6PAIRS, MiniLVDS operates in 6 and 8 + * bit data, six pairs */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__MODE_6PAIRS 0x3U +/* Field Value: MINILVDS_OPCODE__RESERVED1, RESERVED1 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED1 0x4U +/* Field Value: MINILVDS_OPCODE__RESERVED2, RESERVED2 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED2 0x5U +/* Field Value: MINILVDS_OPCODE__RESERVED3, RESERVED3 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED3 0x6U +/* Field Value: MINILVDS_OPCODE__RESERVED4, RESERVED4 */ +#define IMXDPUV1_TCON1_TCON_CTRL_MINILVDS_OPCODE__RESERVED4 0x7U +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP_MASK 0x8000U +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP_SHIFT 15U +/* Field Value: DUAL_SWAP__SWAP, swapping pixels between lower-channel and + * upper-channel */ +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP__SWAP 0x1U +/* Field Value: DUAL_SWAP__NON_SWAP, NON-swapping pixels between lower-channel + * and upper-channel */ +#define IMXDPUV1_TCON1_TCON_CTRL_DUAL_SWAP__NON_SWAP 0U +#define IMXDPUV1_TCON1_TCON_CTRL_SPLITPOSITION_MASK 0x3FFF0000U +#define IMXDPUV1_TCON1_TCON_CTRL_SPLITPOSITION_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_RSDSInvCtrl */ +#define IMXDPUV1_TCON1_RSDSINVCTRL ((uint32_t)(0xE814)) +#define IMXDPUV1_TCON1_RSDSINVCTRL_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_TCON1_RSDSINVCTRL_RESET_VALUE 0U +#define IMXDPUV1_TCON1_RSDSINVCTRL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_MASK 0x7FFFU +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_SHIFT 0U +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_DUAL_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_RSDSINVCTRL_RSDS_INV_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_MapBit3_0 */ +#define IMXDPUV1_TCON1_MAPBIT3_0 ((uint32_t)(0xE818)) +#define IMXDPUV1_TCON1_MAPBIT3_0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_TCON1_MAPBIT3_0_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON1_MAPBIT3_0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT0_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT0_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT1_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT1_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT2_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT2_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT3_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT3_0_MAPBIT3_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit7_4 */ +#define IMXDPUV1_TCON1_MAPBIT7_4 ((uint32_t)(0xE81C)) +#define IMXDPUV1_TCON1_MAPBIT7_4_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_TCON1_MAPBIT7_4_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON1_MAPBIT7_4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT4_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT4_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT5_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT5_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT6_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT6_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT7_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT7_4_MAPBIT7_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit11_8 */ +#define IMXDPUV1_TCON1_MAPBIT11_8 ((uint32_t)(0xE820)) +#define IMXDPUV1_TCON1_MAPBIT11_8_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_TCON1_MAPBIT11_8_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON1_MAPBIT11_8_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT8_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT8_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT9_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT9_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT10_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT10_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT11_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT11_8_MAPBIT11_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit15_12 */ +#define IMXDPUV1_TCON1_MAPBIT15_12 ((uint32_t)(0xE824)) +#define IMXDPUV1_TCON1_MAPBIT15_12_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_TCON1_MAPBIT15_12_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON1_MAPBIT15_12_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT12_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT12_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT13_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT13_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT14_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT14_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT15_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT15_12_MAPBIT15_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit19_16 */ +#define IMXDPUV1_TCON1_MAPBIT19_16 ((uint32_t)(0xE828)) +#define IMXDPUV1_TCON1_MAPBIT19_16_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_TCON1_MAPBIT19_16_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON1_MAPBIT19_16_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT16_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT16_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT17_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT17_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT18_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT18_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT19_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT19_16_MAPBIT19_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit23_20 */ +#define IMXDPUV1_TCON1_MAPBIT23_20 ((uint32_t)(0xE82C)) +#define IMXDPUV1_TCON1_MAPBIT23_20_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_TCON1_MAPBIT23_20_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON1_MAPBIT23_20_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT20_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT20_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT21_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT21_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT22_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT22_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT23_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT23_20_MAPBIT23_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit27_24 */ +#define IMXDPUV1_TCON1_MAPBIT27_24 ((uint32_t)(0xE830)) +#define IMXDPUV1_TCON1_MAPBIT27_24_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_TCON1_MAPBIT27_24_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON1_MAPBIT27_24_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT24_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT24_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT25_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT25_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT26_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT26_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT27_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT27_24_MAPBIT27_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit31_28 */ +#define IMXDPUV1_TCON1_MAPBIT31_28 ((uint32_t)(0xE834)) +#define IMXDPUV1_TCON1_MAPBIT31_28_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_TCON1_MAPBIT31_28_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON1_MAPBIT31_28_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT28_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT28_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT29_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT29_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT30_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT30_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT31_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT31_28_MAPBIT31_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit34_32 */ +#define IMXDPUV1_TCON1_MAPBIT34_32 ((uint32_t)(0xE838)) +#define IMXDPUV1_TCON1_MAPBIT34_32_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_TCON1_MAPBIT34_32_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON1_MAPBIT34_32_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT32_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT32_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT33_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT33_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT34_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT34_32_MAPBIT34_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_MapBit3_0_Dual */ +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL ((uint32_t)(0xE83C)) +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_RESET_VALUE 0x3020100U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT0_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT0_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT1_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT1_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT2_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT2_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT3_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT3_0_DUAL_MAPBIT3_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit7_4_Dual */ +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL ((uint32_t)(0xE840)) +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_RESET_VALUE 0x7060504U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT4_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT4_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT5_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT5_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT6_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT6_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT7_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT7_4_DUAL_MAPBIT7_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit11_8_Dual */ +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL ((uint32_t)(0xE844)) +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_RESET_VALUE 0xB0A0908U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT8_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT8_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT9_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT9_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT10_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT10_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT11_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT11_8_DUAL_MAPBIT11_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit15_12_Dual */ +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL ((uint32_t)(0xE848)) +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_RESET_VALUE 0xF0E0D0CU +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT12_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT12_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT13_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT13_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT14_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT14_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT15_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT15_12_DUAL_MAPBIT15_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit19_16_Dual */ +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL ((uint32_t)(0xE84C)) +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_RESET_VALUE 0x13121110U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT16_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT16_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT17_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT17_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT18_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT18_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT19_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT19_16_DUAL_MAPBIT19_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit23_20_Dual */ +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL ((uint32_t)(0xE850)) +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_RESET_VALUE 0x17161514U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT20_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT20_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT21_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT21_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT22_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT22_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT23_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT23_20_DUAL_MAPBIT23_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit27_24_Dual */ +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL ((uint32_t)(0xE854)) +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_RESET_VALUE 0x1B1A1918U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT24_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT24_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT25_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT25_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT26_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT26_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT27_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT27_24_DUAL_MAPBIT27_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit31_28_Dual */ +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL ((uint32_t)(0xE858)) +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_RESET_VALUE 0x1F1E1D1CU +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT28_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT28_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT29_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT29_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT30_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT30_DUAL_SHIFT 16U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT31_DUAL_MASK 0x3F000000U +#define IMXDPUV1_TCON1_MAPBIT31_28_DUAL_MAPBIT31_DUAL_SHIFT 24U + +/* Register: IMXDPUV1_tcon1_MapBit34_32_Dual */ +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL ((uint32_t)(0xE85C)) +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_RESET_VALUE 0x222120U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT32_DUAL_MASK 0x3FU +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT32_DUAL_SHIFT 0U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT33_DUAL_MASK 0x3F00U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT33_DUAL_SHIFT 8U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT34_DUAL_MASK 0x3F0000U +#define IMXDPUV1_TCON1_MAPBIT34_32_DUAL_MAPBIT34_DUAL_SHIFT 16U + +/* Register: IMXDPUV1_tcon1_SPG0PosOn */ +#define IMXDPUV1_TCON1_SPG0POSON ((uint32_t)(0xE860)) +#define IMXDPUV1_TCON1_SPG0POSON_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_TCON1_SPG0POSON_RESET_VALUE 0x1480000U +#define IMXDPUV1_TCON1_SPG0POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_Y0_SHIFT 0U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_X0_SHIFT 16U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG0POSON_SPGPSON_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG0MaskOn */ +#define IMXDPUV1_TCON1_SPG0MASKON ((uint32_t)(0xE864)) +#define IMXDPUV1_TCON1_SPG0MASKON_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_TCON1_SPG0MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG0MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKON_SPGMKON0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKON_SPGMKON0_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG0PosOff */ +#define IMXDPUV1_TCON1_SPG0POSOFF ((uint32_t)(0xE868)) +#define IMXDPUV1_TCON1_SPG0POSOFF_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_TCON1_SPG0POSOFF_RESET_VALUE 0x1680000U +#define IMXDPUV1_TCON1_SPG0POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_Y0_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_Y0_SHIFT 0U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_FIELD0_SHIFT 15U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_X0_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_X0_SHIFT 16U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG0POSOFF_SPGPSOFF_TOGGLE0_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG0MaskOff */ +#define IMXDPUV1_TCON1_SPG0MASKOFF ((uint32_t)(0xE86C)) +#define IMXDPUV1_TCON1_SPG0MASKOFF_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_TCON1_SPG0MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG0MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKOFF_SPGMKOFF0_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG0MASKOFF_SPGMKOFF0_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG1PosOn */ +#define IMXDPUV1_TCON1_SPG1POSON ((uint32_t)(0xE870)) +#define IMXDPUV1_TCON1_SPG1POSON_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_TCON1_SPG1POSON_RESET_VALUE 0xF3U +#define IMXDPUV1_TCON1_SPG1POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_Y1_SHIFT 0U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_X1_SHIFT 16U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG1POSON_SPGPSON_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG1MaskOn */ +#define IMXDPUV1_TCON1_SPG1MASKON ((uint32_t)(0xE874)) +#define IMXDPUV1_TCON1_SPG1MASKON_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_TCON1_SPG1MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKON_SPGMKON1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKON_SPGMKON1_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG1PosOff */ +#define IMXDPUV1_TCON1_SPG1POSOFF ((uint32_t)(0xE878)) +#define IMXDPUV1_TCON1_SPG1POSOFF_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_TCON1_SPG1POSOFF_RESET_VALUE 0xF7U +#define IMXDPUV1_TCON1_SPG1POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_Y1_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_Y1_SHIFT 0U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_FIELD1_SHIFT 15U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_X1_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_X1_SHIFT 16U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG1POSOFF_SPGPSOFF_TOGGLE1_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG1MaskOff */ +#define IMXDPUV1_TCON1_SPG1MASKOFF ((uint32_t)(0xE87C)) +#define IMXDPUV1_TCON1_SPG1MASKOFF_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_TCON1_SPG1MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG1MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKOFF_SPGMKOFF1_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG1MASKOFF_SPGMKOFF1_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG2PosOn */ +#define IMXDPUV1_TCON1_SPG2POSON ((uint32_t)(0xE880)) +#define IMXDPUV1_TCON1_SPG2POSON_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_TCON1_SPG2POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG2POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_Y2_SHIFT 0U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_X2_SHIFT 16U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG2POSON_SPGPSON_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG2MaskOn */ +#define IMXDPUV1_TCON1_SPG2MASKON ((uint32_t)(0xE884)) +#define IMXDPUV1_TCON1_SPG2MASKON_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_TCON1_SPG2MASKON_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG2MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKON_SPGMKON2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKON_SPGMKON2_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG2PosOff */ +#define IMXDPUV1_TCON1_SPG2POSOFF ((uint32_t)(0xE888)) +#define IMXDPUV1_TCON1_SPG2POSOFF_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_TCON1_SPG2POSOFF_RESET_VALUE 0x1400000U +#define IMXDPUV1_TCON1_SPG2POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_Y2_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_Y2_SHIFT 0U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_FIELD2_SHIFT 15U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_X2_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_X2_SHIFT 16U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG2POSOFF_SPGPSOFF_TOGGLE2_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG2MaskOff */ +#define IMXDPUV1_TCON1_SPG2MASKOFF ((uint32_t)(0xE88C)) +#define IMXDPUV1_TCON1_SPG2MASKOFF_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_TCON1_SPG2MASKOFF_RESET_VALUE 0xFFFFU +#define IMXDPUV1_TCON1_SPG2MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKOFF_SPGMKOFF2_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG2MASKOFF_SPGMKOFF2_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG3PosOn */ +#define IMXDPUV1_TCON1_SPG3POSON ((uint32_t)(0xE890)) +#define IMXDPUV1_TCON1_SPG3POSON_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_TCON1_SPG3POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG3POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_Y3_SHIFT 0U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_X3_SHIFT 16U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG3POSON_SPGPSON_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG3MaskOn */ +#define IMXDPUV1_TCON1_SPG3MASKON ((uint32_t)(0xE894)) +#define IMXDPUV1_TCON1_SPG3MASKON_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_TCON1_SPG3MASKON_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKON_SPGMKON3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKON_SPGMKON3_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG3PosOff */ +#define IMXDPUV1_TCON1_SPG3POSOFF ((uint32_t)(0xE898)) +#define IMXDPUV1_TCON1_SPG3POSOFF_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_TCON1_SPG3POSOFF_RESET_VALUE 0xF0U +#define IMXDPUV1_TCON1_SPG3POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_Y3_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_Y3_SHIFT 0U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_FIELD3_SHIFT 15U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_X3_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_X3_SHIFT 16U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG3POSOFF_SPGPSOFF_TOGGLE3_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG3MaskOff */ +#define IMXDPUV1_TCON1_SPG3MASKOFF ((uint32_t)(0xE89C)) +#define IMXDPUV1_TCON1_SPG3MASKOFF_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_TCON1_SPG3MASKOFF_RESET_VALUE 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG3MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKOFF_SPGMKOFF3_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG3MASKOFF_SPGMKOFF3_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG4PosOn */ +#define IMXDPUV1_TCON1_SPG4POSON ((uint32_t)(0xE8A0)) +#define IMXDPUV1_TCON1_SPG4POSON_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_TCON1_SPG4POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_Y4_SHIFT 0U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_X4_SHIFT 16U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG4POSON_SPGPSON_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG4MaskOn */ +#define IMXDPUV1_TCON1_SPG4MASKON ((uint32_t)(0xE8A4)) +#define IMXDPUV1_TCON1_SPG4MASKON_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_TCON1_SPG4MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKON_SPGMKON4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKON_SPGMKON4_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG4PosOff */ +#define IMXDPUV1_TCON1_SPG4POSOFF ((uint32_t)(0xE8A8)) +#define IMXDPUV1_TCON1_SPG4POSOFF_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_TCON1_SPG4POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_Y4_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_Y4_SHIFT 0U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_FIELD4_SHIFT 15U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_X4_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_X4_SHIFT 16U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG4POSOFF_SPGPSOFF_TOGGLE4_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG4MaskOff */ +#define IMXDPUV1_TCON1_SPG4MASKOFF ((uint32_t)(0xE8AC)) +#define IMXDPUV1_TCON1_SPG4MASKOFF_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_TCON1_SPG4MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG4MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKOFF_SPGMKOFF4_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG4MASKOFF_SPGMKOFF4_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG5PosOn */ +#define IMXDPUV1_TCON1_SPG5POSON ((uint32_t)(0xE8B0)) +#define IMXDPUV1_TCON1_SPG5POSON_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_TCON1_SPG5POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_Y5_SHIFT 0U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_X5_SHIFT 16U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG5POSON_SPGPSON_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG5MaskOn */ +#define IMXDPUV1_TCON1_SPG5MASKON ((uint32_t)(0xE8B4)) +#define IMXDPUV1_TCON1_SPG5MASKON_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_TCON1_SPG5MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKON_SPGMKON5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKON_SPGMKON5_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG5PosOff */ +#define IMXDPUV1_TCON1_SPG5POSOFF ((uint32_t)(0xE8B8)) +#define IMXDPUV1_TCON1_SPG5POSOFF_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_TCON1_SPG5POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_Y5_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_Y5_SHIFT 0U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_FIELD5_SHIFT 15U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_X5_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_X5_SHIFT 16U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG5POSOFF_SPGPSOFF_TOGGLE5_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG5MaskOff */ +#define IMXDPUV1_TCON1_SPG5MASKOFF ((uint32_t)(0xE8BC)) +#define IMXDPUV1_TCON1_SPG5MASKOFF_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_TCON1_SPG5MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG5MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKOFF_SPGMKOFF5_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG5MASKOFF_SPGMKOFF5_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG6PosOn */ +#define IMXDPUV1_TCON1_SPG6POSON ((uint32_t)(0xE8C0)) +#define IMXDPUV1_TCON1_SPG6POSON_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_TCON1_SPG6POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_Y6_SHIFT 0U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_X6_SHIFT 16U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG6POSON_SPGPSON_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG6MaskOn */ +#define IMXDPUV1_TCON1_SPG6MASKON ((uint32_t)(0xE8C4)) +#define IMXDPUV1_TCON1_SPG6MASKON_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_TCON1_SPG6MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKON_SPGMKON6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKON_SPGMKON6_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG6PosOff */ +#define IMXDPUV1_TCON1_SPG6POSOFF ((uint32_t)(0xE8C8)) +#define IMXDPUV1_TCON1_SPG6POSOFF_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_TCON1_SPG6POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_Y6_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_Y6_SHIFT 0U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_FIELD6_SHIFT 15U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_X6_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_X6_SHIFT 16U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG6POSOFF_SPGPSOFF_TOGGLE6_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG6MaskOff */ +#define IMXDPUV1_TCON1_SPG6MASKOFF ((uint32_t)(0xE8CC)) +#define IMXDPUV1_TCON1_SPG6MASKOFF_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_TCON1_SPG6MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG6MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKOFF_SPGMKOFF6_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG6MASKOFF_SPGMKOFF6_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG7PosOn */ +#define IMXDPUV1_TCON1_SPG7POSON ((uint32_t)(0xE8D0)) +#define IMXDPUV1_TCON1_SPG7POSON_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_TCON1_SPG7POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_Y7_SHIFT 0U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_X7_SHIFT 16U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG7POSON_SPGPSON_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG7MaskOn */ +#define IMXDPUV1_TCON1_SPG7MASKON ((uint32_t)(0xE8D4)) +#define IMXDPUV1_TCON1_SPG7MASKON_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_TCON1_SPG7MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKON_SPGMKON7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKON_SPGMKON7_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG7PosOff */ +#define IMXDPUV1_TCON1_SPG7POSOFF ((uint32_t)(0xE8D8)) +#define IMXDPUV1_TCON1_SPG7POSOFF_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_TCON1_SPG7POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_Y7_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_Y7_SHIFT 0U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_FIELD7_SHIFT 15U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_X7_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_X7_SHIFT 16U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG7POSOFF_SPGPSOFF_TOGGLE7_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG7MaskOff */ +#define IMXDPUV1_TCON1_SPG7MASKOFF ((uint32_t)(0xE8DC)) +#define IMXDPUV1_TCON1_SPG7MASKOFF_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_TCON1_SPG7MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG7MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKOFF_SPGMKOFF7_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG7MASKOFF_SPGMKOFF7_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG8PosOn */ +#define IMXDPUV1_TCON1_SPG8POSON ((uint32_t)(0xE8E0)) +#define IMXDPUV1_TCON1_SPG8POSON_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_TCON1_SPG8POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_Y8_SHIFT 0U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_X8_SHIFT 16U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG8POSON_SPGPSON_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG8MaskOn */ +#define IMXDPUV1_TCON1_SPG8MASKON ((uint32_t)(0xE8E4)) +#define IMXDPUV1_TCON1_SPG8MASKON_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_TCON1_SPG8MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKON_SPGMKON8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKON_SPGMKON8_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG8PosOff */ +#define IMXDPUV1_TCON1_SPG8POSOFF ((uint32_t)(0xE8E8)) +#define IMXDPUV1_TCON1_SPG8POSOFF_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_TCON1_SPG8POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_Y8_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_Y8_SHIFT 0U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_FIELD8_SHIFT 15U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_X8_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_X8_SHIFT 16U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG8POSOFF_SPGPSOFF_TOGGLE8_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG8MaskOff */ +#define IMXDPUV1_TCON1_SPG8MASKOFF ((uint32_t)(0xE8EC)) +#define IMXDPUV1_TCON1_SPG8MASKOFF_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_TCON1_SPG8MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG8MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKOFF_SPGMKOFF8_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG8MASKOFF_SPGMKOFF8_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG9PosOn */ +#define IMXDPUV1_TCON1_SPG9POSON ((uint32_t)(0xE8F0)) +#define IMXDPUV1_TCON1_SPG9POSON_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_TCON1_SPG9POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_Y9_SHIFT 0U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_X9_SHIFT 16U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG9POSON_SPGPSON_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG9MaskOn */ +#define IMXDPUV1_TCON1_SPG9MASKON ((uint32_t)(0xE8F4)) +#define IMXDPUV1_TCON1_SPG9MASKON_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_TCON1_SPG9MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKON_SPGMKON9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKON_SPGMKON9_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG9PosOff */ +#define IMXDPUV1_TCON1_SPG9POSOFF ((uint32_t)(0xE8F8)) +#define IMXDPUV1_TCON1_SPG9POSOFF_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_TCON1_SPG9POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_Y9_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_Y9_SHIFT 0U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_FIELD9_SHIFT 15U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_X9_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_X9_SHIFT 16U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG9POSOFF_SPGPSOFF_TOGGLE9_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG9MaskOff */ +#define IMXDPUV1_TCON1_SPG9MASKOFF ((uint32_t)(0xE8FC)) +#define IMXDPUV1_TCON1_SPG9MASKOFF_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_TCON1_SPG9MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG9MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKOFF_SPGMKOFF9_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG9MASKOFF_SPGMKOFF9_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG10PosOn */ +#define IMXDPUV1_TCON1_SPG10POSON ((uint32_t)(0xE900)) +#define IMXDPUV1_TCON1_SPG10POSON_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_TCON1_SPG10POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_Y10_SHIFT 0U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_X10_SHIFT 16U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG10POSON_SPGPSON_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG10MaskOn */ +#define IMXDPUV1_TCON1_SPG10MASKON ((uint32_t)(0xE904)) +#define IMXDPUV1_TCON1_SPG10MASKON_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_TCON1_SPG10MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKON_SPGMKON10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKON_SPGMKON10_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG10PosOff */ +#define IMXDPUV1_TCON1_SPG10POSOFF ((uint32_t)(0xE908)) +#define IMXDPUV1_TCON1_SPG10POSOFF_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_TCON1_SPG10POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_Y10_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_Y10_SHIFT 0U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_FIELD10_SHIFT 15U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_X10_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_X10_SHIFT 16U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG10POSOFF_SPGPSOFF_TOGGLE10_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG10MaskOff */ +#define IMXDPUV1_TCON1_SPG10MASKOFF ((uint32_t)(0xE90C)) +#define IMXDPUV1_TCON1_SPG10MASKOFF_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_TCON1_SPG10MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG10MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKOFF_SPGMKOFF10_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG10MASKOFF_SPGMKOFF10_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG11PosOn */ +#define IMXDPUV1_TCON1_SPG11POSON ((uint32_t)(0xE910)) +#define IMXDPUV1_TCON1_SPG11POSON_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_TCON1_SPG11POSON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11POSON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_Y11_SHIFT 0U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_X11_SHIFT 16U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG11POSON_SPGPSON_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG11MaskOn */ +#define IMXDPUV1_TCON1_SPG11MASKON ((uint32_t)(0xE914)) +#define IMXDPUV1_TCON1_SPG11MASKON_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_TCON1_SPG11MASKON_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11MASKON_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKON_SPGMKON11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKON_SPGMKON11_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SPG11PosOff */ +#define IMXDPUV1_TCON1_SPG11POSOFF ((uint32_t)(0xE918)) +#define IMXDPUV1_TCON1_SPG11POSOFF_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_TCON1_SPG11POSOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11POSOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_Y11_MASK 0x7FFFU +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_Y11_SHIFT 0U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_MASK 0x8000U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_FIELD11_SHIFT 15U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_X11_MASK 0x7FFF0000U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_X11_SHIFT 16U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_MASK 0x80000000U +#define IMXDPUV1_TCON1_SPG11POSOFF_SPGPSOFF_TOGGLE11_SHIFT 31U + +/* Register: IMXDPUV1_tcon1_SPG11MaskOff */ +#define IMXDPUV1_TCON1_SPG11MASKOFF ((uint32_t)(0xE91C)) +#define IMXDPUV1_TCON1_SPG11MASKOFF_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_TCON1_SPG11MASKOFF_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SPG11MASKOFF_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKOFF_SPGMKOFF11_MASK 0x7FFFFFFFU +#define IMXDPUV1_TCON1_SPG11MASKOFF_SPGMKOFF11_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx0Sigs */ +#define IMXDPUV1_TCON1_SMX0SIGS ((uint32_t)(0xE920)) +#define IMXDPUV1_TCON1_SMX0SIGS_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_TCON1_SMX0SIGS_RESET_VALUE 0x2U +#define IMXDPUV1_TCON1_SMX0SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX0SIGS_SMX0SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx0FctTable */ +#define IMXDPUV1_TCON1_SMX0FCTTABLE ((uint32_t)(0xE924)) +#define IMXDPUV1_TCON1_SMX0FCTTABLE_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_TCON1_SMX0FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON1_SMX0FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX0FCTTABLE_SMXFCT0_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX0FCTTABLE_SMXFCT0_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx1Sigs */ +#define IMXDPUV1_TCON1_SMX1SIGS ((uint32_t)(0xE928)) +#define IMXDPUV1_TCON1_SMX1SIGS_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_TCON1_SMX1SIGS_RESET_VALUE 0x3U +#define IMXDPUV1_TCON1_SMX1SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX1SIGS_SMX1SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx1FctTable */ +#define IMXDPUV1_TCON1_SMX1FCTTABLE ((uint32_t)(0xE92C)) +#define IMXDPUV1_TCON1_SMX1FCTTABLE_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_TCON1_SMX1FCTTABLE_RESET_VALUE 0x1U +#define IMXDPUV1_TCON1_SMX1FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX1FCTTABLE_SMXFCT1_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX1FCTTABLE_SMXFCT1_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx2Sigs */ +#define IMXDPUV1_TCON1_SMX2SIGS ((uint32_t)(0xE930)) +#define IMXDPUV1_TCON1_SMX2SIGS_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_TCON1_SMX2SIGS_RESET_VALUE 0x2CU +#define IMXDPUV1_TCON1_SMX2SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX2SIGS_SMX2SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx2FctTable */ +#define IMXDPUV1_TCON1_SMX2FCTTABLE ((uint32_t)(0xE934)) +#define IMXDPUV1_TCON1_SMX2FCTTABLE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_TCON1_SMX2FCTTABLE_RESET_VALUE 0x8U +#define IMXDPUV1_TCON1_SMX2FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX2FCTTABLE_SMXFCT2_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX2FCTTABLE_SMXFCT2_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx3Sigs */ +#define IMXDPUV1_TCON1_SMX3SIGS ((uint32_t)(0xE938)) +#define IMXDPUV1_TCON1_SMX3SIGS_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_TCON1_SMX3SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX3SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX3SIGS_SMX3SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx3FctTable */ +#define IMXDPUV1_TCON1_SMX3FCTTABLE ((uint32_t)(0xE93C)) +#define IMXDPUV1_TCON1_SMX3FCTTABLE_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_TCON1_SMX3FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX3FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX3FCTTABLE_SMXFCT3_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX3FCTTABLE_SMXFCT3_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx4Sigs */ +#define IMXDPUV1_TCON1_SMX4SIGS ((uint32_t)(0xE940)) +#define IMXDPUV1_TCON1_SMX4SIGS_OFFSET ((uint32_t)(0x140)) +#define IMXDPUV1_TCON1_SMX4SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX4SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX4SIGS_SMX4SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx4FctTable */ +#define IMXDPUV1_TCON1_SMX4FCTTABLE ((uint32_t)(0xE944)) +#define IMXDPUV1_TCON1_SMX4FCTTABLE_OFFSET ((uint32_t)(0x144)) +#define IMXDPUV1_TCON1_SMX4FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX4FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX4FCTTABLE_SMXFCT4_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX4FCTTABLE_SMXFCT4_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx5Sigs */ +#define IMXDPUV1_TCON1_SMX5SIGS ((uint32_t)(0xE948)) +#define IMXDPUV1_TCON1_SMX5SIGS_OFFSET ((uint32_t)(0x148)) +#define IMXDPUV1_TCON1_SMX5SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX5SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX5SIGS_SMX5SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx5FctTable */ +#define IMXDPUV1_TCON1_SMX5FCTTABLE ((uint32_t)(0xE94C)) +#define IMXDPUV1_TCON1_SMX5FCTTABLE_OFFSET ((uint32_t)(0x14C)) +#define IMXDPUV1_TCON1_SMX5FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX5FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX5FCTTABLE_SMXFCT5_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX5FCTTABLE_SMXFCT5_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx6Sigs */ +#define IMXDPUV1_TCON1_SMX6SIGS ((uint32_t)(0xE950)) +#define IMXDPUV1_TCON1_SMX6SIGS_OFFSET ((uint32_t)(0x150)) +#define IMXDPUV1_TCON1_SMX6SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX6SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX6SIGS_SMX6SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx6FctTable */ +#define IMXDPUV1_TCON1_SMX6FCTTABLE ((uint32_t)(0xE954)) +#define IMXDPUV1_TCON1_SMX6FCTTABLE_OFFSET ((uint32_t)(0x154)) +#define IMXDPUV1_TCON1_SMX6FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX6FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX6FCTTABLE_SMXFCT6_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX6FCTTABLE_SMXFCT6_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx7Sigs */ +#define IMXDPUV1_TCON1_SMX7SIGS ((uint32_t)(0xE958)) +#define IMXDPUV1_TCON1_SMX7SIGS_OFFSET ((uint32_t)(0x158)) +#define IMXDPUV1_TCON1_SMX7SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX7SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX7SIGS_SMX7SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx7FctTable */ +#define IMXDPUV1_TCON1_SMX7FCTTABLE ((uint32_t)(0xE95C)) +#define IMXDPUV1_TCON1_SMX7FCTTABLE_OFFSET ((uint32_t)(0x15C)) +#define IMXDPUV1_TCON1_SMX7FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX7FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX7FCTTABLE_SMXFCT7_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX7FCTTABLE_SMXFCT7_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx8Sigs */ +#define IMXDPUV1_TCON1_SMX8SIGS ((uint32_t)(0xE960)) +#define IMXDPUV1_TCON1_SMX8SIGS_OFFSET ((uint32_t)(0x160)) +#define IMXDPUV1_TCON1_SMX8SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX8SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX8SIGS_SMX8SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx8FctTable */ +#define IMXDPUV1_TCON1_SMX8FCTTABLE ((uint32_t)(0xE964)) +#define IMXDPUV1_TCON1_SMX8FCTTABLE_OFFSET ((uint32_t)(0x164)) +#define IMXDPUV1_TCON1_SMX8FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX8FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX8FCTTABLE_SMXFCT8_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX8FCTTABLE_SMXFCT8_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx9Sigs */ +#define IMXDPUV1_TCON1_SMX9SIGS ((uint32_t)(0xE968)) +#define IMXDPUV1_TCON1_SMX9SIGS_OFFSET ((uint32_t)(0x168)) +#define IMXDPUV1_TCON1_SMX9SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX9SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX9SIGS_SMX9SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx9FctTable */ +#define IMXDPUV1_TCON1_SMX9FCTTABLE ((uint32_t)(0xE96C)) +#define IMXDPUV1_TCON1_SMX9FCTTABLE_OFFSET ((uint32_t)(0x16C)) +#define IMXDPUV1_TCON1_SMX9FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX9FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX9FCTTABLE_SMXFCT9_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX9FCTTABLE_SMXFCT9_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx10Sigs */ +#define IMXDPUV1_TCON1_SMX10SIGS ((uint32_t)(0xE970)) +#define IMXDPUV1_TCON1_SMX10SIGS_OFFSET ((uint32_t)(0x170)) +#define IMXDPUV1_TCON1_SMX10SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX10SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX10SIGS_SMX10SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx10FctTable */ +#define IMXDPUV1_TCON1_SMX10FCTTABLE ((uint32_t)(0xE974)) +#define IMXDPUV1_TCON1_SMX10FCTTABLE_OFFSET ((uint32_t)(0x174)) +#define IMXDPUV1_TCON1_SMX10FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX10FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX10FCTTABLE_SMXFCT10_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX10FCTTABLE_SMXFCT10_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_SMx11Sigs */ +#define IMXDPUV1_TCON1_SMX11SIGS ((uint32_t)(0xE978)) +#define IMXDPUV1_TCON1_SMX11SIGS_OFFSET ((uint32_t)(0x178)) +#define IMXDPUV1_TCON1_SMX11SIGS_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX11SIGS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S0_MASK 0x7U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S0_SHIFT 0U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S1_MASK 0x38U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S1_SHIFT 3U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S2_MASK 0x1C0U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S2_SHIFT 6U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S3_MASK 0xE00U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S3_SHIFT 9U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S4_MASK 0x7000U +#define IMXDPUV1_TCON1_SMX11SIGS_SMX11SIGS_S4_SHIFT 12U + +/* Register: IMXDPUV1_tcon1_SMx11FctTable */ +#define IMXDPUV1_TCON1_SMX11FCTTABLE ((uint32_t)(0xE97C)) +#define IMXDPUV1_TCON1_SMX11FCTTABLE_OFFSET ((uint32_t)(0x17C)) +#define IMXDPUV1_TCON1_SMX11FCTTABLE_RESET_VALUE 0U +#define IMXDPUV1_TCON1_SMX11FCTTABLE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX11FCTTABLE_SMXFCT11_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_SMX11FCTTABLE_SMXFCT11_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_Reset_Over_Unferflow */ +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW ((uint32_t)(0xE980)) +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_OFFSET ((uint32_t)(0x180)) +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_VALUE 0U +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_STATUS_MASK 0x1U +#define IMXDPUV1_TCON1_RESET_OVER_UNFERFLOW_RESET_STATUS_SHIFT 0U + +/* Register: IMXDPUV1_tcon1_Dual_Debug */ +#define IMXDPUV1_TCON1_DUAL_DEBUG ((uint32_t)(0xE984)) +#define IMXDPUV1_TCON1_DUAL_DEBUG_OFFSET ((uint32_t)(0x184)) +#define IMXDPUV1_TCON1_DUAL_DEBUG_RESET_VALUE 0U +#define IMXDPUV1_TCON1_DUAL_DEBUG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_MASK 0x1U +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_OVERFLOW_SHIFT 0U +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_MASK 0x2U +#define IMXDPUV1_TCON1_DUAL_DEBUG_LOWER_FIFO_UNDERFLOW_SHIFT 1U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_MASK 0x10U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_OVERFLOW_SHIFT 4U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_MASK 0x20U +#define IMXDPUV1_TCON1_DUAL_DEBUG_UPPER_FIFO_UNDERFLOW_SHIFT 5U + +/* Register: IMXDPUV1_sig1_LockUnlock */ +#define IMXDPUV1_SIG1_LOCKUNLOCK ((uint32_t)(0xEC00)) +#define IMXDPUV1_SIG1_LOCKUNLOCK_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_SIG1_LOCKUNLOCK_RESET_VALUE 0U +#define IMXDPUV1_SIG1_LOCKUNLOCK_RESET_MASK 0U +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK_SHIFT 0U +/* Field Value: LOCKUNLOCK__LOCK_KEY, Decrements the unlock counter. When + * the counter value is null, lock protection is active. Reset counter value + * is 1. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__LOCK_KEY 0x5651F763U +/* Field Value: LOCKUNLOCK__UNLOCK_KEY, Increments the unlock counter. Max + * allowed value is 15. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__UNLOCK_KEY 0x691DB936U +/* Field Value: LOCKUNLOCK__PRIVILEGE_KEY, Enables privilege protection. Disabled + * after reset. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__PRIVILEGE_KEY 0xAEE95CDCU +/* Field Value: LOCKUNLOCK__UNPRIVILEGE_KEY, Disables privilege protection. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__UNPRIVILEGE_KEY 0xB5E2466EU +/* Field Value: LOCKUNLOCK__FREEZE_KEY, Freezes current protection status. + * Writing keys to this register has no more effect until reset. */ +#define IMXDPUV1_SIG1_LOCKUNLOCK_LOCKUNLOCK__FREEZE_KEY 0xFBE8B1E6U + +/* Register: IMXDPUV1_sig1_LockStatus */ +#define IMXDPUV1_SIG1_LOCKSTATUS ((uint32_t)(0xEC04)) +#define IMXDPUV1_SIG1_LOCKSTATUS_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_SIG1_LOCKSTATUS_RESET_VALUE 0U +#define IMXDPUV1_SIG1_LOCKSTATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_LOCKSTATUS_LOCKSTATUS_MASK 0x1U +#define IMXDPUV1_SIG1_LOCKSTATUS_LOCKSTATUS_SHIFT 0U +#define IMXDPUV1_SIG1_LOCKSTATUS_PRIVILEGESTATUS_MASK 0x10U +#define IMXDPUV1_SIG1_LOCKSTATUS_PRIVILEGESTATUS_SHIFT 4U +#define IMXDPUV1_SIG1_LOCKSTATUS_FREEZESTATUS_MASK 0x100U +#define IMXDPUV1_SIG1_LOCKSTATUS_FREEZESTATUS_SHIFT 8U + +/* Register: IMXDPUV1_sig1_StaticControl */ +#define IMXDPUV1_SIG1_STATICCONTROL ((uint32_t)(0xEC08)) +#define IMXDPUV1_SIG1_STATICCONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_SIG1_STATICCONTROL_RESET_VALUE 0x8000000U +#define IMXDPUV1_SIG1_STATICCONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_STATICCONTROL_SHDEN_MASK 0x1U +#define IMXDPUV1_SIG1_STATICCONTROL_SHDEN_SHIFT 0U +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL_MASK 0x10U +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL_SHIFT 4U +/* Field Value: SHDLDSEL__LOCAL, Shadows are loaded at start of frame for + * each evaluation window for which ShdLdReq has been set. */ +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL__LOCAL 0U +/* Field Value: SHDLDSEL__GLOBAL, Shadows of all evaluation windows are loaded + * synchronous to the display stream (shadow load token received on + * frame input port). */ +#define IMXDPUV1_SIG1_STATICCONTROL_SHDLDSEL__GLOBAL 0x1U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRES_MASK 0xFF0000U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRES_SHIFT 16U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRESRESET_MASK 0xFF000000U +#define IMXDPUV1_SIG1_STATICCONTROL_ERRTHRESRESET_SHIFT 24U + +/* Register: IMXDPUV1_sig1_PanicColor */ +#define IMXDPUV1_SIG1_PANICCOLOR ((uint32_t)(0xEC0C)) +#define IMXDPUV1_SIG1_PANICCOLOR_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_SIG1_PANICCOLOR_RESET_VALUE 0U +#define IMXDPUV1_SIG1_PANICCOLOR_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_PANICCOLOR_PANICALPHA_MASK 0x80U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICALPHA_SHIFT 7U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICBLUE_MASK 0xFF00U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICBLUE_SHIFT 8U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICGREEN_MASK 0xFF0000U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICGREEN_SHIFT 16U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICRED_MASK 0xFF000000U +#define IMXDPUV1_SIG1_PANICCOLOR_PANICRED_SHIFT 24U + +/* Register: IMXDPUV1_sig1_EvalControl0 */ +#define IMXDPUV1_SIG1_EVALCONTROL0 ((uint32_t)(0xEC10)) +#define IMXDPUV1_SIG1_EVALCONTROL0_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_SIG1_EVALCONTROL0_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL0_ENEVALWIN0_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENEVALWIN0_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENCRC0_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENCRC0_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAMASK0_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAMASK0_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAINV0_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL0_ALPHAINV0_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENLOCALPANIC0_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENLOCALPANIC0_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENGLOBALPANIC0_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL0_ENGLOBALPANIC0_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft0 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT0 ((uint32_t)(0xEC14)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_XEVALUPPERLEFT0_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_XEVALUPPERLEFT0_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_YEVALUPPERLEFT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT0_YEVALUPPERLEFT0_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight0 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0 ((uint32_t)(0xEC18)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_XEVALLOWERRIGHT0_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT0_YEVALLOWERRIGHT0_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef0 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF0 ((uint32_t)(0xEC1C)) +#define IMXDPUV1_SIG1_SIGCRCREDREF0_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_SIG1_SIGCRCREDREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF0_SIGCRCREDREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF0_SIGCRCREDREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef0 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF0 ((uint32_t)(0xEC20)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_SIGCRCGREENREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF0_SIGCRCGREENREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef0 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0 ((uint32_t)(0xEC24)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_SIGCRCBLUEREF0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF0_SIGCRCBLUEREF0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed0 */ +#define IMXDPUV1_SIG1_SIGCRCRED0 ((uint32_t)(0xEC28)) +#define IMXDPUV1_SIG1_SIGCRCRED0_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_SIG1_SIGCRCRED0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED0_SIGCRCRED0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED0_SIGCRCRED0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen0 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN0 ((uint32_t)(0xEC2C)) +#define IMXDPUV1_SIG1_SIGCRCGREEN0_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_SIG1_SIGCRCGREEN0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN0_SIGCRCGREEN0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN0_SIGCRCGREEN0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue0 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE0 ((uint32_t)(0xEC30)) +#define IMXDPUV1_SIG1_SIGCRCBLUE0_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_SIG1_SIGCRCBLUE0_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE0_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE0_SIGCRCBLUE0_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE0_SIGCRCBLUE0_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl1 */ +#define IMXDPUV1_SIG1_EVALCONTROL1 ((uint32_t)(0xEC34)) +#define IMXDPUV1_SIG1_EVALCONTROL1_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_SIG1_EVALCONTROL1_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL1_ENEVALWIN1_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENEVALWIN1_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENCRC1_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENCRC1_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAMASK1_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAMASK1_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAINV1_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL1_ALPHAINV1_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENLOCALPANIC1_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENLOCALPANIC1_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENGLOBALPANIC1_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL1_ENGLOBALPANIC1_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft1 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT1 ((uint32_t)(0xEC38)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_XEVALUPPERLEFT1_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_XEVALUPPERLEFT1_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_YEVALUPPERLEFT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT1_YEVALUPPERLEFT1_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight1 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1 ((uint32_t)(0xEC3C)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_XEVALLOWERRIGHT1_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT1_YEVALLOWERRIGHT1_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef1 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF1 ((uint32_t)(0xEC40)) +#define IMXDPUV1_SIG1_SIGCRCREDREF1_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_SIG1_SIGCRCREDREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF1_SIGCRCREDREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF1_SIGCRCREDREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef1 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF1 ((uint32_t)(0xEC44)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_SIGCRCGREENREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF1_SIGCRCGREENREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef1 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1 ((uint32_t)(0xEC48)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_SIGCRCBLUEREF1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF1_SIGCRCBLUEREF1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed1 */ +#define IMXDPUV1_SIG1_SIGCRCRED1 ((uint32_t)(0xEC4C)) +#define IMXDPUV1_SIG1_SIGCRCRED1_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_SIG1_SIGCRCRED1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED1_SIGCRCRED1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED1_SIGCRCRED1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen1 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN1 ((uint32_t)(0xEC50)) +#define IMXDPUV1_SIG1_SIGCRCGREEN1_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_SIG1_SIGCRCGREEN1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN1_SIGCRCGREEN1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN1_SIGCRCGREEN1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue1 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE1 ((uint32_t)(0xEC54)) +#define IMXDPUV1_SIG1_SIGCRCBLUE1_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_SIG1_SIGCRCBLUE1_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE1_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE1_SIGCRCBLUE1_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE1_SIGCRCBLUE1_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl2 */ +#define IMXDPUV1_SIG1_EVALCONTROL2 ((uint32_t)(0xEC58)) +#define IMXDPUV1_SIG1_EVALCONTROL2_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_SIG1_EVALCONTROL2_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL2_ENEVALWIN2_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENEVALWIN2_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENCRC2_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENCRC2_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAMASK2_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAMASK2_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAINV2_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL2_ALPHAINV2_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENLOCALPANIC2_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENLOCALPANIC2_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENGLOBALPANIC2_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL2_ENGLOBALPANIC2_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft2 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT2 ((uint32_t)(0xEC5C)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_XEVALUPPERLEFT2_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_XEVALUPPERLEFT2_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_YEVALUPPERLEFT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT2_YEVALUPPERLEFT2_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight2 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2 ((uint32_t)(0xEC60)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_XEVALLOWERRIGHT2_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT2_YEVALLOWERRIGHT2_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef2 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF2 ((uint32_t)(0xEC64)) +#define IMXDPUV1_SIG1_SIGCRCREDREF2_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_SIG1_SIGCRCREDREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF2_SIGCRCREDREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF2_SIGCRCREDREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef2 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF2 ((uint32_t)(0xEC68)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_SIGCRCGREENREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF2_SIGCRCGREENREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef2 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2 ((uint32_t)(0xEC6C)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_SIGCRCBLUEREF2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF2_SIGCRCBLUEREF2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed2 */ +#define IMXDPUV1_SIG1_SIGCRCRED2 ((uint32_t)(0xEC70)) +#define IMXDPUV1_SIG1_SIGCRCRED2_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_SIG1_SIGCRCRED2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED2_SIGCRCRED2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED2_SIGCRCRED2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen2 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN2 ((uint32_t)(0xEC74)) +#define IMXDPUV1_SIG1_SIGCRCGREEN2_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_SIG1_SIGCRCGREEN2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN2_SIGCRCGREEN2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN2_SIGCRCGREEN2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue2 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE2 ((uint32_t)(0xEC78)) +#define IMXDPUV1_SIG1_SIGCRCBLUE2_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_SIG1_SIGCRCBLUE2_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE2_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE2_SIGCRCBLUE2_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE2_SIGCRCBLUE2_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl3 */ +#define IMXDPUV1_SIG1_EVALCONTROL3 ((uint32_t)(0xEC7C)) +#define IMXDPUV1_SIG1_EVALCONTROL3_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_SIG1_EVALCONTROL3_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL3_ENEVALWIN3_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENEVALWIN3_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENCRC3_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENCRC3_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAMASK3_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAMASK3_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAINV3_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL3_ALPHAINV3_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENLOCALPANIC3_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENLOCALPANIC3_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENGLOBALPANIC3_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL3_ENGLOBALPANIC3_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft3 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT3 ((uint32_t)(0xEC80)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_XEVALUPPERLEFT3_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_XEVALUPPERLEFT3_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_YEVALUPPERLEFT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT3_YEVALUPPERLEFT3_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight3 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3 ((uint32_t)(0xEC84)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_XEVALLOWERRIGHT3_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT3_YEVALLOWERRIGHT3_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef3 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF3 ((uint32_t)(0xEC88)) +#define IMXDPUV1_SIG1_SIGCRCREDREF3_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_SIG1_SIGCRCREDREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF3_SIGCRCREDREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF3_SIGCRCREDREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef3 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF3 ((uint32_t)(0xEC8C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_SIGCRCGREENREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF3_SIGCRCGREENREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef3 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3 ((uint32_t)(0xEC90)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_OFFSET ((uint32_t)(0x90)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_SIGCRCBLUEREF3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF3_SIGCRCBLUEREF3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed3 */ +#define IMXDPUV1_SIG1_SIGCRCRED3 ((uint32_t)(0xEC94)) +#define IMXDPUV1_SIG1_SIGCRCRED3_OFFSET ((uint32_t)(0x94)) +#define IMXDPUV1_SIG1_SIGCRCRED3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED3_SIGCRCRED3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED3_SIGCRCRED3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen3 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN3 ((uint32_t)(0xEC98)) +#define IMXDPUV1_SIG1_SIGCRCGREEN3_OFFSET ((uint32_t)(0x98)) +#define IMXDPUV1_SIG1_SIGCRCGREEN3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN3_SIGCRCGREEN3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN3_SIGCRCGREEN3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue3 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE3 ((uint32_t)(0xEC9C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE3_OFFSET ((uint32_t)(0x9C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE3_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE3_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE3_SIGCRCBLUE3_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE3_SIGCRCBLUE3_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl4 */ +#define IMXDPUV1_SIG1_EVALCONTROL4 ((uint32_t)(0xECA0)) +#define IMXDPUV1_SIG1_EVALCONTROL4_OFFSET ((uint32_t)(0xA0)) +#define IMXDPUV1_SIG1_EVALCONTROL4_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL4_ENEVALWIN4_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENEVALWIN4_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENCRC4_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENCRC4_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAMASK4_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAMASK4_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAINV4_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL4_ALPHAINV4_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENLOCALPANIC4_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENLOCALPANIC4_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENGLOBALPANIC4_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL4_ENGLOBALPANIC4_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft4 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT4 ((uint32_t)(0xECA4)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_OFFSET ((uint32_t)(0xA4)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_XEVALUPPERLEFT4_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_XEVALUPPERLEFT4_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_YEVALUPPERLEFT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT4_YEVALUPPERLEFT4_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight4 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4 ((uint32_t)(0xECA8)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_OFFSET ((uint32_t)(0xA8)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_XEVALLOWERRIGHT4_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT4_YEVALLOWERRIGHT4_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef4 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF4 ((uint32_t)(0xECAC)) +#define IMXDPUV1_SIG1_SIGCRCREDREF4_OFFSET ((uint32_t)(0xAC)) +#define IMXDPUV1_SIG1_SIGCRCREDREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF4_SIGCRCREDREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF4_SIGCRCREDREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef4 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF4 ((uint32_t)(0xECB0)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_OFFSET ((uint32_t)(0xB0)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_SIGCRCGREENREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF4_SIGCRCGREENREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef4 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4 ((uint32_t)(0xECB4)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_OFFSET ((uint32_t)(0xB4)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_SIGCRCBLUEREF4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF4_SIGCRCBLUEREF4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed4 */ +#define IMXDPUV1_SIG1_SIGCRCRED4 ((uint32_t)(0xECB8)) +#define IMXDPUV1_SIG1_SIGCRCRED4_OFFSET ((uint32_t)(0xB8)) +#define IMXDPUV1_SIG1_SIGCRCRED4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED4_SIGCRCRED4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED4_SIGCRCRED4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen4 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN4 ((uint32_t)(0xECBC)) +#define IMXDPUV1_SIG1_SIGCRCGREEN4_OFFSET ((uint32_t)(0xBC)) +#define IMXDPUV1_SIG1_SIGCRCGREEN4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN4_SIGCRCGREEN4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN4_SIGCRCGREEN4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue4 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE4 ((uint32_t)(0xECC0)) +#define IMXDPUV1_SIG1_SIGCRCBLUE4_OFFSET ((uint32_t)(0xC0)) +#define IMXDPUV1_SIG1_SIGCRCBLUE4_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE4_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE4_SIGCRCBLUE4_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE4_SIGCRCBLUE4_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl5 */ +#define IMXDPUV1_SIG1_EVALCONTROL5 ((uint32_t)(0xECC4)) +#define IMXDPUV1_SIG1_EVALCONTROL5_OFFSET ((uint32_t)(0xC4)) +#define IMXDPUV1_SIG1_EVALCONTROL5_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL5_ENEVALWIN5_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENEVALWIN5_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENCRC5_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENCRC5_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAMASK5_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAMASK5_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAINV5_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL5_ALPHAINV5_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENLOCALPANIC5_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENLOCALPANIC5_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENGLOBALPANIC5_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL5_ENGLOBALPANIC5_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft5 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT5 ((uint32_t)(0xECC8)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_OFFSET ((uint32_t)(0xC8)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_XEVALUPPERLEFT5_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_XEVALUPPERLEFT5_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_YEVALUPPERLEFT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT5_YEVALUPPERLEFT5_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight5 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5 ((uint32_t)(0xECCC)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_OFFSET ((uint32_t)(0xCC)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_XEVALLOWERRIGHT5_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT5_YEVALLOWERRIGHT5_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef5 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF5 ((uint32_t)(0xECD0)) +#define IMXDPUV1_SIG1_SIGCRCREDREF5_OFFSET ((uint32_t)(0xD0)) +#define IMXDPUV1_SIG1_SIGCRCREDREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF5_SIGCRCREDREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF5_SIGCRCREDREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef5 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF5 ((uint32_t)(0xECD4)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_OFFSET ((uint32_t)(0xD4)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_SIGCRCGREENREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF5_SIGCRCGREENREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef5 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5 ((uint32_t)(0xECD8)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_OFFSET ((uint32_t)(0xD8)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_SIGCRCBLUEREF5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF5_SIGCRCBLUEREF5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed5 */ +#define IMXDPUV1_SIG1_SIGCRCRED5 ((uint32_t)(0xECDC)) +#define IMXDPUV1_SIG1_SIGCRCRED5_OFFSET ((uint32_t)(0xDC)) +#define IMXDPUV1_SIG1_SIGCRCRED5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED5_SIGCRCRED5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED5_SIGCRCRED5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen5 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN5 ((uint32_t)(0xECE0)) +#define IMXDPUV1_SIG1_SIGCRCGREEN5_OFFSET ((uint32_t)(0xE0)) +#define IMXDPUV1_SIG1_SIGCRCGREEN5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN5_SIGCRCGREEN5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN5_SIGCRCGREEN5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue5 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE5 ((uint32_t)(0xECE4)) +#define IMXDPUV1_SIG1_SIGCRCBLUE5_OFFSET ((uint32_t)(0xE4)) +#define IMXDPUV1_SIG1_SIGCRCBLUE5_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE5_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE5_SIGCRCBLUE5_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE5_SIGCRCBLUE5_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl6 */ +#define IMXDPUV1_SIG1_EVALCONTROL6 ((uint32_t)(0xECE8)) +#define IMXDPUV1_SIG1_EVALCONTROL6_OFFSET ((uint32_t)(0xE8)) +#define IMXDPUV1_SIG1_EVALCONTROL6_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL6_ENEVALWIN6_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENEVALWIN6_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENCRC6_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENCRC6_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAMASK6_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAMASK6_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAINV6_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL6_ALPHAINV6_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENLOCALPANIC6_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENLOCALPANIC6_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENGLOBALPANIC6_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL6_ENGLOBALPANIC6_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft6 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT6 ((uint32_t)(0xECEC)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_OFFSET ((uint32_t)(0xEC)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_XEVALUPPERLEFT6_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_XEVALUPPERLEFT6_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_YEVALUPPERLEFT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT6_YEVALUPPERLEFT6_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight6 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6 ((uint32_t)(0xECF0)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_OFFSET ((uint32_t)(0xF0)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_XEVALLOWERRIGHT6_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT6_YEVALLOWERRIGHT6_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef6 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF6 ((uint32_t)(0xECF4)) +#define IMXDPUV1_SIG1_SIGCRCREDREF6_OFFSET ((uint32_t)(0xF4)) +#define IMXDPUV1_SIG1_SIGCRCREDREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF6_SIGCRCREDREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF6_SIGCRCREDREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef6 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF6 ((uint32_t)(0xECF8)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_OFFSET ((uint32_t)(0xF8)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_SIGCRCGREENREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF6_SIGCRCGREENREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef6 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6 ((uint32_t)(0xECFC)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_OFFSET ((uint32_t)(0xFC)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_SIGCRCBLUEREF6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF6_SIGCRCBLUEREF6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed6 */ +#define IMXDPUV1_SIG1_SIGCRCRED6 ((uint32_t)(0xED00)) +#define IMXDPUV1_SIG1_SIGCRCRED6_OFFSET ((uint32_t)(0x100)) +#define IMXDPUV1_SIG1_SIGCRCRED6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED6_SIGCRCRED6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED6_SIGCRCRED6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen6 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN6 ((uint32_t)(0xED04)) +#define IMXDPUV1_SIG1_SIGCRCGREEN6_OFFSET ((uint32_t)(0x104)) +#define IMXDPUV1_SIG1_SIGCRCGREEN6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN6_SIGCRCGREEN6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN6_SIGCRCGREEN6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue6 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE6 ((uint32_t)(0xED08)) +#define IMXDPUV1_SIG1_SIGCRCBLUE6_OFFSET ((uint32_t)(0x108)) +#define IMXDPUV1_SIG1_SIGCRCBLUE6_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE6_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE6_SIGCRCBLUE6_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE6_SIGCRCBLUE6_SHIFT 0U + +/* Register: IMXDPUV1_sig1_EvalControl7 */ +#define IMXDPUV1_SIG1_EVALCONTROL7 ((uint32_t)(0xED0C)) +#define IMXDPUV1_SIG1_EVALCONTROL7_OFFSET ((uint32_t)(0x10C)) +#define IMXDPUV1_SIG1_EVALCONTROL7_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALCONTROL7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALCONTROL7_ENEVALWIN7_MASK 0x1U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENEVALWIN7_SHIFT 0U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENCRC7_MASK 0x2U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENCRC7_SHIFT 1U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAMASK7_MASK 0x100U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAMASK7_SHIFT 8U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAINV7_MASK 0x200U +#define IMXDPUV1_SIG1_EVALCONTROL7_ALPHAINV7_SHIFT 9U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENLOCALPANIC7_MASK 0x10000U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENLOCALPANIC7_SHIFT 16U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENGLOBALPANIC7_MASK 0x20000U +#define IMXDPUV1_SIG1_EVALCONTROL7_ENGLOBALPANIC7_SHIFT 17U + +/* Register: IMXDPUV1_sig1_EvalUpperLeft7 */ +#define IMXDPUV1_SIG1_EVALUPPERLEFT7 ((uint32_t)(0xED10)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_OFFSET ((uint32_t)(0x110)) +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_XEVALUPPERLEFT7_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_XEVALUPPERLEFT7_SHIFT 0U +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_YEVALUPPERLEFT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALUPPERLEFT7_YEVALUPPERLEFT7_SHIFT 16U + +/* Register: IMXDPUV1_sig1_EvalLowerRight7 */ +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7 ((uint32_t)(0xED14)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_OFFSET ((uint32_t)(0x114)) +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_RESET_VALUE 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_MASK 0x3FFFU +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_XEVALLOWERRIGHT7_SHIFT 0U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_MASK 0x3FFF0000U +#define IMXDPUV1_SIG1_EVALLOWERRIGHT7_YEVALLOWERRIGHT7_SHIFT 16U + +/* Register: IMXDPUV1_sig1_SigCRCRedRef7 */ +#define IMXDPUV1_SIG1_SIGCRCREDREF7 ((uint32_t)(0xED18)) +#define IMXDPUV1_SIG1_SIGCRCREDREF7_OFFSET ((uint32_t)(0x118)) +#define IMXDPUV1_SIG1_SIGCRCREDREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF7_SIGCRCREDREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCREDREF7_SIGCRCREDREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreenRef7 */ +#define IMXDPUV1_SIG1_SIGCRCGREENREF7 ((uint32_t)(0xED1C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_OFFSET ((uint32_t)(0x11C)) +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_SIGCRCGREENREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREENREF7_SIGCRCGREENREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlueRef7 */ +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7 ((uint32_t)(0xED20)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_OFFSET ((uint32_t)(0x120)) +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_SIGCRCBLUEREF7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUEREF7_SIGCRCBLUEREF7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCRed7 */ +#define IMXDPUV1_SIG1_SIGCRCRED7 ((uint32_t)(0xED24)) +#define IMXDPUV1_SIG1_SIGCRCRED7_OFFSET ((uint32_t)(0x124)) +#define IMXDPUV1_SIG1_SIGCRCRED7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED7_SIGCRCRED7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCRED7_SIGCRCRED7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCGreen7 */ +#define IMXDPUV1_SIG1_SIGCRCGREEN7 ((uint32_t)(0xED28)) +#define IMXDPUV1_SIG1_SIGCRCGREEN7_OFFSET ((uint32_t)(0x128)) +#define IMXDPUV1_SIG1_SIGCRCGREEN7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN7_SIGCRCGREEN7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCGREEN7_SIGCRCGREEN7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SigCRCBlue7 */ +#define IMXDPUV1_SIG1_SIGCRCBLUE7 ((uint32_t)(0xED2C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE7_OFFSET ((uint32_t)(0x12C)) +#define IMXDPUV1_SIG1_SIGCRCBLUE7_RESET_VALUE 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE7_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE7_SIGCRCBLUE7_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SIGCRCBLUE7_SIGCRCBLUE7_SHIFT 0U + +/* Register: IMXDPUV1_sig1_ShadowLoad */ +#define IMXDPUV1_SIG1_SHADOWLOAD ((uint32_t)(0xED30)) +#define IMXDPUV1_SIG1_SHADOWLOAD_OFFSET ((uint32_t)(0x130)) +#define IMXDPUV1_SIG1_SHADOWLOAD_RESET_VALUE 0U +#define IMXDPUV1_SIG1_SHADOWLOAD_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SHADOWLOAD_SHDLDREQ_MASK 0xFFU +#define IMXDPUV1_SIG1_SHADOWLOAD_SHDLDREQ_SHIFT 0U + +/* Register: IMXDPUV1_sig1_ContinuousMode */ +#define IMXDPUV1_SIG1_CONTINUOUSMODE ((uint32_t)(0xED34)) +#define IMXDPUV1_SIG1_CONTINUOUSMODE_OFFSET ((uint32_t)(0x134)) +#define IMXDPUV1_SIG1_CONTINUOUSMODE_RESET_VALUE 0U +#define IMXDPUV1_SIG1_CONTINUOUSMODE_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_CONTINUOUSMODE_ENCONT_MASK 0x1U +#define IMXDPUV1_SIG1_CONTINUOUSMODE_ENCONT_SHIFT 0U + +/* Register: IMXDPUV1_sig1_SoftwareKick */ +#define IMXDPUV1_SIG1_SOFTWAREKICK ((uint32_t)(0xED38)) +#define IMXDPUV1_SIG1_SOFTWAREKICK_OFFSET ((uint32_t)(0x138)) +#define IMXDPUV1_SIG1_SOFTWAREKICK_RESET_VALUE 0U +#define IMXDPUV1_SIG1_SOFTWAREKICK_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_SOFTWAREKICK_KICK_MASK 0x1U +#define IMXDPUV1_SIG1_SOFTWAREKICK_KICK_SHIFT 0U + +/* Register: IMXDPUV1_sig1_Status */ +#define IMXDPUV1_SIG1_STATUS ((uint32_t)(0xED3C)) +#define IMXDPUV1_SIG1_STATUS_OFFSET ((uint32_t)(0x13C)) +#define IMXDPUV1_SIG1_STATUS_RESET_VALUE 0x100000U +#define IMXDPUV1_SIG1_STATUS_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_SIG1_STATUS_STSSIGERROR_MASK 0xFFU +#define IMXDPUV1_SIG1_STATUS_STSSIGERROR_SHIFT 0U +#define IMXDPUV1_SIG1_STATUS_STSSIGVALID_MASK 0x10000U +#define IMXDPUV1_SIG1_STATUS_STSSIGVALID_SHIFT 16U +#define IMXDPUV1_SIG1_STATUS_STSSIGIDLE_MASK 0x100000U +#define IMXDPUV1_SIG1_STATUS_STSSIGIDLE_SHIFT 20U + +/* Register: IMXDPUV1_DPUXPC_Control */ +#define IMXDPUV1_DPUXPC_CONTROL ((uint32_t)(0xF000)) +#define IMXDPUV1_DPUXPC_CONTROL_OFFSET ((uint32_t)(0)) +#define IMXDPUV1_DPUXPC_CONTROL_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_CONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_CONTROL_ENABLE_MASK 0x1U +#define IMXDPUV1_DPUXPC_CONTROL_ENABLE_SHIFT 0U +#define IMXDPUV1_DPUXPC_CONTROL_MODE_MASK 0x6U +#define IMXDPUV1_DPUXPC_CONTROL_MODE_SHIFT 1U +/* Field Value: MODE__XPC_MODE_MANUAL, Manual measurement end */ +#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_MANUAL 0U +/* Field Value: MODE__XPC_MODE_TIMER, Timer controlled measurement end */ +#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_TIMER 0x1U +/* Field Value: MODE__XPC_MODE_CONTINUOUS, Continuous measurement; retriggered + * by reading SW_Tag register */ +#define IMXDPUV1_DPUXPC_CONTROL_MODE__XPC_MODE_CONTINUOUS 0x2U +#define IMXDPUV1_DPUXPC_CONTROL_INCREMENTMODE_MASK 0x40000000U +#define IMXDPUV1_DPUXPC_CONTROL_INCREMENTMODE_SHIFT 30U +#define IMXDPUV1_DPUXPC_CONTROL_OTCDISABLE_MASK 0x80000000U +#define IMXDPUV1_DPUXPC_CONTROL_OTCDISABLE_SHIFT 31U + +/* Register: IMXDPUV1_DPUXPC_Timer */ +#define IMXDPUV1_DPUXPC_TIMER ((uint32_t)(0xF004)) +#define IMXDPUV1_DPUXPC_TIMER_OFFSET ((uint32_t)(0x4)) +#define IMXDPUV1_DPUXPC_TIMER_RESET_VALUE 0xFFFFFFFU +#define IMXDPUV1_DPUXPC_TIMER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_TIMER_LOAD_MASK 0xFFFFFFFU +#define IMXDPUV1_DPUXPC_TIMER_LOAD_SHIFT 0U +#define IMXDPUV1_DPUXPC_TIMER_DIVIDER_MASK 0xF0000000U +#define IMXDPUV1_DPUXPC_TIMER_DIVIDER_SHIFT 28U + +/* Register: IMXDPUV1_DPUXPC_MeasurementTimeControl */ +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL ((uint32_t)(0xF008)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_OFFSET ((uint32_t)(0x8)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTDIVIDER_MASK 0xFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTDIVIDER_SHIFT 0U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTENABLE_MASK 0x80000000U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIMECONTROL_MTENABLE_SHIFT 31U + +/* Register: IMXDPUV1_DPUXPC_SW_Tag */ +#define IMXDPUV1_DPUXPC_SW_TAG ((uint32_t)(0xF00C)) +#define IMXDPUV1_DPUXPC_SW_TAG_OFFSET ((uint32_t)(0xC)) +#define IMXDPUV1_DPUXPC_SW_TAG_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_SW_TAG_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_SW_TAG_TAG_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_SW_TAG_TAG_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MeasurementTime */ +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME ((uint32_t)(0xF010)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_OFFSET ((uint32_t)(0x10)) +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_TIME_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MEASUREMENTTIME_TIME_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_Global_Counter */ +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER ((uint32_t)(0xF014)) +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_OFFSET ((uint32_t)(0x14)) +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_GLOBAL_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_GLOBAL_COUNTER_GLOBAL_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Switch */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH ((uint32_t)(0xF018)) +#define IMXDPUV1_DPUXPC_MU00_SWITCH_OFFSET ((uint32_t)(0x18)) +#define IMXDPUV1_DPUXPC_MU00_SWITCH_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT_SHIFT 0U +/* Field Value: MU00_SELECT__MU00_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC00 0U +/* Field Value: MU00_SELECT__MU00_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC01 0x1U +/* Field Value: MU00_SELECT__MU00_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC02 0x2U +/* Field Value: MU00_SELECT__MU00_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC03 0x3U +/* Field Value: MU00_SELECT__MU00_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC04 0x4U +/* Field Value: MU00_SELECT__MU00_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC05 0x5U +/* Field Value: MU00_SELECT__MU00_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC06 0x6U +/* Field Value: MU00_SELECT__MU00_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC07 0x7U +/* Field Value: MU00_SELECT__MU00_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC08 0x8U +/* Field Value: MU00_SELECT__MU00_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC09 0x9U +/* Field Value: MU00_SELECT__MU00_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC10 0xAU +/* Field Value: MU00_SELECT__MU00_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC11 0xBU +/* Field Value: MU00_SELECT__MU00_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC12 0xCU +/* Field Value: MU00_SELECT__MU00_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC13 0xDU +/* Field Value: MU00_SELECT__MU00_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC14 0xEU +/* Field Value: MU00_SELECT__MU00_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC15 0xFU +/* Field Value: MU00_SELECT__MU00_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC16 0x10U +/* Field Value: MU00_SELECT__MU00_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU00_SWITCH_MU00_SELECT__MU00_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU00_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER ((uint32_t)(0xF01C)) +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_OFFSET ((uint32_t)(0x1C)) +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_MU00_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_DATA_COUNTER_MU00_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER ((uint32_t)(0xF020)) +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_OFFSET ((uint32_t)(0x20)) +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_MU00_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_BUSY_COUNTER_MU00_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER ((uint32_t)(0xF024)) +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x24)) +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_MU00_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_TRANSFER_COUNTER_MU00_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER ((uint32_t)(0xF028)) +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x28)) +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_ADDRBUSY_COUNTER_MU00_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU00_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER ((uint32_t)(0xF02C)) +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_OFFSET ((uint32_t)(0x2C)) +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_MU00_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU00_LATENCY_COUNTER_MU00_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Switch */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH ((uint32_t)(0xF030)) +#define IMXDPUV1_DPUXPC_MU01_SWITCH_OFFSET ((uint32_t)(0x30)) +#define IMXDPUV1_DPUXPC_MU01_SWITCH_RESET_VALUE 0x1U +#define IMXDPUV1_DPUXPC_MU01_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT_SHIFT 0U +/* Field Value: MU01_SELECT__MU01_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC00 0U +/* Field Value: MU01_SELECT__MU01_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC01 0x1U +/* Field Value: MU01_SELECT__MU01_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC02 0x2U +/* Field Value: MU01_SELECT__MU01_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC03 0x3U +/* Field Value: MU01_SELECT__MU01_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC04 0x4U +/* Field Value: MU01_SELECT__MU01_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC05 0x5U +/* Field Value: MU01_SELECT__MU01_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC06 0x6U +/* Field Value: MU01_SELECT__MU01_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC07 0x7U +/* Field Value: MU01_SELECT__MU01_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC08 0x8U +/* Field Value: MU01_SELECT__MU01_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC09 0x9U +/* Field Value: MU01_SELECT__MU01_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC10 0xAU +/* Field Value: MU01_SELECT__MU01_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC11 0xBU +/* Field Value: MU01_SELECT__MU01_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC12 0xCU +/* Field Value: MU01_SELECT__MU01_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC13 0xDU +/* Field Value: MU01_SELECT__MU01_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC14 0xEU +/* Field Value: MU01_SELECT__MU01_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC15 0xFU +/* Field Value: MU01_SELECT__MU01_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC16 0x10U +/* Field Value: MU01_SELECT__MU01_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU01_SWITCH_MU01_SELECT__MU01_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU01_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER ((uint32_t)(0xF034)) +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_OFFSET ((uint32_t)(0x34)) +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_MU01_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_DATA_COUNTER_MU01_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER ((uint32_t)(0xF038)) +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_OFFSET ((uint32_t)(0x38)) +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_MU01_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_BUSY_COUNTER_MU01_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER ((uint32_t)(0xF03C)) +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x3C)) +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_MU01_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_TRANSFER_COUNTER_MU01_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER ((uint32_t)(0xF040)) +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x40)) +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_ADDRBUSY_COUNTER_MU01_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU01_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER ((uint32_t)(0xF044)) +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_OFFSET ((uint32_t)(0x44)) +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_MU01_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU01_LATENCY_COUNTER_MU01_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Switch */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH ((uint32_t)(0xF048)) +#define IMXDPUV1_DPUXPC_MU02_SWITCH_OFFSET ((uint32_t)(0x48)) +#define IMXDPUV1_DPUXPC_MU02_SWITCH_RESET_VALUE 0x2U +#define IMXDPUV1_DPUXPC_MU02_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT_SHIFT 0U +/* Field Value: MU02_SELECT__MU02_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC00 0U +/* Field Value: MU02_SELECT__MU02_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC01 0x1U +/* Field Value: MU02_SELECT__MU02_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC02 0x2U +/* Field Value: MU02_SELECT__MU02_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC03 0x3U +/* Field Value: MU02_SELECT__MU02_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC04 0x4U +/* Field Value: MU02_SELECT__MU02_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC05 0x5U +/* Field Value: MU02_SELECT__MU02_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC06 0x6U +/* Field Value: MU02_SELECT__MU02_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC07 0x7U +/* Field Value: MU02_SELECT__MU02_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC08 0x8U +/* Field Value: MU02_SELECT__MU02_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC09 0x9U +/* Field Value: MU02_SELECT__MU02_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC10 0xAU +/* Field Value: MU02_SELECT__MU02_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC11 0xBU +/* Field Value: MU02_SELECT__MU02_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC12 0xCU +/* Field Value: MU02_SELECT__MU02_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC13 0xDU +/* Field Value: MU02_SELECT__MU02_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC14 0xEU +/* Field Value: MU02_SELECT__MU02_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC15 0xFU +/* Field Value: MU02_SELECT__MU02_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC16 0x10U +/* Field Value: MU02_SELECT__MU02_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU02_SWITCH_MU02_SELECT__MU02_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU02_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER ((uint32_t)(0xF04C)) +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_OFFSET ((uint32_t)(0x4C)) +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_MU02_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_DATA_COUNTER_MU02_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER ((uint32_t)(0xF050)) +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_OFFSET ((uint32_t)(0x50)) +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_MU02_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_BUSY_COUNTER_MU02_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER ((uint32_t)(0xF054)) +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x54)) +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_MU02_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_TRANSFER_COUNTER_MU02_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER ((uint32_t)(0xF058)) +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x58)) +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_ADDRBUSY_COUNTER_MU02_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU02_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER ((uint32_t)(0xF05C)) +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_OFFSET ((uint32_t)(0x5C)) +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_MU02_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU02_LATENCY_COUNTER_MU02_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Switch */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH ((uint32_t)(0xF060)) +#define IMXDPUV1_DPUXPC_MU03_SWITCH_OFFSET ((uint32_t)(0x60)) +#define IMXDPUV1_DPUXPC_MU03_SWITCH_RESET_VALUE 0x3U +#define IMXDPUV1_DPUXPC_MU03_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT_SHIFT 0U +/* Field Value: MU03_SELECT__MU03_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC00 0U +/* Field Value: MU03_SELECT__MU03_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC01 0x1U +/* Field Value: MU03_SELECT__MU03_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC02 0x2U +/* Field Value: MU03_SELECT__MU03_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC03 0x3U +/* Field Value: MU03_SELECT__MU03_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC04 0x4U +/* Field Value: MU03_SELECT__MU03_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC05 0x5U +/* Field Value: MU03_SELECT__MU03_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC06 0x6U +/* Field Value: MU03_SELECT__MU03_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC07 0x7U +/* Field Value: MU03_SELECT__MU03_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC08 0x8U +/* Field Value: MU03_SELECT__MU03_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC09 0x9U +/* Field Value: MU03_SELECT__MU03_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC10 0xAU +/* Field Value: MU03_SELECT__MU03_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC11 0xBU +/* Field Value: MU03_SELECT__MU03_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC12 0xCU +/* Field Value: MU03_SELECT__MU03_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC13 0xDU +/* Field Value: MU03_SELECT__MU03_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC14 0xEU +/* Field Value: MU03_SELECT__MU03_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC15 0xFU +/* Field Value: MU03_SELECT__MU03_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC16 0x10U +/* Field Value: MU03_SELECT__MU03_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU03_SWITCH_MU03_SELECT__MU03_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU03_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER ((uint32_t)(0xF064)) +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_OFFSET ((uint32_t)(0x64)) +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_MU03_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_DATA_COUNTER_MU03_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER ((uint32_t)(0xF068)) +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_OFFSET ((uint32_t)(0x68)) +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_MU03_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_BUSY_COUNTER_MU03_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER ((uint32_t)(0xF06C)) +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x6C)) +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_MU03_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_TRANSFER_COUNTER_MU03_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER ((uint32_t)(0xF070)) +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x70)) +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_ADDRBUSY_COUNTER_MU03_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU03_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER ((uint32_t)(0xF074)) +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_OFFSET ((uint32_t)(0x74)) +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_MU03_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU03_LATENCY_COUNTER_MU03_LATENCY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Switch */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH ((uint32_t)(0xF078)) +#define IMXDPUV1_DPUXPC_MU04_SWITCH_OFFSET ((uint32_t)(0x78)) +#define IMXDPUV1_DPUXPC_MU04_SWITCH_RESET_VALUE 0x4U +#define IMXDPUV1_DPUXPC_MU04_SWITCH_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT_MASK 0x1FU +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT_SHIFT 0U +/* Field Value: MU04_SELECT__MU04_OTC00, cmdseq read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC00 0U +/* Field Value: MU04_SELECT__MU04_OTC01, cmdseq write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC01 0x1U +/* Field Value: MU04_SELECT__MU04_OTC02, fetchdecode9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC02 0x2U +/* Field Value: MU04_SELECT__MU04_OTC03, fetchpersp9 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC03 0x3U +/* Field Value: MU04_SELECT__MU04_OTC04, fetcheco9 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC04 0x4U +/* Field Value: MU04_SELECT__MU04_OTC05, fetchdecode2 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC05 0x5U +/* Field Value: MU04_SELECT__MU04_OTC06, fetchdecode3 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC06 0x6U +/* Field Value: MU04_SELECT__MU04_OTC07, fetchwarp2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC07 0x7U +/* Field Value: MU04_SELECT__MU04_OTC08, fetcheco2 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC08 0x8U +/* Field Value: MU04_SELECT__MU04_OTC09, fetchdecode0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC09 0x9U +/* Field Value: MU04_SELECT__MU04_OTC10, fetcheco0 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC10 0xAU +/* Field Value: MU04_SELECT__MU04_OTC11, fetchdecode1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC11 0xBU +/* Field Value: MU04_SELECT__MU04_OTC12, fetcheco1 read direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC12 0xCU +/* Field Value: MU04_SELECT__MU04_OTC13, fetchlayer0 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC13 0xDU +/* Field Value: MU04_SELECT__MU04_OTC14, fetchlayer1 read direction (ACLK + * clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC14 0xEU +/* Field Value: MU04_SELECT__MU04_OTC15, store9 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC15 0xFU +/* Field Value: MU04_SELECT__MU04_OTC16, store4 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC16 0x10U +/* Field Value: MU04_SELECT__MU04_OTC17, store5 write direction (ACLK clock) */ +#define IMXDPUV1_DPUXPC_MU04_SWITCH_MU04_SELECT__MU04_OTC17 0x11U + +/* Register: IMXDPUV1_DPUXPC_MU04_Data_Counter */ +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER ((uint32_t)(0xF07C)) +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_OFFSET ((uint32_t)(0x7C)) +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_MU04_DATA_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_DATA_COUNTER_MU04_DATA_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Busy_Counter */ +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER ((uint32_t)(0xF080)) +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_OFFSET ((uint32_t)(0x80)) +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_MU04_BUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_BUSY_COUNTER_MU04_BUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Transfer_Counter */ +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER ((uint32_t)(0xF084)) +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_OFFSET ((uint32_t)(0x84)) +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_MU04_TRANSFER_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_TRANSFER_COUNTER_MU04_TRANSFER_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Addrbusy_Counter */ +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER ((uint32_t)(0xF088)) +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_OFFSET ((uint32_t)(0x88)) +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_ADDRBUSY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_ADDRBUSY_COUNTER_MU04_ADDRBUSY_SHIFT 0U + +/* Register: IMXDPUV1_DPUXPC_MU04_Latency_Counter */ +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER ((uint32_t)(0xF08C)) +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_OFFSET ((uint32_t)(0x8C)) +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_RESET_VALUE 0U +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_RESET_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_MU04_LATENCY_MASK 0xFFFFFFFFU +#define IMXDPUV1_DPUXPC_MU04_LATENCY_COUNTER_MU04_LATENCY_SHIFT 0U + +#endif /* IMXDPUV1_REGISTERS_H */ diff --git a/include/in112525.h b/include/in112525.h new file mode 100644 index 00000000000..146a94f7c26 --- /dev/null +++ b/include/in112525.h @@ -0,0 +1,236 @@ +/* + * Copyright 2018-2021 NXP + * Copyright 2018 INPHI + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Inphi is a registered trademark of Inphi Corporation + * + */ + +#ifndef _IN112525_H_ +#define _IN112525_H_ + +#define PHYCTRL_REG0 0x0000 +#define PHYCTRL_REG1 0x0012 +#define PHYCTRL_REG2 0x0014 +#define PHYCTRL_REG4 0x0121 +#define PHYCTRL_REG5 0x0180 +#define PHYCTRL_REG6 0x0580 +#define PHYCTRL_REG7 0x05C4 +#define PHYCTRL_REG8 0x01C8 +#define PHYCTRL_REG10 0x0520 +#define PHYCTRL_REG11 0x0521 +#define PHYCTRL_REG12 0x0522 +#define PHYCTRL_REG13 0x05c8 +#define PHYCTRL_REG14 0x059b +#define PHYCTRL_REG15 0x0520 +#define PHYCTRL_REG16 0x0521 +#define PHYCTRL_REG17 0x0522 +#define PHYCTRL_REG18 0x0525 +#define PHYCTRL_REG19 0x0524 +#define PHYCTRL_REG20 0x05ad + +#define PHYSTAT_REG1 0x0021 +#define PHYSTAT_REG2 0x0022 +#define PHYSTAT_REG3 0x0123 + +#define PHYMISC_REG1 0x0025 +#define PHYMISC_REG2 0x002c +#define PHYMISC_REG3 0x00b3 +#define PHYMISC_REG4 0x0181 +#define PHYMISC_REG5 0x019d +#define PHYMISC_REG6 0x0198 +#define PHYMISC_REG7 0x0199 +#define PHYMISC_REG8 0x0581 +#define PHYMISC_REG9 0x0598 +#define PHYMISC_REG11 0x00f0 +#define PHYMISC_REG12 0x00f4 +#define PHYMISC_REG20 0x01B0 +#define PHYMISC_REG21 0x01BC +#define PHYMISC_REG22 0x01C0 +#define PHYMISC_REG30 0x0584 +#define PHYMISC_REG31 0x0585 +#define PHYMISC_REG32 0x0184 + +#define IN112525_HRESET 0x20 +#define IN112525_SRESET 0x200 +#define IN112525_MDIOINIT 0x1000 +#define IN112525_MANUALRESET_SELECT 0x8000 +#define IN112525_LANE0_DISABLE BIT(0) +#define IN112525_LANE1_DISABLE BIT(1) +#define IN112525_CALIBRATION_DONE 0x10 +#define IN112525_PLL_POWERDOWN 0x8 +#define IN112525_CORE_DATAPATH_RESET 0x0400 +#define IN112525_TX_SERDES_RESET 0x0800 +#define IN112525_TX_PLL_RESET 0x1000 +#define IN112525_RX_PLL_RESET 0x8000 + +#if defined(CONFIG_IN112525_S05_10G) || defined(CONFIG_IN112525_S05_40G) +#define IN112525_EXT_REFCLK_EN 0x8000 +#define IN112525_CTLE_10G 0x8 +#else +#define IN112525_EXT_REFCLK_EN 0x0000 +#define IN112525_CTLE_10G 0x0 +#endif + +#define IN112525_FORCE_PC 0x1000 +#define IN112525_LOL_CTRL 0x2000 +#define IN112525_USEQ_EN 0x8000 +#define IN112525_USEQ_FL 0x4 +#define IN112525_USEQ_LOS 0x2 +#define IN112525_USEQ_LOL 0x1 + +#define PHYCTRL_REG15_VAL 0x2032 +#define PHYCTRL_REG17_VAL 0x0007 +#define PHYCTRL_REG15_VAL_EXT 0xA02D +#define PHYCTRL_REG17_VAL_EXT 0x0005 + +#if defined(CONFIG_IN112525_S05_10G) || defined(CONFIG_IN112525_S05_40G) +#define IN112525_TXPLL_MSDIV 0x10 +#define IN112525_TXPLL_IQDIV 0x100 +#else +#define IN112525_TXPLL_MSDIV 0x0 +#define IN112525_TXPLL_IQDIV 0x0 +#endif + +#define IN112525_FA_WIN_SIZE 0x2 +#define IN112525_RX_MISC_TRIM1_VAL 0xB + +#define IN112525_RX_HALFRATE_EN 0x20 + +#define IN112525_RX_LOS_EN 0x8000 +#define IN112525_RX_LOS_10G_THRESHOLD 0x1 +#define IN112525_RX_LOS_100G_THRESHOLD 0x2 + +#if defined(CONFIG_IN112525_S05_10G) || defined(CONFIG_IN112525_S05_40G) +#define PHYCTRL_REG13_VAL 0x8 +#define IN112525_LOSD_HYSTERESIS_EN 0x11 +#else +#define PHYCTRL_REG13_VAL 0x0 +#define IN112525_LOSD_HYSTERESIS_EN 0x01 +#endif + +#define IN112525_EFUSE_REG 0x600 +#define IN112525_EFUSE_DONE 0x2000 +#define IN112525_AUTOZERO_COMPLETION_DONE 0x4 +#define IN112525_RX_PLL_LOCK_ACQUIRED 0x20 +#define IN112525_TX_PLL_LOCK_ACQUIRED 0x40 + +#define IN112525_PRESCALE_20M 0xB5 + +#define IN112525_RX_VCO_CODE_OFFSET 5 +#define IN112525_RX_PHASE_ADJUST_TRACK_VAL 36 + +#define L0_VCO_CODE_trim 390 +#define L1_VCO_CODE_trim 390 +#define L2_VCO_CODE_trim 390 +#define L3_VCO_CODE_trim 390 + +/* Micro-Sequencer Data Memory 0x700 - 0x73F */ +#define IN112525_US_DATA_MEM_ADDR 0x73E +#define IN112525_PHASE_ADJUST_VAL 0x3 + +struct in112525_reg_config { + unsigned short reg_addr; + unsigned short reg_value; +}; + +/* define mapping for CTLE codes to rx_ctl registers 0x1c8,...,0x4c8 */ +enum in112525_eq_mode { + MODE_25_10_10 = 0x0, + MODE_25_10_25 = 0x1, + MODE_25_25_10 = 0x2, + MODE_25_25_25 = 0x3, + MODE_10_10_10 = 0x80, + MODE_10_10_25 = 0x81, + MODE_10_25_10 = 0x82, + MODE_10_25_25 = 0x83 +}; + +enum in112525_s03_mode { + INIT_OC192, + INIT_10GE, + INIT_16GFC, + INIT_20GE, + INIT_100GE, + INIT_25GE, + INIT_OTU4, + INIT_32GFC, + INIT_F28P2G +}; + +enum in112525_refclock { + RECOV_CLK, /* Normal Mission Mode */ + EXTERNAL, /* BERT Mode */ + RXMUX_CLK, + LPBK, + SEC_REFCLK = 5 +}; + +struct in112525_s03_vco_codes { + int l0_vco_code; + int l1_vco_code; + int l2_vco_code; + int l3_vco_code; +}; + +struct in112525_config { + /* OTU protocol check */ + unsigned char enable_otu_protocol:1; + /* external refclk buffer */ + unsigned char enable_external_refclk:1; + /* clk prescaler */ + unsigned char enable_prescaler:1; + /* set half-rate mode */ + unsigned char enable_half_rate:1; + /* FA sweep range for lower rates */ + unsigned char enable_extended_range:1; + /* PLL multiplier ratio settings */ + unsigned short tx_pll_mpy_ratio; + /* src for TX PLL (external or recovered clk */ + enum in112525_refclock tx_pll_refclk_source; + /* equalizer preset mode (25:25:25, 25:25:10, 10:10:10 */ + enum in112525_eq_mode ctle_mode; + /* common mode settings */ + unsigned char rx_common_mode; + /* rx termination adjustments for non-matched tx */ + unsigned char rx_odt_override; + /* default phase adjustments per lanes */ + unsigned char l0_phase_adjust_val; + unsigned char l1_phase_adjust_val; + unsigned char l2_phase_adjust_val; + unsigned char l3_phase_adjust_val; +}; + +int bit_test(int value, int bit_field); +void WAIT(int delay_cycles); +void tx_restart(int lane); +void disable_lane(int lane); +void rx_powerdown_assert(int lane); +void rx_powerdown_de_assert(int lane); +void rx_reset_assert(int lane); +void rx_reset_de_assert(int lane); +void toggle_reset(int lane); +int in112525_s03_phy_init(struct phy_device *phydev); +int in112525_s03_lane_recovery(int lane); +#endif diff --git a/include/init.h b/include/init.h index fd51d7f9667..7a32b57b17d 100644 --- a/include/init.h +++ b/include/init.h @@ -278,6 +278,10 @@ int init_func_vid(void); int checkboard(void); int show_board_info(void); +#ifdef CONFIG_ANDROID_BOOT_IMAGE +void get_reboot_reason(char *ret); +#endif + /** * Get the uppermost pointer that is valid to access * diff --git a/include/interface/avb/avb.h b/include/interface/avb/avb.h new file mode 100644 index 00000000000..f9da80c21d7 --- /dev/null +++ b/include/interface/avb/avb.h @@ -0,0 +1,102 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_INTERFACE_AVB_H_ +#define TRUSTY_INTERFACE_AVB_H_ + +#include + +#define AVB_PORT "com.android.trusty.avb" +#define AVB_MAX_BUFFER_LENGTH 2048 + +enum avb_command { + AVB_REQ_SHIFT = 1, + AVB_RESP_BIT = 1, + + READ_ROLLBACK_INDEX = (0 << AVB_REQ_SHIFT), + WRITE_ROLLBACK_INDEX = (1 << AVB_REQ_SHIFT), + AVB_GET_VERSION = (2 << AVB_REQ_SHIFT), + READ_PERMANENT_ATTRIBUTES = (3 << AVB_REQ_SHIFT), + WRITE_PERMANENT_ATTRIBUTES = (4 << AVB_REQ_SHIFT), + READ_LOCK_STATE = (5 << AVB_REQ_SHIFT), + WRITE_LOCK_STATE = (6 << AVB_REQ_SHIFT), + LOCK_BOOT_STATE = (7 << AVB_REQ_SHIFT), + READ_VBMETA_PUBLIC_KEY = (8 << AVB_REQ_SHIFT), + WRITE_VBMETA_PUBLIC_KEY = (9 << AVB_REQ_SHIFT), + WRITE_OEM_UNLOCK_DEVICE_PERMISSION = (10 << AVB_REQ_SHIFT), + READ_OEM_UNLOCK_DEVICE_PERMISSION = (11 << AVB_REQ_SHIFT), +}; + +/** + * enum avb_error - error codes for AVB protocol + * @AVB_ERROR_NONE: All OK + * @AVB_ERROR_INVALID: Invalid input + * @AVB_ERROR_INTERNAL: Error occurred during an operation in Trusty + */ +enum avb_error { + AVB_ERROR_NONE = 0, + AVB_ERROR_INVALID = 1, + AVB_ERROR_INTERNAL = 2, +}; + +/** + * avb_message - Serial header for communicating with AVB server + * @cmd: the command. Payload must be a serialized buffer of the + * corresponding request object. + * @result: resulting error code for message, one of avb_error. + * @payload: start of the serialized command specific payload + */ +struct avb_message { + uint32_t cmd; + uint32_t result; + uint8_t payload[0]; +}; + +/** + * avb_rollback_req - request format for [READ|WRITE]_ROLLBACK_INDEX + * @value: value to write to rollback index. Ignored for read. + * @slot: slot number of rollback index to write + */ +struct avb_rollback_req { + uint64_t value; + uint32_t slot; +} TRUSTY_ATTR_PACKED; + +/** + * avb_rollback_resp - response format for [READ|WRITE]_ROLLBACK_INDEX. + * @value: value of the requested rollback index. + */ +struct avb_rollback_resp { + uint64_t value; +}; + +/** + * avb_get_version_resp - response format for AVB_GET_VERSION. + * @version: version of AVB message format + */ +struct avb_get_version_resp { + uint32_t version; +}; + +#endif /* TRUSTY_INTERFACE_AVB_H_ */ diff --git a/include/interface/hwcrypto/hwcrypto.h b/include/interface/hwcrypto/hwcrypto.h new file mode 100644 index 00000000000..0bfb2136895 --- /dev/null +++ b/include/interface/hwcrypto/hwcrypto.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * Copyright NXP 2018 + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ + +#ifndef TRUSTY_INTERFACE_HWCRYPTO_H_ +#define TRUSTY_INTERFACE_HWCRYPTO_H_ + +#include + +#define HWCRYPTO_PORT "com.android.trusty.hwcrypto" +#define HWCRYPTO_MAX_BUFFER_LENGTH 2048 + +enum hwcrypto_command { + HWCRYPTO_REQ_SHIFT = 1, + HWCRYPTO_RESP_BIT = 1, + + HWCRYPTO_HASH = (1 << HWCRYPTO_REQ_SHIFT), + HWCRYPTO_ENCAP_BLOB = (2 << HWCRYPTO_REQ_SHIFT), + HWCRYPTO_GEN_RNG = (3 << HWCRYPTO_REQ_SHIFT), + HWCRYPTO_GEN_BKEK = (4 << HWCRYPTO_REQ_SHIFT), + HWCRYPTO_LOCK_BOOT_STATE = (5 << HWCRYPTO_REQ_SHIFT), + HWCRYPTO_PROVISION_WV_KEY = (6 << HWCRYPTO_REQ_SHIFT), + HWCRYPTO_PROVISION_WV_KEY_ENC = (7 << HWCRYPTO_REQ_SHIFT), +}; + +/** + * enum hwcrypto_error - error codes for HWCRYPTO protocol + * @HWCRYPTO_ERROR_NONE: All OK + * @HWCRYPTO_ERROR_INVALID: Invalid input + * @HWCRYPTO_ERROR_INTERNAL: Error occurred during an operation in Trusty + */ +enum hwcrypto_error { + HWCRYPTO_ERROR_NONE = 0, + HWCRYPTO_ERROR_INVALID = 1, + HWCRYPTO_ERROR_INTERNAL = 2, +}; + +enum hwcrypto_hash_algo { + SHA1 = 0, + SHA256 +}; +/** + * hwcrypto_message - Serial header for communicating with hwcrypto server + * @cmd: the command. Payload must be a serialized buffer of the + * corresponding request object. + * @result: resulting error code for message, one of hwcrypto_error. + * @payload: start of the serialized command specific payload + */ +struct hwcrypto_message { + uint32_t cmd; + uint32_t result; + uint8_t payload[0]; +}; + +/** + * hwcrypto_hash_msg - Serial header for communicating with hwcrypto server + * @in_addr: start address of the input buf. + * @in_len: size of the input buf. + * @out_addr: start addrss of the output buf. + * @out_len: size of the output buf. + * @algo: hash algorithm expect to use. + */ +typedef struct hwcrypto_hash_msg { + uint32_t in_addr; + uint32_t in_len; + uint32_t out_addr; + uint32_t out_len; + enum hwcrypto_hash_algo algo; +} hwcrypto_hash_msg; + +/** + * @plain_pa: physical start address of the plain blob buf. + * @plain_size: size of the plain blob. + * @blob: physical start addrss of the output buf. + */ +typedef struct hwcrypto_blob_msg { + uint32_t plain_pa; + uint32_t plain_size; + uint32_t blob_pa; +}hwcrypto_blob_msg; + +/** + * @buf: physical start address of the output rng buf. + * @len: size of required rng. + */ +typedef struct hwcrypto_rng_msg { + uint32_t buf; + uint32_t len; +}hwcrypto_rng_msg; + +/** + * @buf: physical start address of the output bkek buf. + * @len: size of required rng. + */ +typedef struct hwcrypto_bkek_msg { + uint32_t buf; + uint32_t len; +}hwcrypto_bkek_msg; +#endif /* TRUSTY_INTERFACE_HWCRYPTO_H_ */ diff --git a/include/interface/keymaster/keymaster.h b/include/interface/keymaster/keymaster.h new file mode 100644 index 00000000000..b094d40a417 --- /dev/null +++ b/include/interface/keymaster/keymaster.h @@ -0,0 +1,306 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_INTERFACE_KEYMASTER_H_ +#define TRUSTY_INTERFACE_KEYMASTER_H_ + +#include + +#define KEYMASTER_PORT "com.android.trusty.keymaster" +#define KEYMASTER_MAX_BUFFER_LENGTH 4096 + +enum keymaster_command { + KEYMASTER_RESP_BIT = 1, + KEYMASTER_STOP_BIT = 2, + KEYMASTER_REQ_SHIFT = 2, + + KM_GENERATE_KEY = (0 << KEYMASTER_REQ_SHIFT), + KM_BEGIN_OPERATION = (1 << KEYMASTER_REQ_SHIFT), + KM_UPDATE_OPERATION = (2 << KEYMASTER_REQ_SHIFT), + KM_FINISH_OPERATION = (3 << KEYMASTER_REQ_SHIFT), + KM_ABORT_OPERATION = (4 << KEYMASTER_REQ_SHIFT), + KM_IMPORT_KEY = (5 << KEYMASTER_REQ_SHIFT), + + KM_EXPORT_KEY = (6 << KEYMASTER_REQ_SHIFT), + KM_GET_VERSION = (7 << KEYMASTER_REQ_SHIFT), + KM_ADD_RNG_ENTROPY = (8 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_ALGORITHMS = (9 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_BLOCK_MODES = (10 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_PADDING_MODES = (11 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_DIGESTS = (12 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_IMPORT_FORMATS = (13 << KEYMASTER_REQ_SHIFT), + KM_GET_SUPPORTED_EXPORT_FORMATS = (14 << KEYMASTER_REQ_SHIFT), + KM_GET_KEY_CHARACTERISTICS = (15 << KEYMASTER_REQ_SHIFT), + + // Bootloader calls. + KM_SET_BOOT_PARAMS = (0x1000 << KEYMASTER_REQ_SHIFT), + KM_SET_ATTESTATION_KEY = (0x2000 << KEYMASTER_REQ_SHIFT), + KM_APPEND_ATTESTATION_CERT_CHAIN = (0x3000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_GET_CA_REQUEST = (0x4000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_SET_CA_RESPONSE_BEGIN = (0x5000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_SET_CA_RESPONSE_UPDATE = (0x6000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_SET_CA_RESPONSE_FINISH = (0x7000 << KEYMASTER_REQ_SHIFT), + KM_ATAP_READ_UUID = (0x8000 << KEYMASTER_REQ_SHIFT), + KM_SET_PRODUCT_ID = (0x9000 << KEYMASTER_REQ_SHIFT), + KM_GET_MPPUBK = (0xb000 << KEYMASTER_REQ_SHIFT), + KM_APPEND_ATTESTATION_CERT_CHAIN_ENC = (0xc000 << KEYMASTER_REQ_SHIFT), + KM_SET_ATTESTATION_KEY_ENC = (0xd000 << KEYMASTER_REQ_SHIFT), + KM_VERIFY_SECURE_UNLOCK = (0xe000 << KEYMASTER_REQ_SHIFT), + KM_APPEND_ATTESTATION_ID = (0xf000 << KEYMASTER_REQ_SHIFT) +}; + +typedef enum { + KM_VERIFIED_BOOT_VERIFIED = 0, /* Full chain of trust extending from the bootloader to + * verified partitions, including the bootloader, boot + * partition, and all verified partitions*/ + KM_VERIFIED_BOOT_SELF_SIGNED = 1, /* The boot partition has been verified using the embedded + * certificate, and the signature is valid. The bootloader + * displays a warning and the fingerprint of the public + * key before allowing the boot process to continue.*/ + KM_VERIFIED_BOOT_UNVERIFIED = 2, /* The device may be freely modified. Device integrity is left + * to the user to verify out-of-band. The bootloader + * displays a warning to the user before allowing the boot + * process to continue */ + KM_VERIFIED_BOOT_FAILED = 3, /* The device failed verification. The bootloader displays a + * warning and stops the boot process, so no keymaster + * implementation should ever actually return this value, + * since it should not run. Included here only for + * completeness. */ +} keymaster_verified_boot_t; + +/** + * Algorithms that may be provided by keymaster implementations. + */ +typedef enum { + /* Asymmetric algorithms. */ + KM_ALGORITHM_RSA = 1, + // KM_ALGORITHM_DSA = 2, -- Removed, do not re-use value 2. + KM_ALGORITHM_EC = 3, + + /* Block ciphers algorithms */ + KM_ALGORITHM_AES = 32, + + /* MAC algorithms */ + KM_ALGORITHM_HMAC = 128, +} keymaster_algorithm_t; + +typedef enum { + KM_ERROR_OK = 0, + KM_ERROR_ROOT_OF_TRUST_ALREADY_SET = -1, + KM_ERROR_UNSUPPORTED_PURPOSE = -2, + KM_ERROR_INCOMPATIBLE_PURPOSE = -3, + KM_ERROR_UNSUPPORTED_ALGORITHM = -4, + KM_ERROR_INCOMPATIBLE_ALGORITHM = -5, + KM_ERROR_UNSUPPORTED_KEY_SIZE = -6, + KM_ERROR_UNSUPPORTED_BLOCK_MODE = -7, + KM_ERROR_INCOMPATIBLE_BLOCK_MODE = -8, + KM_ERROR_UNSUPPORTED_MAC_LENGTH = -9, + KM_ERROR_UNSUPPORTED_PADDING_MODE = -10, + KM_ERROR_INCOMPATIBLE_PADDING_MODE = -11, + KM_ERROR_UNSUPPORTED_DIGEST = -12, + KM_ERROR_INCOMPATIBLE_DIGEST = -13, + KM_ERROR_INVALID_EXPIRATION_TIME = -14, + KM_ERROR_INVALID_USER_ID = -15, + KM_ERROR_INVALID_AUTHORIZATION_TIMEOUT = -16, + KM_ERROR_UNSUPPORTED_KEY_FORMAT = -17, + KM_ERROR_INCOMPATIBLE_KEY_FORMAT = -18, + KM_ERROR_UNSUPPORTED_KEY_ENCRYPTION_ALGORITHM = -19, /* For PKCS8 & PKCS12 */ + KM_ERROR_UNSUPPORTED_KEY_VERIFICATION_ALGORITHM = -20, /* For PKCS8 & PKCS12 */ + KM_ERROR_INVALID_INPUT_LENGTH = -21, + KM_ERROR_KEY_EXPORT_OPTIONS_INVALID = -22, + KM_ERROR_DELEGATION_NOT_ALLOWED = -23, + KM_ERROR_KEY_NOT_YET_VALID = -24, + KM_ERROR_KEY_EXPIRED = -25, + KM_ERROR_KEY_USER_NOT_AUTHENTICATED = -26, + KM_ERROR_OUTPUT_PARAMETER_NULL = -27, + KM_ERROR_INVALID_OPERATION_HANDLE = -28, + KM_ERROR_INSUFFICIENT_BUFFER_SPACE = -29, + KM_ERROR_VERIFICATION_FAILED = -30, + KM_ERROR_TOO_MANY_OPERATIONS = -31, + KM_ERROR_UNEXPECTED_NULL_POINTER = -32, + KM_ERROR_INVALID_KEY_BLOB = -33, + KM_ERROR_IMPORTED_KEY_NOT_ENCRYPTED = -34, + KM_ERROR_IMPORTED_KEY_DECRYPTION_FAILED = -35, + KM_ERROR_IMPORTED_KEY_NOT_SIGNED = -36, + KM_ERROR_IMPORTED_KEY_VERIFICATION_FAILED = -37, + KM_ERROR_INVALID_ARGUMENT = -38, + KM_ERROR_UNSUPPORTED_TAG = -39, + KM_ERROR_INVALID_TAG = -40, + KM_ERROR_MEMORY_ALLOCATION_FAILED = -41, + KM_ERROR_IMPORT_PARAMETER_MISMATCH = -44, + KM_ERROR_SECURE_HW_ACCESS_DENIED = -45, + KM_ERROR_OPERATION_CANCELLED = -46, + KM_ERROR_CONCURRENT_ACCESS_CONFLICT = -47, + KM_ERROR_SECURE_HW_BUSY = -48, + KM_ERROR_SECURE_HW_COMMUNICATION_FAILED = -49, + KM_ERROR_UNSUPPORTED_EC_FIELD = -50, + KM_ERROR_MISSING_NONCE = -51, + KM_ERROR_INVALID_NONCE = -52, + KM_ERROR_MISSING_MAC_LENGTH = -53, + KM_ERROR_KEY_RATE_LIMIT_EXCEEDED = -54, + KM_ERROR_CALLER_NONCE_PROHIBITED = -55, + KM_ERROR_KEY_MAX_OPS_EXCEEDED = -56, + KM_ERROR_INVALID_MAC_LENGTH = -57, + KM_ERROR_MISSING_MIN_MAC_LENGTH = -58, + KM_ERROR_UNSUPPORTED_MIN_MAC_LENGTH = -59, + KM_ERROR_UNSUPPORTED_KDF = -60, + KM_ERROR_UNSUPPORTED_EC_CURVE = -61, + KM_ERROR_KEY_REQUIRES_UPGRADE = -62, + KM_ERROR_ATTESTATION_CHALLENGE_MISSING = -63, + KM_ERROR_KEYMASTER_NOT_CONFIGURED = -64, + + KM_ERROR_UNIMPLEMENTED = -100, + KM_ERROR_VERSION_MISMATCH = -101, + + KM_ERROR_UNKNOWN_ERROR = -1000, +} keymaster_error_t; + +/** + * keymaster_message - Serial header for communicating with KM server + * + * @cmd: the command, one of keymaster_command. + * @payload: start of the serialized command specific payload + */ +struct keymaster_message { + uint32_t cmd; + uint8_t payload[0]; +}; + +/** + * km_no_response - Generic keymaster response for commands with no special + * response data + * + * @error: error code from command + */ +struct km_no_response { + int32_t error; +}; + +/** + * km_get_version_resp - response format for KM_GET_VERSION. + */ +struct km_get_version_resp { + int32_t error; + uint8_t major_ver; + uint8_t minor_ver; + uint8_t subminor_ver; +} TRUSTY_ATTR_PACKED; + +/** + * km_raw_buffer_resp - response format for a raw buffer + */ +struct km_raw_buffer_resp { + int32_t error; + uint32_t data_size; + int8_t data[0]; +} TRUSTY_ATTR_PACKED; + +/** + * km_get_mppubk_resp - response format for mppubk buffer + */ +struct km_get_mppubk_resp { + int32_t error; + uint32_t data_size; + uint8_t data[64]; +} TRUSTY_ATTR_PACKED; + +/** + * km_secure_unlock_data - represents the secure unlock data + * + * @serial_size: size of |serial_data| + * @serial_data: serial_data (serial number) + * @credential_size: size of |credential_data| + * @credential_data: credential data + */ +struct km_secure_unlock_data { + uint32_t serial_size; + const uint8_t *serial_data; + uint32_t credential_size; + const uint8_t *credential_data; +} TRUSTY_ATTR_PACKED; +/** + * km_set_ca_response_begin_req - starts the process to set the ATAP CA Response + * + * @ca_response_size: total size of the CA Response message + */ +struct km_set_ca_response_begin_req { + uint32_t ca_response_size; +} TRUSTY_ATTR_PACKED; + +/** + * km_boot_params - Parameters sent from the bootloader to the Keymaster TA + * + * Since verified_boot_key_hash and verified_boot_hash have variable sizes, this + * structure must be serialized before sending to the secure side + * using km_boot_params_serialize(). + * + * @os_version: OS version from Android image header + * @os_patchlevel: OS patch level from Android image header + * @device_locked: nonzero if device is locked + * @verified_boot_state: one of keymaster_verified_boot_t + * @verified_boot_key_hash_size: size of verified_boot_key_hash + * @verified_boot_key_hash: hash of key used to verify Android image + * @verified_boot_hash_size: size of verified_boot_hash + * @verified_boot_hash: cumulative hash of all images verified thus far + */ +struct km_boot_params { + uint32_t os_version; + uint32_t os_patchlevel; + uint32_t device_locked; + uint32_t verified_boot_state; + uint32_t verified_boot_key_hash_size; + const uint8_t *verified_boot_key_hash; + uint32_t verified_boot_hash_size; + const uint8_t *verified_boot_hash; +} TRUSTY_ATTR_PACKED; + +/** + * km_attestation_data - represents a DER encoded key or certificate + * + * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC + * @data_size: size of |data| + * @data: DER encoded key or certificate (depending on operation) + */ +struct km_attestation_data { + uint32_t algorithm; + uint32_t data_size; + const uint8_t *data; +} TRUSTY_ATTR_PACKED; + +struct km_attestation_id_data { + uint32_t data_size; + const uint8_t *data; +} TRUSTY_ATTR_PACKED; +/** + * km_raw_buffer - represents a single raw buffer + * + * @data_size: size of |data| + * @data: pointer to the buffer + */ +struct km_raw_buffer { + uint32_t data_size; + const uint8_t *data; +} TRUSTY_ATTR_PACKED; + +#endif /* TRUSTY_INTERFACE_KEYMASTER_H_ */ diff --git a/include/interface/storage/storage.h b/include/interface/storage/storage.h new file mode 100644 index 00000000000..4d524984e6c --- /dev/null +++ b/include/interface/storage/storage.h @@ -0,0 +1,168 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_INTERFACE_STORAGE_H_ +#define TRUSTY_INTERFACE_STORAGE_H_ + +/* + * The contents of this file are copied from + * trusty/lib/interface/storage/include/interface/storage/storage.h. + * It is required to stay in sync for struct formats and enum values. + */ + +#include + +/* + * @STORAGE_DISK_PROXY_PORT: Port used by non-secure proxy server + */ +#define STORAGE_DISK_PROXY_PORT "com.android.trusty.storage.proxy" + +enum storage_cmd { + STORAGE_REQ_SHIFT = 1, + STORAGE_RESP_BIT = 1, + + STORAGE_RESP_MSG_ERR = STORAGE_RESP_BIT, + + STORAGE_FILE_DELETE = 1 << STORAGE_REQ_SHIFT, + STORAGE_FILE_OPEN = 2 << STORAGE_REQ_SHIFT, + STORAGE_FILE_CLOSE = 3 << STORAGE_REQ_SHIFT, + STORAGE_FILE_READ = 4 << STORAGE_REQ_SHIFT, + STORAGE_FILE_WRITE = 5 << STORAGE_REQ_SHIFT, + STORAGE_FILE_GET_SIZE = 6 << STORAGE_REQ_SHIFT, + STORAGE_FILE_SET_SIZE = 7 << STORAGE_REQ_SHIFT, + + STORAGE_RPMB_SEND = 8 << STORAGE_REQ_SHIFT, + + /* transaction support */ + STORAGE_END_TRANSACTION = 9 << STORAGE_REQ_SHIFT, + + STORAGE_RPMB_KEY_SET = 12 << STORAGE_REQ_SHIFT, + STORAGE_RPMB_ERASE_ALL = 13 << STORAGE_REQ_SHIFT, +}; + +/** + * enum storage_err - error codes for storage protocol + * @STORAGE_NO_ERROR: all OK + * @STORAGE_ERR_GENERIC: unknown error. Can occur when there's an internal server + * error, e.g. the server runs out of memory or is in a bad state. + * @STORAGE_ERR_NOT_VALID: input not valid. May occur if the arguments passed + * into the command are not valid, for example if the file handle + * passed in is not a valid one. + * @STORAGE_ERR_UNIMPLEMENTED: the command passed in is not recognized + * @STORAGE_ERR_ACCESS: the file is not accessible in the requested mode + * @STORAGE_ERR_NOT_FOUND: the file was not found + * @STORAGE_ERR_EXIST the file exists when it shouldn't as in with OPEN_CREATE | OPEN_EXCLUSIVE. + * @STORAGE_ERR_TRANSACT returned by various operations to indicate that current transaction + * is in error state. Such state could be only cleared by sending + * STORAGE_END_TRANSACTION message. + */ +enum storage_err { + STORAGE_NO_ERROR = 0, + STORAGE_ERR_GENERIC = 1, + STORAGE_ERR_NOT_VALID = 2, + STORAGE_ERR_UNIMPLEMENTED = 3, + STORAGE_ERR_ACCESS = 4, + STORAGE_ERR_NOT_FOUND = 5, + STORAGE_ERR_EXIST = 6, + STORAGE_ERR_TRANSACT = 7, +}; + +/** + * enum storage_msg_flag - protocol-level flags in struct storage_msg + * @STORAGE_MSG_FLAG_BATCH: if set, command belongs to a batch transaction. + * No response will be sent by the server until + * it receives a command with this flag unset, at + * which point a cummulative result for all messages + * sent with STORAGE_MSG_FLAG_BATCH will be sent. + * This is only supported by the non-secure disk proxy + * server. + * @STORAGE_MSG_FLAG_PRE_COMMIT: if set, indicates that server need to commit + * pending changes before processing this message. + * @STORAGE_MSG_FLAG_POST_COMMIT: if set, indicates that server need to commit + * pending changes after processing this message. + * @STORAGE_MSG_FLAG_TRANSACT_COMPLETE: if set, indicates that server need to commit + * current transaction after processing this message. + * It is an alias for STORAGE_MSG_FLAG_POST_COMMIT. + */ +enum storage_msg_flag { + STORAGE_MSG_FLAG_BATCH = 0x1, + STORAGE_MSG_FLAG_PRE_COMMIT = 0x2, + STORAGE_MSG_FLAG_POST_COMMIT = 0x4, + STORAGE_MSG_FLAG_TRANSACT_COMPLETE = STORAGE_MSG_FLAG_POST_COMMIT, +}; + +/* + * The following declarations are the message-specific contents of + * the 'payload' element inside struct storage_msg. + */ + +/** + * struct storage_rpmb_send_req - request format for STORAGE_RPMB_SEND + * @reliable_write_size: size in bytes of reliable write region + * @write_size: size in bytes of write region + * @read_size: number of bytes to read for a read request + * @__reserved: unused, must be set to 0 + * @payload: start of reliable write region, followed by + * write region. + * + * Only used in proxy<->server interface. + */ +struct storage_rpmb_send_req { + uint32_t reliable_write_size; + uint32_t write_size; + uint32_t read_size; + uint32_t __reserved; + uint8_t payload[0]; +}; + +/** + * struct storage_rpmb_send_resp: response type for STORAGE_RPMB_SEND + * @data: the data frames frames retrieved from the MMC. + */ +struct storage_rpmb_send_resp { + uint8_t data[0]; +}; + +/** + * struct storage_msg - generic req/resp format for all storage commands + * @cmd: one of enum storage_cmd + * @op_id: client chosen operation identifier for an instance + * of a command or atomic grouping of commands (transaction). + * @flags: one or many of enum storage_msg_flag or'ed together. + * @size: total size of the message including this header + * @result: one of enum storage_err + * @__reserved: unused, must be set to 0. + * @payload: beginning of command specific message format + */ +struct storage_msg { + uint32_t cmd; + uint32_t op_id; + uint32_t flags; + uint32_t size; + int32_t result; + uint32_t __reserved; + uint8_t payload[0]; +}; + +#endif /* TRUSTY_INTERFACE_STORAGE_H_ */ diff --git a/include/lcd.h b/include/lcd.h index 9a4c0da5bac..b9c94cdabb3 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -30,6 +30,7 @@ extern struct vidinfo panel_info; void lcd_ctrl_init(void *lcdbase); void lcd_enable(void); void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue); +void lcd_initcolregs (void); ulong lcd_setmem(ulong addr); /** @@ -47,6 +48,64 @@ void lcd_set_flush_dcache(int flush); #include #elif defined(CONFIG_EXYNOS_FB) #include +#elif defined(CONFIG_MXC_EPDC) + +struct waveform_modes { + int mode_init; + int mode_du; + int mode_gc4; + int mode_gc8; + int mode_gc16; + int mode_gc32; +}; + +struct epdc_timing_params { + int vscan_holdoff; + int sdoed_width; + int sdoed_delay; + int sdoez_width; + int sdoez_delay; + int gdclk_hp_offs; + int gdsp_offs; + int gdoe_offs; + int gdclk_offs; + int num_ce; +}; + +struct epdc_data_struct { + /* EPDC buffer pointers */ + u_long working_buf_addr; + u_long waveform_buf_addr; + + /* Waveform mode definitions */ + struct waveform_modes wv_modes; + struct epdc_timing_params epdc_timings; +}; + +typedef struct vidinfo { + u_long vl_refresh; /* Refresh Rate Hz */ + u_long vl_row; /* resolution in x */ + u_long vl_col; /* resolution in y */ + u_long vl_rot; + u_long vl_pixclock; /* pixel clock in picoseconds */ + u_long vl_left_margin; /* Horizontal back porch */ + u_long vl_right_margin; /* Horizontal front porch */ + u_long vl_upper_margin; /* Vertical back porch */ + u_long vl_lower_margin; /* Vertical front porch */ + u_long vl_hsync; /* Horizontal sync pulse length */ + u_long vl_vsync; /* Vertical sync pulse length */ + u_long vl_sync; /* Polarity on data enable */ + u_long vl_mode; /* Video Mode */ + u_long vl_flag; + u_char vl_bpix; + ushort *cmap; + struct epdc_data_struct epdc_data; +} vidinfo_t; + +static __maybe_unused ushort *configuration_get_cmap(void) +{ + return panel_info.cmap; +} #else typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 160) */ @@ -163,6 +222,16 @@ void lcd_sync(void); #define LCD_BPP LCD_COLOR8 #endif +#if LCD_BPP == LCD_MONOCHROME +# define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ + (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) +#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || \ + (LCD_BPP == LCD_COLOR32) +# define COLOR_MASK(c) (c) +#else +#error Unsupported LCD BPP. +#endif + #ifndef LCD_DF #define LCD_DF 1 #endif @@ -171,7 +240,14 @@ void lcd_sync(void); #define NBITS(bit_code) (1 << (bit_code)) #define NCOLORS(bit_code) (1 << NBITS(bit_code)) -#if LCD_BPP == LCD_COLOR8 +#if LCD_BPP == LCD_MONOCHROME +/* + * Simple black/white definitions + */ +# define CONSOLE_COLOR_BLACK 0 +# define CONSOLE_COLOR_WHITE 1 /* Must remain last / highest */ + +#elif LCD_BPP == LCD_COLOR8 # define CONSOLE_COLOR_BLACK 0 # define CONSOLE_COLOR_RED 1 # define CONSOLE_COLOR_GREEN 2 diff --git a/include/linux/ethtool.h b/include/linux/ethtool.h index f6dbdb096d3..ccb5b8c123f 100644 --- a/include/linux/ethtool.h +++ b/include/linux/ethtool.h @@ -620,6 +620,10 @@ enum ethtool_sfeatures_retval_bits { #define SPEED_1000 1000 #define SPEED_2500 2500 #define SPEED_10000 10000 +#define SPEED_25000 25000 +#define SPEED_40000 40000 +#define SPEED_50000 50000 +#define SPEED_100000 100000 /* Duplex, half or full. */ #define DUPLEX_HALF 0x00 diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h index 66febc6b721..cfb1334c4a2 100644 --- a/include/linux/mtd/rawnand.h +++ b/include/linux/mtd/rawnand.h @@ -55,7 +55,7 @@ void nand_wait_ready(struct mtd_info *mtd); * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ -#define NAND_MAX_OOBSIZE 1664 +#define NAND_MAX_OOBSIZE 1872 #define NAND_MAX_PAGESIZE 16384 /* diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index 9ceee0a1c9f..c63a5f34c0c 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -154,6 +154,7 @@ struct dwc3 { /* offset: 0xC100 */ /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) +#define DWC3_GCTL_PWRDNSCALE_MASK DWC3_GCTL_PWRDNSCALE(0x1fff) #define DWC3_GCTL_U2RSTECN (1 << 16) #define DWC3_GCTL_RAMCLKSEL(x) \ (((x) & DWC3_GCTL_CLK_MASK) << 6) diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h index 7e6d329e542..cc8c2eaafcf 100644 --- a/include/linux/usb/gadget.h +++ b/include/linux/usb/gadget.h @@ -973,7 +973,6 @@ extern int usb_gadget_handle_interrupts(int index); #if CONFIG_IS_ENABLED(DM_USB_GADGET) int usb_gadget_initialize(int index); int usb_gadget_release(int index); -int dm_usb_gadget_handle_interrupts(struct udevice *dev); #else #include static inline int usb_gadget_initialize(int index) diff --git a/include/lmb.h b/include/lmb.h index e9f19b16ea0..61aa146aa0d 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -37,6 +37,7 @@ extern void lmb_init_and_reserve_range(struct lmb *lmb, phys_addr_t base, phys_size_t size, void *fdt_blob); extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size); extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size); +extern long lmb_reserve_overlap(struct lmb *lmb, phys_addr_t base, phys_size_t size); extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align); extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align, phys_addr_t max_addr); diff --git a/include/mailbox.h b/include/mailbox.h index 93f4715e169..639ce324c0d 100644 --- a/include/mailbox.h +++ b/include/mailbox.h @@ -122,7 +122,7 @@ int mbox_free(struct mbox_chan *chan); * will ignore this parameter. * @return 0 if OK, or a negative error code. */ -int mbox_send(struct mbox_chan *chan, const void *data); +int mbox_send(struct mbox_chan *chan, const void *data, ulong timeout_us); /** * mbox_recv - Receive any available message from a mailbox channel diff --git a/include/mmc.h b/include/mmc.h index 8600881705f..6695cb64be3 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -341,6 +341,8 @@ static inline bool mmc_is_tuning_cmd(uint cmdidx) #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1) #define MMC_QUIRK_RETRY_APP_CMD BIT(2) +#define BOOT1_PWR_WP (0x83) + enum mmc_voltage { MMC_SIGNAL_VOLTAGE_000 = 0, MMC_SIGNAL_VOLTAGE_120 = 1, @@ -876,6 +878,24 @@ int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode); /* Function to modify the RST_n_FUNCTION field of EXT_CSD */ int mmc_set_rst_n_function(struct mmc *mmc, u8 enable); /* Functions to read / write the RPMB partition */ +/* Sizes of RPMB data frame */ +#define RPMB_SZ_STUFF 196 +#define RPMB_SZ_MAC 32 +#define RPMB_SZ_DATA 256 +#define RPMB_SZ_NONCE 16 + +/* Structure of RPMB data frame. */ +struct s_rpmb { + unsigned char stuff[RPMB_SZ_STUFF]; + unsigned char mac[RPMB_SZ_MAC]; + unsigned char data[RPMB_SZ_DATA]; + unsigned char nonce[RPMB_SZ_NONCE]; + unsigned int write_counter; + unsigned short address; + unsigned short block_count; + unsigned short result; + unsigned short request; +}; int mmc_rpmb_set_key(struct mmc *mmc, void *key); int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter); int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk, @@ -901,6 +921,11 @@ int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk, int mmc_rpmb_route_frames(struct mmc *mmc, void *req, unsigned long reqlen, void *rsp, unsigned long rsplen); +int mmc_rpmb_request(struct mmc *mmc, const struct s_rpmb *s, + unsigned int count, bool is_rel_write); +int mmc_rpmb_response(struct mmc *mmc, struct s_rpmb *s, + unsigned int count, unsigned short expected); + #ifdef CONFIG_CMD_BKOPS_ENABLE int mmc_set_bkops_enable(struct mmc *mmc); #endif @@ -956,6 +981,7 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); extern uint mmc_get_env_part(struct mmc *mmc); # endif int mmc_get_env_dev(void); +int mmc_map_to_kernel_blk(int dev_no); /* Minimum partition switch timeout in units of 10-milliseconds */ #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */ diff --git a/include/mxc_epdc_fb.h b/include/mxc_epdc_fb.h new file mode 100644 index 00000000000..9aef8a17295 --- /dev/null +++ b/include/mxc_epdc_fb.h @@ -0,0 +1,552 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ +#ifndef __EPDC_REGS_INCLUDED__ +#define __EPDC_REGS_INCLUDED__ + +#include +#include +#include + +/************************************* + * Register addresses + *************************************/ +#define EPDC_BASE (EPDC_BASE_ADDR) + +#define EPDC_CTRL 0x000 +#define EPDC_CTRL_SET 0x004 +#define EPDC_CTRL_CLR 0x008 +#define EPDC_CTRL_TOG 0x00C +#define EPDC_WVADDR 0x020 +#define EPDC_WB_ADDR 0x030 +#define EPDC_RES 0x040 +#define EPDC_FORMAT 0x050 +#define EPDC_FORMAT_SET 0x054 +#define EPDC_FORMAT_CLR 0x058 +#define EPDC_FORMAT_TOG 0x05C +#define EPDC_WB_FIELD0 0x060 +#define EPDC_WB_FIELD0_SET 0x064 +#define EPDC_WB_FIELD0_CLR 0x068 +#define EPDC_WB_FIELD0_TOG 0x06C +#define EPDC_WB_FIELD1 0x070 +#define EPDC_WB_FIELD1_SET 0x074 +#define EPDC_WB_FIELD1_CLR 0x078 +#define EPDC_WB_FIELD1_TOG 0x07C +#define EPDC_WB_FIELD2 0x080 +#define EPDC_WB_FIELD2_SET 0x084 +#define EPDC_WB_FIELD2_CLR 0x088 +#define EPDC_WB_FIELD2_TOG 0x08C +#define EPDC_WB_FIELD3 0x090 +#define EPDC_WB_FIELD3_SET 0x094 +#define EPDC_WB_FIELD3_CLR 0x098 +#define EPDC_WB_FIELD3_TOG 0x09C +#define EPDC_FIFOCTRL 0x0A0 +#define EPDC_FIFOCTRL_SET 0x0A4 +#define EPDC_FIFOCTRL_CLR 0x0A8 +#define EPDC_FIFOCTRL_TOG 0x0AC +#define EPDC_UPD_ADDR 0x100 +#define EPDC_UPD_STRIDE 0x110 +#define EPDC_UPD_CORD 0x120 +#define EPDC_UPD_SIZE 0x140 +#define EPDC_UPD_CTRL 0x160 +#define EPDC_UPD_FIXED 0x180 +#define EPDC_TEMP 0x1A0 +#define EPDC_AUTOWV_LUT 0x1C0 +#define EPDC_LUT_STANDBY1 0x1E0 +#define EPDC_LUT_STANDBY1_SET 0x1E4 +#define EPDC_LUT_STANDBY1_CLR 0x1E8 +#define EPDC_LUT_STANDBY1_TOG 0x1EC +#define EPDC_LUT_STANDBY2 0x1F0 +#define EPDC_LUT_STANDBY2_SET 0x1F4 +#define EPDC_LUT_STANDBY2_CLR 0x1F8 +#define EPDC_LUT_STANDBY2_TOG 0x1FC +#define EPDC_TCE_CTRL 0x200 +#define EPDC_TCE_SDCFG 0x220 +#define EPDC_TCE_GDCFG 0x240 +#define EPDC_TCE_HSCAN1 0x260 +#define EPDC_TCE_HSCAN2 0x280 +#define EPDC_TCE_VSCAN 0x2A0 +#define EPDC_TCE_OE 0x2C0 +#define EPDC_TCE_POLARITY 0x2E0 +#define EPDC_TCE_TIMING1 0x300 +#define EPDC_TCE_TIMING2 0x310 +#define EPDC_TCE_TIMING3 0x320 +#define EPDC_PIGEON_CTRL0 0x380 +#define EPDC_PIGEON_CTRL1 0x390 +#define EPDC_IRQ_MASK1 0x3C0 +#define EPDC_IRQ_MASK1_SET 0x3C4 +#define EPDC_IRQ_MASK1_CLR 0x3C8 +#define EPDC_IRQ_MASK1_TOG 0x3CC +#define EPDC_IRQ_MASK2 0x3D0 +#define EPDC_IRQ_MASK2_SET 0x3D4 +#define EPDC_IRQ_MASK2_CLR 0x3D8 +#define EPDC_IRQ_MASK2_TOG 0x3DC +#define EPDC_IRQ1 0x3E0 +#define EPDC_IRQ1_SET 0x3E4 +#define EPDC_IRQ1_CLR 0x3E8 +#define EPDC_IRQ1_TOG 0x3EC +#define EPDC_IRQ2 0x3F0 +#define EPDC_IRQ2_SET 0x3F4 +#define EPDC_IRQ2_CLR 0x3F8 +#define EPDC_IRQ2_TOG 0x3FC +#define EPDC_IRQ_MASK 0x400 +#define EPDC_IRQ_MASK_SET 0x404 +#define EPDC_IRQ_MASK_CLR 0x408 +#define EPDC_IRQ_MASK_TOG 0x40C +#define EPDC_IRQ 0x420 +#define EPDC_IRQ_SET 0x424 +#define EPDC_IRQ_CLR 0x428 +#define EPDC_IRQ_TOG 0x42C +#define EPDC_STATUS_LUTS 0x440 +#define EPDC_STATUS_LUTS_SET 0x444 +#define EPDC_STATUS_LUTS_CLR 0x448 +#define EPDC_STATUS_LUTS_TOG 0x44C +#define EPDC_STATUS_LUTS2 0x450 +#define EPDC_STATUS_LUTS2_SET 0x454 +#define EPDC_STATUS_LUTS2_CLR 0x458 +#define EPDC_STATUS_LUTS2_TOG 0x45C +#define EPDC_STATUS_NEXTLUT 0x460 +#define EPDC_STATUS_COL 0x480 +#define EPDC_STATUS_COL2 0x490 +#define EPDC_STATUS 0x4A0 +#define EPDC_STATUS_SET 0x4A4 +#define EPDC_STATUS_CLR 0x4A8 +#define EPDC_STATUS_TOG 0x4AC +#define EPDC_UPD_COL_CORD 0x4C0 +#define EPDC_UPD_COL_SIZE 0x4E0 +#define EPDC_DEBUG 0x500 +#define EPDC_DEBUG_LUT 0x530 +#define EPDC_HIST1_PARAM 0x600 +#define EPDC_HIST2_PARAM 0x610 +#define EPDC_HIST4_PARAM 0x620 +#define EPDC_HIST8_PARAM0 0x630 +#define EPDC_HIST8_PARAM1 0x640 +#define EPDC_HIST16_PARAM0 0x650 +#define EPDC_HIST16_PARAM1 0x660 +#define EPDC_HIST16_PARAM2 0x670 +#define EPDC_HIST16_PARAM3 0x680 +#define EPDC_GPIO 0x700 +#define EPDC_VERSION 0x7F0 +#define EPDC_PIGEON_0_0 0x800 +#define EPDC_PIGEON_0_1 0x810 +#define EPDC_PIGEON_0_2 0x820 +#define EPDC_PIGEON_1_0 0x840 +#define EPDC_PIGEON_1_1 0x850 +#define EPDC_PIGEON_1_2 0x860 +#define EPDC_PIGEON_2_0 0x880 +#define EPDC_PIGEON_2_1 0x890 +#define EPDC_PIGEON_2_2 0x8A0 +#define EPDC_PIGEON_3_0 0x8C0 +#define EPDC_PIGEON_3_1 0x8D0 +#define EPDC_PIGEON_3_2 0x8E0 +#define EPDC_PIGEON_4_0 0x900 +#define EPDC_PIGEON_4_1 0x910 +#define EPDC_PIGEON_4_2 0x920 +#define EPDC_PIGEON_5_0 0x940 +#define EPDC_PIGEON_5_1 0x950 +#define EPDC_PIGEON_5_2 0x960 +#define EPDC_PIGEON_6_0 0x980 +#define EPDC_PIGEON_6_1 0x990 +#define EPDC_PIGEON_6_2 0x9A0 +#define EPDC_PIGEON_7_0 0x9C0 +#define EPDC_PIGEON_7_1 0x9D0 +#define EPDC_PIGEON_7_2 0x9E0 +#define EPDC_PIGEON_8_0 0xA00 +#define EPDC_PIGEON_8_1 0xA10 +#define EPDC_PIGEON_8_2 0xA20 +#define EPDC_PIGEON_9_0 0xA40 +#define EPDC_PIGEON_9_1 0xA50 +#define EPDC_PIGEON_9_2 0xA60 +#define EPDC_PIGEON_10_0 0xA80 +#define EPDC_PIGEON_10_1 0xA90 +#define EPDC_PIGEON_10_2 0xAA0 +#define EPDC_PIGEON_11_0 0xAC0 +#define EPDC_PIGEON_11_1 0xAD0 +#define EPDC_PIGEON_11_2 0xAE0 +#define EPDC_PIGEON_12_0 0xB00 +#define EPDC_PIGEON_12_1 0xB10 +#define EPDC_PIGEON_12_2 0xB20 +#define EPDC_PIGEON_13_0 0xB40 +#define EPDC_PIGEON_13_1 0xB50 +#define EPDC_PIGEON_13_2 0xB60 +#define EPDC_PIGEON_14_0 0xB80 +#define EPDC_PIGEON_14_1 0xB90 +#define EPDC_PIGEON_14_2 0xBA0 +#define EPDC_PIGEON_15_0 0xBC0 +#define EPDC_PIGEON_15_1 0xBD0 +#define EPDC_PIGEON_15_2 0xBE0 +#define EPDC_PIGEON_16_0 0xC00 +#define EPDC_PIGEON_16_1 0xC10 +#define EPDC_PIGEON_16_2 0xC20 +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) +#define EPDC_WB_ADDR_TCE 0x010 +#else +#define EPDC_WB_ADDR_TCE 0xC10 +#endif + +#define REG_RD(base, reg) \ + (*(volatile unsigned int *)((base) + (reg))) +#define REG_WR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg))) = (value)) +#define REG_SET(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value)) +#define REG_CLR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value)) +#define REG_TOG(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value)) +/* + * Register field definitions + */ + +enum { +/* EPDC_CTRL field values */ + EPDC_CTRL_SFTRST = 0x80000000, + EPDC_CTRL_CLKGATE = 0x40000000, + EPDC_CTRL_SRAM_POWERDOWN = 0x100, + EPDC_CTRL_UPD_DATA_SWIZZLE_MASK = 0xC0, + EPDC_CTRL_UPD_DATA_SWIZZLE_NO_SWAP = 0, + EPDC_CTRL_UPD_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x40, + EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_SWAP = 0x80, + EPDC_CTRL_UPD_DATA_SWIZZLE_HWD_BYTE_SWAP = 0xC0, + EPDC_CTRL_LUT_DATA_SWIZZLE_MASK = 0x30, + EPDC_CTRL_LUT_DATA_SWIZZLE_NO_SWAP = 0, + EPDC_CTRL_LUT_DATA_SWIZZLE_ALL_BYTES_SWAP = 0x10, + EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_SWAP = 0x20, + EPDC_CTRL_LUT_DATA_SWIZZLE_HWD_BYTE_SWAP = 0x30, + EPDC_CTRL_BURST_LEN_8_8 = 0x1, + EPDC_CTRL_BURST_LEN_8_16 = 0, + +/* EPDC_RES field values */ + EPDC_RES_VERTICAL_MASK = 0x1FFF0000, + EPDC_RES_VERTICAL_OFFSET = 16, + EPDC_RES_HORIZONTAL_MASK = 0x1FFF, + EPDC_RES_HORIZONTAL_OFFSET = 0, + +/* EPDC_FORMAT field values */ + EPDC_FORMAT_BUF_PIXEL_SCALE_ROUND = 0x1000000, + EPDC_FORMAT_DEFAULT_TFT_PIXEL_MASK = 0xFF0000, + EPDC_FORMAT_DEFAULT_TFT_PIXEL_OFFSET = 16, + EPDC_FORMAT_WB_ADDR_NO_COPY = 0x4000, + EPDC_FORMAT_WB_TYPE_MASK = 0x3000, + EPDC_FORMAT_WB_TYPE_OFFSET = 12, + EPDC_FORMAT_WB_TYPE_WB_INTERNAL = 0x0, + EPDC_FORMAT_WB_TYPE_WB_WAVEFORM = 0x1000, + EPDC_FORMAT_WB_TYPE_WB_EXTERNAL16 = 0x2000, + EPDC_FORMAT_WB_TYPE_WB_EXTERNAL32 = 0x3000, + EPDC_FORMAT_WB_COMPRESS = 0x800, + EPDC_FORMAT_BUF_PIXEL_FORMAT_MASK = 0x700, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P2N = 0x200, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P3N = 0x300, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P4N = 0x400, + EPDC_FORMAT_BUF_PIXEL_FORMAT_P5N = 0x500, + EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT = 0x0, + EPDC_FORMAT_TFT_PIXEL_FORMAT_2BIT_VCOM = 0x1, + EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT = 0x2, + EPDC_FORMAT_TFT_PIXEL_FORMAT_4BIT_VCOM = 0x3, + +/* EPDC_WB_FIELD field values */ + EPDC_WB_FIELD_FIXED_MASK = 0xFF000000, + EPDC_WB_FIELD_FIXED_OFFSET = 24, + EPDC_WB_FIELD_USE_FIXED_MASK = 0x30000, + EPDC_WB_FIELD_USE_FIXED_OFFSET = 16, + EPDC_WB_FIELD_USE_FIXED_NO_FIXED = 0x0, + EPDC_WB_FIELD_USE_FIXED_USE_FIXED = 0x1, + EPDC_WB_FIELD_USE_FIXED_NE_FIXED = 0x2, + EPDC_WB_FIELD_USE_FIXED_EQ_FIXED = 0x3, + EPDC_WB_FIELD_USAGE_MASK = 0xE000, + EPDC_WB_FIELD_USAGE_OFFSET = 13, + EPDC_WB_FIELD_USAGE_NOT_USED = 0x0, + EPDC_WB_FIELD_USAGE_PARTIAL = 0x3, + EPDC_WB_FIELD_USAGE_LUT = 0x4, + EPDC_WB_FIELD_USAGE_CP = 0x5, + EPDC_WB_FIELD_USAGE_NP = 0x6, + EPDC_WB_FIELD_USAGE_PTS = 0x7, + EPDC_WB_FIELD_FROM_MASK = 0x1F00, + EPDC_WB_FIELD_FROM_OFFSET = 8, + EPDC_WB_FIELD_TO_MASK = 0xF0, + EPDC_WB_FIELD_TO_OFFSET = 4, + EPDC_WB_FIELD_LEN_MASK = 0xF, + EPDC_WB_FIELD_LEN_OFFSET = 0, + +/* EPDC_FIFOCTRL field values */ + EPDC_FIFOCTRL_ENABLE_PRIORITY = 0x80000000, + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_MASK = 0xFF0000, + EPDC_FIFOCTRL_FIFO_INIT_LEVEL_OFFSET = 16, + EPDC_FIFOCTRL_FIFO_H_LEVEL_MASK = 0xFF00, + EPDC_FIFOCTRL_FIFO_H_LEVEL_OFFSET = 8, + EPDC_FIFOCTRL_FIFO_L_LEVEL_MASK = 0xFF, + EPDC_FIFOCTRL_FIFO_L_LEVEL_OFFSET = 0, + +/* EPDC_UPD_CORD field values */ + EPDC_UPD_CORD_YCORD_MASK = 0x1FFF0000, + EPDC_UPD_CORD_YCORD_OFFSET = 16, + EPDC_UPD_CORD_XCORD_MASK = 0x1FFF, + EPDC_UPD_CORD_XCORD_OFFSET = 0, + +/* EPDC_UPD_SIZE field values */ + EPDC_UPD_SIZE_HEIGHT_MASK = 0x1FFF0000, + EPDC_UPD_SIZE_HEIGHT_OFFSET = 16, + EPDC_UPD_SIZE_WIDTH_MASK = 0x1FFF, + EPDC_UPD_SIZE_WIDTH_OFFSET = 0, + +/* EPDC_UPD_CTRL field values */ + EPDC_UPD_CTRL_USE_FIXED = 0x80000000, +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) + EPDC_UPD_CTRL_LUT_SEL_MASK = 0x3F0000, +#else + EPDC_UPD_CTRL_LUT_SEL_MASK = 0xF0000, +#endif + EPDC_UPD_CTRL_LUT_SEL_OFFSET = 16, + EPDC_UPD_CTRL_WAVEFORM_MODE_MASK = 0xFF00, + EPDC_UPD_CTRL_WAVEFORM_MODE_OFFSET = 8, + EPDC_UPD_CTRL_NO_LUT_CANCEL = 0x10, + EPDC_UPD_CTRL_AUTOWV_PAUSE = 0x8, + EPDC_UPD_CTRL_AUTOWV = 0x4, + EPDC_UPD_CTRL_DRY_RUN = 0x2, + EPDC_UPD_CTRL_UPDATE_MODE_FULL = 0x1, + +/* EPDC_UPD_FIXED field values */ + EPDC_UPD_FIXED_FIXNP_EN = 0x80000000, + EPDC_UPD_FIXED_FIXCP_EN = 0x40000000, + EPDC_UPD_FIXED_FIXNP_MASK = 0xFF00, + EPDC_UPD_FIXED_FIXNP_OFFSET = 8, + EPDC_UPD_FIXED_FIXCP_MASK = 0xFF, + EPDC_UPD_FIXED_FIXCP_OFFSET = 0, + +/* EPDC_AUTOWV_LUT field values */ + EPDC_AUTOWV_LUT_DATA_MASK = 0xFF0000, + EPDC_AUTOWV_LUT_DATA_OFFSET = 16, +#if defined(CONFIG_MX7) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX6SLL) + EPDC_AUTOWV_LUT_ADDR_MASK = 0x7, +#else + EPDC_AUTOWV_LUT_ADDR_MASK = 0xFF, +#endif + EPDC_AUTOWV_LUT_ADDR_OFFSET = 0, + +/* EPDC_TCE_CTRL field values */ + EPDC_TCE_CTRL_VSCAN_HOLDOFF_MASK = 0x1FF0000, + EPDC_TCE_CTRL_VSCAN_HOLDOFF_OFFSET = 16, + EPDC_TCE_CTRL_VCOM_VAL_MASK = 0xC00, + EPDC_TCE_CTRL_VCOM_VAL_OFFSET = 10, + EPDC_TCE_CTRL_VCOM_MODE_AUTO = 0x200, + EPDC_TCE_CTRL_VCOM_MODE_MANUAL = 0x000, + EPDC_TCE_CTRL_DDR_MODE_ENABLE = 0x100, + EPDC_TCE_CTRL_LVDS_MODE_CE_ENABLE = 0x80, + EPDC_TCE_CTRL_LVDS_MODE_ENABLE = 0x40, + EPDC_TCE_CTRL_SCAN_DIR_1_UP = 0x20, + EPDC_TCE_CTRL_SCAN_DIR_0_UP = 0x10, + EPDC_TCE_CTRL_DUAL_SCAN_ENABLE = 0x8, + EPDC_TCE_CTRL_SDDO_WIDTH_16BIT = 0x4, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_2 = 1, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_4 = 2, + EPDC_TCE_CTRL_PIXELS_PER_SDCLK_8 = 3, + +/* EPDC_TCE_SDCFG field values */ + EPDC_TCE_SDCFG_SDCLK_HOLD = 0x200000, + EPDC_TCE_SDCFG_SDSHR = 0x100000, + EPDC_TCE_SDCFG_NUM_CE_MASK = 0xF0000, + EPDC_TCE_SDCFG_NUM_CE_OFFSET = 16, + EPDC_TCE_SDCFG_SDDO_REFORMAT_STANDARD = 0, + EPDC_TCE_SDCFG_SDDO_REFORMAT_FLIP_PIXELS = 0x4000, + EPDC_TCE_SDCFG_SDDO_INVERT_ENABLE = 0x2000, + EPDC_TCE_SDCFG_PIXELS_PER_CE_MASK = 0x1FFF, + EPDC_TCE_SDCFG_PIXELS_PER_CE_OFFSET = 0, + +/* EPDC_TCE_GDCFG field values */ + EPDC_TCE_SDCFG_GDRL = 0x10, + EPDC_TCE_SDCFG_GDOE_MODE_DELAYED_GDCLK = 0x2, + EPDC_TCE_SDCFG_GDSP_MODE_FRAME_SYNC = 0x1, + EPDC_TCE_SDCFG_GDSP_MODE_ONE_LINE = 0x0, + +/* EPDC_TCE_HSCAN1 field values */ + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_MASK = 0xFFF0000, + EPDC_TCE_HSCAN1_LINE_SYNC_WIDTH_OFFSET = 16, + EPDC_TCE_HSCAN1_LINE_SYNC_MASK = 0xFFF, + EPDC_TCE_HSCAN1_LINE_SYNC_OFFSET = 0, + +/* EPDC_TCE_HSCAN2 field values */ + EPDC_TCE_HSCAN2_LINE_END_MASK = 0xFFF0000, + EPDC_TCE_HSCAN2_LINE_END_OFFSET = 16, + EPDC_TCE_HSCAN2_LINE_BEGIN_MASK = 0xFFF, + EPDC_TCE_HSCAN2_LINE_BEGIN_OFFSET = 0, + +/* EPDC_TCE_VSCAN field values */ + EPDC_TCE_VSCAN_FRAME_END_MASK = 0xFF0000, + EPDC_TCE_VSCAN_FRAME_END_OFFSET = 16, + EPDC_TCE_VSCAN_FRAME_BEGIN_MASK = 0xFF00, + EPDC_TCE_VSCAN_FRAME_BEGIN_OFFSET = 8, + EPDC_TCE_VSCAN_FRAME_SYNC_MASK = 0xFF, + EPDC_TCE_VSCAN_FRAME_SYNC_OFFSET = 0, + +/* EPDC_TCE_OE field values */ + EPDC_TCE_OE_SDOED_WIDTH_MASK = 0xFF000000, + EPDC_TCE_OE_SDOED_WIDTH_OFFSET = 24, + EPDC_TCE_OE_SDOED_DLY_MASK = 0xFF0000, + EPDC_TCE_OE_SDOED_DLY_OFFSET = 16, + EPDC_TCE_OE_SDOEZ_WIDTH_MASK = 0xFF00, + EPDC_TCE_OE_SDOEZ_WIDTH_OFFSET = 8, + EPDC_TCE_OE_SDOEZ_DLY_MASK = 0xFF, + EPDC_TCE_OE_SDOEZ_DLY_OFFSET = 0, + +/* EPDC_TCE_POLARITY field values */ + EPDC_TCE_POLARITY_GDSP_POL_ACTIVE_HIGH = 0x10, + EPDC_TCE_POLARITY_GDOE_POL_ACTIVE_HIGH = 0x8, + EPDC_TCE_POLARITY_SDOE_POL_ACTIVE_HIGH = 0x4, + EPDC_TCE_POLARITY_SDLE_POL_ACTIVE_HIGH = 0x2, + EPDC_TCE_POLARITY_SDCE_POL_ACTIVE_HIGH = 0x1, + +/* EPDC_TCE_TIMING1 field values */ + EPDC_TCE_TIMING1_SDLE_SHIFT_NONE = 0x00, + EPDC_TCE_TIMING1_SDLE_SHIFT_1 = 0x10, + EPDC_TCE_TIMING1_SDLE_SHIFT_2 = 0x20, + EPDC_TCE_TIMING1_SDLE_SHIFT_3 = 0x30, + EPDC_TCE_TIMING1_SDCLK_INVERT = 0x8, + EPDC_TCE_TIMING1_SDCLK_SHIFT_NONE = 0, + EPDC_TCE_TIMING1_SDCLK_SHIFT_1CYCLE = 1, + EPDC_TCE_TIMING1_SDCLK_SHIFT_2CYCLES = 2, + EPDC_TCE_TIMING1_SDCLK_SHIFT_3CYCLES = 3, + +/* EPDC_TCE_TIMING2 field values */ + EPDC_TCE_TIMING2_GDCLK_HP_MASK = 0xFFFF0000, + EPDC_TCE_TIMING2_GDCLK_HP_OFFSET = 16, + EPDC_TCE_TIMING2_GDSP_OFFSET_MASK = 0xFFFF, + EPDC_TCE_TIMING2_GDSP_OFFSET_OFFSET = 0, + +/* EPDC_TCE_TIMING3 field values */ + EPDC_TCE_TIMING3_GDOE_OFFSET_MASK = 0xFFFF0000, + EPDC_TCE_TIMING3_GDOE_OFFSET_OFFSET = 16, + EPDC_TCE_TIMING3_GDCLK_OFFSET_MASK = 0xFFFF, + EPDC_TCE_TIMING3_GDCLK_OFFSET_OFFSET = 0, + +/* EPDC EPDC_PIGEON_CTRL0 field values */ + EPDC_PIGEON_CTRL0_LD_PERIOD_MASK = 0xFFF0000, + EPDC_PIGEON_CTRL0_LD_PERIOD_OFFSET = 16, + EPDC_PIGEON_CTRL0_FD_PERIOD_MASK = 0xFFF, + EPDC_PIGEON_CTRL0_FD_PERIOD_OFFSET = 0, + +/* EPDC EPDC_PIGEON_CTRL1 field values */ + EPDC_PIGEON_CTRL1_LD_PERIOD_MASK = 0xFFF0000, + EPDC_PIGEON_CTRL1_LD_PERIOD_OFFSET = 16, + EPDC_PIGEON_CTRL1_FD_PERIOD_MASK = 0xFFF, + EPDC_PIGEON_CTRL1_FD_PERIOD_OFFSET = 0, + +/* EPDC_IRQ_MASK/EPDC_IRQ field values */ + EPDC_IRQ_WB_CMPLT_IRQ = 0x10000, + EPDC_IRQ_LUT_COL_IRQ = 0x20000, + EPDC_IRQ_TCE_UNDERRUN_IRQ = 0x40000, + EPDC_IRQ_FRAME_END_IRQ = 0x80000, + EPDC_IRQ_BUS_ERROR_IRQ = 0x100000, + EPDC_IRQ_TCE_IDLE_IRQ = 0x200000, + EPDC_IRQ_UPD_DONE_IRQ = 0x400000, + EPDC_IRQ_PWR_IRQ = 0x800000, + +/* EPDC_STATUS_NEXTLUT field values */ + EPDC_STATUS_NEXTLUT_NEXT_LUT_VALID = 0x100, + EPDC_STATUS_NEXTLUT_NEXT_LUT_MASK = 0x3F, + EPDC_STATUS_NEXTLUT_NEXT_LUT_OFFSET = 0, + +/* EPDC_STATUS field values */ + EPDC_STATUS_HISTOGRAM_CP_MASK = 0x1F0000, + EPDC_STATUS_HISTOGRAM_CP_OFFSET = 16, + EPDC_STATUS_HISTOGRAM_NP_MASK = 0x1F00, + EPDC_STATUS_HISTOGRAM_NP_OFFSET = 8, + EPDC_STATUS_UPD_VOID = 0x8, + EPDC_STATUS_LUTS_UNDERRUN = 0x4, + EPDC_STATUS_LUTS_BUSY = 0x2, + EPDC_STATUS_WB_BUSY = 0x1, + +/* EPDC_UPD_COL_CORD field values */ + EPDC_UPD_COL_CORD_YCORD_MASK = 0x1FFF0000, + EPDC_UPD_COL_CORD_YCORD_OFFSET = 16, + EPDC_UPD_COL_CORD_XCORD_MASK = 0x1FFF, + EPDC_UPD_COL_CORD_XCORD_OFFSET = 0, + +/* EPDC_UPD_COL_SIZE field values */ + EPDC_UPD_COL_SIZE_HEIGHT_MASK = 0x1FFF0000, + EPDC_UPD_COL_SIZE_HEIGHT_OFFSET = 16, + EPDC_UPD_COL_SIZE_WIDTH_MASK = 0x1FFF, + EPDC_UPD_COL_SIZE_WIDTH_OFFSET = 0, + +/* EPDC_DEBUG field values */ + EPDC_DEBUG_DEBUG_LUT_SEL_MASK = 0x3F00000, + EPDC_DEBUG_DEBUG_LUT_SEL_OFFSET = 24, + EPDC_DEBUG_UBW_BURST_LEN_MASK = 0xF000, + EPDC_DEBUG_UBW_BURST_LEN_OFFSET = 12, + EPDC_DEBUG_UBR_BURST_LEN_MASK = 0xF00, + EPDC_DEBUG_UBR_BURST_LEN = 8, + EPDC_DEBUG_UPD_BURST_LEN_MASK = 0xF0, + EPDC_DEBUG_UPD_BURST_LEN_OFFSET = 4, + EPDC_DEBUG_UPDATE_SAME = 0x4, + EPDC_DEBUG_UNDERRUN_RECOVER = 0x2, + EPDC_DEBUG_COLLISION_OFF = 0x1, + +/* EPDC_DEBUG_LUT field values */ + EPDC_DEBUG_LUT_LUTADDR_MASK = 0x3FF0000, + EPDC_DEBUG_LUT_LUTADDR_OFFSET = 16, + EPDC_DEBUG_LUT_FRAME_MASK = 0x7FE0, + EPDC_DEBUG_LUT_FRAME_OFFSET = 5, + EPDC_DEBUG_LUT_STATEMACHINE_MASK = 0x1F, + EPDC_DEBUG_LUT_STATEMACHINE_OFFSET = 0, + +/* EPDC_HISTx_PARAM field values */ + EPDC_HIST_PARAM_VALUE0_MASK = 0x1F, + EPDC_HIST_PARAM_VALUE0_OFFSET = 0, + EPDC_HIST_PARAM_VALUE1_MASK = 0x1F00, + EPDC_HIST_PARAM_VALUE1_OFFSET = 8, + EPDC_HIST_PARAM_VALUE2_MASK = 0x1F0000, + EPDC_HIST_PARAM_VALUE2_OFFSET = 16, + EPDC_HIST_PARAM_VALUE3_MASK = 0x1F000000, + EPDC_HIST_PARAM_VALUE3_OFFSET = 24, + EPDC_HIST_PARAM_VALUE4_MASK = 0x1F, + EPDC_HIST_PARAM_VALUE4_OFFSET = 0, + EPDC_HIST_PARAM_VALUE5_MASK = 0x1F00, + EPDC_HIST_PARAM_VALUE5_OFFSET = 8, + EPDC_HIST_PARAM_VALUE6_MASK = 0x1F0000, + EPDC_HIST_PARAM_VALUE6_OFFSET = 16, + EPDC_HIST_PARAM_VALUE7_MASK = 0x1F000000, + EPDC_HIST_PARAM_VALUE7_OFFSET = 24, + EPDC_HIST_PARAM_VALUE8_MASK = 0x1F, + EPDC_HIST_PARAM_VALUE8_OFFSET = 0, + EPDC_HIST_PARAM_VALUE9_MASK = 0x1F00, + EPDC_HIST_PARAM_VALUE9_OFFSET = 8, + EPDC_HIST_PARAM_VALUE10_MASK = 0x1F0000, + EPDC_HIST_PARAM_VALUE10_OFFSET = 16, + EPDC_HIST_PARAM_VALUE11_MASK = 0x1F000000, + EPDC_HIST_PARAM_VALUE11_OFFSET = 24, + EPDC_HIST_PARAM_VALUE12_MASK = 0x1F, + EPDC_HIST_PARAM_VALUE12_OFFSET = 0, + EPDC_HIST_PARAM_VALUE13_MASK = 0x1F00, + EPDC_HIST_PARAM_VALUE13_OFFSET = 8, + EPDC_HIST_PARAM_VALUE14_MASK = 0x1F0000, + EPDC_HIST_PARAM_VALUE14_OFFSET = 16, + EPDC_HIST_PARAM_VALUE15_MASK = 0x1F000000, + EPDC_HIST_PARAM_VALUE15_OFFSET = 24, + +/* EPDC_GPIO field values */ + EPDC_GPIO_PWRSTAT = 0x100, + EPDC_GPIO_PWRWAKE = 0x80, + EPDC_GPIO_PWRCOM = 0x40, + EPDC_GPIO_PWRCTRL_MASK = 0x3C, + EPDC_GPIO_PWRCTRL_OFFSET = 2, + EPDC_GPIO_BDR_MASK = 0x3, + EPDC_GPIO_BDR_OFFSET = 0, + +/* EPDC_VERSION field values */ + EPDC_VERSION_MAJOR_MASK = 0xFF000000, + EPDC_VERSION_MAJOR_OFFSET = 24, + EPDC_VERSION_MINOR_MASK = 0xFF0000, + EPDC_VERSION_MINOR_OFFSET = 16, + EPDC_VERSION_STEP_MASK = 0xFFFF, + EPDC_VERSION_STEP_OFFSET = 0, +}; + +int board_setup_waveform_file(ulong waveform_buf); +int board_setup_logo_file(void *display_buf); +void epdc_power_on(void); +void epdc_power_off(void); + +extern void *lcd_base; + +#endif /* __EPDC_REGS_INCLUDED__ */ diff --git a/include/mxc_keyb.h b/include/mxc_keyb.h new file mode 100644 index 00000000000..c43297760c0 --- /dev/null +++ b/include/mxc_keyb.h @@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2009-2014 Freescale Semiconductor, Inc. All Rights Reserved. + * + */ + +/*! + * @defgroup keypad Keypad Driver + */ + +/*! + * @file mxc_keyb.h + * + * @brief MXC keypad header file. + * + * @ingroup keypad + */ +#ifndef __MXC_KEYB_H__ +#define __MXC_KEYB_H__ + +/*! + * Keypad Module Name + */ +#define MOD_NAME "mxckpd" + +/*! + * Keypad irq number + */ +#define KPP_IRQ MXC_INT_KPP + +/*! + * XLATE mode selection + */ +#define KEYPAD_XLATE 0 + +/*! + * RAW mode selection + */ +#define KEYPAD_RAW 1 + +/*! + * Maximum number of keys. + */ +#define MAXROW 8 +#define MAXCOL 8 +#define MXC_MAXKEY (MAXROW * MAXCOL) + +/*! + * This define indicates break scancode for every key release. A constant + * of 128 is added to the key press scancode. + */ +#define MXC_KEYRELEASE 128 + +/* + * _reg_KPP_KPCR _reg_KPP_KPSR _reg_KPP_KDDR _reg_KPP_KPDR + * Keypad Control Register Address + */ +#define KPCR (KPP_BASE_ADDR + 0x00) + +/* + * Keypad Status Register Address + */ +#define KPSR (KPP_BASE_ADDR + 0x02) + +/* + * Keypad Data Direction Address + */ +#define KDDR (KPP_BASE_ADDR + 0x04) + +/* + * Keypad Data Register + */ +#define KPDR (KPP_BASE_ADDR + 0x06) + +/* + * Key Press Interrupt Status bit + */ +#define KBD_STAT_KPKD 0x01 + +/* + * Key Release Interrupt Status bit + */ +#define KBD_STAT_KPKR 0x02 + +/* + * Key Depress Synchronizer Chain Status bit + */ +#define KBD_STAT_KDSC 0x04 + +/* + * Key Release Synchronizer Status bit + */ +#define KBD_STAT_KRSS 0x08 + +/* + * Key Depress Interrupt Enable Status bit + */ +#define KBD_STAT_KDIE 0x100 + +/* + * Key Release Interrupt Enable + */ +#define KBD_STAT_KRIE 0x200 + +/* + * Keypad Clock Enable + */ +#define KBD_STAT_KPPEN 0x400 + +/*! + * Buffer size of keypad queue. Should be a power of 2. + */ +#define KPP_BUF_SIZE 128 + +/*! + * Test whether bit is set for integer c + */ +#define TEST_BIT(c, n) ((c) & (0x1 << (n))) + +/*! + * Set nth bit in the integer c + */ +#define BITSET(c, n) ((c) | (1 << (n))) + +/*! + * Reset nth bit in the integer c + */ +#define BITRESET(c, n) ((c) & ~(1 << (n))) + +enum KeyEvent { + KDepress, + KRelease +}; + +/*! + * This enum represents the keypad state machine to maintain debounce logic + * for key press/release. + */ +enum KeyState { + + /*! + * Key press state. + */ + KStateUp, + + /*! + * Key press debounce state. + */ + KStateFirstDown, + + /*! + * Key release state. + */ + KStateDown, + + /*! + * Key release debounce state. + */ + KStateFirstUp +}; + +/*! + * Keypad Private Data Structure + */ +struct keypad_priv { + + /*! + * Keypad state machine. + */ + enum KeyState iKeyState; + + /*! + * Number of rows configured in the keypad matrix + */ + unsigned long kpp_rows; + + /*! + * Number of Columns configured in the keypad matrix + */ + unsigned long kpp_cols; +}; + +/*! + * Keypad Data Structure + * */ +struct kpp_key_info { + enum KeyEvent evt; + unsigned short val; +}; + +int mxc_kpp_init(void); +int mxc_kpp_getc(struct kpp_key_info **); + +/*! + * These functions are used to configure and the GPIO pins for keypad to + * activate and deactivate it. + */ +void setup_mxc_kpd(void); + + +#endif /* __MXC_KEYB_H__ */ diff --git a/include/mxsfb.h b/include/mxsfb.h new file mode 100644 index 00000000000..85f24aa2865 --- /dev/null +++ b/include/mxsfb.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MXSFB_H__ +#define __MXSFB_H__ + +#include + +#ifdef CONFIG_VIDEO_MXS +struct display_panel { + unsigned int reg_base; + unsigned int width; + unsigned int height; + unsigned int gdfindex; + unsigned int gdfbytespp; +}; + +void mxs_lcd_get_panel(struct display_panel *panel); +void lcdif_power_down(void); +int mxs_lcd_panel_setup(struct fb_videomode mode, int bpp, + uint32_t base_addr); +#endif + +#endif /* __MXSFB_H__ */ diff --git a/include/part.h b/include/part.h index 7f78271a983..95170388f8a 100644 --- a/include/part.h +++ b/include/part.h @@ -103,6 +103,7 @@ struct disk_part { struct blk_desc *blk_get_dev(const char *ifname, int dev); struct blk_desc *mg_disk_get_dev(int dev); +struct blk_desc *sata_get_dev(int dev); int host_get_dev_err(int dev, struct blk_desc **blk_devp); /* disk/part.c */ @@ -257,6 +258,7 @@ extern const struct block_drvr block_drvr[]; static inline struct blk_desc *blk_get_dev(const char *ifname, int dev) { return NULL; } static inline struct blk_desc *mg_disk_get_dev(int dev) { return NULL; } +static inline struct blk_desc *sata_get_dev(int dev) { return NULL; } static inline int part_get_info(struct blk_desc *dev_desc, int part, struct disk_partition *info) { return -1; } @@ -284,7 +286,8 @@ static inline int blk_get_device_part_str(const char *ifname, #ifdef CONFIG_SPL_BUILD # define part_print_ptr(x) NULL # if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \ - defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION) + defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION) || \ + defined(CONFIG_DUAL_BOOTLOADER) # define part_get_info_ptr(x) x # else # define part_get_info_ptr(x) NULL @@ -408,6 +411,15 @@ int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf); */ int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf); +/** + * write_backup_gpt_partitions - write MBR, backup gpt table. + * @param dev_desc - block device descriptor + * @param buf - buffer which contains the MBR and Primary GPT info + * + * @return - '0' on success, otherwise error + */ +int write_backup_gpt_partitions(struct blk_desc *dev_desc, void *buf); + /** * gpt_verify_headers() - Function to read and CRC32 check of the GPT's header * and partition table entries (PTE) @@ -457,6 +469,11 @@ int gpt_verify_partitions(struct blk_desc *dev_desc, */ int get_disk_guid(struct blk_desc *dev_desc, char *guid); +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_SPL_BUILD) +int part_get_info_efi_by_name(struct blk_desc *dev_desc, const char *name, + struct disk_partition *info); +#endif + #endif #if CONFIG_IS_ENABLED(DOS_PARTITION) diff --git a/include/phy.h b/include/phy.h index 2754421ed4f..acc1c34a920 100644 --- a/include/phy.h +++ b/include/phy.h @@ -517,6 +517,7 @@ int phy_cortina_init(void); int phy_cortina_access_init(void); int phy_davicom_init(void); int phy_et1011c_init(void); +int phy_in112525_init(void); int phy_lxt_init(void); int phy_marvell_init(void); int phy_micrel_ksz8xxx_init(void); @@ -574,5 +575,5 @@ static inline bool phy_interface_is_sgmii(struct phy_device *phydev) #define PHY_UID_CS4223 0x03e57003 #define PHY_UID_TN2020 0x00a19410 #define PHY_UID_IN112525_S03 0x02107440 - +#define PHY_UID_IN112525_S05 0x02107441 #endif diff --git a/include/power-domain.h b/include/power-domain.h index 72ff2ff25ba..69a6ab5ca2a 100644 --- a/include/power-domain.h +++ b/include/power-domain.h @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2016, NVIDIA CORPORATION. + * Copyright 2017 NXP + * */ #ifndef _POWER_DOMAIN_H @@ -63,6 +65,19 @@ struct power_domain { void *priv; }; +/** + * power_domain_lookup_name - Lookup the power domain device by name and request it. + * + * This looks up and requests a provider power domain by using its device name. This + * skip the associated client device, but directly get the power domain device. + * + * @name: The power domain device's name. + * @power_domain A pointer to a power domain struct to initialize. + * @return 0 if OK, or a negative error code. + */ + +int power_domain_lookup_name(const char *name, struct power_domain *power_domain); + /** * power_domain_get - Get/request the power domain for a device. * diff --git a/include/power/bd71837.h b/include/power/bd71837.h index 75e07e1de31..469973ce19f 100644 --- a/include/power/bd71837.h +++ b/include/power/bd71837.h @@ -100,4 +100,6 @@ enum { #define BD71847_LDO5_RANGE_MASK 0x20 #define BD71837_LDO7_MASK 0x0f +int power_bd71837_init(unsigned char bus); + #endif diff --git a/include/recovery.h b/include/recovery.h new file mode 100644 index 00000000000..c6b097efeb3 --- /dev/null +++ b/include/recovery.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2010-2016 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + */ + +#ifndef __RECOVERY_H_ +#define __RECOVERY_H_ + +struct reco_envs { + char *cmd; + char *args; +}; + +void board_recovery_setup(void); + +#endif diff --git a/include/reset.h b/include/reset.h index cde2c4b4a8c..1c65650c511 100644 --- a/include/reset.h +++ b/include/reset.h @@ -226,6 +226,8 @@ int reset_get_by_index_nodev(ofnode node, int index, */ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk); +int reset_get_bulk_nodev(ofnode node, struct reset_ctl_bulk *bulk); + /** * reset_get_by_name - Get/request a reset signal by name. * diff --git a/include/serial.h b/include/serial.h index 6d1e62c6770..117f2a930e0 100644 --- a/include/serial.h +++ b/include/serial.h @@ -186,6 +186,14 @@ struct dm_serial_ops { * @return character (0..255), -ve on error */ int (*getc)(struct udevice *dev); + /** + * puts() - puts a string + * + * @dev: Device pointer + * @str: string to write + * @return 0 if OK, -ve on error + */ + int (*puts)(struct udevice *dev, const char *str); /** * putc() - Write a character * diff --git a/include/spl.h b/include/spl.h index 0d134587de2..02de1868ae9 100644 --- a/include/spl.h +++ b/include/spl.h @@ -206,6 +206,9 @@ struct spl_image_info { ulong dcrc_length; ulong dcrc; #endif +#ifdef CONFIG_DUAL_BOOTLOADER + uint64_t rbindex; +#endif }; /** @@ -289,6 +292,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, #define SPL_COPY_PAYLOAD_ONLY 1 #define SPL_FIT_FOUND 2 +#define SPL_FIT_BYPASS_POST_LOAD 4 /** * spl_load_legacy_img() - Loads a legacy image from a device. diff --git a/include/trusty/avb.h b/include/trusty/avb.h new file mode 100644 index 00000000000..02128078240 --- /dev/null +++ b/include/trusty/avb.h @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_AVB_H_ +#define TRUSTY_AVB_H_ + +#include +#include +#include + +/* + * Initialize AVB TIPC client. Returns one of trusty_err. + * + * @dev: initialized with trusty_ipc_dev_create + */ +int avb_tipc_init(struct trusty_ipc_dev *dev); +/* + * Shutdown AVB TIPC client. + * + * @dev: initialized with trusty_ipc_dev_create + */ +void avb_tipc_shutdown(struct trusty_ipc_dev *dev); +/* + * Send request to secure side to read rollback index. + * Returns one of trusty_err. + * + * @slot: rollback index slot + * @value: rollback index value stored here + */ +int trusty_read_rollback_index(uint32_t slot, uint64_t *value); +/* + * Send request to secure side to write rollback index + * Returns one of trusty_err. + * + * @slot: rollback index slot + * @value: rollback index value to write + */ +int trusty_write_rollback_index(uint32_t slot, uint64_t value); +/* + * Send request to secure side to read permanent attributes. When permanent + * attributes are stored in RPMB, a hash of the permanent attributes which is + * given to AVB during verification MUST still be backed by write-once hardware. + * + * Copies attributes received by secure side to |attributes|. If |size| does not + * match the size returned by the secure side, an error is returned. Returns one + * of trusty_err. + * + * @attributes: caller allocated buffer + * @size: size of |attributes| + */ +int trusty_read_permanent_attributes(uint8_t *attributes, uint32_t size); +/* + * Send request to secure side to write permanent attributes. Permanent + * attributes can only be written to storage once. + * + * Returns one of trusty_err. + */ +int trusty_write_permanent_attributes(uint8_t *attributes, uint32_t size); +/* + * Send request to secure side to read vbmeta public key. + * + * Copies public key received by secure side to |publickey|. If |size| does not + * match the size returned by the secure side, an error is returned. Returns one + * of trusty_err. + * + * @publickey: caller allocated buffer + * @size: size of |publickey| + */ +int trusty_read_vbmeta_public_key(uint8_t *publickey, uint32_t size); +/* + * Send request to secure side to write vbmeta public key. Public key + * can only be written to storage once. + * + * Returns one of trusty_err. + */ +int trusty_write_vbmeta_public_key(uint8_t *publickey, uint32_t size); +/* + * Send request to secure side to read device lock state from RPMB. + * + * Returns one of trusty_err. + */ +int trusty_read_lock_state(uint8_t *lock_state); +/* + * Send request to secure side to write device lock state to RPMB. If the lock + * state is changed, all rollback index data will be cleared. + * + * Returns one of trusty_err. + */ +int trusty_write_lock_state(uint8_t lock_state); +/* + * Send request to secure side to lock the boot state. After this is invoked, + * the non-secure side will not be able to write to data managed by the AVB + * service until next boot. + * + * Returns one of trusty_err. + */ +int trusty_lock_boot_state(void); +/* + * Send request to secure side to read oem device unlock state from RPMB. + * + * Returns one of trusty_err. + */ +int trusty_read_oem_unlock_device_permission(uint8_t *lock_state); + +#endif /* TRUSTY_AVB_H_ */ diff --git a/include/trusty/hwcrypto.h b/include/trusty/hwcrypto.h new file mode 100644 index 00000000000..e9f03442076 --- /dev/null +++ b/include/trusty/hwcrypto.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * Copyright NXP 2018 + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + * + */ + +#ifndef TRUSTY_HWCRYPTO_H_ +#define TRUSTY_HWCRYPTO_H_ + +#include +#include +#include + +/* + * Initialize HWCRYPTO TIPC client. Returns one of trusty_err. + * + * @dev: initialized with trusty_ipc_dev_create + */ +int hwcrypto_tipc_init(struct trusty_ipc_dev *dev); +/* + * Shutdown HWCRYPTO TIPC client. + * + * @dev: initialized with trusty_ipc_dev_create + */ +void hwcrypto_tipc_shutdown(struct trusty_ipc_dev *dev); +/* + * Send request to secure side to calculate sha256 hash with caam. + * Returns one of trusty_err. + * + * @in_addr: start address of the input buf + * @in_len: size of the input buf + * @out_addr: start address of the output buf + * @out_len: size of the output buf + * @algo: hash algorithm type expect to use + */ +int hwcrypto_hash(uint32_t in_addr, uint32_t in_len, uint32_t out_addr, + uint32_t out_len, enum hwcrypto_hash_algo algo); + +/* + * Send request to secure side to generate blob with caam. + * Returns one of trusty_err. + * + * @plain_pa: physical start address of the plain blob buffer. + * @plain_size: size of the plain blob buffer. + * @blob_pa: physical start address of the generated blob buffer. + */ +int hwcrypto_gen_blob(uint32_t plain_pa, + uint32_t plain_size, uint32_t blob_pa); + +/* Send request to secure side to generate rng with caam. + * Returns one of trusty_err. + * + * @buf: physical start address of the output rng buf. + * @len: size of required rng. + * */ +int hwcrypto_gen_rng(uint32_t buf, uint32_t len); + +/* Send request to secure side to generate bkek with caam. + * Returns one of trusty_err. + * + * @buf: physical start address of the output rng buf. + * @len: size of required rng. + * */ +int hwcrypto_gen_bkek(uint32_t buf, uint32_t len); + +/* Send request to secure side to lock boot state, so some + * hwcrypto commands can't be used outside of bootloader. + * Returns one of trusty_err. + * */ +int hwcrypto_lock_boot_state(void); + +/* Send request to secure side to provision widevine keybox + * */ +int hwcrypto_provision_wv_key(const char *data, uint32_t data_size); + +/* Send request to secure side to provision encrypted widevine keybox + * */ +int hwcrypto_provision_wv_key_enc(const char *data, uint32_t data_size); + +#endif /* TRUSTY_HWCRYPTO_H_ */ diff --git a/include/trusty/imx_snvs.h b/include/trusty/imx_snvs.h new file mode 100644 index 00000000000..e2e2405c619 --- /dev/null +++ b/include/trusty/imx_snvs.h @@ -0,0 +1,11 @@ + +#ifndef _IMX_SNVS_H_ +#define _IMX_SNVS_H_ +#include + +uint32_t trusty_snvs_read(uint32_t target); +void trusty_snvs_write(uint32_t target, uint32_t value); +void trusty_snvs_update_lpcr(uint32_t target, uint32_t enable); +int imx_snvs_init(struct trusty_ipc_dev *dev); + +#endif diff --git a/include/trusty/keymaster.h b/include/trusty/keymaster.h new file mode 100644 index 00000000000..2a5551cce89 --- /dev/null +++ b/include/trusty/keymaster.h @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_KEYMASTER_H_ +#define TRUSTY_KEYMASTER_H_ + +#include +#include +#include + +/* + * Initialize Keymaster TIPC client. Returns one of trusty_err. + * + * @dev: initialized with trusty_ipc_dev_create + */ +int km_tipc_init(struct trusty_ipc_dev *dev); + +/* + * Shutdown Keymaster TIPC client. + * + * @dev: initialized with trusty_ipc_dev_create + */ +void km_tipc_shutdown(struct trusty_ipc_dev *dev); + +/* + * Set Keymaster boot parameters. Returns one of trusty_err. + * + * @os_version: OS version from Android image header + * @os_patchlevel: OS patch level from Android image header + * @verified_boot_state: one of keymaster_verified_boot_t + * @device_locked: nonzero if device is locked + * @verified_boot_key_hash: hash of key used to verify Android image + * @verified_boot_key_hash_size: size of verified_boot_key_hash + * @verified_boot_hash: cumulative hash of all images verified thus far. + * May be NULL if not computed. + * @verified_boot_hash_size: size of verified_boot_hash + */ +int trusty_set_boot_params(uint32_t os_version, uint32_t os_patchlevel, + keymaster_verified_boot_t verified_boot_state, + bool device_locked, + const uint8_t *verified_boot_key_hash, + uint32_t verified_boot_key_hash_size, + const uint8_t *verified_boot_hash, + uint32_t verified_boot_hash_size); + +/* + * Set Keymaster attestation key. Returns one of trusty_err. + * + * @key: buffer containing key + * @key_size: size of key in bytes + * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC + */ +int trusty_set_attestation_key(const uint8_t *key, uint32_t key_size, + keymaster_algorithm_t algorithm); + +/* + * Append certificate to Keymaster attestation certificate chain. Returns + * one of trusty_err. + * + * @cert: buffer containing certificate + * @cert_size: size of certificate in bytes + * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC + */ +int trusty_append_attestation_cert_chain(const uint8_t *cert, + uint32_t cert_size, + keymaster_algorithm_t algorithm); +/* + * Set encrypted Keymaster attestation key. Returns one of trusty_err. + * + * @key: buffer containing encrypted key + * @key_size: size of key in bytes + * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC + */ +int trusty_set_attestation_key_enc(const uint8_t *key, + uint32_t key_size, + keymaster_algorithm_t algorithm); + +/* + * Append encrypted certificate to Keymaster attestation certificate chain. Returns + * one of trusty_err. + * + * @cert: buffer containing encrypted certificate + * @cert_size: size of certificate in bytes + * @algorithm: one of KM_ALGORITHM_RSA or KM_ALGORITHM_EC + */ +int trusty_append_attestation_cert_chain_enc(const uint8_t *cert, + uint32_t cert_size, + keymaster_algorithm_t algorithm); +/* + * Reads a CA Request from Keymaster. On success allocates a new CA Request + * message at |*ca_request_p|, and the caller takes ownership. Returns one + * of trusty_err. + * + * @operation_start: Operation Start message + * @operation_start_size: size of operation_start + * @ca_request_p: location of newly allocated CA Request message + * @ca_request_size_p: location of size of the CA Request message + */ +int trusty_atap_get_ca_request(const uint8_t *operation_start, + uint32_t operation_start_size, + uint8_t** ca_request_p, + uint32_t* ca_request_size_p); +/* + * Sends the CA Response to Keymaster. Returns one of trusty_err. + * + * @ca_response: CA Response message + * @ca_response_size: size of ca_response + */ +int trusty_atap_set_ca_response(const uint8_t *ca_response, + uint32_t ca_response_size); + +/* +* Reads the UUID from the certificate of the last provisioned attestation +* credentials as a c-string into |*uuid_p|. Caller takes ownership of +* |*uuid_p|. Returns one of trusty_err. +* +* @uuid_p: location of newly allocated UUID c-string +*/ +int trusty_atap_read_uuid_str(char **uuid_p); + +/* + * SetProductId is only called once to set the secure product id. Caller should + * read the product id from permanent attributes structure and set the product + * id while fusing the permanent attributes. + * + * @product_id: The product id to be set. + * @size: The size of the product id. + */ +int trusty_set_product_id(const uint8_t *product_id, uint32_t size); + +/* + * trusty_get_mppubk is called to get the mppubk from trusty side. + * + * @mppubk: Pointer to the buffer which store the mppubk. + * @size: Pointer to The size of mppubk. + */ +int trusty_get_mppubk(uint8_t *mppubk, uint32_t* size); + +/* trusty_verify_secure_unlock is called to the verify the secure unlock + * credential. + * + * @unlock_credential: Poniter to the unlock credential. + * @credential_size: credential size. + * @serial: serial number to verify. + * @serial_size: serial number size. + */ +int trusty_verify_secure_unlock(uint8_t *unlock_credential, + uint32_t credential_size, + uint8_t *serial, uint32_t serial_size); + +/* + * trusty_append_attestation_id is called to set attestation Device ID. + * + * @ data: Device ID string + * @ data_size: Device ID size + * */ +int trusty_append_attestation_id(const char *data, uint32_t data_size); + +#endif /* TRUSTY_KEYMASTER_H_ */ diff --git a/include/trusty/keymaster_serializable.h b/include/trusty/keymaster_serializable.h new file mode 100644 index 00000000000..830c0ba13b5 --- /dev/null +++ b/include/trusty/keymaster_serializable.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_KEYMASTER_SERIALIZABLE_H_ +#define TRUSTY_KEYMASTER_SERIALIZABLE_H_ + +#include + +/** + * Simple serialization routines for dynamically sized keymaster messages. + */ + +/** + * Appends |data_len| bytes at |data| to |buf|. Performs no bounds checking, + * assumes sufficient memory allocated at |buf|. Returns |buf| + |data_len|. + */ +uint8_t *append_to_buf(uint8_t *buf, const void *data, size_t data_len); + +/** + * Appends |val| to |buf|. Performs no bounds checking. Returns |buf| + + * sizeof(uint32_t). + */ +uint8_t *append_uint32_to_buf(uint8_t *buf, uint32_t val); + +/** + * Appends a sized buffer to |buf|. First appends |data_len| to |buf|, then + * appends |data_len| bytes at |data| to |buf|. Performs no bounds checking. + * Returns |buf| + sizeof(uint32_t) + |data_len|. + */ +uint8_t *append_sized_buf_to_buf(uint8_t *buf, const uint8_t *data, + uint32_t data_len); + +/** + * Serializes a km_boot_params structure. On success, allocates |*out_size| + * bytes to |*out| and writes the serialized |params| to |*out|. Caller takes + * ownership of |*out|. Returns one of trusty_err. + */ +int km_boot_params_serialize(const struct km_boot_params *params, uint8_t **out, + uint32_t *out_size); + +/** + * Serializes a km_attestation_data structure. On success, allocates |*out_size| + * bytes to |*out| and writes the serialized |data| to |*out|. Caller takes + * ownership of |*out|. Returns one of trusty_err. + */ +int km_attestation_data_serialize(const struct km_attestation_data *data, + uint8_t **out, uint32_t *out_size); + +/** + * Serializes a km_attestation_id_data structure. On success, allocates |*out_size| + * bytes to |*out| and writes the serialized |data| to |*out|. Caller takes + * ownership of |*out|. Returns one of trusty_err. + */ +int km_attestation_id_data_serialize(const struct km_attestation_id_data *data, + uint8_t** out, uint32_t *out_size); + +/** + * Serializes a km_secure_unlock_data structure. On success, allocates |*out_size| + * bytes to |*out| and writes the serialized |data| to |*out|. Caller takes + * ownership of |*out|. Returns one of trusty_err. + */ +int km_secure_unlock_data_serialize(const struct km_secure_unlock_data *data, + uint8_t **out, uint32_t *out_size); + +/** + * Serializes a km_raw_buffer structure. On success, allocates |*out_size| + * bytes to |*out| and writes the serialized |data| to |*out|. Caller takes + * ownership of |*out|. Returns one of trusty_err. + */ +int km_raw_buffer_serialize(const struct km_raw_buffer *buf, uint8_t** out, + uint32_t *out_size); + +#endif /* TRUSTY_KEYMASTER_SERIALIZABLE_H_ */ diff --git a/include/trusty/libtipc.h b/include/trusty/libtipc.h new file mode 100644 index 00000000000..f06e9e9a0e6 --- /dev/null +++ b/include/trusty/libtipc.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef TRUSTY_LIBTIPC_H_ +#define TRUSTY_LIBTIPC_H_ + +#include +#include +#include +#include +#include + +/* + * Initialize TIPC library + */ +int trusty_ipc_init(void); +/* + * Shutdown TIPC library + */ +void trusty_ipc_shutdown(void); + +#endif /* TRUSTY_LIBTIPC_H_ */ diff --git a/include/trusty/rpmb.h b/include/trusty/rpmb.h new file mode 100644 index 00000000000..810b8a1d7f8 --- /dev/null +++ b/include/trusty/rpmb.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_RPMB_H_ +#define TRUSTY_RPMB_H_ + +#include +#include + +#define MMC_BLOCK_SIZE 512 + +/* + * Initialize RPMB storage proxy. Returns one of trusty_err. + * + * @dev: initialized with trusty_ipc_dev_create + * @rpmb_dev: Context of RPMB device, initialized with rpmb_storage_get_ctx + */ +int rpmb_storage_proxy_init(struct trusty_ipc_dev *dev, void *rpmb_dev); +/* + * Shutdown RPMB storage proxy + * + * @dev: initialized with trusty_ipc_dev_create + */ +void rpmb_storage_proxy_shutdown(struct trusty_ipc_dev *dev); +/* + * Execute RPMB command. Implementation is platform specific. + * Returns one of trusty_err. + * + * @rpmb_dev: Context of RPMB device, initialized with + * rpmb_storage_get_ctx + * @reliable_write_data: Buffer containing RPMB structs for reliable write + * @reliable_write_size: Size of reliable_write_data + * @write_data: Buffer containing RPMB structs for write + * @write_size: Size of write_data + * @read_data: Buffer to be filled with RPMB structs read from RPMB + * partition + * @read_size: Size of read_data + */ +int rpmb_storage_send(void *rpmb_dev, + const void *reliable_write_data, + size_t reliable_write_size, + const void *write_data, size_t write_size, + void *read_buf, size_t read_size); +/* + * Return context for RPMB device. This is called when the RPMB storage proxy is + * initialized, and subsequently used when issuing RPMB storage requests. + * Implementation is platform specific. + */ +void *rpmb_storage_get_ctx(void); + +/* + * Put back RPMB device. This is called when the RPMB storage proxy is + * shutdown + */ +void rpmb_storage_put_ctx(void *dev); + +/* + * Set rpmb key by secure side. + */ +int storage_set_rpmb_key(void); + +/* + * Erase rpmb storage by secure side. + */ +int storage_erase_rpmb(void); + +#endif /* TRUSTY_RPMB_H_ */ diff --git a/include/trusty/sysdeps.h b/include/trusty/sysdeps.h new file mode 100644 index 00000000000..b21a29ca08d --- /dev/null +++ b/include/trusty/sysdeps.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_SYSDEPS_H_ +#define TRUSTY_SYSDEPS_H_ +/* + * Change these includes to match your platform to bring in the equivalent + * types available in a normal C runtime. At least things like uint64_t, + * uintptr_t, and bool (with |false|, |true| keywords) must be present. + */ +#include +#include +#include + +/* + * These attribute macros may need to be adjusted if not using gcc or clang. + */ +#define TRUSTY_ATTR_PACKED __attribute__((packed)) +#define TRUSTY_ATTR_NO_RETURN __attribute__((noreturn)) +#define TRUSTY_ATTR_SENTINEL __attribute__((__sentinel__)) +#define TRUSTY_ATTR_WARN_UNUSED_RESULT __attribute__((warn_unused_result)) + +#define PAGE_SIZE 4096 +/* + * Struct containing attributes for memory to be shared with secure size. + */ +struct ns_mem_page_info { + uint64_t attr; +}; + +struct trusty_dev; + +/* + * Lock/unlock mutex associated with @dev. These can be safely empty in a single + * threaded environment. + * + * @dev: Trusty device initialized with trusty_dev_init + */ +void trusty_lock(struct trusty_dev *dev); +void trusty_unlock(struct trusty_dev *dev); +/* + * Disable/enable IRQ interrupts and save/restore @state + */ +void trusty_local_irq_disable(unsigned long *state); +void trusty_local_irq_restore(unsigned long *state); +/* + * Put in standby state waiting for interrupt. + * + * @dev: Trusty device initialized with trusty_dev_init + */ +void trusty_idle(struct trusty_dev *dev); +/* + * Aborts the program or reboots the device. + */ +void trusty_abort(void) TRUSTY_ATTR_NO_RETURN; +/* + * Print a formatted string. @format must point to a NULL-terminated string, and + * is followed by arguments to be printed. + */ +void trusty_printf(const char *format, ...); +/* + * Copy @n bytes from @src to @dest. + */ +void *trusty_memcpy(void *dest, const void *src, size_t n); +/* + * Set @n bytes starting at @dest to @c. Returns @dest. + */ +void *trusty_memset(void *dest, const int c, size_t n); +/* + * Copy string from @src to @dest, including the terminating NULL byte. + * + * The size of the array at @dest should be long enough to contain the string + * at @src, and should not overlap in memory with @src. + */ +char *trusty_strcpy(char *dest, const char *src); +/* + * Returns the length of @str, excluding the terminating NULL byte. + */ +size_t trusty_strlen(const char *str); +/* + * Allocate @n elements of size @size. Initializes memory to 0, returns pointer + * to it. + */ +void *trusty_calloc(size_t n, size_t size) TRUSTY_ATTR_WARN_UNUSED_RESULT; +/* + * Free memory at @addr allocated with trusty_calloc. + */ +void trusty_free(void *addr); +/* + * Allocate @count contiguous pages to be shared with secure side. + * + * Returns: vaddr of allocated memory + */ +void *trusty_alloc_pages(unsigned count) TRUSTY_ATTR_WARN_UNUSED_RESULT; +/* + * Free @count pages at @vaddr allocated by trusty_alloc_pages + */ +void trusty_free_pages(void *vaddr, unsigned count); + +#endif /* TRUSTY_SYSDEPS_H_ */ diff --git a/include/trusty/trusty_dev.h b/include/trusty/trusty_dev.h new file mode 100644 index 00000000000..899c8690fad --- /dev/null +++ b/include/trusty/trusty_dev.h @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_TRUSTY_DEV_H_ +#define TRUSTY_TRUSTY_DEV_H_ + +#include + +/* + * Architecture specific Trusty device struct. + * + * @priv_data: system dependent data, may be unused + * @api_version: TIPC version + */ +struct trusty_dev { + void *priv_data; + uint32_t api_version; +}; + +/* + * Initializes @dev with @priv, and gets the API version by calling + * into Trusty. Returns negative on error. + */ +int trusty_dev_init(struct trusty_dev *dev, void *priv); + +/* + * Cleans up anything related to @dev. Returns negative on error. + */ +int trusty_dev_shutdown(struct trusty_dev *dev); + +/* + * Invokes creation of queueless Trusty IPC device on the secure side. + * @buf will be mapped into Trusty's address space. + * + * @dev: trusty device, initialized with trusty_dev_init + * @buf: physical address info of buffer to share with Trusty + * @buf_size: size of @buf + */ +int trusty_dev_init_ipc(struct trusty_dev *dev, struct ns_mem_page_info *buf, + uint32_t buf_size); +/* + * Invokes execution of command on the secure side. + * + * @dev: trusty device, initialized with trusty_dev_init + * @buf: physical address info of shared buffer containing command + * @buf_size: size of command data + */ +int trusty_dev_exec_ipc(struct trusty_dev *dev, struct ns_mem_page_info *buf, + uint32_t buf_size); +/* + * Invokes deletion of queueless Trusty IPC device on the secure side. + * @buf is unmapped, and all open channels are closed. + * + * @dev: trusty device, initialized with trusty_dev_init + * @buf: physical address info of shared buffer + * @buf_size: size of @buf + */ +int trusty_dev_shutdown_ipc(struct trusty_dev *dev, + struct ns_mem_page_info *buf, uint32_t buf_size); + +/* + * Export Trusty fastcall API + */ +int32_t trusty_simple_fast_call32(uint32_t smcnr, + uint32_t a0, uint32_t a1, uint32_t a2); + +#endif /* TRUSTY_TRUSTY_DEV_H_ */ diff --git a/include/trusty/trusty_ipc.h b/include/trusty/trusty_ipc.h new file mode 100644 index 00000000000..ce7cbd126aa --- /dev/null +++ b/include/trusty/trusty_ipc.h @@ -0,0 +1,258 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_TRUSTY_IPC_H_ +#define TRUSTY_TRUSTY_IPC_H_ + +#include + +/* + * handle_t is an opaque 32 bit value that is used to reference an + * Trusty IPC channel + */ +typedef uint32_t handle_t; + +#define INVALID_IPC_HANDLE 0 + +/* + * Error codes returned by Trusty IPC device function calls + */ +enum trusty_err { + TRUSTY_ERR_NONE = 0, + TRUSTY_ERR_GENERIC = -1, + TRUSTY_ERR_NOT_SUPPORTED = -2, + TRUSTY_ERR_NO_MEMORY = -3, + TRUSTY_ERR_INVALID_ARGS = -4, + TRUSTY_ERR_SECOS_ERR = -5, + TRUSTY_ERR_MSG_TOO_BIG = -6, + TRUSTY_ERR_NO_MSG = -7, + TRUSTY_ERR_CHANNEL_CLOSED = -8, + TRUSTY_ERR_SEND_BLOCKED = -9, +}; +/* + * Return codes for successful Trusty IPC events (failures return trusty_err) + */ +enum trusty_event_result { + TRUSTY_EVENT_HANDLED = 1, + TRUSTY_EVENT_NONE = 2 +}; + +/* + * Combination of these values are used for the event field + * of trusty_ipc_event structure. + */ +enum trusty_ipc_event_type { + IPC_HANDLE_POLL_NONE = 0x0, + IPC_HANDLE_POLL_READY = 0x1, + IPC_HANDLE_POLL_ERROR = 0x2, + IPC_HANDLE_POLL_HUP = 0x4, + IPC_HANDLE_POLL_MSG = 0x8, + IPC_HANDLE_POLL_SEND_UNBLOCKED = 0x10, +}; + +struct trusty_dev; +struct trusty_ipc_chan; + +/* + * Trusty IPC event + * + * @event: event type + * @handle: handle this event is related to + * @cookie: cookie associated with handle + */ +struct trusty_ipc_event { + uint32_t event; + uint32_t handle; + uint64_t cookie; +}; + +struct trusty_ipc_iovec { + void *base; + size_t len; +}; + +/* + * Trusty IPC device + * + * @buf_vaddr: virtual address of shared buffer associated with device + * @buf_size: size of shared buffer + * @buf_ns: physical address info of shared buffer + * @tdev: trusty device + */ +struct trusty_ipc_dev { + void *buf_vaddr; + size_t buf_size; + struct ns_mem_page_info buf_ns; + struct trusty_dev *tdev; +}; + +/* + * Trusty IPC event handlers. + */ +struct trusty_ipc_ops { + int (*on_raw_event)(struct trusty_ipc_chan *chan, + struct trusty_ipc_event *evt); + int (*on_connect_complete)(struct trusty_ipc_chan *chan); + int (*on_send_unblocked)(struct trusty_ipc_chan *chan); + int (*on_message)(struct trusty_ipc_chan *chan); + int (*on_disconnect)(struct trusty_ipc_chan *chan); +}; + +/* + * Trusty IPC channel. + * + * @ops_ctx: refers to additional data that may be used by trusty_ipc_ops + * @handle: identifier for channel + * @complete: completion status of last event on channel + * @dev: Trusty IPC device used by channel, initialized with + trusty_ipc_dev_create + * @ops: callbacks for Trusty events + */ +struct trusty_ipc_chan { + void *ops_ctx; + handle_t handle; + volatile int complete; + struct trusty_ipc_dev *dev; + struct trusty_ipc_ops *ops; +}; + +/* + * Creates new Trusty IPC device on @tdev. Allocates shared buffer, and calls + * trusty_dev_init_ipc to register with secure side. Returns a trusty_err. + * + * @ipc_dev: new Trusty IPC device to be initialized + * @tdev: associated Trusty device + * @shared_buf_size: size of shared buffer to be allocated + */ +int trusty_ipc_dev_create(struct trusty_ipc_dev **ipc_dev, + struct trusty_dev *tdev, + size_t shared_buf_size); +/* + * Shutdown @dev. Frees shared buffer, and calls trusty_dev_shutdown_ipc + * to shutdown on the secure side. + */ +void trusty_ipc_dev_shutdown(struct trusty_ipc_dev *dev); + +/* + * Calls into secure OS to initiate a new connection to a Trusty IPC service. + * Returns handle for the new channel, a trusty_err on error. + * + * @dev: Trusty IPC device initialized with trusty_ipc_dev_create + * @port: name of port to connect to on secure side + * @cookie: cookie associated with new channel. + */ +int trusty_ipc_dev_connect(struct trusty_ipc_dev *dev, const char *port, + uint64_t cookie); +/* + * Calls into secure OS to close connection to Trusty IPC service. + * Returns a trusty_err. + * + * @dev: Trusty IPC device + * @chan: handle for connection, opened with trusty_ipc_dev_connect + */ +int trusty_ipc_dev_close(struct trusty_ipc_dev *dev, handle_t chan); + +/* + * Calls into secure OS to receive pending event. Returns a trusty_err. + * + * @dev: Trusty IPC device + * @chan: handle for connection + * @event: pointer to output event struct + */ +int trusty_ipc_dev_get_event(struct trusty_ipc_dev *dev, handle_t chan, + struct trusty_ipc_event *event); +/* + * Calls into secure OS to send message to channel. Returns a trusty_err. + * + * @dev: Trusty IPC device + * @chan: handle for connection + * @iovs: contains messages to be sent + * @iovs_cnt: number of iovecs to be sent + */ +int trusty_ipc_dev_send(struct trusty_ipc_dev *dev, handle_t chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt); +/* + * Calls into secure OS to receive message on channel. Returns number of bytes + * received on success, trusty_err on failure. + * + * @dev: Trusty IPC device + * @chan: handle for connection + * @iovs: contains received messages + * @iovs_cnt: number of iovecs received + */ +int trusty_ipc_dev_recv(struct trusty_ipc_dev *dev, handle_t chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt); + +void trusty_ipc_dev_idle(struct trusty_ipc_dev *dev); + +/* + * Initializes @chan with default values and @dev. + */ +void trusty_ipc_chan_init(struct trusty_ipc_chan *chan, + struct trusty_ipc_dev *dev); +/* + * Calls trusty_ipc_dev_connect to get a handle for channel. + * Returns a trusty_err. + * + * @chan: channel to initialize with new handle + * @port: name of port to connect to on secure side + * @wait: flag to wait for connect to complete by polling for + * IPC_HANDLE_POLL_READY event + */ +int trusty_ipc_connect(struct trusty_ipc_chan *chan, const char *port, + bool wait); +/* + * Calls trusty_ipc_dev_close and invalidates @chan. Returns a trusty_err. + */ +int trusty_ipc_close(struct trusty_ipc_chan *chan); +/* + * Calls trusty_ipc_dev_get_event to poll @dev for events. Handles + * events by calling appropriate callbacks. Returns nonnegative on success. + */ +int trusty_ipc_poll_for_event(struct trusty_ipc_dev *dev); +/* + * Calls trusty_ipc_dev_send to send a message. Returns a trusty_err. + * + * @chan: handle for connection + * @iovs: contains messages to be sent + * @iovs_cnt: number of iovecs to be sent + * @wait: flag to wait for send to complete + */ +int trusty_ipc_send(struct trusty_ipc_chan *chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + bool wait); +/* + * Calls trusty_ipc_dev_recv to receive a message. Return number of bytes + * received on success, trusty_err on failure. + * + * @chan: handle for connection + * @iovs: contains received messages + * @iovs_cnt: number of iovecs received + * @wait: flag to wait for a message to receive + */ +int trusty_ipc_recv(struct trusty_ipc_chan *chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + bool wait); + +#endif /* TRUSTY_TRUSTY_IPC_H_ */ diff --git a/include/trusty/trusty_mem.h b/include/trusty/trusty_mem.h new file mode 100644 index 00000000000..c796baa03f4 --- /dev/null +++ b/include/trusty/trusty_mem.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2018 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_TRUSTY_MEM_H_ +#define TRUSTY_TRUSTY_MEM_H_ + +#include + +/* + * Encodes the memory attributes of @va into @inf + * + * @inf: ns_mem_page_info allocated by the caller + * @va: virtual addresses to retrieve attributes for + * + * Returns 0 on success and -1 on failure + */ + +int trusty_encode_page_info(struct ns_mem_page_info *inf, void *va); + +#endif /* TRUSTY_TRUSTY_MEM_H_ */ diff --git a/include/trusty/util.h b/include/trusty/util.h new file mode 100644 index 00000000000..fff81c183ef --- /dev/null +++ b/include/trusty/util.h @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef TRUSTY_UTIL_H_ +#define TRUSTY_UTIL_H_ + +#include + +/* Returns the basename of |str|. This is defined as the last path + * component, assuming the normal POSIX separator '/'. If there are no + * separators, returns |str|. + */ +const char* trusty_basename(const char* str); + +#define TRUSTY_STRINGIFY(x) #x +#define TRUSTY_TO_STRING(x) TRUSTY_STRINGIFY(x) + +/* + * Aborts the program if @expr is false. + * + * This has no effect unless TIPC_ENABLE_DEBUG is defined. + */ +#ifdef TIPC_ENABLE_DEBUG +#define trusty_assert(expr) \ + do { \ + if (!(expr)) { \ + trusty_fatal("assert fail: " #expr "\n"); \ + } \ + } while(0) +#else +#define trusty_assert(expr) +#endif + +/* + * Prints debug message. + * + * This has no effect unless TIPC_ENABLE_DEBUG and LOCAL_LOG is defined. + */ +#ifdef TIPC_ENABLE_DEBUG +#define trusty_debug(message, ...) \ + do { \ + if (LOCAL_LOG) { \ + trusty_printf(trusty_basename(__FILE__)); \ + trusty_printf(":" TRUSTY_TO_STRING(__LINE__) ": DEBUG "); \ + trusty_printf(message, ##__VA_ARGS__); \ + } \ + } while(0) +#else +#define trusty_debug(message, ...) +#endif + +/* + * Prints info message. + */ +#define trusty_info(message, ...) \ + do { \ + trusty_printf("INFO "); \ + trusty_printf(message, ##__VA_ARGS__); \ + } while(0) + +/* + * Prints error message. + */ +#define trusty_error(message, ...) \ + do { \ + trusty_printf(trusty_basename(__FILE__)); \ + trusty_printf(":" TRUSTY_TO_STRING(__LINE__) ": ERROR "); \ + trusty_printf(message, ##__VA_ARGS__); \ + } while(0) + +/* + * Prints message and calls trusty_abort. + */ +#define trusty_fatal(message, ...) \ + do { \ + trusty_printf(trusty_basename(__FILE__)); \ + trusty_printf(":" TRUSTY_TO_STRING(__LINE__) ": FATAL "); \ + trusty_printf(message, ##__VA_ARGS__); \ + trusty_abort(); \ + } while(0) + +#endif /* TRUSTY_UTIL_H_ */ diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h index 9aa1251789a..6fbf542f671 100644 --- a/include/u-boot/sha256.h +++ b/include/u-boot/sha256.h @@ -22,4 +22,7 @@ void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN]); void sha256_csum_wd(const unsigned char *input, unsigned int ilen, unsigned char *output, unsigned int chunk_sz); +void sha256_hmac(const unsigned char *key, int keylen, + const unsigned char *input, unsigned int ilen, + unsigned char *output); #endif /* _SHA256_H */ diff --git a/include/usb/ci_udc.h b/include/usb/ci_udc.h index 06adb2bb4d3..3e10f813dc3 100644 --- a/include/usb/ci_udc.h +++ b/include/usb/ci_udc.h @@ -7,7 +7,11 @@ #ifndef __CI_UDC_H__ #define __CI_UDC_H__ +#include #define EP_MAX_PACKET_SIZE 0x200 #define EP0_MAX_PACKET_SIZE 64 + +bool ci_udc_check_bus_active(ulong ehci_addr, ulong phy_addr, int index); + #endif /* __CI_UDC_H__ */ diff --git a/include/usb/usb_mx6_common.h b/include/usb/usb_mx6_common.h new file mode 100644 index 00000000000..39751fded4e --- /dev/null +++ b/include/usb/usb_mx6_common.h @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + * + */ + +#ifndef __USB_MX6_COMMON_H__ +#define __USB_MX6_COMMON_H__ +#include + +int ehci_mx6_common_init(struct usb_ehci *ehci, int index); +#endif /* __USB_MX6_COMMON_H__ */ diff --git a/include/video_link.h b/include/video_link.h new file mode 100644 index 00000000000..5350bfa9e9d --- /dev/null +++ b/include/video_link.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __VIDEO_LINK +#define __VIDEO_LINK + +int video_link_init(void); + +int video_link_shut_down(void); + +struct udevice *video_link_get_next_device(struct udevice *curr_dev); + +struct udevice *video_link_get_video_device(void); + +int video_link_get_display_timings(struct display_timing *timings); + +#endif diff --git a/include/vsprintf.h b/include/vsprintf.h index 2290083eba4..ed8a060ee17 100644 --- a/include/vsprintf.h +++ b/include/vsprintf.h @@ -10,15 +10,60 @@ #include #include +/** + * simple_strtoul - convert a string to an unsigned long + * + * @cp: The string to be converted + * @endp: Updated to point to the first character not converted + * @base: The number base to use (0 for the default) + * Return: value decoded from string (0 if invalid) + * + * Converts a string to an unsigned long. If there are invalid characters at + * the end these are ignored. In the worst case, if all characters are invalid, + * 0 is returned + * + * A hex prefix is supported (e.g. 0x123) regardless of the value of @base. + * If found, the base is set to hex (16). + * + * If @base is 0: + * - an octal '0' prefix (e.g. 0777) sets the base to octal (8). + * - otherwise the base defaults to decimal (10). + */ ulong simple_strtoul(const char *cp, char **endp, unsigned int base); +/** + * hex_strtoul - convert a string in hex to an unsigned long + * + * @cp: The string to be converted + * @endp: Updated to point to the first character not converted + * Return: value decoded from string (0 if invalid) + * + * Converts a hex string to an unsigned long. If there are invalid characters at + * the end these are ignored. In the worst case, if all characters are invalid, + * 0 is returned + */ +unsigned long hextoul(const char *cp, char **endp); + +/** + * dec_strtoul - convert a string in decimal to an unsigned long + * + * @cp: The string to be converted + * @endp: Updated to point to the first character not converted + * Return: value decoded from string (0 if invalid) + * + * Converts a decimal string to an unsigned long. If there are invalid + * characters at the end these are ignored. In the worst case, if all characters + * are invalid, 0 is returned + */ +unsigned long dectoul(const char *cp, char **endp); + /** * strict_strtoul - convert a string to an unsigned long strictly - * @param cp The string to be converted - * @param base The number base to use - * @param res The converted result value - * @return 0 if conversion is successful and *res is set to the converted - * value, otherwise it returns -EINVAL and *res is set to 0. + * @cp: The string to be converted + * @base: The number base to use (0 for the default) + * @res: The converted result value + * Return: 0 if conversion is successful and `*res` is set to the converted + * value, otherwise it returns -EINVAL and `*res` is set to 0. * * strict_strtoul converts a string to an unsigned long only if the * string is really an unsigned long string, any string containing @@ -30,8 +75,12 @@ ulong simple_strtoul(const char *cp, char **endp, unsigned int base); * * echo will append a newline to the tail. * - * simple_strtoul just ignores the successive invalid characters and - * return the converted value of prefix part of the string. + * A hex prefix is supported (e.g. 0x123) regardless of the value of @base. + * If found, the base is set to hex (16). + * + * If @base is 0: + * - an octal '0' prefix (e.g. 0777) sets the base to octal (8). + * - otherwise the base defaults to decimal (10). * * Copied this function from Linux 2.6.38 commit ID: * 521cb40b0c44418a4fd36dc633f575813d59a43d @@ -41,6 +90,7 @@ int strict_strtoul(const char *cp, unsigned int base, unsigned long *res); unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base); long simple_strtol(const char *cp, char **endp, unsigned int base); +long long simple_strtoll(const char *cp, char **endp, unsigned int base); /** * trailing_strtol() - extract a trailing integer from a string @@ -48,8 +98,11 @@ long simple_strtol(const char *cp, char **endp, unsigned int base); * Given a string this finds a trailing number on the string and returns it. * For example, "abc123" would return 123. * - * @str: String to exxamine - * @return training number if found, else -1 + * Note that this does not handle a string without a prefix. See dectoul() for + * that case. + * + * @str: String to examine + * Return: trailing number if found, else -1 */ long trailing_strtol(const char *str); @@ -61,20 +114,38 @@ long trailing_strtol(const char *str); * characters between @str and @end - 1 are examined. If @end is NULL, it is * set to str + strlen(str). * - * @str: String to exxamine + * @str: String to examine * @end: Pointer to end of string to examine, or NULL to use the * whole string - * @return training number if found, else -1 + * Return: trailing number if found, else -1 */ long trailing_strtoln(const char *str, const char *end); +/** + * trailing_strtoln_end() - extract trailing integer from a fixed-length string + * + * Given a fixed-length string this finds a trailing number on the string + * and returns it. For example, "abc123" would return 123. Only the + * characters between @str and @end - 1 are examined. If @end is NULL, it is + * set to str + strlen(str). + * + * @str: String to examine + * @end: Pointer to end of string to examine, or NULL to use the + * whole string + * @endp: If non-NULL, this is set to point to the character where the + * number starts, e.g. for "mmc0" this would be point to the '0'; if no + * trailing number is found, it is set to the end of the string + * Return: training number if found, else -1 + */ +long trailing_strtoln_end(const char *str, const char *end, char const **endp); + /** * panic() - Print a message and reset/hang * * Prints a message on the console(s) and then resets. If CONFIG_PANIC_HANG is * defined, then it will hang instead of resetting. * - * @param fmt: printf() format string for message, which should not include + * @fmt: printf() format string for message, which should not include * \n, followed by arguments */ void panic(const char *fmt, ...) @@ -89,16 +160,16 @@ void panic(const char *fmt, ...) * This function can be used instead of panic() when your board does not * already use printf(), * to keep code size small. * - * @param fmt: string to display, which should not include \n + * @str: string to display, which should not include \n */ void panic_str(const char *str) __attribute__ ((noreturn)); /** * Format a string and place it in a buffer * - * @param buf The buffer to place the result into - * @param fmt The format string to use - * @param ... Arguments for the format string + * @buf: The buffer to place the result into + * @fmt: The format string to use + * @...: Arguments for the format string * * The function returns the number of characters written * into @buf. @@ -111,10 +182,10 @@ int sprintf(char *buf, const char *fmt, ...) /** * Format a string and place it in a buffer (va_list version) * - * @param buf The buffer to place the result into - * @param fmt The format string to use - * @param args Arguments for the format string - * @return the number of characters which have been written into + * @buf: The buffer to place the result into + * @fmt: The format string to use + * @args: Arguments for the format string + * Return: the number of characters which have been written into * the @buf not including the trailing '\0'. * * If you're not already dealing with a va_list consider using scnprintf(). @@ -122,16 +193,39 @@ int sprintf(char *buf, const char *fmt, ...) * See the vsprintf() documentation for format string extensions over C99. */ int vsprintf(char *buf, const char *fmt, va_list args); -char *simple_itoa(ulong i); + +/** + * simple_itoa() - convert an unsigned integer to a string + * + * This returns a static string containing the decimal representation of the + * given value. The returned value may be overwritten by other calls to other + * simple... functions, so should be used immediately + * + * @val: Value to convert + * Return: string containing the decimal representation of @val + */ +char *simple_itoa(ulong val); + +/** + * simple_xtoa() - convert an unsigned integer to a hex string + * + * This returns a static string containing the hexadecimal representation of the + * given value. The returned value may be overwritten by other calls to other + * simple... functions, so should be used immediately + * + * @num: Value to convert + * Return: string containing the hexecimal representation of @val + */ +char *simple_xtoa(ulong num); /** * Format a string and place it in a buffer * - * @param buf The buffer to place the result into - * @param size The size of the buffer, including the trailing null space - * @param fmt The format string to use - * @param ... Arguments for the format string - * @return the number of characters which would be + * @buf: The buffer to place the result into + * @size: The size of the buffer, including the trailing null space + * @fmt: The format string to use + * @...: Arguments for the format string + * Return: the number of characters which would be * generated for the given input, excluding the trailing null, * as per ISO C99. If the return is greater than or equal to * @size, the resulting string is truncated. @@ -144,10 +238,10 @@ int snprintf(char *buf, size_t size, const char *fmt, ...) /** * Format a string and place it in a buffer * - * @param buf The buffer to place the result into - * @param size The size of the buffer, including the trailing null space - * @param fmt The format string to use - * @param ... Arguments for the format string + * @buf: The buffer to place the result into + * @size: The size of the buffer, including the trailing null space + * @fmt: The format string to use + * @...: Arguments for the format string * * The return value is the number of characters written into @buf not including * the trailing '\0'. If @size is == 0 the function returns 0. @@ -160,11 +254,11 @@ int scnprintf(char *buf, size_t size, const char *fmt, ...) /** * Format a string and place it in a buffer (base function) * - * @param buf The buffer to place the result into - * @param size The size of the buffer, including the trailing null space - * @param fmt The format string to use - * @param args Arguments for the format string - * @return The number characters which would be generated for the given + * @buf: The buffer to place the result into + * @size: The size of the buffer, including the trailing null space + * @fmt: The format string to use + * @args: Arguments for the format string + * Return: The number characters which would be generated for the given * input, excluding the trailing '\0', as per ISO C99. Note that fewer * characters may be written if this number of characters is >= size. * @@ -185,11 +279,11 @@ int vsnprintf(char *buf, size_t size, const char *fmt, va_list args); /** * Format a string and place it in a buffer (va_list version) * - * @param buf The buffer to place the result into - * @param size The size of the buffer, including the trailing null space - * @param fmt The format string to use - * @param args Arguments for the format string - * @return the number of characters which have been written into + * @buf: The buffer to place the result into + * @size: The size of the buffer, including the trailing null space + * @fmt: The format string to use + * @args: Arguments for the format string + * Return: the number of characters which have been written into * the @buf not including the trailing '\0'. If @size is == 0 the function * returns 0. * @@ -205,8 +299,8 @@ int vscnprintf(char *buf, size_t size, const char *fmt, va_list args); * This prints a value with grouped digits, like 12,345,678 to make it easier * to read. * - * @val: Value to print - * @digits: Number of digiits to print + * @int_val: Value to print + * @digits: Number of digiits to print */ void print_grouped_ull(unsigned long long int_val, int digits); @@ -234,6 +328,38 @@ char *strmhz(char *buf, unsigned long hz); */ void str_to_upper(const char *in, char *out, size_t len); +/** + * str_to_list() - Convert a string to a list of string pointers + * + * Splits a string containing space-delimited substrings into a number of + * separate strings, e.g. "this is" becomes {"this", "is", NULL}. If @instr is + * empty then this returns just {NULL}. The string should have only a single + * space between items, with no leading or trailing spaces. + * + * @instr: String to process (this is alloced by this function) + * Returns: List of string pointers, terminated by NULL. Each entry points to + * a string. If @instr is empty, the list consists just of a single NULL entry. + * Note that the first entry points to the alloced string. + * Returns NULL if out of memory + */ +const char **str_to_list(const char *instr); + +/** + * str_free_list() - Free a string list + * + * @ptr: String list to free, as created by str_to_list(). This can also be + * NULL, in which case the function does nothing + */ +void str_free_list(const char **ptr); + +/** + * vsscanf - Unformat a buffer into a list of arguments + * @inp: input buffer + * @fmt0: format of buffer + * @ap: arguments + */ +int vsscanf(const char *inp, char const *fmt0, va_list ap); + /** * sscanf - Unformat a buffer into a list of arguments * @buf: input buffer diff --git a/lib/Kconfig b/lib/Kconfig index 72883406143..a821618af66 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -345,6 +345,38 @@ config LIBAVB device. Introduces such features as boot chain of trust, rollback protection etc. +config AVB_SUPPORT + bool "Enable Android AVB lib support" + select LIBAVB + +config AVB_ATX + bool "Enable AVB_ATX support" + depends on AVB_SUPPORT + +config AVB_WARNING_LOGO + bool "Enable avb warning show logo on screen" + help + Enable avb warning show logo on screen + +config AVB_WARNING_LOGO_COLS + hex "x resolution on the screen" + default 0x1E0 + depends on AVB_WARNING_LOGO + help + The x resolution on the screen. + +config AVB_WARNING_LOGO_ROWS + hex "y resolution on the screen" + default 0x60 + depends on AVB_WARNING_LOGO + help + The y resolution on the screen. + +config AVB_WARNING_TIME_LAST + hex "the time of avb warning logo will last" + default 0x3 + help + The time of avb warning logo will last (s). endmenu menu "Hashing Support" @@ -440,7 +472,7 @@ config LZ4 is included. The LZ4 algorithm can run in-place as long as the compressed image is loaded to the end of the output buffer, and trades lower compression ratios for much faster decompression. - + NOTE: This implements the release version of the LZ4 frame format as generated by default by the 'lz4' command line tool. This is not the same as the outdated, less efficient legacy diff --git a/lib/Makefile b/lib/Makefile index edc1c3dd4f9..e20949b820c 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91) += at91/ obj-$(CONFIG_OPTEE) += optee/ obj-$(CONFIG_ASN1_DECODER) += asn1_decoder.o obj-y += crypto/ +obj-$(CONFIG_IMX_TRUSTY_OS) += trusty/ql-tipc/ obj-$(CONFIG_AES) += aes.o obj-$(CONFIG_AES) += aes/ @@ -72,6 +73,7 @@ obj-$(CONFIG_$(SPL_)LZMA) += lzma/ obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o obj-$(CONFIG_LIBAVB) += libavb/ +obj-$(CONFIG_AVB_SUPPORT) += avb/ obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/ ifneq ($(CONFIG_$(SPL_TPL_)BUILD)$(CONFIG_$(SPL_TPL_)OF_PLATDATA),yy) diff --git a/lib/avb/Makefile b/lib/avb/Makefile new file mode 100644 index 00000000000..6841faf8553 --- /dev/null +++ b/lib/avb/Makefile @@ -0,0 +1,18 @@ +subdir-ccflags-y += -I./lib \ + -D_FILE_OFFSET_BITS=64 \ + -D_POSIX_C_SOURCE=199309L \ + -Wa,--noexecstack \ + -Wall \ + -Wextra \ + -Wformat=2 \ + -Wno-type-limits \ + -Wno-psabi \ + -Wno-unused-parameter \ + -Wno-sign-compare \ + -ffunction-sections \ + -std=gnu99 + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_AVB_ATX) += libavb_atx/ +endif +obj-y += fsl/ diff --git a/lib/avb/fsl/Makefile b/lib/avb/fsl/Makefile new file mode 100644 index 00000000000..eb641d4b41d --- /dev/null +++ b/lib/avb/fsl/Makefile @@ -0,0 +1,9 @@ +ifndef CONFIG_SPL_BUILD +obj-y += fsl_avb.o +endif + +obj-y += fsl_avbkey.o +obj-y += utils.o +obj-y += fsl_bootctrl.o +obj-$(CONFIG_AVB_ATX) += fsl_atx_attributes.o +obj-$(CONFIG_AVB_WARNING_LOGO) += orange_warning_bmp_data.o diff --git a/lib/avb/fsl/debug.h b/lib/avb/fsl/debug.h new file mode 100644 index 00000000000..c1165ec1ec1 --- /dev/null +++ b/lib/avb/fsl/debug.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AVB_DEBUG_H__ +#define __AVB_DEBUG_H__ + +#ifdef AVB_VVDEBUG +#define AVB_VDEBUG +#define VVDEBUG(format, ...) printf(" %s: "format, __func__, ##__VA_ARGS__) +#else +#define VVDEBUG(format, ...) +#endif + +#ifdef AVB_VDEBUG +#define AVB_DEBUG +#define VDEBUG(format, ...) printf(" %s: "format, __func__, ##__VA_ARGS__) +#else +#define VDEBUG(format, ...) +#endif + +#ifdef AVB_DEBUG +#define DEBUGAVB(format, ...) printf(" %s: "format, __func__, ##__VA_ARGS__) +#else +#define DEBUGAVB(format, ...) +#endif + +#define ERR(format, ...) printf("%s: "format, __func__, ##__VA_ARGS__) + +#define HEXDUMP_COLS 16 +#define HEXDUMP_WIDTH 1 + +#endif diff --git a/lib/avb/fsl/fsl_atx_attributes.c b/lib/avb/fsl/fsl_atx_attributes.c new file mode 100644 index 00000000000..2297140dd17 --- /dev/null +++ b/lib/avb/fsl/fsl_atx_attributes.c @@ -0,0 +1,145 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* This product_id is generated from + * extern/avb/test/data/atx_product_id.bin */ +unsigned char fsl_atx_product_id[16] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 +}; +/* This product_root_public_key is generated form + * extern/avb/test/data/testkey_atx_prk.pem */ +unsigned char fsl_product_root_public_key[1032] = { + 0x00,0x00,0x10,0x00,0x9f,0x35,0xef,0x65, + 0xc3,0x29,0x4c,0x23,0x16,0x10,0xac,0x32, + 0xc1,0x3c,0xd5,0xc5,0xab,0xa1,0xd9,0xe7, + 0x13,0x3f,0x7e,0xd1,0xe6,0x61,0x5d,0xa3, + 0xa1,0x60,0xda,0x57,0x4b,0xb2,0xe6,0x0f, + 0xe1,0x50,0xbf,0x47,0xff,0x09,0xaf,0xcd, + 0x49,0x2d,0x82,0x33,0x76,0xa1,0xfe,0x28, + 0x5f,0x89,0x62,0xb3,0xc0,0xf1,0x11,0xaf, + 0x15,0x09,0x27,0xdb,0xeb,0x06,0x01,0xa2, + 0xf8,0xb7,0xd7,0x9c,0xe4,0x88,0x3a,0x86, + 0x05,0x02,0x20,0x69,0xb2,0x36,0x4c,0x3e, + 0x25,0x03,0xed,0xfc,0x0c,0x6b,0x1b,0x0a, + 0x04,0x9c,0xce,0x7f,0x83,0x82,0x60,0xd9, + 0x52,0x7e,0xc4,0x35,0x7b,0x1c,0xe6,0x64, + 0x9c,0x17,0xec,0x81,0xe7,0x9c,0x0c,0x8b, + 0x4b,0x7e,0x48,0xbe,0x00,0x98,0xa8,0x20, + 0x10,0x4c,0x9b,0xd1,0x16,0x5b,0x25,0xe9, + 0x4e,0x61,0xda,0x7c,0x63,0x80,0x8f,0xa4, + 0xac,0x74,0xee,0xa8,0x06,0xac,0x26,0xd5, + 0x71,0x6f,0xaa,0x73,0x20,0x9c,0x7f,0xcd, + 0x73,0xd4,0xa9,0xa0,0x7e,0x5a,0xb5,0x61, + 0xb0,0x88,0xb0,0xdd,0xdb,0x6b,0x79,0xd1, + 0x5a,0x9e,0x54,0x49,0x55,0xc6,0x89,0x76, + 0x7a,0xc6,0x78,0x99,0xdc,0xc9,0x00,0x5d, + 0x20,0xf5,0xfc,0x8f,0x39,0x46,0xf3,0x02, + 0x96,0x0d,0x9b,0xfb,0xbc,0xd5,0xcf,0x5a, + 0x4f,0xc4,0xb8,0x0b,0xd0,0xf3,0x19,0x3c, + 0x74,0x04,0xd5,0x94,0x2c,0x19,0x15,0x64, + 0xbf,0x53,0x67,0x97,0x7b,0x9e,0xc6,0xe0, + 0xfb,0x29,0x5b,0x90,0xad,0x04,0x8a,0xd8, + 0x5b,0xdf,0x69,0x09,0xe4,0xa5,0xe9,0xd9, + 0x0f,0xc4,0xff,0xae,0xb7,0x44,0x12,0xae, + 0xad,0x03,0x97,0xb8,0xda,0xd7,0x60,0x37, + 0x15,0xf2,0xb9,0xdb,0x10,0xf6,0xe2,0x26, + 0x48,0x7e,0x3e,0x3e,0xc3,0x67,0xd3,0xa6, + 0x02,0xf7,0xbc,0x60,0xed,0x45,0xdf,0x37, + 0xef,0xf9,0xea,0x97,0x5f,0x37,0xb4,0xeb, + 0xb4,0x91,0x6c,0x39,0x4d,0xed,0x52,0x15, + 0x39,0x47,0x59,0x62,0xde,0x32,0x55,0xe1, + 0xd4,0x15,0x58,0x7d,0x52,0x41,0x12,0x78, + 0xee,0x9f,0x0d,0xc8,0x5e,0x34,0x91,0xf9, + 0xe7,0x4c,0x1e,0xe7,0x2f,0x90,0x7f,0xbb, + 0xf8,0x99,0x3e,0xc9,0x79,0xab,0x01,0xdb, + 0x24,0x39,0xe3,0xb4,0xc9,0x52,0x73,0xdb, + 0x65,0x42,0xa5,0x2e,0x43,0x56,0xa0,0x33, + 0x8c,0x1a,0xb7,0xa1,0xed,0x5c,0xd0,0x14, + 0x93,0x8d,0x23,0x78,0x93,0xcb,0x3a,0x03, + 0x1f,0xbb,0xc6,0x7b,0xcd,0x51,0x4e,0xaa, + 0x14,0x01,0xe9,0x03,0x27,0x13,0xe2,0xb2, + 0xf8,0x36,0xc6,0xe3,0xc3,0x7f,0xb5,0x74, + 0x20,0x5e,0x17,0xaa,0x25,0x07,0x9b,0x60, + 0xda,0x83,0x98,0xb5,0x55,0xae,0x1b,0x7a, + 0xc1,0x1f,0x49,0x72,0xe2,0xcb,0x6a,0x11, + 0x77,0xdf,0x3f,0xc0,0x9f,0x8f,0x33,0xc7, + 0x10,0x17,0x8c,0xfc,0xd5,0xb7,0x5f,0x5e, + 0xb2,0xe3,0x7b,0x2e,0xdc,0xc7,0x34,0xdb, + 0x31,0xb0,0xdc,0x5d,0x14,0x98,0xb6,0x1a, + 0x2a,0xd4,0xb4,0x04,0x2c,0xf0,0x68,0x1c, + 0x91,0x60,0x28,0xa5,0x3b,0x01,0x98,0xb6, + 0x1e,0x6e,0xaa,0x35,0x89,0xc7,0x94,0xaa, + 0x9e,0xf0,0x11,0x52,0x0f,0x28,0xa1,0x3d, + 0xd3,0x17,0xb5,0x08,0xd8,0x7a,0x41,0xf9, + 0x07,0xe2,0x87,0x36,0xcd,0x86,0x3e,0x79, + 0x99,0x73,0x50,0x21,0x30,0x00,0xd2,0xf3, + 0x88,0x60,0x32,0x59,0x58,0x2f,0x55,0x93, + 0x86,0x56,0x9a,0x96,0xb9,0xf8,0xbf,0x24, + 0xc4,0xba,0xea,0xa4,0x73,0xb0,0x0c,0xa6, + 0xdb,0x09,0x2d,0x0a,0x36,0x3f,0x80,0xe6, + 0x85,0x7a,0xf3,0x01,0x90,0x3a,0xc6,0xee, + 0x2d,0xa8,0xce,0xb4,0x3f,0x3a,0xa6,0xa3, + 0xaf,0xb9,0x21,0xef,0x40,0x6f,0xf4,0x7f, + 0x78,0x25,0x55,0x39,0x53,0x67,0x53,0x56, + 0x8d,0x81,0xaf,0x63,0x97,0x68,0x86,0x75, + 0x66,0x14,0x1e,0xa6,0x63,0x1e,0x02,0xd0, + 0x41,0xd8,0x78,0x75,0x0d,0x76,0x77,0xfa, + 0x9c,0xc5,0xcc,0x54,0x06,0x25,0x53,0x95, + 0xeb,0x4b,0x7c,0xb4,0xc8,0xbb,0x5d,0x6b, + 0x6e,0xf0,0xd7,0x8d,0x3f,0xdf,0x93,0x4c, + 0x30,0x5b,0x02,0xf5,0x0e,0x49,0x87,0x60, + 0x5f,0x19,0x06,0x24,0x3d,0x5d,0x97,0x37, + 0x61,0xef,0x3e,0x0b,0x9e,0x85,0x1c,0x1a, + 0xa6,0x53,0x91,0xd2,0x2c,0x18,0x7c,0x8f, + 0x5b,0x4a,0xd5,0xdd,0xd9,0x8a,0xc3,0x92, + 0x19,0x54,0x39,0xde,0x33,0xa1,0xe1,0x37, + 0x60,0x3c,0x3b,0x3b,0xc5,0xed,0x1b,0xef, + 0x28,0xf5,0xdf,0x44,0x91,0xa3,0x1e,0x69, + 0x6a,0x35,0x85,0x6e,0x26,0x46,0x22,0x4d, + 0x87,0x92,0x44,0x6b,0x96,0xdb,0x75,0xfe, + 0x76,0x03,0x60,0xf7,0xfd,0x90,0x55,0x7d, + 0x6e,0xd7,0xaa,0x44,0x05,0xc7,0x23,0x37, + 0x12,0xa8,0xd4,0xb2,0x2b,0xed,0x41,0x5f, + 0x23,0x38,0x7c,0x16,0xe6,0x16,0xd3,0x10, + 0x19,0x12,0xcc,0x8b,0x6e,0xcd,0xd6,0xa6, + 0x39,0x8a,0x1b,0x24,0x3f,0x4d,0x6f,0xa6, + 0x00,0x7c,0xa0,0xa1,0x4a,0xfd,0xcd,0x68, + 0x50,0x76,0xc8,0x68,0x9d,0xeb,0xdf,0x24, + 0x39,0xaf,0x77,0xb2,0xb6,0xaf,0xb6,0x34, + 0x61,0x37,0x6a,0xfd,0xc7,0x6d,0x02,0x9f, + 0x29,0xd5,0x45,0xf4,0x89,0xd8,0x8c,0x5c, + 0xd3,0x31,0xa0,0x58,0x19,0x54,0x33,0x46, + 0x92,0xbc,0x1e,0x4b,0x14,0xac,0x73,0xa5, + 0x09,0x9f,0xb6,0x2b,0x2b,0x73,0x6b,0x83, + 0x86,0x13,0x6e,0x03,0xf7,0xe0,0x7d,0x81, + 0x47,0x18,0x08,0xea,0x09,0x10,0x24,0x61, + 0x6d,0x09,0x1d,0xb8,0x8e,0xba,0x04,0x4d, + 0xcc,0xe6,0xff,0x28,0x27,0x86,0x38,0x01, + 0x86,0xbe,0xf0,0x5b,0xf8,0x1a,0xd6,0xde, + 0xbe,0xf9,0x3b,0x76,0x3f,0x85,0x82,0x22, + 0x92,0x4b,0xe0,0x76,0x15,0xb2,0x57,0x5a, + 0xb0,0x64,0xde,0xce,0x93,0xb8,0x9f,0x25, + 0x53,0x8c,0x5e,0xdf,0x29,0x4e,0x50,0x69, + 0xfb,0x7e,0x33,0xcb,0x0e,0x28,0x01,0x6c, + 0xab,0xfa,0xd8,0x88,0x02,0xbc,0xf2,0xb1, + 0x0e,0x2f,0x6d,0x1c,0x8d,0xe4,0x11,0x23, + 0xcc,0x67,0x94,0x7b,0xf7,0x8a,0xf3,0x68, + 0x52,0xe4,0x82,0x25,0x86,0xc6,0x72,0x19, + 0x77,0x80,0x28,0xe3,0x86,0xc8,0x8a,0xea, + 0x3d,0x54,0x2f,0x0b,0x64,0x0a,0xc5,0x12, + 0x8c,0xb2,0x07,0x72,0x1b,0x09,0x9f,0x32, + 0xbd,0xa3,0xb0,0x0c,0x95,0xc8,0x4d,0xe5, + 0xd7,0x20,0xdb,0xf8,0x34,0x2a,0x9d,0x91, + 0x58,0x38,0x7a,0x9c,0xe0,0xa3,0x0f,0x40, + 0x9d,0xff,0xeb,0x4b,0xe2,0x16,0x94,0x32, + 0xce,0xe8,0x52,0x75,0x49,0xf4,0x71,0x13, + 0xbc,0x59,0x7d,0x9a,0xe8,0x60,0x29,0x58, + 0x1a,0x14,0x94,0xe6,0x37,0x23,0xad,0xfe, + 0x0b,0xf0,0x63,0x60,0x4f,0x5d,0x10,0x91, + 0xf2,0x50,0x8e,0x0b,0x4a,0x47,0xc9,0x0c, + 0x1f,0xdc,0x94,0x75,0x25,0x52,0x99,0xfc +}; diff --git a/lib/avb/fsl/fsl_atx_attributes.h b/lib/avb/fsl/fsl_atx_attributes.h new file mode 100644 index 00000000000..e6e43835a1e --- /dev/null +++ b/lib/avb/fsl/fsl_atx_attributes.h @@ -0,0 +1,18 @@ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_ATX_ATTRIBUTES_H__ +#define __FSL_ATX_ATTRIBUTES_H__ + +#define fsl_version 1 +/* This product_id is generated from + * extern/avb/test/data/atx_product_id.bin */ +extern unsigned char fsl_atx_product_id[17]; +/* This product_root_public_key is generated form + * extern/avb/test/data/testkey_atx_prk.pem */ +extern unsigned char fsl_product_root_public_key[1032]; + +#endif /* __FSL_ATX_ATTRIBUTES_H__ */ diff --git a/lib/avb/fsl/fsl_avb.c b/lib/avb/fsl/fsl_avb.c new file mode 100644 index 00000000000..f4797f1eea0 --- /dev/null +++ b/lib/avb/fsl/fsl_avb.c @@ -0,0 +1,844 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#include +#include "../../../drivers/fastboot/fb_fsl/fastboot_lock_unlock.h" + +#include +#include "fsl_avbkey.h" +#include "utils.h" +#include "debug.h" +#include "trusty/avb.h" +#ifndef CONFIG_LOAD_KEY_FROM_RPMB +#include "fsl_public_key.h" +#endif +#include "fsl_atx_attributes.h" + +#define FSL_AVB_DEV "mmc" +#define AVB_MAX_BUFFER_LENGTH 2048 + +static struct blk_desc *fs_dev_desc = NULL; +static struct blk_desc *get_mmc_desc(void) { + extern int mmc_get_env_dev(void); + int dev_no = mmc_get_env_dev(); + return blk_get_dev(FSL_AVB_DEV, dev_no); +} + + /* Reads |num_bytes| from offset |offset| from partition with name + * |partition| (NUL-terminated UTF-8 string). If |offset| is + * negative, its absolute value should be interpreted as the number + * of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * |offset| is outside the partition, and AVB_IO_RESULT_ERROR_IO if + * there was an I/O error from the underlying I/O subsystem. If the + * operation succeeds as requested AVB_IO_RESULT_OK is returned and + * the data is available in |buffer|. + * + * The only time partial I/O may occur is if reading beyond the end + * of the partition. In this case the value returned in + * |out_num_read| may be smaller than |num_bytes|. + */ + AvbIOResult fsl_read_from_partition(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read) +{ + struct fastboot_ptentry *pte; + unsigned char *bdata; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned long blksz; + unsigned long s, cnt; + size_t num_read = 0; + lbaint_t part_start, part_end, bs, be; + margin_pos_t margin; + + AvbIOResult ret; + + DEBUGAVB("[%s]: offset=%ld, num_bytes=%zu\n", partition, (long)offset, num_bytes); + + assert(buffer != NULL && out_num_read != NULL); + + if ((fs_dev_desc = get_mmc_desc()) == NULL) { + ERR("mmc device not found\n"); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + blksz = fs_dev_desc->blksz; + part_start = pte->start; + part_end = pte->start + pte->length - 1; + VDEBUG("blksz: %ld, part_end: %ld, part_start: %ld:\n", + blksz, part_end, part_start); + + if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, true)) + return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION; + + bs = (lbaint_t)margin.blk_start; + be = (lbaint_t)margin.blk_end; + s = margin.start; + + // alloc a blksz mem + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) + return AVB_IO_RESULT_ERROR_OOM; + + // one block a time + while (bs <= be) { + memset(bdata, 0, blksz); + if (blk_dread(fs_dev_desc, bs, 1, bdata) != 1) { + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + VDEBUG("cur: bs=%ld, start=%ld, cnt=%ld bdata=0x%08x\n", + bs, s, cnt, bdata); + memcpy(out_buf, bdata + s, cnt); + bs++; + num_read += cnt; + out_buf += cnt; + s = 0; + } + *out_num_read = num_read; + ret = AVB_IO_RESULT_OK; +#ifdef AVB_VVDEBUG + printf("\nnum_read=%zu", num_read); + printf("\n----dump---\n"); + print_buffer(0, buffer, HEXDUMP_WIDTH, num_read, 0); + printf("--- end ---\n"); +#endif + +fail: + free(bdata); + return ret; +} + +/* multi block read version of read_from_partition */ + AvbIOResult fsl_read_from_partition_multi(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read) +{ + struct fastboot_ptentry *pte; + unsigned char *bdata; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned char *dst, *dst64 = NULL; + unsigned long blksz; + unsigned long s, cnt; + size_t num_read = 0; + lbaint_t part_start, part_end, bs, be, bm, blk_num; + margin_pos_t margin; + + AvbIOResult ret; + + DEBUGAVB("[%s]: offset=%ld, num_bytes=%zu\n", partition, (long)offset, num_bytes); + + assert(buffer != NULL && out_num_read != NULL); + + if ((fs_dev_desc = get_mmc_desc()) == NULL) { + ERR("mmc device not found\n"); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + blksz = fs_dev_desc->blksz; + part_start = pte->start; + part_end = pte->start + pte->length - 1; + VDEBUG("blksz: %ld, part_end: %ld, part_start: %ld:\n", + blksz, part_end, part_start); + + if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, true)) + return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION; + + bs = (lbaint_t)margin.blk_start; + be = (lbaint_t)margin.blk_end; + s = margin.start; + bm = margin.multi; + + // alloc a blksz mem + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) + return AVB_IO_RESULT_ERROR_OOM; + + // support multi blk read + while (bs <= be) { + if (!s && bm > 1) { + dst = out_buf; + dst64 = PTR_ALIGN(out_buf, 64); //for mmc blk read alignment + VDEBUG("cur: dst=0x%08x, dst64=0x%08x\n", dst, dst64); + if (dst64 != dst) { + dst = dst64; + bm--; + } + blk_num = bm; + cnt = bm * blksz; + bm = 0; //no more multi blk + } else { + blk_num = 1; + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + dst = bdata; + } + VDEBUG("cur: bs=%ld, num=%ld, start=%ld, cnt=%ld dst=0x%08x\n", + bs, blk_num, s, cnt, dst); + if (blk_dread(fs_dev_desc, bs, blk_num, dst) != blk_num) { + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + + if (dst == bdata) + memcpy(out_buf, bdata + s, cnt); + else if (dst == dst64) + memcpy(out_buf, dst, cnt); //internal copy + + s = 0; + bs += blk_num; + num_read += cnt; + out_buf += cnt; +#ifdef AVB_VVDEBUG + printf("\nnum_read=%ld", cnt); + printf("\n----dump---\n"); + print_buffer(0, buffer, HEXDUMP_WIDTH, cnt, 0); + printf("--- end ---\n"); +#endif + } + *out_num_read = num_read; + ret = AVB_IO_RESULT_OK; +#ifdef AVB_VVDEBUG + printf("\nnum_read=%zu", num_read); + printf("\n----dump---\n"); + print_buffer(0, buffer, HEXDUMP_WIDTH, num_read, 0); + printf("--- end ---\n"); +#endif + +fail: + free(bdata); + return ret; +} + + /* Writes |num_bytes| from |bffer| at offset |offset| to partition + * with name |partition| (NUL-terminated UTF-8 string). If |offset| + * is negative, its absolute value should be interpreted as the + * number of bytes from the end of the partition. + * + * This function returns AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION if + * there is no partition with the given name, + * AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION if the requested + * byterange goes outside the partition, and AVB_IO_RESULT_ERROR_IO + * if there was an I/O error from the underlying I/O subsystem. If + * the operation succeeds as requested AVB_IO_RESULT_OK is + * returned. + * + * This function never does any partial I/O, it either transfers all + * of the requested bytes or returns an error. + */ + AvbIOResult fsl_write_to_partition(AvbOps* ops, const char* partition, + int64_t offset, size_t num_bytes, + const void* buffer) +{ + struct fastboot_ptentry *pte; + unsigned char *bdata; + unsigned char *in_buf = (unsigned char *)buffer; + unsigned long blksz; + unsigned long s, cnt; + size_t num_write = 0; + lbaint_t part_start, part_end, bs; + margin_pos_t margin; + + AvbIOResult ret; + + DEBUGAVB("[%s]: offset=%ld, num_bytes=%zu\n", partition, (long)offset, num_bytes); + + assert(buffer != NULL); + + if ((fs_dev_desc = get_mmc_desc()) == NULL) { + ERR("mmc device not found\n"); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + + blksz = fs_dev_desc->blksz; + part_start = pte->start; + part_end = pte->start + pte->length - 1; + VDEBUG("blksz: %ld, part_end: %ld, part_start: %ld:\n", + blksz, part_end, part_start); + + if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, false)) + return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION; + + bs = (lbaint_t)margin.blk_start; + s = margin.start; + + // alloc a blksz mem + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) + return AVB_IO_RESULT_ERROR_OOM; + + while (num_write < num_bytes) { + memset(bdata, 0, blksz); + cnt = blksz - s; + if (num_write + cnt > num_bytes) + cnt = num_bytes - num_write; + if (!s || cnt != blksz) { //read blk first + if (blk_dread(fs_dev_desc, bs, 1, bdata) != 1) { + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + } + memcpy(bdata + s, in_buf, cnt); //change data + VDEBUG("cur: bs=%ld, start=%ld, cnt=%ld bdata=0x%08x\n", + bs, s, cnt, bdata); + if (blk_dwrite(fs_dev_desc, bs, 1, bdata) != 1) { + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + bs++; + num_write += cnt; + in_buf += cnt; + if (s != 0) + s = 0; + } + ret = AVB_IO_RESULT_OK; + +fail: + free(bdata); + return ret; +} + +/* Gets whether the device is unlocked. The value is returned in + * |out_is_unlocked| (true if unlocked, false otherwise). Returns + * AVB_IO_RESULT_OK if the state was retrieved, otherwise an error + * code. + */ +AvbIOResult fsl_read_is_device_unlocked(AvbOps* ops, bool* out_is_unlocked) { + + FbLockState status; + + assert(out_is_unlocked != NULL); + *out_is_unlocked = false; + + status = fastboot_get_lock_stat(); + if (status != FASTBOOT_LOCK_ERROR) { + if (status == FASTBOOT_LOCK) + *out_is_unlocked = false; + else + *out_is_unlocked = true; + } else + return AVB_IO_RESULT_ERROR_IO; + + DEBUGAVB("is_unlocked=%d\n", *out_is_unlocked); + return AVB_IO_RESULT_OK; +} + +/* Gets the unique partition GUID for a partition with name in + * |partition| (NUL-terminated UTF-8 string). The GUID is copied as + * a string into |guid_buf| of size |guid_buf_size| and will be NUL + * terminated. The string must be lower-case and properly + * hyphenated. For example: + * + * 527c1c6d-6361-4593-8842-3c78fcd39219 + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_unique_guid_for_partition(AvbOps* ops, + const char* partition, + char* guid_buf, + size_t guid_buf_size) { + assert(guid_buf != NULL); +#ifdef CONFIG_PARTITION_UUIDS + struct fastboot_ptentry *pte; + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + strncpy(guid_buf, (const char *)pte->uuid, guid_buf_size); + guid_buf[guid_buf_size - 1] = '\0'; + DEBUGAVB("[%s]: GUID=%s\n", partition, guid_buf); + return AVB_IO_RESULT_OK; +#else + return AVB_IO_RESULT_ERROR_IO; +#endif + +} +/* Gets the size of a partition with the name in |partition| + * (NUL-terminated UTF-8 string). Returns the value in + * |out_size_num_bytes|. + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_size_of_partition(AvbOps* ops, + const char* partition, + uint64_t* out_size_num_bytes) +{ + struct fastboot_ptentry *pte; + pte = fastboot_flash_find_ptn(partition); + if (!pte) { + ERR("no %s partition\n", partition); + fastboot_flash_dump_ptn(); + return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION; + } + *out_size_num_bytes = (uint64_t)(pte->length) * 512; + return AVB_IO_RESULT_OK; +} + +#ifdef CONFIG_AVB_ATX +/* Reads permanent |attributes| data. There are no restrictions on where this + * data is stored. On success, returns AVB_IO_RESULT_OK and populates + * |attributes|. + */ +AvbIOResult fsl_read_permanent_attributes( + AvbAtxOps* atx_ops, AvbAtxPermanentAttributes* attributes) { +#ifdef CONFIG_IMX_TRUSTY_OS + if (!trusty_read_permanent_attributes((uint8_t *)attributes, + sizeof(AvbAtxPermanentAttributes))) { + return AVB_IO_RESULT_OK; + } + ERR("No perm-attr fused. Will use hard code one.\n"); +#endif /* CONFIG_IMX_TRUSTY_OS */ + + /* use hard code permanent attributes due to limited fuse and RPMB */ + attributes->version = fsl_version; + memcpy(attributes->product_root_public_key, fsl_product_root_public_key, + sizeof(fsl_product_root_public_key)); + memcpy(attributes->product_id, fsl_atx_product_id, + sizeof(fsl_atx_product_id)); + + return AVB_IO_RESULT_OK; +} + +/* Reads a |hash| of permanent attributes. This hash MUST be retrieved from a + * permanently read-only location (e.g. fuses) when a device is LOCKED. On + * success, returned AVB_IO_RESULT_OK and populates |hash|. + */ +AvbIOResult fsl_read_permanent_attributes_hash( + AvbAtxOps* atx_ops, uint8_t hash[AVB_SHA256_DIGEST_SIZE]) { +#ifdef CONFIG_ARM64 + /* calculate sha256(permanent attributes) */ + if (permanent_attributes_sha256_hash(hash) != RESULT_OK) { + return AVB_IO_RESULT_ERROR_IO; + } else { + return AVB_IO_RESULT_OK; + } +#else + uint8_t sha256_hash_buf[AVB_SHA256_DIGEST_SIZE]; + uint32_t sha256_hash_fuse[ATX_FUSE_BANK_NUM]; + + /* read first 112 bits of sha256(permanent attributes) from fuse */ + if (fsl_fuse_read(sha256_hash_fuse, ATX_FUSE_BANK_NUM, + PERMANENT_ATTRIBUTE_HASH_OFFSET)) { + printf("ERROR - read permanent attributes hash from " + "fuse error\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* only take the lower 2 bytes of last bank */ + sha256_hash_fuse[ATX_FUSE_BANK_NUM - 1] &= ATX_FUSE_BANK_MASK; + + /* calculate sha256(permanent attributes) */ + if (permanent_attributes_sha256_hash(sha256_hash_buf) != RESULT_OK) { + return AVB_IO_RESULT_ERROR_IO; + } + /* check if the sha256(permanent attributes) hash match the calculated one, + * if not match, just return all zeros hash. + */ + if (memcmp(sha256_hash_fuse, sha256_hash_buf, ATX_HASH_LENGTH)) { + printf("ERROR - sha256(permanent attributes) does not match\n"); + memset(hash, 0, AVB_SHA256_DIGEST_SIZE); + } else { + memcpy(hash, sha256_hash_buf, AVB_SHA256_DIGEST_SIZE); + } + + return AVB_IO_RESULT_OK; +#endif /* CONFIG_ARM64 */ +} + + /* Generates |num_bytes| random bytes and stores them in |output|, + * which must point to a buffer large enough to store the bytes. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ +AvbIOResult fsl_get_random(AvbAtxOps* atx_ops, + size_t num_bytes, + uint8_t* output) +{ + uint32_t num = 0; + uint32_t i; + + if (output == NULL) { + ERR("Output buffer is NULL!\n"); + return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE; + } + + /* set the seed as device boot time. */ + srand((uint32_t)get_timer(0)); + for (i = 0; i < num_bytes; i++) { + num = rand() % 256; + output[i] = (uint8_t)num; + } + + return AVB_IO_RESULT_OK; +} +/* Provides the key version of a key used during verification. This may be + * useful for managing the minimum key version. + */ +void fsl_set_key_version(AvbAtxOps* atx_ops, + size_t rollback_index_location, + uint64_t key_version) { + kblb_hdr_t hdr; + kblb_tag_t *rbk; + uint64_t *plain_idx = NULL; + struct mmc *mmc_dev; + static const uint32_t kTypeMask = 0xF000; + + DEBUGAVB("[rpmb] write to rollback slot: (%zu, %" PRIu64 ")\n", + rollback_index_location, key_version); + + assert(atx_ops != NULL); + + if ((mmc_dev = get_mmc()) == NULL) { + ERR("err get mmc device\n"); + } + /* read the kblb header */ + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("read RPMB error\n"); + } + + if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) { + ERR("magic not match\n"); + } + + /* rollback index for Android Things key versions */ + rbk = &hdr.atx_rbk_tags[rollback_index_location & ~kTypeMask]; + + plain_idx = malloc(rbk->len); + if (plain_idx == NULL) + printf("\nError! allocate memory fail!\n"); + memset(plain_idx, 0, rbk->len); + *plain_idx = key_version; + + /* write rollback_index keyblob */ + if (rpmb_write(mmc_dev, (uint8_t *)plain_idx, rbk->len, rbk->offset) != + 0) { + ERR("write rollback index error\n"); + goto fail; + } +fail: + if (plain_idx != NULL) + free(plain_idx); +} +#endif /* CONFIG_AVB_ATX */ + +#ifdef AVB_RPMB +/* Checks if the given public key used to sign the 'vbmeta' + * partition is trusted. Boot loaders typically compare this with + * embedded key material generated with 'avbtool + * extract_public_key'. + * + * If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set - + * true if trusted or false if untrusted. + */ +AvbIOResult fsl_validate_vbmeta_public_key_rpmb(AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted) { + AvbIOResult ret; + assert(ops != NULL && out_is_trusted != NULL); + *out_is_trusted = false; + +#ifdef CONFIG_LOAD_KEY_FROM_RPMB + uint8_t public_key_buf[AVB_MAX_BUFFER_LENGTH]; + if (trusty_read_vbmeta_public_key(public_key_buf, + public_key_length) != 0) { + ERR("Read public key error\n"); + /* We're not going to return error code here because it will + * abort the following avb verify process even we allow the + * verification error. Return AVB_IO_RESULT_OK and keep the + * 'out_is_trusted' as false, avb will handle the error + * depends on the 'allow_verification_error' flag. + */ + return AVB_IO_RESULT_OK; + } + + if (memcmp(public_key_buf, public_key_data, public_key_length)) { +#else + /* match given public key */ + if (memcmp(fsl_public_key, public_key_data, public_key_length)) { +#endif + ERR("public key not match\n"); + return AVB_IO_RESULT_OK; + } + + *out_is_trusted = true; + ret = AVB_IO_RESULT_OK; + + return ret; +} + +/* Sets the rollback index corresponding to the slot given by + * |rollback_index_slot| to |rollback_index|. Returns + * AVB_IO_RESULT_OK if the rollback index was set, otherwise an + * error code. + * + * A device may have a limited amount of rollback index slots (say, + * one or four) so may error out if |rollback_index_slot| exceeds + * this number. + */ +AvbIOResult fsl_write_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t rollback_index) { + AvbIOResult ret; +#ifdef CONFIG_IMX_TRUSTY_OS + if (trusty_write_rollback_index(rollback_index_slot, rollback_index)) { + ERR("write rollback from Trusty error!\n"); +#ifndef CONFIG_AVB_ATX + /* Read/write rollback index from rpmb will fail if the rpmb + * key hasn't been set, return AVB_IO_RESULT_OK in this case. + */ + if (!rpmbkey_is_set()) + ret = AVB_IO_RESULT_OK; + else +#endif + ret = AVB_IO_RESULT_ERROR_IO; + } else { + ret = AVB_IO_RESULT_OK; + } + return ret; +#else + kblb_hdr_t hdr; + kblb_tag_t *rbk; + uint64_t *plain_idx = NULL; + struct mmc *mmc_dev; +#ifdef CONFIG_AVB_ATX + static const uint32_t kTypeMask = 0xF000; + static const unsigned int kTypeShift = 12; +#endif + + DEBUGAVB("[rpmb] write to rollback slot: (%zu, %" PRIu64 ")\n", + rollback_index_slot, rollback_index); + + assert(ops != NULL); + /* check if the rollback index location exceed the limit */ +#ifdef CONFIG_AVB_ATX + if ((rollback_index_slot & ~kTypeMask) >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) +#else + if (rollback_index_slot >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) +#endif /* CONFIG_AVB_ATX */ + return AVB_IO_RESULT_ERROR_IO; + + if ((mmc_dev = get_mmc()) == NULL) { + ERR("err get mmc device\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* read the kblb header */ + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("read RPMB error\n"); + return AVB_IO_RESULT_ERROR_IO; + } + + if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) { + ERR("magic not match\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* choose rollback index type */ +#ifdef CONFIG_AVB_ATX + if ((rollback_index_slot & kTypeMask) >> kTypeShift) { + /* rollback index for Android Things key versions */ + rbk = &hdr.atx_rbk_tags[rollback_index_slot & ~kTypeMask]; + } else { + /* rollback index for vbmeta */ + rbk = &hdr.rbk_tags[rollback_index_slot & ~kTypeMask]; + } +#else + rbk = &hdr.rbk_tags[rollback_index_slot]; +#endif /* CONFIG_AVB_ATX */ + plain_idx = malloc(rbk->len); + if (plain_idx == NULL) + return AVB_IO_RESULT_ERROR_OOM; + memset(plain_idx, 0, rbk->len); + *plain_idx = rollback_index; + + /* write rollback_index keyblob */ + if (rpmb_write(mmc_dev, (uint8_t *)plain_idx, rbk->len, rbk->offset) != + 0) { + ERR("write rollback index error\n"); + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + ret = AVB_IO_RESULT_OK; +fail: + if (plain_idx != NULL) + free(plain_idx); + return ret; +#endif /* CONFIG_IMX_TRUSTY_OS */ +} + +/* Gets the rollback index corresponding to the slot given by + * |rollback_index_slot|. The value is returned in + * |out_rollback_index|. Returns AVB_IO_RESULT_OK if the rollback + * index was retrieved, otherwise an error code. + * + * A device may have a limited amount of rollback index slots (say, + * one or four) so may error out if |rollback_index_slot| exceeds + * this number. + */ +AvbIOResult fsl_read_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t* out_rollback_index) { + AvbIOResult ret; +#ifdef CONFIG_IMX_TRUSTY_OS + if (trusty_read_rollback_index(rollback_index_slot, out_rollback_index)) { + ERR("read rollback from Trusty error!\n"); +#ifndef CONFIG_AVB_ATX + if (!rpmbkey_is_set()) { + *out_rollback_index = 0; + ret = AVB_IO_RESULT_OK; + } else +#endif + ret = AVB_IO_RESULT_ERROR_IO; + } else { + ret = AVB_IO_RESULT_OK; + } + return ret; +#else + kblb_hdr_t hdr; + kblb_tag_t *rbk; + uint64_t *extract_idx = NULL; + struct mmc *mmc_dev; +#ifdef CONFIG_AVB_ATX + static const uint32_t kTypeMask = 0xF000; + static const unsigned int kTypeShift = 12; +#endif + + assert(ops != NULL && out_rollback_index != NULL); + *out_rollback_index = ~0; + + DEBUGAVB("[rpmb] read rollback slot: %zu\n", rollback_index_slot); + + /* check if the rollback index location exceed the limit */ +#ifdef CONFIG_AVB_ATX + if ((rollback_index_slot & ~kTypeMask) >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) +#else + if (rollback_index_slot >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) +#endif + return AVB_IO_RESULT_ERROR_IO; + + if ((mmc_dev = get_mmc()) == NULL) { + ERR("err get mmc device\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* read the kblb header */ + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("read RPMB error\n"); + return AVB_IO_RESULT_ERROR_IO; + } + + if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) { + ERR("magic not match\n"); + return AVB_IO_RESULT_ERROR_IO; + } + /* choose rollback index type */ +#ifdef CONFIG_AVB_ATX + if ((rollback_index_slot & kTypeMask) >> kTypeShift) { + /* rollback index for Android Things key versions */ + rbk = &hdr.atx_rbk_tags[rollback_index_slot & ~kTypeMask]; + } else { + /* rollback index for vbmeta */ + rbk = &hdr.rbk_tags[rollback_index_slot & ~kTypeMask]; + } +#else + rbk = &hdr.rbk_tags[rollback_index_slot]; +#endif /* CONFIG_AVB_ATX */ + extract_idx = malloc(rbk->len); + if (extract_idx == NULL) + return AVB_IO_RESULT_ERROR_OOM; + + /* read rollback_index keyblob */ + if (rpmb_read(mmc_dev, (uint8_t *)extract_idx, rbk->len, rbk->offset) != 0) { + ERR("read rollback index error\n"); + ret = AVB_IO_RESULT_ERROR_IO; + goto fail; + } + +#ifdef AVB_VVDEBUG + printf("\n----idx dump: ---\n"); + print_buffer(0, extract_idx, HEXDUMP_WIDTH, rbk->len, 0); + printf("--- end ---\n"); +#endif + *out_rollback_index = *extract_idx; + DEBUGAVB("rollback_index = %" PRIu64 "\n", *out_rollback_index); + ret = AVB_IO_RESULT_OK; +fail: + if (extract_idx != NULL) + free(extract_idx); + return ret; +#endif /* CONFIG_IMX_TRUSTY_OS */ +} +#else /* AVB_RPMB */ +AvbIOResult fsl_validate_vbmeta_public_key_rpmb(AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted) { + assert(ops != NULL && out_is_trusted != NULL); + + /* match given public key */ + if (memcmp(fsl_public_key, public_key_data, public_key_length)) { + ERR("public key not match\n"); + *out_is_trusted = false; + } else + *out_is_trusted = true; + + /* We're not going to return error code when public key + * verify fail because it will abort the following avb + * verify process even we allow the verification error. + * Return AVB_IO_RESULT_OK and keep the 'out_is_trusted' + * as false, avb will handle the error depends on the + * 'allow_verification_error' flag. + */ + return AVB_IO_RESULT_OK; +} + +/* In no security enhanced ARM64, rollback index has no protection so no use it */ +AvbIOResult fsl_write_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t rollback_index) { + return AVB_IO_RESULT_OK; + +} +AvbIOResult fsl_read_rollback_index_rpmb(AvbOps* ops, size_t rollback_index_slot, + uint64_t* out_rollback_index) { + *out_rollback_index = 0; + return AVB_IO_RESULT_OK; +} +#endif /* AVB_RPMB */ diff --git a/lib/avb/fsl/fsl_avbkey.c b/lib/avb/fsl/fsl_avbkey.c new file mode 100644 index 00000000000..e4ddbbbaefa --- /dev/null +++ b/lib/avb/fsl/fsl_avbkey.c @@ -0,0 +1,1349 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017-2019 NXP + * SPDX-License-Identifier: GPL-2.0+ + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "trusty/avb.h" +#ifdef CONFIG_IMX_TRUSTY_OS +#include +#endif +#include "fsl_avbkey.h" +#include "utils.h" +#include "debug.h" +#include +#include "trusty/hwcrypto.h" +#include "trusty/rpmb.h" +#include "fsl_atx_attributes.h" +#include +#include +#ifdef CONFIG_ARCH_IMX8 +#include +#endif + +#ifdef CONFIG_SPL_BUILD +#include +#endif + +#define INITFLAG_FUSE_OFFSET 0 +#define INITFLAG_FUSE_MASK 0x00000001 +#define INITFLAG_FUSE 0x00000001 + +#define RPMB_BLKSZ 256 +#define RPMBKEY_LENGTH 32 +#define RPMBKEY_BLOB_LEN ((RPMBKEY_LENGTH) + (CAAM_PAD)) + +extern int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value); + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC_SUPPORT) +int spl_get_mmc_dev(void) +{ + u32 dev_no = spl_boot_device(); + switch (dev_no) { + case BOOT_DEVICE_MMC1: + return 0; + case BOOT_DEVICE_MMC2: + case BOOT_DEVICE_MMC2_2: + return 1; + } + +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT + printf("spl: unsupported mmc boot device.\n"); +#endif + + return -ENODEV; +} +#endif + +#ifdef AVB_RPMB +static u8 skeymod[] = { + 0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, + 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00 +}; + +struct mmc *get_mmc(void) { + int mmc_dev_no; + struct mmc *mmc; +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC_SUPPORT) + mmc_dev_no = spl_get_mmc_dev(); +#else + mmc_dev_no = mmc_get_env_dev(); +#endif + mmc = find_mmc_device(mmc_dev_no); + if (!mmc || mmc_init(mmc)) + return NULL; + return mmc; +} + +void fill_secure_keyslot_package(struct keyslot_package *kp) { + + memcpy((void*)CAAM_ARB_BASE_ADDR, kp, sizeof(struct keyslot_package)); + + /* invalidate the cache to make sure no critical information left in it */ + memset(kp, 0, sizeof(struct keyslot_package)); + invalidate_dcache_range(((ulong)kp) & 0xffffffc0,(((((ulong)kp) + + sizeof(struct keyslot_package)) & 0xffffff00) + + 0x100)); +} + +int read_keyslot_package(struct keyslot_package* kp) { + char original_part; + int blksz; + unsigned char* fill = NULL; + int ret = 0; + /* load tee from boot1 of eMMC. */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC_SUPPORT) + int mmcc = spl_get_mmc_dev(); +#else + int mmcc = mmc_get_env_dev(); +#endif + struct blk_desc *dev_desc = NULL; + + struct mmc *mmc; +#ifdef CONFIG_IMX8_TRUSTY_XEN + mmcc = 0; +#endif + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("boota: cannot find '%d' mmc device\n", mmcc); + return -1; + } +#if !CONFIG_IS_ENABLED(BLK) + original_part = mmc->block_dev.hwpart; + dev_desc = blk_get_dev("mmc", mmcc); +#else + dev_desc = mmc_get_blk_desc(mmc); +#endif + if (NULL == dev_desc) { + printf("** Block device MMC %d not supported\n", mmcc); + return -1; + } +#if CONFIG_IS_ENABLED(BLK) + original_part = dev_desc->hwpart; +#endif + + blksz = dev_desc->blksz; + fill = (unsigned char *)memalign(ALIGN_BYTES, blksz); + + /* below was i.MX mmc operation code */ + if (mmc_init(mmc)) { + printf("mmc%d init failed\n", mmcc); + ret = -1; + goto fail;; + } + + if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) { + ret = -1; + goto fail; + } +#if !CONFIG_IS_ENABLED(BLK) + mmc->block_dev.hwpart = KEYSLOT_HWPARTITION_ID; +#else + dev_desc->hwpart = KEYSLOT_HWPARTITION_ID; +#endif + if (blk_dread(dev_desc, KEYSLOT_BLKS, + 1, fill) != 1) { + printf("Failed to read rpmbkeyblob."); + ret = -1; + goto fail; + } else { + memcpy(kp, fill, sizeof(struct keyslot_package)); + } + +fail: + /* Free allocated memory. */ + if (fill != NULL) + free(fill); + /* Return to original partition */ +#if !CONFIG_IS_ENABLED(BLK) + if (mmc->block_dev.hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + return -1; + mmc->block_dev.hwpart = original_part; + } +#else + if (dev_desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + return -1; + dev_desc->hwpart = original_part; + } +#endif + return ret; +} + +bool rpmbkey_is_set(void) +{ + int mmcc; + bool ret; + uint8_t *buf; + struct mmc *mmc; + char original_part; + struct blk_desc *desc = NULL; + + /* Get current mmc device. */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC_SUPPORT) + mmcc = spl_get_mmc_dev(); +#else + mmcc = mmc_get_env_dev(); +#endif + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("error - cannot find '%d' mmc device\n", mmcc); + return false; + } + +#if !CONFIG_IS_ENABLED(BLK) + original_part = mmc->block_dev.hwpart; + desc = blk_get_dev("mmc", mmcc); +#else + desc = mmc_get_blk_desc(mmc); + original_part = desc->hwpart; +#endif + + /* Switch to the RPMB partition */ +#if !CONFIG_IS_ENABLED(BLK) + if (mmc->block_dev.hwpart != MMC_PART_RPMB) { +#else + if (desc->hwpart != MMC_PART_RPMB) { +#endif + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) { + printf("ERROR - can't switch to rpmb partition \n"); + return false; + } +#if !CONFIG_IS_ENABLED(BLK) + mmc->block_dev.hwpart = MMC_PART_RPMB; +#else + desc->hwpart = MMC_PART_RPMB; +#endif + } + + /* Try to read the first one block, return count '1' means the rpmb + * key has been set, otherwise means the key hasn't been set. + */ + buf = (uint8_t *)memalign(ALIGN_BYTES, desc->blksz); + if (mmc_rpmb_read(mmc, buf, 0, 1, NULL) != 1) + ret = false; + else + ret = true; + + /* return to original partition. */ +#if !CONFIG_IS_ENABLED(BLK) + if (mmc->block_dev.hwpart != original_part) { +#else + if (desc->hwpart != original_part) { +#endif + if (mmc_switch_part(mmc, original_part) != 0) + ret = false; +#if !CONFIG_IS_ENABLED(BLK) + mmc->block_dev.hwpart = original_part; +#else + desc->hwpart = original_part; +#endif + } + /* remember to free the buffer */ + if (buf != NULL) + free(buf); + + return ret; +} + +int rpmb_read(struct mmc *mmc, uint8_t *buffer, size_t num_bytes, int64_t offset) { + + unsigned char *bdata = NULL; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned long s, cnt; + unsigned long blksz; + size_t num_read = 0; + unsigned short part_start, part_length, part_end, bs, be; + margin_pos_t margin; + char original_part; + uint8_t *blob = NULL, *keymod = NULL; + struct blk_desc *desc = mmc_get_blk_desc(mmc); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, extract_key, RPMBKEY_LENGTH); + + struct keyslot_package kp; + int ret; + + blksz = RPMB_BLKSZ; + part_length = mmc->capacity_rpmb >> 8; + part_start = 0; + part_end = part_start + part_length - 1; + + DEBUGAVB("[rpmb]: offset=%ld, num_bytes=%zu\n", (long)offset, num_bytes); + + if(get_margin_pos(part_start, part_end, blksz, + &margin, offset, num_bytes, false)) + return -1; + + bs = (unsigned short)margin.blk_start; + be = (unsigned short)margin.blk_end; + s = margin.start; + + /* Switch to the RPMB partition */ + original_part = desc->hwpart; + if (desc->hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) + return -1; + desc->hwpart = MMC_PART_RPMB; + } + + /* get rpmb key */ + blob = (uint8_t *)memalign(ARCH_DMA_MINALIGN, RPMBKEY_BLOB_LEN); + keymod = (uint8_t *)memalign(ARCH_DMA_MINALIGN, sizeof(skeymod)); + memcpy(keymod, skeymod, sizeof(skeymod)); + if (read_keyslot_package(&kp)) { + ERR("read rpmb key error\n"); + ret = -1; + goto fail; + } + + if (!strcmp(kp.magic, KEYPACK_MAGIC)) { + /* Use the key from keyslot. */ + memcpy(blob, kp.rpmb_keyblob, RPMBKEY_BLOB_LEN); + if (blob_decap(keymod, blob, extract_key, RPMBKEY_LENGTH)) { + ERR("decap rpmb key error\n"); + ret = -1; + goto fail; + } + } else if (derive_blob_kek(extract_key, keymod, RPMBKEY_LENGTH)) { + ERR("get rpmb key error\n"); + ret = -1; + goto fail; + } + + /* alloc a blksz mem */ + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) { + ret = -1; + goto fail; + } + /* one block a time */ + while (bs <= be) { + memset(bdata, 0, blksz); + if (mmc_rpmb_read(mmc, bdata, bs, 1, extract_key) != 1) { + ret = -1; + goto fail; + } + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + VDEBUG("cur: bs=%d, start=%ld, cnt=%ld bdata=0x%p\n", + bs, s, cnt, bdata); + memcpy(out_buf, bdata + s, cnt); + bs++; + num_read += cnt; + out_buf += cnt; + s = 0; + } + memset(extract_key, 0, RPMBKEY_LENGTH); + ret = 0; + +fail: + /* Return to original partition */ + if (desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + ret = -1; + else + desc->hwpart = original_part; + } + if (blob != NULL) + free(blob); + if (keymod != NULL) + free(keymod); + if (bdata != NULL) + free(bdata); + return ret; + +} + +int rpmb_write(struct mmc *mmc, uint8_t *buffer, size_t num_bytes, int64_t offset) { + + unsigned char *bdata = NULL; + unsigned char *in_buf = (unsigned char *)buffer; + unsigned long s, cnt; + unsigned long blksz; + size_t num_write = 0; + unsigned short part_start, part_length, part_end, bs; + margin_pos_t margin; + char original_part; + uint8_t *blob = NULL, *keymod = NULL; + struct blk_desc *desc = mmc_get_blk_desc(mmc); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, extract_key, RPMBKEY_LENGTH); + + struct keyslot_package kp; + int ret; + + blksz = RPMB_BLKSZ; + part_length = mmc->capacity_rpmb >> 8; + part_start = 0; + part_end = part_start + part_length - 1; + + DEBUGAVB("[rpmb]: offset=%ld, num_bytes=%zu\n", (long)offset, num_bytes); + + if(get_margin_pos(part_start, part_end, blksz, + &margin, offset, num_bytes, false)) { + ERR("get_margin_pos err\n"); + return -1; + } + + bs = (unsigned short)margin.blk_start; + s = margin.start; + + /* Switch to the RPMB partition */ + original_part = desc->hwpart; + if (desc->hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) + return -1; + desc->hwpart = MMC_PART_RPMB; + } + + /* get rpmb key */ + blob = (uint8_t *)memalign(ARCH_DMA_MINALIGN, RPMBKEY_BLOB_LEN); + keymod = (uint8_t *)memalign(ARCH_DMA_MINALIGN, sizeof(skeymod)); + memcpy(keymod, skeymod, sizeof(skeymod)); + if (read_keyslot_package(&kp)) { + ERR("read rpmb key error\n"); + ret = -1; + goto fail; + } + if (!strcmp(kp.magic, KEYPACK_MAGIC)) { + /* Use the key from keyslot. */ + memcpy(blob, kp.rpmb_keyblob, RPMBKEY_BLOB_LEN); + if (blob_decap(keymod, blob, extract_key, RPMBKEY_LENGTH)) { + ERR("decap rpmb key error\n"); + ret = -1; + goto fail; + } + } else if (derive_blob_kek(extract_key, keymod, RPMBKEY_LENGTH)) { + ERR("get rpmb key error\n"); + ret = -1; + goto fail; + } + /* alloc a blksz mem */ + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) { + ret = -1; + goto fail; + } + while (num_write < num_bytes) { + memset(bdata, 0, blksz); + cnt = blksz - s; + if (num_write + cnt > num_bytes) + cnt = num_bytes - num_write; + if (!s || cnt != blksz) { /* read blk first */ + if (mmc_rpmb_read(mmc, bdata, bs, 1, extract_key) != 1) { + ERR("mmc_rpmb_read err, mmc= 0x%08x\n", (uint32_t)(ulong)mmc); + ret = -1; + goto fail; + } + } + memcpy(bdata + s, in_buf, cnt); /* change data */ + VDEBUG("cur: bs=%d, start=%ld, cnt=%ld\n", bs, s, cnt); + if (mmc_rpmb_write(mmc, bdata, bs, 1, extract_key) != 1) { + ret = -1; + goto fail; + } + bs++; + num_write += cnt; + in_buf += cnt; + if (s != 0) + s = 0; + } + memset(extract_key, 0, RPMBKEY_LENGTH); + ret = 0; + +fail: + /* Return to original partition */ + if (desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + ret = -1; + else + desc->hwpart = original_part; + } + if (blob != NULL) + free(blob); + if (keymod != NULL) + free(keymod); + if (bdata != NULL) + free(bdata); + + return ret; + +} + +int rpmb_init(void) { +#if !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DUAL_BOOTLOADER) + int i; +#endif + kblb_hdr_t hdr; + kblb_tag_t *tag; + struct mmc *mmc_dev; + uint32_t offset; + uint32_t rbidx_len; + uint8_t *rbidx; + + /* check init status first */ + if ((mmc_dev = get_mmc()) == NULL) { + ERR("ERROR - get mmc device\n"); + return -1; + } + /* The bootloader rollback index is stored in the last 8k bytes of + * RPMB which is different from the rollback index for vbmeta and + * ATX key versions. + */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), + BOOTLOADER_RBIDX_OFFSET) != 0) { +#else + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { +#endif + ERR("read RPMB error\n"); + return -1; + } + if (!memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN)) + return 0; + else + printf("initialize rollback index...\n"); + /* init rollback index */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) + offset = BOOTLOADER_RBIDX_START; + rbidx_len = BOOTLOADER_RBIDX_LEN; + rbidx = malloc(rbidx_len); + if (rbidx == NULL) { + ERR("failed to allocate memory!\n"); + return -1; + } + memset(rbidx, 0, rbidx_len); + *(uint64_t *)rbidx = BOOTLOADER_RBIDX_INITVAL; + tag = &hdr.bootloader_rbk_tags; + tag->offset = offset; + tag->len = rbidx_len; + if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) { + ERR("write RBKIDX RPMB error\n"); + free(rbidx); + return -1; + } + if (rbidx != NULL) + free(rbidx); +#else /* CONFIG_SPL_BUILD && CONFIG_DUAL_BOOTLOADER */ + offset = AVB_RBIDX_START; + rbidx_len = AVB_RBIDX_LEN; + rbidx = malloc(rbidx_len); + if (rbidx == NULL) + return -1; + memset(rbidx, 0, rbidx_len); + *(uint64_t *)rbidx = AVB_RBIDX_INITVAL; + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) { + tag = &hdr.rbk_tags[i]; + tag->flag = AVB_RBIDX_FLAG; + tag->offset = offset; + tag->len = rbidx_len; + if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) { + ERR("write RBKIDX RPMB error\n"); + free(rbidx); + return -1; + } + offset += AVB_RBIDX_ALIGN; + } + if (rbidx != NULL) + free(rbidx); +#ifdef CONFIG_AVB_ATX + /* init rollback index for Android Things key versions */ + offset = ATX_RBIDX_START; + rbidx_len = ATX_RBIDX_LEN; + rbidx = malloc(rbidx_len); + if (rbidx == NULL) + return -1; + memset(rbidx, 0, rbidx_len); + *(uint64_t *)rbidx = ATX_RBIDX_INITVAL; + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) { + tag = &hdr.atx_rbk_tags[i]; + tag->flag = ATX_RBIDX_FLAG; + tag->offset = offset; + tag->len = rbidx_len; + if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) { + ERR("write ATX_RBKIDX RPMB error\n"); + free(rbidx); + return -1; + } + offset += ATX_RBIDX_ALIGN; + } + if (rbidx != NULL) + free(rbidx); +#endif +#endif /* CONFIG_SPL_BUILD && CONFIG_DUAL_BOOTLOADER */ + + /* init hdr */ + memcpy(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN); +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_DUAL_BOOTLOADER) + if (rpmb_write(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), + BOOTLOADER_RBIDX_OFFSET) != 0) { +#else + if (rpmb_write(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { +#endif + ERR("write RPMB hdr error\n"); + return -1; + } + + return 0; +} + +int gen_rpmb_key(struct keyslot_package *kp) { + char original_part; + unsigned char* fill = NULL; + int blksz; + uint8_t *keymod = NULL; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, plain_key, RPMBKEY_LENGTH); + + kp->rpmb_keyblob_len = RPMBKEY_LEN; + strcpy(kp->magic, KEYPACK_MAGIC); + + int ret = -1; + /* load tee from boot1 of eMMC. */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC_SUPPORT) + int mmcc = spl_get_mmc_dev(); +#else + int mmcc = mmc_get_env_dev(); +#endif + struct blk_desc *dev_desc = NULL; + + struct mmc *mmc; + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("boota: cannot find '%d' mmc device\n", mmcc); + return -1; + } +#if !CONFIG_IS_ENABLED(BLK) + original_part = mmc->block_dev.hwpart; + dev_desc = blk_get_dev("mmc", mmcc); +#else + dev_desc = mmc_get_blk_desc(mmc); + original_part = dev_desc->hwpart; +#endif + if (NULL == dev_desc) { + printf("** Block device MMC %d not supported\n", mmcc); + goto fail; + } + + blksz = dev_desc->blksz; + fill = (unsigned char *)memalign(ALIGN_BYTES, blksz); + + /* below was i.MX mmc operation code */ + if (mmc_init(mmc)) { + printf("mmc%d init failed\n", mmcc); + goto fail; + } + + /* Switch to the RPMB partition */ + +#ifdef TRUSTY_RPMB_RANDOM_KEY + /* + * Since boot1 is a bit easy to be erase during development + * so that before production stage use full 0 rpmb key + */ + if (hwrng_generate(plain_key, RPMBKEY_LENGTH)) { + ERR("ERROR - caam rng\n"); + goto fail; + } +#else + memset(plain_key, 0, RPMBKEY_LENGTH); +#endif + + keymod = (uint8_t *)memalign(ARCH_DMA_MINALIGN, sizeof(skeymod)); + memcpy(keymod, skeymod, sizeof(skeymod)); + /* generate keyblob and program to boot1 partition */ + if (blob_encap(keymod, plain_key, kp->rpmb_keyblob, RPMBKEY_LENGTH)) { + ERR("gen rpmb key blb error\n"); + goto fail; + } + memcpy(fill, kp, sizeof(struct keyslot_package)); + + if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) { + ret = -1; + goto fail; + } + + if (blk_dwrite(dev_desc, KEYSLOT_BLKS, + 1, (void *)fill) != 1) { + printf("Failed to write rpmbkeyblob."); + goto fail; + } + + /* program key to mmc */ +#if !CONFIG_IS_ENABLED(BLK) + if (mmc->block_dev.hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) { + ret = -1; + goto fail; + } else + mmc->block_dev.hwpart = MMC_PART_RPMB; + } +#else + if (dev_desc->hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) { + ret = -1; + goto fail; + } else + dev_desc->hwpart = MMC_PART_RPMB; + } +#endif + if (mmc_rpmb_set_key(mmc, plain_key)) { + ERR("Key already programmed ?\n"); + goto fail; + } + + ret = 0; + +fail: + /* Return to original partition */ +#if !CONFIG_IS_ENABLED(BLK) + if (mmc->block_dev.hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + ret = -1; + else + mmc->block_dev.hwpart = original_part; + } +#else + if (dev_desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + ret = -1; + else + dev_desc->hwpart = original_part; + } +#endif + if (fill != NULL) + free(fill); + if (keymod != NULL) + free(keymod); + + return ret; + +} + +int init_avbkey(void) { + struct keyslot_package kp; + read_keyslot_package(&kp); + if (strcmp(kp.magic, KEYPACK_MAGIC)) { + printf("keyslot package magic error. Will generate new one\n"); + memset((void *)&kp, 0, sizeof(struct keyslot_package)); + gen_rpmb_key(&kp); + } +#ifndef CONFIG_IMX_TRUSTY_OS + if (rpmb_init()) + return RESULT_ERROR; +#endif +#if defined(CONFIG_AVB_ATX) && !defined(CONFIG_IMX_TRUSTY_OS) + if (init_permanent_attributes_fuse()) + return RESULT_ERROR; +#endif + fill_secure_keyslot_package(&kp); + return RESULT_OK; +} + +#ifndef CONFIG_IMX_TRUSTY_OS +int rbkidx_erase(void) { + int i; + kblb_hdr_t hdr; + kblb_tag_t *tag; + struct mmc *mmc_dev; + + if ((mmc_dev = get_mmc()) == NULL) { + ERR("err get mmc device\n"); + return -1; + } + + /* read the kblb header */ + if (rpmb_read(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("read RPMB error\n"); + return -1; + } + if (memcmp(hdr.magic, AVB_KBLB_MAGIC, AVB_KBLB_MAGIC_LEN) != 0) { + ERR("magic not match\n"); + return -1; + } + + /* reset rollback index */ + uint32_t offset = AVB_RBIDX_START; + uint32_t rbidx_len = AVB_RBIDX_LEN; + uint8_t *rbidx = malloc(rbidx_len); + if (rbidx == NULL) + return -1; + memset(rbidx, 0, rbidx_len); + *(uint64_t *)rbidx = AVB_RBIDX_INITVAL; + for (i = 0; i < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; i++) { + tag = &hdr.rbk_tags[i]; + tag->flag = AVB_RBIDX_FLAG; + tag->offset = offset; + tag->len = rbidx_len; + /* write */ + if (rpmb_write(mmc_dev, rbidx, tag->len, tag->offset) != 0) { + ERR("write RBKIDX RPMB error\n"); + free(rbidx); + return -1; + } + offset += AVB_RBIDX_ALIGN; + } + free(rbidx); + /* write back hdr */ + if (rpmb_write(mmc_dev, (uint8_t *)&hdr, sizeof(hdr), 0) != 0) { + ERR("write RPMB hdr error\n"); + return -1; + } + return 0; +} +#endif /* CONFIG_IMX_TRUSTY_OS */ +#else /* AVB_RPMB */ +int rbkidx_erase(void) { + return 0; +} +#endif /* AVB_RPMB */ + +#ifdef CONFIG_SPL_BUILD +#if defined (CONFIG_IMX8_TRUSTY_XEN) || \ + (defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX)) +int check_rpmb_blob(struct mmc *mmc) +{ + int ret = 0; + char original_part; + struct keyslot_package kp; +#if CONFIG_IS_ENABLED(BLK) + struct blk_desc *dev_desc = NULL; +#endif + + read_keyslot_package(&kp); + if (strcmp(kp.magic, KEYPACK_MAGIC)) { + /* Return if the magic doesn't match */ + return 0; + } + /* If keyslot package valid, copy it to secure memory */ + fill_secure_keyslot_package(&kp); + + /* switch to boot1 partition. */ +#if !CONFIG_IS_ENABLED(BLK) + original_part = mmc->block_dev.hwpart; +#else + dev_desc = mmc_get_blk_desc(mmc); + original_part = dev_desc->hwpart; +#endif + if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) { + printf("ERROR - can't switch to boot1 partition! \n"); + ret = -1; + goto fail; + } else +#if !CONFIG_IS_ENABLED(BLK) + mmc->block_dev.hwpart = KEYSLOT_HWPARTITION_ID; +#else + dev_desc->hwpart = KEYSLOT_HWPARTITION_ID; +#endif + /* write power-on write protection for boot1 partition. */ + if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) { + printf("ERROR - unable to set power-on write protection!\n"); + ret = -1; + goto fail; + } +fail: + /* return to original partition. */ +#if !CONFIG_IS_ENABLED(BLK) + if (mmc->block_dev.hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + return -1; + mmc->block_dev.hwpart = original_part; + } +#else + if (dev_desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + return -1; + dev_desc->hwpart = original_part; + } +#endif + + return ret; +} +#endif /* CONFIG_IMX_TRUSTY_OS && !defined(CONFIG_AVB_ATX) */ +#else /* CONFIG_SPL_BUILD */ +#ifdef CONFIG_AVB_ATX +static int fsl_fuse_ops(uint32_t *buffer, uint32_t length, uint32_t offset, + const uint8_t read) { + + unsigned short bs, ws, bksz, cnt; + unsigned short num_done = 0; + margin_pos_t margin; + int i; + + /* read from fuse */ + bksz = CONFIG_AVB_FUSE_BANK_SIZEW; + if(get_margin_pos(CONFIG_AVB_FUSE_BANK_START, CONFIG_AVB_FUSE_BANK_END, bksz, + &margin, offset, length, false)) + return -1; + bs = (unsigned short)margin.blk_start; + ws = (unsigned short)margin.start; + + while (num_done < length) { + cnt = bksz - ws; + if (num_done + cnt > length) + cnt = length - num_done; + for (i = 0; i < cnt; i++) { + VDEBUG("cur: bank=%d, word=%d\n",bs, ws); + if (read) { + if (fuse_sense(bs, ws, buffer)) { + ERR("read fuse bank %d, word %d error\n", bs, ws); + return -1; + } + } else { +#ifdef CONFIG_AVB_FUSE + if (fuse_prog(bs, ws, *buffer)) { +#else + if (fuse_override(bs, ws, *buffer)) { +#endif + ERR("write fuse bank %d, word %d error\n", bs, ws); + return -1; + } + } + ws++; + buffer++; + } + bs++; + num_done += cnt; + ws = 0; + } + return 0; +} + +int fsl_fuse_read(uint32_t *buffer, uint32_t length, uint32_t offset) { + + return fsl_fuse_ops( + buffer, + length, + offset, + 1 + ); +} + +int fsl_fuse_write(const uint32_t *buffer, uint32_t length, uint32_t offset) { + + return fsl_fuse_ops( + (uint32_t *)buffer, + length, + offset, + 0 + ); +} + +static int sha256(unsigned char* data, int len, unsigned char* output) { + struct hash_algo *algo; + void *buf; + + if (hash_lookup_algo("sha256", &algo)) { + printf("error in lookup sha256 algo!\n"); + return RESULT_ERROR; + } + buf = map_sysmem((ulong)data, len); + algo->hash_func_ws(buf, len, output, algo->chunk_size); + unmap_sysmem(buf); + + return algo->digest_size; +} + +int permanent_attributes_sha256_hash(unsigned char* output) { + AvbAtxPermanentAttributes attributes; + +#ifdef CONFIG_IMX_TRUSTY_OS + if(!trusty_read_permanent_attributes((uint8_t *)(&attributes), + sizeof(AvbAtxPermanentAttributes))) { + goto calc_sha256; + } else { + ERR("No perm-attr fused. Will use hard code one.\n"); + } +#endif + /* get permanent attributes */ + attributes.version = fsl_version; + memcpy(attributes.product_root_public_key, fsl_product_root_public_key, + sizeof(fsl_product_root_public_key)); + memcpy(attributes.product_id, fsl_atx_product_id, + sizeof(fsl_atx_product_id)); +#ifdef CONFIG_IMX_TRUSTY_OS +calc_sha256: +#endif + /* calculate sha256(permanent attributes) hash */ + if (sha256((unsigned char *)&attributes, sizeof(AvbAtxPermanentAttributes), + output) == RESULT_ERROR) { + printf("ERROR - calculate permanent attributes hash error"); + return RESULT_ERROR; + } + + return RESULT_OK; +} + +static int init_permanent_attributes_fuse(void) { + +#ifdef CONFIG_ARM64 + return RESULT_OK; +#else + uint8_t sha256_hash[AVB_SHA256_DIGEST_SIZE]; + uint32_t buffer[ATX_FUSE_BANK_NUM]; + int num = 0; + + /* read first 112 bits of sha256(permanent attributes) from fuse */ + if (fsl_fuse_read(buffer, ATX_FUSE_BANK_NUM, PERMANENT_ATTRIBUTE_HASH_OFFSET)) { + printf("ERROR - read permanent attributes hash from fuse error\n"); + return RESULT_ERROR; + } + /* only take the lower 2 bytes of the last bank */ + buffer[ATX_FUSE_BANK_NUM - 1] &= ATX_FUSE_BANK_MASK; + + /* return RESULT_OK if fuse has been initialized before */ + for (num = 0; num < ATX_FUSE_BANK_NUM; num++) { + if (buffer[num]) + return RESULT_OK; + } + + /* calculate sha256(permanent attributes) */ + if (permanent_attributes_sha256_hash(sha256_hash) != RESULT_OK) { + printf("ERROR - calculating permanent attributes SHA256 error!\n"); + return RESULT_ERROR; + } + + /* write first 112 bits of sha256(permanent attributes) into fuse */ + memset(buffer, 0, sizeof(buffer)); + memcpy(buffer, sha256_hash, ATX_HASH_LENGTH); + if (fsl_fuse_write(buffer, ATX_FUSE_BANK_NUM, PERMANENT_ATTRIBUTE_HASH_OFFSET)) { + printf("ERROR - write permanent attributes hash to fuse error\n"); + return RESULT_ERROR; + } + + return RESULT_OK; +#endif /* CONFIG_ARM64 */ +} + +int avb_atx_fuse_perm_attr(uint8_t *staged_buffer, uint32_t size) { + + if (staged_buffer == NULL) { + ERR("Error. Get null staged_buffer\n"); + return -1; + } + if (size != sizeof(AvbAtxPermanentAttributes)) { + ERR("Error. expect perm_attr length %u, but get %u.\n", + (uint32_t)sizeof(AvbAtxPermanentAttributes), size); + return -1; + } +#ifdef CONFIG_IMX_TRUSTY_OS + if (trusty_write_permanent_attributes(staged_buffer, size)) { + ERR("Error. Failed to write permanent attributes into secure storage\n"); + return -1; + } + else + return init_permanent_attributes_fuse(); +#else + /* + * TODO: + * Need to handle this when no Trusty OS support. + * But now every Android Things will have Trusty OS support. + */ + ERR("No Trusty OS enabled in bootloader.\n"); + return 0; +#endif +} + +int avb_atx_get_unlock_challenge(struct AvbAtxOps* atx_ops, + uint8_t *upload_buffer, uint32_t *upload_size) +{ + struct AvbAtxUnlockChallenge *buf = NULL; + int ret, size; + + size = sizeof(struct AvbAtxUnlockChallenge); + buf = (struct AvbAtxUnlockChallenge *)malloc(size); + if (buf == NULL) { + ERR("unable to alloc memory!\n"); + return -1; + } + + if (avb_atx_generate_unlock_challenge(atx_ops, buf) != + AVB_IO_RESULT_OK) { + ERR("generate unlock challenge fail!\n"); + ret = -1; + goto fail; + } + /* Current avbtool only accept 16 bytes random numbers as unlock + * challenge, need to return the whole 'AvbAtxUnlockChallenge' + * when avbtool is ready. + */ + memcpy(upload_buffer, buf->challenge, AVB_ATX_UNLOCK_CHALLENGE_SIZE); + *upload_size = AVB_ATX_UNLOCK_CHALLENGE_SIZE; + ret = 0; +fail: + if (buf != NULL) + free(buf); + return ret; +} + +int avb_atx_verify_unlock_credential(struct AvbAtxOps* atx_ops, + uint8_t *staged_buffer) +{ + bool out_is_trusted; + AvbIOResult ret; + const AvbAtxUnlockCredential* buf = NULL; + + buf = (const AvbAtxUnlockCredential*)staged_buffer; + ret = avb_atx_validate_unlock_credential(atx_ops, buf, &out_is_trusted); + if ((ret != AVB_IO_RESULT_OK) || (out_is_trusted != true)) { + ERR("validate unlock credential fail!\n"); + return -1; + } else + return 0; +} + +bool perm_attr_are_fused(void) +{ +#ifdef CONFIG_IMX_TRUSTY_OS + AvbAtxPermanentAttributes attributes; + if(!trusty_read_permanent_attributes((uint8_t *)(&attributes), + sizeof(AvbAtxPermanentAttributes))) { + return true; + } else { + ERR("No perm-attr fused, please fuse your perm-attr first!.\n"); + return false; + } +#else + /* We hard code the perm-attr if trusty is not enabled. */ + return true; +#endif +} + +bool at_unlock_vboot_is_disabled(void) +{ + uint32_t unlock_vboot_status; + + if (fsl_fuse_read(&unlock_vboot_status, 1, + UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD)) { + printf("Read at unlock vboot status error!\n"); + return false; + } + + if (unlock_vboot_status & (1 << UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT)) + return true; + else + return false; +} + +int at_disable_vboot_unlock(void) +{ + uint32_t unlock_vboot_status = 0; + + /* Read the status first */ + if (fsl_fuse_read(&unlock_vboot_status, 1, + UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD)) { + ERR("Read unlock vboot status error!\n"); + return -1; + } + + /* Set the disable unlock vboot bit */ + unlock_vboot_status |= (1 << UNLOCK_VBOOT_STATUS_OFFSET_IN_BIT); + + /* Write disable unlock vboot bit to fuse */ + if (fsl_fuse_write(&unlock_vboot_status, 1, + UNLOCK_VBOOT_STATUS_OFFSET_IN_WORD)) { + ERR("Write unlock vboot status fail!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_AVB_ATX */ + +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) + +extern struct imx_sec_config_fuse_t const imx_sec_config_fuse; +#define HAB_ENABLED_BIT (is_soc_type(MXC_SOC_IMX8M)? 0x2000000 : 0x2) + +/* Check hab status, this is basically copied from imx_hab_is_enabled() */ +bool hab_is_enabled(void) +{ +#ifdef CONFIG_ARCH_IMX8 + sc_err_t err; + uint16_t lc; + + err = sc_seco_chip_info(-1, &lc, NULL, NULL, NULL); + if (err != SC_ERR_NONE) { + printf("Error in get lifecycle\n"); + return false; + } + + if (lc != 0x80) +#else + struct imx_sec_config_fuse_t *fuse = + (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse; + uint32_t reg; + int ret; + + ret = fuse_read(fuse->bank, fuse->word, ®); + if (ret) { + puts("\nSecure boot fuse read error!\n"); + return false; + } + + if (!((reg & HAB_ENABLED_BIT) == HAB_ENABLED_BIT)) +#endif + return false; + else + return true; +} + +int do_rpmb_key_set(uint8_t *key, uint32_t key_size) +{ + int ret = 0; + int mmcc; + struct mmc *mmc; + char original_part; + struct keyslot_package kp; + struct blk_desc *desc = NULL; + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_key, RPMBKEY_LENGTH); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, blob, + RPMBKEY_LENGTH + CAAM_PAD); + + /* copy rpmb key to cache aligned buffer. */ + memset(rpmb_key, 0, RPMBKEY_LENGTH); + memcpy(rpmb_key, key, RPMBKEY_LENGTH); + + /* Get current mmc device. */ +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MMC_SUPPORT) + mmcc = spl_get_mmc_dev(); +#else + mmcc = mmc_get_env_dev(); +#endif + mmc = find_mmc_device(mmcc); + if (!mmc) { + printf("error - cannot find '%d' mmc device\n", mmcc); + return -1; + } + desc = mmc_get_blk_desc(mmc); + original_part = desc->hwpart; + + /* Switch to the RPMB partition */ + if (desc->hwpart != MMC_PART_RPMB) { + if (mmc_switch_part(mmc, MMC_PART_RPMB) != 0) { + printf("ERROR - can't switch to rpmb partition \n"); + return -1; + } + desc->hwpart = MMC_PART_RPMB; + } + + if (mmc_rpmb_set_key(mmc, rpmb_key)) { + printf("ERROR - Key already programmed ?\n"); + ret = -1; + goto fail; + } else + printf("RPMB key programed successfully!\n"); + + /* Generate keyblob with CAAM. */ + memset((void *)&kp, 0, sizeof(struct keyslot_package)); + kp.rpmb_keyblob_len = RPMBKEY_LENGTH + CAAM_PAD; + strcpy(kp.magic, KEYPACK_MAGIC); + if (hwcrypto_gen_blob((uint32_t)(ulong)rpmb_key, RPMBKEY_LENGTH, + (uint32_t)(ulong)blob) != 0) { + printf("ERROR - generate rpmb key blob error!\n"); + ret = -1; + goto fail; + } else + printf("RPMB key blob generated!\n"); + + memcpy(kp.rpmb_keyblob, blob, kp.rpmb_keyblob_len); + + /* Reset key after use */ + memset(rpmb_key, 0, RPMBKEY_LENGTH); + memset(key, 0, RPMBKEY_LENGTH); + + /* Store the rpmb key blob to last block of boot1 partition. */ + if (mmc_switch_part(mmc, KEYSLOT_HWPARTITION_ID) != 0) { + printf("ERROR - can't switch to boot1 partition! \n"); + ret = -1; + goto fail; + } else + desc->hwpart = KEYSLOT_HWPARTITION_ID; + if (blk_dwrite(desc, KEYSLOT_BLKS, 1, (void *)&kp) != 1) { + printf("ERROR - failed to write rpmbkeyblob!"); + ret = -1; + goto fail; + } + /* Set power-on write protection to boot1 partition. */ + if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) { + printf("ERROR - unable to set power-on write protection!\n"); + ret = -1; + goto fail; + } + +fail: + /* Return to original partition */ + if (desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) + return -1; + desc->hwpart = original_part; + } + + return ret; +} + +int fastboot_set_rpmb_staged_key(uint8_t *staged_buf, uint32_t key_size) +{ + + if (memcmp(staged_buf, RPMB_KEY_MAGIC, strlen(RPMB_KEY_MAGIC))) { + printf("ERROR - rpmb magic doesn't match!\n"); + return -1; + } + + return do_rpmb_key_set(staged_buf + strlen(RPMB_KEY_MAGIC), + RPMBKEY_LENGTH); +} + +int fastboot_set_rpmb_hardware_key(void) +{ + return storage_set_rpmb_key(); +} + +int avb_set_public_key(uint8_t *staged_buffer, uint32_t size) { + + if ((staged_buffer == NULL) || (size <= 0)) { + ERR("Error. Get null staged_buffer\n"); + return -1; + } + if (trusty_write_vbmeta_public_key(staged_buffer, size)) { + ERR("Error. Failed to write vbmeta public key into secure storage\n"); + return -1; + } else + printf("Set vbmeta public key successfully!\n"); + + return 0; +} + +int fastboot_get_mppubk(uint8_t *staged_buffer, uint32_t *size) { + + if (!hab_is_enabled()) { + ERR("Error. This command can only be used when hab is closed!!\n"); + return -1; + } + + if ((staged_buffer == NULL) || (size == NULL)) { + ERR("Error. Get null staged_buffer!\n"); + return -1; + } + if (trusty_get_mppubk(staged_buffer, size)) { + ERR("Error. Failed to get mppubk!\n"); + return -1; + } + + return 0; +} +#endif /* CONFIG_IMX_TRUSTY_OS && !defind(CONFIG_AVB_ATX) */ +#endif /* CONFIG_SPL_BUILD */ diff --git a/lib/avb/fsl/fsl_avbkey.h b/lib/avb/fsl/fsl_avbkey.h new file mode 100644 index 00000000000..a4343e06d32 --- /dev/null +++ b/lib/avb/fsl/fsl_avbkey.h @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_AVBKEY_H__ +#define __FSL_AVBKEY_H__ + +#include + +#define CAAM_PAD 48 + +#define AVB_PUBKY_FLAG 0xABAB +#define AVB_PUBKY_OFFSET 0x1000 + +#define AVB_RBIDX_FLAG 0xCDCD +#define AVB_RBIDX_START 0x2000 +#define AVB_RBIDX_ALIGN 0x1000 +#define AVB_RBIDX_LEN 0x08 +#define AVB_RBIDX_INITVAL 0 + +#ifdef CONFIG_AVB_ATX +#define ATX_RBIDX_FLAG 0xEFEF +#define ATX_RBIDX_START 0x22000 +#define ATX_RBIDX_ALIGN 0x1000 +#define ATX_RBIDX_LEN 0x08 +#define ATX_RBIDX_INITVAL 0 +#endif + +#define AVB_KBLB_MAGIC "\0KBLB!" +#define AVB_KBLB_MAGIC_LEN 6 + +#if defined(CONFIG_AVB_ATX) && defined(CONFIG_DUAL_BOOTLOADER) +#define BL_RBINDEX_MAGIC "BL_RBINDEX" +#define BL_RBINDEX_MAGIC_LEN 11 +struct bl_rbindex_package { + char magic[BL_RBINDEX_MAGIC_LEN]; + uint32_t rbindex; +}; +#endif + +#ifndef CONFIG_AVB_ATX +#define RPMB_KEY_MAGIC "RPMB" +#endif + +#ifdef CONFIG_AVB_ATX +#define ATX_FUSE_BANK_NUM 4 +#define ATX_FUSE_BANK_MASK 0xFFFF +#define ATX_HASH_LENGTH 14 +#endif + +#define RESULT_ERROR -1 +#define RESULT_OK 0 + +struct kblb_tag { + uint32_t flag; + uint32_t offset; + uint32_t len; +}; +typedef struct kblb_tag kblb_tag_t; + +struct kblb_hdr { + /* avbkey partition magic */ + char magic[AVB_KBLB_MAGIC_LEN]; + /* Rollback index for bootloader is managed by SPL and + * will be stored in RPMB. + */ +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_SPL_BUILD) + kblb_tag_t bootloader_rbk_tags; +#endif + /* public key keyblb tag */ + kblb_tag_t pubk_tag; + /* vbmeta rollback index keyblb tag */ + kblb_tag_t rbk_tags[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS]; +#ifdef CONFIG_AVB_ATX + /* Android Things key versions rollback index keyblb tag */ + kblb_tag_t atx_rbk_tags[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS]; +#endif +}; +typedef struct kblb_hdr kblb_hdr_t; + +#define RPMBKEY_LEN (32 + CAAM_PAD) +#define KEYPACK_MAGIC "!KS" +#define KEYPACK_PAD_LENGTH (512 - 4 * sizeof(char) - sizeof(unsigned int) - RPMBKEY_LEN * sizeof(unsigned char)) + +struct keyslot_package +{ + char magic[4]; + unsigned int rpmb_keyblob_len; + unsigned char rpmb_keyblob[RPMBKEY_LEN]; + // padding keyslot_package to 1 block size + unsigned char pad[KEYPACK_PAD_LENGTH]; +}; + +int gen_rpmb_key(struct keyslot_package *kp); +int read_keyslot_package(struct keyslot_package* kp); +void fill_secure_keyslot_package(struct keyslot_package *kp); +int rpmb_init(void); +int rpmb_read(struct mmc *mmc, uint8_t *buffer, + size_t num_bytes,int64_t offset); +int rpmb_write(struct mmc *mmc, uint8_t *buffer, size_t num_bytes, + int64_t offset); + +int check_rpmb_blob(struct mmc *mmc); +bool rpmbkey_is_set(void); +int fsl_fuse_write(const uint32_t *buffer, uint32_t length, uint32_t offset); +int fsl_fuse_read(uint32_t *buffer, uint32_t length, uint32_t offset); +int permanent_attributes_sha256_hash(unsigned char* output); +struct mmc *get_mmc(void); +#endif diff --git a/lib/avb/fsl/fsl_bootctrl.c b/lib/avb/fsl/fsl_bootctrl.c new file mode 100755 index 00000000000..e98ce250cba --- /dev/null +++ b/lib/avb/fsl/fsl_bootctrl.c @@ -0,0 +1,1386 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2020 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include "utils.h" +#include +#include +#include +#include +#include "fsl_caam.h" +#include "fsl_avbkey.h" +#include "hang.h" +#include "fsl_bootctrl.h" + +/* Maximum values for slot data */ +#define AVB_AB_MAX_PRIORITY 15 +#define AVB_AB_MAX_TRIES_REMAINING 7 +#define AVB_AB_SLOT_NUM 2 +#ifndef MAX_PTN +#define MAX_PTN 32 +#endif + +/* The bootloader_control struct is stored 2048 bytes into the 'misc' partition + * following the 'struct bootloader_message' field. The struct is compatible with + * the guidelines in + * hardware/interfaces/boot/1.1/default/boot_control/include/libboot_control/libboot_control.h + */ +#define FSL_AB_METADATA_MISC_PARTITION_OFFSET 2048 +extern AvbABOps fsl_avb_ab_ops; + +static char *slot_suffix[AVB_AB_SLOT_NUM] = {"_a", "_b"}; + +static int strcmp_l1(const char *s1, const char *s2) { + if (!s1 || !s2) + return -1; + return strncmp(s1, s2, strlen(s1)); +} + +int get_curr_slot(struct bootloader_control *ab_data) { + if (fsl_slot_is_bootable(&ab_data->slot_info[0]) && + fsl_slot_is_bootable(&ab_data->slot_info[1])) { + if (ab_data->slot_info[1].priority > ab_data->slot_info[0].priority) + return 1; + else + return 0; + } else if (fsl_slot_is_bootable(&ab_data->slot_info[0])) + return 0; + else if (fsl_slot_is_bootable(&ab_data->slot_info[1])) + return 1; + else + return -1; +} + +/* Return current slot without passing 'bootloader_control' struct */ +int current_slot(void) { + struct bootloader_control ab_data; + + /* Load A/B metadata and decide which slot we are going to load */ + if (fsl_avb_ab_ops.read_ab_metadata(&fsl_avb_ab_ops, &ab_data) != + AVB_IO_RESULT_OK) { + printf("Error loading AB metadata from misc!\n"); + return -1; + } + return get_curr_slot(&ab_data); +} + +int slotidx_from_suffix(char *suffix) { + int slot = -1; + + if (!strcmp(suffix, "_a") || + !strcmp(suffix, "a")) + slot = 0; + else if (!strcmp(suffix, "_b") || + !strcmp(suffix, "b")) + slot = 1; + + return slot; +} + +bool is_slotvar_avb(char *cmd) { + + assert(cmd != NULL); + if (!strcmp_l1("has-slot:", cmd) || + !strcmp_l1("slot-successful:", cmd) || + !strcmp_l1("slot-count", cmd) || + !strcmp_l1("slot-suffixes", cmd) || + !strcmp_l1("current-slot", cmd) || + !strcmp_l1("slot-unbootable:", cmd) || + !strcmp_l1("slot-retry-count:", cmd)) + return true; + return false; +} + +extern struct fastboot_ptentry g_ptable[MAX_PTN]; +extern unsigned int g_pcount; + +static bool has_slot(char *cmd) { + unsigned int n; + char *ptr; + + for (n = 0; n < g_pcount; n++) { + ptr = strstr(g_ptable[n].name, cmd); + if (ptr != NULL) { + ptr += strlen(cmd); + if (!strcmp(ptr, "_a") || !strcmp(ptr, "_b")) + return true; + } + } + return false; +} + +int get_slotvar_avb(AvbABOps *ab_ops, char *cmd, char *buffer, size_t size) { + + struct bootloader_control ab_data; + struct slot_metadata *slot_data; + int slot; + + if ((ab_ops == NULL) || (cmd == NULL) || (buffer == NULL)) + return -1; + + char *str = cmd; + if (!strcmp_l1("has-slot:", cmd)) { + str += strlen("has-slot:"); + if (has_slot(str)) + strlcpy(buffer, "yes", size); + else + strlcpy(buffer, "no", size); + return 0; + + } else if (!strcmp_l1("slot-suffixes", cmd)) { + strlcpy(buffer, "_a,_b", size); + return 0 ; + + } else if (!strcmp_l1("slot-count", cmd)) { + strlcpy(buffer, "2", size); + return 0 ; + } + + /* load ab meta */ + if (ab_ops->read_ab_metadata == NULL || + ab_ops->read_ab_metadata(ab_ops, &ab_data) != AVB_IO_RESULT_OK) { + strlcpy(buffer, "ab data read error", size); + return -1 ; + } + + if (!strcmp_l1("current-slot", cmd)) { + int curr = get_curr_slot(&ab_data); + if (curr >= 0 && curr < AVB_AB_SLOT_NUM) + strlcpy(buffer, slot_suffix[curr] + sizeof(unsigned char), size); + else { + strlcpy(buffer, "no bootable slot", size); + return -1; + } + + } else if (!strcmp_l1("slot-successful:", cmd)) { + str += strlen("slot-successful:"); + slot = slotidx_from_suffix(str); + if (slot < 0) { + strlcpy(buffer, "no such slot", size); + return -1; + } else { + slot_data = &ab_data.slot_info[slot]; + bool succ = (slot_data->successful_boot != 0); + strlcpy(buffer, succ ? "yes" : "no", size); + } + + } else if (!strcmp_l1("slot-unbootable:", cmd)) { + str += strlen("slot-unbootable:"); + slot = slotidx_from_suffix(str); + if (slot < 0) { + strlcpy(buffer, "no such slot", size); + return -1; + } else { + slot_data = &ab_data.slot_info[slot]; + bool bootable = fsl_slot_is_bootable(slot_data); + strlcpy(buffer, bootable ? "no" : "yes", size); + } + + } else if (!strcmp_l1("slot-retry-count:", cmd)) { + str += strlen("slot-retry-count:"); + slot = slotidx_from_suffix(str); + if (slot < 0) { + strlcpy(buffer, "no such slot", size); + return -1; + } + else { + slot_data = &ab_data.slot_info[slot]; + char var[7]; + sprintf(var, "%d", + slot_data->tries_remaining); + strlcpy(buffer, var, size); + } + + } else { + strlcpy(buffer, "no such slot command", size); + return -1; + } + + return 0; +} + +char *select_slot(AvbABOps *ab_ops) { + struct bootloader_control ab_data; + int curr; + + if (ab_ops == NULL) { + return NULL; + } + + /* load ab meta */ + if (ab_ops->read_ab_metadata == NULL || + ab_ops->read_ab_metadata(ab_ops, &ab_data) != AVB_IO_RESULT_OK) { + return NULL; + } + curr = get_curr_slot(&ab_data); + if (curr >= 0 && curr < AVB_AB_SLOT_NUM) + return slot_suffix[curr]; + else + return NULL; +} + +bool fsl_avb_ab_data_verify_and_byteswap(const struct bootloader_control* src, + struct bootloader_control* dest) { + /* Ensure magic is correct. */ + if (src->magic != BOOT_CTRL_MAGIC) { + printf("Magic is incorrect.\n"); + return false; + } + + memcpy(dest, src, sizeof(struct bootloader_control)); + + /* Ensure we don't attempt to access any fields if the bootctrl version + * is not supported. + */ + if (dest->version > BOOT_CTRL_VERSION) { + printf("No support for given bootctrl version.\n"); + return false; + } + + /* Fail if CRC32 doesn't match. */ + if (dest->crc32_le != + avb_crc32((const uint8_t*)dest, sizeof(struct bootloader_control) - sizeof(uint32_t))) { + printf("CRC32 does not match.\n"); + return false; + } + + return true; +} + +void fsl_avb_ab_data_update_crc_and_byteswap(const struct bootloader_control* src, + struct bootloader_control* dest) { + memcpy(dest, src, sizeof(struct bootloader_control)); + dest->crc32_le = avb_crc32((const uint8_t*)dest, + sizeof(struct bootloader_control) - sizeof(uint32_t)); +} + +void fsl_avb_ab_data_init(struct bootloader_control* data) { + memset(data, '\0', sizeof(struct bootloader_control)); + data->magic = BOOT_CTRL_MAGIC; + data->version = BOOT_CTRL_VERSION; + // this bootctrl can support up to 4 slots but here we only support 2 + data->nb_slot = AVB_AB_SLOT_NUM; + data->slot_info[0].priority = AVB_AB_MAX_PRIORITY; + data->slot_info[0].tries_remaining = AVB_AB_MAX_TRIES_REMAINING; + data->slot_info[0].successful_boot = 0; + data->slot_info[0].verity_corrupted = 0; +#ifdef CONFIG_DUAL_BOOTLOADER + data->slot_info[0].bootloader_verified = 0; +#endif + data->slot_info[1].priority = AVB_AB_MAX_PRIORITY; + data->slot_info[1].tries_remaining = AVB_AB_MAX_TRIES_REMAINING; + data->slot_info[1].successful_boot = 0; + data->slot_info[1].verity_corrupted = 0; +#ifdef CONFIG_DUAL_BOOTLOADER + data->slot_info[1].bootloader_verified = 0; +#endif +} + +AvbIOResult fsl_avb_ab_data_read(AvbABOps* ab_ops, struct bootloader_control* data) { + AvbOps* ops = ab_ops->ops; + struct bootloader_control serialized; + AvbIOResult io_ret; + size_t num_bytes_read; + + io_ret = ops->read_from_partition(ops, + FASTBOOT_PARTITION_MISC, + FSL_AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(struct bootloader_control), + &serialized, + &num_bytes_read); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_IO_RESULT_ERROR_OOM; + } else if (io_ret != AVB_IO_RESULT_OK || + num_bytes_read != sizeof(struct bootloader_control)) { + printf("Error reading A/B metadata.\n"); + return AVB_IO_RESULT_ERROR_IO; + } + + if (!fsl_avb_ab_data_verify_and_byteswap(&serialized, data)) { + printf( + "Error validating A/B metadata from disk. " + "Resetting and writing new A/B metadata to disk.\n"); + fsl_avb_ab_data_init(data); + return fsl_avb_ab_data_write(ab_ops, data); + } + + return AVB_IO_RESULT_OK; +} + +AvbIOResult fsl_avb_ab_data_write(AvbABOps* ab_ops, const struct bootloader_control* data) { + AvbOps* ops = ab_ops->ops; + struct bootloader_control serialized; + AvbIOResult io_ret; + + fsl_avb_ab_data_update_crc_and_byteswap(data, &serialized); + io_ret = ops->write_to_partition(ops, + FASTBOOT_PARTITION_MISC, + FSL_AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(struct bootloader_control), + &serialized); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + return AVB_IO_RESULT_ERROR_OOM; + } else if (io_ret != AVB_IO_RESULT_OK) { + printf("Error writing A/B metadata.\n"); + return AVB_IO_RESULT_ERROR_IO; + } + return AVB_IO_RESULT_OK; +} + +bool fsl_slot_is_bootable(struct slot_metadata* slot) { +#ifdef CONFIG_DUAL_BOOTLOADER + /* The 'bootloader_verified' will be set when the slot has only one chance + * left, which means the slot is bootable even tries_remaining is 0. + */ + return slot->priority > 0 && + (slot->successful_boot || (slot->tries_remaining > 0)|| + (slot->bootloader_verified == 1)); +#else + return slot->priority > 0 && + (slot->successful_boot || (slot->tries_remaining > 0)); +#endif +} + +static void fsl_slot_set_unbootable(struct slot_metadata* slot) { + slot->priority = 0; + slot->tries_remaining = 0; + slot->successful_boot = 0; +#ifdef CONFIG_DUAL_BOOTLOADER + slot->bootloader_verified = 0; +#endif +} + +/* Ensure all unbootable and/or illegal states are marked as the + * canonical 'unbootable' state, e.g. priority=0, tries_remaining=0, + * and successful_boot=0. + */ +static void fsl_slot_normalize(struct slot_metadata* slot) { + if (slot->priority > 0) { +#if defined(CONFIG_DUAL_BOOTLOADER) && !defined(CONFIG_SPL_BUILD) + if ((slot->tries_remaining == 0) + && (slot->bootloader_verified != 1)) { + /* We've exhausted all tries -> unbootable. */ + fsl_slot_set_unbootable(slot); + } +#else + if (slot->tries_remaining == 0) { + /* We've exhausted all tries -> unbootable. */ + fsl_slot_set_unbootable(slot); + } +#endif + } else { + fsl_slot_set_unbootable(slot); + } +} + +/* Helper function to load metadata - returns AVB_IO_RESULT_OK on + * success, error code otherwise. + */ +static AvbIOResult fsl_load_metadata(AvbABOps* ab_ops, + struct bootloader_control* ab_data, + struct bootloader_control* ab_data_orig) { + AvbIOResult io_ret; + + io_ret = ab_ops->read_ab_metadata(ab_ops, ab_data); + if (io_ret != AVB_IO_RESULT_OK) { + printf("I/O error while loading A/B metadata.\n"); + return io_ret; + } + *ab_data_orig = *ab_data; + + /* Ensure data is normalized, e.g. illegal states will be marked as + * unbootable and all unbootable states are represented with + * (priority=0, tries_remaining=0, successful_boot=0). + */ + fsl_slot_normalize(&ab_data->slot_info[0]); + fsl_slot_normalize(&ab_data->slot_info[1]); + return AVB_IO_RESULT_OK; +} + +/* Writes A/B metadata to disk only if it has been changed. + */ +static AvbIOResult fsl_save_metadata_if_changed(AvbABOps* ab_ops, + struct bootloader_control* ab_data, + struct bootloader_control* ab_data_orig) { + if (avb_safe_memcmp(ab_data, ab_data_orig, sizeof(struct bootloader_control)) != 0) { + printf("Writing A/B metadata to disk.\n"); + return ab_ops->write_ab_metadata(ab_ops, ab_data); + } + return AVB_IO_RESULT_OK; +} + +AvbIOResult fsl_avb_ab_mark_slot_active(AvbABOps* ab_ops, + unsigned int slot_number) { + struct bootloader_control ab_data, ab_data_orig; + unsigned int other_slot_number; + AvbIOResult ret; + + avb_assert(slot_number < 2); + + ret = fsl_load_metadata(ab_ops, &ab_data, &ab_data_orig); + if (ret != AVB_IO_RESULT_OK) { + goto out; + } + + /* Make requested slot top priority, unsuccessful, and with max tries. */ + ab_data.slot_info[slot_number].priority = AVB_AB_MAX_PRIORITY; + ab_data.slot_info[slot_number].tries_remaining = AVB_AB_MAX_TRIES_REMAINING; + ab_data.slot_info[slot_number].successful_boot = 0; +#ifdef CONFIG_DUAL_BOOTLOADER + ab_data.slot_info[slot_number].bootloader_verified = 0; +#endif + + /* Ensure other slot doesn't have as high a priority. */ + other_slot_number = 1 - slot_number; + if (ab_data.slot_info[other_slot_number].priority == AVB_AB_MAX_PRIORITY) { + ab_data.slot_info[other_slot_number].priority = AVB_AB_MAX_PRIORITY - 1; + } + + ret = AVB_IO_RESULT_OK; + +out: + if (ret == AVB_IO_RESULT_OK) { + ret = fsl_save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); + } + return ret; +} + + +/* Below are the A/B AVB flow in spl and uboot proper. */ +#if defined(CONFIG_DUAL_BOOTLOADER) && defined(CONFIG_SPL_BUILD) + +#define PARTITION_NAME_LEN 13 +#define PARTITION_BOOTLOADER "bootloader" + +extern int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value); + +/* Pre-declaration of h_spl_load_read(), see detail implementation in + * common/spl/spl_mmc.c. + */ +ulong h_spl_load_read(struct spl_load_info *load, ulong sector, + ulong count, void *buf); + +/* Writes A/B metadata to disk only if it has changed. + */ +int fsl_save_metadata_if_changed_dual_uboot(struct blk_desc *dev_desc, + struct bootloader_control* ab_data, + struct bootloader_control* ab_data_orig) { + struct bootloader_control serialized; + size_t num_bytes; + struct disk_partition info; + + /* Save metadata if changed. */ + if (memcmp(ab_data, ab_data_orig, sizeof(struct bootloader_control)) != 0) { + /* Get misc partition info */ + if (part_get_info_efi_by_name(dev_desc, FASTBOOT_PARTITION_MISC, &info) == -1) { + printf("Can't get partition info of partition: misc\n"); + return -1; + } + + /* Writing A/B metadata to disk. */ + fsl_avb_ab_data_update_crc_and_byteswap(ab_data, &serialized); + if (write_to_partition_in_bytes(dev_desc, &info, + FSL_AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(struct bootloader_control), + (void *)&serialized, &num_bytes) || + (num_bytes != sizeof(struct bootloader_control))) { + printf("Error--write metadata fail!\n"); + return -1; + } + } + return 0; +} + +/* Load metadate from misc partition. + */ +int fsl_load_metadata_dual_uboot(struct blk_desc *dev_desc, + struct bootloader_control* ab_data, + struct bootloader_control* ab_data_orig) { + struct disk_partition info; + struct bootloader_control serialized; + size_t num_bytes; + + if (part_get_info_efi_by_name(dev_desc, FASTBOOT_PARTITION_MISC, &info) == -1) { + printf("Can't get partition info of partition: misc\n"); + return -1; + } else { + read_from_partition_in_bytes(dev_desc, &info, + FSL_AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(struct bootloader_control), + (void *)ab_data, &num_bytes ); + if (num_bytes != sizeof(struct bootloader_control)) { + printf("Error--read metadata fail!\n"); + return -1; + } else { + if (!fsl_avb_ab_data_verify_and_byteswap(ab_data, &serialized)) { + printf("Error validating A/B metadata from disk.\n"); + printf("Resetting and writing new A/B metadata to disk.\n"); + fsl_avb_ab_data_init(ab_data); + fsl_avb_ab_data_update_crc_and_byteswap(ab_data, &serialized); + num_bytes = 0; + if (write_to_partition_in_bytes(dev_desc, &info, FSL_AB_METADATA_MISC_PARTITION_OFFSET, + sizeof(struct bootloader_control), + (void *)&serialized, &num_bytes) || + (num_bytes != sizeof(struct bootloader_control))) { + printf("Error--write metadata fail!\n"); + return -1; + } else + return 0; + } else { + memcpy(ab_data_orig, ab_data, sizeof(struct bootloader_control)); + /* Ensure data is normalized, e.g. illegal states will be marked as + * unbootable and all unbootable states are represented with + * (priority=0, tries_remaining=0, successful_boot=0). + */ + fsl_slot_normalize(&ab_data->slot_info[0]); + fsl_slot_normalize(&ab_data->slot_info[1]); + return 0; + } + } + } +} + +#if !defined(CONFIG_XEN) && defined(CONFIG_IMX_TRUSTY_OS) +static int spl_verify_rbidx(struct mmc *mmc, struct slot_metadata *slot, + struct spl_image_info *spl_image) +{ + kblb_hdr_t hdr; + kblb_tag_t *rbk; + uint64_t extract_idx; +#ifdef CONFIG_AVB_ATX + struct bl_rbindex_package *bl_rbindex; +#endif + + /* Make sure rollback index has been initialized before verify */ + if (rpmb_init()) { + printf("RPMB init failed!\n"); + return -1; + } + + /* Read bootloader rollback index header first. */ + if (rpmb_read(mmc, (uint8_t *)&hdr, sizeof(hdr), + BOOTLOADER_RBIDX_OFFSET) != 0) { + printf("Read RPMB error!\n"); + return -1; + } + + /* Read bootloader rollback index. */ + rbk = &(hdr.bootloader_rbk_tags); + if (rpmb_read(mmc, (uint8_t *)&extract_idx, rbk->len, rbk->offset) != 0) { + printf("Read rollback index error!\n"); + return -1; + } + + /* Verify bootloader rollback index. */ + if (spl_image->rbindex >= extract_idx) { + /* Rollback index verify pass, update it only when current slot + * has been marked as successful. + */ + if ((slot->successful_boot != 0) && (spl_image->rbindex != extract_idx) && + rpmb_write(mmc, (uint8_t *)(&(spl_image->rbindex)), + rbk->len, rbk->offset)) { + printf("Update bootloader rollback index failed!\n"); + return -1; + } + +#ifdef CONFIG_AVB_ATX + /* Pass bootloader rbindex to u-boot here. */ + bl_rbindex = (struct bl_rbindex_package *)BL_RBINDEX_LOAD_ADDR; + memcpy(bl_rbindex->magic, BL_RBINDEX_MAGIC, BL_RBINDEX_MAGIC_LEN); + if (slot->successful_boot != 0) + bl_rbindex->rbindex = spl_image->rbindex; + else + bl_rbindex->rbindex = extract_idx; +#endif + + return 0; + } else { + printf("Rollback index verify rejected!\n"); + return -1; + } + +} +#endif /* !CONFIG_XEN && CONFIG_IMX_TRUSTY_OS */ + +int mmc_load_image_raw_sector_dual_uboot(struct spl_image_info *spl_image, + struct mmc *mmc) +{ + struct disk_partition info; + unsigned long count; + int ret = 0, n = 0; + char partition_name[PARTITION_NAME_LEN]; + struct blk_desc *dev_desc; + struct image_header *header; + struct spl_load_info load; + struct bootloader_control ab_data, ab_data_orig; + size_t slot_index_to_boot, target_slot; +#if !defined(CONFIG_XEN) && defined(CONFIG_IMX_TRUSTY_OS) + struct keyslot_package kp; +#endif + + /* Check if gpt is valid */ + dev_desc = mmc_get_blk_desc(mmc); + if (dev_desc) { + if (part_get_info(dev_desc, 1, &info)) { + printf("GPT is invalid, please flash correct GPT!\n"); + return -1; + } + } else { + printf("Get block desc fail!\n"); + return -1; + } + +#if !defined(CONFIG_XEN) && defined(CONFIG_IMX_TRUSTY_OS) + read_keyslot_package(&kp); + if (!strcmp(kp.magic, KEYPACK_MAGIC)) { + /* Set power-on write protection to boot1 partition. */ + if (mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, BOOT1_PWR_WP)) { + printf("Unable to set power-on write protection to boot1!\n"); + return -1; + } + } +#endif + + /* Load AB metadata from misc partition */ + if (fsl_load_metadata_dual_uboot(dev_desc, &ab_data, + &ab_data_orig)) { + return -1; + } + + slot_index_to_boot = 2; // Means not 0 or 1 + target_slot = + (ab_data.slot_info[1].priority > ab_data.slot_info[0].priority) ? 1 : 0; + + for (n = 0; n < 2; n++) { + if (!fsl_slot_is_bootable(&ab_data.slot_info[target_slot])) { + target_slot = (target_slot == 1 ? 0 : 1); + continue; + } + /* Choose slot to load. */ + snprintf(partition_name, PARTITION_NAME_LEN, + PARTITION_BOOTLOADER"%s", + slot_suffix[target_slot]); + + /* Read part info from gpt */ + if (part_get_info_by_name(dev_desc, partition_name, &info) == -1) { + printf("Can't get partition info of partition bootloader%s\n", + slot_suffix[target_slot]); + ret = -1; + goto end; + } else { + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + /* read image header to find the image size & load address */ + count = blk_dread(dev_desc, info.start, 1, header); + if (count == 0) { + ret = -1; + goto end; + } + + /* Load fit/container and check HAB */ + load.dev = mmc; + load.priv = NULL; + load.filename = NULL; + load.bl_len = mmc->read_bl_len; + load.read = h_spl_load_read; + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + /* Fit */ + ret = spl_load_simple_fit(spl_image, &load, + info.start, header); + } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { + /* container */ + ret = spl_load_imx_container(spl_image, &load, info.start); + } else + ret = -1; + +#if !defined(CONFIG_XEN) && defined(CONFIG_IMX_TRUSTY_OS) + /* Image loaded successfully, go to verify rollback index */ + if (rpmbkey_is_set()) { + if (!ret) + ret = spl_verify_rbidx(mmc, &ab_data.slot_info[target_slot], spl_image); + + /* Copy rpmb keyslot to secure memory. */ + if (!ret) + fill_secure_keyslot_package(&kp); + } +#endif + } + + /* Set current slot to unbootable if load/verify fail. */ + if (ret != 0) { + /* Reboot if current slot has booted succefully before, this prevents + * slot been marked as "unbootable" due to some random failures (like + * eMMC/DRAM access error at some critical temperature). + */ + if (ab_data.slot_info[target_slot].successful_boot) + do_reset(NULL, 0, 0, NULL); + else { + printf("Load or verify bootloader%s fail, setting unbootable..\n", + slot_suffix[target_slot]); + fsl_slot_set_unbootable(&ab_data.slot_info[target_slot]); + /* Switch to another slot. */ + target_slot = (target_slot == 1 ? 0 : 1); + } + } else { + slot_index_to_boot = target_slot; + n = 2; + } + } + + if (slot_index_to_boot == 2) { + /* No bootable slots, try to boot into recovery! */ + printf("No bootable slots found, try to boot into recovery mode...\n"); + + ab_data.spl_recovery = true; + if ((ab_data.last_boot != 0) && (ab_data.last_boot != 1)) + slot_index_to_boot = 0; + else + slot_index_to_boot = ab_data.last_boot; + + snprintf(partition_name, PARTITION_NAME_LEN, + PARTITION_BOOTLOADER"%s", + slot_suffix[target_slot]); + + /* Read part info from gpt */ + if (part_get_info_by_name(dev_desc, partition_name, &info) == -1) { + printf("Can't get partition info of partition bootloader%s\n", + slot_suffix[target_slot]); + ret = -1; + goto end; + } else { + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE - + sizeof(struct image_header)); + + /* read image header to find the image size & load address */ + count = blk_dread(dev_desc, info.start, 1, header); + if (count == 0) { + ret = -1; + goto end; + } + + /* Load fit/container and check HAB */ + load.dev = mmc; + load.priv = NULL; + load.filename = NULL; + load.bl_len = mmc->read_bl_len; + load.read = h_spl_load_read; + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + /* Fit */ + ret = spl_load_simple_fit(spl_image, &load, + info.start, header); + } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) { + /* container */ + ret = spl_load_imx_container(spl_image, &load, info.start); + } else + ret = -1; + +#if !defined(CONFIG_XEN) && defined(CONFIG_IMX_TRUSTY_OS) + /* Image loaded successfully, go to verify rollback index */ + if (rpmbkey_is_set()) { + if (!ret) + ret = spl_verify_rbidx(mmc, &ab_data.slot_info[target_slot], spl_image); + + /* Copy rpmb keyslot to secure memory. */ + if (!ret) + fill_secure_keyslot_package(&kp); + } +#endif + } + + if (ret) + goto end; + } else if (!ab_data.slot_info[slot_index_to_boot].successful_boot && + (ab_data.slot_info[slot_index_to_boot].tries_remaining > 0)) { + /* Set the bootloader_verified flag as if current slot only has one chance. */ + if (ab_data.slot_info[slot_index_to_boot].tries_remaining == 1) + ab_data.slot_info[slot_index_to_boot].bootloader_verified = 1; + ab_data.slot_info[slot_index_to_boot].tries_remaining -= 1; + + ab_data.last_boot = slot_index_to_boot; + } + printf("Booting from bootloader%s...\n", slot_suffix[slot_index_to_boot]); + +end: + /* Save metadata if changed. */ + if (fsl_save_metadata_if_changed_dual_uboot(dev_desc, &ab_data, &ab_data_orig)) { + ret = -1; + } + + if (ret) + return -1; + else + return 0; +} + +/* + * spl_fit_get_rbindex(): Get rollback index of the bootloader. + * @fit: Pointer to the FDT blob. + * + * Return: the rollback index value of bootloader or a negative + * error number. + */ +int spl_fit_get_rbindex(const void *fit) +{ + const char *str; + uint64_t index; + int conf_node; + int len; + + conf_node = fit_find_config_node(fit); + if (conf_node < 0) { + return conf_node; + } + + str = fdt_getprop(fit, conf_node, "rbindex", &len); + if (!str) { + debug("cannot find property 'rbindex'\n"); + return -EINVAL; + } + + index = simple_strtoul(str, NULL, 10); + + return index; +} + +/* For normal build */ +#elif !defined(CONFIG_SPL_BUILD) + +#ifdef CONFIG_DUAL_BOOTLOADER +// dual bootloader flow in uboot proper +AvbABFlowResult avb_flow_dual_uboot(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data) { + AvbOps* ops = ab_ops->ops; + AvbSlotVerifyData* slot_data = NULL; + AvbSlotVerifyData* data = NULL; + AvbABFlowResult ret = 0; + struct bootloader_control ab_data, ab_data_orig; + AvbIOResult io_ret; + AvbSlotVerifyResult verify_result; + bool set_slot_unbootable = false; + int target_slot, n; + uint64_t rollback_index_value = 0; + uint64_t current_rollback_index_value = 0; + + io_ret = fsl_load_metadata(ab_ops, &ab_data, &ab_data_orig); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + + /* Choose the target slot, it should be the same with the one in SPL. */ + target_slot = get_curr_slot(&ab_data); + if (target_slot == -1) { + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + printf("No bootable slot found!\n"); + goto out; + } + /* Clear the bootloader_verified flag. */ + ab_data.slot_info[target_slot].bootloader_verified = 0; + + printf("Verifying slot %s ...\n", slot_suffix[target_slot]); + verify_result = avb_slot_verify(ops, + requested_partitions, + slot_suffix[target_slot], + flags, + hashtree_error_mode, + &slot_data); + + switch (verify_result) { + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + + case AVB_SLOT_VERIFY_RESULT_OK: + ret = AVB_AB_FLOW_RESULT_OK; + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + /* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR + * these mean game over. + */ + set_slot_unbootable = true; + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) { + /* Do nothing since we allow this. */ + avb_debugv("Allowing slot ", + slot_suffix[target_slot], + " which verified " + "with result ", + avb_slot_verify_result_to_string(verify_result), + " because " + "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR " + "is set.\n", + NULL); + ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; + } else { + set_slot_unbootable = true; + } + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT; + goto out; + /* Do not add a 'default:' case here because + * of -Wswitch. + */ + } + + if (set_slot_unbootable) { + /* Reboot if current slot has booted succefully before, this prevents + * slot been marked as "unbootable" due to some random failures (like + * eMMC/DRAM access error at some critical temperature). + */ + if (ab_data.slot_info[target_slot].successful_boot) + do_reset(NULL, 0, 0, NULL); + else { + avb_errorv("Error verifying slot ", + slot_suffix[target_slot], + " with result ", + avb_slot_verify_result_to_string(verify_result), + " - setting unbootable.\n", + NULL); + fsl_slot_set_unbootable(&ab_data.slot_info[target_slot]); + + /* Only the slot chosen by SPL will be verified here so we + * return AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS if the + * slot should be set unbootable. + */ + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + goto out; + } + } + + /* Update stored rollback index only when the slot has been marked + * as successful. Do this for every rollback index location. + */ + if ((ret == AVB_AB_FLOW_RESULT_OK) && + (ab_data.slot_info[target_slot].successful_boot != 0)) { + for (n = 0; n < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; n++) { + + rollback_index_value = slot_data->rollback_indexes[n]; + + if (rollback_index_value != 0) { + io_ret = ops->read_rollback_index( + ops, n, ¤t_rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + printf("Error getting rollback index for slot.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + if (current_rollback_index_value != rollback_index_value) { + io_ret = ops->write_rollback_index( + ops, n, rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + printf("Error setting stored rollback index.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + } + } + } + } + + /* Finally, select this slot. */ + avb_assert(slot_data != NULL); + data = slot_data; + slot_data = NULL; + +out: + io_ret = fsl_save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); + if (io_ret != AVB_IO_RESULT_OK) { + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + } else { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + } + if (data != NULL) { + avb_slot_verify_data_free(data); + data = NULL; + } + } + + if (slot_data != NULL) + avb_slot_verify_data_free(slot_data); + + if (out_data != NULL) { + *out_data = data; + } else { + if (data != NULL) { + avb_slot_verify_data_free(data); + } + } + + return ret; +} + +static bool spl_recovery_flag = false; +bool is_spl_recovery(void) +{ + return spl_recovery_flag; +} +void check_spl_recovery(void) +{ + struct bootloader_control ab_data, ab_data_orig; + AvbIOResult io_ret; + + io_ret = fsl_load_metadata(&fsl_avb_ab_ops, &ab_data, &ab_data_orig); + if (io_ret != AVB_IO_RESULT_OK) { + printf("Load metadata fail, go to fail!\n"); + hang(); + } + + spl_recovery_flag = ab_data.spl_recovery; + /* Clear spl recovery flag. */ + ab_data.spl_recovery = false; + fsl_save_metadata_if_changed(&fsl_avb_ab_ops, &ab_data, &ab_data_orig); + + if (spl_recovery_flag) { + printf("Enter spl recovery mode, only fastboot commands are supported!\n"); + + while (1) { + run_command("fastboot 0", 0); + } + } +} + +#else /* CONFIG_DUAL_BOOTLOADER */ +/* For legacy i.mx6/7, we won't enable A/B due to the limitation of + * storage capacity, but we still want to verify boot/recovery with + * AVB. */ +AvbABFlowResult avb_single_flow(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data) { + AvbOps* ops = ab_ops->ops; + AvbSlotVerifyData* slot_data = NULL; + AvbSlotVerifyData* data = NULL; + AvbABFlowResult ret; + bool saw_and_allowed_verification_error = false; + + /* Validate boot/recovery. */ + AvbSlotVerifyResult verify_result; + + verify_result = avb_slot_verify(ops, + requested_partitions, + "", + flags, + hashtree_error_mode, + &slot_data); + switch (verify_result) { + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + + case AVB_SLOT_VERIFY_RESULT_OK: + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + /* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR + * these mean game over. + */ + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + goto out; + + /* explicit fallthrough. */ + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) { + /* Do nothing since we allow this. */ + avb_debugv("Allowing slot ", + slot_suffix[n], + " which verified " + "with result ", + avb_slot_verify_result_to_string(verify_result), + " because " + "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR " + "is set.\n", + NULL); + saw_and_allowed_verification_error = true; + } else { + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + goto out; + } + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT; + goto out; + /* Do not add a 'default:' case here because of -Wswitch. */ + } + + avb_assert(slot_data != NULL); + data = slot_data; + slot_data = NULL; + if (saw_and_allowed_verification_error) { + avb_assert(flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR); + ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; + } else { + ret = AVB_AB_FLOW_RESULT_OK; + } + +out: + if (slot_data != NULL) { + avb_slot_verify_data_free(slot_data); + } + + if (out_data != NULL) { + *out_data = data; + } else { + if (data != NULL) { + avb_slot_verify_data_free(data); + } + } + + return ret; +} + +AvbABFlowResult avb_ab_flow_fast(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data) { + AvbOps* ops = ab_ops->ops; + AvbSlotVerifyData* slot_data[2] = {NULL, NULL}; + AvbSlotVerifyData* data = NULL; + AvbABFlowResult ret = 0; + struct bootloader_control ab_data, ab_data_orig; + size_t slot_index_to_boot, n; + AvbIOResult io_ret; + size_t target_slot; + AvbSlotVerifyResult verify_result; + bool set_slot_unbootable = false; + uint64_t rollback_index_value = 0; + uint64_t current_rollback_index_value = 0; + + io_ret = fsl_load_metadata(ab_ops, &ab_data, &ab_data_orig); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + + slot_index_to_boot = 2; // Means not 0 or 1 + target_slot = + (ab_data.slot_info[1].priority > ab_data.slot_info[0].priority) ? 1 : 0; + + for (n = 0; n < 2; n++) { + if (!fsl_slot_is_bootable(&ab_data.slot_info[target_slot])) { + target_slot = (target_slot == 1 ? 0 : 1); + continue; + } + verify_result = avb_slot_verify(ops, + requested_partitions, + slot_suffix[target_slot], + flags, + hashtree_error_mode, + &slot_data[target_slot]); + switch (verify_result) { + case AVB_SLOT_VERIFY_RESULT_ERROR_OOM: + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + + case AVB_SLOT_VERIFY_RESULT_ERROR_IO: + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + + case AVB_SLOT_VERIFY_RESULT_OK: + slot_index_to_boot = target_slot; + ret = AVB_AB_FLOW_RESULT_OK; + n = 2; + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA: + case AVB_SLOT_VERIFY_RESULT_ERROR_UNSUPPORTED_VERSION: + /* Even with AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR + * these mean game over. + */ + set_slot_unbootable = true; + break; + + /* explicit fallthrough. */ + case AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION: + case AVB_SLOT_VERIFY_RESULT_ERROR_ROLLBACK_INDEX: + case AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED: + if (flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR) { + /* Do nothing since we allow this. */ + avb_debugv("Allowing slot ", + slot_suffix[target_slot], + " which verified " + "with result ", + avb_slot_verify_result_to_string(verify_result), + " because " + "AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR " + "is set.\n", + NULL); + slot_index_to_boot = target_slot; + ret = AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR; + n = 2; + } else { + set_slot_unbootable = true; + } + break; + + case AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT: + ret = AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT; + goto out; + /* Do not add a 'default:' case here because + * of -Wswitch. + */ + } + + if (set_slot_unbootable) { + /* Reboot if current slot has booted succefully before, this prevents + * slot been marked as "unbootable" due to some random failures (like + * eMMC/DRAM access error at some critical temperature). + */ + if (ab_data.slot_info[target_slot].successful_boot) + do_reset(NULL, 0, 0, NULL); + else { + avb_errorv("Error verifying slot ", + slot_suffix[target_slot], + " with result ", + avb_slot_verify_result_to_string(verify_result), + " - setting unbootable.\n", + NULL); + fsl_slot_set_unbootable(&ab_data.slot_info[target_slot]); + set_slot_unbootable = false; + } + if (slot_data[target_slot] != NULL) { + avb_slot_verify_data_free(slot_data[target_slot]); + slot_data[target_slot] = NULL; + } + } + /* switch to another slot */ + target_slot = (target_slot == 1 ? 0 : 1); + } + + if (slot_index_to_boot == 2) { + /* No bootable slots! */ + printf("No bootable slots found.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS; + goto out; + } + + /* Update stored rollback index only when the slot has been marked + * as successful. Do this for every rollback index location. + */ + if ((ret == AVB_AB_FLOW_RESULT_OK) && + (ab_data.slot_info[slot_index_to_boot].successful_boot != 0)) { + for (n = 0; n < AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS; n++) { + + rollback_index_value = slot_data[slot_index_to_boot]->rollback_indexes[n]; + + if (rollback_index_value != 0) { + io_ret = ops->read_rollback_index( + ops, n, ¤t_rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + printf("Error getting rollback index for slot.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + if (current_rollback_index_value != rollback_index_value) { + io_ret = ops->write_rollback_index( + ops, n, rollback_index_value); + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + goto out; + } else if (io_ret != AVB_IO_RESULT_OK) { + printf("Error setting stored rollback index.\n"); + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + goto out; + } + } + } + } + } + + /* Finally, select this slot. */ + avb_assert(slot_data[slot_index_to_boot] != NULL); + data = slot_data[slot_index_to_boot]; + slot_data[slot_index_to_boot] = NULL; + + /* ... and decrement tries remaining, if applicable. */ + if (!ab_data.slot_info[slot_index_to_boot].successful_boot && + (ab_data.slot_info[slot_index_to_boot].tries_remaining > 0)) { + ab_data.slot_info[slot_index_to_boot].tries_remaining -= 1; + } + +out: + io_ret = fsl_save_metadata_if_changed(ab_ops, &ab_data, &ab_data_orig); + if (io_ret != AVB_IO_RESULT_OK) { + if (io_ret == AVB_IO_RESULT_ERROR_OOM) { + ret = AVB_AB_FLOW_RESULT_ERROR_OOM; + } else { + ret = AVB_AB_FLOW_RESULT_ERROR_IO; + } + if (data != NULL) { + avb_slot_verify_data_free(data); + data = NULL; + } + } + + for (n = 0; n < 2; n++) { + if (slot_data[n] != NULL) { + avb_slot_verify_data_free(slot_data[n]); + } + } + + if (out_data != NULL) { + *out_data = data; + } else { + if (data != NULL) { + avb_slot_verify_data_free(data); + } + } + + return ret; +} +#endif /* CONFIG_DUAL_BOOTLOADER */ +#endif /* CONFIG_DUAL_BOOTLOADER && CONFIG_SPL_BUILD */ diff --git a/lib/avb/fsl/fsl_bootctrl.h b/lib/avb/fsl/fsl_bootctrl.h new file mode 100644 index 00000000000..6c7b30738a3 --- /dev/null +++ b/lib/avb/fsl/fsl_bootctrl.h @@ -0,0 +1,161 @@ +/* + * Copyright 2020 NXP + * + */ + +#ifndef __FSL_BOOTCTRL_H__ +#define __FSL_BOOTCTRL_H__ + +#include "android_bootloader_message.h" + +typedef enum { + AVB_AB_FLOW_RESULT_OK, + AVB_AB_FLOW_RESULT_OK_WITH_VERIFICATION_ERROR, + AVB_AB_FLOW_RESULT_ERROR_OOM, + AVB_AB_FLOW_RESULT_ERROR_IO, + AVB_AB_FLOW_RESULT_ERROR_NO_BOOTABLE_SLOTS, + AVB_AB_FLOW_RESULT_ERROR_INVALID_ARGUMENT +} AvbABFlowResult; + +/* High-level operations/functions/methods for A/B that are platform + * dependent. + */ +struct AvbABOps; +typedef struct AvbABOps AvbABOps; + +struct AvbABOps { + /* Operations from libavb. */ + AvbOps* ops; + + /* Reads A/B metadata from persistent storage. Returned data is + * properly byteswapped. Returns AVB_IO_RESULT_OK on success, error + * code otherwise. + * + * If the data read is invalid (e.g. wrong magic or CRC checksum + * failure), the metadata shoule be reset using fsl_avb_ab_data_init() + * and then written to persistent storage. + * + * Implementations will typically want to use fsl_avb_ab_data_read() + * here to use the 'misc' partition for persistent storage. + */ + AvbIOResult (*read_ab_metadata)(AvbABOps* ab_ops, struct bootloader_control* data); + + /* Writes A/B metadata to persistent storage. This will byteswap and + * update the CRC as needed. Returns AVB_IO_RESULT_OK on success, + * error code otherwise. + * + * Implementations will typically want to use fsl_avb_ab_data_write() + * here to use the 'misc' partition for persistent storage. + */ + AvbIOResult (*write_ab_metadata)(AvbABOps* ab_ops, + const struct bootloader_control* data); +}; + +/* Copies |src| to |dest|, byte-swapping fields in the + * process. Returns false if the data is invalid (e.g. wrong magic, + * wrong CRC32 etc.), true otherwise. + */ +bool fsl_avb_ab_data_verify_and_byteswap(const struct bootloader_control* src, + struct bootloader_control* dest); + +/* Copies |src| to |dest|, byte-swapping fields in the process. Also + * updates the |crc32| field in |dest|. + */ +void fsl_avb_ab_data_update_crc_and_byteswap(const struct bootloader_control* src, + struct bootloader_control* dest); + +/* Initializes |data| such that it has two slots and both slots have + * maximum tries remaining. The CRC is not set. + */ +void fsl_avb_ab_data_init(struct bootloader_control* data); + +/* Reads A/B metadata from the 'misc' partition using |ops|. Returned + * data is properly byteswapped. Returns AVB_IO_RESULT_OK on + * success, error code otherwise. + * + * If the data read from disk is invalid (e.g. wrong magic or CRC + * checksum failure), the metadata will be reset using + * fsl_avb_ab_data_init() and then written to disk. + */ +AvbIOResult fsl_avb_ab_data_read(AvbABOps* ab_ops, struct bootloader_control* data); + +/* Writes A/B metadata to the 'misc' partition using |ops|. This will + * byteswap and update the CRC as needed. Returns AVB_IO_RESULT_OK on + * success, error code otherwise. + */ +AvbIOResult fsl_avb_ab_data_write(AvbABOps* ab_ops, const struct bootloader_control* data); + +/* True if the given slot is active, false otherwise. + * */ +bool fsl_slot_is_bootable(struct slot_metadata* slot); + +/* Mark one slot as active. */ +AvbIOResult fsl_avb_ab_mark_slot_active(AvbABOps* ab_ops, + unsigned int slot_number); + +/* This is the fast version of avb_ab_flow(), this function will + * not check another slot if one slot can pass the verify (or verify + * fail is acceptable). + */ +AvbABFlowResult avb_ab_flow_fast(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data); + +/* This is for legacy i.mx6/7 which don't enable A/B but want to + * verify boot/recovery with AVB */ +AvbABFlowResult avb_single_flow(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data); + +/* Avb verify flow for dual bootloader, only the slot chosen by SPL will + * be verified. + */ +AvbABFlowResult avb_flow_dual_uboot(AvbABOps* ab_ops, + const char* const* requested_partitions, + AvbSlotVerifyFlags flags, + AvbHashtreeErrorMode hashtree_error_mode, + AvbSlotVerifyData** out_data); + +/* check if the fastboot getvar cmd is for query [avb] bootctl's slot var + * cmd is the fastboot getvar's cmd in + * return true if it is a bootctl related cmd, false if it's not. + * */ +bool is_slotvar_avb(char *cmd); + +/* Get current bootable slot with higher priority. + * return 0 for the first slot + * return 1 for the second slot + * return -1 for not supported slot + * */ +int get_curr_slot(struct bootloader_control* ab_data); + +/* Get current bootable slot without passing the "bootloader_control" struct. + * return 0 for the first slot + * return 1 for the second slot + * return -1 for not supported slot + * */ +int current_slot(void); + +/* return 0 for the first slot + * return 1 for the second slot + * return -1 for not supported slot + * */ +int slotidx_from_suffix(char *suffix); + +/* return fastboot's getvar cmd response + * cmd is the fastboot getvar's cmd in + * if return 0, buffer is bootctl's slot var out + * if return -1, buffer is error string + * */ + +/* read a/b metadata to get curr slot + * return slot suffix '_a'/'_b' or NULL */ +char *select_slot(AvbABOps *ab_ops); + +int get_slotvar_avb(AvbABOps *ab_ops, char *cmd, char *buffer, size_t size); + +#endif /* __FSL_BOOTCTRL_H__ */ diff --git a/lib/avb/fsl/fsl_public_key.h b/lib/avb/fsl/fsl_public_key.h new file mode 100644 index 00000000000..b3b6d65a3cc --- /dev/null +++ b/lib/avb/fsl/fsl_public_key.h @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_PUBLIC_KEY_H_ +#define __FSL_PUBLIC_KEY_H_ +/*This public key is generated from testkey_rsa4096.pem.*/ +static unsigned char fsl_public_key[] = { + 0x00,0x00,0x10,0x00,0x55,0xd9,0x04,0xad, + 0xd8,0x04,0xaf,0xe3,0xd3,0x84,0x6c,0x7e, + 0x0d,0x89,0x3d,0xc2,0x8c,0xd3,0x12,0x55, + 0xe9,0x62,0xc9,0xf1,0x0f,0x5e,0xcc,0x16, + 0x72,0xab,0x44,0x7c,0x2c,0x65,0x4a,0x94, + 0xb5,0x16,0x2b,0x00,0xbb,0x06,0xef,0x13, + 0x07,0x53,0x4c,0xf9,0x64,0xb9,0x28,0x7a, + 0x1b,0x84,0x98,0x88,0xd8,0x67,0xa4,0x23, + 0xf9,0xa7,0x4b,0xdc,0x4a,0x0f,0xf7,0x3a, + 0x18,0xae,0x54,0xa8,0x15,0xfe,0xb0,0xad, + 0xac,0x35,0xda,0x3b,0xad,0x27,0xbc,0xaf, + 0xe8,0xd3,0x2f,0x37,0x34,0xd6,0x51,0x2b, + 0x6c,0x5a,0x27,0xd7,0x96,0x06,0xaf,0x6b, + 0xb8,0x80,0xca,0xfa,0x30,0xb4,0xb1,0x85, + 0xb3,0x4d,0xaa,0xaa,0xc3,0x16,0x34,0x1a, + 0xb8,0xe7,0xc7,0xfa,0xf9,0x09,0x77,0xab, + 0x97,0x93,0xeb,0x44,0xae,0xcf,0x20,0xbc, + 0xf0,0x80,0x11,0xdb,0x23,0x0c,0x47,0x71, + 0xb9,0x6d,0xd6,0x7b,0x60,0x47,0x87,0x16, + 0x56,0x93,0xb7,0xc2,0x2a,0x9a,0xb0,0x4c, + 0x01,0x0c,0x30,0xd8,0x93,0x87,0xf0,0xed, + 0x6e,0x8b,0xbe,0x30,0x5b,0xf6,0xa6,0xaf, + 0xdd,0x80,0x7c,0x45,0x5e,0x8f,0x91,0x93, + 0x5e,0x44,0xfe,0xb8,0x82,0x07,0xee,0x79, + 0xca,0xbf,0x31,0x73,0x62,0x58,0xe3,0xcd, + 0xc4,0xbc,0xc2,0x11,0x1d,0xa1,0x4a,0xbf, + 0xfe,0x27,0x7d,0xa1,0xf6,0x35,0xa3,0x5e, + 0xca,0xdc,0x57,0x2f,0x3e,0xf0,0xc9,0x5d, + 0x86,0x6a,0xf8,0xaf,0x66,0xa7,0xed,0xcd, + 0xb8,0xed,0xa1,0x5f,0xba,0x9b,0x85,0x1a, + 0xd5,0x09,0xae,0x94,0x4e,0x3b,0xcf,0xcb, + 0x5c,0xc9,0x79,0x80,0xf7,0xcc,0xa6,0x4a, + 0xa8,0x6a,0xd8,0xd3,0x31,0x11,0xf9,0xf6, + 0x02,0x63,0x2a,0x1a,0x2d,0xd1,0x1a,0x66, + 0x1b,0x16,0x41,0xbd,0xbd,0xf7,0x4d,0xc0, + 0x4a,0xe5,0x27,0x49,0x5f,0x7f,0x58,0xe3, + 0x27,0x2d,0xe5,0xc9,0x66,0x0e,0x52,0x38, + 0x16,0x38,0xfb,0x16,0xeb,0x53,0x3f,0xe6, + 0xfd,0xe9,0xa2,0x5e,0x25,0x59,0xd8,0x79, + 0x45,0xff,0x03,0x4c,0x26,0xa2,0x00,0x5a, + 0x8e,0xc2,0x51,0xa1,0x15,0xf9,0x7b,0xf4, + 0x5c,0x81,0x9b,0x18,0x47,0x35,0xd8,0x2d, + 0x05,0xe9,0xad,0x0f,0x35,0x74,0x15,0xa3, + 0x8e,0x8b,0xcc,0x27,0xda,0x7c,0x5d,0xe4, + 0xfa,0x04,0xd3,0x05,0x0b,0xba,0x3a,0xb2, + 0x49,0x45,0x2f,0x47,0xc7,0x0d,0x41,0x3f, + 0x97,0x80,0x4d,0x3f,0xc1,0xb5,0xbb,0x70, + 0x5f,0xa7,0x37,0xaf,0x48,0x22,0x12,0x45, + 0x2e,0xf5,0x0f,0x87,0x92,0xe2,0x84,0x01, + 0xf9,0x12,0x0f,0x14,0x15,0x24,0xce,0x89, + 0x99,0xee,0xb9,0xc4,0x17,0x70,0x70,0x15, + 0xea,0xbe,0xc6,0x6c,0x1f,0x62,0xb3,0xf4, + 0x2d,0x16,0x87,0xfb,0x56,0x1e,0x45,0xab, + 0xae,0x32,0xe4,0x5e,0x91,0xed,0x53,0x66, + 0x5e,0xbd,0xed,0xad,0xe6,0x12,0x39,0x0d, + 0x83,0xc9,0xe8,0x6b,0x6c,0x2d,0xa5,0xee, + 0xc4,0x5a,0x66,0xae,0x8c,0x97,0xd7,0x0d, + 0x6c,0x49,0xc7,0xf5,0xc4,0x92,0x31,0x8b, + 0x09,0xee,0x33,0xda,0xa9,0x37,0xb6,0x49, + 0x18,0xf8,0x0e,0x60,0x45,0xc8,0x33,0x91, + 0xef,0x20,0x57,0x10,0xbe,0x78,0x2d,0x83, + 0x26,0xd6,0xca,0x61,0xf9,0x2f,0xe0,0xbf, + 0x05,0x30,0x52,0x5a,0x12,0x1c,0x00,0xa7, + 0x5d,0xcc,0x7c,0x2e,0xc5,0x95,0x8b,0xa3, + 0x3b,0xf0,0x43,0x2e,0x5e,0xdd,0x00,0xdb, + 0x0d,0xb3,0x37,0x99,0xa9,0xcd,0x9c,0xb7, + 0x43,0xf7,0x35,0x44,0x21,0xc2,0x82,0x71, + 0xab,0x8d,0xaa,0xb4,0x41,0x11,0xec,0x1e, + 0x8d,0xfc,0x14,0x82,0x92,0x4e,0x83,0x6a, + 0x0a,0x6b,0x35,0x5e,0x5d,0xe9,0x5c,0xcc, + 0x8c,0xde,0x39,0xd1,0x4a,0x5b,0x5f,0x63, + 0xa9,0x64,0xe0,0x0a,0xcb,0x0b,0xb8,0x5a, + 0x7c,0xc3,0x0b,0xe6,0xbe,0xfe,0x8b,0x0f, + 0x7d,0x34,0x8e,0x02,0x66,0x74,0x01,0x6c, + 0xca,0x76,0xac,0x7c,0x67,0x08,0x2f,0x3f, + 0x1a,0xa6,0x2c,0x60,0xb3,0xff,0xda,0x8d, + 0xb8,0x12,0x0c,0x00,0x7f,0xcc,0x50,0xa1, + 0x5c,0x64,0xa1,0xe2,0x5f,0x32,0x65,0xc9, + 0x9c,0xbe,0xd6,0x0a,0x13,0x87,0x3c,0x2a, + 0x45,0x47,0x0c,0xca,0x42,0x82,0xfa,0x89, + 0x65,0xe7,0x89,0xb4,0x8f,0xf7,0x1e,0xe6, + 0x23,0xa5,0xd0,0x59,0x37,0x79,0x92,0xd7, + 0xce,0x3d,0xfd,0xe3,0xa1,0x0b,0xcf,0x6c, + 0x85,0xa0,0x65,0xf3,0x5c,0xc6,0x4a,0x63, + 0x5f,0x6e,0x3a,0x3a,0x2a,0x8b,0x6a,0xb6, + 0x2f,0xbb,0xf8,0xb2,0x4b,0x62,0xbc,0x1a, + 0x91,0x25,0x66,0xe3,0x69,0xca,0x60,0x49, + 0x0b,0xf6,0x8a,0xbe,0x3e,0x76,0x53,0xc2, + 0x7a,0xa8,0x04,0x17,0x75,0xf1,0xf3,0x03, + 0x62,0x1b,0x85,0xb2,0xb0,0xef,0x80,0x15, + 0xb6,0xd4,0x4e,0xdf,0x71,0xac,0xdb,0x2a, + 0x04,0xd4,0xb4,0x21,0xba,0x65,0x56,0x57, + 0xe8,0xfa,0x84,0xa2,0x7d,0x13,0x0e,0xaf, + 0xd7,0x9a,0x58,0x2a,0xa3,0x81,0x84,0x8d, + 0x09,0xa0,0x6a,0xc1,0xbb,0xd9,0xf5,0x86, + 0xac,0xbd,0x75,0x61,0x09,0xe6,0x8c,0x3d, + 0x77,0xb2,0xed,0x30,0x20,0xe4,0x00,0x1d, + 0x97,0xe8,0xbf,0xc7,0x00,0x1b,0x21,0xb1, + 0x16,0xe7,0x41,0x67,0x2e,0xec,0x38,0xbc, + 0xe5,0x1b,0xb4,0x06,0x23,0x31,0x71,0x1c, + 0x49,0xcd,0x76,0x4a,0x76,0x36,0x8d,0xa3, + 0x89,0x8b,0x4a,0x7a,0xf4,0x87,0xc8,0x15, + 0x0f,0x37,0x39,0xf6,0x6d,0x80,0x19,0xef, + 0x5c,0xa8,0x66,0xce,0x1b,0x16,0x79,0x21, + 0xdf,0xd7,0x31,0x30,0xc4,0x21,0xdd,0x34, + 0x5b,0xd2,0x1a,0x2b,0x3e,0x5d,0xf7,0xea, + 0xca,0x05,0x8e,0xb7,0xcb,0x49,0x2e,0xa0, + 0xe3,0xf4,0xa7,0x48,0x19,0x10,0x9c,0x04, + 0xa7,0xf4,0x28,0x74,0xc8,0x6f,0x63,0x20, + 0x2b,0x46,0x24,0x26,0x19,0x1d,0xd1,0x2c, + 0x31,0x6d,0x5a,0x29,0xa2,0x06,0xa6,0xb2, + 0x41,0xcc,0x0a,0x27,0x96,0x09,0x96,0xac, + 0x47,0x65,0x78,0x68,0x51,0x98,0xd6,0xd8, + 0xa6,0x2d,0xa0,0xcf,0xec,0xe2,0x74,0xf2, + 0x82,0xe3,0x97,0xd9,0x7e,0xd4,0xf8,0x0b, + 0x70,0x43,0x3d,0xb1,0x7b,0x97,0x80,0xd6, + 0xcb,0xd7,0x19,0xbc,0x63,0x0b,0xfd,0x4d, + 0x88,0xfe,0x67,0xac,0xb8,0xcc,0x50,0xb7, + 0x68,0xb3,0x5b,0xd6,0x1e,0x25,0xfc,0x5f, + 0x3c,0x8d,0xb1,0x33,0x7c,0xb3,0x49,0x01, + 0x3f,0x71,0x55,0x0e,0x51,0xba,0x61,0x26, + 0xfa,0xea,0xe5,0xb5,0xe8,0xaa,0xcf,0xcd, + 0x96,0x9f,0xd6,0xc1,0x5f,0x53,0x91,0xad, + 0x05,0xde,0x20,0xe7,0x51,0xda,0x5b,0x95, + 0x67,0xed,0xf4,0xee,0x42,0x65,0x70,0x13, + 0x0b,0x70,0x14,0x1c,0xc9,0xe0,0x19,0xca, + 0x5f,0xf5,0x1d,0x70,0x4b,0x6c,0x06,0x74, + 0xec,0xb5,0x2e,0x77,0xe1,0x74,0xa1,0xa3, + 0x99,0xa0,0x85,0x9e,0xf1,0xac,0xd8,0x7e +}; + + +#endif diff --git a/lib/avb/fsl/orange_warning_bmp_data.c b/lib/avb/fsl/orange_warning_bmp_data.c new file mode 100644 index 00000000000..49f04bbc59f --- /dev/null +++ b/lib/avb/fsl/orange_warning_bmp_data.c @@ -0,0 +1,1066 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright NXP 2020 + * + */ + +/* + * Note: The orange_warning_bmp_palette[] and orange_warning_bmp_bitmap + * data are generated by "tools/bmp_logo", command: + * "./bmp_logo --gen-bmp source.bmp > bmp_data.c" + * */ + +#include "fsl_avb_logo.h" + +unsigned short orange_warning_bmp_palette[] = { + 0x0000, 0x0233, 0x072E, 0x0E72, 0x02E7, 0x072E, 0x0E72, 0x02E7, + 0x072E, 0x0E72, 0x02E7, 0x072E, 0x0E72, 0x02E7, 0x072E, 0x0E72, + 0x02E7, 0x072E, 0x0E72, 0x02E7, 0x072E, 0x0E72, 0x02E7, 0x072E, + 0x0E72, 0x02E7, 0x072E, 0x0E72, 0x02E7, 0x072E, 0x0E72, 0x02E7, + 0x072E, 0x0E72, 0x02E7, 0x072E, 0x0E72, 0x02E7, 0x072E, 0x0E72, + 0x01E7, 0x0207, 0x0000, 0x02C6, 0x072F, 0x0F72, 0x02F7, 0x072F, + 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, + 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, + 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, + 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, + 0x072F, 0x0F72, 0x02F7, 0x030F, 0x0000, 0x0211, 0x072F, 0x0F72, + 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, + 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, + 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, + 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, + 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x000E, 0x0000, 0x0000, + 0x0824, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, + 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, + 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, + 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, + 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x00F8, 0x0002, + 0x0000, 0x0000, 0x0720, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, + 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, + 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, + 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, + 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, + 0x00D7, 0x0000, 0x0000, 0x0000, 0x0100, 0x0F82, 0x02F7, 0x072F, + 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, + 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, + 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, 0x0F72, 0x02F7, 0x072F, + +}; + +unsigned char orange_warning_bmp_bitmap[] = { + 0x42, 0x4D, 0xB6, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x36, 0x00, 0x00, 0x00, 0x28, 0x00, + 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x30, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x18, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC4, 0x0E, + 0x00, 0x00, 0xC4, 0x0E, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x05, + 0x05, 0x0C, 0x30, 0x34, 0x24, 0x7A, 0xE3, 0x25, + 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, + 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, + 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, + 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, + 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, + 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, + 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, + 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, + 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, + 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, + 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, + 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, + 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, + 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, + 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, + 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, + 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, + 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, + 0x7D, 0xEA, 0x25, 0x7D, 0xEA, 0x25, 0x7D, 0xEA, + 0x1B, 0x6C, 0x75, 0x0C, 0x2E, 0x33, 0x01, 0x05, + 0x06, 0x20, 0x6E, 0xC7, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x80, 0xFE, 0x0E, 0x36, 0x3A, 0x00, 0x00, + 0x00, 0x06, 0x16, 0x18, 0x26, 0x7F, 0xF1, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x25, 0x7B, 0xE6, 0x03, 0x0D, 0x0E, 0x00, 0x00, + 0x00, 0x01, 0x03, 0x03, 0x0F, 0x3E, 0x43, 0x27, + 0x80, 0xFE, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, + 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, + 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x80, 0xFD, + 0x0A, 0x26, 0x2A, 0x00, 0x01, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x03, 0x0C, 0x0D, 0x24, + 0x79, 0xDF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, + 0x27, 0x7F, 0xFF, 0x27, 0x7F, 0xFF, 0x27, 0x7F, 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+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x05, 0x13, 0x14, 0x26, + 0x7E, 0xED, 0x27, 0x7F, 0xFF, 0x25, 0x7C, 0xE6, + 0x04, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 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+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, + 0x08, 0x09, 0x05, 0x13, 0x14, 0x01, 0x04, 0x04, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + diff --git a/lib/avb/fsl/utils.c b/lib/avb/fsl/utils.c new file mode 100644 index 00000000000..52ac1bd2a1c --- /dev/null +++ b/lib/avb/fsl/utils.c @@ -0,0 +1,216 @@ +/* ++ * Copyright (C) 2016 Freescale Semiconductor, Inc. ++ * Copyright 2018 NXP ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ +#include +#include +#include + +#include "debug.h" +#include "utils.h" + +/* + * get margin_pos struct from offset [to the partition start/end] and + * num_bytes to read/write + */ +int get_margin_pos(long part_start, long part_end, long blksz, + margin_pos_t *margin, long offset, size_t num_bytes, + bool allow_partial) { + long off; + if (margin == NULL) + return -1; + + if (blksz == 0 || part_start > part_end) + return -1; + + if (offset < 0) { + margin->blk_start = (offset + 1) / blksz + part_end; + // offset == -1 means the last byte?, or start need -1 + margin->start = (off = offset % blksz) == 0 ? + 0 : blksz + off; + if (offset + num_bytes - 1 >= 0) { + if (!allow_partial) + return -1; + margin->blk_end = part_end; + margin->end = blksz - 1; + } else { + // which blk the last byte is in + margin->blk_end = (num_bytes + offset) / + blksz + part_end; + margin->end = (off = (num_bytes + offset - 1) % blksz) == 0 ? + 0 : blksz + off; // last byte + } + } else { + margin->blk_start = offset / blksz + part_start; + margin->start = offset % blksz; + margin->blk_end = ((offset + num_bytes - 1) / blksz) + + part_start ; + margin->end = (offset + num_bytes - 1) % blksz; + if (margin->blk_end > part_end) { + if (!allow_partial) + return -1; + margin->blk_end = part_end; + margin->end = blksz - 1; + } + } + VDEBUG("bs=%ld, be=%ld, s=%ld, e=%ld\n", + margin->blk_start, margin->blk_end, margin->start, margin->end); + + if (margin->blk_start > part_end || margin->blk_start < part_start) + return -1; + long multi = margin->blk_end - margin->blk_start - 1 + + (margin->start == 0) + (margin->end == blksz -1); + margin->multi = multi > 0 ? multi : 0; + VDEBUG("bm=%ld\n", margin->multi); + return 0; +} + +int read_from_partition_in_bytes(struct blk_desc *fs_dev_desc, + struct disk_partition *info, int64_t offset, + size_t num_bytes, void* buffer, + size_t* out_num_read) +{ + unsigned char *bdata; + unsigned char *out_buf = (unsigned char *)buffer; + unsigned char *dst, *dst64 = NULL; + unsigned long blksz; + unsigned long s, cnt; + size_t num_read = 0; + lbaint_t part_start, part_end, bs, be, bm, blk_num; + margin_pos_t margin; + int ret; + + if(buffer == NULL || out_num_read == NULL) { + printf("NULL pointer error!\n"); + return -1; + } + + blksz = fs_dev_desc->blksz; + part_start = info->start; + part_end = info->start + info->size - 1; + + if (get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, true)) + return -1; + + bs = (lbaint_t)margin.blk_start; + be = (lbaint_t)margin.blk_end; + s = margin.start; + bm = margin.multi; + + /* alloc a blksz mem */ + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) { + printf("Failed to allocate memory!\n"); + return -1; + } + + /* support multi blk read */ + while (bs <= be) { + if (!s && bm > 1) { + dst = out_buf; + /* for mmc blk read alignment */ + dst64 = PTR_ALIGN(out_buf, 64); + if (dst64 != dst) { + dst = dst64; + bm--; + } + blk_num = bm; + cnt = bm * blksz; + bm = 0; /* no more multi blk */ + } else { + blk_num = 1; + cnt = blksz - s; + if (num_read + cnt > num_bytes) + cnt = num_bytes - num_read; + dst = bdata; + } + if (!blk_dread(fs_dev_desc, bs, blk_num, dst)) { + ret = -1; + goto fail; + } + + if (dst == bdata) + memcpy(out_buf, bdata + s, cnt); + else if (dst == dst64) + memcpy(out_buf, dst, cnt); /* internal copy */ + + s = 0; + bs += blk_num; + num_read += cnt; + out_buf += cnt; + } + *out_num_read = num_read; + ret = 0; + +fail: + free(bdata); + return ret; +} + +int write_to_partition_in_bytes(struct blk_desc *fs_dev_desc, + struct disk_partition *info, int64_t offset, + size_t num_bytes, + void* buffer, size_t *out_num_write) +{ + unsigned char *bdata; + unsigned char *in_buf = (unsigned char *)buffer; + unsigned long blksz; + unsigned long s, cnt; + size_t num_write = 0; + lbaint_t part_start, part_end, bs; + margin_pos_t margin; + int ret; + + if(buffer == NULL || out_num_write == NULL) { + printf("NULL pointer error!\n"); + return -1; + } + + blksz = fs_dev_desc->blksz; + part_start = info->start; + part_end = info->start + info->size - 1; + + if(get_margin_pos((uint64_t)part_start, (uint64_t)part_end, blksz, + &margin, offset, num_bytes, false)) + return -1; + + bs = (lbaint_t)margin.blk_start; + s = margin.start; + + // alloc a blksz mem + bdata = (unsigned char *)memalign(ALIGN_BYTES, blksz); + if (bdata == NULL) + return -1; + + while (num_write < num_bytes) { + memset(bdata, 0, blksz); + cnt = blksz - s; + if (num_write + cnt > num_bytes) + cnt = num_bytes - num_write; + if (!s || cnt != blksz) { //read blk first + if (!blk_dread(fs_dev_desc, bs, 1, + bdata)) { + ret = -1; + goto fail; + } + } + memcpy(bdata + s, in_buf, cnt); //change data + if (!blk_dwrite(fs_dev_desc, bs, 1, bdata)) { + ret = -1; + goto fail; + } + bs++; + num_write += cnt; + in_buf += cnt; + s = 0; + } + *out_num_write = num_write; + ret = 0; + +fail: + free(bdata); + return ret; +} diff --git a/lib/avb/fsl/utils.h b/lib/avb/fsl/utils.h new file mode 100644 index 00000000000..60172a71e33 --- /dev/null +++ b/lib/avb/fsl/utils.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __UTILS_H__ +#define __UTILS_H__ + +#include + +#define ALIGN_BYTES 64 /*mmc block read/write need 64 bytes aligned */ + +struct margin_pos { + /* which blk the read/write starts */ + uint64_t blk_start; + /* which blk the read/write ends */ + uint64_t blk_end; + /* start position inside the start blk */ + unsigned long start; + /* end position inside the end blk */ + unsigned long end; + /* how many blks can be read/write one time */ + unsigned long multi; +}; +typedef struct margin_pos margin_pos_t; + +int get_margin_pos(long part_start, long part_end, long blksz, + margin_pos_t *margin, long offset, size_t num_bytes, + bool allow_partial); + +int read_from_partition_in_bytes(struct blk_desc *fs_dev_desc, + struct disk_partition *info, + int64_t offset, size_t num_bytes, + void* buffer, size_t* out_num_read); + +int write_to_partition_in_bytes(struct blk_desc *fs_dev_desc, + struct disk_partition *info, int64_t offset, + size_t num_bytes, void* buffer, + size_t *out_num_write); + +#endif diff --git a/lib/avb/libavb_atx/Makefile b/lib/avb/libavb_atx/Makefile new file mode 100644 index 00000000000..bdd7bccbeb0 --- /dev/null +++ b/lib/avb/libavb_atx/Makefile @@ -0,0 +1,2 @@ +ccflags-y += -DAVB_COMPILATION +obj-y += avb_atx_validate.o diff --git a/lib/avb/libavb_atx/avb_atx_ops.h b/lib/avb/libavb_atx/avb_atx_ops.h new file mode 100644 index 00000000000..e7bd686f3d7 --- /dev/null +++ b/lib/avb/libavb_atx/avb_atx_ops.h @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_ATX_H) && !defined(AVB_COMPILATION) +#error \ + "Never include this file directly, include libavb_atx/libavb_atx.h instead." +#endif + +#ifndef AVB_ATX_OPS_H_ +#define AVB_ATX_OPS_H_ + +#include <../lib/libavb/libavb.h> + +#include "avb_atx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct AvbAtxOps; +typedef struct AvbAtxOps AvbAtxOps; + +/* An extension to AvbOps required by avb_atx_validate_vbmeta_public_key(). */ +struct AvbAtxOps { + /* Operations from libavb. */ + AvbOps* ops; + + /* Reads permanent |attributes| data. There are no restrictions on where this + * data is stored. On success, returns AVB_IO_RESULT_OK and populates + * |attributes|. + */ + AvbIOResult (*read_permanent_attributes)( + AvbAtxOps* atx_ops, AvbAtxPermanentAttributes* attributes); + + /* Reads a |hash| of permanent attributes. This hash MUST be retrieved from a + * permanently read-only location (e.g. fuses) when a device is LOCKED. On + * success, returned AVB_IO_RESULT_OK and populates |hash|. + */ + AvbIOResult (*read_permanent_attributes_hash)( + AvbAtxOps* atx_ops, uint8_t hash[AVB_SHA256_DIGEST_SIZE]); + + /* Provides the key version of a key used during verification. This may be + * useful for managing the minimum key version. + */ + void (*set_key_version)(AvbAtxOps* atx_ops, + size_t rollback_index_location, + uint64_t key_version); + + /* Generates |num_bytes| random bytes and stores them in |output|, + * which must point to a buffer large enough to store the bytes. + * + * Returns AVB_IO_RESULT_OK on success, otherwise an error code. + */ + AvbIOResult (*get_random)(AvbAtxOps* atx_ops, + size_t num_bytes, + uint8_t* output); +}; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_ATX_OPS_H_ */ diff --git a/lib/avb/libavb_atx/avb_atx_types.h b/lib/avb/libavb_atx/avb_atx_types.h new file mode 100644 index 00000000000..a4563c0d080 --- /dev/null +++ b/lib/avb/libavb_atx/avb_atx_types.h @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_ATX_H) && !defined(AVB_COMPILATION) +#error \ + "Never include this file directly, include libavb_atx/libavb_atx.h instead." +#endif + +#ifndef AVB_ATX_TYPES_H_ +#define AVB_ATX_TYPES_H_ + +#include <../lib/libavb/libavb.h> + +#ifdef __cplusplus +extern "C" { +#endif + +/* Size in bytes of an Android Things product ID. */ +#define AVB_ATX_PRODUCT_ID_SIZE 16 + +/* Size in bytes of an Android Things unlock challenge. */ +#define AVB_ATX_UNLOCK_CHALLENGE_SIZE 16 + +/* Size in bytes of a serialized public key with a 4096-bit modulus. */ +#define AVB_ATX_PUBLIC_KEY_SIZE (sizeof(AvbRSAPublicKeyHeader) + 1024) + +/* Data structure of Android Things permanent attributes. */ +typedef struct AvbAtxPermanentAttributes { + uint32_t version; + uint8_t product_root_public_key[AVB_ATX_PUBLIC_KEY_SIZE]; + uint8_t product_id[AVB_ATX_PRODUCT_ID_SIZE]; +} AVB_ATTR_PACKED AvbAtxPermanentAttributes; + +/* Data structure of signed fields in an Android Things certificate. */ +typedef struct AvbAtxCertificateSignedData { + uint32_t version; + uint8_t public_key[AVB_ATX_PUBLIC_KEY_SIZE]; + uint8_t subject[AVB_SHA256_DIGEST_SIZE]; + uint8_t usage[AVB_SHA256_DIGEST_SIZE]; + uint64_t key_version; +} AVB_ATTR_PACKED AvbAtxCertificateSignedData; + +/* Data structure of an Android Things certificate. */ +typedef struct AvbAtxCertificate { + AvbAtxCertificateSignedData signed_data; + uint8_t signature[AVB_RSA4096_NUM_BYTES]; +} AVB_ATTR_PACKED AvbAtxCertificate; + +/* Data structure of Android Things public key metadata in vbmeta. */ +typedef struct AvbAtxPublicKeyMetadata { + uint32_t version; + AvbAtxCertificate product_intermediate_key_certificate; + AvbAtxCertificate product_signing_key_certificate; +} AVB_ATTR_PACKED AvbAtxPublicKeyMetadata; + +/* Data structure of an Android Things unlock challenge. */ +typedef struct AvbAtxUnlockChallenge { + uint32_t version; + uint8_t product_id_hash[AVB_SHA256_DIGEST_SIZE]; + uint8_t challenge[AVB_ATX_UNLOCK_CHALLENGE_SIZE]; +} AVB_ATTR_PACKED AvbAtxUnlockChallenge; + +/* Data structure of an Android Things unlock credential. */ +typedef struct AvbAtxUnlockCredential { + uint32_t version; + AvbAtxCertificate product_intermediate_key_certificate; + AvbAtxCertificate product_unlock_key_certificate; + uint8_t challenge_signature[AVB_RSA4096_NUM_BYTES]; +} AVB_ATTR_PACKED AvbAtxUnlockCredential; + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_ATX_TYPES_H_ */ diff --git a/lib/avb/libavb_atx/avb_atx_validate.c b/lib/avb/libavb_atx/avb_atx_validate.c new file mode 100644 index 00000000000..f3c1d968412 --- /dev/null +++ b/lib/avb/libavb_atx/avb_atx_validate.c @@ -0,0 +1,401 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include "avb_atx_validate.h" + +#include +#include +#include +#include + +/* The most recent unlock challenge generated. */ +static uint8_t last_unlock_challenge[AVB_ATX_UNLOCK_CHALLENGE_SIZE]; + +/* Computes the SHA256 |hash| of |length| bytes of |data|. */ +static void sha256(const uint8_t* data, + uint32_t length, + uint8_t hash[AVB_SHA256_DIGEST_SIZE]) { + AvbSHA256Ctx context; + avb_sha256_init(&context); + avb_sha256_update(&context, data, length); + uint8_t* tmp = avb_sha256_final(&context); + avb_memcpy(hash, tmp, AVB_SHA256_DIGEST_SIZE); +} + +/* Computes the SHA512 |hash| of |length| bytes of |data|. */ +static void sha512(const uint8_t* data, + uint32_t length, + uint8_t hash[AVB_SHA512_DIGEST_SIZE]) { + AvbSHA512Ctx context; + avb_sha512_init(&context); + avb_sha512_update(&context, data, length); + uint8_t* tmp = avb_sha512_final(&context); + avb_memcpy(hash, tmp, AVB_SHA512_DIGEST_SIZE); +} + +/* Computes the SHA256 |hash| of a NUL-terminated |str|. */ +static void sha256_str(const char* str, uint8_t hash[AVB_SHA256_DIGEST_SIZE]) { + sha256((const uint8_t*)str, avb_strlen(str), hash); +} + +/* Verifies structure and |expected_hash| of permanent |attributes|. */ +static bool verify_permanent_attributes( + const AvbAtxPermanentAttributes* attributes, + const uint8_t expected_hash[AVB_SHA256_DIGEST_SIZE]) { + uint8_t hash[AVB_SHA256_DIGEST_SIZE]; + + if (attributes->version != 1) { + avb_error("Unsupported permanent attributes version.\n"); + return false; + } + sha256((const uint8_t*)attributes, sizeof(AvbAtxPermanentAttributes), hash); + if (0 != avb_safe_memcmp(hash, expected_hash, AVB_SHA256_DIGEST_SIZE)) { + avb_error("Invalid permanent attributes.\n"); + return false; + } + return true; +} + +/* Verifies the format, key version, usage, and signature of a certificate. */ +static bool verify_certificate( + const AvbAtxCertificate* certificate, + const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE], + uint64_t minimum_key_version, + const uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE]) { + const AvbAlgorithmData* algorithm_data; + uint8_t certificate_hash[AVB_SHA512_DIGEST_SIZE]; + + if (certificate->signed_data.version != 1) { + avb_error("Unsupported certificate format.\n"); + return false; + } + algorithm_data = avb_get_algorithm_data(AVB_ALGORITHM_TYPE_SHA512_RSA4096); + sha512((const uint8_t*)&certificate->signed_data, + sizeof(AvbAtxCertificateSignedData), + certificate_hash); + if (!avb_rsa_verify(authority, + AVB_ATX_PUBLIC_KEY_SIZE, + certificate->signature, + AVB_RSA4096_NUM_BYTES, + certificate_hash, + AVB_SHA512_DIGEST_SIZE, + algorithm_data->padding, + algorithm_data->padding_len)) { + avb_error("Invalid certificate signature.\n"); + return false; + } + if (certificate->signed_data.key_version < minimum_key_version) { + avb_error("Key rollback detected.\n"); + return false; + } + if (0 != avb_safe_memcmp(certificate->signed_data.usage, + expected_usage, + AVB_SHA256_DIGEST_SIZE)) { + avb_error("Invalid certificate usage.\n"); + return false; + } + return true; +} + +/* Verifies signature and fields of a PIK certificate. */ +static bool verify_pik_certificate( + const AvbAtxCertificate* certificate, + const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE], + uint64_t minimum_version) { + uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE]; + + sha256_str("com.google.android.things.vboot.ca", expected_usage); + if (!verify_certificate( + certificate, authority, minimum_version, expected_usage)) { + avb_error("Invalid PIK certificate.\n"); + return false; + } + return true; +} + +/* Verifies signature and fields of a PSK certificate. */ +static bool verify_psk_certificate( + const AvbAtxCertificate* certificate, + const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE], + uint64_t minimum_version, + const uint8_t product_id[AVB_ATX_PRODUCT_ID_SIZE]) { + uint8_t expected_subject[AVB_SHA256_DIGEST_SIZE]; + uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE]; + + sha256_str("com.google.android.things.vboot", expected_usage); + if (!verify_certificate( + certificate, authority, minimum_version, expected_usage)) { + avb_error("Invalid PSK certificate.\n"); + return false; + } + sha256(product_id, AVB_ATX_PRODUCT_ID_SIZE, expected_subject); + if (0 != avb_safe_memcmp(certificate->signed_data.subject, + expected_subject, + AVB_SHA256_DIGEST_SIZE)) { + avb_error("PSK: Product ID mismatch.\n"); + return false; + } + return true; +} + +/* Verifies signature and fields of a PUK certificate. */ +static bool verify_puk_certificate( + const AvbAtxCertificate* certificate, + const uint8_t authority[AVB_ATX_PUBLIC_KEY_SIZE], + uint64_t minimum_version, + const uint8_t product_id[AVB_ATX_PRODUCT_ID_SIZE]) { + uint8_t expected_subject[AVB_SHA256_DIGEST_SIZE]; + uint8_t expected_usage[AVB_SHA256_DIGEST_SIZE]; + + sha256_str("com.google.android.things.vboot.unlock", expected_usage); + if (!verify_certificate( + certificate, authority, minimum_version, expected_usage)) { + avb_error("Invalid PUK certificate.\n"); + return false; + } + sha256(product_id, AVB_ATX_PRODUCT_ID_SIZE, expected_subject); + if (0 != avb_safe_memcmp(certificate->signed_data.subject, + expected_subject, + AVB_SHA256_DIGEST_SIZE)) { + avb_error("PUK: Product ID mismatch.\n"); + return false; + } + return true; +} + +AvbIOResult avb_atx_validate_vbmeta_public_key( + AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted) { + AvbIOResult result = AVB_IO_RESULT_OK; + AvbAtxPermanentAttributes permanent_attributes; + uint8_t permanent_attributes_hash[AVB_SHA256_DIGEST_SIZE]; + AvbAtxPublicKeyMetadata metadata; + uint64_t minimum_version; + + /* Be pessimistic so we can exit early without having to remember to clear. + */ + *out_is_trusted = false; + + /* Read and verify permanent attributes. */ + result = ops->atx_ops->read_permanent_attributes(ops->atx_ops, + &permanent_attributes); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes.\n"); + return result; + } + result = ops->atx_ops->read_permanent_attributes_hash( + ops->atx_ops, permanent_attributes_hash); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes hash.\n"); + return result; + } + if (!verify_permanent_attributes(&permanent_attributes, + permanent_attributes_hash)) { + return AVB_IO_RESULT_OK; + } + + /* Sanity check public key metadata. */ + if (public_key_metadata_length != sizeof(AvbAtxPublicKeyMetadata)) { + avb_error("Invalid public key metadata.\n"); + return AVB_IO_RESULT_OK; + } + avb_memcpy(&metadata, public_key_metadata, sizeof(AvbAtxPublicKeyMetadata)); + if (metadata.version != 1) { + avb_error("Unsupported public key metadata.\n"); + return AVB_IO_RESULT_OK; + } + + /* Verify the PIK certificate. */ + result = ops->read_rollback_index( + ops, AVB_ATX_PIK_VERSION_LOCATION, &minimum_version); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read PIK minimum version.\n"); + return result; + } + if (!verify_pik_certificate(&metadata.product_intermediate_key_certificate, + permanent_attributes.product_root_public_key, + minimum_version)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the PSK certificate. */ + result = ops->read_rollback_index( + ops, AVB_ATX_PSK_VERSION_LOCATION, &minimum_version); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read PSK minimum version.\n"); + return result; + } + if (!verify_psk_certificate( + &metadata.product_signing_key_certificate, + metadata.product_intermediate_key_certificate.signed_data.public_key, + minimum_version, + permanent_attributes.product_id)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the PSK is the same key that verified vbmeta. */ + if (public_key_length != AVB_ATX_PUBLIC_KEY_SIZE) { + avb_error("Public key length mismatch.\n"); + return AVB_IO_RESULT_OK; + } + if (0 != avb_safe_memcmp( + metadata.product_signing_key_certificate.signed_data.public_key, + public_key_data, + AVB_ATX_PUBLIC_KEY_SIZE)) { + avb_error("Public key mismatch.\n"); + return AVB_IO_RESULT_OK; + } + + /* Report the key versions used during verification. */ + ops->atx_ops->set_key_version( + ops->atx_ops, + AVB_ATX_PIK_VERSION_LOCATION, + metadata.product_intermediate_key_certificate.signed_data.key_version); + ops->atx_ops->set_key_version( + ops->atx_ops, + AVB_ATX_PSK_VERSION_LOCATION, + metadata.product_signing_key_certificate.signed_data.key_version); + + *out_is_trusted = true; + return AVB_IO_RESULT_OK; +} + +AvbIOResult avb_atx_generate_unlock_challenge( + AvbAtxOps* atx_ops, AvbAtxUnlockChallenge* out_unlock_challenge) { + AvbIOResult result = AVB_IO_RESULT_OK; + AvbAtxPermanentAttributes permanent_attributes; + + /* We need the permanent attributes to compute the product_id_hash. */ + result = atx_ops->read_permanent_attributes(atx_ops, &permanent_attributes); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes.\n"); + return result; + } + result = atx_ops->get_random( + atx_ops, AVB_ATX_UNLOCK_CHALLENGE_SIZE, last_unlock_challenge); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to generate random challenge.\n"); + return result; + } + out_unlock_challenge->version = 1; + sha256(permanent_attributes.product_id, + AVB_ATX_PRODUCT_ID_SIZE, + out_unlock_challenge->product_id_hash); + avb_memcpy(out_unlock_challenge->challenge, + last_unlock_challenge, + AVB_ATX_UNLOCK_CHALLENGE_SIZE); + return result; +} + +AvbIOResult avb_atx_validate_unlock_credential( + AvbAtxOps* atx_ops, + const AvbAtxUnlockCredential* unlock_credential, + bool* out_is_trusted) { + AvbIOResult result = AVB_IO_RESULT_OK; + AvbAtxPermanentAttributes permanent_attributes; + uint8_t permanent_attributes_hash[AVB_SHA256_DIGEST_SIZE]; + uint64_t minimum_version; + const AvbAlgorithmData* algorithm_data; + uint8_t challenge_hash[AVB_SHA512_DIGEST_SIZE]; + + /* Be pessimistic so we can exit early without having to remember to clear. + */ + *out_is_trusted = false; + + /* Sanity check the credential. */ + if (unlock_credential->version != 1) { + avb_error("Unsupported unlock credential format.\n"); + return AVB_IO_RESULT_OK; + } + + /* Read and verify permanent attributes. */ + result = atx_ops->read_permanent_attributes(atx_ops, &permanent_attributes); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes.\n"); + return result; + } + result = atx_ops->read_permanent_attributes_hash(atx_ops, + permanent_attributes_hash); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read permanent attributes hash.\n"); + return result; + } + if (!verify_permanent_attributes(&permanent_attributes, + permanent_attributes_hash)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the PIK certificate. */ + result = atx_ops->ops->read_rollback_index( + atx_ops->ops, AVB_ATX_PIK_VERSION_LOCATION, &minimum_version); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read PIK minimum version.\n"); + return result; + } + if (!verify_pik_certificate( + &unlock_credential->product_intermediate_key_certificate, + permanent_attributes.product_root_public_key, + minimum_version)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the PUK certificate. The minimum version is shared with the PSK. */ + result = atx_ops->ops->read_rollback_index( + atx_ops->ops, AVB_ATX_PSK_VERSION_LOCATION, &minimum_version); + if (result != AVB_IO_RESULT_OK) { + avb_error("Failed to read PSK minimum version.\n"); + return result; + } + if (!verify_puk_certificate( + &unlock_credential->product_unlock_key_certificate, + unlock_credential->product_intermediate_key_certificate.signed_data + .public_key, + minimum_version, + permanent_attributes.product_id)) { + return AVB_IO_RESULT_OK; + } + + /* Verify the challenge signature. */ + algorithm_data = avb_get_algorithm_data(AVB_ALGORITHM_TYPE_SHA512_RSA4096); + sha512(last_unlock_challenge, AVB_ATX_UNLOCK_CHALLENGE_SIZE, challenge_hash); + if (!avb_rsa_verify(unlock_credential->product_unlock_key_certificate + .signed_data.public_key, + AVB_ATX_PUBLIC_KEY_SIZE, + unlock_credential->challenge_signature, + AVB_RSA4096_NUM_BYTES, + challenge_hash, + AVB_SHA512_DIGEST_SIZE, + algorithm_data->padding, + algorithm_data->padding_len)) { + avb_error("Invalid unlock challenge signature.\n"); + return AVB_IO_RESULT_OK; + } + + *out_is_trusted = true; + return AVB_IO_RESULT_OK; +} diff --git a/lib/avb/libavb_atx/avb_atx_validate.h b/lib/avb/libavb_atx/avb_atx_validate.h new file mode 100644 index 00000000000..1a0690d4913 --- /dev/null +++ b/lib/avb/libavb_atx/avb_atx_validate.h @@ -0,0 +1,91 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if !defined(AVB_INSIDE_LIBAVB_ATX_H) && !defined(AVB_COMPILATION) +#error \ + "Never include this file directly, include libavb_atx/libavb_atx.h instead." +#endif + +#ifndef AVB_ATX_VALIDATE_H_ +#define AVB_ATX_VALIDATE_H_ + +#include "avb_atx_ops.h" +#include "avb_atx_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Rollback index locations for Android Things key versions. */ +#define AVB_ATX_PIK_VERSION_LOCATION 0x1000 +#define AVB_ATX_PSK_VERSION_LOCATION 0x1001 + +/* An implementation of validate_vbmeta_public_key for Android Things. See + * libavb/avb_ops.h for details on validate_vbmeta_public_key in general. This + * implementation uses the metadata expected with Android Things vbmeta images + * to perform validation on the public key. The ATX ops must be implemented. + * That is, |ops->atx_ops| must be valid. + * + * There are a multiple values that need verification: + * - Permanent Product Attributes: A hash of these attributes is fused into + * hardware. Consistency is checked. + * - Product Root Key (PRK): This key is provided in permanent attributes and + * is the root authority for all Android Things + * products. + * - Product Intermediate Key (PIK): This key is a rotated intermediary. It is + * certified by the PRK. + * - Product Signing Key (PSK): This key is a rotated authority for a specific + * Android Things product. It is certified by a + * PIK and must match |public_key_data|. + * - Product ID: This value is provided in permanent attributes and is unique + * to a specific Android Things product. This value must match + * the subject of the PSK certificate. + */ +AvbIOResult avb_atx_validate_vbmeta_public_key( + AvbOps* ops, + const uint8_t* public_key_data, + size_t public_key_length, + const uint8_t* public_key_metadata, + size_t public_key_metadata_length, + bool* out_is_trusted); + +/* Generates a challenge which can be used to create an unlock credential. */ +AvbIOResult avb_atx_generate_unlock_challenge( + AvbAtxOps* atx_ops, AvbAtxUnlockChallenge* out_unlock_challenge); + +/* Validates an unlock credential. The certificate validation is very similar to + * the validation of public key metadata except in place of the PSK is a Product + * Unlock Key (PUK) and the certificate usage field identifies it as such. The + * challenge signature field is verified against this PUK. + */ +AvbIOResult avb_atx_validate_unlock_credential( + AvbAtxOps* atx_ops, + const AvbAtxUnlockCredential* unlock_credential, + bool* out_is_trusted); + +#ifdef __cplusplus +} +#endif + +#endif /* AVB_ATX_VALIDATE_H_ */ diff --git a/lib/avb/libavb_atx/libavb_atx.h b/lib/avb/libavb_atx/libavb_atx.h new file mode 100644 index 00000000000..3d830ac831e --- /dev/null +++ b/lib/avb/libavb_atx/libavb_atx.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef LIBAVB_ATX_H_ +#define LIBAVB_ATX_H_ + +#include <../lib/libavb/libavb.h> + +/* The AVB_INSIDE_LIBAVB_ATX_H preprocessor symbol is used to enforce + * library users to include only this file. All public interfaces, and + * only public interfaces, must be included here. + */ + +#define AVB_INSIDE_LIBAVB_ATX_H +#include "avb_atx_ops.h" +#include "avb_atx_types.h" +#include "avb_atx_validate.h" +#undef AVB_INSIDE_LIBAVB_ATX_H + +#endif /* LIBAVB_ATX_H_ */ diff --git a/lib/crypto/pkcs7_verify.c b/lib/crypto/pkcs7_verify.c index 58683ef614c..284e61c29ae 100644 --- a/lib/crypto/pkcs7_verify.c +++ b/lib/crypto/pkcs7_verify.c @@ -529,7 +529,6 @@ static int pkcs7_verify_one(struct pkcs7_message *pkcs7, if (sinfo->signing_time < sinfo->signer->valid_from || sinfo->signing_time > sinfo->signer->valid_to) { pr_warn("Message signed outside of X.509 validity window\n"); - return -EKEYREJECTED; } } diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c index 8ece8e71ee1..214dfe985bb 100644 --- a/lib/efi_loader/efi_file.c +++ b/lib/efi_loader/efi_file.c @@ -515,7 +515,7 @@ static efi_status_t efi_file_read_int(struct efi_file_handle *this, efi_status_t ret = EFI_SUCCESS; u64 bs; - if (!this || !buffer_size || !buffer) + if (!this || !buffer_size) return EFI_INVALID_PARAMETER; bs = *buffer_size; diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c index f53ef367ec1..5717be5227b 100644 --- a/lib/efi_loader/efi_image_loader.c +++ b/lib/efi_loader/efi_image_loader.c @@ -27,6 +27,7 @@ const efi_guid_t efi_guid_loaded_image_device_path = const efi_guid_t efi_simple_file_system_protocol_guid = EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_GUID; const efi_guid_t efi_file_info_guid = EFI_FILE_INFO_GUID; +const efi_guid_t efi_memory_only_reset_control_guid = EFI_MEMORY_ONLY_RESET_CONTROL_GUID; static int machines[] = { #if defined(__aarch64__) @@ -715,6 +716,18 @@ efi_status_t efi_check_pe(void *buffer, size_t size, void **nt_header) return EFI_SUCCESS; } +extern int autnenticate_buffer(void *buffer, size_t size); +efi_status_t efi_check_csf(void *buffer, size_t size, void **nt_header) +{ +#if defined(CONFIG_IMX_HAB) && !defined(CONFIG_AVB_SUPPORT) + if (authenticate_buffer( (uint32_t) buffer, size )) { + return EFI_SECURITY_VIOLATION; + } else { + return EFI_SUCCESS; + } +#endif + return EFI_SUCCESS; +} /** * efi_load_pe() - relocate EFI binary * @@ -751,6 +764,12 @@ efi_status_t efi_load_pe(struct efi_loaded_image_obj *handle, return EFI_LOAD_ERROR; } + ret = efi_check_csf(efi, efi_size, (void **)&nt); + if (ret != EFI_SUCCESS) { + log_err("CSF Errot\n"); + return EFI_LOAD_ERROR; + } + for (i = 0; machines[i]; i++) if (machines[i] == nt->FileHeader.Machine) { supported = 1; diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index b1c5125032b..6d01524212e 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -6,11 +6,15 @@ */ #include +#include #include #include +#include #define OBJ_LIST_NOT_INITIALIZED 1 +DECLARE_GLOBAL_DATA_PTR; + efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED; /* @@ -171,6 +175,68 @@ static efi_status_t efi_init_os_indications(void) &os_indications_supported, false); } +/** + * efi_init_memory_only_reset_control() - indicate supported features for + * OS requests + * + * Set the MemoryOverwriteRequestControl variable. + * + * Return: status code + */ +static efi_status_t efi_init_memory_only_reset_control(void) +{ + u8 memory_only_reset_control = 0; + efi_status_t ret; + efi_uintn_t data_size = 0; + + data_size = sizeof(memory_only_reset_control); + ret = efi_get_variable_int(L"MemoryOverwriteRequestControl", + &efi_memory_only_reset_control_guid, + NULL, &data_size, + &memory_only_reset_control, NULL); + if (ret == EFI_SUCCESS) { + if (memory_only_reset_control & 0x01) { + struct bd_info *bd = gd->bd; + int i; + void *start, *buf; + ulong count; + + memory_only_reset_control = memory_only_reset_control & (~(0x01)); + ret = efi_set_variable_int(L"MemoryOverwriteRequestControl", + &efi_memory_only_reset_control_guid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + sizeof(memory_only_reset_control), + &memory_only_reset_control, 0); + + for (i = CONFIG_NR_DRAM_BANKS - 1; i > 0; --i) { + count = bd->bi_dram[i].size; + if (!count) + continue; + start = map_sysmem(bd->bi_dram[i].start, count); + buf = start; + while (count > 0) { + *((u8 *)buf) = 0; + buf += 1; + count--; + } + unmap_sysmem(start); + } + } + return ret; + } + + ret = efi_set_variable_int(L"MemoryOverwriteRequestControl", + &efi_memory_only_reset_control_guid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS | + EFI_VARIABLE_NON_VOLATILE, + sizeof(memory_only_reset_control), + &memory_only_reset_control, 0); + return ret; +} + /** * efi_init_obj_list() - Initialize and populate EFI object list * @@ -222,6 +288,11 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; + /* Platform Reset Attack features */ + ret = efi_init_memory_only_reset_control(); + if (ret != EFI_SUCCESS) + goto out; + /* Initialize system table */ ret = efi_initialize_system_table(); if (ret != EFI_SUCCESS) @@ -253,11 +324,13 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; #endif +#if 0 #ifdef CONFIG_NET ret = efi_net_register(); if (ret != EFI_SUCCESS) goto out; #endif +#endif #ifdef CONFIG_GENERATE_ACPI_TABLE ret = efi_acpi_register(); if (ret != EFI_SUCCESS) diff --git a/lib/image-sparse.c b/lib/image-sparse.c index 187ac28cd36..d8934717efe 100644 --- a/lib/image-sparse.c +++ b/lib/image-sparse.c @@ -58,7 +58,7 @@ int write_sparse_image(struct sparse_storage *info, uint32_t bytes_written = 0; unsigned int chunk; unsigned int offset; - unsigned int chunk_data_sz; + uint64_t chunk_data_sz; uint32_t *fill_buf = NULL; uint32_t fill_val; sparse_header_t *sparse_header; @@ -132,7 +132,7 @@ int write_sparse_image(struct sparse_storage *info, sizeof(chunk_header_t)); } - chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz; + chunk_data_sz = (uint64_t)sparse_header->blk_sz * (uint64_t)chunk_header->chunk_sz; blkcnt = chunk_data_sz / info->blksz; switch (chunk_header->chunk_type) { case CHUNK_TYPE_RAW: @@ -200,6 +200,7 @@ int write_sparse_image(struct sparse_storage *info, __func__); info->mssg("Request would exceed partition size!", response); + free(fill_buf); return -1; } diff --git a/lib/libavb/Makefile b/lib/libavb/Makefile index b983fe768e5..9238240a7f1 100644 --- a/lib/libavb/Makefile +++ b/lib/libavb/Makefile @@ -2,6 +2,7 @@ # # (C) Copyright 2017 Linaro Limited +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_LIBAVB) += avb_chain_partition_descriptor.o avb_cmdline.o obj-$(CONFIG_LIBAVB) += avb_crypto.o avb_footer.o avb_hashtree_descriptor.o obj-$(CONFIG_LIBAVB) += avb_property_descriptor.o avb_sha256.o @@ -9,5 +10,7 @@ obj-$(CONFIG_LIBAVB) += avb_slot_verify.o avb_util.o avb_version.o obj-$(CONFIG_LIBAVB) += avb_descriptor.o avb_hash_descriptor.o obj-$(CONFIG_LIBAVB) += avb_kernel_cmdline_descriptor.o avb_rsa.o avb_sha512.o obj-$(CONFIG_LIBAVB) += avb_sysdeps_posix.o avb_vbmeta_image.o +endif +obj-$(CONFIG_LIBAVB) += avb_crc32.o ccflags-y = -DAVB_COMPILATION diff --git a/lib/libavb/avb_cmdline.c b/lib/libavb/avb_cmdline.c index cb54e658c48..dde1182a325 100644 --- a/lib/libavb/avb_cmdline.c +++ b/lib/libavb/avb_cmdline.c @@ -10,7 +10,11 @@ #include #include +#ifndef CONFIG_ANDROID_DYNAMIC_PARTITION #define NUM_GUIDS 3 +#else +#define NUM_GUIDS 2 +#endif /* Substitutes all variables (e.g. $(ANDROID_SYSTEM_PARTUUID)) with * values. Returns NULL on OOM, otherwise the cmdline with values @@ -21,10 +25,16 @@ char* avb_sub_cmdline(AvbOps* ops, const char* ab_suffix, bool using_boot_for_vbmeta, const AvbCmdlineSubstList* additional_substitutions) { +#ifndef CONFIG_ANDROID_DYNAMIC_PARTITION const char* part_name_str[NUM_GUIDS] = {"system", "boot", "vbmeta"}; const char* replace_str[NUM_GUIDS] = {"$(ANDROID_SYSTEM_PARTUUID)", "$(ANDROID_BOOT_PARTUUID)", "$(ANDROID_VBMETA_PARTUUID)"}; +#else + const char* part_name_str[NUM_GUIDS] = {"boot", "vbmeta"}; + const char* replace_str[NUM_GUIDS] = {"$(ANDROID_BOOT_PARTUUID)", + "$(ANDROID_VBMETA_PARTUUID)"}; +#endif char* ret = NULL; AvbIOResult io_ret; size_t n; @@ -33,7 +43,11 @@ char* avb_sub_cmdline(AvbOps* ops, * partition. */ if (using_boot_for_vbmeta) { +#ifndef CONFIG_ANDROID_DYNAMIC_PARTITION part_name_str[2] = "boot"; +#else + part_name_str[1] = "boot"; +#endif } /* Replace unique partition GUIDs */ @@ -223,7 +237,7 @@ AvbSlotVerifyResult avb_append_options( AvbHashtreeErrorMode hashtree_error_mode, AvbHashtreeErrorMode resolved_hashtree_error_mode) { AvbSlotVerifyResult ret; - const char* verity_mode; + const char* verity_mode = NULL; bool is_device_unlocked; AvbIOResult io_ret; @@ -325,7 +339,7 @@ AvbSlotVerifyResult avb_append_options( if (toplevel_vbmeta->flags & AVB_VBMETA_IMAGE_FLAGS_HASHTREE_DISABLED) { verity_mode = "disabled"; } else { - const char* dm_verity_mode; + const char* dm_verity_mode = NULL; char* new_ret; switch (resolved_hashtree_error_mode) { diff --git a/lib/libavb/avb_crc32.c b/lib/libavb/avb_crc32.c new file mode 100644 index 00000000000..7d4cb09035a --- /dev/null +++ b/lib/libavb/avb_crc32.c @@ -0,0 +1,114 @@ +/*- + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or + * code or tables extracted from it, as desired without restriction. + */ + +/* + * First, the polynomial itself and its table of feedback terms. The + * polynomial is + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 + * + * Note that we take it "backwards" and put the highest-order term in + * the lowest-order bit. The X^32 term is "implied"; the LSB is the + * X^31 term, etc. The X^0 term (usually shown as "+1") results in + * the MSB being 1 + * + * Note that the usual hardware shift register implementation, which + * is what we're using (we're merely optimizing it by doing eight-bit + * chunks at a time) shifts bits into the lowest-order term. In our + * implementation, that means shifting towards the right. Why do we + * do it this way? Because the calculated CRC must be transmitted in + * order from highest-order term to lowest-order term. UARTs transmit + * characters in order from LSB to MSB. By storing the CRC this way + * we hand it to the UART in the order low-byte to high-byte; the UART + * sends each low-bit to hight-bit; and the result is transmission bit + * by bit from highest- to lowest-order term without requiring any bit + * shuffling on our part. Reception works similarly + * + * The feedback terms table consists of 256, 32-bit entries. Notes + * + * The table can be generated at runtime if desired; code to do so + * is shown later. It might not be obvious, but the feedback + * terms simply represent the results of eight shift/xor opera + * tions for all combinations of data and CRC register values + * + * The values must be right-shifted by eight bits by the "updcrc + * logic; the shift must be unsigned (bring in zeroes). On some + * hardware you could probably optimize the shift in assembler by + * using byte-swap instructions + * polynomial $edb88320 + * + * + * CRC32 code derived from work by Gary S. Brown. + */ + +#include "avb_sysdeps.h" +#include "avb_util.h" + +/* Code taken from FreeBSD 8 */ + +static uint32_t iavb_crc32_tab[] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d}; + +/* + * A function that calculates the CRC-32 based on the table above is + * given below for documentation purposes. An equivalent implementation + * of this function that's actually used in the kernel can be found + * in sys/libkern.h, where it can be inlined. + */ + +static uint32_t iavb_crc32(uint32_t crc_in, const uint8_t* buf, int size) { + const uint8_t* p = buf; + uint32_t crc; + + crc = crc_in ^ ~0U; + while (size--) + crc = iavb_crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8); + return crc ^ ~0U; +} + +uint32_t avb_crc32(const uint8_t* buf, size_t size) { + return iavb_crc32(0, buf, size); +} diff --git a/lib/libavb/avb_slot_verify.c b/lib/libavb/avb_slot_verify.c index ae8e1dffa4c..436983771c2 100644 --- a/lib/libavb/avb_slot_verify.c +++ b/lib/libavb/avb_slot_verify.c @@ -16,6 +16,10 @@ #include "avb_version.h" #include #include +#include +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) +#include "trusty/hwcrypto.h" +#endif /* Maximum number of partitions that can be loaded with avb_slot_verify(). */ #define MAX_NUMBER_OF_LOADED_PARTITIONS 32 @@ -25,6 +29,21 @@ /* Maximum size of a vbmeta image - 64 KiB. */ #define VBMETA_MAX_SIZE (64 * 1024) +/* Set the image load addr start from 96MB offset of CONFIG_FASTBOOT_BUF_ADDR */ +#define PARTITION_LOAD_ADDR_START (CONFIG_FASTBOOT_BUF_ADDR + (96 * 1024 * 1024)) + +/* Load dtbo/boot partition to fixed address instead of heap memory. */ +static void *image_addr_top = (void *)PARTITION_LOAD_ADDR_START; +static void *alloc_partition_addr(int size) +{ + void *ptr = image_addr_top; + image_addr_top = image_addr_top + ROUND(size, ARCH_DMA_MINALIGN); + return ptr; +} +static void free_partition_addr(int size) +{ + image_addr_top = (void *)(image_addr_top - ROUND(size, ARCH_DMA_MINALIGN)); +} static AvbSlotVerifyResult initialize_persistent_digest( AvbOps* ops, @@ -98,7 +117,7 @@ static AvbSlotVerifyResult load_full_partition(AvbOps* ops, /* Allocate and copy the partition. */ if (!*out_image_preloaded) { - *out_image_buf = avb_malloc(image_size); + *out_image_buf = (void *)alloc_partition_addr(image_size); if (*out_image_buf == NULL) { return AVB_SLOT_VERIFY_RESULT_ERROR_OOM; } @@ -276,11 +295,16 @@ static AvbSlotVerifyResult load_and_verify_hash_partition( bool image_preloaded = false; uint8_t* digest; size_t digest_len; - const char* found; + const char* found = NULL; uint64_t image_size; size_t expected_digest_len = 0; uint8_t expected_digest_buf[AVB_SHA512_DIGEST_SIZE]; const uint8_t* expected_digest = NULL; +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) + uint8_t* hash_out = NULL; + uint8_t* hash_buf = NULL; +#endif + if (!avb_hash_descriptor_validate_and_byteswap( (const AvbHashDescriptor*)descriptor, &hash_desc)) { @@ -371,7 +395,9 @@ static AvbSlotVerifyResult load_and_verify_hash_partition( // Although only one of the type might be used, we have to defined the // structure here so that they would live outside the 'if/else' scope to be // used later. +#if !defined(CONFIG_IMX_TRUSTY_OS) || defined(CONFIG_AVB_ATX) || defined(CONFIG_XEN) AvbSHA256Ctx sha256_ctx; +#endif AvbSHA512Ctx sha512_ctx; size_t image_size_to_hash = hash_desc.image_size; // If we allow verification error and the whole partition is smaller than @@ -380,10 +406,37 @@ static AvbSlotVerifyResult load_and_verify_hash_partition( image_size_to_hash = image_size; } if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha256") == 0) { +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) + /* DMA requires cache aligned input/output buffer */ + hash_out = memalign(ARCH_DMA_MINALIGN, AVB_SHA256_DIGEST_SIZE); + if (hash_out == NULL) { + avb_error("failed to alloc memory!\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM; + goto out; + } + hash_buf = (void *)CONFIG_FASTBOOT_BUF_ADDR; + + avb_memcpy(hash_buf, desc_salt, hash_desc.salt_len); + avb_memcpy(hash_buf + hash_desc.salt_len, + image_buf, image_size_to_hash); + /* calculate sha256 hash by caam */ + if (hwcrypto_hash((uint32_t)(ulong)hash_buf, + (hash_desc.salt_len + image_size_to_hash), + (uint32_t)(ulong)hash_out, + AVB_SHA256_DIGEST_SIZE, + SHA256) != 0) { + avb_error("Failed to calculate sha256 hash with caam.\n"); + ret = AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION; + goto out; + } + + digest = hash_out; +#else avb_sha256_init(&sha256_ctx); avb_sha256_update(&sha256_ctx, desc_salt, hash_desc.salt_len); avb_sha256_update(&sha256_ctx, image_buf, image_size_to_hash); digest = avb_sha256_final(&sha256_ctx); +#endif digest_len = AVB_SHA256_DIGEST_SIZE; } else if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha512") == 0) { avb_sha512_init(&sha512_ctx); @@ -436,6 +489,12 @@ static AvbSlotVerifyResult load_and_verify_hash_partition( out: +#if defined(CONFIG_IMX_TRUSTY_OS) && !defined(CONFIG_AVB_ATX) + if (hash_out != NULL) { + free(hash_out); + hash_out = NULL; + } +#endif /* If it worked and something was loaded, copy to slot_data. */ if ((ret == AVB_SLOT_VERIFY_RESULT_OK || result_should_continue(ret)) && image_buf != NULL) { @@ -455,8 +514,10 @@ static AvbSlotVerifyResult load_and_verify_hash_partition( } fail: + /* Now the image_buf is not allocated by malloc(), we should not free. + * Instead, we should reset the image_addr_top.*/ if (image_buf != NULL && !image_preloaded) { - avb_free(image_buf); + free_partition_addr(image_size); } return ret; } @@ -468,13 +529,13 @@ static AvbSlotVerifyResult load_requested_partitions( AvbSlotVerifyData* slot_data) { AvbSlotVerifyResult ret; uint8_t* image_buf = NULL; + uint64_t image_size; bool image_preloaded = false; size_t n; for (n = 0; requested_partitions[n] != NULL; n++) { char part_name[AVB_PART_NAME_MAX_SIZE]; AvbIOResult io_ret; - uint64_t image_size; AvbPartitionData* loaded_partition; if (!avb_str_concat(part_name, @@ -528,9 +589,10 @@ static AvbSlotVerifyResult load_requested_partitions( ret = AVB_SLOT_VERIFY_RESULT_OK; out: - /* Free the current buffer if any. */ + /* Now the image_buf is not allocated by malloc(), we should not free. + * Instead, we should reset the image_addr_top.*/ if (image_buf != NULL && !image_preloaded) { - avb_free(image_buf); + free_partition_addr(image_size); } /* Buffers that are already saved in slot_data will be handled by the caller * even on failure. */ @@ -1635,10 +1697,10 @@ void avb_slot_verify_data_free(AvbSlotVerifyData* data) { if (loaded_partition->partition_name != NULL) { avb_free(loaded_partition->partition_name); } - if (loaded_partition->data != NULL && !loaded_partition->preloaded) { - avb_free(loaded_partition->data); - } } + /* partition data is not loaded to heap memory, so we just reset the + * image_addr_top here. */ + image_addr_top = (void *)PARTITION_LOAD_ADDR_START; avb_free(data->loaded_partitions); } avb_free(data); diff --git a/lib/lmb.c b/lib/lmb.c index d126f8dc04a..39037cd3940 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -174,7 +174,7 @@ static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t break; } else if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) { /* regions overlap */ - return -1; + return -2; } } @@ -289,6 +289,41 @@ static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base, return (i < rgn->cnt) ? i : -1; } +long lmb_reserve_overlap(struct lmb *lmb, phys_addr_t base, phys_size_t size) +{ + struct lmb_region *_rgn = &(lmb->reserved); + long ret = lmb_add_region(_rgn, base, size); + long overlap_rgn; + phys_addr_t res_base; + phys_size_t res_size; + + /* Handle the overlap */ + if (ret == -2) { + overlap_rgn = lmb_overlaps_region(_rgn, base, size); + res_base = lmb->reserved.region[overlap_rgn].base; + res_size = lmb->reserved.region[overlap_rgn].size; + + if ((base >= res_base) && ((base + size) <= (res_base + res_size))) { + /* new region is inside reserved region, so it is already reserved */ + return 0; + } else { + if (base < res_base) { + ret = lmb_reserve(lmb, base, res_base - base); + if (ret < 0) + return ret; + } + + if ((base + size) > (res_base + res_size)) { + ret = lmb_reserve(lmb, res_base + res_size, (base + size) - (res_base + res_size)); + if (ret < 0) + return ret; + } + } + } + + return ret; +} + phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align) { return lmb_alloc_base(lmb, size, align, LMB_ALLOC_ANYWHERE); diff --git a/lib/sha256.c b/lib/sha256.c index c1fe93de012..70123c10608 100644 --- a/lib/sha256.c +++ b/lib/sha256.c @@ -289,3 +289,43 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen, sha256_finish(&ctx, output); } + +/* + * Output = HMAC-SHA-256( input buffer, hmac key ) + */ +void sha256_hmac(const unsigned char *key, int keylen, + const unsigned char *input, unsigned int ilen, + unsigned char *output) +{ + int i; + sha256_context ctx; + unsigned char k_ipad[64]; + unsigned char k_opad[64]; + unsigned char tmpbuf[32]; + + memset (k_ipad, 0x36, 64); + memset (k_opad, 0x5C, 64); + + for (i = 0; i < keylen; i++) { + if (i >= 64) + break; + + k_ipad[i] ^= key[i]; + k_opad[i] ^= key[i]; + } + + sha256_starts (&ctx); + sha256_update (&ctx, k_ipad, 64); + sha256_update (&ctx, input, ilen); + sha256_finish (&ctx, tmpbuf); + + sha256_starts (&ctx); + sha256_update (&ctx, k_opad, 64); + sha256_update (&ctx, tmpbuf, 32); + sha256_finish (&ctx, output); + + memset (k_ipad, 0, 64); + memset (k_opad, 0, 64); + memset (tmpbuf, 0, 32); + memset (&ctx, 0, sizeof (sha256_context)); +} diff --git a/lib/strto.c b/lib/strto.c index c00bb5895df..5157332d6c1 100644 --- a/lib/strto.c +++ b/lib/strto.c @@ -9,38 +9,61 @@ * Wirzenius wrote this portably, Torvalds fucked it up :-) */ -#include #include +#include +#include #include /* from lib/kstrtox.c */ -static const char *_parse_integer_fixup_radix(const char *s, unsigned int *base) -{ - if (*base == 0) { - if (s[0] == '0') { - if (tolower(s[1]) == 'x' && isxdigit(s[2])) - *base = 16; - else - *base = 8; - } else - *base = 10; +static const char *_parse_integer_fixup_radix(const char *s, uint *basep) +{ + /* Look for a 0x prefix */ + if (s[0] == '0') { + int ch = tolower(s[1]); + + if (ch == 'x') { + *basep = 16; + s += 2; + } else if (!*basep) { + /* Only select octal if we don't have a base */ + *basep = 8; + } } - if (*base == 16 && s[0] == '0' && tolower(s[1]) == 'x') - s += 2; + + /* Use decimal by default */ + if (!*basep) + *basep = 10; + return s; } -unsigned long simple_strtoul(const char *cp, char **endp, - unsigned int base) +/** + * decode_digit() - Decode a single character into its numeric digit value + * + * This ignore case + * + * @ch: Character to convert (expects '0'..'9', 'a'..'f' or 'A'..'F') + * Return: value of digit (0..0xf) or 255 if the character is invalid + */ +static uint decode_digit(int ch) { - unsigned long result = 0; - unsigned long value; + if (!isxdigit(ch)) + return 256; + + ch = tolower(ch); + + return ch <= '9' ? ch - '0' : ch - 'a' + 0xa; +} + +ulong simple_strtoul(const char *cp, char **endp, uint base) +{ + ulong result = 0; + uint value; cp = _parse_integer_fixup_radix(cp, &base); - while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp) - ? toupper(*cp) : *cp)-'A'+10) < base) { - result = result*base + value; + while (value = decode_digit(*cp), value < base) { + result = result * base + value; cp++; } @@ -50,6 +73,16 @@ unsigned long simple_strtoul(const char *cp, char **endp, return result; } +ulong hextoul(const char *cp, char **endp) +{ + return simple_strtoul(cp, endp, 16); +} + +ulong dectoul(const char *cp, char **endp) +{ + return simple_strtoul(cp, endp, 10); +} + int strict_strtoul(const char *cp, unsigned int base, unsigned long *res) { char *tail; @@ -127,12 +160,12 @@ unsigned long long ustrtoull(const char *cp, char **endp, unsigned int base) unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int base) { - unsigned long long result = 0, value; + unsigned long long result = 0; + uint value; cp = _parse_integer_fixup_radix(cp, &base); - while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp - '0' - : (islower(*cp) ? toupper(*cp) : *cp) - 'A' + 10) < base) { + while (value = decode_digit(*cp), value < base) { result = result * base + value; cp++; } @@ -143,22 +176,41 @@ unsigned long long simple_strtoull(const char *cp, char **endp, return result; } -long trailing_strtoln(const char *str, const char *end) +long long simple_strtoll(const char *cp, char **endp, unsigned int base) +{ + if (*cp == '-') + return -simple_strtoull(cp + 1, endp, base); + + return simple_strtoull(cp, endp, base); +} + +long trailing_strtoln_end(const char *str, const char *end, char const **endp) { const char *p; if (!end) end = str + strlen(str); - if (isdigit(end[-1])) { - for (p = end - 1; p > str; p--) { - if (!isdigit(*p)) - return simple_strtoul(p + 1, NULL, 10); - } + p = end - 1; + if (p > str && isdigit(*p)) { + do { + if (!isdigit(p[-1])) { + if (endp) + *endp = p; + return dectoul(p, NULL); + } + } while (--p > str); } + if (endp) + *endp = end; return -1; } +long trailing_strtoln(const char *str, const char *end) +{ + return trailing_strtoln_end(str, end, NULL); +} + long trailing_strtol(const char *str) { return trailing_strtoln(str, NULL); @@ -171,3 +223,43 @@ void str_to_upper(const char *in, char *out, size_t len) if (len) *out = '\0'; } + +const char **str_to_list(const char *instr) +{ + const char **ptr; + char *str, *p; + int count, i; + + /* don't allocate if the string is empty */ + str = *instr ? strdup(instr) : (char *)instr; + if (!str) + return NULL; + + /* count the number of space-separated strings */ + for (count = *str != '\0', p = str; *p; p++) { + if (*p == ' ') { + count++; + *p = '\0'; + } + } + + /* allocate the pointer array, allowing for a NULL terminator */ + ptr = calloc(count + 1, sizeof(char *)); + if (!ptr) { + if (*str) + free(str); + return NULL; + } + + for (i = 0, p = str; i < count; p += strlen(p) + 1, i++) + ptr[i] = p; + + return ptr; +} + +void str_free_list(const char **ptr) +{ + if (ptr) + free((char *)ptr[0]); + free(ptr); +} diff --git a/lib/trusty/ql-tipc/LICENSE b/lib/trusty/ql-tipc/LICENSE new file mode 100644 index 00000000000..d21621abc4b --- /dev/null +++ b/lib/trusty/ql-tipc/LICENSE @@ -0,0 +1,20 @@ +Copyright 2016, The Android Open Source Project + +Permission is hereby granted, free of charge, to any person obtaining +a copy of this software and associated documentation files (the +"Software"), to deal in the Software without restriction, including +without limitation the rights to use, copy, modify, merge, publish, +distribute, sublicense, and/or sell copies of the Software, and to +permit persons to whom the Software is furnished to do so, subject to +the following conditions: + +The above copyright notice and this permission notice shall be +included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. diff --git a/lib/trusty/ql-tipc/Makefile b/lib/trusty/ql-tipc/Makefile new file mode 100644 index 00000000000..57b48223e2b --- /dev/null +++ b/lib/trusty/ql-tipc/Makefile @@ -0,0 +1,50 @@ +# +# Copyright (C) 2016 The Android Open Source Project +# +# Permission is hereby granted, free of charge, to any person +# obtaining a copy of this software and associated documentation +# files (the "Software"), to deal in the Software without +# restriction, including without limitation the rights to use, copy, +# modify, merge, publish, distribute, sublicense, and/or sell copies +# of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be +# included in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# + +# Sample Makefile for U-boot + +#ccflags-y += -DTIPC_ENABLE_DEBUG + +TRUSTY_DIR = lib/trusty +#ccflags-y += -I$(TRUSTY_DIR)/ql-tipc/include +ccflags-y += -I$(TRUSTY_DIR)/interface/include + +QL_TIPC = . +obj-y += \ + $(QL_TIPC)/avb.o \ + $(QL_TIPC)/hwcrypto.o \ + $(QL_TIPC)/keymaster.o \ + $(QL_TIPC)/keymaster_serializable.o \ + $(QL_TIPC)/ipc.o \ + $(QL_TIPC)/ipc_dev.o \ + $(QL_TIPC)/libtipc.o \ + $(QL_TIPC)/rpmb_proxy.o \ + $(QL_TIPC)/util.o \ + $(QL_TIPC)/imx_snvs.o \ + sysdeps/sysdeps_uboot.o \ + sysdeps/storage_ops_uboot.o + +obj-$(CONFIG_ARM) += \ + $(QL_TIPC)/arch/arm/trusty_mem.o \ + $(QL_TIPC)/arch/arm/trusty_dev.o diff --git a/lib/trusty/ql-tipc/README.md b/lib/trusty/ql-tipc/README.md new file mode 100644 index 00000000000..76e37817561 --- /dev/null +++ b/lib/trusty/ql-tipc/README.md @@ -0,0 +1,30 @@ +# Queueless Trusty IPC + +ql-tipc is a portable client library that implements Trusty queueless IPC. +It is intended to enable Trusty IPC in bootloader environments. + +## Code organization + +### IPC components + +- libtipc - Functions to be called by library user +- ipc - IPC library +- ipc_dev - Helper functions for sending requests to the secure OS +- rpmb_proxy - Handles RPMB requests from secure storage service +- avb - Sends requests to the Android Verified Boot service + +### Misc + +- examples/ - Implementations of bootloader-specific code. +- arch/$ARCH/ - Architecture dependent implementation of Trusty device + (see trusty_dev.h). Implements SMCs on ARM for example. + +## Portability Notes + +The suggested approach to porting ql-tipc is to copy all header and C files +into the bootloader and integrate as needed. RPMB storage operations and +functions defined in trusty/sysdeps.h require system dependent implementations. + +If the TIPC_ENABLE_DEBUG preprocessor symbol is set, the code will include +debug information and run-time checks. Production builds should not use this. + diff --git a/lib/trusty/ql-tipc/arch/arm/sm_err.h b/lib/trusty/ql-tipc/arch/arm/sm_err.h new file mode 100644 index 00000000000..940125611c4 --- /dev/null +++ b/lib/trusty/ql-tipc/arch/arm/sm_err.h @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef QL_TIPC_SM_ERR_H_ +#define QL_TIPC_SM_ERR_H_ + +/* Errors from the secure monitor */ +#define SM_ERR_UNDEFINED_SMC 0xFFFFFFFF /* Unknown SMC (defined by ARM DEN 0028A(0.9.0) */ +#define SM_ERR_INVALID_PARAMETERS -2 +#define SM_ERR_INTERRUPTED -3 /* Got interrupted. Call back with restart SMC */ +#define SM_ERR_UNEXPECTED_RESTART -4 /* Got an restart SMC when we didn't expect it */ +#define SM_ERR_BUSY -5 /* Temporarily busy. Call back with original args */ +#define SM_ERR_INTERLEAVED_SMC -6 /* Got a trusted_service SMC when a restart SMC is required */ +#define SM_ERR_INTERNAL_FAILURE -7 /* Unknown error */ +#define SM_ERR_NOT_SUPPORTED -8 +#define SM_ERR_NOT_ALLOWED -9 /* SMC call not allowed */ +#define SM_ERR_END_OF_INPUT -10 +#define SM_ERR_PANIC -11 /* Secure OS crashed */ +#define SM_ERR_FIQ_INTERRUPTED -12 /* Got interrupted by FIQ. Call back with SMC_SC_RESTART_FIQ on same CPU */ +#define SM_ERR_CPU_IDLE -13 /* SMC call waiting for another CPU */ +#define SM_ERR_NOP_INTERRUPTED -14 /* Got interrupted. Call back with new SMC_SC_NOP */ +#define SM_ERR_NOP_DONE -15 /* Cpu idle after SMC_SC_NOP (not an error) */ + +#endif /* QL_TIPC_SM_ERR_H_ */ diff --git a/lib/trusty/ql-tipc/arch/arm/smcall.h b/lib/trusty/ql-tipc/arch/arm/smcall.h new file mode 100644 index 00000000000..695776c93ec --- /dev/null +++ b/lib/trusty/ql-tipc/arch/arm/smcall.h @@ -0,0 +1,143 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef QL_TIPC_SMCALL_H_ +#define QL_TIPC_SMCALL_H_ + +#define SMC_NUM_ENTITIES 64 +#define SMC_NUM_ARGS 4 +#define SMC_NUM_PARAMS (SMC_NUM_ARGS - 1) + +#define SMC_IS_FASTCALL(smc_nr) ((smc_nr) & 0x80000000) +#define SMC_IS_SMC64(smc_nr) ((smc_nr) & 0x40000000) +#define SMC_ENTITY(smc_nr) (((smc_nr) & 0x3F000000) >> 24) +#define SMC_FUNCTION(smc_nr) ((smc_nr) & 0x0000FFFF) + +#define SMC_NR(entity, fn, fastcall, smc64) ((((fastcall) & 0x1) << 31) | \ + (((smc64) & 0x1) << 30) | \ + (((entity) & 0x3F) << 24) | \ + ((fn) & 0xFFFF) \ + ) + +#define SMC_FASTCALL_NR(entity, fn) SMC_NR((entity), (fn), 1, 0) +#define SMC_STDCALL_NR(entity, fn) SMC_NR((entity), (fn), 0, 0) +#define SMC_FASTCALL64_NR(entity, fn) SMC_NR((entity), (fn), 1, 1) +#define SMC_STDCALL64_NR(entity, fn) SMC_NR((entity), (fn), 0, 1) + +#define SMC_ENTITY_ARCH 0 /* ARM Architecture calls */ +#define SMC_ENTITY_CPU 1 /* CPU Service calls */ +#define SMC_ENTITY_SIP 2 /* SIP Service calls */ +#define SMC_ENTITY_OEM 3 /* OEM Service calls */ +#define SMC_ENTITY_STD 4 /* Standard Service calls */ +#define SMC_ENTITY_RESERVED 5 /* Reserved for future use */ +#define SMC_ENTITY_TRUSTED_APP 48 /* Trusted Application calls */ +#define SMC_ENTITY_TRUSTED_OS 50 /* Trusted OS calls */ +#define SMC_ENTITY_LOGGING 51 /* Used for secure -> nonsecure logging */ +#define SMC_ENTITY_SECURE_MONITOR 60 /* Trusted OS calls internal to secure monitor */ + +/* FC = Fast call, SC = Standard call */ +#define SMC_SC_RESTART_LAST SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0) +#define SMC_SC_LOCKED_NOP SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 1) + +/** + * SMC_SC_RESTART_FIQ - Re-enter trusty after it was interrupted by an fiq + * + * No arguments, no return value. + * + * Re-enter trusty after returning to ns to process an fiq. Must be called iff + * trusty returns SM_ERR_FIQ_INTERRUPTED. + * + * Enable by selecting api version TRUSTY_API_VERSION_RESTART_FIQ (1) or later. + */ +#define SMC_SC_RESTART_FIQ SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 2) + +/** + * SMC_SC_NOP - Enter trusty to run pending work. + * + * No arguments. + * + * Returns SM_ERR_NOP_INTERRUPTED or SM_ERR_NOP_DONE. + * If SM_ERR_NOP_INTERRUPTED is returned, the call must be repeated. + * + * Enable by selecting api version TRUSTY_API_VERSION_SMP (2) or later. + */ +#define SMC_SC_NOP SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 3) + +/* + * Return from secure os to non-secure os with return value in r1 + */ +#define SMC_SC_NS_RETURN SMC_STDCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0) + +#define SMC_FC_RESERVED SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 0) +#define SMC_FC_FIQ_EXIT SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 1) +#define SMC_FC_REQUEST_FIQ SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 2) +#define SMC_FC_GET_NEXT_IRQ SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 3) +#define SMC_FC_FIQ_ENTER SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 4) + +#define SMC_FC64_SET_FIQ_HANDLER SMC_FASTCALL64_NR(SMC_ENTITY_SECURE_MONITOR, 5) +#define SMC_FC64_GET_FIQ_REGS SMC_FASTCALL64_NR (SMC_ENTITY_SECURE_MONITOR, 6) + +#define SMC_FC_CPU_SUSPEND SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 7) +#define SMC_FC_CPU_RESUME SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 8) + +#define SMC_FC_AARCH_SWITCH SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 9) +#define SMC_FC_GET_VERSION_STR SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 10) + +/** + * SMC_FC_API_VERSION - Find and select supported API version. + * + * @r1: Version supported by client. + * + * Returns version supported by trusty. + * + * If multiple versions are supported, the client should start by calling + * SMC_FC_API_VERSION with the largest version it supports. Trusty will then + * return a version it supports. If the client does not support the version + * returned by trusty and the version returned is less than the version + * requested, repeat the call with the largest supported version less than the + * last returned version. + * + * This call must be made before any calls that are affected by the api version. + */ +#define TRUSTY_API_VERSION_RESTART_FIQ (1) +#define TRUSTY_API_VERSION_SMP (2) +#define TRUSTY_API_VERSION_SMP_NOP (3) +#define TRUSTY_API_VERSION_CURRENT (3) +#define SMC_FC_API_VERSION SMC_FASTCALL_NR (SMC_ENTITY_SECURE_MONITOR, 11) + +/* TRUSTED_OS entity calls */ +#define SMC_SC_VIRTIO_GET_DESCR SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 20) +#define SMC_SC_VIRTIO_START SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 21) +#define SMC_SC_VIRTIO_STOP SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 22) + +#define SMC_SC_VDEV_RESET SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 23) +#define SMC_SC_VDEV_KICK_VQ SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 24) +#define SMC_NC_VDEV_KICK_VQ SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 25) + +/* Queueless Trusty IPC Interface */ +#define SMC_SC_TRUSTY_IPC_CREATE_QL_DEV SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 30) +#define SMC_SC_TRUSTY_IPC_SHUTDOWN_QL_DEV SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 31) +#define SMC_SC_TRUSTY_IPC_HANDLE_QL_DEV_CMD SMC_STDCALL_NR(SMC_ENTITY_TRUSTED_OS, 32) + +#endif /* QL_TIPC_SMCALL_H_ */ diff --git a/lib/trusty/ql-tipc/arch/arm/trusty_dev.c b/lib/trusty/ql-tipc/arch/arm/trusty_dev.c new file mode 100644 index 00000000000..fd8f2f367e9 --- /dev/null +++ b/lib/trusty/ql-tipc/arch/arm/trusty_dev.c @@ -0,0 +1,265 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include + +#include "sm_err.h" +#include "smcall.h" + +struct trusty_dev; + +#define LOCAL_LOG 0 + +#ifndef __asmeq +#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t" +#endif + +#ifdef NS_ARCH_ARM64 +#define SMC_ARG0 "x0" +#define SMC_ARG1 "x1" +#define SMC_ARG2 "x2" +#define SMC_ARG3 "x3" +#define SMC_ARCH_EXTENSION "" +#define SMC_REGISTERS_TRASHED "x4","x5","x6","x7","x8","x9","x10","x11", \ + "x12","x13","x14","x15","x16","x17" +#else +#define SMC_ARG0 "r0" +#define SMC_ARG1 "r1" +#define SMC_ARG2 "r2" +#define SMC_ARG3 "r3" +#define SMC_ARCH_EXTENSION ".arch_extension sec\n" +#define SMC_REGISTERS_TRASHED "ip" +#endif + +/* + * Execute SMC call into trusty + */ +static unsigned long smc(unsigned long r0, + unsigned long r1, + unsigned long r2, + unsigned long r3) +{ + register unsigned long _r0 __asm__(SMC_ARG0) = r0; + register unsigned long _r1 __asm__(SMC_ARG1) = r1; + register unsigned long _r2 __asm__(SMC_ARG2) = r2; + register unsigned long _r3 __asm__(SMC_ARG3) = r3; + + __asm__ volatile( + __asmeq("%0", SMC_ARG0) + __asmeq("%1", SMC_ARG1) + __asmeq("%2", SMC_ARG2) + __asmeq("%3", SMC_ARG3) + __asmeq("%4", SMC_ARG0) + __asmeq("%5", SMC_ARG1) + __asmeq("%6", SMC_ARG2) + __asmeq("%7", SMC_ARG3) + SMC_ARCH_EXTENSION + "smc #0" /* switch to secure world */ + : "=r" (_r0), "=r" (_r1), "=r" (_r2), "=r" (_r3) + : "r" (_r0), "r" (_r1), "r" (_r2), "r" (_r3) + : SMC_REGISTERS_TRASHED); + return _r0; +} + +int32_t trusty_simple_fast_call32(uint32_t smcnr, + uint32_t a0, uint32_t a1, uint32_t a2) +{ + trusty_assert(SMC_IS_FASTCALL(smcnr)); + + return smc(smcnr, a0, a1, a2); +} + +static int32_t trusty_fast_call32(struct trusty_dev *dev, uint32_t smcnr, + uint32_t a0, uint32_t a1, uint32_t a2) +{ + trusty_assert(dev); + trusty_assert(SMC_IS_FASTCALL(smcnr)); + + return smc(smcnr, a0, a1, a2); +} + +static unsigned long trusty_std_call_inner(struct trusty_dev *dev, + unsigned long smcnr, + unsigned long a0, + unsigned long a1, + unsigned long a2) +{ + unsigned long ret; + int retry = 5; + + trusty_debug("%s(0x%lx 0x%lx 0x%lx 0x%lx)\n", __func__, smcnr, a0, a1, a2); + + while (true) { + ret = smc(smcnr, a0, a1, a2); + while ((int32_t)ret == SM_ERR_FIQ_INTERRUPTED) + ret = smc(SMC_SC_RESTART_FIQ, 0, 0, 0); + if ((int)ret != SM_ERR_BUSY || !retry) + break; + + trusty_debug("%s(0x%lx 0x%lx 0x%lx 0x%lx) returned busy, retry\n", + __func__, smcnr, a0, a1, a2); + + retry--; + } + + return ret; +} + +static unsigned long trusty_std_call_helper(struct trusty_dev *dev, + unsigned long smcnr, + unsigned long a0, + unsigned long a1, + unsigned long a2) +{ + unsigned long ret; + unsigned long irq_state; + + while (true) { + trusty_local_irq_disable(&irq_state); + ret = trusty_std_call_inner(dev, smcnr, a0, a1, a2); + trusty_local_irq_restore(&irq_state); + + if ((int)ret != SM_ERR_BUSY) + break; + + trusty_idle(dev); + } + + return ret; +} + +static int32_t trusty_std_call32(struct trusty_dev *dev, uint32_t smcnr, + uint32_t a0, uint32_t a1, uint32_t a2) +{ + int ret; + + trusty_assert(dev); + trusty_assert(!SMC_IS_FASTCALL(smcnr)); + + if (smcnr != SMC_SC_NOP) { + trusty_lock(dev); + } + + trusty_debug("%s(0x%x 0x%x 0x%x 0x%x) started\n", __func__, + smcnr, a0, a1, a2); + + ret = trusty_std_call_helper(dev, smcnr, a0, a1, a2); + while (ret == SM_ERR_INTERRUPTED || ret == SM_ERR_CPU_IDLE) { + trusty_debug("%s(0x%x 0x%x 0x%x 0x%x) interrupted\n", __func__, + smcnr, a0, a1, a2); + if (ret == SM_ERR_CPU_IDLE) { + trusty_idle(dev); + } + ret = trusty_std_call_helper(dev, SMC_SC_RESTART_LAST, 0, 0, 0); + } + + trusty_debug("%s(0x%x 0x%x 0x%x 0x%x) returned 0x%x\n", + __func__, smcnr, a0, a1, a2, ret); + + if (smcnr != SMC_SC_NOP) { + trusty_unlock(dev); + } + + return ret; +} + +static int trusty_call32_mem_buf(struct trusty_dev *dev, uint32_t smcnr, + struct ns_mem_page_info *page, uint32_t size) +{ + trusty_assert(dev); + trusty_assert(page); + + if (SMC_IS_FASTCALL(smcnr)) { + return trusty_fast_call32(dev, smcnr, + (uint32_t)page->attr, + (uint32_t)(page->attr >> 32), size); + } else { + return trusty_std_call32(dev, smcnr, + (uint32_t)page->attr, + (uint32_t)(page->attr >> 32), size); + } +} + +int trusty_dev_init_ipc(struct trusty_dev *dev, + struct ns_mem_page_info *buf, uint32_t buf_size) +{ + return trusty_call32_mem_buf(dev, SMC_SC_TRUSTY_IPC_CREATE_QL_DEV, + buf, buf_size); +} + +int trusty_dev_exec_ipc(struct trusty_dev *dev, + struct ns_mem_page_info *buf, uint32_t buf_size) +{ + return trusty_call32_mem_buf(dev, SMC_SC_TRUSTY_IPC_HANDLE_QL_DEV_CMD, + buf, buf_size); +} + +int trusty_dev_shutdown_ipc(struct trusty_dev *dev, + struct ns_mem_page_info *buf, uint32_t buf_size) +{ + return trusty_call32_mem_buf(dev, SMC_SC_TRUSTY_IPC_SHUTDOWN_QL_DEV, + buf, buf_size); +} + + +static int trusty_init_api_version(struct trusty_dev *dev) +{ + uint32_t api_version; + + api_version = trusty_fast_call32(dev, SMC_FC_API_VERSION, + TRUSTY_API_VERSION_CURRENT, 0, 0); + if (api_version == SM_ERR_UNDEFINED_SMC) + api_version = 0; + + if (api_version > TRUSTY_API_VERSION_CURRENT) { + trusty_error("unsupported trusty api version %u > %u\n", + api_version, TRUSTY_API_VERSION_CURRENT); + return -1; + } + + trusty_info("selected trusty api version: %u (requested %u)\n", + api_version, TRUSTY_API_VERSION_CURRENT); + + dev->api_version = api_version; + + return 0; +} + +int trusty_dev_init(struct trusty_dev *dev, void *priv_data) +{ + trusty_assert(dev); + + dev->priv_data = priv_data; + return trusty_init_api_version(dev); +} + +int trusty_dev_shutdown(struct trusty_dev *dev) +{ + trusty_assert(dev); + + dev->priv_data = NULL; + return 0; +} + diff --git a/lib/trusty/ql-tipc/arch/arm/trusty_mem.c b/lib/trusty/ql-tipc/arch/arm/trusty_mem.c new file mode 100644 index 00000000000..890dbe48bcd --- /dev/null +++ b/lib/trusty/ql-tipc/arch/arm/trusty_mem.c @@ -0,0 +1,284 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include + +/* 48-bit physical address bits 47:12 */ + +#define NS_PTE_PHYSADDR_SHIFT 12 +#define NS_PTE_PHYSADDR(pte) ((pte) & 0xFFFFFFFFF000ULL) + +/* Access permissions bits 7:6 + * EL0 EL1 + * 00 None RW + * 01 RW RW + * 10 None RO + * 11 RO RO + */ +#define NS_PTE_AP_SHIFT 6 +#define NS_PTE_AP_MASK (0x3 << NS_PTE_AP_SHIFT) + +/* Memory type and cache attributes bits 55:48 */ +#define NS_PTE_MAIR_SHIFT 48 +#define NS_PTE_MAIR_MASK (0x00FFULL << NS_PTE_MAIR_SHIFT) + +#define NS_PTE_MAIR_INNER_SHIFT 48 +#define NS_PTE_MAIR_INNER_MASK (0x000FULL << NS_PTE_MAIR_INNER_SHIFT) + +#define NS_PTE_MAIR_OUTER_SHIFT 52 +#define NS_PTE_MAIR_OUTER_MASK (0x000FULL << NS_PTE_MAIR_OUTER_SHIFT) + +/* Normal memory */ +#define NS_MAIR_NORMAL_CACHED_WB_RWA 0xFF /* inner and outer write back read/write allocate */ +#define NS_MAIR_NORMAL_CACHED_WT_RA 0xAA /* inner and outer write through read allocate */ +#define NS_MAIR_NORMAL_CACHED_WB_RA 0xEE /* inner and outer write back, read allocate */ +#define NS_MAIR_NORMAL_UNCACHED 0x44 /* uncached */ + +/* Device memory */ +#define NS_MAIR_DEVICE_STRONGLY_ORDERED 0x00 /* nGnRnE (strongly ordered) */ +#define NS_MAIR_DEVICE 0x04 /* nGnRE (device) */ +#define NS_MAIR_DEVICE_GRE 0x0C /* GRE */ + +/* shareable attributes bits 9:8 */ +#define NS_PTE_SHAREABLE_SHIFT 8 + +#define NS_NON_SHAREABLE 0x0 +#define NS_OUTER_SHAREABLE 0x2 +#define NS_INNER_SHAREABLE 0x3 + +typedef uintptr_t addr_t; +typedef uintptr_t vaddr_t; +typedef uintptr_t paddr_t; + +#if NS_ARCH_ARM64 + +#define PAR_F (0x1 << 0) + +/* + * ARM64 + */ + +/* Note: this will crash if called from user space */ +static void arm64_write_ATS1ExW(uint64_t vaddr) +{ + uint64_t _current_el; + + __asm__ volatile("mrs %0, CurrentEL" : "=r" (_current_el)); + + _current_el = (_current_el >> 2) & 0x3; + switch (_current_el) { + case 0x1: + __asm__ volatile("at S1E1W, %0" :: "r" (vaddr)); + break; + case 0x2: + __asm__ volatile("at S1E2W, %0" :: "r" (vaddr)); + break; + case 0x3: + default: + trusty_fatal("Unsupported execution state: EL%lu\n", _current_el ); + break; + } + + __asm__ volatile("isb" ::: "memory"); +} + +static uint64_t arm64_read_par64(void) +{ + uint64_t _val; + __asm__ volatile("mrs %0, par_el1" : "=r" (_val)); + return _val; +} + + +static uint64_t va2par(vaddr_t va) +{ + uint64_t par; + unsigned long irq_state; + + trusty_local_irq_disable(&irq_state); + arm64_write_ATS1ExW(va); + par = arm64_read_par64(); + trusty_local_irq_restore(&irq_state); + + return par; +} + +static uint64_t par2attr(uint64_t par) +{ + uint64_t attr; + + /* set phys address */ + attr = NS_PTE_PHYSADDR(par); + + /* cache attributes */ + attr |= ((par >> 56) & 0xFF) << NS_PTE_MAIR_SHIFT; + + /* shareable attributes */ + attr |= ((par >> 7) & 0x03) << NS_PTE_SHAREABLE_SHIFT; + + /* the memory is writable and accessible so leave AP field 0 */ + attr |= 0x0 << NS_PTE_AP_SHIFT; + + return attr; +} + +#else + +#define PAR_F (0x1 << 0) +#define PAR_SS (0x1 << 1) +#define PAR_SH (0x1 << 7) +#define PAR_NOS (0x1 << 10) +#define PAR_LPAE (0x1 << 11) + +/* + * ARM32 + */ + +/* Note: this will crash if called from user space */ +static void arm_write_ATS1xW(uint64_t vaddr) +{ + uint32_t _cpsr; + + __asm__ volatile("mrs %0, cpsr" : "=r"(_cpsr)); + + if ((_cpsr & 0xF) == 0xa) + __asm__ volatile("mcr p15, 4, %0, c7, c8, 1" : : "r"(vaddr)); + else + __asm__ volatile("mcr p15, 0, %0, c7, c8, 1" : : "r"(vaddr)); +} + +static uint64_t arm_read_par64(void) +{ + uint32_t lower, higher; + + __asm__ volatile( + "mrc p15, 0, %0, c7, c4, 0 \n" + "tst %0, #(1 << 11) @ LPAE / long desc format\n" + "moveq %1, #0 \n" + "mrrcne p15, 0, %0, %1, c7 \n" + :"=r"(lower), "=r"(higher) : : + ); + + return ((uint64_t)higher << 32) | lower; +} + + +static uint8_t ish_to_mair[8] = { + 0x04, /* 0b000 Non cacheble */ + 0x00, /* 0b001 Strongly ordered */ + 0xF0, /* 0b010 reserved */ + 0x04, /* 0b011 device */ + 0xF0, /* 0b100 reserved */ + 0x0F, /* 0b101 write back - write allocate */ + 0x0A, /* 0b110 write through */ + 0x0E, /* 0b111 write back - no write allocate */ +}; + +static uint8_t osh_to_mair[4] = { + 0x00, /* 0b00 Non-cacheable */ + 0x0F, /* 0b01 Write-back, Write-allocate */ + 0x0A, /* 0b10 Write-through, no Write-allocate */ + 0x0E, /* 0b11 Write-back, no Write-allocate */ +}; + +static uint64_t par2attr(uint64_t par) +{ + uint64_t attr; + + if (par & PAR_LPAE) { + /* set phys address */ + attr = NS_PTE_PHYSADDR(par); + + /* cache attributes */ + attr |= ((par >> 56) & 0xFF) << NS_PTE_MAIR_SHIFT; + + /* shareable attributes */ + attr |= ((par >> 7) & 0x03) << NS_PTE_SHAREABLE_SHIFT; + + } else { + + /* set phys address */ + trusty_assert((par & PAR_SS) == 0); /* super section not supported */ + attr = NS_PTE_PHYSADDR(par); + + /* cache attributes */ + uint64_t inner = ((uint64_t)ish_to_mair[(par >> 4) & 0x7]) << NS_PTE_MAIR_INNER_SHIFT; + uint64_t outer = ((uint64_t)osh_to_mair[(par >> 2) & 0x3]) << NS_PTE_MAIR_OUTER_SHIFT; + uint64_t cache_attributes = (outer << 4) | inner; + + /* Trusty does not support any kind of device memory, so we will force + * cache attributes to be NORMAL UNCACHED on the Trusty side. + */ + if (cache_attributes == NS_MAIR_DEVICE_STRONGLY_ORDERED) { + attr |= ((uint64_t)NS_MAIR_NORMAL_UNCACHED << NS_PTE_MAIR_SHIFT); + } else { + attr |= inner; + attr |= outer; + } + + /* shareable attributes */ + if (par & PAR_SH) { + /* how to handle NOS bit ? */ + attr |= ((uint64_t)NS_INNER_SHAREABLE) << NS_PTE_SHAREABLE_SHIFT; + } else { + attr |= ((uint64_t)NS_NON_SHAREABLE) << NS_PTE_SHAREABLE_SHIFT; + } + } + + /* the memory is writable and accessible so leave AP field 0 */ + attr |= 0x0 << NS_PTE_AP_SHIFT; + + return attr; +} + +static uint64_t va2par(vaddr_t va) +{ + uint64_t par; + unsigned long irq_state; + + trusty_local_irq_disable(&irq_state); + arm_write_ATS1xW(va); + par = arm_read_par64(); + trusty_local_irq_restore(&irq_state); + + return par; +} + +#endif /* ARM64 */ + + +int trusty_encode_page_info(struct ns_mem_page_info *inf, void *va) +{ + uint64_t par = va2par((vaddr_t)va); + + if (par & PAR_F) { + return -1; + } + + inf->attr = par2attr(par); + + return 0; +} + diff --git a/lib/trusty/ql-tipc/avb.c b/lib/trusty/ql-tipc/avb.c new file mode 100644 index 00000000000..937cafc9106 --- /dev/null +++ b/lib/trusty/ql-tipc/avb.c @@ -0,0 +1,269 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include + +#define LOCAL_LOG 0 + +static bool initialized; +static int avb_tipc_version = 1; +static struct trusty_ipc_chan avb_chan; + +static int avb_send_request(struct avb_message *msg, void *req, size_t req_len) +{ + struct trusty_ipc_iovec req_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = req, .len = req_len }, + }; + + return trusty_ipc_send(&avb_chan, req_iovs, req ? 2 : 1, true); +} + +static int avb_read_response(struct avb_message *msg, uint32_t cmd, void *resp, + size_t resp_len) +{ + int rc; + struct trusty_ipc_iovec resp_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = resp, .len = resp_len }, + }; + + rc = trusty_ipc_recv(&avb_chan, resp_iovs, resp ? 2 : 1, true); + if (rc < 0) { + trusty_error("failed (%d) to recv response\n", rc); + return rc; + } + if (msg->cmd != (cmd | AVB_RESP_BIT)) { + trusty_error("malformed response\n"); + return TRUSTY_ERR_GENERIC; + } + /* return payload size */ + return rc - sizeof(*msg); +} + +/* + * Convenience function to send a request to the AVB service and read the + * response. + * + * @cmd: the command + * @req: the request buffer + * @req_size: size of the request buffer + * @resp: the response buffer + * @resp_size_p: pointer to the size of the response buffer. changed to the + actual size of the response read from the secure side + */ +static int avb_do_tipc(uint32_t cmd, void *req, uint32_t req_size, void *resp, + uint32_t *resp_size_p) +{ + int rc; + struct avb_message msg = { .cmd = cmd }; + + if (!initialized && cmd != AVB_GET_VERSION) { + trusty_error("%s: AVB TIPC client not initialized\n", __func__); + return TRUSTY_ERR_GENERIC; + } + + rc = avb_send_request(&msg, req, req_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to send AVB request\n", __func__, rc); + return rc; + } + + uint32_t resp_size = resp_size_p ? *resp_size_p : 0; + rc = avb_read_response(&msg, cmd, resp, resp_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to read AVB response\n", __func__, rc); + return rc; + } + /* change response size to actual response size */ + if (resp_size_p && rc != *resp_size_p) { + *resp_size_p = rc; + } + if (msg.result != AVB_ERROR_NONE) { + trusty_error("%s: AVB service returned error (%d)\n", __func__, + msg.result); + return TRUSTY_ERR_GENERIC; + } + return TRUSTY_ERR_NONE; +} + +static int avb_get_version(uint32_t *version) +{ + int rc; + struct avb_get_version_resp resp; + uint32_t resp_size = sizeof(resp); + + rc = avb_do_tipc(AVB_GET_VERSION, NULL, 0, &resp, &resp_size); + + *version = resp.version; + return rc; +} + + +int avb_tipc_init(struct trusty_ipc_dev *dev) +{ + int rc; + uint32_t version = 0; + + trusty_assert(dev); + trusty_assert(!initialized); + + trusty_ipc_chan_init(&avb_chan, dev); + trusty_debug("Connecting to AVB service\n"); + + /* connect to AVB service and wait for connect to complete */ + rc = trusty_ipc_connect(&avb_chan, AVB_PORT, true); + if (rc < 0) { + trusty_error("failed (%d) to connect to '%s'\n", rc, AVB_PORT); + return rc; + } + + /* check for version mismatch */ + rc = avb_get_version(&version); + if (rc != 0) { + trusty_error("Error getting version"); + return TRUSTY_ERR_GENERIC; + } + if (version != avb_tipc_version) { + trusty_error("AVB TIPC version mismatch. Expected %u, received %u\n", + avb_tipc_version, version); + return TRUSTY_ERR_GENERIC; + } + + /* mark as initialized */ + initialized = true; + + return TRUSTY_ERR_NONE; +} + +void avb_tipc_shutdown(struct trusty_ipc_dev *dev) +{ + if (!initialized) + return; /* nothing to do */ + + /* close channel */ + trusty_ipc_close(&avb_chan); + + initialized = false; +} + +int trusty_read_rollback_index(uint32_t slot, uint64_t *value) +{ + int rc; + struct avb_rollback_req req = { .slot = slot, .value = 0 }; + struct avb_rollback_resp resp; + uint32_t resp_size = sizeof(resp); + + rc = avb_do_tipc(READ_ROLLBACK_INDEX, &req, sizeof(req), &resp, + &resp_size); + + *value = resp.value; + return rc; +} + +int trusty_write_rollback_index(uint32_t slot, uint64_t value) +{ + int rc; + struct avb_rollback_req req = { .slot = slot, .value = value }; + struct avb_rollback_resp resp; + uint32_t resp_size = sizeof(resp); + + rc = avb_do_tipc(WRITE_ROLLBACK_INDEX, &req, sizeof(req), &resp, + &resp_size); + return rc; +} + +int trusty_read_permanent_attributes(uint8_t *attributes, uint32_t size) +{ + uint8_t resp_buf[AVB_MAX_BUFFER_LENGTH]; + uint32_t resp_size = AVB_MAX_BUFFER_LENGTH; + int rc = avb_do_tipc(READ_PERMANENT_ATTRIBUTES, NULL, 0, resp_buf, + &resp_size); + if (rc != 0) { + return rc; + } + /* ensure caller passed size matches size returned by Trusty */ + if (size != resp_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + trusty_memcpy(attributes, resp_buf, resp_size); + return rc; +} + +int trusty_write_permanent_attributes(uint8_t *attributes, uint32_t size) +{ + return avb_do_tipc(WRITE_PERMANENT_ATTRIBUTES, attributes, size, NULL, + NULL); +} + +int trusty_read_vbmeta_public_key(uint8_t *publickey, uint32_t size) +{ + uint8_t resp_buf[AVB_MAX_BUFFER_LENGTH]; + uint32_t resp_size = AVB_MAX_BUFFER_LENGTH; + int rc = avb_do_tipc(READ_VBMETA_PUBLIC_KEY, NULL, 0, resp_buf, + &resp_size); + if (rc != 0) { + return rc; + } + /* ensure caller passed size matches size returned by Trusty */ + if (size < resp_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + trusty_memcpy(publickey, resp_buf, resp_size); + return rc; +} + +int trusty_write_vbmeta_public_key(uint8_t *publickey, uint32_t size) +{ + return avb_do_tipc(WRITE_VBMETA_PUBLIC_KEY, publickey, size, NULL, + NULL); +} + +int trusty_read_lock_state(uint8_t *lock_state) +{ + uint32_t resp_size = sizeof(*lock_state); + return avb_do_tipc(READ_LOCK_STATE, NULL, 0, lock_state, + &resp_size); +} + +int trusty_write_lock_state(uint8_t lock_state) +{ + return avb_do_tipc(WRITE_LOCK_STATE, &lock_state, sizeof(lock_state), NULL, + NULL); +} + +int trusty_lock_boot_state(void) +{ + return avb_do_tipc(LOCK_BOOT_STATE, NULL, 0, NULL, NULL); +} + +int trusty_read_oem_unlock_device_permission(uint8_t *oem_device_unlock) +{ + uint32_t resp_size = sizeof(*oem_device_unlock); + return avb_do_tipc(READ_OEM_UNLOCK_DEVICE_PERMISSION, NULL, 0, oem_device_unlock, + &resp_size); +} diff --git a/lib/trusty/ql-tipc/hwcrypto.c b/lib/trusty/ql-tipc/hwcrypto.c new file mode 100644 index 00000000000..21c58826c89 --- /dev/null +++ b/lib/trusty/ql-tipc/hwcrypto.c @@ -0,0 +1,329 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * Copyright NXP 2018 + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include "common.h" +#include +#include +#include + +#define LOCAL_LOG 0 +#define CAAM_KB_HEADER_LEN 48 + +static bool initialized; +static struct trusty_ipc_chan hwcrypto_chan; + +static int hwcrypto_send_request(struct hwcrypto_message *msg, void *req, size_t req_len) +{ + struct trusty_ipc_iovec req_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = req, .len = req_len }, + }; + + return trusty_ipc_send(&hwcrypto_chan, req_iovs, req ? 2 : 1, true); +} + +static int hwcrypto_read_response(struct hwcrypto_message *msg, uint32_t cmd, void *resp, + size_t resp_len) +{ + int rc; + struct trusty_ipc_iovec resp_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = resp, .len = resp_len }, + }; + + rc = trusty_ipc_recv(&hwcrypto_chan, resp_iovs, resp ? 2 : 1, true); + if (rc < 0) { + trusty_error("failed (%d) to recv response\n", rc); + return rc; + } + if (msg->cmd != (cmd | HWCRYPTO_RESP_BIT)) { + trusty_error("malformed response\n"); + return TRUSTY_ERR_GENERIC; + } + /* return payload size */ + return rc - sizeof(*msg); +} + +/* + * Convenience function to send a request to the hwcrypto service and read the + * response. + * + * @cmd: the command + * @req: the request buffer + * @req_size: size of the request buffer + * @resp: the response buffer + * @resp_size_p: pointer to the size of the response buffer. changed to the + actual size of the response read from the secure side + */ +static int hwcrypto_do_tipc(uint32_t cmd, void *req, uint32_t req_size, void *resp, + uint32_t *resp_size_p) +{ + int rc; + struct hwcrypto_message msg = { .cmd = cmd }; + + if (!initialized) { + trusty_error("%s: HWCRYPTO TIPC client not initialized\n", __func__); + return TRUSTY_ERR_GENERIC; + } + + rc = hwcrypto_send_request(&msg, req, req_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to send hwcrypto request\n", __func__, rc); + return rc; + } + + uint32_t resp_size = resp_size_p ? *resp_size_p : 0; + rc = hwcrypto_read_response(&msg, cmd, resp, resp_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to read HWCRYPTO response\n", __func__, rc); + return rc; + } + /* change response size to actual response size */ + if (resp_size_p && rc != *resp_size_p) { + *resp_size_p = rc; + } + if (msg.result != HWCRYPTO_ERROR_NONE) { + trusty_error("%s: HWCRYPTO service returned error (%d)\n", __func__, + msg.result); + return TRUSTY_ERR_GENERIC; + } + return TRUSTY_ERR_NONE; +} + +int hwcrypto_tipc_init(struct trusty_ipc_dev *dev) +{ + int rc; + + trusty_assert(dev); + trusty_assert(!initialized); + + trusty_ipc_chan_init(&hwcrypto_chan, dev); + trusty_debug("Connecting to hwcrypto service\n"); + + /* connect to hwcrypto service and wait for connect to complete */ + rc = trusty_ipc_connect(&hwcrypto_chan, HWCRYPTO_PORT, true); + if (rc < 0) { + trusty_error("failed (%d) to connect to '%s'\n", rc, HWCRYPTO_PORT); + return rc; + } + + /* mark as initialized */ + initialized = true; + + return TRUSTY_ERR_NONE; +} + +void hwcrypto_tipc_shutdown(struct trusty_ipc_dev *dev) +{ + if (!initialized) + return; /* nothing to do */ + + /* close channel */ + trusty_ipc_close(&hwcrypto_chan); + + initialized = false; +} + +int hwcrypto_hash(uint32_t in_addr, uint32_t in_len, uint32_t out_addr, + uint32_t out_len, enum hwcrypto_hash_algo algo) +{ + hwcrypto_hash_msg req; + unsigned long start, end; + + /* check the address */ + if (in_addr == 0 || out_addr == 0) + return TRUSTY_ERR_INVALID_ARGS; + /* fill the request buffer */ + req.in_addr = in_addr; + req.out_addr = out_addr; + req.in_len = in_len; + req.out_len = out_len; + req.algo = algo; + + /* flush dcache for input buffer */ + start = (unsigned long)in_addr & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)in_addr + in_len, ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + + /* invalidate dcache for output buffer */ + start = (unsigned long)out_addr & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)out_addr + out_len, ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + + int rc = hwcrypto_do_tipc(HWCRYPTO_HASH, (void*)&req, + sizeof(req), NULL, 0); + + /* invalidate the dcache again before read to avoid coherency + * problem caused by speculative memory access by the CPU. + */ + invalidate_dcache_range(start, end); + + return rc; +} + +int hwcrypto_gen_blob(uint32_t plain_pa, + uint32_t plain_size, uint32_t blob_pa) +{ + hwcrypto_blob_msg req; + unsigned long start, end; + + /* check the address */ + if (plain_pa == 0 || blob_pa == 0) + return TRUSTY_ERR_INVALID_ARGS; + /* fill the request buffer */ + req.plain_pa = plain_pa; + req.plain_size = plain_size; + req.blob_pa = blob_pa; + + /* flush dcache for input buffer */ + start = (unsigned long)plain_pa & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)plain_pa + plain_size, ARCH_DMA_MINALIGN); + flush_dcache_range(start, end); + + /* invalidate dcache for output buffer */ + start = (unsigned long)blob_pa & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)blob_pa + plain_size + + CAAM_KB_HEADER_LEN, ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + + int rc = hwcrypto_do_tipc(HWCRYPTO_ENCAP_BLOB, (void*)&req, + sizeof(req), NULL, 0); + + /* invalidate the dcache again before read to avoid coherency + * problem caused by speculative memory access by the CPU. + */ + invalidate_dcache_range(start, end); + return rc; +} + +int hwcrypto_gen_rng(uint32_t buf, uint32_t len) +{ + hwcrypto_rng_msg req; + unsigned long start, end; + + /* check the address */ + if (buf == 0) + return TRUSTY_ERR_INVALID_ARGS; + /* fill the request buffer */ + req.buf = buf; + req.len = len; + + /* invalidate dcache for output buffer */ + start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)buf + len, ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + + int rc = hwcrypto_do_tipc(HWCRYPTO_GEN_RNG, (void*)&req, + sizeof(req), NULL, 0); + + /* invalidate the dcache again before read to avoid coherency + * problem caused by speculative memory access by the CPU. + */ + invalidate_dcache_range(start, end); + return rc; +} + +int hwcrypto_gen_bkek(uint32_t buf, uint32_t len) +{ + hwcrypto_bkek_msg req; + unsigned long start, end; + + /* check the address */ + if (buf == 0) + return TRUSTY_ERR_INVALID_ARGS; + /* fill the request buffer */ + req.buf = buf; + req.len = len; + + /* invalidate dcache for output buffer */ + start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1); + end = ALIGN((unsigned long)buf + len, ARCH_DMA_MINALIGN); + invalidate_dcache_range(start, end); + + int rc = hwcrypto_do_tipc(HWCRYPTO_GEN_BKEK, (void*)&req, + sizeof(req), NULL, 0); + + /* invalidate the dcache again before read to avoid coherency + * problem caused by speculative memory access by the CPU. + */ + invalidate_dcache_range(start, end); + return rc; +} + +int hwcrypto_lock_boot_state(void) +{ + return hwcrypto_do_tipc(HWCRYPTO_LOCK_BOOT_STATE, NULL, 0, NULL, 0); +} + +int hwcrypto_provision_wv_key(const char *data, uint32_t data_size) +{ + uint8_t *req = NULL, *tmp; + /* sanity check */ + if (!data || !data_size) + return TRUSTY_ERR_INVALID_ARGS; + + /* serialize the request */ + req = trusty_calloc(data_size + sizeof(data_size), 1); + if (!req) { + return TRUSTY_ERR_NO_MEMORY; + } + tmp = append_sized_buf_to_buf(req, (uint8_t *)data, data_size); + + int rc = hwcrypto_do_tipc(HWCRYPTO_PROVISION_WV_KEY, (void*)req, + data_size + sizeof(data_size), NULL, 0); + + if (req) + trusty_free(req); + + return rc; +} + +int hwcrypto_provision_wv_key_enc(const char *data, uint32_t data_size) +{ + uint8_t *req = NULL, *tmp; + /* sanity check */ + if (!data || !data_size) + return TRUSTY_ERR_INVALID_ARGS; + + /* serialize the request */ + req = trusty_calloc(data_size + sizeof(data_size), 1); + if (!req) { + return TRUSTY_ERR_NO_MEMORY; + } + tmp = append_sized_buf_to_buf(req, (uint8_t *)data, data_size); + + int rc = hwcrypto_do_tipc(HWCRYPTO_PROVISION_WV_KEY_ENC, (void*)req, + data_size + sizeof(data_size), NULL, 0); + + if (req) + trusty_free(req); + + return rc; +} diff --git a/lib/trusty/ql-tipc/imx_snvs.c b/lib/trusty/ql-tipc/imx_snvs.c new file mode 100644 index 00000000000..972cb427f3c --- /dev/null +++ b/lib/trusty/ql-tipc/imx_snvs.c @@ -0,0 +1,53 @@ +#include +#include +#include +#include +#include "arch/arm/smcall.h" + +#define SMC_ENTITY_SNVS_RTC 53 +#define SMC_SNVS_PROBE SMC_FASTCALL_NR(SMC_ENTITY_SNVS_RTC, 0) +#define SMC_SNVS_REGS_OP SMC_FASTCALL_NR(SMC_ENTITY_SNVS_RTC, 1) +#define SMC_SNVS_LPCR_OP SMC_FASTCALL_NR(SMC_ENTITY_SNVS_RTC, 2) + +#define OPT_READ 0x1 +#define OPT_WRITE 0x2 + +static struct trusty_ipc_dev *_dev = NULL; + +uint32_t trusty_snvs_read(uint32_t target) { + if (!_dev) { + trusty_error("trusty imx snvs driver is not initialized!\n"); + return 0; + } + return trusty_simple_fast_call32(SMC_SNVS_REGS_OP, target, OPT_READ, 0); +} + +void trusty_snvs_write(uint32_t target, uint32_t value) { + if (!_dev) { + trusty_error("trusty imx snvs driver is not initialized!\n"); + return; + } + trusty_simple_fast_call32(SMC_SNVS_REGS_OP, target, OPT_WRITE, value); +} + +void trusty_snvs_update_lpcr(uint32_t target, uint32_t enable) { + if (!_dev) { + trusty_error("trusty imx snvs driver is not initialized!\n"); + return; + } + trusty_simple_fast_call32(SMC_SNVS_LPCR_OP, target, enable, 0); +} + +int imx_snvs_init(struct trusty_ipc_dev *dev) +{ + trusty_assert(dev); + int error; + error = trusty_simple_fast_call32(SMC_SNVS_PROBE, 0, 0, 0); + if (error < 0) { + trusty_error("trusty imx snvs driver initialize failed! error=%d\n", error); + return error; + } + _dev = dev; + return 0; + +} diff --git a/lib/trusty/ql-tipc/ipc.c b/lib/trusty/ql-tipc/ipc.c new file mode 100644 index 00000000000..d1eb5ef456b --- /dev/null +++ b/lib/trusty/ql-tipc/ipc.c @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include + +#define LOCAL_LOG 0 + +static int sync_ipc_on_connect_complete(struct trusty_ipc_chan *chan) +{ + trusty_assert(chan); + + chan->complete = 1; + return TRUSTY_EVENT_HANDLED; +} + +static int sync_ipc_on_message(struct trusty_ipc_chan *chan) +{ + trusty_assert(chan); + + chan->complete = 1; + return TRUSTY_EVENT_HANDLED; +} + +static int sync_ipc_on_disconnect(struct trusty_ipc_chan *chan) +{ + trusty_assert(chan); + + chan->complete = TRUSTY_ERR_CHANNEL_CLOSED; + return TRUSTY_EVENT_HANDLED; +} + +static int wait_for_complete(struct trusty_ipc_chan *chan) +{ + int rc; + + chan->complete = 0; + for (;;) { + rc = trusty_ipc_poll_for_event(chan->dev); + if (rc < 0) + return rc; + + if (chan->complete) + break; + + if (rc == TRUSTY_EVENT_NONE) + trusty_ipc_dev_idle(chan->dev); + } + + return chan->complete; +} + +static int wait_for_connect(struct trusty_ipc_chan *chan) +{ + trusty_debug("%s: chan %x: waiting for connect\n", __func__, + (int)chan->handle); + return wait_for_complete(chan); +} + +static int wait_for_send(struct trusty_ipc_chan *chan) +{ + trusty_debug("%s: chan %d: waiting for send\n", __func__, chan->handle); + return wait_for_complete(chan); +} + +static int wait_for_reply(struct trusty_ipc_chan *chan) +{ + trusty_debug("%s: chan %d: waiting for reply\n", __func__, chan->handle); + return wait_for_complete(chan); +} + +static struct trusty_ipc_ops sync_ipc_ops = { + .on_connect_complete = sync_ipc_on_connect_complete, + .on_message = sync_ipc_on_message, + .on_disconnect = sync_ipc_on_disconnect, +}; + +void trusty_ipc_chan_init(struct trusty_ipc_chan *chan, + struct trusty_ipc_dev *dev) +{ + trusty_assert(chan); + trusty_assert(dev); + + trusty_memset(chan, 0, sizeof(*chan)); + + chan->handle = INVALID_IPC_HANDLE; + chan->dev = dev; + chan->ops = &sync_ipc_ops; + chan->ops_ctx = chan; +} + +int trusty_ipc_connect(struct trusty_ipc_chan *chan, const char *port, + bool wait) +{ + int rc; + + trusty_assert(chan); + trusty_assert(chan->dev); + trusty_assert(chan->handle == INVALID_IPC_HANDLE); + trusty_assert(port); + + rc = trusty_ipc_dev_connect(chan->dev, port, (uint64_t)(uintptr_t)chan); + if (rc < 0) { + trusty_error("%s: init connection failed (%d)\n", __func__, rc); + return rc; + } + chan->handle = (handle_t)rc; + trusty_debug("chan->handle: %x\n", (int)chan->handle); + + /* got valid channel */ + if (wait) { + rc = wait_for_connect(chan); + if (rc < 0) { + trusty_error("%s: wait for connect failed (%d)\n", __func__, rc); + trusty_ipc_close(chan); + } + } + + return rc; +} + +int trusty_ipc_close(struct trusty_ipc_chan *chan) +{ + int rc; + + trusty_assert(chan); + + rc = trusty_ipc_dev_close(chan->dev, chan->handle); + chan->handle = INVALID_IPC_HANDLE; + + return rc; +} + +int trusty_ipc_send(struct trusty_ipc_chan *chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + bool wait) +{ + int rc; + + trusty_assert(chan); + trusty_assert(chan->dev); + trusty_assert(chan->handle); + +Again: + rc = trusty_ipc_dev_send(chan->dev, chan->handle, iovs, iovs_cnt); + if (rc == TRUSTY_ERR_SEND_BLOCKED) { + if (wait) { + rc = wait_for_send(chan); + if (rc < 0) { + trusty_error("%s: wait to send failed (%d)\n", __func__, rc); + return rc; + } + goto Again; + } + } + return rc; +} + +extern bool proxy_resp_flag; + +int trusty_ipc_recv(struct trusty_ipc_chan *chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + bool wait) +{ + int rc; + trusty_assert(chan); + trusty_assert(chan->dev); + trusty_assert(chan->handle); + + if (wait) { + rc = wait_for_reply(chan); + if (rc < 0) { + trusty_error("%s: wait to reply failed (%d)\n", __func__, rc); + return rc; + } + } + + /* Return directly if the iovs have been received. */ + if (!proxy_resp_flag) { + rc = trusty_ipc_dev_recv(chan->dev, chan->handle, iovs, iovs_cnt); + if (rc < 0) + trusty_error("%s: ipc recv failed (%d)\n", __func__, rc); + } else + rc = 0; + + return rc; +} + +int trusty_ipc_poll_for_event(struct trusty_ipc_dev *ipc_dev) +{ + int rc; + struct trusty_ipc_event evt; + struct trusty_ipc_chan *chan; + + trusty_assert(dev); + + rc = trusty_ipc_dev_get_event(ipc_dev, 0, &evt); + if (rc) { + trusty_error("%s: get event failed (%d)\n", __func__, rc); + return rc; + } + + /* check if we have an event */ + if (!evt.event) { + trusty_debug("%s: no event\n", __func__); + return TRUSTY_EVENT_NONE; + } + + chan = (struct trusty_ipc_chan *)(uintptr_t)evt.cookie; + trusty_assert(chan && chan->ops); + + /* check if we have raw event handler */ + if (chan->ops->on_raw_event) { + /* invoke it first */ + rc = chan->ops->on_raw_event(chan, &evt); + if (rc < 0) { + trusty_error("%s: chan %d: raw event cb returned (%d)\n", __func__, + chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; /* handled */ + } + + if (evt.event & IPC_HANDLE_POLL_ERROR) { + /* something is very wrong */ + trusty_error("%s: chan %d: chan in error state\n", __func__, + chan->handle); + return TRUSTY_ERR_GENERIC; + } + + /* send unblocked should be handled first as it is edge truggered event */ + if (evt.event & IPC_HANDLE_POLL_SEND_UNBLOCKED) { + if (chan->ops->on_send_unblocked) { + rc = chan->ops->on_send_unblocked(chan); + if (rc < 0) { + trusty_error("%s: chan %d: send unblocked cb returned (%d)\n", + __func__, chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; /* handled */ + } + } + + /* check for connection complete */ + if (evt.event & IPC_HANDLE_POLL_READY) { + if (chan->ops->on_connect_complete) { + rc = chan->ops->on_connect_complete(chan); + if (rc < 0) { + trusty_error("%s: chan %d: ready cb returned (%d)\n", __func__, + chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; /* handled */ + } + } + + /* check for incomming messages */ + if (evt.event & IPC_HANDLE_POLL_MSG) { + if (chan->ops->on_message) { + rc = chan->ops->on_message(chan); + if (rc < 0) { + trusty_error("%s: chan %d: msg cb returned (%d)\n", __func__, + chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; + } + } + + /* check for hangups */ + if (evt.event & IPC_HANDLE_POLL_HUP) { + if (chan->ops->on_disconnect) { + rc = chan->ops->on_disconnect(chan); + if (rc < 0) { + trusty_error("%s: chan %d: hup cb returned (%d)\n", __func__, + chan->handle, rc); + return rc; + } + if (rc > 0) + return rc; + } + } + + return TRUSTY_ERR_NONE; +} diff --git a/lib/trusty/ql-tipc/ipc_dev.c b/lib/trusty/ql-tipc/ipc_dev.c new file mode 100644 index 00000000000..720acf22be0 --- /dev/null +++ b/lib/trusty/ql-tipc/ipc_dev.c @@ -0,0 +1,458 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include + +#define NS_PTE_PHYSADDR(pte) ((pte) & 0xFFFFFFFFF000ULL) + +#define QL_TIPC_DEV_RESP 0x8000 +#define QL_TIPC_DEV_CONNECT 0x1 +#define QL_TIPC_DEV_GET_EVENT 0x2 +#define QL_TIPC_DEV_SEND 0x3 +#define QL_TIPC_DEV_RECV 0x4 +#define QL_TIPC_DEV_DISCONNECT 0x5 + +#define LOCAL_LOG 0 + +struct trusty_ipc_cmd_hdr { + uint16_t opcode; + uint16_t flags; + uint32_t status; + uint32_t handle; + uint32_t payload_len; + uint8_t payload[0]; +}; + +struct trusty_ipc_wait_req { + uint64_t reserved; +}; + +struct trusty_ipc_connect_req { + uint64_t cookie; + uint64_t reserved; + uint8_t name[0]; +}; + +static size_t iovec_size(const struct trusty_ipc_iovec *iovs, size_t iovs_cnt) +{ + size_t i; + size_t cb = 0; + + trusty_assert(iovs); + + for (i = 0; i < iovs_cnt; i++) { + cb += iovs[i].len; + } + + return cb; +} + +static size_t iovec_to_buf(void *buf, size_t buf_len, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt) +{ + size_t i; + size_t buf_pos = 0; + + trusty_assert(iovs); + + for (i = 0; i < iovs_cnt; i++) { + size_t to_copy = (size_t)iovs[i].len; + + if (!to_copy) + continue; + + if (to_copy > buf_len) + to_copy = buf_len; + + trusty_memcpy((uint8_t *)buf + buf_pos, iovs[i].base, to_copy); + + buf_pos += to_copy; + buf_len -= to_copy; + + if (buf_len == 0) + break; + } + + return buf_pos; +} + +static size_t buf_to_iovec(const struct trusty_ipc_iovec *iovs, size_t iovs_cnt, + const void *buf, size_t buf_len) +{ + size_t i; + size_t copied = 0; + const uint8_t *buf_ptr = buf; + + trusty_assert(buf_ptr); + trusty_assert(iovs); + + if (iovs_cnt == 0 || buf_len == 0) + return 0; + + for (i = 0; i < iovs_cnt; i++) { + size_t to_copy = buf_len; + + if (to_copy > iovs[i].len) + to_copy = iovs[i].len; + + if (!to_copy) + continue; + + trusty_memcpy(iovs[i].base, buf_ptr, to_copy); + + copied += to_copy; + buf_ptr += to_copy; + buf_len -= to_copy; + + if (buf_len == 0) + break; + } + + return copied; +} + +static int check_response(struct trusty_ipc_dev *dev, + volatile struct trusty_ipc_cmd_hdr *hdr, uint16_t cmd) +{ + if (hdr->opcode != (cmd | QL_TIPC_DEV_RESP)) { + /* malformed response */ + trusty_error("%s: malformed response cmd: 0x%x\n", + __func__, hdr->opcode); + return TRUSTY_ERR_SECOS_ERR; + } + + if (hdr->status) { + /* secure OS responded with error: TODO need error code */ + trusty_error("%s: cmd 0x%x: status = %d\n", + __func__, hdr->opcode, hdr->status); + return TRUSTY_ERR_SECOS_ERR; + } + + return TRUSTY_ERR_NONE; +} + +int trusty_ipc_dev_create(struct trusty_ipc_dev **idev, + struct trusty_dev *tdev, + size_t shared_buf_size) +{ + int rc; + struct trusty_ipc_dev *dev; + + trusty_assert(idev); + trusty_assert(!(shared_buf_size % PAGE_SIZE)); + trusty_debug("%s: Create new Trusty IPC device (%zu)\n", __func__, + shared_buf_size); + + /* allocate device context */ + dev = trusty_calloc(1, sizeof(*dev)); + if (!dev) { + trusty_error("%s: failed to allocate Trusty IPC device\n", __func__); + return TRUSTY_ERR_NO_MEMORY; + } + dev->tdev = tdev; + + /* allocate shared buffer */ + dev->buf_size = shared_buf_size; + dev->buf_vaddr = trusty_alloc_pages(shared_buf_size / PAGE_SIZE); + if (!dev->buf_vaddr) { + trusty_error("%s: failed to allocate shared memory\n", __func__); + rc = TRUSTY_ERR_NO_MEMORY; + goto err_alloc_pages; + } + + /* Get memory attributes */ + rc = trusty_encode_page_info(&dev->buf_ns, dev->buf_vaddr); + if (rc != 0) { + trusty_error("%s: failed to get shared memory attributes\n", __func__); + rc = TRUSTY_ERR_GENERIC; + goto err_page_info; + } + /* call secure OS to register shared buffer */ + rc = trusty_dev_init_ipc(dev->tdev, &dev->buf_ns, dev->buf_size); + if (rc != 0) { + trusty_error("%s: failed (%d) to create Trusty IPC device\n", + __func__, rc); + rc = TRUSTY_ERR_SECOS_ERR; + goto err_create_sec_dev; + } + + trusty_debug("%s: new Trusty IPC device (%p)\n", __func__, dev); + + *idev = dev; + return TRUSTY_ERR_NONE; + +err_page_info: +err_create_sec_dev: + trusty_free_pages(dev->buf_vaddr, dev->buf_size / PAGE_SIZE); +err_alloc_pages: + trusty_free(dev); + return rc; +} + +void trusty_ipc_dev_shutdown(struct trusty_ipc_dev *dev) +{ + int rc; + trusty_assert(dev); + + trusty_debug("%s: shutting down Trusty IPC device (%p)\n", __func__, dev); + + /* shutdown Trusty IPC device */ + rc = trusty_dev_shutdown_ipc(dev->tdev, &dev->buf_ns, dev->buf_size); + trusty_assert(!rc); + if (rc != 0) { + trusty_error("%s: failed (%d) to shutdown Trusty IPC device\n", + __func__, rc); + } + trusty_free_pages(dev->buf_vaddr, dev->buf_size / PAGE_SIZE); + trusty_free(dev); +} + +int trusty_ipc_dev_connect(struct trusty_ipc_dev *dev, const char *port, + uint64_t cookie) +{ + int rc; + size_t port_len; + volatile struct trusty_ipc_cmd_hdr *cmd; + struct trusty_ipc_connect_req *req; + + trusty_assert(dev); + trusty_assert(port); + + trusty_debug("%s: connecting to '%s'\n", __func__, port); + + /* check port name length */ + port_len = trusty_strlen(port) + 1; + if (port_len > (dev->buf_size - sizeof(*cmd) + sizeof(*req))) { + /* it would not fit into buffer */ + trusty_error("%s: port name is too long (%zu)\n", __func__, port_len); + return TRUSTY_ERR_INVALID_ARGS; + } + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_CONNECT; + + /* prepare payload */ + req = (struct trusty_ipc_connect_req *)cmd->payload; + trusty_memset((void *)req, 0, sizeof(*req)); + req->cookie = cookie; + trusty_strcpy((char *)req->name, port); + cmd->payload_len = sizeof(*req) + port_len; + + /* call secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc) { + /* secure OS returned an error */ + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_CONNECT); + if (rc) { + trusty_error("%s: connect cmd failed (%d)\n", __func__, rc); + return rc; + } + + /* success */ + return cmd->handle; +} + +int trusty_ipc_dev_close(struct trusty_ipc_dev *dev, handle_t handle) +{ + int rc; + volatile struct trusty_ipc_cmd_hdr *cmd; + + trusty_assert(dev); + + trusty_debug("%s: chan %d: closing\n", __func__, handle); + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_DISCONNECT; + cmd->handle = handle; + /* no payload */ + + /* call into secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc) { + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_DISCONNECT); + if (rc) { + trusty_error("%s: disconnect cmd failed (%d)\n", __func__, rc); + return rc; + } + + trusty_debug("%s: chan %d: closed\n", __func__, handle); + + return TRUSTY_ERR_NONE; +} + +int trusty_ipc_dev_get_event(struct trusty_ipc_dev *dev, handle_t chan, + struct trusty_ipc_event *event) +{ + int rc; + volatile struct trusty_ipc_cmd_hdr *cmd; + + trusty_assert(dev); + trusty_assert(event); + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_GET_EVENT; + cmd->handle = chan; + + /* prepare payload */ + trusty_memset((void *)cmd->payload, 0, sizeof(struct trusty_ipc_wait_req)); + cmd->payload_len = sizeof(struct trusty_ipc_wait_req); + + /* call into secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc) { + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_GET_EVENT); + if (rc) { + trusty_error("%s: get event cmd failed (%d)\n", __func__, rc); + return rc; + } + + if ((size_t)cmd->payload_len < sizeof(*event)) { + trusty_error("%s: invalid response length (%zd)\n", + __func__, (size_t)cmd->payload_len); + return TRUSTY_ERR_SECOS_ERR; + } + + /* copy out event */ + trusty_memcpy(event, (const void *)cmd->payload, sizeof(*event)); + return TRUSTY_ERR_NONE; +} + +int trusty_ipc_dev_send(struct trusty_ipc_dev *dev, handle_t chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt) +{ + int rc; + size_t msg_size; + volatile struct trusty_ipc_cmd_hdr *cmd; + + trusty_assert(dev); + /* calc message length */ + msg_size = iovec_size(iovs, iovs_cnt); + if (msg_size > dev->buf_size - sizeof(*cmd)) { + /* msg is too big to fit provided buffer */ + trusty_error("%s: chan %d: msg is too long (%zu)\n", __func__, + chan, msg_size); + return TRUSTY_ERR_MSG_TOO_BIG; + } + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_SEND; + cmd->handle = chan; + + /* copy in message data */ + cmd->payload_len = (uint32_t)msg_size; + msg_size = iovec_to_buf(dev->buf_vaddr + sizeof(*cmd), dev->buf_size - sizeof(*cmd), + iovs, iovs_cnt); + trusty_assert(msg_size == (size_t)cmd->payload_len); + + /* call into secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc < 0) { + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_SEND); + if (rc) { + trusty_error("%s: send msg failed (%d)\n", __func__, rc); + } + + return rc; +} + + +int trusty_ipc_dev_recv(struct trusty_ipc_dev *dev, handle_t chan, + const struct trusty_ipc_iovec *iovs, size_t iovs_cnt) +{ + int rc; + size_t copied; + volatile struct trusty_ipc_cmd_hdr *cmd; + + trusty_assert(dev); + + /* prepare command */ + cmd = dev->buf_vaddr; + trusty_memset((void *)cmd, 0, sizeof(*cmd)); + cmd->opcode = QL_TIPC_DEV_RECV; + cmd->handle = chan; + /* no payload */ + + /* call into secure os */ + rc = trusty_dev_exec_ipc(dev->tdev, + &dev->buf_ns, sizeof(*cmd) + cmd->payload_len); + if (rc < 0) { + trusty_error("%s: secure OS returned (%d)\n", __func__, rc); + return TRUSTY_ERR_SECOS_ERR; + } + + rc = check_response(dev, cmd, QL_TIPC_DEV_RECV); + if (rc) { + trusty_error("%s: recv cmd failed (%d)\n", __func__, rc); + return rc; + } + + /* copy data out to proper destination */ + copied = buf_to_iovec(iovs, iovs_cnt, + (const void *)cmd->payload, cmd->payload_len); + if (copied != (size_t)cmd->payload_len) { + /* msg is too big to fit provided buffer */ + trusty_error("%s: chan %d: buffer too small (%zu vs. %zu)\n", + __func__, chan, copied, (size_t)cmd->payload_len); + return TRUSTY_ERR_MSG_TOO_BIG; + } + + return (int)copied; +} + +void trusty_ipc_dev_idle(struct trusty_ipc_dev *dev) +{ + trusty_idle(dev->tdev); +} + diff --git a/lib/trusty/ql-tipc/keymaster.c b/lib/trusty/ql-tipc/keymaster.c new file mode 100644 index 00000000000..90a34e5d2cb --- /dev/null +++ b/lib/trusty/ql-tipc/keymaster.c @@ -0,0 +1,605 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include +#include + +#define LOCAL_LOG 0 + +static struct trusty_ipc_chan km_chan; +static bool initialized = false; +static int trusty_km_version = 2; +static const size_t kMaxCaRequestSize = 10000; +static const size_t kMaxSendSize = 4000; +static const size_t kUuidSize = 32; + +#ifndef MIN +#define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif + +#ifndef NELEMS +#define NELEMS(x) (sizeof(x) / sizeof((x)[0])) +#endif + +static int km_send_request(uint32_t cmd, const void *req, size_t req_len) +{ + struct keymaster_message header = { .cmd = cmd }; + int num_iovecs = req ? 2 : 1; + + struct trusty_ipc_iovec req_iovs[2] = { + { .base = &header, .len = sizeof(header) }, + { .base = (void*)req, .len = req_len }, + }; + + return trusty_ipc_send(&km_chan, req_iovs, num_iovecs, true); +} + +/* Checks that the command opcode in |header| matches |ex-ected_cmd|. Checks + * that |tipc_result| is a valid response size. Returns negative on error. + */ +static int check_response_error(uint32_t expected_cmd, + struct keymaster_message header, + int32_t tipc_result) +{ + if (tipc_result < 0) { + trusty_error("failed (%d) to recv response\n", tipc_result); + return tipc_result; + } + if ((size_t) tipc_result < sizeof(struct keymaster_message)) { + trusty_error("invalid response size (%d)\n", tipc_result); + return TRUSTY_ERR_GENERIC; + } + if ((header.cmd & ~(KEYMASTER_STOP_BIT)) != + (expected_cmd | KEYMASTER_RESP_BIT)) { + trusty_error("malformed response\n"); + return TRUSTY_ERR_GENERIC; + } + return tipc_result; +} + +/* Reads the raw response to |resp| up to a maximum size of |resp_len|. Format + * of each message frame read from the secure side: + * + * command header : 4 bytes + * opaque bytes : MAX(KEYMASTER_MAX_BUFFER_LENGTH, x) bytes + * + * The individual message frames from the secure side are reassembled + * into |resp|, stripping each frame's command header. Returns the number + * of bytes written to |resp| on success, negative on error. + */ +static int km_read_raw_response(uint32_t cmd, void *resp, size_t resp_len) +{ + struct keymaster_message header = { .cmd = cmd }; + int rc = TRUSTY_ERR_GENERIC; + size_t max_resp_len = resp_len; + struct trusty_ipc_iovec resp_iovs[2] = { + { .base = &header, .len = sizeof(header) }, + { .base = resp, .len = MIN(KEYMASTER_MAX_BUFFER_LENGTH, max_resp_len) } + }; + + if (!resp) { + return TRUSTY_ERR_GENERIC; + } + resp_len = 0; + while (true) { + resp_iovs[1].base = (uint8_t*)resp + resp_len; + resp_iovs[1].len = MIN(KEYMASTER_MAX_BUFFER_LENGTH, + (int)max_resp_len - (int)resp_len); + + rc = trusty_ipc_recv(&km_chan, resp_iovs, NELEMS(resp_iovs), true); + rc = check_response_error(cmd, header, rc); + if (rc < 0) { + return rc; + } + resp_len += ((size_t)rc - sizeof(struct keymaster_message)); + if (header.cmd & KEYMASTER_STOP_BIT || resp_len >= max_resp_len) { + break; + } + } + + return resp_len; +} + +/* Reads a Keymaster Response message with a sized buffer. The format + * of the response is as follows: + * + * command header : 4 bytes + * error : 4 bytes + * data length : 4 bytes + * data : |data length| bytes + * + * On success, |error|, |resp_data|, and |resp_data_len| are filled + * successfully. Returns a trusty_err. + */ +static int km_read_data_response(uint32_t cmd, int32_t *error, + uint8_t* resp_data, uint32_t* resp_data_len) +{ + struct keymaster_message header = { .cmd = cmd }; + int rc = TRUSTY_ERR_GENERIC; + size_t max_resp_len = *resp_data_len; + uint32_t resp_data_bytes = 0; + /* On the first read, recv the keymaster_message header, error code, + * response data length, and response data. On subsequent iterations, + * only recv the keymaster_message header and response data. + */ + struct trusty_ipc_iovec resp_iovs[4] = { + { .base = &header, .len = sizeof(header) }, + { .base = error, .len = sizeof(int32_t) }, + { .base = resp_data_len, .len = sizeof(uint32_t) }, + { .base = resp_data, .len = MIN(KEYMASTER_MAX_BUFFER_LENGTH, max_resp_len) } + }; + + rc = trusty_ipc_recv(&km_chan, resp_iovs, NELEMS(resp_iovs), true); + rc = check_response_error(cmd, header, rc); + if (rc < 0) { + return rc; + } + /* resp_data_bytes does not include the error or response data length */ + resp_data_bytes += ((size_t)rc - sizeof(struct keymaster_message) - + 2 * sizeof(uint32_t)); + if (header.cmd & KEYMASTER_STOP_BIT) { + return TRUSTY_ERR_NONE; + } + + /* Read the remaining response data */ + uint8_t* resp_data_start = resp_data + resp_data_bytes; + size_t resp_data_remaining = *resp_data_len - resp_data_bytes; + rc = km_read_raw_response(cmd, resp_data_start, resp_data_remaining); + if (rc < 0) { + return rc; + } + resp_data_bytes += rc; + if (*resp_data_len != resp_data_bytes) { + return TRUSTY_ERR_GENERIC; + } + return TRUSTY_ERR_NONE; +} + +/** + * Convenience method to send a request to the secure side, handle rpmb + * operations, and receive the response. If |resp_data| is not NULL, the + * caller expects an additional data buffer to be returned from the secure + * side. + */ +static int km_do_tipc(uint32_t cmd, void* req, uint32_t req_len, + void* resp_data, uint32_t* resp_data_len) +{ + int rc = TRUSTY_ERR_GENERIC; + struct km_no_response resp_header; + + rc = km_send_request(cmd, req, req_len); + if (rc < 0) { + trusty_error("%s: failed (%d) to send km request\n", __func__, rc); + return rc; + } + + if (!resp_data) { + rc = km_read_raw_response(cmd, &resp_header, sizeof(resp_header)); + } else { + rc = km_read_data_response(cmd, &resp_header.error, resp_data, + resp_data_len); + } + + if (rc < 0) { + trusty_error("%s: failed (%d) to read km response\n", __func__, rc); + return rc; + } + if (resp_header.error != KM_ERROR_OK) { + trusty_error("%s: keymaster returned error (%d)\n", __func__, + resp_header.error); + return TRUSTY_ERR_GENERIC; + } + return TRUSTY_ERR_NONE; +} + +static int32_t MessageVersion(uint8_t major_ver, uint8_t minor_ver, + uint8_t subminor_ver) { + int32_t message_version = -1; + switch (major_ver) { + case 0: + message_version = 0; + break; + case 1: + switch (minor_ver) { + case 0: + message_version = 1; + break; + case 1: + message_version = 2; + break; + } + break; + case 2: + message_version = 3; + break; + } + return message_version; +} + +static int km_get_version(int32_t *version) +{ + int rc = TRUSTY_ERR_GENERIC; + struct km_get_version_resp resp; + + rc = km_send_request(KM_GET_VERSION, NULL, 0); + if (rc < 0) { + trusty_error("failed (%d) to send km version request", rc); + return rc; + } + + rc = km_read_raw_response(KM_GET_VERSION, &resp, sizeof(resp)); + if (rc < 0) { + trusty_error("%s: failed (%d) to read km response\n", __func__, rc); + return rc; + } + + *version = MessageVersion(resp.major_ver, resp.minor_ver, + resp.subminor_ver); + return TRUSTY_ERR_NONE; +} + +int km_tipc_init(struct trusty_ipc_dev *dev) +{ + int rc = TRUSTY_ERR_GENERIC; + + trusty_assert(dev); + + trusty_ipc_chan_init(&km_chan, dev); + trusty_debug("Connecting to Keymaster service\n"); + + /* connect to km service and wait for connect to complete */ + rc = trusty_ipc_connect(&km_chan, KEYMASTER_PORT, true); + if (rc < 0) { + trusty_error("failed (%d) to connect to '%s'\n", rc, KEYMASTER_PORT); + return rc; + } + + int32_t version = -1; + rc = km_get_version(&version); + if (rc < 0) { + trusty_error("failed (%d) to get keymaster version\n", rc); + return rc; + } + if (version < trusty_km_version) { + trusty_error("keymaster version mismatch. Expected %d, received %d\n", + trusty_km_version, version); + return TRUSTY_ERR_GENERIC; + } + + /* mark as initialized */ + initialized = true; + + return TRUSTY_ERR_NONE; +} + +void km_tipc_shutdown(struct trusty_ipc_dev *dev) +{ + if (!initialized) + return; + /* close channel */ + trusty_ipc_close(&km_chan); + + initialized = false; +} + +int trusty_set_boot_params(uint32_t os_version, uint32_t os_patchlevel, + keymaster_verified_boot_t verified_boot_state, + bool device_locked, + const uint8_t *verified_boot_key_hash, + uint32_t verified_boot_key_hash_size, + const uint8_t *verified_boot_hash, + uint32_t verified_boot_hash_size) +{ + if (!initialized) { + trusty_error("Keymaster TIPC client not initialized!\n"); + return -1; + } + struct km_boot_params params = { + .os_version = os_version, + .os_patchlevel = os_patchlevel, + .device_locked = (uint32_t)device_locked, + .verified_boot_state = (uint32_t)verified_boot_state, + .verified_boot_key_hash_size = verified_boot_key_hash_size, + .verified_boot_key_hash = verified_boot_key_hash, + .verified_boot_hash_size = verified_boot_hash_size, + .verified_boot_hash = verified_boot_hash + }; + uint8_t *req = NULL; + uint32_t req_size = 0; + int rc = km_boot_params_serialize(¶ms, &req, &req_size); + + if (rc < 0) { + trusty_error("failed (%d) to serialize request\n", rc); + goto end; + } + rc = km_do_tipc(KM_SET_BOOT_PARAMS, req, req_size, NULL, NULL); + +end: + if (req) { + trusty_free(req); + } + return rc; +} + +static int trusty_send_attestation_data(uint32_t cmd, const uint8_t *data, + uint32_t data_size, + keymaster_algorithm_t algorithm) +{ + struct km_attestation_data attestation_data = { + .algorithm = (uint32_t)algorithm, + .data_size = data_size, + .data = data, + }; + uint8_t *req = NULL; + uint32_t req_size = 0; + int rc = km_attestation_data_serialize(&attestation_data, &req, &req_size); + + if (rc < 0) { + trusty_error("failed (%d) to serialize request\n", rc); + goto end; + } + rc = km_do_tipc(cmd, req, req_size, NULL, NULL); + +end: + if (req) { + trusty_free(req); + } + return rc; +} + +static int trusty_send_raw_buffer(uint32_t cmd, const uint8_t *req_data, + uint32_t req_data_size, uint8_t *resp_data, + uint32_t *resp_data_size) +{ + struct km_raw_buffer buf = { + .data_size = req_data_size, + .data = req_data, + }; + uint8_t *req = NULL; + uint32_t req_size = 0; + int rc = km_raw_buffer_serialize(&buf, &req, &req_size); + if (rc < 0) { + trusty_error("failed (%d) to serialize request\n", rc); + goto end; + } + rc = km_do_tipc(cmd, req, req_size, resp_data, resp_data_size); + +end: + if (req) { + trusty_free(req); + } + return rc; +} + +int trusty_set_attestation_key(const uint8_t *key, uint32_t key_size, + keymaster_algorithm_t algorithm) +{ + if (!initialized) { + trusty_error("Keymaster TIPC client not initialized!\n"); + return -1; + } + return trusty_send_attestation_data(KM_SET_ATTESTATION_KEY, key, key_size, + algorithm); +} + +int trusty_append_attestation_cert_chain(const uint8_t *cert, + uint32_t cert_size, + keymaster_algorithm_t algorithm) +{ + if (!initialized) { + trusty_error("Keymaster TIPC client not initialized!\n"); + return -1; + } + return trusty_send_attestation_data(KM_APPEND_ATTESTATION_CERT_CHAIN, + cert, cert_size, algorithm); +} + +int trusty_set_attestation_key_enc(const uint8_t *key, uint32_t key_size, + keymaster_algorithm_t algorithm) +{ + if (!initialized) { + trusty_error("Keymaster TIPC client not initialized!\n"); + return -1; + } + return trusty_send_attestation_data(KM_SET_ATTESTATION_KEY_ENC, key, key_size, + algorithm); +} + +int trusty_append_attestation_cert_chain_enc(const uint8_t *cert, + uint32_t cert_size, + keymaster_algorithm_t algorithm) +{ + if (!initialized) { + trusty_error("Keymaster TIPC client not initialized!\n"); + return -1; + } + return trusty_send_attestation_data(KM_APPEND_ATTESTATION_CERT_CHAIN_ENC, + cert, cert_size, algorithm); +} + +int trusty_atap_get_ca_request(const uint8_t *operation_start, + uint32_t operation_start_size, + uint8_t **ca_request_p, + uint32_t *ca_request_size_p) +{ + *ca_request_p = trusty_calloc(1, kMaxCaRequestSize); + if (!*ca_request_p) { + return TRUSTY_ERR_NO_MEMORY; + } + *ca_request_size_p = kMaxCaRequestSize; + int rc = trusty_send_raw_buffer(KM_ATAP_GET_CA_REQUEST, operation_start, + operation_start_size, *ca_request_p, + ca_request_size_p); + if (rc != TRUSTY_ERR_NONE) { + trusty_free(*ca_request_p); + } + return rc; +} + +int trusty_atap_set_ca_response(const uint8_t *ca_response, + uint32_t ca_response_size) +{ + struct km_set_ca_response_begin_req begin_req; + int rc = TRUSTY_ERR_GENERIC; + uint32_t bytes_sent = 0, send_size = 0; + + /* Tell the Trusty Keymaster TA the size of CA Response message */ + begin_req.ca_response_size = ca_response_size; + rc = km_do_tipc(KM_ATAP_SET_CA_RESPONSE_BEGIN, &begin_req, + sizeof(begin_req), NULL, NULL); + if (rc != TRUSTY_ERR_NONE) { + return rc; + } + + /* Send the CA Response message in chunks */ + while (bytes_sent < ca_response_size) { + send_size = MIN(kMaxSendSize, ca_response_size - bytes_sent); + rc = trusty_send_raw_buffer(KM_ATAP_SET_CA_RESPONSE_UPDATE, + ca_response + bytes_sent, send_size, + NULL, NULL); + if (rc != TRUSTY_ERR_NONE) { + return rc; + } + bytes_sent += send_size; + } + + /* Tell Trusty Keymaster to parse the CA Response message */ + return km_do_tipc(KM_ATAP_SET_CA_RESPONSE_FINISH, NULL, 0, NULL, NULL); +} + + +int trusty_atap_read_uuid_str(char **uuid_p) +{ + *uuid_p = (char*) trusty_calloc(1, kUuidSize); + + uint32_t response_size = kUuidSize; + int rc = km_do_tipc(KM_ATAP_READ_UUID, NULL, 0, *uuid_p, + &response_size); + if (rc < 0) { + trusty_error("failed to read uuid: %d\n", rc); + trusty_free(*uuid_p); + return rc; + } + if (response_size != kUuidSize) { + trusty_error("keymaster returned wrong uuid size: %d\n", response_size); + trusty_free(*uuid_p); + rc = TRUSTY_ERR_GENERIC; + } + return rc; +} + +int trusty_get_mppubk(uint8_t *mppubk, uint32_t *size) +{ + int rc = TRUSTY_ERR_GENERIC; + struct km_get_mppubk_resp resp; + + if (!initialized) { + trusty_error("Keymaster TIPC client not initialized!\n"); + return -1; + } + + rc = km_send_request(KM_GET_MPPUBK, NULL, 0); + if (rc < 0) { + trusty_error("%s: failed (%d) to send km mppubk request\n", __func__, rc); + return rc; + } + + rc = km_read_raw_response(KM_GET_MPPUBK, &resp, sizeof(resp)); + if (rc < 0) { + trusty_error("%s: failed (%d) to read km mppubk response\n", __func__, rc); + return rc; + } + + if (resp.data_size != 64) { + trusty_error("%s: Wrong mppubk size!\n", __func__); + return TRUSTY_ERR_GENERIC; + } else { + *size = resp.data_size; + } + + memcpy(mppubk, resp.data, resp.data_size); + return TRUSTY_ERR_NONE; +} + +int trusty_verify_secure_unlock(uint8_t *unlock_credential, + uint32_t credential_size, + uint8_t *serial, uint32_t serial_size) +{ + int rc = TRUSTY_ERR_GENERIC; + uint8_t *req = NULL; + uint32_t req_size = 0; + + if (!initialized) { + trusty_error("Keymaster TIPC client not initialized!\n"); + return -1; + } + + struct km_secure_unlock_data secure_unlock_data = { + .serial_size = serial_size, + .serial_data = serial, + .credential_size = credential_size, + .credential_data = unlock_credential, + }; + + rc = km_secure_unlock_data_serialize(&secure_unlock_data, + &req, &req_size); + + if (rc < 0) { + trusty_error("failed (%d) to serialize request\n", rc); + goto end; + } + rc = km_do_tipc(KM_VERIFY_SECURE_UNLOCK, req, req_size, NULL, NULL); + +end: + if (req) { + trusty_free(req); + } + return rc; +} + +int trusty_append_attestation_id(const char *data, uint32_t data_size) +{ + struct km_attestation_id_data attestation_id_data = { + .data_size = data_size, + .data = (uint8_t *)data, + }; + uint8_t *req = NULL; + uint32_t req_size = 0; + int rc = km_attestation_id_data_serialize(&attestation_id_data, &req, &req_size); + + if (rc < 0) { + trusty_error("failed (%d) to serialize request\n", rc); + goto end; + } + rc = km_do_tipc(KM_APPEND_ATTESTATION_ID, req, req_size, NULL, NULL); + +end: + if (req) { + trusty_free(req); + } + return rc; +} diff --git a/lib/trusty/ql-tipc/keymaster_serializable.c b/lib/trusty/ql-tipc/keymaster_serializable.c new file mode 100644 index 00000000000..232a093a9e7 --- /dev/null +++ b/lib/trusty/ql-tipc/keymaster_serializable.c @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include + +uint8_t *append_to_buf(uint8_t *buf, const void *data, size_t data_len) +{ + if (data && data_len) { + trusty_memcpy(buf, data, data_len); + } + return buf + data_len; +} + +uint8_t *append_uint32_to_buf(uint8_t *buf, uint32_t val) +{ + return append_to_buf(buf, &val, sizeof(val)); +} + +uint8_t *append_sized_buf_to_buf(uint8_t *buf, const uint8_t *data, + uint32_t data_len) +{ + buf = append_uint32_to_buf(buf, data_len); + return append_to_buf(buf, data, data_len); +} + +int km_boot_params_serialize(const struct km_boot_params *params, uint8_t** out, + uint32_t *out_size) +{ + uint8_t *tmp; + + if (!out || !params || !out_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + *out_size = (sizeof(params->os_version) + sizeof(params->os_patchlevel) + + sizeof(params->device_locked) + + sizeof(params->verified_boot_state) + + sizeof(params->verified_boot_key_hash_size) + + sizeof(params->verified_boot_hash_size) + + params->verified_boot_key_hash_size + + params->verified_boot_hash_size); + *out = trusty_calloc(*out_size, 1); + if (!*out) { + return TRUSTY_ERR_NO_MEMORY; + } + + tmp = append_uint32_to_buf(*out, params->os_version); + tmp = append_uint32_to_buf(tmp, params->os_patchlevel); + tmp = append_uint32_to_buf(tmp, params->device_locked); + tmp = append_uint32_to_buf(tmp, params->verified_boot_state); + tmp = append_sized_buf_to_buf(tmp, params->verified_boot_key_hash, + params->verified_boot_key_hash_size); + tmp = append_sized_buf_to_buf(tmp, params->verified_boot_hash, + params->verified_boot_hash_size); + + return TRUSTY_ERR_NONE; +} + +int km_attestation_data_serialize(const struct km_attestation_data *data, + uint8_t** out, uint32_t *out_size) +{ + uint8_t *tmp; + + if (!out || !data || !out_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + *out_size = (sizeof(data->algorithm) + sizeof(data->data_size) + + data->data_size); + *out = trusty_calloc(*out_size, 1); + if (!*out) { + return TRUSTY_ERR_NO_MEMORY; + } + + tmp = append_uint32_to_buf(*out, data->algorithm); + tmp = append_sized_buf_to_buf(tmp, data->data, data->data_size); + + return TRUSTY_ERR_NONE; +} + +int km_attestation_id_data_serialize(const struct km_attestation_id_data *data, + uint8_t** out, uint32_t *out_size) +{ + if (!out || !data || !out_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + *out_size = (sizeof(data->data_size) + data->data_size); + *out = trusty_calloc(*out_size, 1); + if (!*out) { + return TRUSTY_ERR_NO_MEMORY; + } + + append_sized_buf_to_buf(*out, data->data, data->data_size); + + return TRUSTY_ERR_NONE; +} + +int km_secure_unlock_data_serialize(const struct km_secure_unlock_data *data, + uint8_t** out, uint32_t *out_size) +{ + uint8_t *tmp; + + if (!out || !data || !out_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + *out_size = (sizeof(data->serial_size) + sizeof(data->credential_size) + + data->serial_size + data->credential_size); + *out = trusty_calloc(*out_size, 1); + if (!*out) { + return TRUSTY_ERR_NO_MEMORY; + } + + tmp = append_sized_buf_to_buf(*out, data->serial_data, data->serial_size); + tmp = append_sized_buf_to_buf(tmp, data->credential_data, data->credential_size); + + return TRUSTY_ERR_NONE; +} + +int km_raw_buffer_serialize(const struct km_raw_buffer *buf, uint8_t** out, + uint32_t *out_size) +{ + if (!out || !buf || !out_size) { + return TRUSTY_ERR_INVALID_ARGS; + } + *out_size = sizeof(buf->data_size) + buf->data_size; + *out = trusty_calloc(*out_size, 1); + if (!*out) { + return TRUSTY_ERR_NO_MEMORY; + } + append_sized_buf_to_buf(*out, buf->data, buf->data_size); + + return TRUSTY_ERR_NONE; +} diff --git a/lib/trusty/ql-tipc/libtipc.c b/lib/trusty/ql-tipc/libtipc.c new file mode 100644 index 00000000000..d21b364c73a --- /dev/null +++ b/lib/trusty/ql-tipc/libtipc.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * Copyright NXP 2018 + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOCAL_LOG 0 + +typedef uintptr_t vaddr_t; + +static struct trusty_ipc_dev *_ipc_dev; +static struct trusty_dev _tdev; /* There should only be one trusty device */ +static void *rpmb_ctx; +#ifndef CONFIG_AVB_ATX +bool rpmbkey_is_set(void); +#endif + +void rpmb_storage_put_ctx(void *dev); +void trusty_ipc_shutdown(void) +{ + /** + * Trusty OS is not well initialized when the rpmb + * key is not set, skip ipc shut down to avoid panic. + */ + if (!rpmbkey_is_set()) { + return; + } + + (void)rpmb_storage_proxy_shutdown(_ipc_dev); + (void)rpmb_storage_put_ctx(rpmb_ctx); + + (void)avb_tipc_shutdown(_ipc_dev); + (void)km_tipc_shutdown(_ipc_dev); + +#ifndef CONFIG_AVB_ATX + (void)hwcrypto_tipc_shutdown(_ipc_dev); +#endif + + /* shutdown Trusty IPC device */ + (void)trusty_ipc_dev_shutdown(_ipc_dev); + + /* shutdown Trusty device */ + (void)trusty_dev_shutdown(&_tdev); +} + +int trusty_ipc_init(void) +{ + int rc; + bool use_keystore = true; + /* init Trusty device */ + trusty_info("Initializing Trusty device\n"); + rc = trusty_dev_init(&_tdev, NULL); + if (rc != 0) { + trusty_error("Initializing Trusty device failed (%d)\n", rc); + return rc; + } + + /* create Trusty IPC device */ + trusty_info("Initializing Trusty IPC device\n"); + rc = trusty_ipc_dev_create(&_ipc_dev, &_tdev, PAGE_SIZE); + if (rc != 0) { + trusty_error("Initializing Trusty IPC device failed (%d)\n", rc); + return rc; + } + + /* get storage rpmb */ + rpmb_ctx = rpmb_storage_get_ctx(); + + /* start secure storage proxy service */ + trusty_info("Initializing RPMB storage proxy service\n"); + rc = rpmb_storage_proxy_init(_ipc_dev, rpmb_ctx); + if (rc != 0) { + trusty_error("Initlializing RPMB storage proxy service failed (%d)\n", rc); +#ifndef CONFIG_AVB_ATX + /* check if rpmb key has been fused. */ + if(rpmbkey_is_set()) { + /* Go to hang if the key has been destroyed. */ + trusty_error("RPMB key was destroyed!\n"); + hang(); + } +#else + return rc; +#endif + } + + /** + * The proxy service can return success even the storage initialization + * failed (when the rpmb key not set). Init the avb and keymaster service + * only when the rpmb key has been set. + */ + if (rpmbkey_is_set()) { + rc = avb_tipc_init(_ipc_dev); + if (rc != 0) { + trusty_error("Initlializing Trusty AVB client failed (%d)\n", rc); + return rc; + } + + trusty_info("Initializing Trusty Keymaster client\n"); + rc = km_tipc_init(_ipc_dev); + if (rc != 0) { + trusty_error("Initlializing Trusty Keymaster client failed (%d)\n", rc); + return rc; + } + } else + use_keystore = false; + +#ifndef CONFIG_AVB_ATX + trusty_info("Initializing Trusty Hardware Crypto client\n"); + rc = hwcrypto_tipc_init(_ipc_dev); + if (rc != 0) { + trusty_error("Initlializing Trusty hwcrypto client failed (%d)\n", rc); + return rc; + } +#endif + +#ifdef CONFIG_IMX8M + trusty_info("Initializing Trusty SNVS driver\n"); + rc = imx_snvs_init(_ipc_dev); + if (rc != 0) { + trusty_error("Initlializing Trusty SNVS driver failed (%d)\n", rc); + return rc; + } +#endif + + /* secure storage service init ok, use trusty backed keystore */ + if (use_keystore) + env_set("keystore", "trusty"); + + return TRUSTY_ERR_NONE; +} diff --git a/lib/trusty/ql-tipc/rpmb_proxy.c b/lib/trusty/ql-tipc/rpmb_proxy.c new file mode 100644 index 00000000000..74ce4b32e87 --- /dev/null +++ b/lib/trusty/ql-tipc/rpmb_proxy.c @@ -0,0 +1,470 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include +#include + +#define LOCAL_LOG 0 + +static bool initialized; +/* Address of rpmb device */ +static void *proxy_rpmb; +struct trusty_ipc_chan proxy_chan; + +struct storage_msg req_msg; +static uint8_t req_buf[4096]; +static uint8_t read_buf[4096]; +bool proxy_resp_flag = false; +static int req_len = 0; + +/* + * Read RPMB request from storage service. Writes message to @msg + * and @req. + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @req: address of storage message request + * @req_len: length of req in bytes + */ +static int proxy_read_request(struct trusty_ipc_chan *chan, + struct storage_msg *msg, void *req, + size_t req_len) +{ + int rc; + + struct trusty_ipc_iovec req_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = req, .len = req_len }, + }; + rc = trusty_ipc_recv(chan, req_iovs, 2, false); + if (rc < 0) { + /* recv message failed */ + trusty_error("%s: failed (%d) to recv request\n", __func__, rc); + return rc; + } + + if ((size_t)rc < sizeof(*msg)) { + /* malformed message */ + trusty_error("%s: malformed request (%zu)\n", __func__, (size_t)rc); + return TRUSTY_ERR_GENERIC; + } + + return rc - sizeof(*msg); /* return payload size */ +} + +/* + * Read RPMB response from storage service. Writes message to @msg + * and @req. + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @cmd: cmd corresponding to the request + * @resp: address of storage message response + * @resp_len: length of resp in bytes + */ +static int proxy_read_response(struct trusty_ipc_chan *chan, struct storage_msg *msg, + uint32_t cmd, void *resp, size_t resp_len) +{ + int rc; + + struct trusty_ipc_iovec resp_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = resp, .len = resp_len }, + }; + rc = trusty_ipc_recv(chan, resp_iovs, resp ? 2 : 1, true); + if (rc < 0) { + /* recv message failed */ + trusty_error("%s: failed (%d) to recv response\n", __func__, rc); + return rc; + } + if (proxy_resp_flag) { + memcpy(msg, &req_msg, sizeof(struct storage_msg)); + if (resp) + memcpy(resp, req_buf, req_len); + rc = req_len + sizeof(struct storage_msg); + proxy_resp_flag = false; + } + + if ((size_t)rc < sizeof(*msg)) { + /* malformed message */ + trusty_error("%s: malformed request (%zu)\n", __func__, (size_t)rc); + return TRUSTY_ERR_GENERIC; + } + + if (msg->cmd != (cmd | STORAGE_RESP_BIT)) { + trusty_error("malformed response, cmd: 0x%x\n", msg->cmd); + return TRUSTY_ERR_GENERIC; + } + + return rc - sizeof(*msg); /* return payload size */ +} + +/* + * Send RPMB response to storage service + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @resp: address of storage message response + * @resp_len: length of resp in bytes + */ +static int proxy_send_response(struct trusty_ipc_chan *chan, + struct storage_msg *msg, void *resp, + size_t resp_len) +{ + struct trusty_ipc_iovec resp_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = resp, .len = resp_len } + }; + + msg->cmd |= STORAGE_RESP_BIT; + return trusty_ipc_send(chan, resp_iovs, resp ? 2 : 1, false); +} + +/* + * Send RPMB request to storage service + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @req: address of storage message request + * @req_len: length of request in bytes + */ +static int proxy_send_request(struct trusty_ipc_chan *chan, + struct storage_msg *msg, void *req, + size_t req_len) +{ + struct trusty_ipc_iovec req_iovs[2] = { + { .base = msg, .len = sizeof(*msg) }, + { .base = req, .len = req_len } + }; + + return trusty_ipc_send(chan, req_iovs, req ? 2 : 1, false); +} + +/* + * Convenience function to send a request to the storage service and read the + * response. + * + * @cmd: the command + * @req: the request buffer + * @req_size: size of the request buffer + * @resp: the response buffer + * @resp_size_p: pointer to the size of the response buffer. changed to the + actual size of the response read from the secure side + */ +static int storage_do_tipc(uint32_t cmd, void *req, uint32_t req_size, void *resp, + uint32_t *resp_size_p) +{ + int rc; + struct storage_msg msg = { .cmd = cmd }; + + if (!initialized) { + trusty_error("%s: Secure storage TIPC client not initialized\n", __func__); + return TRUSTY_ERR_GENERIC; + } + rc = proxy_send_request(&proxy_chan, &msg, req, req_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to send storage request\n", __func__, rc); + return rc; + } + + uint32_t resp_size = resp_size_p ? *resp_size_p : 0; + rc = proxy_read_response(&proxy_chan, &msg, cmd, resp, resp_size); + if (rc < 0) { + trusty_error("%s: failed (%d) to read secure storage response\n", __func__, rc); + return rc; + } + /* change response size to actual response size */ + if (resp_size_p && rc != *resp_size_p) { + *resp_size_p = rc; + } + if (msg.result != STORAGE_NO_ERROR) { + trusty_error("%s: secure storage service returned error (%d)\n", __func__, + msg.result); + return TRUSTY_ERR_GENERIC; + } + return TRUSTY_ERR_NONE; +} + +/* + * Executes the RPMB request at @r, sends response to storage service. + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @r: address of storage message request + * @req_len: length of resp in bytes + */ +static int proxy_handle_rpmb(struct trusty_ipc_chan *chan, + struct storage_msg *msg, const void *r, + size_t req_len) +{ + int rc; + size_t exp_len; + const void *write_data = NULL; + const void *rel_write_data = NULL; + const struct storage_rpmb_send_req *req = r; + + if (req_len < sizeof(req)) { + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + + exp_len = sizeof(*req) + req->reliable_write_size + req->write_size; + if (req_len != exp_len) { + trusty_error( + "%s: malformed rpmb request: invalid length (%zu != %zu)\n", + __func__, req_len, exp_len); + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + + if (req->reliable_write_size) { + if ((req->reliable_write_size % MMC_BLOCK_SIZE) != 0) { + trusty_error("%s: invalid reliable write size %u\n", __func__, + req->reliable_write_size); + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + rel_write_data = req->payload; + } + + if (req->write_size) { + if ((req->write_size % MMC_BLOCK_SIZE) != 0) { + trusty_error("%s: invalid write size %u\n", __func__, + req->write_size); + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + write_data = req->payload + req->reliable_write_size; + } + + if (req->read_size) { + if (req->read_size % MMC_BLOCK_SIZE != 0 || + req->read_size > sizeof(read_buf)) { + trusty_error("%s: invalid read size %u\n", __func__, + req->read_size); + msg->result = STORAGE_ERR_NOT_VALID; + goto err_response; + } + } + + /* execute rpmb command */ + rc = rpmb_storage_send(proxy_rpmb, + rel_write_data, req->reliable_write_size, + write_data, req->write_size, + read_buf, req->read_size); + if (rc) { + trusty_error("%s: rpmb_storage_send failed: %d\n", __func__, rc); + msg->result = STORAGE_ERR_GENERIC; + goto err_response; + } + + if (msg->flags & STORAGE_MSG_FLAG_POST_COMMIT) { + /* + * Nothing todo for post msg commit request as MMC_IOC_MULTI_CMD + * is fully synchronous in this implementation. + */ + } + + msg->result = STORAGE_NO_ERROR; + return proxy_send_response(chan, msg, read_buf, req->read_size); + +err_response: + return proxy_send_response(chan, msg, NULL, 0); +} + +/* + * Handles storage request. + * + * @chan: proxy ipc channel + * @msg: address of storage message header + * @req: address of storage message request + * @req_len: length of resp in bytes + */ +static int proxy_handle_req(struct trusty_ipc_chan *chan, + struct storage_msg *msg, const void *req, + size_t req_len) +{ + int rc; + + if (msg->flags & STORAGE_MSG_FLAG_PRE_COMMIT) { + /* nothing to do */ + } + + switch (msg->cmd) { + case STORAGE_RPMB_SEND: + rc = proxy_handle_rpmb(chan, msg, req, req_len); + break; + + case STORAGE_FILE_DELETE: + case STORAGE_FILE_OPEN: + case STORAGE_FILE_CLOSE: + case STORAGE_FILE_WRITE: + case STORAGE_FILE_READ: + case STORAGE_FILE_GET_SIZE: + case STORAGE_FILE_SET_SIZE: + /* Bulk filesystem is not supported */ + msg->result = STORAGE_ERR_UNIMPLEMENTED; + rc = proxy_send_response(chan, msg, NULL, 0); + break; + + default: + msg->result = STORAGE_ERR_UNIMPLEMENTED; + rc = proxy_send_response(chan, msg, NULL, 0); + } + + return rc; +} + +/* + * Invalidates @chan on hangup event + * + * @chan: proxy ipc channel + */ +static int proxy_on_disconnect(struct trusty_ipc_chan *chan) +{ + trusty_assert(chan); + + trusty_debug("%s: closed by peer\n", __func__); + chan->handle = INVALID_IPC_HANDLE; + return TRUSTY_EVENT_HANDLED; +} + +/* + * Handles received storage message on message event + * + * @chan: proxy ipc channel + */ +static int proxy_on_message(struct trusty_ipc_chan *chan) +{ + int rc; + + trusty_assert(chan); + + /* read request */ + rc = proxy_read_request(chan, &req_msg, req_buf, sizeof(req_buf)); + if (rc < 0) { + trusty_error("%s: failed (%d) to read request\n", __func__, rc); + trusty_ipc_close(chan); + return rc; + } + + /** + * The response of proxy will also be routed to here but we should + * not handle them, just return and set "proxy_resp_flag" to indicate + * func trusty_ipc_dev_recv() not try to receive the msg again. + */ + if (req_msg.cmd & STORAGE_RESP_BIT) { + chan->complete = 1; + proxy_resp_flag = 1; + req_len = rc; + return TRUSTY_EVENT_HANDLED; + } + + /* handle it and send reply */ + rc = proxy_handle_req(chan, &req_msg, req_buf, rc); + if (rc < 0) { + trusty_error("%s: failed (%d) to handle request\n", __func__, rc); + trusty_ipc_close(chan); + return rc; + } + + return TRUSTY_EVENT_HANDLED; +} + +static struct trusty_ipc_ops proxy_ops = { + .on_message = proxy_on_message, + .on_disconnect = proxy_on_disconnect, +}; + +/* + * Initialize RPMB storage proxy + */ +int rpmb_storage_proxy_init(struct trusty_ipc_dev *dev, void *rpmb_dev) +{ + int rc; + + trusty_assert(dev); + trusty_assert(!initialized); + + /* attach rpmb device */ + proxy_rpmb = rpmb_dev; + + /* init ipc channel */ + trusty_ipc_chan_init(&proxy_chan, dev); + + /* connect to proxy service and wait for connect to complete */ + rc = trusty_ipc_connect(&proxy_chan, STORAGE_DISK_PROXY_PORT, true); + if (rc < 0) { + trusty_error("%s: failed (%d) to connect to '%s'\n", __func__, rc, + STORAGE_DISK_PROXY_PORT); + return rc; + } + + /* override default ops */ + proxy_chan.ops = &proxy_ops; + + do { + /* Check for RPMB events */ + rc = trusty_ipc_poll_for_event(proxy_chan.dev); + if (rc < 0) { + trusty_error("%s: failed (%d) to get rpmb event\n", __func__, rc); + return rc; + } + + if (proxy_chan.handle == INVALID_IPC_HANDLE) { + trusty_error("%s: unexpected proxy channel close\n", __func__); + return TRUSTY_ERR_CHANNEL_CLOSED; + } + } + while (rc != TRUSTY_EVENT_NONE); + + /* mark as initialized */ + initialized = true; + + return TRUSTY_ERR_NONE; +} + +void rpmb_storage_proxy_shutdown(struct trusty_ipc_dev *dev) +{ + trusty_assert(initialized); + + /* close channel */ + trusty_ipc_close(&proxy_chan); + + initialized = false; +} + +int storage_set_rpmb_key(void) +{ + uint32_t size = 0; + return storage_do_tipc(STORAGE_RPMB_KEY_SET, NULL, 0, NULL, &size); +} + +int storage_erase_rpmb(void) +{ + uint32_t size = 0; + return storage_do_tipc(STORAGE_RPMB_ERASE_ALL, NULL, 0, NULL, &size); +} diff --git a/lib/trusty/ql-tipc/sysdeps/Makefile b/lib/trusty/ql-tipc/sysdeps/Makefile new file mode 100644 index 00000000000..f9b19d05ccc --- /dev/null +++ b/lib/trusty/ql-tipc/sysdeps/Makefile @@ -0,0 +1,46 @@ +# +# Copyright (C) 2016 The Android Open Source Project +# +# Permission is hereby granted, free of charge, to any person +# obtaining a copy of this software and associated documentation +# files (the "Software"), to deal in the Software without +# restriction, including without limitation the rights to use, copy, +# modify, merge, publish, distribute, sublicense, and/or sell copies +# of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be +# included in all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +# BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +# ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. +# + +# Sample Makefile for U-boot + +#ccflags-y += -DTIPC_ENABLE_DEBUG + +TRUSTY_DIR = lib/trusty +#ccflags-y += -I$(TRUSTY_DIR)/ql-tipc/include +ccflags-y += -I$(TRUSTY_DIR)/interface/include + +QL_TIPC = ../ +obj-y += \ + $(QL_TIPC)/avb.o \ + $(QL_TIPC)/keymaster.o \ + $(QL_TIPC)/ipc.o \ + $(QL_TIPC)/ipc_dev.o \ + $(QL_TIPC)/libtipc.o \ + $(QL_TIPC)/rpmb_proxy.o \ + sysdeps_uboot.o \ + storage_ops_uboot.o + +obj-$(CONFIG_ARM) += \ + $(QL_TIPC)/arch/arm/trusty_mem.o \ + $(QL_TIPC)/arch/arm/trusty_dev.o diff --git a/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c b/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c new file mode 100644 index 00000000000..cf15bf77b03 --- /dev/null +++ b/lib/trusty/ql-tipc/sysdeps/storage_ops_uboot.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include +#include +#include + +#include +#include +#include + +void *rpmb_storage_get_ctx(void) +{ + /* Unused for U-boot */ + return NULL; +} + +void rpmb_storage_put_ctx(void *dev) +{ +} + +int rpmb_storage_send(void *rpmb_dev, const void *rel_write_data, + size_t rel_write_size, const void *write_data, + size_t write_size, void *read_buf, size_t read_size) +{ + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_rel_write_data, rel_write_size); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_write_data, write_size); + ALLOC_CACHE_ALIGN_BUFFER(uint8_t, rpmb_read_data, read_size); + int ret = TRUSTY_ERR_NONE; + struct mmc *mmc = find_mmc_device(mmc_get_env_dev()); + if (!mmc) { + trusty_error("failed to get mmc device.\n"); + return -1; + } + struct blk_desc *desc = mmc_get_blk_desc(mmc); + if (!desc) { + trusty_error("failed to get mmc desc.\n"); + return -1; + } + char original_part = desc->hwpart; + + /* Switch to RPMB partition */ + if (desc->hwpart != MMC_PART_RPMB) { + ret = mmc_switch_part(mmc, MMC_PART_RPMB); + if (ret) { + trusty_error("failed to switch to RPMB partition\n"); + ret = TRUSTY_ERR_GENERIC; + goto end; + } + desc->hwpart = MMC_PART_RPMB; + } + + if (rel_write_size) { + if (rel_write_size % MMC_BLOCK_SIZE) { + trusty_error( + "rel_write_size is not a multiple of MMC_BLOCK_SIZE: %lu\n", + rel_write_size); + ret = TRUSTY_ERR_INVALID_ARGS; + goto end; + } + trusty_memcpy(rpmb_rel_write_data, rel_write_data, rel_write_size); + ret = mmc_rpmb_request(mmc, + (const struct s_rpmb *)rpmb_rel_write_data, + rel_write_size / MMC_BLOCK_SIZE, true); + if (ret) { + trusty_error("failed to execute rpmb reliable write\n"); + goto end; + } + } + if (write_size) { + if (write_size % MMC_BLOCK_SIZE) { + trusty_error("write_size is not a multiple of MMC_BLOCK_SIZE: %lu\n", + write_size); + ret = TRUSTY_ERR_INVALID_ARGS; + goto end; + } + trusty_memcpy(rpmb_write_data, write_data, write_size); + ret = mmc_rpmb_request(mmc, (const struct s_rpmb *)rpmb_write_data, + write_size / MMC_BLOCK_SIZE, false); + if (ret) { + trusty_error("failed to execute rpmb write\n"); + goto end; + } + } + if (read_size) { + if (read_size % MMC_BLOCK_SIZE) { + trusty_error("read_size is not a multiple of MMC_BLOCK_SIZE: %lu\n", + read_size); + ret = TRUSTY_ERR_INVALID_ARGS; + goto end; + } + ret = mmc_rpmb_response(mmc, (struct s_rpmb *)rpmb_read_data, + read_size / MMC_BLOCK_SIZE, 0); + trusty_memcpy((void *)read_buf, rpmb_read_data, read_size); + if (ret < 0) { + trusty_error("failed to execute rpmb read\n"); + } + } + +end: + /* Return to original partition */ + if (desc->hwpart != original_part) { + if (mmc_switch_part(mmc, original_part) != 0) { + trusty_error("failed to switch back to original partition\n"); + return TRUSTY_ERR_GENERIC; + } + desc->hwpart = original_part; + } + return ret; +} diff --git a/lib/trusty/ql-tipc/sysdeps/sysdeps_uboot.c b/lib/trusty/ql-tipc/sysdeps/sysdeps_uboot.c new file mode 100644 index 00000000000..589e9e12ef6 --- /dev/null +++ b/lib/trusty/ql-tipc/sysdeps/sysdeps_uboot.c @@ -0,0 +1,113 @@ +/* + * Copyright (C) 2016 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include + +#include +#include +#include +#include +#include + +extern int trusty_encode_page_info(struct ns_mem_page_info *page_info, + void *vaddr); + +void trusty_lock(struct trusty_dev *dev) +{ +} +void trusty_unlock(struct trusty_dev *dev) +{ +} + +void trusty_local_irq_disable(unsigned long *state) +{ + disable_interrupts(); +} + +void trusty_local_irq_restore(unsigned long *state) +{ + enable_interrupts(); +} + +void trusty_idle(struct trusty_dev *dev) +{ + wfi(); +} + +void trusty_abort(void) +{ + do_reset(NULL, 0, 0, NULL); + __builtin_unreachable(); +} + +void trusty_printf(const char *format, ...) +{ + va_list ap; + + va_start(ap, format); + vprintf(format, ap); + va_end(ap); +} + +void *trusty_memcpy(void *dest, const void *src, size_t n) +{ + return memcpy(dest, src, n); +} + +void *trusty_memset(void *dest, const int c, size_t n) +{ + return memset(dest, c, n); +} + +char *trusty_strcpy(char *dest, const char *src) +{ + return strcpy(dest, src); +} + +size_t trusty_strlen(const char *str) +{ + return strlen(str); +} + +void *trusty_calloc(size_t n, size_t size) +{ + return calloc(n, size); +} + +void trusty_free(void *addr) +{ + if (addr) + free(addr); +} + +void *trusty_alloc_pages(unsigned count) +{ + return memalign(PAGE_SIZE, count * PAGE_SIZE); +} + +void trusty_free_pages(void *va, unsigned count) +{ + if (va) + free(va); +} diff --git a/lib/trusty/ql-tipc/util.c b/lib/trusty/ql-tipc/util.c new file mode 100644 index 00000000000..89ea855ba29 --- /dev/null +++ b/lib/trusty/ql-tipc/util.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, copy, + * modify, merge, publish, distribute, sublicense, and/or sell copies + * of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#include + +const char* trusty_basename(const char* str) { + int64_t n; + size_t len; + + len = trusty_strlen(str); + if (len >= 2) { + for (n = len - 2; n >= 0; n--) { + if (str[n] == '/') { + return str + n + 1; + } + } + } + return str; +} diff --git a/net/fastboot.c b/net/fastboot.c index 7e7a601b9fe..7284efe2110 100644 --- a/net/fastboot.c +++ b/net/fastboot.c @@ -229,6 +229,9 @@ static void fastboot_send(struct fastboot_header header, char *fastboot_data, case FASTBOOT_COMMAND_REBOOT_BOOTLOADER: case FASTBOOT_COMMAND_REBOOT_FASTBOOTD: case FASTBOOT_COMMAND_REBOOT_RECOVERY: +#ifdef CONFIG_ANDROID_RECOVERY + case FASTBOOT_COMMAND_RECOVERY_FASTBOOT: +#endif do_reset(NULL, 0, 0, NULL); break; } diff --git a/net/mdio-uclass.c b/net/mdio-uclass.c index 5da984ca3f1..1b687765b8c 100644 --- a/net/mdio-uclass.c +++ b/net/mdio-uclass.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -137,11 +138,13 @@ static struct phy_device *dm_eth_connect_phy_handle(struct udevice *ethdev, struct udevice *mdiodev; struct phy_device *phy; struct ofnode_phandle_args phandle = {.node = ofnode_null()}; + ofnode phynode; int i; if (CONFIG_IS_ENABLED(PHY_FIXED) && - ofnode_valid(dev_read_subnode(ethdev, "fixed-link"))) { - phy = phy_connect(NULL, -1, ethdev, interface); + ofnode_phy_is_fixed_link(dev_ofnode(ethdev), &phynode)) { + phy = phy_connect(NULL, 0, ethdev, interface); + phandle.node = phynode; goto out; } diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 1fd63efdfd3..8f502fd5d2a 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -99,6 +99,7 @@ endif libs-y += drivers/ libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/dwc3/ libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/cdns3/ +libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/imx/ libs-y += dts/ libs-y += fs/ libs-$(CONFIG_SPL_POST_MEM_SUPPORT) += post/drivers/ diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl index 6ea097d36dd..fbdab757f17 100644 --- a/scripts/Makefile.uncmd_spl +++ b/scripts/Makefile.uncmd_spl @@ -9,6 +9,7 @@ CONFIG_DM_SERIAL= CONFIG_DM_I2C= CONFIG_DM_SPI= CONFIG_DM_SPI_FLASH= +CONFIG_DM_USB= endif endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 43295eec7d4..cb711a01e0b 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -85,6 +85,10 @@ CONFIG_ATMEL_MCI_8BIT CONFIG_ATMEL_SPI0 CONFIG_AT_TRANS CONFIG_AUTO_ZRELADDR +CONFIG_AVB_FUSE +CONFIG_AVB_FUSE_BANK_END +CONFIG_AVB_FUSE_BANK_SIZEW +CONFIG_AVB_FUSE_BANK_START CONFIG_BACKSIDE_L2_CACHE CONFIG_BAT_PAIR CONFIG_BAT_RW @@ -201,6 +205,7 @@ CONFIG_COMMON_ENV_SETTINGS CONFIG_COMMON_ENV_UBI CONFIG_COMPACT_FLASH CONFIG_COMPAT +CONFIG_CONSOLE CONFIG_CONS_EXTC_PINSEL CONFIG_CONS_EXTC_RATE CONFIG_CONS_NONE @@ -351,6 +356,7 @@ CONFIG_DYNAMIC_MMC_DEVNO CONFIG_E1000_NO_NVM CONFIG_E300 CONFIG_E5500 +CONFIG_EARLYCON CONFIG_ECC CONFIG_ECC_INIT_VIA_DDRCONTROLLER CONFIG_ECC_MODE_MASK @@ -380,6 +386,7 @@ CONFIG_EHCI_MXS_PORT0 CONFIG_EHCI_MXS_PORT1 CONFIG_EMU CONFIG_ENABLE_36BIT_PHYS +CONFIG_ENABLE_LOCKSTATUS_SUPPORT CONFIG_ENABLE_MMU CONFIG_ENABLE_MUST_CHECK CONFIG_ENV_ADDR_FLEX @@ -1022,6 +1029,7 @@ CONFIG_MEM_HOLE_16M CONFIG_MEM_INIT_VALUE CONFIG_MEM_REMAP CONFIG_MFG_ENV_SETTINGS +CONFIG_MFG_ENV_SETTINGS_DEFAULT CONFIG_MIIM_ADDRESS CONFIG_MII_DEFAULT_TSEC CONFIG_MII_INIT @@ -1099,6 +1107,10 @@ CONFIG_MX6DL_LPDDR2 CONFIG_MX6DQ_LPDDR2 CONFIG_MXC_EPDC CONFIG_MXC_GPT_HCLK +CONFIG_MXC_KEYMAPPING +CONFIG_MXC_KPD +CONFIG_MXC_KPD_COLMAX +CONFIG_MXC_KPD_ROWMAX CONFIG_MXC_MCI_REGS_BASE CONFIG_MXC_NAND_HWECC CONFIG_MXC_NAND_IP_REGS_BASE @@ -1273,6 +1285,7 @@ CONFIG_POWER_FSL CONFIG_POWER_FSL_MC13892 CONFIG_POWER_HI6553 CONFIG_POWER_I2C +CONFIG_POWER_KEY CONFIG_POWER_LTC3676 CONFIG_POWER_LTC3676_I2C_ADDR CONFIG_POWER_MAX77696 @@ -1471,6 +1484,7 @@ CONFIG_SIEMENS_MACH_TYPE CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY +CONFIG_SKIP_RESOURCE_CHECKING CONFIG_SKIP_TRUNOFF_WATCHDOG CONFIG_SLIC CONFIG_SLTTMR @@ -1684,6 +1698,7 @@ CONFIG_SYS_ATMEL_TOTALSECT CONFIG_SYS_AUTOLOAD CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION CONFIG_SYS_AUXCORE_BOOTDATA +CONFIG_SYS_AUXCORE_FASTUP CONFIG_SYS_BARGSIZE CONFIG_SYS_BAUDRATE_TABLE CONFIG_SYS_BCSR @@ -3620,6 +3635,7 @@ CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SPL_LEN CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_SPL_MALLOC_START +CONFIG_SYS_SPL_PTE_RAM_BASE CONFIG_SYS_SPR CONFIG_SYS_SRIO CONFIG_SYS_SRIO1_MEM_BASE @@ -3944,16 +3960,21 @@ CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP CONFIG_VIDEO_BCM2835 CONFIG_VIDEO_BMP_LOGO CONFIG_VIDEO_CORALP +CONFIG_VIDEO_CSI CONFIG_VIDEO_DA8XX CONFIG_VIDEO_FONT_4X6 +CONFIG_VIDEO_GIS CONFIG_VIDEO_LCD_I2C_BUS CONFIG_VIDEO_LOGO CONFIG_VIDEO_MXS CONFIG_VIDEO_MXS_MODE_SYSTEM +CONFIG_VIDEO_PXP CONFIG_VIDEO_STD_TIMINGS +CONFIG_VIDEO_VADC CONFIG_VID_FLS_ENV CONFIG_VM86 CONFIG_VOIPAC_LCD +CONFIG_VOL_DOWN_KEY CONFIG_VOL_MONITOR_INA220 CONFIG_VOL_MONITOR_IR36021_READ CONFIG_VOL_MONITOR_IR36021_SET diff --git a/test/dm/Makefile b/test/dm/Makefile index fd1455109d4..d0d46e7f7e7 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK) += clk.o clk_ccf.o obj-$(CONFIG_CROS_EC) += cros_ec.o obj-$(CONFIG_DEVRES) += devres.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi_host.o +obj-$(CONFIG_DM_DSA) += dsa.o obj-$(CONFIG_DM_ETH) += eth.o obj-$(CONFIG_FIRMWARE) += firmware.o obj-$(CONFIG_DM_GPIO) += gpio.o @@ -89,6 +90,7 @@ obj-$(CONFIG_DM_MDIO) += mdio.o obj-$(CONFIG_DM_MDIO_MUX) += mdio_mux.o obj-$(CONFIG_DM_RNG) += rng.o obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o +obj-$(CONFIG_SIMPLE_BUS) += simple-bus.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o obj-$(CONFIG_SCMI_FIRMWARE) += scmi.o diff --git a/test/dm/dsa.c b/test/dm/dsa.c new file mode 100644 index 00000000000..18c1776460d --- /dev/null +++ b/test/dm/dsa.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP Semiconductors + */ + +#include +#include +#include +#include +#include +#include + +/* This test exercises the major dsa.h API functions, after making sure + * that the DSA ports and the master Eth are correctly probed. + */ +static int dm_test_dsa_probe(struct unit_test_state *uts) +{ + struct udevice *dev_dsa, *dev_port, *dev_master; + struct dsa_pdata *dsa_pdata; + enum uclass_id id; + + id = uclass_get_by_name("dsa"); + ut_assert(id == UCLASS_DSA); + + ut_assertok(uclass_find_device_by_name(UCLASS_DSA, "dsa-test", + &dev_dsa)); + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "dsa-test-eth", + &dev_master)); + ut_assertok(device_probe(dev_master)); + + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "dsa-test@0", + &dev_port)); + ut_assertok(device_probe(dev_port)); + + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "dsa-test@1", + &dev_port)); + ut_assertok(device_probe(dev_port)); + + /* exercise DSA API */ + dsa_pdata = dev_get_uclass_plat(dev_dsa); + ut_assertnonnull(dsa_pdata); + /* includes CPU port */ + ut_assert(dsa_pdata->num_ports == 3); + + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "lan0", + &dev_port)); + ut_assertok(device_probe(dev_port)); + + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "lan1", + &dev_port)); + ut_assertok(device_probe(dev_port)); + + dev_master = dsa_get_master(dev_dsa); + ut_assertnonnull(dev_master); + ut_asserteq_str("dsa-test-eth", dev_master->name); + + return 0; +} + +DM_TEST(dm_test_dsa_probe, UT_TESTF_SCAN_FDT); + +/* This test sends ping requests with the local address through each DSA port + * via the sandbox DSA master Eth. + */ +static int dm_test_dsa(struct unit_test_state *uts) +{ + net_ping_ip = string_to_ip("1.2.3.5"); + + env_set("ethact", "eth2"); + ut_assertok(net_loop(PING)); + + env_set("ethact", "lan0"); + ut_assertok(net_loop(PING)); + env_set("ethact", "lan1"); + ut_assertok(net_loop(PING)); + + env_set("ethact", ""); + + return 0; +} + +DM_TEST(dm_test_dsa, UT_TESTF_SCAN_FDT); diff --git a/test/dm/eth.c b/test/dm/eth.c index fa8a69da701..e4ee6956106 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -53,8 +53,8 @@ static int dm_test_eth_alias(struct unit_test_state *uts) ut_assertok(net_loop(PING)); ut_asserteq_str("eth@10004000", env_get("ethact")); - /* Expected to fail since eth2 is not defined in the device tree */ - env_set("ethact", "eth2"); + /* Expected to fail since eth1 is not defined in the device tree */ + env_set("ethact", "eth1"); ut_assertok(net_loop(PING)); ut_asserteq_str("eth@10002000", env_get("ethact")); @@ -227,7 +227,7 @@ static int _dm_test_net_retry(struct unit_test_state *uts) * the active device should be eth0 */ sandbox_eth_disable_response(1, true); - env_set("ethact", "eth@10004000"); + env_set("ethact", "lan1"); env_set("netretry", "yes"); sandbox_eth_skip_timeout(); ut_assertok(net_loop(PING)); @@ -237,11 +237,11 @@ static int _dm_test_net_retry(struct unit_test_state *uts) * eth1 is disabled and netretry is no, so the ping should fail and the * active device should be eth1 */ - env_set("ethact", "eth@10004000"); + env_set("ethact", "lan1"); env_set("netretry", "no"); sandbox_eth_skip_timeout(); ut_asserteq(-ENONET, net_loop(PING)); - ut_asserteq_str("eth@10004000", env_get("ethact")); + ut_asserteq_str("lan1", env_get("ethact")); return 0; } diff --git a/test/dm/of_extra.c b/test/dm/of_extra.c index b19cd3787d8..ac2d886892d 100644 --- a/test/dm/of_extra.c +++ b/test/dm/of_extra.c @@ -36,3 +36,21 @@ static int dm_test_ofnode_read_fmap_entry(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_ofnode_read_fmap_entry, 0); + +static int dm_test_ofnode_phy_is_fixed_link(struct unit_test_state *uts) +{ + ofnode eth_node, phy_node, node; + + eth_node = ofnode_path("/dsa-test/ports/port@0"); + ut_assert(ofnode_phy_is_fixed_link(eth_node, &phy_node)); + node = ofnode_path("/dsa-test/ports/port@0/fixed-link"); + ut_asserteq_mem(&phy_node, &node, sizeof(ofnode)); + + eth_node = ofnode_path("/dsa-test/ports/port@1"); + ut_assert(ofnode_phy_is_fixed_link(eth_node, &phy_node)); + node = eth_node; + ut_asserteq_mem(&phy_node, &node, sizeof(ofnode)); + + return 0; +} +DM_TEST(dm_test_ofnode_phy_is_fixed_link, 0); diff --git a/test/dm/simple-bus.c b/test/dm/simple-bus.c new file mode 100644 index 00000000000..3530b47fac2 --- /dev/null +++ b/test/dm/simple-bus.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021, Bin Meng + */ + +#include +#include +#include +#include +#include +#include + +static int dm_test_simple_bus(struct unit_test_state *uts) +{ + struct udevice *dev; + struct simple_bus_plat *plat; + + /* locate the dummy device @ translation-test node */ + ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, &dev)); + ut_asserteq_str("dev@0,0", dev->name); + + /* locate the parent node which is a simple-bus */ + ut_assertnonnull(dev = dev_get_parent(dev)); + ut_asserteq_str("translation-test@8000", dev->name); + + ut_assertnonnull(plat = dev_get_uclass_plat(dev)); + ut_asserteq(0, plat->base); + ut_asserteq(0x8000, plat->target); + ut_asserteq(0x1000, plat->size); + + return 0; +} +DM_TEST(dm_test_simple_bus, UT_TESTF_SCAN_FDT | UT_TESTF_FLAT_TREE); diff --git a/test/py/requirements.txt b/test/py/requirements.txt index 926bccad694..48857ad0fb0 100644 --- a/test/py/requirements.txt +++ b/test/py/requirements.txt @@ -9,7 +9,7 @@ more-itertools==7.2.0 packaging==19.2 pbr==5.4.3 pluggy==0.13.0 -py==1.8.0 +py>=1.10.0 pyelftools==0.27 pygit2==1.4.0 pyparsing==2.4.2 @@ -21,4 +21,4 @@ testtools==2.3.0 traceback2==1.4.0 unittest2==1.1.0 wcwidth==0.1.7 -zipp==0.6.0 +zipp==3.19.1 diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config index 053895a2c07..02ba2da1aa4 100644 --- a/tools/env/fw_env.config +++ b/tools/env/fw_env.config @@ -6,33 +6,9 @@ # be the same as the Environment size, which is valid for NOR and SPI-dataflash # Device offset must be prefixed with 0x to be parsed as a hexadecimal value. -# NOR example -# MTD device name Device offset Env. size Flash sector size Number of sectors -/dev/mtd1 0x0000 0x4000 0x4000 -/dev/mtd2 0x0000 0x4000 0x4000 - -# MTD SPI-dataflash example -# MTD device name Device offset Env. size Flash sector size Number of sectors -#/dev/mtd5 0x4200 0x4200 -#/dev/mtd6 0x4200 0x4200 - -# NAND example -#/dev/mtd0 0x4000 0x4000 0x20000 2 - -# On a block device a negative offset is treated as a backwards offset from the -# end of the device/partition, rather than a forwards offset from the start. - -# Block device example -#/dev/mmcblk0 0xc0000 0x20000 -#/dev/mmcblk0 -0x20000 0x20000 - -# VFAT example -#/boot/uboot.env 0x0000 0x4000 - -# UBI volume -#/dev/ubi0_0 0x0 0x1f000 0x1f000 -#/dev/ubi0_1 0x0 0x1f000 0x1f000 - -# UBI volume by name -#/dev/ubi0:env 0x0 0x1f000 0x1f000 -#/dev/ubi0:env-redund 0x0 0x1f000 0x1f000 +# Block devices for CompuLab imx8m-plus +# emmc +/dev/mmcblk2boot0 0x3f0000 0x4000 +#/dev/mmcblk2boot1 0x3f0000 0x4000 +# sd-card; if AltBoot is in use +#/dev/mmcblk1 0x3f0000 0x4000 diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c index 1d193bd437d..8d247ae9100 100644 --- a/tools/env/fw_env_main.c +++ b/tools/env/fw_env_main.c @@ -49,6 +49,8 @@ static struct option long_options[] = { {"noheader", no_argument, NULL, 'n'}, {"lock", required_argument, NULL, 'l'}, {"version", no_argument, NULL, 'v'}, + {"env", no_argument, NULL, 'e'}, + {"viadt", no_argument, NULL, 'E'}, {NULL, 0, NULL, 0} }; @@ -74,6 +76,10 @@ void usage_printenv(void) #endif " -n, --noheader do not repeat variable name in output\n" " -l, --lock lock node, default:/var/lock\n" + " -e, --env print default fw_env.config\n" +#ifdef CONFIG_DT_NODE + " -E, --viadt print environment passed via devicetree\n" +#endif "\n"); } @@ -112,6 +118,61 @@ void usage_env_set(void) "\n"); } + +#if defined(CONFIG_DT_NODE) + +#define GET_PROP_i(NAME) int NAME = read_dt_prop_int( CONFIG_DT_NODE "/" #NAME, NULL ) +#define GET_PROP_s(NAME) char* NAME = NULL; read_dt_prop_int( CONFIG_DT_NODE "/" #NAME , &NAME) +#define CLEAR_s(NAME) if(NAME) free(NAME) + +static int read_dt_prop_int(const char *name, char** str) +{ + FILE *fp; + int retval; + char *buf = NULL; + size_t count = 0; + + fp = fopen(name, "r"); + if(fp == NULL) { + fprintf(stderr, "Can't open property %s %m\n", name); + return -1; + } + + retval = getline(&buf, &count, fp); + fclose(fp); + if(0 < retval) { + if(str) { //extract a string property + *str = buf; + return 0; + } + else { //extract a integer property + retval = strtoul(buf, NULL, 0); + } + } + + CLEAR_s(buf); + + return retval; +} + +int get_config_via_dt(void) +{ + GET_PROP_i(env_size); + GET_PROP_i(env_off); + GET_PROP_s(env_dev); + + if( !env_dev || 0 >= env_size || 0>= env_off) { + fprintf(stderr, "Valid DT node %s not found\n", CONFIG_DT_NODE); + return -1; + } + + printf("%s\t0x%x\t0x%x\n", env_dev, env_off, env_size); + + CLEAR_s(env_dev); + + return 0; +} +#endif static void parse_common_args(int argc, char *argv[]) { int c; @@ -120,7 +181,7 @@ static void parse_common_args(int argc, char *argv[]) env_opts.config_file = CONFIG_FILE; #endif - while ((c = getopt_long(argc, argv, ":a:c:l:h:v", long_options, NULL)) != + while ((c = getopt_long(argc, argv, ":a:c:l:h:veE", long_options, NULL)) != EOF) { switch (c) { #ifdef CONFIG_FILE @@ -139,6 +200,16 @@ static void parse_common_args(int argc, char *argv[]) fprintf(stderr, "Compiled with " U_BOOT_VERSION "\n"); exit(EXIT_SUCCESS); break; + case 'e': + fprintf(stdout, "/dev/mmcblk2boot0 0x%x 0x%x\n", CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE); + fprintf(stdout, "/dev/mmcblk1 0x%x 0x%x\n", CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE); + exit(EXIT_SUCCESS); + break; +#if defined(CONFIG_DT_NODE) + case 'E': + exit(get_config_via_dt()); + break; +#endif default: /* ignore unknown options */ break; diff --git a/tools/env/fw_env_private.h b/tools/env/fw_env_private.h index 86be16dabc6..9c3b7bf50cc 100644 --- a/tools/env/fw_env_private.h +++ b/tools/env/fw_env_private.h @@ -22,6 +22,7 @@ * for notes on configuration. */ #define CONFIG_FILE "/etc/fw_env.config" +#define CONFIG_DT_NODE "/sys/firmware/devicetree/base/fw_env" #ifndef CONFIG_FILE #define HAVE_REDUND /* For systems with 2 env sectors */ diff --git a/tools/logos/freescale.bmp b/tools/logos/freescale.bmp index 1589e8073d1..43e0591c8ea 100644 Binary files a/tools/logos/freescale.bmp and b/tools/logos/freescale.bmp differ